1 | Squashed in a trivial fix for 32-bit hosts: | 1 | This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's |
---|---|---|---|
2 | cleanup patchset (3) one patch fixing an smmuv3 bug... | ||
2 | 3 | ||
3 | --- a/target/arm/mve_helper.c | 4 | v2 changes: fix build failure on aarch64 hosts by moving the |
4 | +++ b/target/arm/mve_helper.c | 5 | gicv3_add_its() and gicv3_foreach_its() functions to |
5 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | 6 | arm_gicv3_its_common.h. |
6 | acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
7 | m[H##ESIZE(e)])); \ | ||
8 | } \ | ||
9 | - acc = int128_add(acc, 1 << 7); \ | ||
10 | + acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
11 | } \ | ||
12 | } \ | ||
13 | mve_advance_vpt(env); \ | ||
14 | 7 | ||
8 | thanks | ||
15 | -- PMM | 9 | -- PMM |
16 | 10 | ||
17 | The following changes since commit 53f306f316549d20c76886903181413d20842423: | ||
18 | 11 | ||
19 | Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100) | 12 | The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f: |
13 | |||
14 | Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging (2022-04-21 18:48:18 -0700) | ||
20 | 15 | ||
21 | are available in the Git repository at: | 16 | are available in the Git repository at: |
22 | 17 | ||
23 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624 | 18 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1 |
24 | 19 | ||
25 | for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee: | 20 | for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce: |
26 | 21 | ||
27 | docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100) | 22 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100) |
28 | 23 | ||
29 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
30 | target-arm queue: | 25 | target-arm queue: |
31 | * Don't require 'virt' board to be compiled in for ACPI GHES code | 26 | * Implement GICv4 emulation |
32 | * docs: Document which architecture extensions we emulate | 27 | * Some cleanup patches in target/arm |
33 | * Fix bugs in M-profile FPCXT_NS accesses | 28 | * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() |
34 | * First slice of MVE patches | ||
35 | * Implement MTE3 | ||
36 | * docs/system: arm: Add nRF boards description | ||
37 | 29 | ||
38 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
39 | Alexandre Iooss (1): | 31 | Peter Maydell (41): |
40 | docs/system: arm: Add nRF boards description | 32 | hw/intc/arm_gicv3_its: Add missing blank line |
33 | hw/intc/arm_gicv3: Sanity-check num-cpu property | ||
34 | hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count | ||
35 | hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers | ||
36 | target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 | ||
37 | hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" | ||
38 | hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 | ||
39 | hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI | ||
40 | hw/intc/arm_gicv3_its: Implement VMAPP | ||
41 | hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE | ||
42 | hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" | ||
43 | hw/intc/arm_gicv3_its: Factor out CTE lookup sequence | ||
44 | hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code | ||
45 | hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() | ||
46 | hw/intc/arm_gicv3: Keep pointers to every connected ITS | ||
47 | hw/intc/arm_gicv3_its: Implement VMOVP | ||
48 | hw/intc/arm_gicv3_its: Implement VSYNC | ||
49 | hw/intc/arm_gicv3_its: Implement INV command properly | ||
50 | hw/intc/arm_gicv3_its: Implement INV for virtual interrupts | ||
51 | hw/intc/arm_gicv3_its: Implement VMOVI | ||
52 | hw/intc/arm_gicv3_its: Implement VINVALL | ||
53 | hw/intc/arm_gicv3: Implement GICv4's new redistributor frame | ||
54 | hw/intc/arm_gicv3: Implement new GICv4 redistributor registers | ||
55 | hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() | ||
56 | hw/intc/arm_gicv3_cpuif: Support vLPIs | ||
57 | hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily | ||
58 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic | ||
59 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic | ||
60 | hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes | ||
61 | hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code | ||
62 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() | ||
63 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() | ||
64 | hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling | ||
65 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() | ||
66 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() | ||
67 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() | ||
68 | hw/intc/arm_gicv3: Update ID and feature registers for GICv4 | ||
69 | hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 | ||
70 | hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() | ||
71 | hw/arm/virt: Abstract out calculation of redistributor region capacity | ||
72 | hw/arm/virt: Support TCG GICv4 | ||
41 | 73 | ||
42 | Peter Collingbourne (1): | 74 | Richard Henderson (19): |
43 | target/arm: Implement MTE3 | 75 | target/arm: Update ISAR fields for ARMv8.8 |
76 | target/arm: Update SCR_EL3 bits to ARMv8.8 | ||
77 | target/arm: Update SCTLR bits to ARMv9.2 | ||
78 | target/arm: Change DisasContext.aarch64 to bool | ||
79 | target/arm: Change CPUArchState.aarch64 to bool | ||
80 | target/arm: Extend store_cpu_offset to take field size | ||
81 | target/arm: Change DisasContext.thumb to bool | ||
82 | target/arm: Change CPUArchState.thumb to bool | ||
83 | target/arm: Remove fpexc32_access | ||
84 | target/arm: Split out set_btype_raw | ||
85 | target/arm: Split out gen_rebuild_hflags | ||
86 | target/arm: Simplify GEN_SHIFT in translate.c | ||
87 | target/arm: Simplify gen_sar | ||
88 | target/arm: Simplify aa32 DISAS_WFI | ||
89 | target/arm: Use tcg_constant in translate-m-nocp.c | ||
90 | target/arm: Use tcg_constant in translate-neon.c | ||
91 | target/arm: Use smin/smax for do_sat_addsub_32 | ||
92 | target/arm: Use tcg_constant in translate-vfp.c | ||
93 | target/arm: Use tcg_constant_i32 in translate.h | ||
44 | 94 | ||
45 | Peter Maydell (55): | 95 | Xiang Chen (1): |
46 | hw/acpi: Provide stub version of acpi_ghes_record_errors() | 96 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() |
47 | hw/acpi: Provide function acpi_ghes_present() | ||
48 | target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors | ||
49 | docs/system/arm: Document which architecture extensions we emulate | ||
50 | target/arm/translate-vfp.c: Whitespace fixes | ||
51 | target/arm: Handle FPU being disabled in FPCXT_NS accesses | ||
52 | target/arm: Don't NOCP fault for FPCXT_NS accesses | ||
53 | target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access | ||
54 | target/arm: Factor FP context update code out into helper function | ||
55 | target/arm: Split vfp_access_check() into A and M versions | ||
56 | target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() | ||
57 | target/arm: Implement MVE VLDR/VSTR (non-widening forms) | ||
58 | target/arm: Implement widening/narrowing MVE VLDR/VSTR insns | ||
59 | target/arm: Implement MVE VCLZ | ||
60 | target/arm: Implement MVE VCLS | ||
61 | target/arm: Implement MVE VREV16, VREV32, VREV64 | ||
62 | target/arm: Implement MVE VMVN (register) | ||
63 | target/arm: Implement MVE VABS | ||
64 | target/arm: Implement MVE VNEG | ||
65 | tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 | ||
66 | target/arm: Implement MVE VDUP | ||
67 | target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR | ||
68 | target/arm: Implement MVE VADD, VSUB, VMUL | ||
69 | target/arm: Implement MVE VMULH | ||
70 | target/arm: Implement MVE VRMULH | ||
71 | target/arm: Implement MVE VMAX, VMIN | ||
72 | target/arm: Implement MVE VABD | ||
73 | target/arm: Implement MVE VHADD, VHSUB | ||
74 | target/arm: Implement MVE VMULL | ||
75 | target/arm: Implement MVE VMLALDAV | ||
76 | target/arm: Implement MVE VMLSLDAV | ||
77 | target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH | ||
78 | target/arm: Implement MVE VADD (scalar) | ||
79 | target/arm: Implement MVE VSUB, VMUL (scalar) | ||
80 | target/arm: Implement MVE VHADD, VHSUB (scalar) | ||
81 | target/arm: Implement MVE VBRSR | ||
82 | target/arm: Implement MVE VPST | ||
83 | target/arm: Implement MVE VQADD and VQSUB | ||
84 | target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) | ||
85 | target/arm: Implement MVE VQDMULL scalar | ||
86 | target/arm: Implement MVE VQDMULH, VQRDMULH (vector) | ||
87 | target/arm: Implement MVE VQADD, VQSUB (vector) | ||
88 | target/arm: Implement MVE VQSHL (vector) | ||
89 | target/arm: Implement MVE VQRSHL | ||
90 | target/arm: Implement MVE VSHL insn | ||
91 | target/arm: Implement MVE VRSHL | ||
92 | target/arm: Implement MVE VQDMLADH and VQRDMLADH | ||
93 | target/arm: Implement MVE VQDMLSDH and VQRDMLSDH | ||
94 | target/arm: Implement MVE VQDMULL (vector) | ||
95 | target/arm: Implement MVE VRHADD | ||
96 | target/arm: Implement MVE VADC, VSBC | ||
97 | target/arm: Implement MVE VCADD | ||
98 | target/arm: Implement MVE VHCADD | ||
99 | target/arm: Implement MVE VADDV | ||
100 | target/arm: Make VMOV scalar <-> gpreg beatwise for MVE | ||
101 | 97 | ||
102 | docs/system/arm/emulation.rst | 103 ++++ | 98 | docs/system/arm/virt.rst | 5 +- |
103 | docs/system/arm/nrf.rst | 51 ++ | 99 | hw/intc/gicv3_internal.h | 213 +++++++- |
104 | docs/system/target-arm.rst | 7 + | 100 | include/hw/arm/virt.h | 19 +- |
105 | include/hw/acpi/ghes.h | 9 + | 101 | include/hw/intc/arm_gicv3_common.h | 13 + |
106 | include/tcg/tcg-op.h | 8 + | 102 | include/hw/intc/arm_gicv3_its_common.h | 19 + |
107 | include/tcg/tcg.h | 1 - | 103 | target/arm/cpu.h | 59 ++- |
108 | target/arm/helper-mve.h | 357 +++++++++++++ | 104 | target/arm/translate-a32.h | 13 +- |
109 | target/arm/helper.h | 2 + | 105 | target/arm/translate.h | 17 +- |
110 | target/arm/internals.h | 11 + | 106 | hw/arm/smmuv3.c | 2 +- |
111 | target/arm/translate-a32.h | 3 + | 107 | hw/arm/virt.c | 102 +++- |
112 | target/arm/translate.h | 10 + | 108 | hw/intc/arm_gicv3_common.c | 54 +- |
113 | target/arm/m-nocp.decode | 24 + | 109 | hw/intc/arm_gicv3_cpuif.c | 195 ++++++-- |
114 | target/arm/mve.decode | 240 +++++++++ | 110 | hw/intc/arm_gicv3_dist.c | 7 +- |
115 | target/arm/vfp.decode | 14 - | 111 | hw/intc/arm_gicv3_its.c | 876 +++++++++++++++++++++++++++------ |
116 | hw/acpi/ghes-stub.c | 22 + | 112 | hw/intc/arm_gicv3_its_kvm.c | 2 + |
117 | hw/acpi/ghes.c | 17 + | 113 | hw/intc/arm_gicv3_kvm.c | 5 + |
118 | target/arm/cpu64.c | 2 +- | 114 | hw/intc/arm_gicv3_redist.c | 480 +++++++++++++++--- |
119 | target/arm/kvm64.c | 6 +- | 115 | linux-user/arm/cpu_loop.c | 2 +- |
120 | target/arm/mte_helper.c | 82 +-- | 116 | target/arm/cpu.c | 16 +- |
121 | target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++ | 117 | target/arm/helper-a64.c | 4 +- |
122 | target/arm/translate-m-nocp.c | 550 +++++++++++++++++++ | 118 | target/arm/helper.c | 19 +- |
123 | target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++ | 119 | target/arm/hvf/hvf.c | 2 +- |
124 | target/arm/translate-vfp.c | 741 +++++++------------------- | 120 | target/arm/m_helper.c | 6 +- |
125 | tcg/tcg-op-gvec.c | 20 +- | 121 | target/arm/op_helper.c | 13 - |
126 | MAINTAINERS | 1 + | 122 | target/arm/translate-a64.c | 50 +- |
127 | hw/acpi/meson.build | 6 +- | 123 | target/arm/translate-m-nocp.c | 12 +- |
128 | target/arm/meson.build | 1 + | 124 | target/arm/translate-neon.c | 21 +- |
129 | 27 files changed, 3578 insertions(+), 629 deletions(-) | 125 | target/arm/translate-sve.c | 9 +- |
130 | create mode 100644 docs/system/arm/emulation.rst | 126 | target/arm/translate-vfp.c | 76 +-- |
131 | create mode 100644 docs/system/arm/nrf.rst | 127 | target/arm/translate.c | 101 ++-- |
132 | create mode 100644 target/arm/helper-mve.h | 128 | hw/intc/trace-events | 18 +- |
133 | create mode 100644 hw/acpi/ghes-stub.c | 129 | 31 files changed, 1890 insertions(+), 540 deletions(-) |
134 | create mode 100644 target/arm/mve_helper.c | ||
135 | diff view generated by jsdifflib |