[PULL v2 00/57] target-arm queue
[PULL v2 00/23] target-arm queue
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Squashed in a trivial fix for 32-bit hosts:
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v1->v2: fix format string nit in ITS patches (%lu used when PRIu64 needed)
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--- a/target/arm/mve_helper.c
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The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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4
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-- PMM
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-1
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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for you to fetch changes up to 925e3b205bb17af52ac06c7bdd9d84b27345a4e9:
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:36:50 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
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* docs: Document which architecture extensions we emulate
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line user-created devices are not plugged into them
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* Fix bugs in M-profile FPCXT_NS accesses
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* Take an exception if PSTATE.IL is set
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* First slice of MVE patches
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* Support an emulated ITS in the virt board
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* Implement MTE3
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* Add support for kudo-bmc board
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* docs/system: arm: Add nRF boards description
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* Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
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* cadence_uart: Fix clock handling issues that prevented
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u-boot from running
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alexandre Iooss (1):
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Bin Meng (6):
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docs/system: arm: Add nRF boards description
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hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase
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hw/char: cadence_uart: Disable transmit when input clock is disabled
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hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
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hw/char: cadence_uart: Convert to memop_with_attrs() ops
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hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()
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hw/char: cadence_uart: Log a guest error when device is unclocked or in reset
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Peter Collingbourne (1):
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Chris Rauer (1):
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target/arm: Implement MTE3
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hw/arm: Add support for kudo-bmc board.
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Peter Maydell (55):
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Marc Zyngier (1):
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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docs/system/arm: Document which architecture extensions we emulate
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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docs/system/arm/emulation.rst | 103 ++++
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Peter Maydell (5):
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docs/system/arm/nrf.rst | 51 ++
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target/arm: Take an exception if PSTATE.IL is set
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docs/system/target-arm.rst | 7 +
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qdev: Support marking individual buses as 'full'
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include/hw/acpi/ghes.h | 9 +
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hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
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include/tcg/tcg-op.h | 8 +
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hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
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include/tcg/tcg.h | 1 -
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hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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Richard Henderson (1):
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target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
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Shashi Mallela (9):
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hw/intc: GICv3 ITS initial framework
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hw/intc: GICv3 ITS register definitions added
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hw/intc: GICv3 ITS command queue framework
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hw/intc: GICv3 ITS Command processing
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hw/intc: GICv3 ITS Feature enablement
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hw/intc: GICv3 redistributor ITS processing
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tests/data/acpi/virt: Add IORT files for ITS
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hw/arm/virt: add ITS support in virt GIC
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tests/data/acpi/virt: Update IORT files for ITS
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docs/system/arm/nuvoton.rst | 1 +
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hw/intc/gicv3_internal.h | 188 ++++-
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include/hw/arm/virt.h | 2 +
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include/hw/intc/arm_gicv3_common.h | 13 +
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include/hw/intc/arm_gicv3_its_common.h | 32 +-
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include/hw/qdev-core.h | 24 +
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target/arm/cpu.h | 1 +
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target/arm/kvm_arm.h | 4 +-
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target/arm/syndrome.h | 5 +
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target/arm/translate.h | 2 +
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hw/arm/mps2-tz.c | 92 ++-
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hw/arm/mps2.c | 12 +-
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hw/arm/npcm7xx_boards.c | 34 +
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hw/arm/virt.c | 29 +-
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hw/char/cadence_uart.c | 61 +-
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hw/intc/arm_gicv3.c | 14 +
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hw/intc/arm_gicv3_common.c | 13 +
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hw/intc/arm_gicv3_cpuif.c | 7 +-
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hw/intc/arm_gicv3_dist.c | 5 +-
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hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++
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hw/intc/arm_gicv3_its_common.c | 7 +-
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hw/intc/arm_gicv3_its_kvm.c | 2 +-
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hw/intc/arm_gicv3_redist.c | 153 +++-
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hw/misc/zynq_slcr.c | 31 +-
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softmmu/qdev-monitor.c | 7 +-
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target/arm/helper-a64.c | 1 +
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target/arm/helper.c | 8 +
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target/arm/kvm.c | 7 +-
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target/arm/translate-a64.c | 255 +++---
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target/arm/translate.c | 21 +
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hw/intc/meson.build | 1 +
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tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes
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tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes
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35 files changed, 2144 insertions(+), 210 deletions(-)
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create mode 100644 hw/intc/arm_gicv3_its.c
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create mode 100644 tests/data/acpi/virt/IORT
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create mode 100644 tests/data/acpi/virt/IORT.memhp
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create mode 100644 tests/data/acpi/virt/IORT.numamem
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create mode 100644 tests/data/acpi/virt/IORT.pxb
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