The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:

Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24 09:31:26 +0100)

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2

for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:

hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24 05:00:13 -0700)

Third RISC-V PR for 6.1 release

- Fix MISA in the DisasContext

- Fix GDB CSR XML generation

- QOMify the SiFive UART

- Add support for the OpenTitan timer

Alistair Francis (4):

target/riscv: Use target_ulong for the DisasContext misa

hw/char/ibex_uart: Make the register layout private

hw/timer: Initial commit of Ibex Timer

hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

Bin Meng (1):

target/riscv: gdbstub: Fix dynamic CSR XML generation

Lukas Jünger (2):

hw/char: Consistent function names for sifive_uart

hw/char: QOMify sifive_uart

From: Bin Meng <bin.meng@windriver.com>

Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")

the CSR predicate() function was changed to return RISCV_EXCP_NONE

instead of 0 for a valid CSR, but it forgot to update the dynamic

CSR XML generation codes in gdbstub.

Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")

Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>

Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com

target/riscv/gdbstub.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c

--- a/target/riscv/gdbstub.c

+++ b/target/riscv/gdbstub.c

@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)

for (i = 0; i < CSR_TABLE_SIZE; i++) {

predicate = csr_ops[i].predicate;

- if (predicate && !predicate(env, i)) {

+ if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {

if (csr_ops[i].name) {

g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);

} else {

From: Lukas Jünger <lukas.juenger@greensocs.com>

This cleans up function names in the SiFive UART model.

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com

hw/char/sifive_uart.c | 46 ++++++++++++++++++++++---------------------

1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c

--- a/hw/char/sifive_uart.c

+++ b/hw/char/sifive_uart.c

@@ -XXX,XX +XXX,XX @@

*/

/* Returns the state of the IP (interrupt pending) register */

-static uint64_t uart_ip(SiFiveUARTState *s)

+static uint64_t sifive_uart_ip(SiFiveUARTState *s)

{

uint64_t ret = 0;

@@ -XXX,XX +XXX,XX @@ static uint64_t uart_ip(SiFiveUARTState *s)

return ret;

-static void update_irq(SiFiveUARTState *s)

+static void sifive_uart_update_irq(SiFiveUARTState *s)

{

int cond = 0;

if ((s->ie & SIFIVE_UART_IE_TXWM) ||

@@ -XXX,XX +XXX,XX @@ static void update_irq(SiFiveUARTState *s)

}

static uint64_t

-uart_read(void *opaque, hwaddr addr, unsigned int size)

+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)

{

SiFiveUARTState *s = opaque;

unsigned char r;

@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)

memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);

s->rx_fifo_len--;

qemu_chr_fe_accept_input(&s->chr);

- update_irq(s);

+ sifive_uart_update_irq(s);

return r;

}

return 0x80000000;

@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)

case SIFIVE_UART_IE:

return s->ie;

case SIFIVE_UART_IP:

- return uart_ip(s);

+ return sifive_uart_ip(s);

case SIFIVE_UART_TXCTRL:

return s->txctrl;

case SIFIVE_UART_RXCTRL:

@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)

}

static void

-uart_write(void *opaque, hwaddr addr,

- uint64_t val64, unsigned int size)

+sifive_uart_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

{

SiFiveUARTState *s = opaque;

uint32_t value = val64;

@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,

switch (addr) {

case SIFIVE_UART_TXFIFO:

qemu_chr_fe_write(&s->chr, &ch, 1);

- update_irq(s);

+ sifive_uart_update_irq(s);

return;

case SIFIVE_UART_IE:

s->ie = val64;

- update_irq(s);

+ sifive_uart_update_irq(s);

return;

case SIFIVE_UART_TXCTRL:

s->txctrl = val64;

@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,

__func__, (int)addr, (int)value);

}

-static const MemoryRegionOps uart_ops = {

- .read = uart_read,

- .write = uart_write,

+static const MemoryRegionOps sifive_uart_ops = {

+ .read = sifive_uart_read,

+ .write = sifive_uart_write,

.endianness = DEVICE_NATIVE_ENDIAN,

.valid = {

.min_access_size = 4,

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {

}

};

-static void uart_rx(void *opaque, const uint8_t *buf, int size)

+static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)

{

SiFiveUARTState *s = opaque;

@@ -XXX,XX +XXX,XX @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)

}

s->rx_fifo[s->rx_fifo_len++] = *buf;

- update_irq(s);

+ sifive_uart_update_irq(s);

}

-static int uart_can_rx(void *opaque)

+static int sifive_uart_can_rx(void *opaque)

{

SiFiveUARTState *s = opaque;

return s->rx_fifo_len < sizeof(s->rx_fifo);

}

-static void uart_event(void *opaque, QEMUChrEvent event)

+static void sifive_uart_event(void *opaque, QEMUChrEvent event)

{

}

-static int uart_be_change(void *opaque)

+static int sifive_uart_be_change(void *opaque)

{

SiFiveUARTState *s = opaque;

- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,

- uart_be_change, s, NULL, true);

+ qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,

+ sifive_uart_event, sifive_uart_be_change, s,

+ NULL, true);

return 0;

}

@@ -XXX,XX +XXX,XX @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,

SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));

s->irq = irq;

qemu_chr_fe_init(&s->chr, chr, &error_abort);

- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,

- uart_be_change, s, NULL, true);

- memory_region_init_io(&s->mmio, NULL, &uart_ops, s,

+ qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,

+ sifive_uart_event, sifive_uart_be_change, s,

+ NULL, true);

+ memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,

TYPE_SIFIVE_UART, SIFIVE_UART_MAX);

memory_region_add_subregion(address_space, base, &s->mmio);

return s;