[PULL v2 00/33] tcg patch queue
[PULL v3 00/28] tcg patch queue
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The following changes since commit 3ccf6cd0e3e1dfd663814640b3b18b55715d7a75:
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v3: One more try to fix macos issues.
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Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210617-pull-request' into staging (2021-06-18 09:54:42 +0100)
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r~
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The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
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Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210619-2
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
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for you to fetch changes up to 1c9638667b7068539dc5783c9428d588b14162ea:
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for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
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util/oslib-win32: Fix fatal assertion in qemu_try_memalign (2021-06-19 14:51:51 -0700)
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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TCI cleanup and re-encoding
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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Fixes for #367 and #390.
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tcg: Cleanups after disallowing 64-on-32
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Move TCGCond to tcg/tcg-cond.h.
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tcg: Introduce constraint for zero register
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Fix for win32 qemu_try_memalign.
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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linux-user: Fix alignment when unmapping excess reservation
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alessandro Di Federico (1):
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Andreas Schwab (1):
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tcg: expose TCGCond manipulation routines
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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Richard Henderson (31):
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Artyom Tarasenko (1):
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tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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tcg: Add tcg_call_flags
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accel/tcg/plugin-gen: Drop inline markers
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plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
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accel/tcg: Add tcg call flags to plugins helpers
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tcg: Store the TCGHelperInfo in the TCGOp for call
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tcg: Add tcg_call_func
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tcg: Build ffi data structures for helpers
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tcg/tci: Improve tcg_target_call_clobber_regs
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tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
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tcg/tci: Use ffi for calls
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tcg/tci: Reserve r13 for a temporary
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tcg/tci: Emit setcond before brcond
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tcg/tci: Remove tci_write_reg
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tcg/tci: Change encoding to uint32_t units
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tcg/tci: Implement goto_ptr
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tcg/tci: Implement movcond
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tcg/tci: Implement andc, orc, eqv, nand, nor
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tcg/tci: Implement extract, sextract
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tcg/tci: Implement clz, ctz, ctpop
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tcg/tci: Implement mulu2, muls2
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tcg/tci: Implement add2, sub2
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tcg/tci: Split out tci_qemu_ld, tci_qemu_st
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Revert "tcg/tci: Use exec/cpu_ldst.h interfaces"
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tcg/tci: Remove the qemu_ld/st_type macros
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tcg/tci: Use {set,clear}_helper_retaddr
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tests/tcg: Increase timeout for TCI
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accel/tcg: Probe the proper permissions for atomic ops
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tcg/sparc: Fix temp_allocate_frame vs sparc stack bias
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tcg: Allocate sufficient storage in temp_allocate_frame
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tcg: Restart when exhausting the stack frame
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Stefan Weil (1):
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Fabiano Rosas (1):
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util/oslib-win32: Fix fatal assertion in qemu_try_memalign
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elfload: Fix alignment when unmapping excess reservation
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configure | 3 +
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Mikael Szreder (2):
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accel/tcg/atomic_template.h | 24 +-
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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accel/tcg/plugin-helpers.h | 5 +-
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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include/exec/helper-head.h | 37 +-
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include/exec/helper-tcg.h | 34 +-
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include/qemu/plugin.h | 1 -
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include/tcg/tcg-cond.h | 101 ++
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include/tcg/tcg-opc.h | 4 +-
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include/tcg/tcg.h | 71 +-
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target/hppa/helper.h | 3 -
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target/i386/ops_sse_header.h | 3 -
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target/m68k/helper.h | 1 -
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target/ppc/helper.h | 3 -
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tcg/tcg-internal.h | 22 +
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tcg/tci/tcg-target-con-set.h | 1 +
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tcg/tci/tcg-target.h | 68 +-
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accel/tcg/cputlb.c | 95 +-
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accel/tcg/plugin-gen.c | 20 +-
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accel/tcg/user-exec.c | 8 +-
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plugins/core.c | 30 +-
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tcg/optimize.c | 3 +-
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tcg/tcg.c | 299 +++--
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tcg/tci.c | 1203 ++++++++++----------
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util/oslib-win32.c | 6 +-
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tcg/sparc/tcg-target.c.inc | 16 +-
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tcg/tci/tcg-target.c.inc | 550 ++++-----
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tcg/meson.build | 8 +-
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tcg/tci/README | 20 +-
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tests/docker/dockerfiles/alpine.docker | 1 +
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tests/docker/dockerfiles/centos8.docker | 1 +
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tests/docker/dockerfiles/debian10.docker | 1 +
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tests/docker/dockerfiles/fedora-i386-cross.docker | 1 +
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tests/docker/dockerfiles/fedora-win32-cross.docker | 1 +
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tests/docker/dockerfiles/fedora-win64-cross.docker | 1 +
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tests/docker/dockerfiles/fedora.docker | 1 +
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tests/docker/dockerfiles/ubuntu.docker | 1 +
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tests/docker/dockerfiles/ubuntu1804.docker | 1 +
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tests/docker/dockerfiles/ubuntu2004.docker | 1 +
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tests/tcg/Makefile.target | 6 +-
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39 files changed, 1453 insertions(+), 1202 deletions(-)
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create mode 100644 include/tcg/tcg-cond.h
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Richard Henderson (23):
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Remove TCG_OVERSIZED_GUEST
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tcg: Drop support for two address registers in gen_ldst
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tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
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tcg/arm: Drop addrhi from prepare_host_addr
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tcg/i386: Drop addrhi from prepare_host_addr
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tcg/mips: Drop addrhi from prepare_host_addr
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tcg/ppc: Drop addrhi from prepare_host_addr
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tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
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plugins: Fix qemu_plugin_read_memory_vaddr parameters
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accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
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target/loongarch: Use VADDR_PRIx for logging pc_next
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target/mips: Use VADDR_PRIx for logging pc_next
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include/exec: Change vaddr to uintptr_t
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include/exec: Use uintptr_t in CPUTLBEntry
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tcg: Introduce the 'z' constraint for a hardware zero register
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tcg/aarch64: Use 'z' constraint
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tcg/loongarch64: Use 'z' constraint
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tcg/mips: Use 'z' constraint
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tcg/riscv: Use 'z' constraint
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tcg/sparc64: Use 'z' constraint
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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include/exec/tlb-common.h | 10 +-
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include/exec/vaddr.h | 16 +-
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include/qemu/atomic.h | 18 +-
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include/tcg/oversized-guest.h | 23 ---
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include/tcg/tcg-opc.h | 28 +--
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include/tcg/tcg.h | 3 +-
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linux-user/aarch64/target_signal.h | 2 +
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linux-user/arm/target_signal.h | 2 +
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linux-user/generic/signal.h | 1 -
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linux-user/i386/target_signal.h | 2 +
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linux-user/m68k/target_signal.h | 1 +
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linux-user/microblaze/target_signal.h | 2 +
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linux-user/ppc/target_signal.h | 2 +
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linux-user/s390x/target_signal.h | 2 +
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linux-user/sh4/target_signal.h | 2 +
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linux-user/x86_64/target_signal.h | 2 +
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linux-user/xtensa/target_signal.h | 2 +
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tcg/aarch64/tcg-target-con-set.h | 12 +-
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tcg/aarch64/tcg-target.h | 2 +
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tcg/loongarch64/tcg-target-con-set.h | 15 +-
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tcg/loongarch64/tcg-target-con-str.h | 1 -
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tcg/loongarch64/tcg-target-has.h | 2 -
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tcg/loongarch64/tcg-target.h | 2 +
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tcg/mips/tcg-target-con-set.h | 26 +--
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tcg/mips/tcg-target-con-str.h | 1 -
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tcg/mips/tcg-target.h | 2 +
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tcg/riscv/tcg-target-con-set.h | 10 +-
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tcg/riscv/tcg-target-con-str.h | 1 -
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tcg/riscv/tcg-target-has.h | 2 -
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tcg/riscv/tcg-target.h | 2 +
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tcg/sparc64/tcg-target-con-set.h | 12 +-
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tcg/sparc64/tcg-target-con-str.h | 1 -
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tcg/sparc64/tcg-target.h | 3 +-
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tcg/tci/tcg-target.h | 1 -
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accel/tcg/cputlb.c | 32 +---
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accel/tcg/tcg-all.c | 9 +-
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linux-user/elfload.c | 4 +-
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plugins/api.c | 2 +-
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target/arm/ptw.c | 34 ----
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target/loongarch/tcg/translate.c | 2 +-
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target/mips/tcg/octeon_translate.c | 4 +-
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target/riscv/cpu_helper.c | 13 +-
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target/sparc/gdbstub.c | 18 +-
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target/sparc/translate.c | 19 +++
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tcg/optimize.c | 21 +--
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tcg/tcg-op-ldst.c | 103 +++--------
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tcg/tcg.c | 97 +++++------
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tcg/tci.c | 119 +++----------
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docs/devel/multi-thread-tcg.rst | 1 -
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docs/devel/tcg-ops.rst | 4 +-
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target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
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target/sparc/insns.decode | 19 ++-
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tcg/aarch64/tcg-target.c.inc | 86 ++++------
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tcg/arm/tcg-target.c.inc | 114 ++++---------
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tcg/i386/tcg-target.c.inc | 190 +++++----------------
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tcg/loongarch64/tcg-target.c.inc | 72 +++-----
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tcg/mips/tcg-target.c.inc | 169 ++++++------------
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tcg/ppc/tcg-target.c.inc | 164 +++++-------------
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tcg/riscv/tcg-target.c.inc | 56 +++---
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tcg/s390x/tcg-target.c.inc | 40 ++---
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tcg/sparc64/tcg-target.c.inc | 45 ++---
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tcg/tci/tcg-target.c.inc | 60 ++-----
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62 files changed, 550 insertions(+), 1162 deletions(-)
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delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL v2 30/33] tcg: Allocate sufficient storage in temp_allocate_frame
[PULL v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
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This function should have been updated for vector types
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DisasContextBase.pc_next has type vaddr; use the correct log format.
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when they were introduced.
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Fixes: d2fd745fe8b
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Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367
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Cc: qemu-stable@nongnu.org
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Tested-by: Stefan Weil <sw@weilnetz.de>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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---
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tcg/tcg.c | 31 ++++++++++++++++++++++++++-----
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target/mips/tcg/octeon_translate.c | 4 ++--
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1 file changed, 26 insertions(+), 5 deletions(-)
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/tcg/tcg.c b/tcg/tcg.c
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diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/tcg/tcg.c
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--- a/target/mips/tcg/octeon_translate.c
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+++ b/tcg/tcg.c
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+++ b/target/mips/tcg/octeon_translate.c
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@@ -XXX,XX +XXX,XX @@ static void check_regs(TCGContext *s)
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@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
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14
TCGv p;
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static void temp_allocate_frame(TCGContext *s, TCGTemp *ts)
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21
{
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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- if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
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- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
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- s->frame_end) {
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- TARGET_FMT_lx "\n", ctx->base.pc_next);
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- tcg_abort();
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+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
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+ intptr_t off, size, align;
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+ ctx->base.pc_next);
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+
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generate_exception_end(ctx, EXCP_RI);
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+ switch (ts->type) {
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return true;
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+ case TCG_TYPE_I32:
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+ size = align = 4;
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+ break;
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+ case TCG_TYPE_I64:
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+ case TCG_TYPE_V64:
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+ size = align = 8;
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+ break;
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+ case TCG_TYPE_V128:
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+ size = align = 16;
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+ break;
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+ case TCG_TYPE_V256:
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+ /* Note that we do not require aligned storage for V256. */
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+ size = 32, align = 16;
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+ break;
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+ default:
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+ g_assert_not_reached();
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}
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}
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- ts->mem_offset = s->current_frame_offset;
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+
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+ assert(align <= TCG_TARGET_STACK_ALIGN);
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+ off = ROUND_UP(s->current_frame_offset, align);
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+ assert(off + size <= s->frame_end);
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+ s->current_frame_offset = off + size;
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+
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+ ts->mem_offset = off;
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#if defined(__sparc__)
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ts->mem_offset += TCG_TARGET_STACK_BIAS;
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#endif
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ts->mem_base = s->frame_temp;
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ts->mem_allocated = 1;
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- s->current_frame_offset += sizeof(tcg_target_long);
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}
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61
static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet);
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--
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--
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2.25.1
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2.43.0
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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