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[PATCH] tests/qtest/nvme-test: add persistent memory region test

Gollu Appalanaidu posted 1 patch 2 years, 10 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210618103431.9951-1-anaidu.gollu@samsung.com
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Keith Busch <kbusch@kernel.org>, Thomas Huth <thuth@redhat.com>, Laurent Vivier <lvivier@redhat.com>, Klaus Jensen <its@irrelevant.dk>
tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 77 insertions(+), 1 deletion(-)
[PATCH] tests/qtest/nvme-test: add persistent memory region test
Posted by Gollu Appalanaidu 2 years, 10 months ago 
This will test the PMR functionality.

Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
---
 tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 77 insertions(+), 1 deletion(-)

diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
index d32c953a38..6d557be6ca 100644
--- a/tests/qtest/nvme-test.c
+++ b/tests/qtest/nvme-test.c
@@ -13,6 +13,7 @@
 #include "libqos/libqtest.h"
 #include "libqos/qgraph.h"
 #include "libqos/pci.h"
+#include "include/block/nvme.h"
 
 typedef struct QNvme QNvme;
 
@@ -21,6 +22,9 @@ struct QNvme {
     QPCIDevice dev;
 };
 
+static char *t_path;
+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
+
 static void *nvme_get_driver(void *obj, const char *interface)
 {
     QNvme *nvme = obj;
@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
     g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
 }
 
+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QNvme *nvme = obj;
+    QPCIDevice *pdev = &nvme->dev;
+    QPCIBar pmr_bar, nvme_bar;
+    uint32_t pmrcap, pmrsts;
+
+    qpci_device_enable(pdev);
+    pmr_bar = qpci_iomap(pdev, 4, NULL);
+
+    /* Without Enabling PMRCTL check bar enablemet */
+    qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
+
+    /* Map NVMe Bar Register to Enable the Mem Region */
+    nvme_bar = qpci_iomap(pdev, 0, NULL);
+
+    pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
+    g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
+    g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
+    g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
+    g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
+    g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
+
+    /* Enable PMRCTRL */
+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
+
+    qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
+
+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
+
+    /* Disable PMRCTRL */
+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
+
+    qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
+
+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
+
+    qpci_iounmap(pdev, nvme_bar);
+    qpci_iounmap(pdev, pmr_bar);
+}
+
 static void nvme_register_nodes(void)
 {
+    int fd, ret;
+    t_path = g_strdup("/tmp/qtest.XXXXXX");
+
+    /* Create a temporary raw image*/
+    fd = mkstemp(t_path);
+    g_assert(fd >= 0);
+    ret = ftruncate(fd, TEST_IMAGE_SIZE);
+    g_assert(ret == 0);
+    close(fd);
+
+    char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
+                                         "share=on,mem-path=%s,size=8", t_path);
+
     QOSGraphEdgeOptions opts = {
         .extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
         .before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
-                           "file.read-zeroes=on,format=raw",
+                           "file.read-zeroes=on,format=raw ",
+                           pmr_cmd_line,
     };
 
     add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
     qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
         .edge.extra_device_opts = "cmb_size_mb=2"
     });
+
+    qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
+                 &(QOSGraphTestOptions) {
+        .edge.extra_device_opts = "pmrdev=pmr0"
+    });
+
+    unlink(t_path);
 }
 
 libqos_init(nvme_register_nodes);
-- 
2.17.1
Re: [PATCH] tests/qtest/nvme-test: add persistent memory region test
Posted by Klaus Jensen 2 years, 10 months ago 
On Jun 18 16:04, Gollu Appalanaidu wrote:
>This will test the PMR functionality.
>
>Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
>---
> tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 77 insertions(+), 1 deletion(-)
>
>diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
>index d32c953a38..6d557be6ca 100644
>--- a/tests/qtest/nvme-test.c
>+++ b/tests/qtest/nvme-test.c
>@@ -13,6 +13,7 @@
> #include "libqos/libqtest.h"
> #include "libqos/qgraph.h"
> #include "libqos/pci.h"
>+#include "include/block/nvme.h"
>
> typedef struct QNvme QNvme;
>
>@@ -21,6 +22,9 @@ struct QNvme {
>     QPCIDevice dev;
> };
>
>+static char *t_path;
>+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
>+
> static void *nvme_get_driver(void *obj, const char *interface)
> {
>     QNvme *nvme = obj;
>@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
>     g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
> }
>
>+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
>+{
>+    QNvme *nvme = obj;
>+    QPCIDevice *pdev = &nvme->dev;
>+    QPCIBar pmr_bar, nvme_bar;
>+    uint32_t pmrcap, pmrsts;
>+
>+    qpci_device_enable(pdev);
>+    pmr_bar = qpci_iomap(pdev, 4, NULL);
>+
>+    /* Without Enabling PMRCTL check bar enablemet */
>+    qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
>+
>+    /* Map NVMe Bar Register to Enable the Mem Region */
>+    nvme_bar = qpci_iomap(pdev, 0, NULL);
>+
>+    pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
>+    g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
>+    g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
>+    g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
>+    g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
>+    g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
>+
>+    /* Enable PMRCTRL */
>+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
>+
>+    qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
>+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
>+
>+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
>+
>+    /* Disable PMRCTRL */
>+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
>+
>+    qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
>+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
>+
>+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
>+
>+    qpci_iounmap(pdev, nvme_bar);
>+    qpci_iounmap(pdev, pmr_bar);
>+}
>+
> static void nvme_register_nodes(void)
> {
>+    int fd, ret;
>+    t_path = g_strdup("/tmp/qtest.XXXXXX");
>+
>+    /* Create a temporary raw image*/
>+    fd = mkstemp(t_path);
>+    g_assert(fd >= 0);
>+    ret = ftruncate(fd, TEST_IMAGE_SIZE);
>+    g_assert(ret == 0);
>+    close(fd);
>+
>+    char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
>+                                         "share=on,mem-path=%s,size=8", t_path);
>+
>     QOSGraphEdgeOptions opts = {
>         .extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
>         .before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
>-                           "file.read-zeroes=on,format=raw",
>+                           "file.read-zeroes=on,format=raw ",
>+                           pmr_cmd_line,
>     };
>
>     add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
>@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
>     qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
>         .edge.extra_device_opts = "cmb_size_mb=2"
>     });
>+
>+    qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
>+                 &(QOSGraphTestOptions) {
>+        .edge.extra_device_opts = "pmrdev=pmr0"
>+    });
>+
>+    unlink(t_path);
> }
>
> libqos_init(nvme_register_nodes);
>-- 
>2.17.1
>

An extra test is always nice and looks fine,

Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Re: [PATCH] tests/qtest/nvme-test: add persistent memory region test
Posted by Klaus Jensen 2 years, 9 months ago 
On Jun 18 16:04, Gollu Appalanaidu wrote:
>This will test the PMR functionality.
>
>Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
>---
> tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 77 insertions(+), 1 deletion(-)
>
>diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
>index d32c953a38..6d557be6ca 100644
>--- a/tests/qtest/nvme-test.c
>+++ b/tests/qtest/nvme-test.c
>@@ -13,6 +13,7 @@
> #include "libqos/libqtest.h"
> #include "libqos/qgraph.h"
> #include "libqos/pci.h"
>+#include "include/block/nvme.h"
>
> typedef struct QNvme QNvme;
>
>@@ -21,6 +22,9 @@ struct QNvme {
>     QPCIDevice dev;
> };
>
>+static char *t_path;
>+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
>+
> static void *nvme_get_driver(void *obj, const char *interface)
> {
>     QNvme *nvme = obj;
>@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
>     g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
> }
>
>+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
>+{
>+    QNvme *nvme = obj;
>+    QPCIDevice *pdev = &nvme->dev;
>+    QPCIBar pmr_bar, nvme_bar;
>+    uint32_t pmrcap, pmrsts;
>+
>+    qpci_device_enable(pdev);
>+    pmr_bar = qpci_iomap(pdev, 4, NULL);
>+
>+    /* Without Enabling PMRCTL check bar enablemet */
>+    qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
>+
>+    /* Map NVMe Bar Register to Enable the Mem Region */
>+    nvme_bar = qpci_iomap(pdev, 0, NULL);
>+
>+    pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
>+    g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
>+    g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
>+    g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
>+    g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
>+    g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
>+
>+    /* Enable PMRCTRL */
>+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
>+
>+    qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
>+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
>+
>+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
>+
>+    /* Disable PMRCTRL */
>+    qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
>+
>+    qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
>+    g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
>+    g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
>+    g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
>+
>+    pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+    g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
>+
>+    qpci_iounmap(pdev, nvme_bar);
>+    qpci_iounmap(pdev, pmr_bar);
>+}
>+
> static void nvme_register_nodes(void)
> {
>+    int fd, ret;
>+    t_path = g_strdup("/tmp/qtest.XXXXXX");
>+
>+    /* Create a temporary raw image*/
>+    fd = mkstemp(t_path);
>+    g_assert(fd >= 0);
>+    ret = ftruncate(fd, TEST_IMAGE_SIZE);
>+    g_assert(ret == 0);
>+    close(fd);
>+
>+    char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
>+                                         "share=on,mem-path=%s,size=8", t_path);
>+
>     QOSGraphEdgeOptions opts = {
>         .extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
>         .before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
>-                           "file.read-zeroes=on,format=raw",
>+                           "file.read-zeroes=on,format=raw ",
>+                           pmr_cmd_line,
>     };
>
>     add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
>@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
>     qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
>         .edge.extra_device_opts = "cmb_size_mb=2"
>     });
>+
>+    qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
>+                 &(QOSGraphTestOptions) {
>+        .edge.extra_device_opts = "pmrdev=pmr0"
>+    });
>+
>+    unlink(t_path);
> }
>
> libqos_init(nvme_register_nodes);
>-- 
>2.17.1
>

Applied to nvme-next. I swapped the memory-backend-file with a 
memory-backend-ram so we don't need to setup an actual file.

Patchew 2.1-devel-0870f84

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