[PULL 00/25] target-arm queue
[PULL 0/1] target-arm queue
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v2: dropped the hw/acpi/ghes-stub.c changes, which produce a
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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weird Meson error ("Tried to extract unknown source ghes-stub.c")
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which didn't happen on my local builds; I'll investigate later...
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-- PMM
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2:
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100)
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
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* fix part of the "TCG-disabled builds are broken" issue
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* handle some UNALLOCATED decode cases correctly rather
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than asserting
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* hw: virt: consider hw_compat_6_0
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* hw/arm: add quanta-gbs-bmc machine
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* hw/intc/armv7m_nvic: Remove stale comment
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* target/arm: Fix mte page crossing test
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* hw/arm: quanta-q71l add pca954x muxes
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* target/arm: First few parts of MVE support
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----------------------------------------------------------------
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----------------------------------------------------------------
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Heinrich Schuchardt (1):
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Philippe Mathieu-Daudé (1):
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hw: virt: consider hw_compat_6_0
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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Jean-Philippe Brucker (1):
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target/arm/gdbstub.c | 5 +++--
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hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
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1 file changed, 3 insertions(+), 2 deletions(-)
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Patrick Venture (5):
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hw/arm: add quanta-gbs-bmc machine
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hw/arm: quanta-gbs-bmc add i2c comments
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hw/arm: gsj add i2c comments
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hw/arm: gsj add pca9548
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hw/arm: quanta-q71l add pca954x muxes
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Peter Maydell (14):
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hw/intc/armv7m_nvic: Remove stale comment
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target/arm: Provide and use H8 and H1_8 macros
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target/arm: Enable FPSCR.QC bit for MVE
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target/arm: Handle VPR semantics in existing code
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target/arm: Add handling for PSR.ECI/ICI
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target/arm: Let vfp_access_check() handle late NOCP checks
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target/arm: Implement MVE LCTP
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target/arm: Implement MVE WLSTP insn
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target/arm: Implement MVE DLSTP
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target/arm: Implement MVE LETP insn
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target/arm: Add framework for MVE decode
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target/arm: Move expand_pred_b() data to vec_helper.c
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bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
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include/qemu/int128.h: Add function to create Int128 from int64_t
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Richard Henderson (4):
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target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
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target/arm: Remove fprintf from disas_simd_mod_imm
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target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
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target/arm: Fix mte page crossing test
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include/qemu/bitops.h | 29 +++
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include/qemu/int128.h | 10 +
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target/arm/translate-a32.h | 2 +
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target/arm/translate.h | 9 +
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target/arm/vec_internal.h | 9 +
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target/arm/mve.decode | 20 ++
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target/arm/t32.decode | 15 +-
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hw/arm/aspeed.c | 11 +-
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hw/arm/npcm7xx_boards.c | 107 ++++++++++-
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hw/arm/virt.c | 2 +
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hw/intc/arm_gicv3_cpuif.c | 5 +-
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hw/intc/armv7m_nvic.c | 6 -
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target/arm/m_helper.c | 54 +++++-
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target/arm/mte_helper.c | 2 +-
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target/arm/sve_helper.c | 381 +++++++++++++-------------------------
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target/arm/translate-a64.c | 87 +++++----
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target/arm/translate-m-nocp.c | 16 +-
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target/arm/translate-mve.c | 29 +++
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target/arm/translate-vfp.c | 65 +++++--
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target/arm/translate.c | 300 ++++++++++++++++++++++++++++--
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target/arm/vec_helper.c | 116 +++++++++++-
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target/arm/vfp_helper.c | 3 +-
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tests/tcg/aarch64/mte-7.c | 31 ++++
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hw/arm/Kconfig | 2 +
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target/arm/meson.build | 2 +
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tests/tcg/aarch64/Makefile.target | 2 +-
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26 files changed, 967 insertions(+), 348 deletions(-)
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create mode 100644 target/arm/mve.decode
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create mode 100644 target/arm/translate-mve.c
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create mode 100644 tests/tcg/aarch64/mte-7.c
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diff view generated by jsdifflib
New patch
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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