[PULL 00/25] target-arm queue
[PULL 0/3] target-arm queue
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v2: dropped the hw/acpi/ghes-stub.c changes, which produce a
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
2
weird Meson error ("Tried to extract unknown source ghes-stub.c")
3
which didn't happen on my local builds; I'll investigate later...
4
2
5
-- PMM
3
-- PMM
6
4
7
The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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6
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100)
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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8
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are available in the Git repository at:
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are available in the Git repository at:
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10
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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12
15
for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2:
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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14
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include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100)
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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16
19
----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
18
target-arm queue:
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* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
19
* Fix KVM SVE ID register probe code
22
* handle some UNALLOCATED decode cases correctly rather
23
than asserting
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* hw: virt: consider hw_compat_6_0
25
* hw/arm: add quanta-gbs-bmc machine
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* hw/intc/armv7m_nvic: Remove stale comment
27
* target/arm: Fix mte page crossing test
28
* hw/arm: quanta-q71l add pca954x muxes
29
* target/arm: First few parts of MVE support
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20
31
----------------------------------------------------------------
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----------------------------------------------------------------
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Heinrich Schuchardt (1):
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Richard Henderson (3):
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hw: virt: consider hw_compat_6_0
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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target/arm: Move sve probe inside kvm >= 4.15 branch
34
26
35
Jean-Philippe Brucker (1):
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
36
hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
28
1 file changed, 22 insertions(+), 23 deletions(-)
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38
Patrick Venture (5):
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hw/arm: add quanta-gbs-bmc machine
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hw/arm: quanta-gbs-bmc add i2c comments
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hw/arm: gsj add i2c comments
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hw/arm: gsj add pca9548
43
hw/arm: quanta-q71l add pca954x muxes
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45
Peter Maydell (14):
46
hw/intc/armv7m_nvic: Remove stale comment
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target/arm: Provide and use H8 and H1_8 macros
48
target/arm: Enable FPSCR.QC bit for MVE
49
target/arm: Handle VPR semantics in existing code
50
target/arm: Add handling for PSR.ECI/ICI
51
target/arm: Let vfp_access_check() handle late NOCP checks
52
target/arm: Implement MVE LCTP
53
target/arm: Implement MVE WLSTP insn
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target/arm: Implement MVE DLSTP
55
target/arm: Implement MVE LETP insn
56
target/arm: Add framework for MVE decode
57
target/arm: Move expand_pred_b() data to vec_helper.c
58
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
59
include/qemu/int128.h: Add function to create Int128 from int64_t
60
61
Richard Henderson (4):
62
target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
63
target/arm: Remove fprintf from disas_simd_mod_imm
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target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
65
target/arm: Fix mte page crossing test
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67
include/qemu/bitops.h | 29 +++
68
include/qemu/int128.h | 10 +
69
target/arm/translate-a32.h | 2 +
70
target/arm/translate.h | 9 +
71
target/arm/vec_internal.h | 9 +
72
target/arm/mve.decode | 20 ++
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target/arm/t32.decode | 15 +-
74
hw/arm/aspeed.c | 11 +-
75
hw/arm/npcm7xx_boards.c | 107 ++++++++++-
76
hw/arm/virt.c | 2 +
77
hw/intc/arm_gicv3_cpuif.c | 5 +-
78
hw/intc/armv7m_nvic.c | 6 -
79
target/arm/m_helper.c | 54 +++++-
80
target/arm/mte_helper.c | 2 +-
81
target/arm/sve_helper.c | 381 +++++++++++++-------------------------
82
target/arm/translate-a64.c | 87 +++++----
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target/arm/translate-m-nocp.c | 16 +-
84
target/arm/translate-mve.c | 29 +++
85
target/arm/translate-vfp.c | 65 +++++--
86
target/arm/translate.c | 300 ++++++++++++++++++++++++++++--
87
target/arm/vec_helper.c | 116 +++++++++++-
88
target/arm/vfp_helper.c | 3 +-
89
tests/tcg/aarch64/mte-7.c | 31 ++++
90
hw/arm/Kconfig | 2 +
91
target/arm/meson.build | 2 +
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tests/tcg/aarch64/Makefile.target | 2 +-
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26 files changed, 967 insertions(+), 348 deletions(-)
94
create mode 100644 target/arm/mve.decode
95
create mode 100644 target/arm/translate-mve.c
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create mode 100644 tests/tcg/aarch64/mte-7.c
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diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
was always returning zero. This also obviates the adjustment
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
7
The effects of the bug are not visible, because the only thing that
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/kvm64.c | 27 +++++++++++++--------------
18
1 file changed, 13 insertions(+), 14 deletions(-)
19
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/kvm64.c
23
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
25
bool sve_supported;
26
bool pmu_supported = false;
27
uint64_t features = 0;
28
- uint64_t t;
29
int err;
30
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
struct kvm_vcpu_init init = { .target = -1, };
34
35
/*
36
- * Ask for Pointer Authentication if supported. We can't play the
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
38
- * whether we have the architected or IMPDEF version of PAuth, so
39
- * we have to use the actual ID regs.
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
41
+ * which is otherwise RAZ.
42
+ */
43
+ sve_supported = kvm_arm_sve_supported();
44
+ if (sve_supported) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
46
+ }
47
+
48
+ /*
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
*/
52
if (kvm_arm_pauth_supported()) {
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
}
56
}
57
58
- sve_supported = kvm_arm_sve_supported();
59
-
60
- /* Add feature bits that can't appear until after VCPU init. */
61
if (sve_supported) {
62
- t = ahcf->isar.id_aa64pfr0;
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
- ahcf->isar.id_aa64pfr0 = t;
65
-
66
/*
67
* There is a range of kernels between kernel commit 73433762fcae
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
- * SVE support, so we only read it here, rather than together with all
71
- * the other ID registers earlier.
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
*/
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
77
--
78
2.25.1
diff view generated by jsdifflib
New patch
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The test for the IF block indicates no ID registers are exposed, much
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 22 +++++++++++-----------
12
1 file changed, 11 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
21
}
22
- }
23
24
- if (sve_supported) {
25
- /*
26
- * There is a range of kernels between kernel commit 73433762fcae
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
29
- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
31
- */
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
34
+ if (sve_supported) {
35
+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
45
}
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
48
--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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