| 1 | v2: dropped the hw/acpi/ghes-stub.c changes, which produce a | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | weird Meson error ("Tried to extract unknown source ghes-stub.c") | ||
| 3 | which didn't happen on my local builds; I'll investigate later... | ||
| 4 | 2 | ||
| 5 | -- PMM | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 6 | 4 | ||
| 7 | The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 8 | |||
| 9 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100) | ||
| 10 | 6 | ||
| 11 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 12 | 8 | ||
| 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 14 | 10 | ||
| 15 | for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2: | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 16 | 12 | ||
| 17 | include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100) | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 18 | 14 | ||
| 19 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 16 | target-arm queue: |
| 21 | * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes | 17 | * Implement IMPDEF pauth algorithm |
| 22 | * handle some UNALLOCATED decode cases correctly rather | 18 | * Support ARMv8.4-SEL2 |
| 23 | than asserting | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 24 | * hw: virt: consider hw_compat_6_0 | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 25 | * hw/arm: add quanta-gbs-bmc machine | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 26 | * hw/intc/armv7m_nvic: Remove stale comment | 22 | * docs: Build and install all the docs in a single manual |
| 27 | * target/arm: Fix mte page crossing test | ||
| 28 | * hw/arm: quanta-q71l add pca954x muxes | ||
| 29 | * target/arm: First few parts of MVE support | ||
| 30 | 23 | ||
| 31 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 32 | Heinrich Schuchardt (1): | 25 | Gan Qixin (1): |
| 33 | hw: virt: consider hw_compat_6_0 | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 34 | 27 | ||
| 35 | Jean-Philippe Brucker (1): | 28 | Peter Maydell (1): |
| 36 | hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes | 29 | docs: Build and install all the docs in a single manual |
| 37 | 30 | ||
| 38 | Patrick Venture (5): | 31 | Philippe Mathieu-Daudé (1): |
| 39 | hw/arm: add quanta-gbs-bmc machine | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 40 | hw/arm: quanta-gbs-bmc add i2c comments | ||
| 41 | hw/arm: gsj add i2c comments | ||
| 42 | hw/arm: gsj add pca9548 | ||
| 43 | hw/arm: quanta-q71l add pca954x muxes | ||
| 44 | 33 | ||
| 45 | Peter Maydell (14): | 34 | Richard Henderson (7): |
| 46 | hw/intc/armv7m_nvic: Remove stale comment | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 47 | target/arm: Provide and use H8 and H1_8 macros | 36 | target/arm: Add cpu properties to control pauth |
| 48 | target/arm: Enable FPSCR.QC bit for MVE | 37 | target/arm: Use object_property_add_bool for "sve" property |
| 49 | target/arm: Handle VPR semantics in existing code | 38 | target/arm: Introduce PREDDESC field definitions |
| 50 | target/arm: Add handling for PSR.ECI/ICI | 39 | target/arm: Update PFIRST, PNEXT for pred_desc |
| 51 | target/arm: Let vfp_access_check() handle late NOCP checks | 40 | target/arm: Update ZIP, UZP, TRN for pred_desc |
| 52 | target/arm: Implement MVE LCTP | 41 | target/arm: Update REV, PUNPK for pred_desc |
| 53 | target/arm: Implement MVE WLSTP insn | ||
| 54 | target/arm: Implement MVE DLSTP | ||
| 55 | target/arm: Implement MVE LETP insn | ||
| 56 | target/arm: Add framework for MVE decode | ||
| 57 | target/arm: Move expand_pred_b() data to vec_helper.c | ||
| 58 | bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations | ||
| 59 | include/qemu/int128.h: Add function to create Int128 from int64_t | ||
| 60 | 42 | ||
| 61 | Richard Henderson (4): | 43 | Rémi Denis-Courmont (19): |
| 62 | target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 | 44 | target/arm: remove redundant tests |
| 63 | target/arm: Remove fprintf from disas_simd_mod_imm | 45 | target/arm: add arm_is_el2_enabled() helper |
| 64 | target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 | 46 | target/arm: use arm_is_el2_enabled() where applicable |
| 65 | target/arm: Fix mte page crossing test | 47 | target/arm: use arm_hcr_el2_eff() where applicable |
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 66 | 63 | ||
| 67 | include/qemu/bitops.h | 29 +++ | 64 | docs/conf.py | 46 ++++- |
| 68 | include/qemu/int128.h | 10 + | 65 | docs/devel/conf.py | 15 -- |
| 69 | target/arm/translate-a32.h | 2 + | 66 | docs/index.html.in | 17 -- |
| 70 | target/arm/translate.h | 9 + | 67 | docs/interop/conf.py | 28 --- |
| 71 | target/arm/vec_internal.h | 9 + | 68 | docs/meson.build | 64 +++--- |
| 72 | target/arm/mve.decode | 20 ++ | 69 | docs/specs/conf.py | 16 -- |
| 73 | target/arm/t32.decode | 15 +- | 70 | docs/system/arm/cpu-features.rst | 21 ++ |
| 74 | hw/arm/aspeed.c | 11 +- | 71 | docs/system/conf.py | 28 --- |
| 75 | hw/arm/npcm7xx_boards.c | 107 ++++++++++- | 72 | docs/tools/conf.py | 37 ---- |
| 76 | hw/arm/virt.c | 2 + | 73 | docs/user/conf.py | 15 -- |
| 77 | hw/intc/arm_gicv3_cpuif.c | 5 +- | 74 | include/qemu/xxhash.h | 98 +++++++++ |
| 78 | hw/intc/armv7m_nvic.c | 6 - | 75 | target/arm/cpu-param.h | 2 +- |
| 79 | target/arm/m_helper.c | 54 +++++- | 76 | target/arm/cpu.h | 107 ++++++++-- |
| 80 | target/arm/mte_helper.c | 2 +- | 77 | target/arm/internals.h | 45 +++++ |
| 81 | target/arm/sve_helper.c | 381 +++++++++++++------------------------- | 78 | target/arm/cpu.c | 23 ++- |
| 82 | target/arm/translate-a64.c | 87 +++++---- | 79 | target/arm/cpu64.c | 65 ++++-- |
| 83 | target/arm/translate-m-nocp.c | 16 +- | 80 | target/arm/helper-a64.c | 8 +- |
| 84 | target/arm/translate-mve.c | 29 +++ | 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- |
| 85 | target/arm/translate-vfp.c | 65 +++++-- | 82 | target/arm/m_helper.c | 2 +- |
| 86 | target/arm/translate.c | 300 ++++++++++++++++++++++++++++-- | 83 | target/arm/monitor.c | 1 + |
| 87 | target/arm/vec_helper.c | 116 +++++++++++- | 84 | target/arm/op_helper.c | 4 +- |
| 88 | target/arm/vfp_helper.c | 3 +- | 85 | target/arm/pauth_helper.c | 27 ++- |
| 89 | tests/tcg/aarch64/mte-7.c | 31 ++++ | 86 | target/arm/sve_helper.c | 33 ++-- |
| 90 | hw/arm/Kconfig | 2 + | 87 | target/arm/tlb_helper.c | 3 + |
| 91 | target/arm/meson.build | 2 + | 88 | target/arm/translate-a64.c | 4 + |
| 92 | tests/tcg/aarch64/Makefile.target | 2 +- | 89 | target/arm/translate-sve.c | 31 ++- |
| 93 | 26 files changed, 967 insertions(+), 348 deletions(-) | 90 | target/arm/translate.c | 36 +++- |
| 94 | create mode 100644 target/arm/mve.decode | 91 | tests/qtest/arm-cpu-features.c | 13 ++ |
| 95 | create mode 100644 target/arm/translate-mve.c | 92 | tests/qtest/npcm7xx_adc-test.c | 1 + |
| 96 | create mode 100644 tests/tcg/aarch64/mte-7.c | 93 | .gitlab-ci.yml | 4 +- |
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 97 | 102 | diff view generated by jsdifflib |