[v1] tcg: bswap improvements

[PATCH 25/28] target/mips: Fix gen_mxu_s32ldd_s32lddr

Posted by Richard Henderson 3 years, 4 months ago

There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.

The best fix is to fold the bswap into the memory operation,
producing the desired result directly.

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/mxu_translate.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c12cf78df7..f4356432c7 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -857,12 +857,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
         tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
     }
     tcg_gen_add_tl(t1, t0, t1);
-    tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
+    tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
 
-    if (sel == 1) {
-        /* S32LDDR */
-        tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
-    }
     gen_store_mxu_gpr(t1, XRa);
 
     tcg_temp_free(t0);
-- 
2.25.1

Re: [PATCH 25/28] target/mips: Fix gen_mxu_s32ldd_s32lddr

Posted by Philippe Mathieu-Daudé 3 years, 4 months ago

Cc'ing Craig

On 6/14/21 10:37 AM, Richard Henderson wrote:
> There were two bugs here: (1) the required endianness was
> not present in the MemOp, and (2) we were not providing a
> zero-extended input to the bswap as semantics required.
> 
> The best fix is to fold the bswap into the memory operation,
> producing the desired result directly.
> 
> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/mips/tcg/mxu_translate.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
> index c12cf78df7..f4356432c7 100644
> --- a/target/mips/tcg/mxu_translate.c
> +++ b/target/mips/tcg/mxu_translate.c
> @@ -857,12 +857,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
>          tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
>      }
>      tcg_gen_add_tl(t1, t0, t1);
> -    tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
> +    tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
>  
> -    if (sel == 1) {
> -        /* S32LDDR */
> -        tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
> -    }
>      gen_store_mxu_gpr(t1, XRa);
>  
>      tcg_temp_free(t0);
> 

Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>