[PULL 00/32] riscv-to-apply queue
[PULL 00/28] riscv-to-apply queue
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The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:
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The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
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Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100)
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Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
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for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:
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for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
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target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)
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target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
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----------------------------------------------------------------
13
----------------------------------------------------------------
14
Second RISC-V PR for QEMU 6.1
14
RISC-V PR for 9.1
15
15
16
- Update the PLIC and CLINT DT bindings
16
* APLICs add child earlier than realize
17
- Improve documentation for RISC-V machines
17
* Fix exposure of Zkr
18
- Support direct kernel boot for microchip_pfsoc
18
* Raise exceptions on wrs.nto
19
- Fix WFI exception behaviour
19
* Implement SBI debug console (DBCN) calls for KVM
20
- Improve CSR printing
20
* Support 64-bit addresses for initrd
21
- Initial support for the experimental Bit Manip extension
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
* Tolerate KVM disable ext errors
23
* Set tval in breakpoints
24
* Add support for Zve32x extension
25
* Add support for Zve64x extension
26
* Relax vector register check in RISCV gdbstub
27
* Fix the element agnostic Vector function problem
28
* Fix Zvkb extension config
29
* Implement dynamic establishment of custom decoder
30
* Add th.sxstatus CSR emulation
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Check single width operator for vector fp widen instructions
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
22
43
23
----------------------------------------------------------------
44
----------------------------------------------------------------
45
Alexei Filippov (1):
46
target/riscv: do not set mtval2 for non guest-page faults
47
24
Alistair Francis (2):
48
Alistair Francis (2):
25
docs/system: Move the RISC-V -bios information to removed
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
26
target/riscv/pmp: Add assert for ePMP operations
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
27
51
28
Bin Meng (9):
52
Andrew Jones (2):
29
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
53
target/riscv/kvm: Fix exposure of Zkr
30
hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
54
target/riscv: Raise exceptions on wrs.nto
31
hw/riscv: Support the official CLINT DT bindings
32
hw/riscv: Support the official PLIC DT bindings
33
docs/system/riscv: Correct the indentation level of supported devices
34
docs/system/riscv: sifive_u: Document '-dtb' usage
35
hw/riscv: Use macros for BIOS image names
36
hw/riscv: microchip_pfsoc: Support direct kernel boot
37
target/riscv: Remove unnecessary riscv_*_names[] declaration
38
55
39
Changbin Du (1):
56
Cheng Yang (1):
40
target/riscv: Dump CSR mscratch/sscratch/satp
57
hw/riscv/boot.c: Support 64-bit address for initrd
41
58
42
Frank Chang (6):
59
Christoph Müllner (1):
43
target/riscv: rvb: count bits set
60
riscv: thead: Add th.sxstatus CSR emulation
44
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
45
target/riscv: rvb: single-bit instructions
46
target/riscv: rvb: generalized reverse
47
target/riscv: rvb: generalized or-combine
48
target/riscv: rvb: add b-ext version cpu option
49
61
50
Jose Martins (1):
62
Clément Léger (1):
51
target/riscv: fix wfi exception behavior
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
52
64
53
Kito Cheng (11):
65
Daniel Henrique Barboza (6):
54
target/riscv: reformat @sh format encoding for B-extension
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
55
target/riscv: rvb: count leading/trailing zeros
67
target/riscv/kvm: tolerate KVM disable ext errors
56
target/riscv: rvb: logic-with-negate
68
target/riscv/debug: set tval=pc in breakpoint exceptions
57
target/riscv: rvb: pack two words into one register
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
58
target/riscv: rvb: min/max instructions
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
59
target/riscv: rvb: sign-extend instructions
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
60
target/riscv: rvb: shift ones
61
target/riscv: rvb: rotate (left/right)
62
target/riscv: rvb: address calculation
63
target/riscv: rvb: add/shift with prefix zero-extend
64
target/riscv: rvb: support and turn on B-extension from command line
65
72
66
LIU Zhiwei (1):
73
Huang Tao (2):
67
target/riscv: Pass the same value to oprsz and maxsz.
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
68
76
69
Philippe Mathieu-Daudé (1):
77
Jason Chien (3):
70
target/riscv: Do not include 'pmp.h' in user emulation
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
71
81
72
docs/system/deprecated.rst | 19 --
82
Max Chou (4):
73
docs/system/removed-features.rst | 5 +
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
74
docs/system/riscv/microchip-icicle-kit.rst | 50 +++-
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
75
docs/system/riscv/sifive_u.rst | 77 +++--
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
76
docs/system/target-riscv.rst | 13 +-
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
77
include/hw/riscv/boot.h | 5 +
78
target/riscv/cpu.h | 9 +-
79
target/riscv/cpu_bits.h | 1 +
80
target/riscv/helper.h | 6 +
81
target/riscv/insn32.decode | 87 +++++-
82
hw/riscv/microchip_pfsoc.c | 81 +++++-
83
hw/riscv/sifive_u.c | 24 +-
84
hw/riscv/spike.c | 12 +-
85
hw/riscv/virt.c | 25 +-
86
target/riscv/bitmanip_helper.c | 90 ++++++
87
target/riscv/cpu.c | 38 ++-
88
target/riscv/op_helper.c | 11 +-
89
target/riscv/pmp.c | 4 +
90
target/riscv/translate.c | 306 ++++++++++++++++++++
91
target/riscv/insn_trans/trans_rvb.c.inc | 438 +++++++++++++++++++++++++++++
92
target/riscv/insn_trans/trans_rvi.c.inc | 54 +---
93
target/riscv/insn_trans/trans_rvv.c.inc | 89 +++---
94
target/riscv/meson.build | 1 +
95
23 files changed, 1260 insertions(+), 185 deletions(-)
96
create mode 100644 target/riscv/bitmanip_helper.c
97
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
98
87
88
Rob Bradford (1):
89
target/riscv: Remove experimental prefix from "B" extension
90
91
Yangyu Chen (1):
92
target/riscv/cpu.c: fix Zvkb extension config
93
94
Yong-Xuan Wang (1):
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
96
97
Yu-Ming Chang (1):
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
100
yang.zhang (1):
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
103
MAINTAINERS | 1 +
104
target/riscv/cpu.h | 11 ++
105
target/riscv/cpu_bits.h | 2 +-
106
target/riscv/cpu_cfg.h | 2 +
107
target/riscv/helper.h | 1 +
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
disas/riscv.c | 65 +++++++++-
111
hw/intc/riscv_aplic.c | 8 +-
112
hw/riscv/boot.c | 4 +-
113
target/riscv/cpu.c | 10 +-
114
target/riscv/cpu_helper.c | 37 +++---
115
target/riscv/csr.c | 71 +++++++++--
116
target/riscv/debug.c | 3 +
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
target/riscv/op_helper.c | 17 ++-
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
target/riscv/th_csr.c | 79 +++++++++++++
122
target/riscv/translate.c | 31 +++--
123
target/riscv/vector_internals.c | 22 ++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/meson.build | 1 +
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
create mode 100644 target/riscv/th_csr.c
131
diff view generated by jsdifflib
[PULL 29/32] target/riscv: rvb: address calculation
[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: "yang.zhang" <yang.zhang@hexintek.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
be initialized first.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
12
---
9
target/riscv/insn32.decode | 6 +++++
13
hw/intc/riscv_aplic.c | 8 ++++----
10
target/riscv/translate.c | 32 +++++++++++++++++++++++++
14
1 file changed, 4 insertions(+), 4 deletions(-)
11
target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
12
3 files changed, 62 insertions(+)
13
15
14
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/insn32.decode
18
--- a/hw/intc/riscv_aplic.c
17
+++ b/target/riscv/insn32.decode
19
+++ b/hw/intc/riscv_aplic.c
18
@@ -XXX,XX +XXX,XX @@ ror 0110000 .......... 101 ..... 0110011 @r
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
19
rol 0110000 .......... 001 ..... 0110011 @r
21
qdev_prop_set_bit(dev, "msimode", msimode);
20
grev 0110100 .......... 101 ..... 0110011 @r
22
qdev_prop_set_bit(dev, "mmode", mmode);
21
gorc 0010100 .......... 101 ..... 0110011 @r
23
22
+sh1add 0010000 .......... 010 ..... 0110011 @r
24
+ if (parent) {
23
+sh2add 0010000 .......... 100 ..... 0110011 @r
25
+ riscv_aplic_add_child(parent, dev);
24
+sh3add 0010000 .......... 110 ..... 0110011 @r
26
+ }
25
26
bseti 00101. ........... 001 ..... 0010011 @sh
27
bclri 01001. ........... 001 ..... 0010011 @sh
28
@@ -XXX,XX +XXX,XX @@ rorw 0110000 .......... 101 ..... 0111011 @r
29
rolw 0110000 .......... 001 ..... 0111011 @r
30
grevw 0110100 .......... 101 ..... 0111011 @r
31
gorcw 0010100 .......... 101 ..... 0111011 @r
32
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
33
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
34
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
35
36
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
37
bclriw 0100100 .......... 001 ..... 0011011 @sh5
38
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/translate.c
41
+++ b/target/riscv/translate.c
42
@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
43
return true;
44
}
45
46
+#define GEN_SHADD(SHAMT) \
47
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
48
+{ \
49
+ TCGv t = tcg_temp_new(); \
50
+ \
51
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
52
+ tcg_gen_add_tl(ret, t, arg2); \
53
+ \
54
+ tcg_temp_free(t); \
55
+}
56
+
27
+
57
+GEN_SHADD(1)
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
58
+GEN_SHADD(2)
29
59
+GEN_SHADD(3)
30
if (!is_kvm_aia(msimode)) {
60
+
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
61
static void gen_ctzw(TCGv ret, TCGv arg1)
32
}
62
{
33
63
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
34
- if (parent) {
64
@@ -XXX,XX +XXX,XX @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
35
- riscv_aplic_add_child(parent, dev);
65
gen_helper_gorcw(ret, arg1, arg2);
36
- }
66
}
37
-
67
38
if (!msimode) {
68
+#define GEN_SHADD_UW(SHAMT) \
39
for (i = 0; i < num_harts; i++) {
69
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
70
+{ \
71
+ TCGv t = tcg_temp_new(); \
72
+ \
73
+ tcg_gen_ext32u_tl(t, arg1); \
74
+ \
75
+ tcg_gen_shli_tl(t, t, SHAMT); \
76
+ tcg_gen_add_tl(ret, t, arg2); \
77
+ \
78
+ tcg_temp_free(t); \
79
+}
80
+
81
+GEN_SHADD_UW(1)
82
+GEN_SHADD_UW(2)
83
+GEN_SHADD_UW(3)
84
+
85
static bool gen_arith(DisasContext *ctx, arg_r *a,
86
void(*func)(TCGv, TCGv, TCGv))
87
{
88
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/riscv/insn_trans/trans_rvb.c.inc
91
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
92
@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
93
return gen_shifti(ctx, a, gen_helper_gorc);
94
}
95
96
+#define GEN_TRANS_SHADD(SHAMT) \
97
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
98
+{ \
99
+ REQUIRE_EXT(ctx, RVB); \
100
+ return gen_arith(ctx, a, gen_sh##SHAMT##add); \
101
+}
102
+
103
+GEN_TRANS_SHADD(1)
104
+GEN_TRANS_SHADD(2)
105
+GEN_TRANS_SHADD(3)
106
+
107
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
108
{
109
REQUIRE_64BIT(ctx);
110
@@ -XXX,XX +XXX,XX @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
111
REQUIRE_EXT(ctx, RVB);
112
return gen_shiftiw(ctx, a, gen_gorcw);
113
}
114
+
115
+#define GEN_TRANS_SHADD_UW(SHAMT) \
116
+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
117
+ arg_sh##SHAMT##add_uw *a) \
118
+{ \
119
+ REQUIRE_64BIT(ctx); \
120
+ REQUIRE_EXT(ctx, RVB); \
121
+ return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
122
+}
123
+
124
+GEN_TRANS_SHADD_UW(1)
125
+GEN_TRANS_SHADD_UW(2)
126
+GEN_TRANS_SHADD_UW(3)
127
--
41
--
128
2.31.1
42
2.45.1
129
130
diff view generated by jsdifflib
[PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation
[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
Physical Memory Protection is a system feature.
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
Avoid polluting the user-mode emulation by its definitions.
4
implements the SEED CSR. Use the same implementation as TCG.
5
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Without this patch, running with a KVM which does not forward the
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
SEED CSR access to QEMU will result in an ILL exception being
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
injected into the guest (this results in Linux guests crashing on
9
Message-id: 20210516205333.696094-1-f4bug@amsat.org
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
11
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Cc: qemu-stable <qemu-stable@nongnu.org>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
target/riscv/cpu.h | 2 ++
19
target/riscv/cpu.h | 3 +++
13
1 file changed, 2 insertions(+)
20
target/riscv/csr.c | 18 ++++++++++++++----
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
14
23
15
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.h
26
--- a/target/riscv/cpu.h
18
+++ b/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@ enum {
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
20
29
21
typedef struct CPURISCVState CPURISCVState;
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
22
31
23
+#if !defined(CONFIG_USER_ONLY)
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
24
#include "pmp.h"
33
+ target_ulong write_mask);
25
+#endif
34
+
26
35
uint8_t satp_mode_max_from_map(uint32_t map);
27
#define RV_VLEN_MAX 256
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
28
37
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
43
#endif
44
45
/* Crypto Extension */
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
47
- target_ulong *ret_value,
48
- target_ulong new_value,
49
- target_ulong write_mask)
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
51
+ target_ulong write_mask)
52
{
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
57
}
58
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
80
}
81
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
83
+{
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
85
+ target_ulong new_value = run->riscv_csr.new_value;
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
29
--
117
--
30
2.31.1
118
2.45.1
31
32
diff view generated by jsdifflib
[PULL 28/32] target/riscv: rvb: generalized or-combine
[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
Signed-off-by: Frank Chang <frank.chang@sifive.com>
3
Implementing wrs.nto to always just return is consistent with the
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
specification, as the instruction is permitted to terminate the
5
Message-id: 20210505160620.15723-14-frank.chang@sifive.com
5
stall for any reason, but it's not useful for virtualization, where
6
we'd like the guest to trap to the hypervisor in order to allow
7
scheduling of the lock holding VCPU. Change to always immediately
8
raise exceptions when the appropriate conditions are present,
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
13
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
20
---
8
target/riscv/helper.h | 2 ++
21
target/riscv/helper.h | 1 +
9
target/riscv/insn32.decode | 4 ++++
22
target/riscv/op_helper.c | 11 ++++++++
10
target/riscv/bitmanip_helper.c | 26 +++++++++++++++++++++++++
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
11
target/riscv/translate.c | 6 ++++++
24
3 files changed, 32 insertions(+), 9 deletions(-)
12
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
13
5 files changed, 64 insertions(+)
14
25
15
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
16
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/helper.h
28
--- a/target/riscv/helper.h
18
+++ b/target/riscv/helper.h
29
+++ b/target/riscv/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
20
/* Bitmanip */
31
DEF_HELPER_1(sret, tl, env)
21
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
32
DEF_HELPER_1(mret, tl, env)
22
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
33
DEF_HELPER_1(wfi, void, env)
23
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
34
+DEF_HELPER_1(wrs_nto, void, env)
24
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
35
DEF_HELPER_1(tlb_flush, void, env)
25
36
DEF_HELPER_1(tlb_flush_all, void, env)
26
/* Special functions */
37
/* Native Debug */
27
DEF_HELPER_3(csrrw, tl, env, tl, tl)
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
28
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
29
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
30
--- a/target/riscv/insn32.decode
40
--- a/target/riscv/op_helper.c
31
+++ b/target/riscv/insn32.decode
41
+++ b/target/riscv/op_helper.c
32
@@ -XXX,XX +XXX,XX @@ sro 0010000 .......... 101 ..... 0110011 @r
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
33
ror 0110000 .......... 101 ..... 0110011 @r
43
}
34
rol 0110000 .......... 001 ..... 0110011 @r
35
grev 0110100 .......... 101 ..... 0110011 @r
36
+gorc 0010100 .......... 101 ..... 0110011 @r
37
38
bseti 00101. ........... 001 ..... 0010011 @sh
39
bclri 01001. ........... 001 ..... 0010011 @sh
40
@@ -XXX,XX +XXX,XX @@ sloi 00100. ........... 001 ..... 0010011 @sh
41
sroi 00100. ........... 101 ..... 0010011 @sh
42
rori 01100. ........... 101 ..... 0010011 @sh
43
grevi 01101. ........... 101 ..... 0010011 @sh
44
+gorci 00101. ........... 101 ..... 0010011 @sh
45
46
# *** RV64B Standard Extension (in addition to RV32B) ***
47
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
48
@@ -XXX,XX +XXX,XX @@ srow 0010000 .......... 101 ..... 0111011 @r
49
rorw 0110000 .......... 101 ..... 0111011 @r
50
rolw 0110000 .......... 001 ..... 0111011 @r
51
grevw 0110100 .......... 101 ..... 0111011 @r
52
+gorcw 0010100 .......... 101 ..... 0111011 @r
53
54
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
55
bclriw 0100100 .......... 001 ..... 0011011 @sh5
56
@@ -XXX,XX +XXX,XX @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
57
sroiw 0010000 .......... 101 ..... 0011011 @sh5
58
roriw 0110000 .......... 101 ..... 0011011 @sh5
59
greviw 0110100 .......... 101 ..... 0011011 @sh5
60
+gorciw 0010100 .......... 101 ..... 0011011 @sh5
61
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/bitmanip_helper.c
64
+++ b/target/riscv/bitmanip_helper.c
65
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
66
{
67
return do_grev(rs1, rs2, 32);
68
}
44
}
69
+
45
70
+static target_ulong do_gorc(target_ulong rs1,
46
+void helper_wrs_nto(CPURISCVState *env)
71
+ target_ulong rs2,
72
+ int bits)
73
+{
47
+{
74
+ target_ulong x = rs1;
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
75
+ int i, shift;
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
76
+
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
77
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
78
+ if (rs2 & shift) {
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
79
+ x |= do_swap(x, adjacent_masks[i], shift);
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
80
+ }
81
+ }
54
+ }
82
+
83
+ return x;
84
+}
55
+}
85
+
56
+
86
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
57
void helper_tlb_flush(CPURISCVState *env)
58
{
59
CPUState *cs = env_cpu(env);
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
64
@@ -XXX,XX +XXX,XX @@
65
* this program. If not, see <http://www.gnu.org/licenses/>.
66
*/
67
68
-static bool trans_wrs(DisasContext *ctx)
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
70
{
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
75
}
76
77
-#define GEN_TRANS_WRS(insn) \
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
79
-{ \
80
- (void)a; \
81
- return trans_wrs(ctx); \
82
-}
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
87
+{
84
+{
88
+ return do_gorc(rs1, rs2, TARGET_LONG_BITS);
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
89
+}
86
+ return false;
87
+ }
88
89
-GEN_TRANS_WRS(wrs_nto)
90
-GEN_TRANS_WRS(wrs_sto)
91
+ /*
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
93
+ * should raise an exception when the implementation-specific bounded time
94
+ * limit has expired. Our time limit is zero, so we either return
95
+ * immediately, as does our implementation of wrs.sto, or raise an
96
+ * exception, as handled by the wrs.nto helper.
97
+ */
98
+#ifndef CONFIG_USER_ONLY
99
+ gen_helper_wrs_nto(tcg_env);
100
+#endif
90
+
101
+
91
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
92
+{
103
+ return trans_wrs_sto(ctx, NULL);
93
+ return do_gorc(rs1, rs2, 32);
94
+}
95
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/riscv/translate.c
98
+++ b/target/riscv/translate.c
99
@@ -XXX,XX +XXX,XX @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
100
gen_helper_grev(ret, arg1, arg2);
101
}
102
103
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
104
+{
105
+ tcg_gen_ext32u_tl(arg1, arg1);
106
+ gen_helper_gorcw(ret, arg1, arg2);
107
+}
108
+
109
static bool gen_arith(DisasContext *ctx, arg_r *a,
110
void(*func)(TCGv, TCGv, TCGv))
111
{
112
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/riscv/insn_trans/trans_rvb.c.inc
115
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
116
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
117
return gen_grevi(ctx, a);
118
}
119
120
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
121
+{
122
+ REQUIRE_EXT(ctx, RVB);
123
+ return gen_shift(ctx, a, gen_helper_gorc);
124
+}
125
+
126
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
127
+{
128
+ REQUIRE_EXT(ctx, RVB);
129
+ return gen_shifti(ctx, a, gen_helper_gorc);
130
+}
131
+
132
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
133
{
134
REQUIRE_64BIT(ctx);
135
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
136
REQUIRE_EXT(ctx, RVB);
137
return gen_shiftiw(ctx, a, gen_grevw);
138
}
139
+
140
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
141
+{
142
+ REQUIRE_64BIT(ctx);
143
+ REQUIRE_EXT(ctx, RVB);
144
+ return gen_shiftw(ctx, a, gen_gorcw);
145
+}
146
+
147
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
148
+{
149
+ REQUIRE_64BIT(ctx);
150
+ REQUIRE_EXT(ctx, RVB);
151
+ return gen_shiftiw(ctx, a, gen_gorcw);
152
+}
104
+}
153
--
105
--
154
2.31.1
106
2.45.1
155
107
156
108
diff view generated by jsdifflib
[PULL 26/32] target/riscv: rvb: rotate (left/right)
[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
the legacy console putchar and getchar SBI extensions.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
Message-id: 20210505160620.15723-12-frank.chang@sifive.com
7
read/written in the SBI console in a single SBI call.
8
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
module to userspace. But this will only happens if the KVM module
11
actually supports this SBI extension and we activate it.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
25
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
30
---
10
target/riscv/insn32.decode | 6 ++++
31
target/riscv/sbi_ecall_interface.h | 17 +++++
11
target/riscv/translate.c | 36 +++++++++++++++++++++++
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
12
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
33
2 files changed, 128 insertions(+)
13
3 files changed, 81 insertions(+)
34
14
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
15
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
16
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn32.decode
37
--- a/target/riscv/sbi_ecall_interface.h
18
+++ b/target/riscv/insn32.decode
38
+++ b/target/riscv/sbi_ecall_interface.h
19
@@ -XXX,XX +XXX,XX @@ binv 0110100 .......... 001 ..... 0110011 @r
39
@@ -XXX,XX +XXX,XX @@
20
bext 0100100 .......... 101 ..... 0110011 @r
40
21
slo 0010000 .......... 001 ..... 0110011 @r
41
/* clang-format off */
22
sro 0010000 .......... 101 ..... 0110011 @r
42
23
+ror 0110000 .......... 101 ..... 0110011 @r
43
+#define SBI_SUCCESS 0
24
+rol 0110000 .......... 001 ..... 0110011 @r
44
+#define SBI_ERR_FAILED -1
25
45
+#define SBI_ERR_NOT_SUPPORTED -2
26
bseti 00101. ........... 001 ..... 0010011 @sh
46
+#define SBI_ERR_INVALID_PARAM -3
27
bclri 01001. ........... 001 ..... 0010011 @sh
47
+#define SBI_ERR_DENIED -4
28
@@ -XXX,XX +XXX,XX @@ binvi 01101. ........... 001 ..... 0010011 @sh
48
+#define SBI_ERR_INVALID_ADDRESS -5
29
bexti 01001. ........... 101 ..... 0010011 @sh
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
30
sloi 00100. ........... 001 ..... 0010011 @sh
50
+#define SBI_ERR_ALREADY_STARTED -7
31
sroi 00100. ........... 101 ..... 0010011 @sh
51
+#define SBI_ERR_ALREADY_STOPPED -8
32
+rori 01100. ........... 101 ..... 0010011 @sh
52
+#define SBI_ERR_NO_SHMEM -9
33
53
+
34
# *** RV64B Standard Extension (in addition to RV32B) ***
54
/* SBI Extension IDs */
35
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
55
#define SBI_EXT_0_1_SET_TIMER 0x0
36
@@ -XXX,XX +XXX,XX @@ binvw 0110100 .......... 001 ..... 0111011 @r
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
37
bextw 0100100 .......... 101 ..... 0111011 @r
57
@@ -XXX,XX +XXX,XX @@
38
slow 0010000 .......... 001 ..... 0111011 @r
58
#define SBI_EXT_IPI 0x735049
39
srow 0010000 .......... 101 ..... 0111011 @r
59
#define SBI_EXT_RFENCE 0x52464E43
40
+rorw 0110000 .......... 101 ..... 0111011 @r
60
#define SBI_EXT_HSM 0x48534D
41
+rolw 0110000 .......... 001 ..... 0111011 @r
61
+#define SBI_EXT_DBCN 0x4442434E
42
62
43
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
63
/* SBI function IDs for BASE extension */
44
bclriw 0100100 .......... 001 ..... 0011011 @sh5
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
45
binviw 0110100 .......... 001 ..... 0011011 @sh5
65
@@ -XXX,XX +XXX,XX @@
46
sloiw 0010000 .......... 001 ..... 0011011 @sh5
66
#define SBI_EXT_HSM_HART_STOP 0x1
47
sroiw 0010000 .......... 101 ..... 0011011 @sh5
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
48
+roriw 0110000 .......... 101 ..... 0011011 @sh5
68
49
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
69
+/* SBI function IDs for DBCN extension */
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
73
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
50
index XXXXXXX..XXXXXXX 100644
78
index XXXXXXX..XXXXXXX 100644
51
--- a/target/riscv/translate.c
79
--- a/target/riscv/kvm/kvm-cpu.c
52
+++ b/target/riscv/translate.c
80
+++ b/target/riscv/kvm/kvm-cpu.c
53
@@ -XXX,XX +XXX,XX @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
54
tcg_temp_free(t);
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
55
}
83
};
56
84
57
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
85
+static KVMCPUConfig kvm_sbi_dbcn = {
86
+ .name = "sbi_dbcn",
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
89
+};
90
+
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
92
{
93
CPURISCVState *env = &cpu->env;
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
95
return 0;
96
}
97
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
99
+ KVMScratchCPU *kvmcpu,
100
+ struct kvm_reg_list *reglist)
58
+{
101
+{
59
+ TCGv_i32 t1 = tcg_temp_new_i32();
102
+ struct kvm_reg_list *reg_search;
60
+ TCGv_i32 t2 = tcg_temp_new_i32();
103
+
61
+
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
62
+ /* truncate to 32-bits */
105
+ sizeof(uint64_t), uint64_cmp);
63
+ tcg_gen_trunc_tl_i32(t1, arg1);
106
+
64
+ tcg_gen_trunc_tl_i32(t2, arg2);
107
+ if (reg_search) {
65
+
108
+ kvm_sbi_dbcn.supported = true;
66
+ tcg_gen_rotr_i32(t1, t1, t2);
109
+ }
67
+
68
+ /* sign-extend 64-bits */
69
+ tcg_gen_ext_i32_tl(ret, t1);
70
+
71
+ tcg_temp_free_i32(t1);
72
+ tcg_temp_free_i32(t2);
73
+}
110
+}
74
+
111
+
75
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
76
+{
129
+{
77
+ TCGv_i32 t1 = tcg_temp_new_i32();
130
+ target_ulong reg = 1;
78
+ TCGv_i32 t2 = tcg_temp_new_i32();
131
+
79
+
132
+ if (!kvm_sbi_dbcn.supported) {
80
+ /* truncate to 32-bits */
133
+ return 0;
81
+ tcg_gen_trunc_tl_i32(t1, arg1);
134
+ }
82
+ tcg_gen_trunc_tl_i32(t2, arg2);
135
+
83
+
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
84
+ tcg_gen_rotl_i32(t1, t1, t2);
85
+
86
+ /* sign-extend 64-bits */
87
+ tcg_gen_ext_i32_tl(ret, t1);
88
+
89
+ tcg_temp_free_i32(t1);
90
+ tcg_temp_free_i32(t2);
91
+}
137
+}
92
+
138
+
93
static bool gen_arith(DisasContext *ctx, arg_r *a,
139
int kvm_arch_init_vcpu(CPUState *cs)
94
void(*func)(TCGv, TCGv, TCGv))
140
{
95
{
141
int ret = 0;
96
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
97
index XXXXXXX..XXXXXXX 100644
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
98
--- a/target/riscv/insn_trans/trans_rvb.c.inc
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
99
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
145
100
@@ -XXX,XX +XXX,XX @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
101
return gen_shifti(ctx, a, gen_sro);
147
+
102
}
148
return ret;
103
149
}
104
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
105
+{
156
+{
106
+ REQUIRE_EXT(ctx, RVB);
157
+ g_autofree uint8_t *buf = NULL;
107
+ return gen_shift(ctx, a, tcg_gen_rotr_tl);
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
159
+ target_ulong num_bytes;
160
+ uint64_t addr;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
225
+ }
108
+}
226
+}
109
+
227
+
110
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
111
+{
229
{
112
+ REQUIRE_EXT(ctx, RVB);
230
int ret = 0;
113
+ return gen_shifti(ctx, a, tcg_gen_rotr_tl);
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
114
+}
232
}
115
+
233
ret = 0;
116
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
234
break;
117
+{
235
+ case SBI_EXT_DBCN:
118
+ REQUIRE_EXT(ctx, RVB);
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
119
+ return gen_shift(ctx, a, tcg_gen_rotl_tl);
237
+ break;
120
+}
238
default:
121
+
239
qemu_log_mask(LOG_UNIMP,
122
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
123
{
124
REQUIRE_64BIT(ctx);
125
@@ -XXX,XX +XXX,XX @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
126
REQUIRE_EXT(ctx, RVB);
127
return gen_shiftiw(ctx, a, gen_sro);
128
}
129
+
130
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
131
+{
132
+ REQUIRE_64BIT(ctx);
133
+ REQUIRE_EXT(ctx, RVB);
134
+ return gen_shiftw(ctx, a, gen_rorw);
135
+}
136
+
137
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
138
+{
139
+ REQUIRE_64BIT(ctx);
140
+ REQUIRE_EXT(ctx, RVB);
141
+ return gen_shiftiw(ctx, a, gen_rorw);
142
+}
143
+
144
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
145
+{
146
+ REQUIRE_64BIT(ctx);
147
+ REQUIRE_EXT(ctx, RVB);
148
+ return gen_shiftw(ctx, a, gen_rolw);
149
+}
150
--
241
--
151
2.31.1
242
2.45.1
152
153
diff view generated by jsdifflib
[PULL 25/32] target/riscv: rvb: shift ones
[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Cheng Yang <yangcheng.work@foxmail.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
to set the address of initrd in FDT to support 64-bit address.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
---
10
target/riscv/insn32.decode | 8 ++++
11
hw/riscv/boot.c | 4 ++--
11
target/riscv/translate.c | 14 +++++++
12
1 file changed, 2 insertions(+), 2 deletions(-)
12
target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
13
3 files changed, 74 insertions(+)
14
13
15
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn32.decode
16
--- a/hw/riscv/boot.c
18
+++ b/target/riscv/insn32.decode
17
+++ b/hw/riscv/boot.c
19
@@ -XXX,XX +XXX,XX @@ bset 0010100 .......... 001 ..... 0110011 @r
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
20
bclr 0100100 .......... 001 ..... 0110011 @r
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
21
binv 0110100 .......... 001 ..... 0110011 @r
20
if (fdt) {
22
bext 0100100 .......... 101 ..... 0110011 @r
21
end = start + size;
23
+slo 0010000 .......... 001 ..... 0110011 @r
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
24
+sro 0010000 .......... 101 ..... 0110011 @r
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
25
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
26
bseti 00101. ........... 001 ..... 0010011 @sh
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
27
bclri 01001. ........... 001 ..... 0010011 @sh
26
}
28
binvi 01101. ........... 001 ..... 0010011 @sh
29
bexti 01001. ........... 101 ..... 0010011 @sh
30
+sloi 00100. ........... 001 ..... 0010011 @sh
31
+sroi 00100. ........... 101 ..... 0010011 @sh
32
33
# *** RV64B Standard Extension (in addition to RV32B) ***
34
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
35
@@ -XXX,XX +XXX,XX @@ bsetw 0010100 .......... 001 ..... 0111011 @r
36
bclrw 0100100 .......... 001 ..... 0111011 @r
37
binvw 0110100 .......... 001 ..... 0111011 @r
38
bextw 0100100 .......... 101 ..... 0111011 @r
39
+slow 0010000 .......... 001 ..... 0111011 @r
40
+srow 0010000 .......... 101 ..... 0111011 @r
41
42
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
43
bclriw 0100100 .......... 001 ..... 0011011 @sh5
44
binviw 0110100 .......... 001 ..... 0011011 @sh5
45
+sloiw 0010000 .......... 001 ..... 0011011 @sh5
46
+sroiw 0010000 .......... 101 ..... 0011011 @sh5
47
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/translate.c
50
+++ b/target/riscv/translate.c
51
@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
52
tcg_gen_andi_tl(ret, ret, 1);
53
}
27
}
54
28
55
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
56
+{
57
+ tcg_gen_not_tl(ret, arg1);
58
+ tcg_gen_shl_tl(ret, ret, arg2);
59
+ tcg_gen_not_tl(ret, ret);
60
+}
61
+
62
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
63
+{
64
+ tcg_gen_not_tl(ret, arg1);
65
+ tcg_gen_shr_tl(ret, ret, arg2);
66
+ tcg_gen_not_tl(ret, ret);
67
+}
68
+
69
static void gen_ctzw(TCGv ret, TCGv arg1)
70
{
71
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
72
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/riscv/insn_trans/trans_rvb.c.inc
75
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
76
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
77
return gen_shifti(ctx, a, gen_bext);
78
}
79
80
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
81
+{
82
+ REQUIRE_EXT(ctx, RVB);
83
+ return gen_shift(ctx, a, gen_slo);
84
+}
85
+
86
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
87
+{
88
+ REQUIRE_EXT(ctx, RVB);
89
+ return gen_shifti(ctx, a, gen_slo);
90
+}
91
+
92
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
93
+{
94
+ REQUIRE_EXT(ctx, RVB);
95
+ return gen_shift(ctx, a, gen_sro);
96
+}
97
+
98
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
99
+{
100
+ REQUIRE_EXT(ctx, RVB);
101
+ return gen_shifti(ctx, a, gen_sro);
102
+}
103
+
104
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
105
{
106
REQUIRE_64BIT(ctx);
107
@@ -XXX,XX +XXX,XX @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
108
REQUIRE_EXT(ctx, RVB);
109
return gen_shiftw(ctx, a, gen_bext);
110
}
111
+
112
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
113
+{
114
+ REQUIRE_64BIT(ctx);
115
+ REQUIRE_EXT(ctx, RVB);
116
+ return gen_shiftw(ctx, a, gen_slo);
117
+}
118
+
119
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
120
+{
121
+ REQUIRE_64BIT(ctx);
122
+ REQUIRE_EXT(ctx, RVB);
123
+ return gen_shiftiw(ctx, a, gen_slo);
124
+}
125
+
126
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
127
+{
128
+ REQUIRE_64BIT(ctx);
129
+ REQUIRE_EXT(ctx, RVB);
130
+ return gen_shiftw(ctx, a, gen_sro);
131
+}
132
+
133
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
134
+{
135
+ REQUIRE_64BIT(ctx);
136
+ REQUIRE_EXT(ctx, RVB);
137
+ return gen_shiftiw(ctx, a, gen_sro);
138
+}
139
--
29
--
140
2.31.1
30
2.45.1
141
142
diff view generated by jsdifflib
[PULL 09/32] target/riscv: fix wfi exception behavior
[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
1
From: Jose Martins <josemartins90@gmail.com>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
The wfi exception trigger behavior should take into account user mode,
3
The current semihost exception number (16) is a reserved number (range
4
hstatus.vtw, and the fact the an wfi might raise different types of
4
[16-17]). The upcoming double trap specification uses that number for
5
exceptions depending on various factors:
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
6
9
7
If supervisor mode is not present:
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
8
11
9
- an illegal instruction exception should be generated if user mode
10
executes and wfi instruction and mstatus.tw = 1.
11
12
If supervisor mode is present:
13
14
- when a wfi instruction is executed, an illegal exception should be triggered
15
if either the current mode is user or the mode is supervisor and mstatus.tw is
16
set.
17
18
Plus, if the hypervisor extensions are enabled:
19
20
- a virtual instruction exception should be raised when a wfi is executed from
21
virtual-user or virtual-supervisor and hstatus.vtw is set.
22
23
Signed-off-by: Jose Martins <josemartins90@gmail.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
---
15
---
28
target/riscv/cpu_bits.h | 1 +
16
target/riscv/cpu_bits.h | 2 +-
29
target/riscv/op_helper.c | 11 ++++++++---
17
1 file changed, 1 insertion(+), 1 deletion(-)
30
2 files changed, 9 insertions(+), 3 deletions(-)
31
18
32
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
33
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/cpu_bits.h
21
--- a/target/riscv/cpu_bits.h
35
+++ b/target/riscv/cpu_bits.h
22
+++ b/target/riscv/cpu_bits.h
36
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
37
#define HSTATUS_HU 0x00000200
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
38
#define HSTATUS_VGEIN 0x0003F000
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
39
#define HSTATUS_VTVM 0x00100000
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
40
+#define HSTATUS_VTW 0x00200000
27
- RISCV_EXCP_SEMIHOST = 0x10,
41
#define HSTATUS_VTSR 0x00400000
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
42
#define HSTATUS_VSXL 0x300000000
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
43
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
44
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
45
index XXXXXXX..XXXXXXX 100644
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
46
--- a/target/riscv/op_helper.c
33
} RISCVException;
47
+++ b/target/riscv/op_helper.c
34
48
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
35
#define RISCV_EXCP_INT_FLAG 0x80000000
49
void helper_wfi(CPURISCVState *env)
50
{
51
CPUState *cs = env_cpu(env);
52
+ bool rvs = riscv_has_ext(env, RVS);
53
+ bool prv_u = env->priv == PRV_U;
54
+ bool prv_s = env->priv == PRV_S;
55
56
- if ((env->priv == PRV_S &&
57
- get_field(env->mstatus, MSTATUS_TW)) ||
58
- riscv_cpu_virt_enabled(env)) {
59
+ if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
60
+ (rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
61
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
62
+ } else if (riscv_cpu_virt_enabled(env) && (prv_u ||
63
+ (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
64
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
65
} else {
66
cs->halted = 1;
67
--
36
--
68
2.31.1
37
2.45.1
69
38
70
39
diff view generated by jsdifflib
[PULL 24/32] target/riscv: rvb: single-bit instructions
[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
Message-id: 20210505160620.15723-10-frank.chang@sifive.com
7
allow it we'll error out and never boot.
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
35
---
10
target/riscv/insn32.decode | 17 +++++
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
11
target/riscv/translate.c | 61 ++++++++++++++++
37
1 file changed, 8 insertions(+), 4 deletions(-)
12
target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
13
3 files changed, 175 insertions(+)
14
38
15
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
16
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn32.decode
41
--- a/target/riscv/kvm/kvm-cpu.c
18
+++ b/target/riscv/insn32.decode
42
+++ b/target/riscv/kvm/kvm-cpu.c
19
@@ -XXX,XX +XXX,XX @@ min 0000101 .......... 100 ..... 0110011 @r
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
20
minu 0000101 .......... 101 ..... 0110011 @r
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
21
max 0000101 .......... 110 ..... 0110011 @r
45
ret = kvm_set_one_reg(cs, id, &reg);
22
maxu 0000101 .......... 111 ..... 0110011 @r
46
if (ret != 0) {
23
+bset 0010100 .......... 001 ..... 0110011 @r
47
- error_report("Unable to %s extension %s in KVM, error %d",
24
+bclr 0100100 .......... 001 ..... 0110011 @r
48
- reg ? "enable" : "disable",
25
+binv 0110100 .......... 001 ..... 0110011 @r
49
- multi_ext_cfg->name, ret);
26
+bext 0100100 .......... 101 ..... 0110011 @r
50
- exit(EXIT_FAILURE);
27
+
51
+ if (!reg && ret == -EINVAL) {
28
+bseti 00101. ........... 001 ..... 0010011 @sh
52
+ warn_report("KVM cannot disable extension %s",
29
+bclri 01001. ........... 001 ..... 0010011 @sh
53
+ multi_ext_cfg->name);
30
+binvi 01101. ........... 001 ..... 0010011 @sh
54
+ } else {
31
+bexti 01001. ........... 101 ..... 0010011 @sh
55
+ error_report("Unable to enable extension %s in KVM, error %d",
32
56
+ multi_ext_cfg->name, ret);
33
# *** RV64B Standard Extension (in addition to RV32B) ***
57
+ exit(EXIT_FAILURE);
34
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
58
+ }
35
@@ -XXX,XX +XXX,XX @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
59
}
36
60
}
37
packw 0000100 .......... 100 ..... 0111011 @r
38
packuw 0100100 .......... 100 ..... 0111011 @r
39
+bsetw 0010100 .......... 001 ..... 0111011 @r
40
+bclrw 0100100 .......... 001 ..... 0111011 @r
41
+binvw 0110100 .......... 001 ..... 0111011 @r
42
+bextw 0100100 .......... 101 ..... 0111011 @r
43
+
44
+bsetiw 0010100 .......... 001 ..... 0011011 @sh5
45
+bclriw 0100100 .......... 001 ..... 0011011 @sh5
46
+binviw 0110100 .......... 001 ..... 0011011 @sh5
47
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/translate.c
50
+++ b/target/riscv/translate.c
51
@@ -XXX,XX +XXX,XX @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
52
tcg_temp_free(t);
53
}
61
}
54
55
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
56
+{
57
+ tcg_gen_movi_tl(ret, 1);
58
+ tcg_gen_shl_tl(ret, ret, shamt);
59
+}
60
+
61
+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
62
+{
63
+ TCGv t = tcg_temp_new();
64
+
65
+ gen_sbop_mask(t, shamt);
66
+ tcg_gen_or_tl(ret, arg1, t);
67
+
68
+ tcg_temp_free(t);
69
+}
70
+
71
+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
72
+{
73
+ TCGv t = tcg_temp_new();
74
+
75
+ gen_sbop_mask(t, shamt);
76
+ tcg_gen_andc_tl(ret, arg1, t);
77
+
78
+ tcg_temp_free(t);
79
+}
80
+
81
+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
82
+{
83
+ TCGv t = tcg_temp_new();
84
+
85
+ gen_sbop_mask(t, shamt);
86
+ tcg_gen_xor_tl(ret, arg1, t);
87
+
88
+ tcg_temp_free(t);
89
+}
90
+
91
+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
92
+{
93
+ tcg_gen_shr_tl(ret, arg1, shamt);
94
+ tcg_gen_andi_tl(ret, ret, 1);
95
+}
96
+
97
static void gen_ctzw(TCGv ret, TCGv arg1)
98
{
99
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
100
@@ -XXX,XX +XXX,XX @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
101
return true;
102
}
103
104
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
105
+ void(*func)(TCGv, TCGv, TCGv))
106
+{
107
+ TCGv source1 = tcg_temp_new();
108
+ TCGv source2 = tcg_temp_new();
109
+
110
+ gen_get_gpr(source1, a->rs1);
111
+ gen_get_gpr(source2, a->rs2);
112
+
113
+ tcg_gen_andi_tl(source2, source2, 31);
114
+ (*func)(source1, source1, source2);
115
+ tcg_gen_ext32s_tl(source1, source1);
116
+
117
+ gen_set_gpr(a->rd, source1);
118
+ tcg_temp_free(source1);
119
+ tcg_temp_free(source2);
120
+ return true;
121
+}
122
+
123
static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
124
void(*func)(TCGv, TCGv, TCGv))
125
{
126
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
127
index XXXXXXX..XXXXXXX 100644
128
--- a/target/riscv/insn_trans/trans_rvb.c.inc
129
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
130
@@ -XXX,XX +XXX,XX @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
131
return gen_unary(ctx, a, tcg_gen_ext16s_tl);
132
}
133
134
+static bool trans_bset(DisasContext *ctx, arg_bset *a)
135
+{
136
+ REQUIRE_EXT(ctx, RVB);
137
+ return gen_shift(ctx, a, gen_bset);
138
+}
139
+
140
+static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
141
+{
142
+ REQUIRE_EXT(ctx, RVB);
143
+ return gen_shifti(ctx, a, gen_bset);
144
+}
145
+
146
+static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
147
+{
148
+ REQUIRE_EXT(ctx, RVB);
149
+ return gen_shift(ctx, a, gen_bclr);
150
+}
151
+
152
+static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
153
+{
154
+ REQUIRE_EXT(ctx, RVB);
155
+ return gen_shifti(ctx, a, gen_bclr);
156
+}
157
+
158
+static bool trans_binv(DisasContext *ctx, arg_binv *a)
159
+{
160
+ REQUIRE_EXT(ctx, RVB);
161
+ return gen_shift(ctx, a, gen_binv);
162
+}
163
+
164
+static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
165
+{
166
+ REQUIRE_EXT(ctx, RVB);
167
+ return gen_shifti(ctx, a, gen_binv);
168
+}
169
+
170
+static bool trans_bext(DisasContext *ctx, arg_bext *a)
171
+{
172
+ REQUIRE_EXT(ctx, RVB);
173
+ return gen_shift(ctx, a, gen_bext);
174
+}
175
+
176
+static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
177
+{
178
+ REQUIRE_EXT(ctx, RVB);
179
+ return gen_shifti(ctx, a, gen_bext);
180
+}
181
+
182
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
183
{
184
REQUIRE_64BIT(ctx);
185
@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
186
REQUIRE_EXT(ctx, RVB);
187
return gen_arith(ctx, a, gen_packuw);
188
}
189
+
190
+static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
191
+{
192
+ REQUIRE_64BIT(ctx);
193
+ REQUIRE_EXT(ctx, RVB);
194
+ return gen_shiftw(ctx, a, gen_bset);
195
+}
196
+
197
+static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
198
+{
199
+ REQUIRE_64BIT(ctx);
200
+ REQUIRE_EXT(ctx, RVB);
201
+ return gen_shiftiw(ctx, a, gen_bset);
202
+}
203
+
204
+static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
205
+{
206
+ REQUIRE_64BIT(ctx);
207
+ REQUIRE_EXT(ctx, RVB);
208
+ return gen_shiftw(ctx, a, gen_bclr);
209
+}
210
+
211
+static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
212
+{
213
+ REQUIRE_64BIT(ctx);
214
+ REQUIRE_EXT(ctx, RVB);
215
+ return gen_shiftiw(ctx, a, gen_bclr);
216
+}
217
+
218
+static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
219
+{
220
+ REQUIRE_64BIT(ctx);
221
+ REQUIRE_EXT(ctx, RVB);
222
+ return gen_shiftw(ctx, a, gen_binv);
223
+}
224
+
225
+static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
226
+{
227
+ REQUIRE_64BIT(ctx);
228
+ REQUIRE_EXT(ctx, RVB);
229
+ return gen_shiftiw(ctx, a, gen_binv);
230
+}
231
+
232
+static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
233
+{
234
+ REQUIRE_64BIT(ctx);
235
+ REQUIRE_EXT(ctx, RVB);
236
+ return gen_shiftw(ctx, a, gen_bext);
237
+}
238
--
62
--
239
2.31.1
63
2.45.1
240
241
diff view generated by jsdifflib
[PULL 22/32] target/riscv: rvb: sign-extend instructions
[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
5.7.12, "Match Control Type 6":
6
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
24
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
7
Message-id: 20210505160620.15723-8-frank.chang@sifive.com
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
30
---
10
target/riscv/insn32.decode | 3 +++
31
target/riscv/cpu_helper.c | 1 +
11
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
32
target/riscv/debug.c | 3 +++
12
2 files changed, 15 insertions(+)
33
2 files changed, 4 insertions(+)
13
34
14
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/insn32.decode
37
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/insn32.decode
38
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
19
clz 011000 000000 ..... 001 ..... 0010011 @r2
40
tval = env->bins;
20
ctz 011000 000001 ..... 001 ..... 0010011 @r2
41
break;
21
cpop 011000 000010 ..... 001 ..... 0010011 @r2
42
case RISCV_EXCP_BREAKPOINT:
22
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
43
+ tval = env->badaddr;
23
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
44
if (cs->watchpoint_hit) {
24
+
45
tval = cs->watchpoint_hit->hitaddr;
25
andn 0100000 .......... 111 ..... 0110011 @r
46
cs->watchpoint_hit = NULL;
26
orn 0100000 .......... 110 ..... 0110011 @r
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
27
xnor 0100000 .......... 100 ..... 0110011 @r
28
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
29
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
30
--- a/target/riscv/insn_trans/trans_rvb.c.inc
49
--- a/target/riscv/debug.c
31
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
50
+++ b/target/riscv/debug.c
32
@@ -XXX,XX +XXX,XX @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
33
return gen_arith(ctx, a, tcg_gen_umax_tl);
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
34
}
53
/* check U/S/M bit against current privilege level */
35
54
if ((ctrl >> 3) & BIT(env->priv)) {
36
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
55
+ env->badaddr = pc;
37
+{
56
return true;
38
+ REQUIRE_EXT(ctx, RVB);
57
}
39
+ return gen_unary(ctx, a, tcg_gen_ext8s_tl);
58
}
40
+}
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
41
+
60
if (env->virt_enabled) {
42
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
61
/* check VU/VS bit against current privilege level */
43
+{
62
if ((ctrl >> 23) & BIT(env->priv)) {
44
+ REQUIRE_EXT(ctx, RVB);
63
+ env->badaddr = pc;
45
+ return gen_unary(ctx, a, tcg_gen_ext16s_tl);
64
return true;
46
+}
65
}
47
+
66
} else {
48
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
67
/* check U/S/M bit against current privilege level */
49
{
68
if ((ctrl >> 3) & BIT(env->priv)) {
50
REQUIRE_64BIT(ctx);
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
51
--
73
--
52
2.31.1
74
2.45.1
53
54
diff view generated by jsdifflib
[PULL 21/32] target/riscv: rvb: min/max instructions
[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
Privileged spec section 4.1.9 mentions:
4
5
"When a trap is taken into S-mode, stval is written with
6
exception-specific information to assist software in handling the trap.
7
(...)
8
9
If stval is written with a nonzero value when a breakpoint,
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
instruction fetch, load, or store, then stval will contain the faulting
12
virtual address."
13
14
A similar text is found for mtval in section 3.1.16.
15
16
Setting mtval/stval in this scenario is optional, but some softwares read
17
these regs when handling ebreaks.
18
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
20
'tval' during riscv_do_cpu_interrrupt().
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
7
Message-id: 20210505160620.15723-7-frank.chang@sifive.com
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
28
---
10
target/riscv/insn32.decode | 4 ++++
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
11
target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
30
1 file changed, 2 insertions(+)
12
2 files changed, 28 insertions(+)
13
31
14
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
15
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/insn32.decode
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
17
+++ b/target/riscv/insn32.decode
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
18
@@ -XXX,XX +XXX,XX @@ xnor 0100000 .......... 100 ..... 0110011 @r
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
19
pack 0000100 .......... 100 ..... 0110011 @r
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
20
packu 0100100 .......... 100 ..... 0110011 @r
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
21
packh 0000100 .......... 111 ..... 0110011 @r
39
} else {
22
+min 0000101 .......... 100 ..... 0110011 @r
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
23
+minu 0000101 .......... 101 ..... 0110011 @r
41
+ offsetof(CPURISCVState, badaddr));
24
+max 0000101 .......... 110 ..... 0110011 @r
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
25
+maxu 0000101 .......... 111 ..... 0110011 @r
43
}
26
44
return true;
27
# *** RV64B Standard Extension (in addition to RV32B) ***
28
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
29
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/insn_trans/trans_rvb.c.inc
32
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
33
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
34
return gen_arith(ctx, a, gen_packh);
35
}
36
37
+static bool trans_min(DisasContext *ctx, arg_min *a)
38
+{
39
+ REQUIRE_EXT(ctx, RVB);
40
+ return gen_arith(ctx, a, tcg_gen_smin_tl);
41
+}
42
+
43
+static bool trans_max(DisasContext *ctx, arg_max *a)
44
+{
45
+ REQUIRE_EXT(ctx, RVB);
46
+ return gen_arith(ctx, a, tcg_gen_smax_tl);
47
+}
48
+
49
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
50
+{
51
+ REQUIRE_EXT(ctx, RVB);
52
+ return gen_arith(ctx, a, tcg_gen_umin_tl);
53
+}
54
+
55
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
56
+{
57
+ REQUIRE_EXT(ctx, RVB);
58
+ return gen_arith(ctx, a, tcg_gen_umax_tl);
59
+}
60
+
61
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
62
{
63
REQUIRE_64BIT(ctx);
64
--
45
--
65
2.31.1
46
2.45.1
66
67
diff view generated by jsdifflib
[PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line
[PULL 10/28] target/riscv: Add support for Zve32x extension
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
enable B-extension.
4
Zve32x, since Zve32f depends on Zve32x.
5
5
6
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Signed-off-by: Frank Chang <frank.chang@sifive.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
target/riscv/cpu.h | 1 +
13
target/riscv/cpu_cfg.h | 1 +
14
target/riscv/cpu.c | 4 ++++
14
target/riscv/cpu.c | 2 ++
15
2 files changed, 5 insertions(+)
15
target/riscv/cpu_helper.c | 2 +-
16
target/riscv/csr.c | 2 +-
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
19
6 files changed, 15 insertions(+), 12 deletions(-)
16
20
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
18
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.h
23
--- a/target/riscv/cpu_cfg.h
20
+++ b/target/riscv/cpu.h
24
+++ b/target/riscv/cpu_cfg.h
21
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
bool ext_f;
26
bool ext_zhinx;
23
bool ext_d;
27
bool ext_zhinxmin;
24
bool ext_c;
28
bool ext_zve32f;
25
+ bool ext_b;
29
+ bool ext_zve32x;
26
bool ext_s;
30
bool ext_zve64f;
27
bool ext_u;
31
bool ext_zve64d;
28
bool ext_h;
32
bool ext_zvbb;
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
30
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu.c
35
--- a/target/riscv/cpu.c
32
+++ b/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
33
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
34
if (cpu->cfg.ext_h) {
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
35
target_misa |= RVH;
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
36
}
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
37
+ if (cpu->cfg.ext_b) {
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
38
+ target_misa |= RVB;
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
59
*cs_base = 0;
60
61
- if (cpu->cfg.ext_zve32f) {
62
+ if (cpu->cfg.ext_zve32x) {
63
/*
64
* If env->vl equals to VLMAX, we can use generic vector operation
65
* expanders (GVEC) to accerlate the vector operations.
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
76
#if !defined(CONFIG_USER_ONLY)
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
78
return RISCV_EXCP_ILLEGAL_INST;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/tcg/tcg-cpu.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
84
return;
85
}
86
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
89
- return;
90
+ /* The Zve32f extension depends on the Zve32x extension */
91
+ if (cpu->cfg.ext_zve32f) {
92
+ if (!riscv_has_ext(env, RVF)) {
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
94
+ return;
39
+ }
95
+ }
40
if (cpu->cfg.ext_v) {
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
41
target_misa |= RVV;
97
}
42
if (!is_power_of_2(cpu->cfg.vlen)) {
98
43
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
99
if (cpu->cfg.ext_zvfh) {
44
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
45
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
46
/* This is experimental so mark with 'x-' */
102
}
47
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
103
48
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
104
- /*
49
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
105
- * In principle Zve*x would also suffice here, were they supported
50
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
106
- * in qemu
107
- */
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
112
error_setg(errp,
113
"Vector crypto extensions require V or Zve* extensions");
114
return;
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
116
index XXXXXXX..XXXXXXX 100644
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
120
{
121
TCGv s1, dst;
122
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
125
return false;
126
}
127
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
129
{
130
TCGv dst;
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
135
}
136
51
--
137
--
52
2.31.1
138
2.45.1
53
54
diff view generated by jsdifflib
[PULL 07/32] hw/riscv: Use macros for BIOS image names
[PULL 11/28] target/riscv: Add support for Zve64x extension
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
The OpenSBI BIOS image names are used by many RISC-V machines.
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
4
Let's define macros for them.
4
enabling Zve64x enables Zve32x according to their dependency.
5
5
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Max Chou <max.chou@sifive.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
13
---
11
include/hw/riscv/boot.h | 5 +++++
14
target/riscv/cpu_cfg.h | 1 +
12
hw/riscv/sifive_u.c | 6 ++----
15
target/riscv/cpu.c | 2 ++
13
hw/riscv/spike.c | 6 ++----
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
14
hw/riscv/virt.c | 6 ++----
17
3 files changed, 14 insertions(+), 6 deletions(-)
15
4 files changed, 11 insertions(+), 12 deletions(-)
16
18
17
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/boot.h
21
--- a/target/riscv/cpu_cfg.h
20
+++ b/include/hw/riscv/boot.h
22
+++ b/target/riscv/cpu_cfg.h
21
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
#include "hw/loader.h"
24
bool ext_zve32x;
23
#include "hw/riscv/riscv_hart.h"
25
bool ext_zve64f;
24
26
bool ext_zve64d;
25
+#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
27
+ bool ext_zve64x;
26
+#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
28
bool ext_zvbb;
27
+#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
29
bool ext_zvbc;
28
+#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
30
bool ext_zvkb;
29
+
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
30
bool riscv_is_32bit(RISCVHartArrayState *harts);
31
32
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
33
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
34
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/riscv/sifive_u.c
33
--- a/target/riscv/cpu.c
36
+++ b/hw/riscv/sifive_u.c
34
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
38
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
39
if (riscv_is_32bit(&s->soc.u_cpus)) {
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
40
firmware_end_addr = riscv_find_and_load_firmware(machine,
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
41
- "opensbi-riscv32-generic-fw_dynamic.bin",
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
42
- start_addr, NULL);
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
43
+ RISCV32_BIOS_BIN, start_addr, NULL);
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
44
} else {
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
45
firmware_end_addr = riscv_find_and_load_firmware(machine,
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
- "opensbi-riscv64-generic-fw_dynamic.bin",
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
47
- start_addr, NULL);
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
48
+ RISCV64_BIOS_BIN, start_addr, NULL);
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/tcg/tcg-cpu.c
54
+++ b/target/riscv/tcg/tcg-cpu.c
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
56
57
/* The Zve64d extension depends on the Zve64f extension */
58
if (cpu->cfg.ext_zve64d) {
59
+ if (!riscv_has_ext(env, RVD)) {
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
61
+ return;
62
+ }
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
49
}
64
}
50
65
51
if (machine->kernel_filename) {
66
- /* The Zve64f extension depends on the Zve32f extension */
52
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
53
index XXXXXXX..XXXXXXX 100644
68
if (cpu->cfg.ext_zve64f) {
54
--- a/hw/riscv/spike.c
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
55
+++ b/hw/riscv/spike.c
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
56
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
57
*/
58
if (riscv_is_32bit(&s->soc[0])) {
59
firmware_end_addr = riscv_find_and_load_firmware(machine,
60
- "opensbi-riscv32-generic-fw_dynamic.elf",
61
- memmap[SPIKE_DRAM].base,
62
+ RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
63
htif_symbol_callback);
64
} else {
65
firmware_end_addr = riscv_find_and_load_firmware(machine,
66
- "opensbi-riscv64-generic-fw_dynamic.elf",
67
- memmap[SPIKE_DRAM].base,
68
+ RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
69
htif_symbol_callback);
70
}
71
}
71
72
72
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
73
index XXXXXXX..XXXXXXX 100644
74
- error_setg(errp, "Zve64d/V extensions require D extension");
74
--- a/hw/riscv/virt.c
75
- return;
75
+++ b/hw/riscv/virt.c
76
+ /* The Zve64x extension depends on the Zve32x extension */
76
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
77
+ if (cpu->cfg.ext_zve64x) {
77
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
78
if (riscv_is_32bit(&s->soc[0])) {
79
firmware_end_addr = riscv_find_and_load_firmware(machine,
80
- "opensbi-riscv32-generic-fw_dynamic.bin",
81
- start_addr, NULL);
82
+ RISCV32_BIOS_BIN, start_addr, NULL);
83
} else {
84
firmware_end_addr = riscv_find_and_load_firmware(machine,
85
- "opensbi-riscv64-generic-fw_dynamic.bin",
86
- start_addr, NULL);
87
+ RISCV64_BIOS_BIN, start_addr, NULL);
88
}
79
}
89
80
90
if (machine->kernel_filename) {
81
/* The Zve32f extension depends on the Zve32x extension */
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
83
return;
84
}
85
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
88
error_setg(
89
errp,
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
92
return;
93
}
94
91
--
95
--
92
2.31.1
96
2.45.1
93
94
diff view generated by jsdifflib
[PULL 19/32] target/riscv: rvb: logic-with-negate
[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
In current implementation, the gdbstub allows reading vector registers
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
only if V extension is supported. However, all vector extensions and
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
vector crypto extensions have the vector registers and they all depend
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
Message-id: 20210505160620.15723-5-frank.chang@sifive.com
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
13
---
10
target/riscv/insn32.decode | 3 +++
14
target/riscv/gdbstub.c | 2 +-
11
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
2 files changed, 21 insertions(+)
13
16
14
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/insn32.decode
19
--- a/target/riscv/gdbstub.c
17
+++ b/target/riscv/insn32.decode
20
+++ b/target/riscv/gdbstub.c
18
@@ -XXX,XX +XXX,XX @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
19
clz 011000 000000 ..... 001 ..... 0010011 @r2
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
20
ctz 011000 000001 ..... 001 ..... 0010011 @r2
23
0);
21
cpop 011000 000010 ..... 001 ..... 0010011 @r2
24
}
22
+andn 0100000 .......... 111 ..... 0110011 @r
25
- if (env->misa_ext & RVV) {
23
+orn 0100000 .......... 110 ..... 0110011 @r
26
+ if (cpu->cfg.ext_zve32x) {
24
+xnor 0100000 .......... 100 ..... 0110011 @r
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
25
28
riscv_gdb_set_vector,
26
# *** RV64B Standard Extension (in addition to RV32B) ***
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
27
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
28
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/riscv/insn_trans/trans_rvb.c.inc
31
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
32
@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
33
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
34
}
35
36
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
37
+{
38
+ REQUIRE_EXT(ctx, RVB);
39
+ return gen_arith(ctx, a, tcg_gen_andc_tl);
40
+}
41
+
42
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
43
+{
44
+ REQUIRE_EXT(ctx, RVB);
45
+ return gen_arith(ctx, a, tcg_gen_orc_tl);
46
+}
47
+
48
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
49
+{
50
+ REQUIRE_EXT(ctx, RVB);
51
+ return gen_arith(ctx, a, tcg_gen_eqv_tl);
52
+}
53
+
54
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
55
{
56
REQUIRE_64BIT(ctx);
57
--
30
--
58
2.31.1
31
2.45.1
59
60
diff view generated by jsdifflib
[PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot
[PULL 13/28] target/riscv: Fix the element agnostic function problem
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
At present the Microchip Icicle Kit machine only supports using
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
'-bios' to load the HSS, and does not support '-kernel' for direct
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
kernel booting just like other RISC-V machines do. One has to use
5
agnostic policy.
6
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
7
This is not so convenient.
8
6
9
Adding '-kernel' support together with the existing '-bios', we
7
However, this function can't deal the big endian situation. This patch fixes
10
follow the following table to select which payload we execute:
8
the problem by adding handling of such case.
11
9
12
-bios | -kernel | payload
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
13
------+------------+--------
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
14
N | N | HSS
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Y | don't care | HSS
13
Cc: qemu-stable <qemu-stable@nongnu.org>
16
N | Y | kernel
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
17
18
This ensures backwards compatibility with how we used to expose
19
'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
20
must be present to provide a valid device tree for the board,
21
as we don't generate device tree.
22
23
When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
24
is used to boot a payload like U-Boot or OS kernel directly.
25
26
Documentation is updated to describe the direct kernel boot. Note
27
as of today there is still no PolarFire SoC support in the upstream
28
Linux kernel hence the document does not include instructions for
29
that. It will be updated in the future.
30
31
Signed-off-by: Bin Meng <bin.meng@windriver.com>
32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
33
Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
16
---
36
docs/system/riscv/microchip-icicle-kit.rst | 30 ++++++--
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
37
hw/riscv/microchip_pfsoc.c | 81 +++++++++++++++++++++-
18
1 file changed, 22 insertions(+)
38
2 files changed, 103 insertions(+), 8 deletions(-)
39
19
40
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
41
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
42
--- a/docs/system/riscv/microchip-icicle-kit.rst
22
--- a/target/riscv/vector_internals.c
43
+++ b/docs/system/riscv/microchip-icicle-kit.rst
23
+++ b/target/riscv/vector_internals.c
44
@@ -XXX,XX +XXX,XX @@ Boot options
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
45
25
if (tot - cnt == 0) {
46
The ``microchip-icicle-kit`` machine can start using the standard -bios
26
return ;
47
functionality for loading its BIOS image, aka Hart Software Services (HSS_).
48
-HSS loads the second stage bootloader U-Boot from an SD card. It does not
49
-support direct kernel loading via the -kernel option. One has to load kernel
50
-from U-Boot.
51
+HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
52
+can be loaded from U-Boot. It also supports direct kernel booting via the
53
+-kernel option along with the device tree blob via -dtb. When direct kernel
54
+boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload
55
+like U-Boot or OS kernel directly.
56
+
57
+The user provided DTB should have the following requirements:
58
+
59
+* The /cpus node should contain at least one subnode for E51 and the number
60
+ of subnodes should match QEMU's ``-smp`` option
61
+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
62
+* Should contain a node for the CLINT device with a compatible string
63
+ "riscv,clint0"
64
+
65
+QEMU follows below truth table to select which payload to execute:
66
+
67
+===== ========== =======
68
+-bios -kernel payload
69
+===== ========== =======
70
+ N N HSS
71
+ Y don't care HSS
72
+ N Y kernel
73
+===== ========== =======
74
75
The memory is set to 1537 MiB by default which is the minimum required high
76
memory size by HSS. A sanity check on ram size is performed in the machine
77
init routine to prompt user to increase the RAM size to > 1537 MiB when less
78
than 1537 MiB ram is detected.
79
80
-Boot the machine
81
-----------------
82
+Running HSS
83
+-----------
84
85
HSS 2020.12 release is tested at the time of writing. To build an HSS image
86
that can be booted by the ``microchip-icicle-kit`` machine, type the following
87
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/riscv/microchip_pfsoc.c
90
+++ b/hw/riscv/microchip_pfsoc.c
91
@@ -XXX,XX +XXX,XX @@
92
#include "hw/riscv/microchip_pfsoc.h"
93
#include "hw/intc/sifive_clint.h"
94
#include "hw/intc/sifive_plic.h"
95
+#include "sysemu/device_tree.h"
96
#include "sysemu/sysemu.h"
97
98
/*
99
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
100
MemoryRegion *mem_high = g_new(MemoryRegion, 1);
101
MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
102
uint64_t mem_high_size;
103
+ hwaddr firmware_load_addr;
104
+ const char *firmware_name;
105
+ bool kernel_as_payload = false;
106
+ target_ulong firmware_end_addr, kernel_start_addr;
107
+ uint64_t kernel_entry;
108
+ uint32_t fdt_load_addr;
109
DriveInfo *dinfo = drive_get_next(IF_SD);
110
111
/* Sanity check on RAM size */
112
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
113
memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
114
mem_high_alias);
115
116
- /* Load the firmware */
117
- riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
118
-
119
/* Attach an SD card */
120
if (dinfo) {
121
CadenceSDHCIState *sdhci = &(s->soc.sdhci);
122
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
123
&error_fatal);
124
qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
125
}
27
}
126
+
28
+
127
+ /*
29
+ if (HOST_BIG_ENDIAN) {
128
+ * We follow the following table to select which payload we execute.
30
+ /*
129
+ *
31
+ * Deal the situation when the elements are insdie
130
+ * -bios | -kernel | payload
32
+ * only one uint64 block including setting the
131
+ * -------+------------+--------
33
+ * masked-off element.
132
+ * N | N | HSS
34
+ */
133
+ * Y | don't care | HSS
35
+ if (((tot - 1) ^ cnt) < 8) {
134
+ * N | Y | kernel
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
135
+ *
37
+ return;
136
+ * This ensures backwards compatibility with how we used to expose -bios
137
+ * to users but allows them to run through direct kernel booting as well.
138
+ *
139
+ * When -kernel is used for direct boot, -dtb must be present to provide
140
+ * a valid device tree for the board, as we don't generate device tree.
141
+ */
142
+
143
+ if (machine->kernel_filename && machine->dtb) {
144
+ int fdt_size;
145
+ machine->fdt = load_device_tree(machine->dtb, &fdt_size);
146
+ if (!machine->fdt) {
147
+ error_report("load_device_tree() failed");
148
+ exit(1);
149
+ }
38
+ }
150
+
39
+ /*
151
+ firmware_name = RISCV64_BIOS_BIN;
40
+ * Otherwise, at least cross two uint64_t blocks.
152
+ firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
41
+ * Set first unaligned block.
153
+ kernel_as_payload = true;
42
+ */
43
+ if (cnt % 8 != 0) {
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
47
+ }
48
+ /* Set other 64bit aligend blocks */
154
+ }
49
+ }
155
+
50
memset(base + cnt, -1, tot - cnt);
156
+ if (!kernel_as_payload) {
157
+ firmware_name = BIOS_FILENAME;
158
+ firmware_load_addr = RESET_VECTOR;
159
+ }
160
+
161
+ /* Load the firmware */
162
+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
163
+ firmware_load_addr, NULL);
164
+
165
+ if (kernel_as_payload) {
166
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
167
+ firmware_end_addr);
168
+
169
+ kernel_entry = riscv_load_kernel(machine->kernel_filename,
170
+ kernel_start_addr, NULL);
171
+
172
+ if (machine->initrd_filename) {
173
+ hwaddr start;
174
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
175
+ machine->ram_size, kernel_entry,
176
+ &start);
177
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
178
+ "linux,initrd-start", start);
179
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
180
+ "linux,initrd-end", end);
181
+ }
182
+
183
+ if (machine->kernel_cmdline) {
184
+ qemu_fdt_setprop_string(machine->fdt, "/chosen",
185
+ "bootargs", machine->kernel_cmdline);
186
+ }
187
+
188
+ /* Compute the fdt load address in dram */
189
+ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
190
+ machine->ram_size, machine->fdt);
191
+ /* Load the reset vector */
192
+ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
193
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
194
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
195
+ kernel_entry, fdt_load_addr, machine->fdt);
196
+ }
197
}
51
}
198
52
199
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
200
--
53
--
201
2.31.1
54
2.45.1
202
203
diff view generated by jsdifflib
[PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp
[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
1
From: Changbin Du <changbin.du@gmail.com>
1
From: Yangyu Chen <cyy@cyyself.name>
2
2
3
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
the output of CSR mtval/stval.
4
enable zvkb through the config. This patch gets this fixed.
5
5
6
Signed-off-by: Changbin Du <changbin.du@gmail.com>
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
target/riscv/cpu.c | 7 +++++--
16
target/riscv/cpu.c | 2 +-
13
1 file changed, 5 insertions(+), 2 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
18
15
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.c
21
--- a/target/riscv/cpu.c
18
+++ b/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
20
if (riscv_has_ext(env, RVH)) {
24
/* Vector cryptography extensions */
21
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
22
}
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
23
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
24
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
25
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
26
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
27
if (riscv_has_ext(env, RVH)) {
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
28
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
29
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
30
}
31
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
32
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
33
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
34
#endif
35
36
for (i = 0; i < 32; i++) {
37
--
32
--
38
2.31.1
33
2.45.1
39
34
40
35
diff view generated by jsdifflib
[PULL 17/32] target/riscv: rvb: count leading/trailing zeros
[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
In this patch, we modify the decoder to be a freely composable data
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
structure instead of a hardcoded one. It can be dynamically builded up
5
according to the extensions.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
20
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20210505160620.15723-3-frank.chang@sifive.com
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
28
---
10
target/riscv/cpu.h | 1 +
29
target/riscv/cpu.h | 1 +
11
target/riscv/insn32.decode | 11 ++++++-
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
12
target/riscv/translate.c | 38 +++++++++++++++++++++
31
target/riscv/cpu.c | 1 +
13
target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
14
4 files changed, 93 insertions(+), 1 deletion(-)
33
target/riscv/translate.c | 31 +++++++++++++++----------------
15
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
34
5 files changed, 47 insertions(+), 16 deletions(-)
16
35
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
18
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.h
38
--- a/target/riscv/cpu.h
20
+++ b/target/riscv/cpu.h
39
+++ b/target/riscv/cpu.h
21
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
22
#define RVS RV('S')
41
uint32_t pmu_avail_ctrs;
23
#define RVU RV('U')
42
/* Mapping of events to counters */
24
#define RVH RV('H')
43
GHashTable *pmu_event_ctr_map;
25
+#define RVB RV('B')
44
+ const GPtrArray *decoders;
26
45
};
27
/* S extension denotes that Supervisor mode exists, however it is possible
46
28
to have a core that support S mode but does not have an MMU and there
47
/**
29
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
30
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/insn32.decode
50
--- a/target/riscv/tcg/tcg-cpu.h
32
+++ b/target/riscv/insn32.decode
51
+++ b/target/riscv/tcg/tcg-cpu.h
33
@@ -XXX,XX +XXX,XX @@
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
34
&i imm rs1 rd
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
35
&j imm rd
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
36
&r rd rs1 rs2
55
37
+&r2 rd rs1
56
+struct DisasContext;
38
&s imm rs1 rs2
57
+struct RISCVCPUConfig;
39
&u imm rd
58
+typedef struct RISCVDecoder {
40
&shift shamt rs1 rd
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
41
@@ -XXX,XX +XXX,XX @@
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
42
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
61
+} RISCVDecoder;
43
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
44
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
45
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
46
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
47
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
48
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
49
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
50
@@ -XXX,XX +XXX,XX @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
51
vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
52
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
53
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
54
+
62
+
55
+# *** RV32B Standard Extension ***
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
56
+clz 011000 000000 ..... 001 ..... 0010011 @r2
57
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
58
+
64
+
59
+# *** RV64B Standard Extension (in addition to RV32B) ***
65
+extern const size_t decoder_table_size;
60
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
66
+
61
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
67
+extern const RISCVDecoder decoder_table[];
68
+
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
70
+
71
#endif
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/riscv/cpu.c
75
+++ b/target/riscv/cpu.c
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
77
error_propagate(errp, local_err);
78
return;
79
}
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
81
} else if (kvm_enabled()) {
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
83
if (local_err != NULL) {
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/riscv/tcg/tcg-cpu.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
89
}
90
}
91
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
93
+{
94
+ GPtrArray *dynamic_decoders;
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
97
+ if (decoder_table[i].guard_func &&
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
99
+ g_ptr_array_add(dynamic_decoders,
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
101
+ }
102
+ }
103
+
104
+ cpu->decoders = dynamic_decoders;
105
+}
106
+
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
108
{
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
62
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
63
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
64
--- a/target/riscv/translate.c
112
--- a/target/riscv/translate.c
65
+++ b/target/riscv/translate.c
113
+++ b/target/riscv/translate.c
66
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
114
@@ -XXX,XX +XXX,XX @@
67
return true;
115
#include "exec/helper-info.c.inc"
116
#undef HELPER_H
117
118
+#include "tcg/tcg-cpu.h"
119
+
120
/* global register indices */
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
124
/* FRM is known to contain a valid value. */
125
bool frm_valid;
126
bool insn_start_updated;
127
+ const GPtrArray *decoders;
128
} DisasContext;
129
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
132
return (first_word & 3) == 3 ? 4 : 2;
68
}
133
}
69
134
70
+static void gen_ctzw(TCGv ret, TCGv arg1)
135
+const RISCVDecoder decoder_table[] = {
71
+{
136
+ { always_true_p, decode_insn32 },
72
+ tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
137
+ { has_xthead_p, decode_xthead},
73
+ tcg_gen_ctzi_tl(ret, ret, 64);
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
74
+}
139
+};
75
+
140
+
76
+static void gen_clzw(TCGv ret, TCGv arg1)
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
77
+{
78
+ tcg_gen_ext32u_tl(ret, arg1);
79
+ tcg_gen_clzi_tl(ret, ret, 64);
80
+ tcg_gen_subi_tl(ret, ret, 32);
81
+}
82
+
142
+
83
static bool gen_arith(DisasContext *ctx, arg_r *a,
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
84
void(*func)(TCGv, TCGv, TCGv))
85
{
144
{
86
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
145
- /*
87
return cpu_ldl_code(env, pc);
146
- * A table with predicate (i.e., guard) functions and decoder functions
147
- * that are tested in-order until a decoder matches onto the opcode.
148
- */
149
- static const struct {
150
- bool (*guard_func)(const RISCVCPUConfig *);
151
- bool (*decode_func)(DisasContext *, uint32_t);
152
- } decoders[] = {
153
- { always_true_p, decode_insn32 },
154
- { has_xthead_p, decode_xthead },
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
156
- };
157
-
158
ctx->virt_inst_excp = false;
159
ctx->cur_insn_len = insn_len(opcode);
160
/* Check for compressed insn */
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
162
ctx->base.pc_next + 2));
163
ctx->opcode = opcode32;
164
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
167
- decoders[i].decode_func(ctx, opcode32)) {
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
170
+ if (func(ctx, opcode32)) {
171
return;
172
}
173
}
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
176
ctx->zero = tcg_constant_tl(0);
177
ctx->virt_inst_excp = false;
178
+ ctx->decoders = cpu->decoders;
88
}
179
}
89
180
90
+static void gen_ctz(TCGv ret, TCGv arg1)
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
91
+{
92
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
93
+}
94
+
95
+static void gen_clz(TCGv ret, TCGv arg1)
96
+{
97
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
98
+}
99
+
100
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
101
+ void(*func)(TCGv, TCGv))
102
+{
103
+ TCGv source = tcg_temp_new();
104
+
105
+ gen_get_gpr(source, a->rs1);
106
+
107
+ (*func)(source, source);
108
+
109
+ gen_set_gpr(a->rd, source);
110
+ tcg_temp_free(source);
111
+ return true;
112
+}
113
+
114
/* Include insn module translation function */
115
#include "insn_trans/trans_rvi.c.inc"
116
#include "insn_trans/trans_rvm.c.inc"
117
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
118
#include "insn_trans/trans_rvd.c.inc"
119
#include "insn_trans/trans_rvh.c.inc"
120
#include "insn_trans/trans_rvv.c.inc"
121
+#include "insn_trans/trans_rvb.c.inc"
122
#include "insn_trans/trans_privileged.c.inc"
123
124
/* Include the auto-generated decoder for 16 bit insn */
125
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
126
new file mode 100644
127
index XXXXXXX..XXXXXXX
128
--- /dev/null
129
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
130
@@ -XXX,XX +XXX,XX @@
131
+/*
132
+ * RISC-V translation routines for the RVB Standard Extension.
133
+ *
134
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
135
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
136
+ *
137
+ * This program is free software; you can redistribute it and/or modify it
138
+ * under the terms and conditions of the GNU General Public License,
139
+ * version 2 or later, as published by the Free Software Foundation.
140
+ *
141
+ * This program is distributed in the hope it will be useful, but WITHOUT
142
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
143
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
144
+ * more details.
145
+ *
146
+ * You should have received a copy of the GNU General Public License along with
147
+ * this program. If not, see <http://www.gnu.org/licenses/>.
148
+ */
149
+
150
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
151
+{
152
+ REQUIRE_EXT(ctx, RVB);
153
+ return gen_unary(ctx, a, gen_clz);
154
+}
155
+
156
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
157
+{
158
+ REQUIRE_EXT(ctx, RVB);
159
+ return gen_unary(ctx, a, gen_ctz);
160
+}
161
+
162
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
163
+{
164
+ REQUIRE_64BIT(ctx);
165
+ REQUIRE_EXT(ctx, RVB);
166
+ return gen_unary(ctx, a, gen_clzw);
167
+}
168
+
169
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
170
+{
171
+ REQUIRE_64BIT(ctx);
172
+ REQUIRE_EXT(ctx, RVB);
173
+ return gen_unary(ctx, a, gen_ctzw);
174
+}
175
--
182
--
176
2.31.1
183
2.45.1
177
178
diff view generated by jsdifflib
[PULL 27/32] target/riscv: rvb: generalized reverse
[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
Signed-off-by: Frank Chang <frank.chang@sifive.com>
3
The th.sxstatus CSR can be used to identify available custom extension
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
on T-Head CPUs. The CSR is documented here:
5
Message-id: 20210505160620.15723-13-frank.chang@sifive.com
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
6
7
An important property of this patch is, that the th.sxstatus MAEE field
8
is not set (indicating that XTheadMae is not available).
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
25
---
8
target/riscv/helper.h | 4 ++
26
MAINTAINERS | 1 +
9
target/riscv/insn32.decode | 4 ++
27
target/riscv/cpu.h | 3 ++
10
target/riscv/bitmanip_helper.c | 64 +++++++++++++++++++++++++
28
target/riscv/cpu.c | 1 +
11
target/riscv/translate.c | 28 +++++++++++
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
12
target/riscv/insn_trans/trans_rvb.c.inc | 31 ++++++++++++
30
target/riscv/meson.build | 1 +
13
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
14
6 files changed, 132 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
15
create mode 100644 target/riscv/bitmanip_helper.c
16
33
17
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
34
diff --git a/MAINTAINERS b/MAINTAINERS
18
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/helper.h
36
--- a/MAINTAINERS
20
+++ b/target/riscv/helper.h
37
+++ b/MAINTAINERS
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
22
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
39
S: Supported
23
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
40
F: target/riscv/insn_trans/trans_xthead.c.inc
24
41
F: target/riscv/xthead*.decode
25
+/* Bitmanip */
42
+F: target/riscv/th_*
26
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
43
F: disas/riscv-xthead*
27
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
44
45
RISC-V XVentanaCondOps extension
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
51
uint8_t satp_mode_max_from_map(uint32_t map);
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
53
54
+/* Implemented in th_csr.c */
55
+void th_register_custom_csrs(RISCVCPU *cpu);
28
+
56
+
29
/* Special functions */
57
#endif /* RISCV_CPU_H */
30
DEF_HELPER_3(csrrw, tl, env, tl, tl)
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
31
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
32
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
33
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn32.decode
60
--- a/target/riscv/cpu.c
35
+++ b/target/riscv/insn32.decode
61
+++ b/target/riscv/cpu.c
36
@@ -XXX,XX +XXX,XX @@ slo 0010000 .......... 001 ..... 0110011 @r
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
37
sro 0010000 .......... 101 ..... 0110011 @r
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
38
ror 0110000 .......... 101 ..... 0110011 @r
64
#ifndef CONFIG_USER_ONLY
39
rol 0110000 .......... 001 ..... 0110011 @r
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
40
+grev 0110100 .......... 101 ..... 0110011 @r
66
+ th_register_custom_csrs(cpu);
41
67
#endif
42
bseti 00101. ........... 001 ..... 0010011 @sh
68
43
bclri 01001. ........... 001 ..... 0010011 @sh
69
/* inherited from parent obj via riscv_cpu_init() */
44
@@ -XXX,XX +XXX,XX @@ bexti 01001. ........... 101 ..... 0010011 @sh
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
45
sloi 00100. ........... 001 ..... 0010011 @sh
46
sroi 00100. ........... 101 ..... 0010011 @sh
47
rori 01100. ........... 101 ..... 0010011 @sh
48
+grevi 01101. ........... 101 ..... 0010011 @sh
49
50
# *** RV64B Standard Extension (in addition to RV32B) ***
51
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
52
@@ -XXX,XX +XXX,XX @@ slow 0010000 .......... 001 ..... 0111011 @r
53
srow 0010000 .......... 101 ..... 0111011 @r
54
rorw 0110000 .......... 101 ..... 0111011 @r
55
rolw 0110000 .......... 001 ..... 0111011 @r
56
+grevw 0110100 .......... 101 ..... 0111011 @r
57
58
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
59
bclriw 0100100 .......... 001 ..... 0011011 @sh5
60
@@ -XXX,XX +XXX,XX @@ binviw 0110100 .......... 001 ..... 0011011 @sh5
61
sloiw 0010000 .......... 001 ..... 0011011 @sh5
62
sroiw 0010000 .......... 101 ..... 0011011 @sh5
63
roriw 0110000 .......... 101 ..... 0011011 @sh5
64
+greviw 0110100 .......... 101 ..... 0011011 @sh5
65
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
66
new file mode 100644
71
new file mode 100644
67
index XXXXXXX..XXXXXXX
72
index XXXXXXX..XXXXXXX
68
--- /dev/null
73
--- /dev/null
69
+++ b/target/riscv/bitmanip_helper.c
74
+++ b/target/riscv/th_csr.c
70
@@ -XXX,XX +XXX,XX @@
75
@@ -XXX,XX +XXX,XX @@
71
+/*
76
+/*
72
+ * RISC-V Bitmanip Extension Helpers for QEMU.
77
+ * T-Head-specific CSRs.
73
+ *
78
+ *
74
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
79
+ * Copyright (c) 2024 VRULL GmbH
75
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
76
+ *
80
+ *
77
+ * This program is free software; you can redistribute it and/or modify it
81
+ * This program is free software; you can redistribute it and/or modify it
78
+ * under the terms and conditions of the GNU General Public License,
82
+ * under the terms and conditions of the GNU General Public License,
79
+ * version 2 or later, as published by the Free Software Foundation.
83
+ * version 2 or later, as published by the Free Software Foundation.
80
+ *
84
+ *
...
...
86
+ * You should have received a copy of the GNU General Public License along with
90
+ * You should have received a copy of the GNU General Public License along with
87
+ * this program. If not, see <http://www.gnu.org/licenses/>.
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
88
+ */
92
+ */
89
+
93
+
90
+#include "qemu/osdep.h"
94
+#include "qemu/osdep.h"
91
+#include "qemu/host-utils.h"
95
+#include "cpu.h"
92
+#include "exec/exec-all.h"
96
+#include "cpu_vendorid.h"
93
+#include "exec/helper-proto.h"
94
+#include "tcg/tcg.h"
95
+
97
+
96
+static const uint64_t adjacent_masks[] = {
98
+#define CSR_TH_SXSTATUS 0x5c0
97
+ dup_const(MO_8, 0x55),
99
+
98
+ dup_const(MO_8, 0x33),
100
+/* TH_SXSTATUS bits */
99
+ dup_const(MO_8, 0x0f),
101
+#define TH_SXSTATUS_UCME BIT(16)
100
+ dup_const(MO_16, 0xff),
102
+#define TH_SXSTATUS_MAEE BIT(21)
101
+ dup_const(MO_32, 0xffff),
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
102
+ UINT32_MAX
104
+
105
+typedef struct {
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
110
+
111
+static RISCVException smode(CPURISCVState *env, int csrno)
112
+{
113
+ if (riscv_has_ext(env, RVS)) {
114
+ return RISCV_EXCP_NONE;
115
+ }
116
+
117
+ return RISCV_EXCP_ILLEGAL_INST;
118
+}
119
+
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
121
+{
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
123
+ return -1;
124
+ }
125
+
126
+ return 0;
127
+}
128
+
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
130
+ target_ulong *val)
131
+{
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
134
+ return RISCV_EXCP_NONE;
135
+}
136
+
137
+static riscv_csr th_csr_list[] = {
138
+ {
139
+ .csrno = CSR_TH_SXSTATUS,
140
+ .insertion_test = test_thead_mvendorid,
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
142
+ }
103
+};
143
+};
104
+
144
+
105
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
145
+void th_register_custom_csrs(RISCVCPU *cpu)
106
+{
146
+{
107
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
108
+}
148
+ int csrno = th_csr_list[i].csrno;
109
+
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
110
+static target_ulong do_grev(target_ulong rs1,
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
111
+ target_ulong rs2,
151
+ riscv_set_csr_ops(csrno, csr_ops);
112
+ int bits)
113
+{
114
+ target_ulong x = rs1;
115
+ int i, shift;
116
+
117
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
118
+ if (rs2 & shift) {
119
+ x = do_swap(x, adjacent_masks[i], shift);
120
+ }
152
+ }
121
+ }
153
+ }
122
+
123
+ return x;
124
+}
125
+
126
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
127
+{
128
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
129
+}
130
+
131
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
132
+{
133
+ return do_grev(rs1, rs2, 32);
134
+}
135
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/target/riscv/translate.c
138
+++ b/target/riscv/translate.c
139
@@ -XXX,XX +XXX,XX @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
140
tcg_gen_not_tl(ret, ret);
141
}
142
143
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
144
+{
145
+ TCGv source1 = tcg_temp_new();
146
+ TCGv source2;
147
+
148
+ gen_get_gpr(source1, a->rs1);
149
+
150
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
151
+ /* rev8, byte swaps */
152
+ tcg_gen_bswap_tl(source1, source1);
153
+ } else {
154
+ source2 = tcg_temp_new();
155
+ tcg_gen_movi_tl(source2, a->shamt);
156
+ gen_helper_grev(source1, source1, source2);
157
+ tcg_temp_free(source2);
158
+ }
159
+
160
+ gen_set_gpr(a->rd, source1);
161
+ tcg_temp_free(source1);
162
+ return true;
163
+}
164
+
165
static void gen_ctzw(TCGv ret, TCGv arg1)
166
{
167
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
168
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
169
tcg_temp_free_i32(t2);
170
}
171
172
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
173
+{
174
+ tcg_gen_ext32u_tl(arg1, arg1);
175
+ gen_helper_grev(ret, arg1, arg2);
176
+}
177
+
178
static bool gen_arith(DisasContext *ctx, arg_r *a,
179
void(*func)(TCGv, TCGv, TCGv))
180
{
181
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/riscv/insn_trans/trans_rvb.c.inc
184
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
185
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
186
return gen_shift(ctx, a, tcg_gen_rotl_tl);
187
}
188
189
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
190
+{
191
+ REQUIRE_EXT(ctx, RVB);
192
+ return gen_shift(ctx, a, gen_helper_grev);
193
+}
194
+
195
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
196
+{
197
+ REQUIRE_EXT(ctx, RVB);
198
+
199
+ if (a->shamt >= TARGET_LONG_BITS) {
200
+ return false;
201
+ }
202
+
203
+ return gen_grevi(ctx, a);
204
+}
205
+
206
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
207
{
208
REQUIRE_64BIT(ctx);
209
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
210
REQUIRE_EXT(ctx, RVB);
211
return gen_shiftw(ctx, a, gen_rolw);
212
}
213
+
214
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
215
+{
216
+ REQUIRE_64BIT(ctx);
217
+ REQUIRE_EXT(ctx, RVB);
218
+ return gen_shiftw(ctx, a, gen_grevw);
219
+}
220
+
221
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
222
+{
223
+ REQUIRE_64BIT(ctx);
224
+ REQUIRE_EXT(ctx, RVB);
225
+ return gen_shiftiw(ctx, a, gen_grevw);
226
+}
154
+}
227
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
228
index XXXXXXX..XXXXXXX 100644
156
index XXXXXXX..XXXXXXX 100644
229
--- a/target/riscv/meson.build
157
--- a/target/riscv/meson.build
230
+++ b/target/riscv/meson.build
158
+++ b/target/riscv/meson.build
231
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
232
'gdbstub.c',
160
'monitor.c',
233
'op_helper.c',
161
'machine.c',
234
'vector_helper.c',
162
'pmu.c',
235
+ 'bitmanip_helper.c',
163
+ 'th_csr.c',
236
'translate.c',
164
'time_helper.c',
165
'riscv-qmp-cmds.c',
237
))
166
))
238
239
--
167
--
240
2.31.1
168
2.45.1
241
169
242
170
diff view generated by jsdifflib
[PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
interfaces for immediate shift instructions.
4
instructions will be affected by Zvfhmin extension.
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
5
7
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
8
* From 1*SEW(16/32) to 2*SEW(32/64)
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
* From 2*SEW(32/64) to 1*SEW(16/32)
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
9
Message-id: 20210505160620.15723-9-frank.chang@sifive.com
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
target/riscv/translate.c | 39 ++++++++++++++++++
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
13
target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
18
1 file changed, 18 insertions(+), 2 deletions(-)
14
2 files changed, 43 insertions(+), 50 deletions(-)
15
19
16
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/translate.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/target/riscv/translate.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
20
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
21
return cpu_ldl_code(env, pc);
25
}
22
}
26
}
23
27
24
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
28
+static bool require_rvfmin(DisasContext *s)
25
+ void(*func)(TCGv, TCGv, TCGv))
26
+{
29
+{
27
+ if (a->shamt >= TARGET_LONG_BITS) {
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
28
+ return false;
31
+ return false;
29
+ }
32
+ }
30
+
33
+
31
+ TCGv source1 = tcg_temp_new();
34
+ switch (s->sew) {
32
+ TCGv source2 = tcg_temp_new();
35
+ case MO_16:
33
+
36
+ return s->cfg_ptr->ext_zvfhmin;
34
+ gen_get_gpr(source1, a->rs1);
37
+ case MO_32:
35
+
38
+ return s->cfg_ptr->ext_zve32f;
36
+ tcg_gen_movi_tl(source2, a->shamt);
39
+ default:
37
+ (*func)(source1, source1, source2);
40
+ return false;
38
+
41
+ }
39
+ gen_set_gpr(a->rd, source1);
40
+ tcg_temp_free(source1);
41
+ tcg_temp_free(source2);
42
+ return true;
43
+}
42
+}
44
+
43
+
45
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
44
static bool require_scale_rvf(DisasContext *s)
46
+ void(*func)(TCGv, TCGv, TCGv))
47
+{
48
+ TCGv source1 = tcg_temp_new();
49
+ TCGv source2 = tcg_temp_new();
50
+
51
+ gen_get_gpr(source1, a->rs1);
52
+ tcg_gen_movi_tl(source2, a->shamt);
53
+
54
+ (*func)(source1, source1, source2);
55
+ tcg_gen_ext32s_tl(source1, source1);
56
+
57
+ gen_set_gpr(a->rd, source1);
58
+ tcg_temp_free(source1);
59
+ tcg_temp_free(source2);
60
+ return true;
61
+}
62
+
63
static void gen_ctz(TCGv ret, TCGv arg1)
64
{
45
{
65
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
66
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
67
index XXXXXXX..XXXXXXX 100644
48
}
68
--- a/target/riscv/insn_trans/trans_rvi.c.inc
49
69
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
50
switch (s->sew) {
70
@@ -XXX,XX +XXX,XX @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
51
- case MO_8:
52
- return s->cfg_ptr->ext_zvfhmin;
53
case MO_16:
54
return s->cfg_ptr->ext_zve32f;
55
case MO_32:
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
58
{
59
return opfv_widen_check(s, a) &&
60
+ require_rvfmin(s) &&
61
require_scale_rvfmin(s) &&
62
(s->sew != MO_8);
71
}
63
}
72
static bool trans_slli(DisasContext *ctx, arg_slli *a)
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
73
{
66
{
74
- if (a->shamt >= TARGET_LONG_BITS) {
67
return opfv_narrow_check(s, a) &&
75
- return false;
68
+ require_rvfmin(s) &&
76
- }
69
require_scale_rvfmin(s) &&
77
-
70
(s->sew != MO_8);
78
- if (a->rd != 0) {
79
- TCGv t = tcg_temp_new();
80
- gen_get_gpr(t, a->rs1);
81
-
82
- tcg_gen_shli_tl(t, t, a->shamt);
83
-
84
- gen_set_gpr(a->rd, t);
85
- tcg_temp_free(t);
86
- } /* NOP otherwise */
87
- return true;
88
+ return gen_shifti(ctx, a, tcg_gen_shl_tl);
89
}
71
}
90
91
static bool trans_srli(DisasContext *ctx, arg_srli *a)
92
{
93
- if (a->shamt >= TARGET_LONG_BITS) {
94
- return false;
95
- }
96
-
97
- if (a->rd != 0) {
98
- TCGv t = tcg_temp_new();
99
- gen_get_gpr(t, a->rs1);
100
-
101
- tcg_gen_shri_tl(t, t, a->shamt);
102
- gen_set_gpr(a->rd, t);
103
- tcg_temp_free(t);
104
- } /* NOP otherwise */
105
- return true;
106
+ return gen_shifti(ctx, a, tcg_gen_shr_tl);
107
}
108
109
static bool trans_srai(DisasContext *ctx, arg_srai *a)
110
{
111
- if (a->shamt >= TARGET_LONG_BITS) {
112
- return false;
113
- }
114
-
115
- if (a->rd != 0) {
116
- TCGv t = tcg_temp_new();
117
- gen_get_gpr(t, a->rs1);
118
-
119
- tcg_gen_sari_tl(t, t, a->shamt);
120
- gen_set_gpr(a->rd, t);
121
- tcg_temp_free(t);
122
- } /* NOP otherwise */
123
- return true;
124
+ return gen_shifti(ctx, a, tcg_gen_sar_tl);
125
}
126
127
static bool trans_add(DisasContext *ctx, arg_add *a)
128
@@ -XXX,XX +XXX,XX @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
129
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
130
{
131
REQUIRE_64BIT(ctx);
132
- TCGv source1;
133
- source1 = tcg_temp_new();
134
- gen_get_gpr(source1, a->rs1);
135
-
136
- tcg_gen_shli_tl(source1, source1, a->shamt);
137
- tcg_gen_ext32s_tl(source1, source1);
138
- gen_set_gpr(a->rd, source1);
139
-
140
- tcg_temp_free(source1);
141
- return true;
142
+ return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
143
}
144
145
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
146
--
72
--
147
2.31.1
73
2.45.1
148
149
diff view generated by jsdifflib
[PULL 16/32] target/riscv: reformat @sh format encoding for B-extension
[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
The require_scale_rvf function only checks the double width operator for
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
the vector floating point widen instructions, so most of the widen
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
checking functions need to add require_rvf for single width operator.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
7
Message-id: 20210505160620.15723-2-frank.chang@sifive.com
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
8
integer to double width float, so the opfxv_widen_check function doesn’t
9
need require_rvf for the single width operator(integer).
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
16
---
10
target/riscv/insn32.decode | 10 +++++-----
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
11
1 file changed, 5 insertions(+), 5 deletions(-)
18
1 file changed, 5 insertions(+)
12
19
13
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/insn32.decode
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
16
+++ b/target/riscv/insn32.decode
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
17
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
18
%rd 7:5
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
19
%sh5 20:5
26
{
20
27
return require_rvv(s) &&
21
-%sh10 20:10
28
+ require_rvf(s) &&
22
+%sh7 20:7
29
require_scale_rvf(s) &&
23
%csr 20:12
30
(s->sew != MO_8) &&
24
%rm 12:3
31
vext_check_isa_ill(s) &&
25
%nf 29:3 !function=ex_plus_1
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
26
@@ -XXX,XX +XXX,XX @@
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
27
@u .................... ..... ....... &u imm=%imm_u %rd
34
{
28
@j .................... ..... ....... &j imm=%imm_j %rd
35
return require_rvv(s) &&
29
36
+ require_rvf(s) &&
30
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
37
require_scale_rvf(s) &&
31
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
38
(s->sew != MO_8) &&
32
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
39
vext_check_isa_ill(s) &&
33
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
34
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
35
@@ -XXX,XX +XXX,XX @@ sltiu ............ ..... 011 ..... 0010011 @i
42
{
36
xori ............ ..... 100 ..... 0010011 @i
43
return require_rvv(s) &&
37
ori ............ ..... 110 ..... 0010011 @i
44
+ require_rvf(s) &&
38
andi ............ ..... 111 ..... 0010011 @i
45
require_scale_rvf(s) &&
39
-slli 00.... ...... ..... 001 ..... 0010011 @sh
46
(s->sew != MO_8) &&
40
-srli 00.... ...... ..... 101 ..... 0010011 @sh
47
vext_check_isa_ill(s) &&
41
-srai 01.... ...... ..... 101 ..... 0010011 @sh
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
42
+slli 00000. ...... ..... 001 ..... 0010011 @sh
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
43
+srli 00000. ...... ..... 101 ..... 0010011 @sh
50
{
44
+srai 01000. ...... ..... 101 ..... 0010011 @sh
51
return require_rvv(s) &&
45
add 0000000 ..... ..... 000 ..... 0110011 @r
52
+ require_rvf(s) &&
46
sub 0100000 ..... ..... 000 ..... 0110011 @r
53
require_scale_rvf(s) &&
47
sll 0000000 ..... ..... 001 ..... 0110011 @r
54
(s->sew != MO_8) &&
55
vext_check_isa_ill(s) &&
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
58
{
59
return reduction_widen_check(s, a) &&
60
+ require_rvf(s) &&
61
require_scale_rvf(s) &&
62
(s->sew != MO_8);
63
}
48
--
64
--
49
2.31.1
65
2.45.1
50
66
51
67
diff view generated by jsdifflib
[PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz.
[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
1
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
3
The opfv_narrow_check needs to check the single width float operator by
4
is still zero(as we don't use this field), simd_desc will trigger an
4
require_rvf.
5
assert.
6
5
7
Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
6
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Here we pass the value to maxsz and oprsz to bypass the assert.
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
8
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
11
---
15
target/riscv/insn_trans/trans_rvv.c.inc | 89 ++++++++++++++-----------
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
16
1 file changed, 50 insertions(+), 39 deletions(-)
13
1 file changed, 1 insertion(+)
17
14
18
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn_trans/trans_rvv.c.inc
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
21
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
22
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
23
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
24
* The second part is lmul, encoded in data of simd_desc.
21
{
25
*/
22
return opfv_narrow_check(s, a) &&
26
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
23
+ require_rvf(s) &&
27
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
24
require_scale_rvf(s) &&
28
25
(s->sew != MO_8);
29
gen_get_gpr(base, rs1);
26
}
30
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
31
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
32
mask = tcg_temp_new_ptr();
33
base = tcg_temp_new();
34
stride = tcg_temp_new();
35
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
36
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
37
38
gen_get_gpr(base, rs1);
39
gen_get_gpr(stride, rs2);
40
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
41
mask = tcg_temp_new_ptr();
42
index = tcg_temp_new_ptr();
43
base = tcg_temp_new();
44
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
45
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
46
47
gen_get_gpr(base, rs1);
48
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
49
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
50
dest = tcg_temp_new_ptr();
51
mask = tcg_temp_new_ptr();
52
base = tcg_temp_new();
53
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
54
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
55
56
gen_get_gpr(base, rs1);
57
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
58
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
59
mask = tcg_temp_new_ptr();
60
index = tcg_temp_new_ptr();
61
base = tcg_temp_new();
62
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
63
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
64
65
gen_get_gpr(base, rs1);
66
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
67
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
68
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
69
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
70
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
71
- cpu_env, 0, s->vlen / 8, data, fn);
72
+ cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
73
}
74
gen_set_label(over);
75
return true;
76
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
77
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
78
data = FIELD_DP32(data, VDATA, VM, vm);
79
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
80
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
81
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
82
83
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
84
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
85
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
86
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
87
data = FIELD_DP32(data, VDATA, VM, vm);
88
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
89
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
90
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
91
92
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
93
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
94
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
95
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
96
vreg_ofs(s, a->rs1),
97
vreg_ofs(s, a->rs2),
98
- cpu_env, 0, s->vlen / 8,
99
+ cpu_env, s->vlen / 8, s->vlen / 8,
100
data, fn);
101
gen_set_label(over);
102
return true;
103
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
104
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
105
vreg_ofs(s, a->rs1),
106
vreg_ofs(s, a->rs2),
107
- cpu_env, 0, s->vlen / 8, data, fn);
108
+ cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
109
gen_set_label(over);
110
return true;
111
}
112
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
113
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
114
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
115
vreg_ofs(s, a->rs1), \
116
- vreg_ofs(s, a->rs2), cpu_env, 0, \
117
- s->vlen / 8, data, fns[s->sew]); \
118
+ vreg_ofs(s, a->rs2), cpu_env, \
119
+ s->vlen / 8, s->vlen / 8, data, \
120
+ fns[s->sew]); \
121
gen_set_label(over); \
122
return true; \
123
} \
124
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
125
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
126
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
127
vreg_ofs(s, a->rs1), \
128
- vreg_ofs(s, a->rs2), cpu_env, 0, \
129
- s->vlen / 8, data, fns[s->sew]); \
130
+ vreg_ofs(s, a->rs2), cpu_env, \
131
+ s->vlen / 8, s->vlen / 8, data, \
132
+ fns[s->sew]); \
133
gen_set_label(over); \
134
return true; \
135
} \
136
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
137
};
138
139
tcg_gen_ext_tl_i64(s1_i64, s1);
140
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
141
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
142
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
143
fns[s->sew](dest, s1_i64, cpu_env, desc);
144
145
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
146
147
s1 = tcg_const_i64(simm);
148
dest = tcg_temp_new_ptr();
149
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
150
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
151
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
152
fns[s->sew](dest, s1, cpu_env, desc);
153
154
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
155
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
156
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
157
vreg_ofs(s, a->rs1), \
158
- vreg_ofs(s, a->rs2), cpu_env, 0, \
159
- s->vlen / 8, data, fns[s->sew - 1]); \
160
+ vreg_ofs(s, a->rs2), cpu_env, \
161
+ s->vlen / 8, s->vlen / 8, data, \
162
+ fns[s->sew - 1]); \
163
gen_set_label(over); \
164
return true; \
165
} \
166
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
167
dest = tcg_temp_new_ptr();
168
mask = tcg_temp_new_ptr();
169
src2 = tcg_temp_new_ptr();
170
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
171
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
172
173
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
174
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
175
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
176
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
177
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
178
vreg_ofs(s, a->rs1), \
179
- vreg_ofs(s, a->rs2), cpu_env, 0, \
180
- s->vlen / 8, data, fns[s->sew - 1]); \
181
+ vreg_ofs(s, a->rs2), cpu_env, \
182
+ s->vlen / 8, s->vlen / 8, data, \
183
+ fns[s->sew - 1]); \
184
gen_set_label(over); \
185
return true; \
186
} \
187
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
188
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
189
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
190
vreg_ofs(s, a->rs1), \
191
- vreg_ofs(s, a->rs2), cpu_env, 0, \
192
- s->vlen / 8, data, fns[s->sew - 1]); \
193
+ vreg_ofs(s, a->rs2), cpu_env, \
194
+ s->vlen / 8, s->vlen / 8, data, \
195
+ fns[s->sew - 1]); \
196
gen_set_label(over); \
197
return true; \
198
} \
199
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
200
data = FIELD_DP32(data, VDATA, VM, a->vm); \
201
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
202
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
203
- vreg_ofs(s, a->rs2), cpu_env, 0, \
204
- s->vlen / 8, data, fns[s->sew - 1]); \
205
+ vreg_ofs(s, a->rs2), cpu_env, \
206
+ s->vlen / 8, s->vlen / 8, data, \
207
+ fns[s->sew - 1]); \
208
gen_set_label(over); \
209
return true; \
210
} \
211
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
212
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
213
214
dest = tcg_temp_new_ptr();
215
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
216
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
217
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
218
fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
219
220
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
221
data = FIELD_DP32(data, VDATA, VM, a->vm); \
222
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
223
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
224
- vreg_ofs(s, a->rs2), cpu_env, 0, \
225
- s->vlen / 8, data, fns[s->sew - 1]); \
226
+ vreg_ofs(s, a->rs2), cpu_env, \
227
+ s->vlen / 8, s->vlen / 8, data, \
228
+ fns[s->sew - 1]); \
229
gen_set_label(over); \
230
return true; \
231
} \
232
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
233
data = FIELD_DP32(data, VDATA, VM, a->vm); \
234
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
235
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
236
- vreg_ofs(s, a->rs2), cpu_env, 0, \
237
- s->vlen / 8, data, fns[s->sew - 1]); \
238
+ vreg_ofs(s, a->rs2), cpu_env, \
239
+ s->vlen / 8, s->vlen / 8, data, \
240
+ fns[s->sew - 1]); \
241
gen_set_label(over); \
242
return true; \
243
} \
244
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
245
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
246
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
247
vreg_ofs(s, a->rs1), \
248
- vreg_ofs(s, a->rs2), cpu_env, 0, \
249
- s->vlen / 8, data, fn); \
250
+ vreg_ofs(s, a->rs2), cpu_env, \
251
+ s->vlen / 8, s->vlen / 8, data, fn); \
252
gen_set_label(over); \
253
return true; \
254
} \
255
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
256
mask = tcg_temp_new_ptr();
257
src2 = tcg_temp_new_ptr();
258
dst = tcg_temp_new();
259
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
260
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
261
262
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
263
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
264
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
265
mask = tcg_temp_new_ptr();
266
src2 = tcg_temp_new_ptr();
267
dst = tcg_temp_new();
268
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
269
+ desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
270
271
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
272
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
273
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
274
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
275
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
276
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
277
- cpu_env, 0, s->vlen / 8, data, fn); \
278
+ cpu_env, s->vlen / 8, s->vlen / 8, \
279
+ data, fn); \
280
gen_set_label(over); \
281
return true; \
282
} \
283
@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
284
gen_helper_viota_m_w, gen_helper_viota_m_d,
285
};
286
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
287
- vreg_ofs(s, a->rs2), cpu_env, 0,
288
- s->vlen / 8, data, fns[s->sew]);
289
+ vreg_ofs(s, a->rs2), cpu_env,
290
+ s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
291
gen_set_label(over);
292
return true;
293
}
294
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
295
gen_helper_vid_v_w, gen_helper_vid_v_d,
296
};
297
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
298
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
299
+ cpu_env, s->vlen / 8, s->vlen / 8,
300
+ data, fns[s->sew]);
301
gen_set_label(over);
302
return true;
303
}
304
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
305
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
306
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
307
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
308
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
309
+ cpu_env, s->vlen / 8, s->vlen / 8, data,
310
+ fns[s->sew]);
311
gen_set_label(over);
312
return true;
313
}
314
--
27
--
315
2.31.1
28
2.45.1
316
317
diff view generated by jsdifflib
[PULL 20/32] target/riscv: rvb: pack two words into one register
[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
If the checking functions check both the single and double width
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
operators at the same time, then the single width operator checking
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
functions (require_rvf[min]) will check whether the SEW is 8.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
7
Message-id: 20210505160620.15723-6-frank.chang@sifive.com
7
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
12
---
10
target/riscv/insn32.decode | 6 ++++
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
11
target/riscv/translate.c | 40 +++++++++++++++++++++++++
14
1 file changed, 4 insertions(+), 12 deletions(-)
12
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
13
3 files changed, 78 insertions(+)
14
15
15
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn32.decode
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn32.decode
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
20
andn 0100000 .......... 111 ..... 0110011 @r
21
return require_rvv(s) &&
21
orn 0100000 .......... 110 ..... 0110011 @r
22
require_rvf(s) &&
22
xnor 0100000 .......... 100 ..... 0110011 @r
23
require_scale_rvf(s) &&
23
+pack 0000100 .......... 100 ..... 0110011 @r
24
- (s->sew != MO_8) &&
24
+packu 0100100 .......... 100 ..... 0110011 @r
25
vext_check_isa_ill(s) &&
25
+packh 0000100 .......... 111 ..... 0110011 @r
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
26
27
# *** RV64B Standard Extension (in addition to RV32B) ***
28
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
29
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
30
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
31
+
32
+packw 0000100 .......... 100 ..... 0111011 @r
33
+packuw 0100100 .......... 100 ..... 0111011 @r
34
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/translate.c
37
+++ b/target/riscv/translate.c
38
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
39
return true;
40
}
27
}
41
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
42
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
29
return require_rvv(s) &&
43
+{
30
require_rvf(s) &&
44
+ tcg_gen_deposit_tl(ret, arg1, arg2,
31
require_scale_rvf(s) &&
45
+ TARGET_LONG_BITS / 2,
32
- (s->sew != MO_8) &&
46
+ TARGET_LONG_BITS / 2);
33
vext_check_isa_ill(s) &&
47
+}
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
48
+
35
}
49
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
50
+{
37
return require_rvv(s) &&
51
+ TCGv t = tcg_temp_new();
38
require_rvf(s) &&
52
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
39
require_scale_rvf(s) &&
53
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
40
- (s->sew != MO_8) &&
54
+ tcg_temp_free(t);
41
vext_check_isa_ill(s) &&
55
+}
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
56
+
43
}
57
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
58
+{
45
return require_rvv(s) &&
59
+ TCGv t = tcg_temp_new();
46
require_rvf(s) &&
60
+ tcg_gen_ext8u_tl(t, arg2);
47
require_scale_rvf(s) &&
61
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
48
- (s->sew != MO_8) &&
62
+ tcg_temp_free(t);
49
vext_check_isa_ill(s) &&
63
+}
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
64
+
51
}
65
static void gen_ctzw(TCGv ret, TCGv arg1)
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
66
{
53
{
67
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
54
return opfv_widen_check(s, a) &&
68
@@ -XXX,XX +XXX,XX @@ static void gen_cpopw(TCGv ret, TCGv arg1)
55
require_rvfmin(s) &&
69
tcg_gen_ctpop_tl(ret, arg1);
56
- require_scale_rvfmin(s) &&
57
- (s->sew != MO_8);
58
+ require_scale_rvfmin(s);
70
}
59
}
71
60
72
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
73
+{
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
74
+ TCGv t = tcg_temp_new();
75
+ tcg_gen_ext16s_tl(t, arg2);
76
+ tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
77
+ tcg_temp_free(t);
78
+}
79
+
80
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
81
+{
82
+ TCGv t = tcg_temp_new();
83
+ tcg_gen_shri_tl(t, arg1, 16);
84
+ tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
85
+ tcg_gen_ext32s_tl(ret, ret);
86
+ tcg_temp_free(t);
87
+}
88
+
89
static bool gen_arith(DisasContext *ctx, arg_r *a,
90
void(*func)(TCGv, TCGv, TCGv))
91
{
63
{
92
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
64
return opfv_narrow_check(s, a) &&
93
index XXXXXXX..XXXXXXX 100644
65
require_rvfmin(s) &&
94
--- a/target/riscv/insn_trans/trans_rvb.c.inc
66
- require_scale_rvfmin(s) &&
95
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
67
- (s->sew != MO_8);
96
@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
68
+ require_scale_rvfmin(s);
97
return gen_arith(ctx, a, tcg_gen_eqv_tl);
98
}
69
}
99
70
100
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
101
+{
102
+ REQUIRE_EXT(ctx, RVB);
103
+ return gen_arith(ctx, a, gen_pack);
104
+}
105
+
106
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
107
+{
108
+ REQUIRE_EXT(ctx, RVB);
109
+ return gen_arith(ctx, a, gen_packu);
110
+}
111
+
112
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
113
+{
114
+ REQUIRE_EXT(ctx, RVB);
115
+ return gen_arith(ctx, a, gen_packh);
116
+}
117
+
118
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
119
{
72
{
120
REQUIRE_64BIT(ctx);
73
return opfv_narrow_check(s, a) &&
121
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
74
require_rvf(s) &&
122
REQUIRE_EXT(ctx, RVB);
75
- require_scale_rvf(s) &&
123
return gen_unary(ctx, a, gen_cpopw);
76
- (s->sew != MO_8);
77
+ require_scale_rvf(s);
124
}
78
}
125
+
79
126
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
127
+{
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
128
+ REQUIRE_64BIT(ctx);
82
{
129
+ REQUIRE_EXT(ctx, RVB);
83
return reduction_widen_check(s, a) &&
130
+ return gen_arith(ctx, a, gen_packw);
84
require_rvf(s) &&
131
+}
85
- require_scale_rvf(s) &&
132
+
86
- (s->sew != MO_8);
133
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
87
+ require_scale_rvf(s);
134
+{
88
}
135
+ REQUIRE_64BIT(ctx);
89
136
+ REQUIRE_EXT(ctx, RVB);
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
137
+ return gen_arith(ctx, a, gen_packuw);
138
+}
139
--
91
--
140
2.31.1
92
2.45.1
141
142
diff view generated by jsdifflib
[PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices
[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
The supported device bullet list has an additional space before each
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
entry, which makes a wrong indentation level. Correct it.
4
checking first if virt_enabled && !first_stage, and then considering the
5
regular inst/load/store faults.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
There's no mention in the spec about guest page fault being a higher
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
34
---
11
docs/system/riscv/microchip-icicle-kit.rst | 20 +++++++--------
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
12
docs/system/riscv/sifive_u.rst | 30 +++++++++++-----------
36
1 file changed, 12 insertions(+), 10 deletions(-)
13
2 files changed, 25 insertions(+), 25 deletions(-)
14
37
15
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/riscv/microchip-icicle-kit.rst
40
--- a/target/riscv/cpu_helper.c
18
+++ b/docs/system/riscv/microchip-icicle-kit.rst
41
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ Supported devices
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
20
43
21
The ``microchip-icicle-kit`` machine supports the following devices:
44
switch (access_type) {
22
45
case MMU_INST_FETCH:
23
- * 1 E51 core
46
- if (env->virt_enabled && !first_stage) {
24
- * 4 U54 cores
47
+ if (pmp_violation) {
25
- * Core Level Interruptor (CLINT)
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
26
- * Platform-Level Interrupt Controller (PLIC)
49
+ } else if (env->virt_enabled && !first_stage) {
27
- * L2 Loosely Integrated Memory (L2-LIM)
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
28
- * DDR memory controller
51
} else {
29
- * 5 MMUARTs
52
- cs->exception_index = pmp_violation ?
30
- * 1 DMA controller
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
31
- * 2 GEM Ethernet controllers
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
32
- * 1 SDHC storage controller
55
}
33
+* 1 E51 core
56
break;
34
+* 4 U54 cores
57
case MMU_DATA_LOAD:
35
+* Core Level Interruptor (CLINT)
58
- if (two_stage && !first_stage) {
36
+* Platform-Level Interrupt Controller (PLIC)
59
+ if (pmp_violation) {
37
+* L2 Loosely Integrated Memory (L2-LIM)
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
38
+* DDR memory controller
61
+ } else if (two_stage && !first_stage) {
39
+* 5 MMUARTs
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
40
+* 1 DMA controller
63
} else {
41
+* 2 GEM Ethernet controllers
64
- cs->exception_index = pmp_violation ?
42
+* 1 SDHC storage controller
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
43
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
44
Boot options
67
}
45
------------
68
break;
46
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
69
case MMU_DATA_STORE:
47
index XXXXXXX..XXXXXXX 100644
70
- if (two_stage && !first_stage) {
48
--- a/docs/system/riscv/sifive_u.rst
71
+ if (pmp_violation) {
49
+++ b/docs/system/riscv/sifive_u.rst
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
50
@@ -XXX,XX +XXX,XX @@ Supported devices
73
+ } else if (two_stage && !first_stage) {
51
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
52
The ``sifive_u`` machine supports the following devices:
75
} else {
53
76
- cs->exception_index = pmp_violation ?
54
- * 1 E51 / E31 core
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
55
- * Up to 4 U54 / U34 cores
78
- RISCV_EXCP_STORE_PAGE_FAULT;
56
- * Core Level Interruptor (CLINT)
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
57
- * Platform-Level Interrupt Controller (PLIC)
80
}
58
- * Power, Reset, Clock, Interrupt (PRCI)
81
break;
59
- * L2 Loosely Integrated Memory (L2-LIM)
82
default:
60
- * DDR memory controller
61
- * 2 UARTs
62
- * 1 GEM Ethernet controller
63
- * 1 GPIO controller
64
- * 1 One-Time Programmable (OTP) memory with stored serial number
65
- * 1 DMA controller
66
- * 2 QSPI controllers
67
- * 1 ISSI 25WP256 flash
68
- * 1 SD card in SPI mode
69
+* 1 E51 / E31 core
70
+* Up to 4 U54 / U34 cores
71
+* Core Level Interruptor (CLINT)
72
+* Platform-Level Interrupt Controller (PLIC)
73
+* Power, Reset, Clock, Interrupt (PRCI)
74
+* L2 Loosely Integrated Memory (L2-LIM)
75
+* DDR memory controller
76
+* 2 UARTs
77
+* 1 GEM Ethernet controller
78
+* 1 GPIO controller
79
+* 1 One-Time Programmable (OTP) memory with stored serial number
80
+* 1 DMA controller
81
+* 2 QSPI controllers
82
+* 1 ISSI 25WP256 flash
83
+* 1 SD card in SPI mode
84
85
Please note the real world HiFive Unleashed board has a fixed configuration of
86
1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
87
--
83
--
88
2.31.1
84
2.45.1
89
90
diff view generated by jsdifflib
[PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage
[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
2
2
3
Update the 'sifive_u' machine documentation to mention the '-dtb'
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
option that can be used to pass a custom DTB to QEMU.
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
5
7
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
14
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
21
---
11
docs/system/riscv/sifive_u.rst | 47 +++++++++++++++++++++++++++++-----
22
target/riscv/cpu_helper.c | 12 ++++++------
12
1 file changed, 41 insertions(+), 6 deletions(-)
23
1 file changed, 6 insertions(+), 6 deletions(-)
13
24
14
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/riscv/sifive_u.rst
27
--- a/target/riscv/cpu_helper.c
17
+++ b/docs/system/riscv/sifive_u.rst
28
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ Hardware configuration information
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
19
----------------------------------
30
__func__, pa, ret, prot_pmp, tlb_size);
20
31
21
The ``sifive_u`` machine automatically generates a device tree blob ("dtb")
32
prot &= prot_pmp;
22
-which it passes to the guest. This provides information about the addresses,
33
- }
23
-interrupt lines and other configuration of the various devices in the system.
34
-
24
-Guest software should discover the devices that are present in the generated
35
- if (ret != TRANSLATE_SUCCESS) {
25
-DTB instead of using a DTB for the real hardware, as some of the devices are
36
+ } else {
26
-not modeled by QEMU and trying to access these devices may cause unexpected
37
/*
27
-behavior.
38
* Guest physical address translation failed, this is a HS
28
+which it passes to the guest, if there is no ``-dtb`` option. This provides
39
* level exception
29
+information about the addresses, interrupt lines and other configuration of
40
*/
30
+the various devices in the system. Guest software should discover the devices
41
first_stage_error = false;
31
+that are present in the generated DTB instead of using a DTB for the real
42
- env->guest_phys_fault_addr = (im_address |
32
+hardware, as some of the devices are not modeled by QEMU and trying to access
43
- (address &
33
+these devices may cause unexpected behavior.
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
34
+
45
+ if (ret != TRANSLATE_PMP_FAIL) {
35
+If users want to provide their own DTB, they can use the ``-dtb`` option.
46
+ env->guest_phys_fault_addr = (im_address |
36
+These DTBs should have the following requirements:
47
+ (address &
37
+
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
38
+* The /cpus node should contain at least one subnode for E51 and the number
49
+ }
39
+ of subnodes should match QEMU's ``-smp`` option
50
}
40
+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
51
}
41
+* Should contain a node for the CLINT device with a compatible string
52
} else {
42
+ "riscv,clint0" if using with OpenSBI BIOS images
43
44
Boot options
45
------------
46
@@ -XXX,XX +XXX,XX @@ To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine:
47
-initrd /path/to/rootfs.ext4 \
48
-append "root=/dev/ram"
49
50
+Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT
51
+node in fu540-c000.dtsi in the Linux kernel,
52
+
53
+.. code-block:: none
54
+
55
+ clint: clint@2000000 {
56
+ compatible = "riscv,clint0";
57
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
58
+ &cpu1_intc 3 &cpu1_intc 7
59
+ &cpu2_intc 3 &cpu2_intc 7
60
+ &cpu3_intc 3 &cpu3_intc 7
61
+ &cpu4_intc 3 &cpu4_intc 7>;
62
+ reg = <0x00 0x2000000 0x00 0x10000>;
63
+ };
64
+
65
+with the following command line options:
66
+
67
+.. code-block:: bash
68
+
69
+ $ qemu-system-riscv64 -M sifive_u -smp 5 -m 8G \
70
+ -display none -serial stdio \
71
+ -kernel arch/riscv/boot/Image \
72
+ -dtb arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb \
73
+ -initrd /path/to/rootfs.ext4 \
74
+ -append "root=/dev/ram"
75
+
76
To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine
77
in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
78
fix the 32-bit boot issue for Linux kernel v5.10.
79
--
53
--
80
2.31.1
54
2.45.1
81
82
diff view generated by jsdifflib
[PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration
[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
1
From: Bin Meng <bmeng.cn@gmail.com>
1
From: Rob Bradford <rbradford@rivosinc.com>
2
2
3
riscv_excp_names[] and riscv_intr_names[] are only referenced by
3
This extension has now been ratified:
4
target/riscv/cpu.c locally.
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
removed.
5
6
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Since this is now a ratified extension add it to the list of extensions
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
17
---
12
target/riscv/cpu.h | 2 --
18
target/riscv/cpu.c | 2 +-
13
target/riscv/cpu.c | 4 ++--
19
target/riscv/tcg/tcg-cpu.c | 2 +-
14
2 files changed, 2 insertions(+), 4 deletions(-)
20
2 files changed, 2 insertions(+), 2 deletions(-)
15
21
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
19
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
21
22
extern const char * const riscv_int_regnames[];
23
extern const char * const riscv_fpr_regnames[];
24
-extern const char * const riscv_excp_names[];
25
-extern const char * const riscv_intr_names[];
26
27
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
28
void riscv_cpu_do_interrupt(CPUState *cpu);
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
30
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu.c
24
--- a/target/riscv/cpu.c
32
+++ b/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
33
@@ -XXX,XX +XXX,XX @@ const char * const riscv_fpr_regnames[] = {
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
34
"f30/ft10", "f31/ft11"
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
35
};
32
};
36
33
37
-const char * const riscv_excp_names[] = {
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
38
+static const char * const riscv_excp_names[] = {
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
39
"misaligned_fetch",
36
index XXXXXXX..XXXXXXX 100644
40
"fault_fetch",
37
--- a/target/riscv/tcg/tcg-cpu.c
41
"illegal_instruction",
38
+++ b/target/riscv/tcg/tcg-cpu.c
42
@@ -XXX,XX +XXX,XX @@ const char * const riscv_excp_names[] = {
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
43
"guest_store_page_fault",
40
const RISCVCPUMultiExtConfig *prop;
44
};
41
45
42
/* Enable RVG, RVJ and RVV that are disabled by default */
46
-const char * const riscv_intr_names[] = {
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
47
+static const char * const riscv_intr_names[] = {
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
48
"u_software",
45
49
"s_software",
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
50
"vs_software",
47
isa_ext_update_enabled(cpu, prop->offset, true);
51
--
48
--
52
2.31.1
49
2.45.1
53
54
diff view generated by jsdifflib
[PULL 18/32] target/riscv: rvb: count bits set
[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
When running the instruction
4
5
```
6
cbo.flush 0(x0)
7
```
8
9
QEMU would segfault.
10
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
26
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Cc: qemu-stable <qemu-stable@nongnu.org>
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
7
Message-id: 20210505160620.15723-4-frank.chang@sifive.com
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
34
---
10
target/riscv/insn32.decode | 2 ++
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
11
target/riscv/translate.c | 6 ++++++
36
1 file changed, 12 insertions(+), 4 deletions(-)
12
target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
13
3 files changed, 21 insertions(+)
14
37
15
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
16
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn32.decode
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
18
+++ b/target/riscv/insn32.decode
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
19
@@ -XXX,XX +XXX,XX @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
42
@@ -XXX,XX +XXX,XX @@
20
# *** RV32B Standard Extension ***
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
21
clz 011000 000000 ..... 001 ..... 0010011 @r2
44
{
22
ctz 011000 000001 ..... 001 ..... 0010011 @r2
45
REQUIRE_ZICBOM(ctx);
23
+cpop 011000 000010 ..... 001 ..... 0010011 @r2
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
24
47
+ TCGv src = get_address(ctx, a->rs1, 0);
25
# *** RV64B Standard Extension (in addition to RV32B) ***
48
+
26
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
27
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
50
return true;
28
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
29
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/translate.c
32
+++ b/target/riscv/translate.c
33
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
34
tcg_gen_subi_tl(ret, ret, 32);
35
}
51
}
36
52
37
+static void gen_cpopw(TCGv ret, TCGv arg1)
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
38
+{
54
{
39
+ tcg_gen_ext32u_tl(arg1, arg1);
55
REQUIRE_ZICBOM(ctx);
40
+ tcg_gen_ctpop_tl(ret, arg1);
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
41
+}
57
+ TCGv src = get_address(ctx, a->rs1, 0);
42
+
58
+
43
static bool gen_arith(DisasContext *ctx, arg_r *a,
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
44
void(*func)(TCGv, TCGv, TCGv))
60
return true;
61
}
62
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
45
{
64
{
46
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
65
REQUIRE_ZICBOM(ctx);
47
index XXXXXXX..XXXXXXX 100644
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
48
--- a/target/riscv/insn_trans/trans_rvb.c.inc
67
+ TCGv src = get_address(ctx, a->rs1, 0);
49
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
68
+
50
@@ -XXX,XX +XXX,XX @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
69
+ gen_helper_cbo_inval(tcg_env, src);
51
return gen_unary(ctx, a, gen_ctz);
70
return true;
52
}
71
}
53
72
54
+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
55
+{
74
{
56
+ REQUIRE_EXT(ctx, RVB);
75
REQUIRE_ZICBOZ(ctx);
57
+ return gen_unary(ctx, a, tcg_gen_ctpop_tl);
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
58
+}
77
+ TCGv src = get_address(ctx, a->rs1, 0);
59
+
78
+
60
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
79
+ gen_helper_cbo_zero(tcg_env, src);
61
{
80
return true;
62
REQUIRE_64BIT(ctx);
63
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
64
REQUIRE_EXT(ctx, RVB);
65
return gen_unary(ctx, a, gen_ctzw);
66
}
81
}
67
+
68
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
69
+{
70
+ REQUIRE_64BIT(ctx);
71
+ REQUIRE_EXT(ctx, RVB);
72
+ return gen_unary(ctx, a, gen_cpopw);
73
+}
74
--
82
--
75
2.31.1
83
2.45.1
76
77
diff view generated by jsdifflib
[PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend
[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
1
From: Kito Cheng <kito.cheng@sifive.com>
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
2
3
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
Signed-off-by: Frank Chang <frank.chang@sifive.com>
4
number to locate the memory pages of interrupt files in the address
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
space. The number of bits required to represent any hart number is equal
6
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
8
9
However, if the largest hart number among groups is a power of 2, QEMU
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
25
---
9
target/riscv/insn32.decode | 3 +++
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
10
target/riscv/translate.c | 6 ++++++
27
1 file changed, 8 insertions(+), 1 deletion(-)
11
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
12
3 files changed, 35 insertions(+)
13
28
14
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/insn32.decode
31
--- a/target/riscv/kvm/kvm-cpu.c
17
+++ b/target/riscv/insn32.decode
32
+++ b/target/riscv/kvm/kvm-cpu.c
18
@@ -XXX,XX +XXX,XX @@ gorcw 0010100 .......... 101 ..... 0111011 @r
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
19
sh1add_uw 0010000 .......... 010 ..... 0111011 @r
34
}
20
sh2add_uw 0010000 .......... 100 ..... 0111011 @r
35
}
21
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
36
22
+add_uw 0000100 .......... 000 ..... 0111011 @r
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
23
24
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
25
bclriw 0100100 .......... 001 ..... 0011011 @sh5
26
@@ -XXX,XX +XXX,XX @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
27
roriw 0110000 .......... 101 ..... 0011011 @sh5
28
greviw 0110100 .......... 101 ..... 0011011 @sh5
29
gorciw 0010100 .......... 101 ..... 0011011 @sh5
30
+
38
+
31
+slli_uw 00001. ........... 001 ..... 0011011 @sh
39
+ if (max_hart_per_socket > 1) {
32
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
40
+ max_hart_per_socket--;
33
index XXXXXXX..XXXXXXX 100644
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
34
--- a/target/riscv/translate.c
35
+++ b/target/riscv/translate.c
36
@@ -XXX,XX +XXX,XX @@ GEN_SHADD_UW(1)
37
GEN_SHADD_UW(2)
38
GEN_SHADD_UW(3)
39
40
+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
41
+{
42
+ tcg_gen_ext32u_tl(arg1, arg1);
43
+ tcg_gen_add_tl(ret, arg1, arg2);
44
+}
45
+
46
static bool gen_arith(DisasContext *ctx, arg_r *a,
47
void(*func)(TCGv, TCGv, TCGv))
48
{
49
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/riscv/insn_trans/trans_rvb.c.inc
52
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
53
@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
54
GEN_TRANS_SHADD_UW(1)
55
GEN_TRANS_SHADD_UW(2)
56
GEN_TRANS_SHADD_UW(3)
57
+
58
+static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
59
+{
60
+ REQUIRE_64BIT(ctx);
61
+ REQUIRE_EXT(ctx, RVB);
62
+ return gen_arith(ctx, a, gen_add_uw);
63
+}
64
+
65
+static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
66
+{
67
+ REQUIRE_64BIT(ctx);
68
+ REQUIRE_EXT(ctx, RVB);
69
+
70
+ TCGv source1 = tcg_temp_new();
71
+ gen_get_gpr(source1, a->rs1);
72
+
73
+ if (a->shamt < 32) {
74
+ tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
75
+ } else {
42
+ } else {
76
+ tcg_gen_shli_tl(source1, source1, a->shamt);
43
+ hart_bits = 0;
77
+ }
44
+ }
78
+
45
+
79
+ gen_set_gpr(a->rd, source1);
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
80
+ tcg_temp_free(source1);
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
81
+ return true;
48
&hart_bits, true, NULL);
82
+}
83
--
49
--
84
2.31.1
50
2.45.1
85
86
diff view generated by jsdifflib
[PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
we can use the new helper to set the clock name for the ethernet
4
in bytes, when in this context we want 'reg_width' as the length in
5
controller node.
5
bits.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
9
beforehand.
10
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
12
clarity about what the variable represents. 'bitsize' is also used in
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
15
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
17
Cc: Alex Bennée <alex.bennee@linaro.org>
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
28
---
12
hw/riscv/sifive_u.c | 6 +++---
29
target/riscv/gdbstub.c | 6 +++---
13
1 file changed, 3 insertions(+), 3 deletions(-)
30
1 file changed, 3 insertions(+), 3 deletions(-)
14
31
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
34
--- a/target/riscv/gdbstub.c
18
+++ b/hw/riscv/sifive_u.c
35
+++ b/target/riscv/gdbstub.c
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
20
int cpu;
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
21
uint32_t *cells;
38
{
22
char *nodename;
39
RISCVCPU *cpu = RISCV_CPU(cs);
23
- char ethclk_names[] = "pclk\0hclk";
40
- int reg_width = cpu->cfg.vlenb;
24
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
41
+ int bitsize = cpu->cfg.vlenb << 3;
25
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
42
GDBFeatureBuilder builder;
26
+ static const char * const ethclk_names[2] = { "pclk", "hclk" };
43
int i;
27
44
28
if (ms->dtb) {
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
29
fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
46
30
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
47
/* First define types and totals in a whole VL */
31
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
32
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
49
- int count = reg_width / vec_lanes[i].size;
33
prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
50
+ int count = bitsize / vec_lanes[i].size;
34
- qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
51
gdb_feature_builder_append_tag(
35
- sizeof(ethclk_names));
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
36
+ qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
37
+ (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
38
qemu_fdt_setprop(fdt, nodename, "local-mac-address",
55
/* Define vector registers */
39
s->soc.gem.conf.macaddr.a, ETH_ALEN);
56
for (i = 0; i < 32; i++) {
40
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
58
- reg_width, i, "riscv_vector", "vector");
59
+ bitsize, i, "riscv_vector", "vector");
60
}
61
62
gdb_feature_builder_end(&builder);
41
--
63
--
42
2.31.1
64
2.45.1
43
65
44
66
diff view generated by jsdifflib
[PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
we can use the new helper to set the compatible strings for the
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
SiFive test device node.
5
CSRs are part of the disassembly.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com
9
Fixes: ea10325917 ("RISC-V Disassembler")
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
hw/riscv/virt.c | 7 +++++--
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
13
1 file changed, 5 insertions(+), 2 deletions(-)
16
1 file changed, 64 insertions(+), 1 deletion(-)
14
17
15
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
18
diff --git a/disas/riscv.c b/disas/riscv.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/virt.c
20
--- a/disas/riscv.c
18
+++ b/hw/riscv/virt.c
21
+++ b/disas/riscv.c
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
20
(long)memmap[VIRT_TEST].base);
23
case 0x0383: return "mibound";
21
qemu_fdt_add_subnode(fdt, name);
24
case 0x0384: return "mdbase";
22
{
25
case 0x0385: return "mdbound";
23
- const char compat[] = "sifive,test1\0sifive,test0\0syscon";
26
- case 0x03a0: return "pmpcfg3";
24
- qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
27
+ case 0x03a0: return "pmpcfg0";
25
+ static const char * const compat[3] = {
28
+ case 0x03a1: return "pmpcfg1";
26
+ "sifive,test1", "sifive,test0", "syscon"
29
+ case 0x03a2: return "pmpcfg2";
27
+ };
30
+ case 0x03a3: return "pmpcfg3";
28
+ qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
31
+ case 0x03a4: return "pmpcfg4";
29
+ ARRAY_SIZE(compat));
32
+ case 0x03a5: return "pmpcfg5";
30
}
33
+ case 0x03a6: return "pmpcfg6";
31
qemu_fdt_setprop_cells(fdt, name, "reg",
34
+ case 0x03a7: return "pmpcfg7";
32
0x0, memmap[VIRT_TEST].base,
35
+ case 0x03a8: return "pmpcfg8";
36
+ case 0x03a9: return "pmpcfg9";
37
+ case 0x03aa: return "pmpcfg10";
38
+ case 0x03ab: return "pmpcfg11";
39
+ case 0x03ac: return "pmpcfg12";
40
+ case 0x03ad: return "pmpcfg13";
41
+ case 0x03ae: return "pmpcfg14";
42
+ case 0x03af: return "pmpcfg15";
43
case 0x03b0: return "pmpaddr0";
44
case 0x03b1: return "pmpaddr1";
45
case 0x03b2: return "pmpaddr2";
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
47
case 0x03bd: return "pmpaddr13";
48
case 0x03be: return "pmpaddr14";
49
case 0x03bf: return "pmpaddr15";
50
+ case 0x03c0: return "pmpaddr16";
51
+ case 0x03c1: return "pmpaddr17";
52
+ case 0x03c2: return "pmpaddr18";
53
+ case 0x03c3: return "pmpaddr19";
54
+ case 0x03c4: return "pmpaddr20";
55
+ case 0x03c5: return "pmpaddr21";
56
+ case 0x03c6: return "pmpaddr22";
57
+ case 0x03c7: return "pmpaddr23";
58
+ case 0x03c8: return "pmpaddr24";
59
+ case 0x03c9: return "pmpaddr25";
60
+ case 0x03ca: return "pmpaddr26";
61
+ case 0x03cb: return "pmpaddr27";
62
+ case 0x03cc: return "pmpaddr28";
63
+ case 0x03cd: return "pmpaddr29";
64
+ case 0x03ce: return "pmpaddr30";
65
+ case 0x03cf: return "pmpaddr31";
66
+ case 0x03d0: return "pmpaddr32";
67
+ case 0x03d1: return "pmpaddr33";
68
+ case 0x03d2: return "pmpaddr34";
69
+ case 0x03d3: return "pmpaddr35";
70
+ case 0x03d4: return "pmpaddr36";
71
+ case 0x03d5: return "pmpaddr37";
72
+ case 0x03d6: return "pmpaddr38";
73
+ case 0x03d7: return "pmpaddr39";
74
+ case 0x03d8: return "pmpaddr40";
75
+ case 0x03d9: return "pmpaddr41";
76
+ case 0x03da: return "pmpaddr42";
77
+ case 0x03db: return "pmpaddr43";
78
+ case 0x03dc: return "pmpaddr44";
79
+ case 0x03dd: return "pmpaddr45";
80
+ case 0x03de: return "pmpaddr46";
81
+ case 0x03df: return "pmpaddr47";
82
+ case 0x03e0: return "pmpaddr48";
83
+ case 0x03e1: return "pmpaddr49";
84
+ case 0x03e2: return "pmpaddr50";
85
+ case 0x03e3: return "pmpaddr51";
86
+ case 0x03e4: return "pmpaddr52";
87
+ case 0x03e5: return "pmpaddr53";
88
+ case 0x03e6: return "pmpaddr54";
89
+ case 0x03e7: return "pmpaddr55";
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
33
--
101
--
34
2.31.1
102
2.45.1
35
36
diff view generated by jsdifflib
[PULL 03/32] hw/riscv: Support the official CLINT DT bindings
Deleted patch
1
From: Bin Meng <bin.meng@windriver.com>
2
1
3
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
4
adds the official DT bindings for CLINT, which uses "sifive,clint0"
5
as the compatible string. "riscv,clint0" is now legacy and has to
6
be kept for backward compatibility of legacy systems.
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/sifive_u.c | 6 +++++-
14
hw/riscv/spike.c | 6 +++++-
15
hw/riscv/virt.c | 6 +++++-
16
3 files changed, 15 insertions(+), 3 deletions(-)
17
18
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/riscv/sifive_u.c
21
+++ b/hw/riscv/sifive_u.c
22
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
23
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
24
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
25
static const char * const ethclk_names[2] = { "pclk", "hclk" };
26
+ static const char * const clint_compat[2] = {
27
+ "sifive,clint0", "riscv,clint0"
28
+ };
29
30
if (ms->dtb) {
31
fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
32
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
33
nodename = g_strdup_printf("/soc/clint@%lx",
34
(long)memmap[SIFIVE_U_DEV_CLINT].base);
35
qemu_fdt_add_subnode(fdt, nodename);
36
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
37
+ qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
38
+ (char **)&clint_compat, ARRAY_SIZE(clint_compat));
39
qemu_fdt_setprop_cells(fdt, nodename, "reg",
40
0x0, memmap[SIFIVE_U_DEV_CLINT].base,
41
0x0, memmap[SIFIVE_U_DEV_CLINT].size);
42
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/riscv/spike.c
45
+++ b/hw/riscv/spike.c
46
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
47
uint32_t cpu_phandle, intc_phandle, phandle = 1;
48
char *name, *mem_name, *clint_name, *clust_name;
49
char *core_name, *cpu_name, *intc_name;
50
+ static const char * const clint_compat[2] = {
51
+ "sifive,clint0", "riscv,clint0"
52
+ };
53
54
fdt = s->fdt = create_device_tree(&s->fdt_size);
55
if (!fdt) {
56
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
57
(memmap[SPIKE_CLINT].size * socket);
58
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
59
qemu_fdt_add_subnode(fdt, clint_name);
60
- qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
61
+ qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
62
+ (char **)&clint_compat, ARRAY_SIZE(clint_compat));
63
qemu_fdt_setprop_cells(fdt, clint_name, "reg",
64
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
65
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
66
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/riscv/virt.c
69
+++ b/hw/riscv/virt.c
70
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
71
char *name, *clint_name, *plic_name, *clust_name;
72
hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
73
hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
74
+ static const char * const clint_compat[2] = {
75
+ "sifive,clint0", "riscv,clint0"
76
+ };
77
78
if (mc->dtb) {
79
fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
80
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
81
(memmap[VIRT_CLINT].size * socket);
82
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
83
qemu_fdt_add_subnode(fdt, clint_name);
84
- qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
85
+ qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
86
+ (char **)&clint_compat, ARRAY_SIZE(clint_compat));
87
qemu_fdt_setprop_cells(fdt, clint_name, "reg",
88
0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
89
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
90
--
91
2.31.1
92
93
diff view generated by jsdifflib
[PULL 04/32] hw/riscv: Support the official PLIC DT bindings
Deleted patch
1
From: Bin Meng <bin.meng@windriver.com>
2
1
3
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
4
compatible string in the upstream Linux kernel. "riscv,plic0" is
5
now legacy and has to be kept for backward compatibility of legacy
6
systems.
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/sifive_u.c | 6 +++++-
14
hw/riscv/virt.c | 6 +++++-
15
2 files changed, 10 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/riscv/sifive_u.c
20
+++ b/hw/riscv/sifive_u.c
21
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
22
static const char * const clint_compat[2] = {
23
"sifive,clint0", "riscv,clint0"
24
};
25
+ static const char * const plic_compat[2] = {
26
+ "sifive,plic-1.0.0", "riscv,plic0"
27
+ };
28
29
if (ms->dtb) {
30
fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
31
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
32
(long)memmap[SIFIVE_U_DEV_PLIC].base);
33
qemu_fdt_add_subnode(fdt, nodename);
34
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
35
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
36
+ qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
37
+ (char **)&plic_compat, ARRAY_SIZE(plic_compat));
38
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
39
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
40
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
41
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/riscv/virt.c
44
+++ b/hw/riscv/virt.c
45
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
46
static const char * const clint_compat[2] = {
47
"sifive,clint0", "riscv,clint0"
48
};
49
+ static const char * const plic_compat[2] = {
50
+ "sifive,plic-1.0.0", "riscv,plic0"
51
+ };
52
53
if (mc->dtb) {
54
fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
55
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
56
"#address-cells", FDT_PLIC_ADDR_CELLS);
57
qemu_fdt_setprop_cell(fdt, plic_name,
58
"#interrupt-cells", FDT_PLIC_INT_CELLS);
59
- qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
60
+ qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
61
+ (char **)&plic_compat, ARRAY_SIZE(plic_compat));
62
qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
63
qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
64
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
65
--
66
2.31.1
67
68
diff view generated by jsdifflib
[PULL 10/32] docs/system: Move the RISC-V -bios information to removed
Deleted patch
1
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
2
and sifive_u machines. This patch moves that change from the
3
deprecated.rst file to the removed-features.rst file and the
4
target-riscv.rst.
5
1
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
9
---
10
docs/system/deprecated.rst | 19 -------------------
11
docs/system/removed-features.rst | 5 +++++
12
docs/system/target-riscv.rst | 13 ++++++++++++-
13
3 files changed, 17 insertions(+), 20 deletions(-)
14
15
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/deprecated.rst
18
+++ b/docs/system/deprecated.rst
19
@@ -XXX,XX +XXX,XX @@ pcspk-audiodev=<name>``.
20
``tty`` and ``parport`` are aliases that will be removed. Instead, the
21
actual backend names ``serial`` and ``parallel`` should be used.
22
23
-RISC-V ``-bios`` (since 5.1)
24
-''''''''''''''''''''''''''''
25
-
26
-QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
27
-RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
28
-default behaviour to avoid breakages.
29
-
30
-QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
31
-
32
-QEMU 5.1 has three options:
33
- 1. ``-bios default`` - This is the current default behavior if no -bios option
34
- is included. This option will load the default OpenSBI firmware automatically.
35
- The firmware is included with the QEMU release and no user interaction is
36
- required. All a user needs to do is specify the kernel they want to boot
37
- with the -kernel option
38
- 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
39
- to the user to load all the images they need.
40
- 3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
41
-
42
Short-form boolean options (since 6.0)
43
''''''''''''''''''''''''''''''''''''''
44
45
diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst
46
index XXXXXXX..XXXXXXX 100644
47
--- a/docs/system/removed-features.rst
48
+++ b/docs/system/removed-features.rst
49
@@ -XXX,XX +XXX,XX @@ devices. Drives the board doesn't pick up can no longer be used with
50
This option was undocumented and not used in the field.
51
Use `-device usb-ccid`` instead.
52
53
+RISC-V firmware not booted by default (removed in 5.1)
54
+''''''''''''''''''''''''''''''''''''''''''''''''''''''
55
+
56
+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``
57
+for the RISC-V ``virt`` machine and ``sifive_u`` machine.
58
59
QEMU Machine Protocol (QMP) commands
60
------------------------------------
61
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
62
index XXXXXXX..XXXXXXX 100644
63
--- a/docs/system/target-riscv.rst
64
+++ b/docs/system/target-riscv.rst
65
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
66
riscv/shakti-c
67
riscv/sifive_u
68
69
-RISC-V CPU features
70
+RISC-V CPU firmware
71
-------------------
72
+
73
+When using the ``sifive_u`` or ``virt`` machine there are three different
74
+firmware boot options:
75
+1. ``-bios default`` - This is the default behaviour if no -bios option
76
+is included. This option will load the default OpenSBI firmware automatically.
77
+The firmware is included with the QEMU release and no user interaction is
78
+required. All a user needs to do is specify the kernel they want to boot
79
+with the -kernel option
80
+2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
81
+to the user to load all the images they need.
82
+3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware.
83
--
84
2.31.1
85
86
diff view generated by jsdifflib
[PULL 14/32] target/riscv/pmp: Add assert for ePMP operations
Deleted patch
1
Although we construct epmp_operation in such a way that it can only be
2
between 0 and 15 Coverity complains that we don't handle the other
3
possible cases. To fix Coverity and make it easier for humans to read
4
add a default case to the switch statement that calls
5
g_assert_not_reached().
6
1
7
Fixes: CID 1453108
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
11
Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
12
---
13
target/riscv/pmp.c | 4 ++++
14
1 file changed, 4 insertions(+)
15
16
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/pmp.c
19
+++ b/target/riscv/pmp.c
20
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
21
case 15:
22
*allowed_privs = PMP_READ;
23
break;
24
+ default:
25
+ g_assert_not_reached();
26
}
27
} else {
28
switch (epmp_operation) {
29
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
30
case 7:
31
*allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
32
break;
33
+ default:
34
+ g_assert_not_reached();
35
}
36
}
37
}
38
--
39
2.31.1
40
41
diff view generated by jsdifflib
[PULL 32/32] target/riscv: rvb: add b-ext version cpu option
[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Yu-Ming Chang <yumin686@andestech.com>
2
2
3
Default b-ext version is v0.93.
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
holding a zero value other than x0, the instruction will still attempt to write
6
the unmodified value back to the CSR and will cause any attendant side effects.
4
7
5
Signed-off-by: Frank Chang <frank.chang@sifive.com>
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
16
---
10
target/riscv/cpu.h | 3 +++
17
target/riscv/cpu.h | 4 ++++
11
target/riscv/cpu.c | 23 +++++++++++++++++++++++
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
12
2 files changed, 26 insertions(+)
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
13
21
14
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu.h
24
--- a/target/riscv/cpu.h
17
+++ b/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
18
@@ -XXX,XX +XXX,XX @@ enum {
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
19
#define PRIV_VERSION_1_10_0 0x00011000
27
void riscv_cpu_update_mask(CPURISCVState *env);
20
#define PRIV_VERSION_1_11_0 0x00011100
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
21
29
22
+#define BEXT_VERSION_0_93_0 0x00009300
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
23
#define VEXT_VERSION_0_07_1 0x00000701
31
+ target_ulong *ret_value);
24
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
25
enum {
33
target_ulong *ret_value,
26
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
34
target_ulong new_value, target_ulong write_mask);
27
target_ulong guest_phys_fault_addr;
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
28
36
target_ulong new_value,
29
target_ulong priv_ver;
37
target_ulong write_mask);
30
+ target_ulong bext_ver;
38
31
target_ulong vext_ver;
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
32
target_ulong misa;
40
+ Int128 *ret_value);
33
target_ulong misa_mask;
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
42
Int128 *ret_value,
35
43
Int128 new_value, Int128 write_mask);
36
char *priv_spec;
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
37
char *user_spec;
38
+ char *bext_spec;
39
char *vext_spec;
40
uint16_t vlen;
41
uint16_t elen;
42
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
43
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
44
--- a/target/riscv/cpu.c
46
--- a/target/riscv/csr.c
45
+++ b/target/riscv/cpu.c
47
+++ b/target/riscv/csr.c
46
@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
47
env->priv_ver = priv_ver;
49
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
51
int csrno,
52
- bool write_mask)
53
+ bool write)
54
{
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
56
bool read_only = get_field(csrno, 0xC00) == 3;
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
58
}
59
60
/* read / write check */
61
- if (write_mask && read_only) {
62
+ if (write && read_only) {
63
return RISCV_EXCP_ILLEGAL_INST;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
67
return RISCV_EXCP_NONE;
48
}
68
}
49
69
50
+static void set_bext_version(CPURISCVState *env, int bext_ver)
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
71
+ target_ulong *ret_value)
51
+{
72
+{
52
+ env->bext_ver = bext_ver;
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
74
+ if (ret != RISCV_EXCP_NONE) {
75
+ return ret;
76
+ }
77
+
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
53
+}
79
+}
54
+
80
+
55
static void set_vext_version(CPURISCVState *env, int vext_ver)
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
56
{
84
{
57
env->vext_ver = vext_ver;
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
58
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
59
CPURISCVState *env = &cpu->env;
87
if (ret != RISCV_EXCP_NONE) {
60
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
88
return ret;
61
int priv_version = PRIV_VERSION_1_11_0;
62
+ int bext_version = BEXT_VERSION_0_93_0;
63
int vext_version = VEXT_VERSION_0_07_1;
64
target_ulong target_misa = env->misa;
65
Error *local_err = NULL;
66
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
67
}
89
}
68
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
69
set_priv_version(env, priv_version);
91
return RISCV_EXCP_NONE;
70
+ set_bext_version(env, bext_version);
92
}
71
set_vext_version(env, vext_version);
93
72
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
73
if (cpu->cfg.mmu) {
95
+ Int128 *ret_value)
74
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
96
+{
75
}
97
+ RISCVException ret;
76
if (cpu->cfg.ext_b) {
77
target_misa |= RVB;
78
+
98
+
79
+ if (cpu->cfg.bext_spec) {
99
+ ret = riscv_csrrw_check(env, csrno, false);
80
+ if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
100
+ if (ret != RISCV_EXCP_NONE) {
81
+ bext_version = BEXT_VERSION_0_93_0;
101
+ return ret;
82
+ } else {
102
+ }
83
+ error_setg(errp,
103
+
84
+ "Unsupported bitmanip spec version '%s'",
104
+ if (csr_ops[csrno].read128) {
85
+ cpu->cfg.bext_spec);
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
86
+ return;
106
+ int128_zero(), int128_zero());
87
+ }
107
+ }
88
+ } else {
108
+
89
+ qemu_log("bitmanip version is not specified, "
109
+ /*
90
+ "use the default value v0.93\n");
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
91
+ }
111
+ * at all defined.
92
+ set_bext_version(env, bext_version);
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
93
}
113
+ * significant), for those, this fallback is correctly handling the
94
if (cpu->cfg.ext_v) {
114
+ * accesses
95
target_misa |= RVV;
115
+ */
96
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
116
+ target_ulong old_value;
97
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
98
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
118
+ (target_ulong)0,
99
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
119
+ (target_ulong)0);
100
+ DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
101
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
121
+ *ret_value = int128_make64(old_value);
102
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
122
+ }
103
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
123
+ return ret;
124
+}
125
+
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
127
Int128 *ret_value,
128
Int128 new_value, Int128 write_mask)
129
{
130
RISCVException ret;
131
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
133
+ ret = riscv_csrrw_check(env, csrno, true);
134
if (ret != RISCV_EXCP_NONE) {
135
return ret;
136
}
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/riscv/op_helper.c
140
+++ b/target/riscv/op_helper.c
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
142
}
143
144
target_ulong val = 0;
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
147
148
if (ret != RISCV_EXCP_NONE) {
149
riscv_raise_exception(env, ret, GETPC());
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
152
{
153
Int128 rv = int128_zero();
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
155
- int128_zero(),
156
- int128_zero());
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
158
159
if (ret != RISCV_EXCP_NONE) {
160
riscv_raise_exception(env, ret, GETPC());
104
--
161
--
105
2.31.1
162
2.45.1
106
107
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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