Series comparison

-[PULL 00/32] riscv-to-apply queue
+[PULL 0/2] riscv-to-apply queue
-The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100)
+The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
   Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
-for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:
+for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
-  target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)
+  hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
 ----------------------------------------------------------------
-Second RISC-V PR for QEMU 6.1
+Seventh RISC-V PR for QEMU 6.2
- - Update the PLIC and CLINT DT bindings
+ - Deprecate IF_NONE for SiFive OTP
- - Improve documentation for RISC-V machines
+ - Don't reset SiFive OTP content
  - Support direct kernel boot for microchip_pfsoc
  - Fix WFI exception behaviour
  - Improve CSR printing
  - Initial support for the experimental Bit Manip extension
 ----------------------------------------------------------------
-Alistair Francis (2):
+Philippe Mathieu-Daudé (1):
-      docs/system: Move the RISC-V -bios information to removed
+      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
       target/riscv/pmp: Add assert for ePMP operations
-Bin Meng (9):
+Thomas Huth (1):
-      hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
+      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
       hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
       hw/riscv: Support the official CLINT DT bindings
       hw/riscv: Support the official PLIC DT bindings
       docs/system/riscv: Correct the indentation level of supported devices
       docs/system/riscv: sifive_u: Document '-dtb' usage
       hw/riscv: Use macros for BIOS image names
       hw/riscv: microchip_pfsoc: Support direct kernel boot
       target/riscv: Remove unnecessary riscv_*_names[] declaration
-Changbin Du (1):
+ docs/about/deprecated.rst |  6 ++++++
-      target/riscv: Dump CSR mscratch/sscratch/satp
+ hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 files changed, 19 insertions(+), 9 deletions(-)
-Frank Chang (6):
-      target/riscv: rvb: count bits set
-      target/riscv: add gen_shifti() and gen_shiftiw() helper functions
-      target/riscv: rvb: single-bit instructions
-      target/riscv: rvb: generalized reverse
-      target/riscv: rvb: generalized or-combine
-      target/riscv: rvb: add b-ext version cpu option
-Jose Martins (1):
-      target/riscv: fix wfi exception behavior
-Kito Cheng (11):
-      target/riscv: reformat @sh format encoding for B-extension
-      target/riscv: rvb: count leading/trailing zeros
-      target/riscv: rvb: logic-with-negate
-      target/riscv: rvb: pack two words into one register
-      target/riscv: rvb: min/max instructions
-      target/riscv: rvb: sign-extend instructions
-      target/riscv: rvb: shift ones
-      target/riscv: rvb: rotate (left/right)
-      target/riscv: rvb: address calculation
-      target/riscv: rvb: add/shift with prefix zero-extend
-      target/riscv: rvb: support and turn on B-extension from command line
-LIU Zhiwei (1):
-      target/riscv: Pass the same value to oprsz and maxsz.
-Philippe Mathieu-Daudé (1):
-      target/riscv: Do not include 'pmp.h' in user emulation
- docs/system/deprecated.rst                 |  19 --
- docs/system/removed-features.rst           |   5 +
- docs/system/riscv/microchip-icicle-kit.rst |  50 +++-
- docs/system/riscv/sifive_u.rst             |  77 +++--
- docs/system/target-riscv.rst               |  13 +-
- include/hw/riscv/boot.h                    |   5 +
- target/riscv/cpu.h                         |   9 +-
- target/riscv/cpu_bits.h                    |   1 +
- target/riscv/helper.h                      |   6 +
- target/riscv/insn32.decode                 |  87 +++++-
- hw/riscv/microchip_pfsoc.c                 |  81 +++++-
- hw/riscv/sifive_u.c                        |  24 +-
- hw/riscv/spike.c                           |  12 +-
- hw/riscv/virt.c                            |  25 +-
- target/riscv/bitmanip_helper.c             |  90 ++++++
- target/riscv/cpu.c                         |  38 ++-
- target/riscv/op_helper.c                   |  11 +-
- target/riscv/pmp.c                         |   4 +
- target/riscv/translate.c                   | 306 ++++++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc    | 438 +++++++++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvi.c.inc    |  54 +---
- target/riscv/insn_trans/trans_rvv.c.inc    |  89 +++---
- target/riscv/meson.build                   |   1 +
-files changed, 1260 insertions(+), 185 deletions(-)
- create mode 100644 target/riscv/bitmanip_helper.c
- create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

-[PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
-we can use the new helper to set the clock name for the ethernet
-controller node.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/sifive_u.c | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     int cpu;
-     uint32_t *cells;
-     char *nodename;
--    char ethclk_names[] = "pclk\0hclk";
-     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
-     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
-+    static const char * const ethclk_names[2] = { "pclk", "hclk" };
-     if (ms->dtb) {
-         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
-     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
-         prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
--    qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
--        sizeof(ethclk_names));
-+    qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
-+        (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
-     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
-         s->soc.gem.conf.macaddr.a, ETH_ALEN);
-     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
---
-.31.1

-[PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
-we can use the new helper to set the compatible strings for the
-SiFive test device node.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 7 +++++--
-file changed, 5 insertions(+), 2 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-         (long)memmap[VIRT_TEST].base);
-     qemu_fdt_add_subnode(fdt, name);
-     {
--        const char compat[] = "sifive,test1\0sifive,test0\0syscon";
--        qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
-+        static const char * const compat[3] = {
-+            "sifive,test1", "sifive,test0", "syscon"
-+        };
-+        qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
-+                                      ARRAY_SIZE(compat));
-     }
-     qemu_fdt_setprop_cells(fdt, name, "reg",
-x0, memmap[VIRT_TEST].base,
---
-.31.1

-[PULL 03/32] hw/riscv: Support the official CLINT DT bindings
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
-adds the official DT bindings for CLINT, which uses "sifive,clint0"
-as the compatible string. "riscv,clint0" is now legacy and has to
-be kept for backward compatibility of legacy systems.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/sifive_u.c | 6 +++++-
- hw/riscv/spike.c    | 6 +++++-
- hw/riscv/virt.c     | 6 +++++-
-files changed, 15 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
-     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
-     static const char * const ethclk_names[2] = { "pclk", "hclk" };
-+    static const char * const clint_compat[2] = {
-+        "sifive,clint0", "riscv,clint0"
-+    };
-     if (ms->dtb) {
-         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     nodename = g_strdup_printf("/soc/clint@%lx",
-         (long)memmap[SIFIVE_U_DEV_CLINT].base);
-     qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
-+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
-+        (char **)&clint_compat, ARRAY_SIZE(clint_compat));
-     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-x0, memmap[SIFIVE_U_DEV_CLINT].base,
-x0, memmap[SIFIVE_U_DEV_CLINT].size);
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-     uint32_t cpu_phandle, intc_phandle, phandle = 1;
-     char *name, *mem_name, *clint_name, *clust_name;
-     char *core_name, *cpu_name, *intc_name;
-+    static const char * const clint_compat[2] = {
-+        "sifive,clint0", "riscv,clint0"
-+    };
-     fdt = s->fdt = create_device_tree(&s->fdt_size);
-     if (!fdt) {
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-             (memmap[SPIKE_CLINT].size * socket);
-         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
-         qemu_fdt_add_subnode(fdt, clint_name);
--        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
-+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
-+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
-         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
-x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
-         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-     char *name, *clint_name, *plic_name, *clust_name;
-     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
-     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
-+    static const char * const clint_compat[2] = {
-+        "sifive,clint0", "riscv,clint0"
-+    };
-     if (mc->dtb) {
-         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-             (memmap[VIRT_CLINT].size * socket);
-         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
-         qemu_fdt_add_subnode(fdt, clint_name);
--        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
-+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
-+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
-         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
-x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
-         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
---
-.31.1

-[PULL 04/32] hw/riscv: Support the official PLIC DT bindings
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
-compatible string in the upstream Linux kernel. "riscv,plic0" is
-now legacy and has to be kept for backward compatibility of legacy
-systems.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/sifive_u.c | 6 +++++-
- hw/riscv/virt.c     | 6 +++++-
-files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     static const char * const clint_compat[2] = {
-         "sifive,clint0", "riscv,clint0"
-     };
-+    static const char * const plic_compat[2] = {
-+        "sifive,plic-1.0.0", "riscv,plic0"
-+    };
-     if (ms->dtb) {
-         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-         (long)memmap[SIFIVE_U_DEV_PLIC].base);
-     qemu_fdt_add_subnode(fdt, nodename);
-     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
-+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
-+        (char **)&plic_compat, ARRAY_SIZE(plic_compat));
-     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
-     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-     static const char * const clint_compat[2] = {
-         "sifive,clint0", "riscv,clint0"
-     };
-+    static const char * const plic_compat[2] = {
-+        "sifive,plic-1.0.0", "riscv,plic0"
-+    };
-     if (mc->dtb) {
-         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-             "#address-cells", FDT_PLIC_ADDR_CELLS);
-         qemu_fdt_setprop_cell(fdt, plic_name,
-             "#interrupt-cells", FDT_PLIC_INT_CELLS);
--        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
-+        qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
-+            (char **)&plic_compat, ARRAY_SIZE(plic_compat));
-         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
-         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
-             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
---
-.31.1

-[PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-The supported device bullet list has an additional space before each
-entry, which makes a wrong indentation level. Correct it.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- docs/system/riscv/microchip-icicle-kit.rst | 20 +++++++--------
- docs/system/riscv/sifive_u.rst             | 30 +++++++++++-----------
-files changed, 25 insertions(+), 25 deletions(-)
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/microchip-icicle-kit.rst
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
-@@ -XXX,XX +XXX,XX @@ Supported devices
- The ``microchip-icicle-kit`` machine supports the following devices:
-- * 1 E51 core
-- * 4 U54 cores
-- * Core Level Interruptor (CLINT)
-- * Platform-Level Interrupt Controller (PLIC)
-- * L2 Loosely Integrated Memory (L2-LIM)
-- * DDR memory controller
-- * 5 MMUARTs
-- * 1 DMA controller
-- * 2 GEM Ethernet controllers
-- * 1 SDHC storage controller
-+* 1 E51 core
-+* 4 U54 cores
-+* Core Level Interruptor (CLINT)
-+* Platform-Level Interrupt Controller (PLIC)
-+* L2 Loosely Integrated Memory (L2-LIM)
-+* DDR memory controller
-+* 5 MMUARTs
-+* 1 DMA controller
-+* 2 GEM Ethernet controllers
-+* 1 SDHC storage controller
- Boot options
- ------------
-diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/sifive_u.rst
-+++ b/docs/system/riscv/sifive_u.rst
-@@ -XXX,XX +XXX,XX @@ Supported devices
- The ``sifive_u`` machine supports the following devices:
-- * 1 E51 / E31 core
-- * Up to 4 U54 / U34 cores
-- * Core Level Interruptor (CLINT)
-- * Platform-Level Interrupt Controller (PLIC)
-- * Power, Reset, Clock, Interrupt (PRCI)
-- * L2 Loosely Integrated Memory (L2-LIM)
-- * DDR memory controller
-- * 2 UARTs
-- * 1 GEM Ethernet controller
-- * 1 GPIO controller
-- * 1 One-Time Programmable (OTP) memory with stored serial number
-- * 1 DMA controller
-- * 2 QSPI controllers
-- * 1 ISSI 25WP256 flash
-- * 1 SD card in SPI mode
-+* 1 E51 / E31 core
-+* Up to 4 U54 / U34 cores
-+* Core Level Interruptor (CLINT)
-+* Platform-Level Interrupt Controller (PLIC)
-+* Power, Reset, Clock, Interrupt (PRCI)
-+* L2 Loosely Integrated Memory (L2-LIM)
-+* DDR memory controller
-+* 2 UARTs
-+* 1 GEM Ethernet controller
-+* 1 GPIO controller
-+* 1 One-Time Programmable (OTP) memory with stored serial number
-+* 1 DMA controller
-+* 2 QSPI controllers
-+* 1 ISSI 25WP256 flash
-+* 1 SD card in SPI mode
- Please note the real world HiFive Unleashed board has a fixed configuration of
-E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
---
-.31.1

-[PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Update the 'sifive_u' machine documentation to mention the '-dtb'
-option that can be used to pass a custom DTB to QEMU.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- docs/system/riscv/sifive_u.rst | 47 +++++++++++++++++++++++++++++-----
-file changed, 41 insertions(+), 6 deletions(-)
-diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/sifive_u.rst
-+++ b/docs/system/riscv/sifive_u.rst
-@@ -XXX,XX +XXX,XX @@ Hardware configuration information
- ----------------------------------
- The ``sifive_u`` machine automatically generates a device tree blob ("dtb")
--which it passes to the guest. This provides information about the addresses,
--interrupt lines and other configuration of the various devices in the system.
--Guest software should discover the devices that are present in the generated
--DTB instead of using a DTB for the real hardware, as some of the devices are
--not modeled by QEMU and trying to access these devices may cause unexpected
--behavior.
-+which it passes to the guest, if there is no ``-dtb`` option. This provides
-+information about the addresses, interrupt lines and other configuration of
-+the various devices in the system. Guest software should discover the devices
-+that are present in the generated DTB instead of using a DTB for the real
-+hardware, as some of the devices are not modeled by QEMU and trying to access
-+these devices may cause unexpected behavior.
-+
-+If users want to provide their own DTB, they can use the ``-dtb`` option.
-+These DTBs should have the following requirements:
-+
-+* The /cpus node should contain at least one subnode for E51 and the number
-+  of subnodes should match QEMU's ``-smp`` option
-+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
-+* Should contain a node for the CLINT device with a compatible string
-+  "riscv,clint0" if using with OpenSBI BIOS images
- Boot options
- ------------
-@@ -XXX,XX +XXX,XX @@ To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine:
-       -initrd /path/to/rootfs.ext4 \
-       -append "root=/dev/ram"
-+Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT
-+node in fu540-c000.dtsi in the Linux kernel,
-+
-+.. code-block:: none
-+
-+    clint: clint@2000000 {
-+        compatible = "riscv,clint0";
-+        interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-+                               &cpu1_intc 3 &cpu1_intc 7
-+                               &cpu2_intc 3 &cpu2_intc 7
-+                               &cpu3_intc 3 &cpu3_intc 7
-+                               &cpu4_intc 3 &cpu4_intc 7>;
-+        reg = <0x00 0x2000000 0x00 0x10000>;
-+    };
-+
-+with the following command line options:
-+
-+.. code-block:: bash
-+
-+  $ qemu-system-riscv64 -M sifive_u -smp 5 -m 8G \
-+      -display none -serial stdio \
-+      -kernel arch/riscv/boot/Image \
-+      -dtb arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb \
-+      -initrd /path/to/rootfs.ext4 \
-+      -append "root=/dev/ram"
-+
- To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine
- in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
- fix the 32-bit boot issue for Linux kernel v5.10.
---
-.31.1

-[PULL 07/32] hw/riscv: Use macros for BIOS image names
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-The OpenSBI BIOS image names are used by many RISC-V machines.
-Let's define macros for them.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/boot.h | 5 +++++
- hw/riscv/sifive_u.c     | 6 ++----
- hw/riscv/spike.c        | 6 ++----
- hw/riscv/virt.c         | 6 ++----
-files changed, 11 insertions(+), 12 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/loader.h"
- #include "hw/riscv/riscv_hart.h"
-+#define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
-+#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
-+#define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
-+#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
-+
- bool riscv_is_32bit(RISCVHartArrayState *harts);
- target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-     if (riscv_is_32bit(&s->soc.u_cpus)) {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv32-generic-fw_dynamic.bin",
--                                    start_addr, NULL);
-+                                    RISCV32_BIOS_BIN, start_addr, NULL);
-     } else {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv64-generic-fw_dynamic.bin",
--                                    start_addr, NULL);
-+                                    RISCV64_BIOS_BIN, start_addr, NULL);
-     }
-     if (machine->kernel_filename) {
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-      */
-     if (riscv_is_32bit(&s->soc[0])) {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv32-generic-fw_dynamic.elf",
--                                    memmap[SPIKE_DRAM].base,
-+                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
-                                     htif_symbol_callback);
-     } else {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv64-generic-fw_dynamic.elf",
--                                    memmap[SPIKE_DRAM].base,
-+                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
-                                     htif_symbol_callback);
-     }
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-     if (riscv_is_32bit(&s->soc[0])) {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv32-generic-fw_dynamic.bin",
--                                    start_addr, NULL);
-+                                    RISCV32_BIOS_BIN, start_addr, NULL);
-     } else {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
--                                    "opensbi-riscv64-generic-fw_dynamic.bin",
--                                    start_addr, NULL);
-+                                    RISCV64_BIOS_BIN, start_addr, NULL);
-     }
-     if (machine->kernel_filename) {
---
-.31.1

-[PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-At present the Microchip Icicle Kit machine only supports using
-'-bios' to load the HSS, and does not support '-kernel' for direct
-kernel booting just like other RISC-V machines do. One has to use
-U-Boot which is chain-loaded by HSS, to load a kernel for testing.
-This is not so convenient.
-Adding '-kernel' support together with the existing '-bios', we
-follow the following table to select which payload we execute:
-  -bios |    -kernel | payload
-  ------+------------+--------
-      N |          N | HSS
-      Y | don't care | HSS
-      N |          Y | kernel
-This ensures backwards compatibility with how we used to expose
-'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
-must be present to provide a valid device tree for the board,
-as we don't generate device tree.
-When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
-is used to boot a payload like U-Boot or OS kernel directly.
-Documentation is updated to describe the direct kernel boot. Note
-as of today there is still no PolarFire SoC support in the upstream
-Linux kernel hence the document does not include instructions for
-that. It will be updated in the future.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- docs/system/riscv/microchip-icicle-kit.rst | 30 ++++++--
- hw/riscv/microchip_pfsoc.c                 | 81 +++++++++++++++++++++-
-files changed, 103 insertions(+), 8 deletions(-)
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/microchip-icicle-kit.rst
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
-@@ -XXX,XX +XXX,XX @@ Boot options
- The ``microchip-icicle-kit`` machine can start using the standard -bios
- functionality for loading its BIOS image, aka Hart Software Services (HSS_).
--HSS loads the second stage bootloader U-Boot from an SD card. It does not
--support direct kernel loading via the -kernel option. One has to load kernel
--from U-Boot.
-+HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
-+can be loaded from U-Boot. It also supports direct kernel booting via the
-+-kernel option along with the device tree blob via -dtb. When direct kernel
-+boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload
-+like U-Boot or OS kernel directly.
-+
-+The user provided DTB should have the following requirements:
-+
-+* The /cpus node should contain at least one subnode for E51 and the number
-+  of subnodes should match QEMU's ``-smp`` option
-+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
-+* Should contain a node for the CLINT device with a compatible string
-+  "riscv,clint0"
-+
-+QEMU follows below truth table to select which payload to execute:
-+
-+=====  ========== =======
-+-bios     -kernel payload
-+=====  ========== =======
-+    N           N     HSS
-+    Y  don't care     HSS
-+    N           Y  kernel
-+=====  ========== =======
- The memory is set to 1537 MiB by default which is the minimum required high
- memory size by HSS. A sanity check on ram size is performed in the machine
- init routine to prompt user to increase the RAM size to > 1537 MiB when less
- than 1537 MiB ram is detected.
--Boot the machine
------------------
-+Running HSS
-+-----------
- HSS 2020.12 release is tested at the time of writing. To build an HSS image
- that can be booted by the ``microchip-icicle-kit`` machine, type the following
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
-+++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/microchip_pfsoc.h"
- #include "hw/intc/sifive_clint.h"
- #include "hw/intc/sifive_plic.h"
-+#include "sysemu/device_tree.h"
- #include "sysemu/sysemu.h"
- /*
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
-     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
-     uint64_t mem_high_size;
-+    hwaddr firmware_load_addr;
-+    const char *firmware_name;
-+    bool kernel_as_payload = false;
-+    target_ulong firmware_end_addr, kernel_start_addr;
-+    uint64_t kernel_entry;
-+    uint32_t fdt_load_addr;
-     DriveInfo *dinfo = drive_get_next(IF_SD);
-     /* Sanity check on RAM size */
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-                                 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
-                                 mem_high_alias);
--    /* Load the firmware */
--    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
--
-     /* Attach an SD card */
-     if (dinfo) {
-         CadenceSDHCIState *sdhci = &(s->soc.sdhci);
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-                                 &error_fatal);
-         qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
-     }
-+
-+    /*
-+     * We follow the following table to select which payload we execute.
-+     *
-+     *  -bios |    -kernel | payload
-+     * -------+------------+--------
-+     *      N |          N | HSS
-+     *      Y | don't care | HSS
-+     *      N |          Y | kernel
-+     *
-+     * This ensures backwards compatibility with how we used to expose -bios
-+     * to users but allows them to run through direct kernel booting as well.
-+     *
-+     * When -kernel is used for direct boot, -dtb must be present to provide
-+     * a valid device tree for the board, as we don't generate device tree.
-+     */
-+
-+    if (machine->kernel_filename && machine->dtb) {
-+        int fdt_size;
-+        machine->fdt = load_device_tree(machine->dtb, &fdt_size);
-+        if (!machine->fdt) {
-+            error_report("load_device_tree() failed");
-+            exit(1);
-+        }
-+
-+        firmware_name = RISCV64_BIOS_BIN;
-+        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
-+        kernel_as_payload = true;
-+    }
-+
-+    if (!kernel_as_payload) {
-+        firmware_name = BIOS_FILENAME;
-+        firmware_load_addr = RESET_VECTOR;
-+    }
-+
-+    /* Load the firmware */
-+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
-+                                                     firmware_load_addr, NULL);
-+
-+    if (kernel_as_payload) {
-+        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
-+                                                         firmware_end_addr);
-+
-+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-+                                         kernel_start_addr, NULL);
-+
-+        if (machine->initrd_filename) {
-+            hwaddr start;
-+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-+                                           machine->ram_size, kernel_entry,
-+                                           &start);
-+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-+                                  "linux,initrd-start", start);
-+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-+                                  "linux,initrd-end", end);
-+        }
-+
-+        if (machine->kernel_cmdline) {
-+            qemu_fdt_setprop_string(machine->fdt, "/chosen",
-+                                    "bootargs", machine->kernel_cmdline);
-+        }
-+
-+        /* Compute the fdt load address in dram */
-+        fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-+                                       machine->ram_size, machine->fdt);
-+        /* Load the reset vector */
-+        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
-+                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
-+                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
-+                                  kernel_entry, fdt_load_addr, machine->fdt);
-+    }
- }
- static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
---
-.31.1

-[PULL 09/32] target/riscv: fix wfi exception behavior
+Deleted patch
-From: Jose Martins <josemartins90@gmail.com>
-The wfi exception trigger behavior should take into account user mode,
-hstatus.vtw, and the fact the an wfi might raise different types of
-exceptions depending on various factors:
-If supervisor mode is not present:
-- an illegal instruction exception should be generated if user mode
-executes and wfi instruction and mstatus.tw = 1.
-If supervisor mode is present:
-- when a wfi instruction is executed, an illegal exception should be triggered
-if either the current mode is user or the mode is supervisor and mstatus.tw is
-set.
-Plus, if the hypervisor extensions are enabled:
-- a virtual instruction exception should be raised when a wfi is executed from
-virtual-user or virtual-supervisor and hstatus.vtw is set.
-Signed-off-by: Jose Martins <josemartins90@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210420213656.85148-1-josemartins90@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_bits.h  |  1 +
- target/riscv/op_helper.c | 11 ++++++++---
-files changed, 9 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
- #define HSTATUS_HU           0x00000200
- #define HSTATUS_VGEIN        0x0003F000
- #define HSTATUS_VTVM         0x00100000
-+#define HSTATUS_VTW          0x00200000
- #define HSTATUS_VTSR         0x00400000
- #define HSTATUS_VSXL         0x300000000
-diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/op_helper.c
-+++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
- void helper_wfi(CPURISCVState *env)
- {
-     CPUState *cs = env_cpu(env);
-+    bool rvs = riscv_has_ext(env, RVS);
-+    bool prv_u = env->priv == PRV_U;
-+    bool prv_s = env->priv == PRV_S;
--    if ((env->priv == PRV_S &&
--        get_field(env->mstatus, MSTATUS_TW)) ||
--        riscv_cpu_virt_enabled(env)) {
-+    if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
-+        (rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
-+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    } else if (riscv_cpu_virt_enabled(env) && (prv_u ||
-+        (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
-         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
-     } else {
-         cs->halted = 1;
---
-.31.1

-[PULL 10/32] docs/system: Move the RISC-V -bios information to removed
+[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
-QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
+From: Thomas Huth <thuth@redhat.com>
 and sifive_u machines. This patch moves that change from the
 deprecated.rst file to the removed-features.rst file and the
 target-riscv.rst.
+Configuring a drive with "if=none" is meant for creation of a backend
+only, it should not get automatically assigned to a device frontend.
+Use "if=pflash" for the One-Time-Programmable device instead (like
+it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
+Since the old way of configuring the device has already been published
+with the previous QEMU versions, we cannot remove this immediately, but
+have to deprecate it and support it for at least two more releases.
+Signed-off-by: Thomas Huth <thuth@redhat.com>
+Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Markus Armbruster <armbru@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20211119102549.217755-1-thuth@redhat.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
 ---
- docs/system/deprecated.rst       | 19 -------------------
+ docs/about/deprecated.rst | 6 ++++++
- docs/system/removed-features.rst |  5 +++++
+ hw/misc/sifive_u_otp.c    | 9 ++++++++-
- docs/system/target-riscv.rst     | 13 ++++++++++++-
+files changed, 14 insertions(+), 1 deletion(-)
 files changed, 17 insertions(+), 20 deletions(-)
-diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
+diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/deprecated.rst
+--- a/docs/about/deprecated.rst
-+++ b/docs/system/deprecated.rst
++++ b/docs/about/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ pcspk-audiodev=<name>``.
+@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
- ``tty`` and ``parport`` are aliases that will be removed. Instead, the
+ However, short-form booleans are deprecated and full explicit ``arg_name=on``
- actual backend names ``serial`` and ``parallel`` should be used.
+ form is preferred.
--RISC-V ``-bios`` (since 5.1)
++``-drive if=none`` for the sifive_u OTP device (since 6.2)
--''''''''''''''''''''''''''''
++''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 -
 -QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
 -RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
 -default behaviour to avoid breakages.
 -
 -QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
 -
 -QEMU 5.1 has three options:
 - 1. ``-bios default`` - This is the current default behavior if no -bios option
 -      is included. This option will load the default OpenSBI firmware automatically.
 -      The firmware is included with the QEMU release and no user interaction is
 -      required. All a user needs to do is specify the kernel they want to boot
 -      with the -kernel option
 - 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
 -      to the user to load all the images they need.
 - 3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
 -
  Short-form boolean options (since 6.0)
  ''''''''''''''''''''''''''''''''''''''
 diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/removed-features.rst
 +++ b/docs/system/removed-features.rst
@@ -XXX,XX +XXX,XX @@ devices.  Drives the board doesn't pick up can no longer be used with
  This option was undocumented and not used in the field.
  Use `-device usb-ccid`` instead.
 +RISC-V firmware not booted by default (removed in 5.1)
 +''''''''''''''''''''''''''''''''''''''''''''''''''''''
 +
-+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``
++Using ``-drive if=none`` to configure the OTP device of the sifive_u
-+for the RISC-V ``virt`` machine and ``sifive_u`` machine.
++RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
 +
  QEMU Machine Protocol (QMP) commands
  ------------------------------------
-diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
+diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-riscv.rst
+--- a/hw/misc/sifive_u_otp.c
-+++ b/docs/system/target-riscv.rst
++++ b/hw/misc/sifive_u_otp.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
-    riscv/shakti-c
+                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
-    riscv/sifive_u
+     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
--RISC-V CPU features
+-    dinfo = drive_get_next(IF_NONE);
-+RISC-V CPU firmware
++    dinfo = drive_get_next(IF_PFLASH);
- -------------------
++    if (!dinfo) {
-+
++        dinfo = drive_get_next(IF_NONE);
-+When using the ``sifive_u`` or ``virt`` machine there are three different
++        if (dinfo) {
-+firmware boot options:
++            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
-+1. ``-bios default`` - This is the default behaviour if no -bios option
++                        "use \"-drive if=pflash\" instead.");
-+is included. This option will load the default OpenSBI firmware automatically.
++        }
-+The firmware is included with the QEMU release and no user interaction is
++    }
-+required. All a user needs to do is specify the kernel they want to boot
+     if (dinfo) {
-+with the -kernel option
+         int ret;
-+2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
+         uint64_t perm;
 +to the user to load all the images they need.
 +3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware.
 --
 .31.1

-[PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation
+[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Physical Memory Protection is a system feature.
+Once a "One Time Programmable" is programmed, it shouldn't be reset.
 Avoid polluting the user-mode emulation by its definitions.
+Do not re-initialize the OTP content in the DeviceReset handler,
+initialize it once in the DeviceRealize one.
+Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
 Message-id: 20210516205333.696094-1-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 2 ++
+ hw/misc/sifive_u_otp.c | 13 +++++--------
-file changed, 2 insertions(+)
+file changed, 5 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/hw/misc/sifive_u_otp.c
-+++ b/target/riscv/cpu.h
++++ b/hw/misc/sifive_u_otp.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
- typedef struct CPURISCVState CPURISCVState;
+             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
+                 error_setg(errp, "failed to read the initial flash content");
-+#if !defined(CONFIG_USER_ONLY)
++                return;
- #include "pmp.h"
+             }
-+#endif
+         }
+     }
- #define RV_VLEN_MAX 256
+-}
+-
 -static void sifive_u_otp_reset(DeviceState *dev)
 -{
 -    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
      /* Initialize all fuses' initial value to 0xFFs */
      memset(s->fuse, 0xff, sizeof(s->fuse));
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
          serial_data = s->serial;
          if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
                         &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
 -            error_report("write error index<%d>", index);
 +            error_setg(errp, "failed to write index<%d>", index);
 +            return;
          }
          serial_data = ~(s->serial);
          if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
                         &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
 -            error_report("write error index<%d>", index + 1);
 +            error_setg(errp, "failed to write index<%d>", index + 1);
 +            return;
          }
      }
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
      device_class_set_props(dc, sifive_u_otp_properties);
      dc->realize = sifive_u_otp_realize;
 -    dc->reset = sifive_u_otp_reset;
  }
  static const TypeInfo sifive_u_otp_info = {
 --
 .31.1

-[PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration
+Deleted patch
-From: Bin Meng <bmeng.cn@gmail.com>
-riscv_excp_names[] and riscv_intr_names[] are only referenced by
-target/riscv/cpu.c locally.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 2 --
- target/riscv/cpu.c | 4 ++--
-files changed, 2 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
- extern const char * const riscv_int_regnames[];
- extern const char * const riscv_fpr_regnames[];
--extern const char * const riscv_excp_names[];
--extern const char * const riscv_intr_names[];
- const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
- void riscv_cpu_do_interrupt(CPUState *cpu);
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char * const riscv_fpr_regnames[] = {
-   "f30/ft10", "f31/ft11"
- };
--const char * const riscv_excp_names[] = {
-+static const char * const riscv_excp_names[] = {
-     "misaligned_fetch",
-     "fault_fetch",
-     "illegal_instruction",
-@@ -XXX,XX +XXX,XX @@ const char * const riscv_excp_names[] = {
-     "guest_store_page_fault",
- };
--const char * const riscv_intr_names[] = {
-+static const char * const riscv_intr_names[] = {
-     "u_software",
-     "s_software",
-     "vs_software",
---
-.31.1

-[PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp
+Deleted patch
-From: Changbin Du <changbin.du@gmail.com>
-This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
-the output of CSR mtval/stval.
-Signed-off-by: Changbin Du <changbin.du@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 20210519155738.20486-1-changbin.du@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.c | 7 +++++--
-file changed, 5 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     if (riscv_has_ext(env, RVH)) {
-         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
-     }
--    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
--    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
-+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
-+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
-     if (riscv_has_ext(env, RVH)) {
-         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
-         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
-     }
-+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
-+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
- #endif
-     for (i = 0; i < 32; i++) {
---
-.31.1

-[PULL 14/32] target/riscv/pmp: Add assert for ePMP operations
+Deleted patch
-Although we construct epmp_operation in such a way that it can only be
-between 0 and 15 Coverity complains that we don't handle the other
-possible cases. To fix Coverity and make it easier for humans to read
-add a default case to the switch statement that calls
-g_assert_not_reached().
-Fixes: CID 1453108
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
----
- target/riscv/pmp.c | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-                     case 15:
-                         *allowed_privs = PMP_READ;
-                         break;
-+                    default:
-+                        g_assert_not_reached();
-                     }
-                 } else {
-                     switch (epmp_operation) {
-@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-                     case 7:
-                         *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-                         break;
-+                    default:
-+                        g_assert_not_reached();
-                     }
-                 }
-             }
---
-.31.1

-[PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz.
+Deleted patch
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
-is still zero(as we don't use this field), simd_desc will trigger an
-assert.
-Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
-Here we pass the value to maxsz and oprsz to bypass the assert.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rvv.c.inc | 89 ++++++++++++++-----------
-file changed, 50 insertions(+), 39 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
-      * The first part is vlen in bytes, encoded in maxsz of simd_desc.
-      * The second part is lmul, encoded in data of simd_desc.
-      */
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     gen_get_gpr(base, rs1);
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
-     mask = tcg_temp_new_ptr();
-     base = tcg_temp_new();
-     stride = tcg_temp_new();
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     gen_get_gpr(base, rs1);
-     gen_get_gpr(stride, rs2);
-@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-     mask = tcg_temp_new_ptr();
-     index = tcg_temp_new_ptr();
-     base = tcg_temp_new();
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     gen_get_gpr(base, rs1);
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
-     dest = tcg_temp_new_ptr();
-     mask = tcg_temp_new_ptr();
-     base = tcg_temp_new();
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     gen_get_gpr(base, rs1);
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-     mask = tcg_temp_new_ptr();
-     index = tcg_temp_new_ptr();
-     base = tcg_temp_new();
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     gen_get_gpr(base, rs1);
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
--                           cpu_env, 0, s->vlen / 8, data, fn);
-+                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
-     }
-     gen_set_label(over);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
-     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
-     data = FIELD_DP32(data, VDATA, VM, vm);
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
-     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
-     data = FIELD_DP32(data, VDATA, VM, vm);
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1),
-                            vreg_ofs(s, a->rs2),
--                           cpu_env, 0, s->vlen / 8,
-+                           cpu_env, s->vlen / 8, s->vlen / 8,
-                            data, fn);
-         gen_set_label(over);
-         return true;
-@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1),
-                            vreg_ofs(s, a->rs2),
--                           cpu_env, 0, s->vlen / 8, data, fn);
-+                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
-         gen_set_label(over);
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew]);        \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew]);                           \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew]);        \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew]);                           \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
-             };
-             tcg_gen_ext_tl_i64(s1_i64, s1);
--            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew](dest, s1_i64, cpu_env, desc);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
-             s1 = tcg_const_i64(simm);
-             dest = tcg_temp_new_ptr();
--            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew](dest, s1, cpu_env, desc);
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew - 1]);    \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew - 1]);                       \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-     dest = tcg_temp_new_ptr();
-     mask = tcg_temp_new_ptr();
-     src2 = tcg_temp_new_ptr();
--    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
-                            vreg_ofs(s, a->rs1),                  \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,      \
--                           s->vlen / 8, data, fns[s->sew - 1]);  \
-+                           vreg_ofs(s, a->rs2), cpu_env,         \
-+                           s->vlen / 8, s->vlen / 8, data,       \
-+                           fns[s->sew - 1]);                     \
-         gen_set_label(over);                                     \
-         return true;                                             \
-     }                                                            \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew - 1]);    \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew - 1]);                       \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew - 1]);    \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew - 1]);                       \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
-             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-             dest = tcg_temp_new_ptr();
--            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew - 1]);    \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew - 1]);                       \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fns[s->sew - 1]);    \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data,         \
-+                           fns[s->sew - 1]);                       \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                            vreg_ofs(s, a->rs1),                    \
--                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
--                           s->vlen / 8, data, fn);                 \
-+                           vreg_ofs(s, a->rs2), cpu_env,           \
-+                           s->vlen / 8, s->vlen / 8, data, fn);    \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = tcg_temp_new();
--        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = tcg_temp_new();
--        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-+        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
-                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
--                           cpu_env, 0, s->vlen / 8, data, fn);     \
-+                           cpu_env, s->vlen / 8, s->vlen / 8,      \
-+                           data, fn);                              \
-         gen_set_label(over);                                       \
-         return true;                                               \
-     }                                                              \
-@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
-             gen_helper_viota_m_w, gen_helper_viota_m_d,
-         };
-         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
--                           vreg_ofs(s, a->rs2), cpu_env, 0,
--                           s->vlen / 8, data, fns[s->sew]);
-+                           vreg_ofs(s, a->rs2), cpu_env,
-+                           s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
-         gen_set_label(over);
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
-             gen_helper_vid_v_w, gen_helper_vid_v_d,
-         };
-         tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
--                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
-+                           cpu_env, s->vlen / 8, s->vlen / 8,
-+                           data, fns[s->sew]);
-         gen_set_label(over);
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
-         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
--                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
-+                           cpu_env, s->vlen / 8, s->vlen / 8, data,
-+                           fns[s->sew]);
-         gen_set_label(over);
-         return true;
-     }
---
-.31.1

-[PULL 16/32] target/riscv: reformat @sh format encoding for B-extension
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-2-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode | 10 +++++-----
-file changed, 5 insertions(+), 5 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@
- %rd        7:5
- %sh5       20:5
--%sh10    20:10
-+%sh7    20:7
- %csr    20:12
- %rm     12:3
- %nf     29:3                     !function=ex_plus_1
-@@ -XXX,XX +XXX,XX @@
- @u       ....................      ..... ....... &u      imm=%imm_u          %rd
- @j       ....................      ..... ....... &j      imm=%imm_j          %rd
--@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
-+@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
- @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
- @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
-@@ -XXX,XX +XXX,XX @@ sltiu    ............     ..... 011 ..... 0010011 @i
- xori     ............     ..... 100 ..... 0010011 @i
- ori      ............     ..... 110 ..... 0010011 @i
- andi     ............     ..... 111 ..... 0010011 @i
--slli     00.... ......    ..... 001 ..... 0010011 @sh
--srli     00.... ......    ..... 101 ..... 0010011 @sh
--srai     01.... ......    ..... 101 ..... 0010011 @sh
-+slli     00000. ......    ..... 001 ..... 0010011 @sh
-+srli     00000. ......    ..... 101 ..... 0010011 @sh
-+srai     01000. ......    ..... 101 ..... 0010011 @sh
- add      0000000 .....    ..... 000 ..... 0110011 @r
- sub      0100000 .....    ..... 000 ..... 0110011 @r
- sll      0000000 .....    ..... 001 ..... 0110011 @r
---
-.31.1

-[PULL 17/32] target/riscv: rvb: count leading/trailing zeros
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-3-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h                      |  1 +
- target/riscv/insn32.decode              | 11 ++++++-
- target/riscv/translate.c                | 38 +++++++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
-files changed, 93 insertions(+), 1 deletion(-)
- create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define RVS RV('S')
- #define RVU RV('U')
- #define RVH RV('H')
-+#define RVB RV('B')
- /* S extension denotes that Supervisor mode exists, however it is possible
-    to have a core that support S mode but does not have an MMU and there
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@
- &i    imm rs1 rd
- &j    imm rd
- &r    rd rs1 rs2
-+&r2   rd rs1
- &s    imm rs1 rs2
- &u    imm rd
- &shift     shamt rs1 rd
-@@ -XXX,XX +XXX,XX @@
- @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
- @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
- @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
--@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
-+@r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
- @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
- @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
- @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
-@@ -XXX,XX +XXX,XX @@ vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
- vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
- vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
- vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-+
-+# *** RV32B Standard Extension ***
-+clz        011000 000000 ..... 001 ..... 0010011 @r2
-+ctz        011000 000001 ..... 001 ..... 0010011 @r2
-+
-+# *** RV64B Standard Extension (in addition to RV32B) ***
-+clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-+ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
-     return true;
- }
-+static void gen_ctzw(TCGv ret, TCGv arg1)
-+{
-+    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-+    tcg_gen_ctzi_tl(ret, ret, 64);
-+}
-+
-+static void gen_clzw(TCGv ret, TCGv arg1)
-+{
-+    tcg_gen_ext32u_tl(ret, arg1);
-+    tcg_gen_clzi_tl(ret, ret, 64);
-+    tcg_gen_subi_tl(ret, ret, 32);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
-     return cpu_ldl_code(env, pc);
- }
-+static void gen_ctz(TCGv ret, TCGv arg1)
-+{
-+    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
-+}
-+
-+static void gen_clz(TCGv ret, TCGv arg1)
-+{
-+    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
-+}
-+
-+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
-+                      void(*func)(TCGv, TCGv))
-+{
-+    TCGv source = tcg_temp_new();
-+
-+    gen_get_gpr(source, a->rs1);
-+
-+    (*func)(source, source);
-+
-+    gen_set_gpr(a->rd, source);
-+    tcg_temp_free(source);
-+    return true;
-+}
-+
- /* Include insn module translation function */
- #include "insn_trans/trans_rvi.c.inc"
- #include "insn_trans/trans_rvm.c.inc"
-@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
- #include "insn_trans/trans_rvd.c.inc"
- #include "insn_trans/trans_rvh.c.inc"
- #include "insn_trans/trans_rvv.c.inc"
-+#include "insn_trans/trans_rvb.c.inc"
- #include "insn_trans/trans_privileged.c.inc"
- /* Include the auto-generated decoder for 16 bit insn */
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * RISC-V translation routines for the RVB Standard Extension.
-+ *
-+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
-+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2 or later, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+static bool trans_clz(DisasContext *ctx, arg_clz *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, gen_clz);
-+}
-+
-+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, gen_ctz);
-+}
-+
-+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, gen_clzw);
-+}
-+
-+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, gen_ctzw);
-+}
---
-.31.1

-[PULL 18/32] target/riscv: rvb: count bits set
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20210505160620.15723-4-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  2 ++
- target/riscv/translate.c                |  6 ++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
-files changed, 21 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
- # *** RV32B Standard Extension ***
- clz        011000 000000 ..... 001 ..... 0010011 @r2
- ctz        011000 000001 ..... 001 ..... 0010011 @r2
-+cpop       011000 000010 ..... 001 ..... 0010011 @r2
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
- ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-+cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
-     tcg_gen_subi_tl(ret, ret, 32);
- }
-+static void gen_cpopw(TCGv ret, TCGv arg1)
-+{
-+    tcg_gen_ext32u_tl(arg1, arg1);
-+    tcg_gen_ctpop_tl(ret, arg1);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
-     return gen_unary(ctx, a, gen_ctz);
- }
-+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, tcg_gen_ctpop_tl);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_unary(ctx, a, gen_ctzw);
- }
-+
-+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, gen_cpopw);
-+}
---
-.31.1

-[PULL 19/32] target/riscv: rvb: logic-with-negate
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-5-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  3 +++
- target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
-files changed, 21 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
- clz        011000 000000 ..... 001 ..... 0010011 @r2
- ctz        011000 000001 ..... 001 ..... 0010011 @r2
- cpop       011000 000010 ..... 001 ..... 0010011 @r2
-+andn       0100000 .......... 111 ..... 0110011 @r
-+orn        0100000 .......... 110 ..... 0110011 @r
-+xnor       0100000 .......... 100 ..... 0110011 @r
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
-     return gen_unary(ctx, a, tcg_gen_ctpop_tl);
- }
-+static bool trans_andn(DisasContext *ctx, arg_andn *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_andc_tl);
-+}
-+
-+static bool trans_orn(DisasContext *ctx, arg_orn *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_orc_tl);
-+}
-+
-+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_eqv_tl);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
---
-.31.1

-[PULL 20/32] target/riscv: rvb: pack two words into one register
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-6-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  6 ++++
- target/riscv/translate.c                | 40 +++++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
-files changed, 78 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ cpop       011000 000010 ..... 001 ..... 0010011 @r2
- andn       0100000 .......... 111 ..... 0110011 @r
- orn        0100000 .......... 110 ..... 0110011 @r
- xnor       0100000 .......... 100 ..... 0110011 @r
-+pack       0000100 .......... 100 ..... 0110011 @r
-+packu      0100100 .......... 100 ..... 0110011 @r
-+packh      0000100 .......... 111 ..... 0110011 @r
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
- ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
- cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
-+
-+packw      0000100 .......... 100 ..... 0111011 @r
-+packuw     0100100 .......... 100 ..... 0111011 @r
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
-     return true;
- }
-+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_deposit_tl(ret, arg1, arg2,
-+                       TARGET_LONG_BITS / 2,
-+                       TARGET_LONG_BITS / 2);
-+}
-+
-+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv t = tcg_temp_new();
-+    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
-+    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
-+    tcg_temp_free(t);
-+}
-+
-+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv t = tcg_temp_new();
-+    tcg_gen_ext8u_tl(t, arg2);
-+    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
-+    tcg_temp_free(t);
-+}
-+
- static void gen_ctzw(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-@@ -XXX,XX +XXX,XX @@ static void gen_cpopw(TCGv ret, TCGv arg1)
-     tcg_gen_ctpop_tl(ret, arg1);
- }
-+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv t = tcg_temp_new();
-+    tcg_gen_ext16s_tl(t, arg2);
-+    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
-+    tcg_temp_free(t);
-+}
-+
-+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv t = tcg_temp_new();
-+    tcg_gen_shri_tl(t, arg1, 16);
-+    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
-+    tcg_gen_ext32s_tl(ret, ret);
-+    tcg_temp_free(t);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
-     return gen_arith(ctx, a, tcg_gen_eqv_tl);
- }
-+static bool trans_pack(DisasContext *ctx, arg_pack *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_pack);
-+}
-+
-+static bool trans_packu(DisasContext *ctx, arg_packu *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_packu);
-+}
-+
-+static bool trans_packh(DisasContext *ctx, arg_packh *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_packh);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_unary(ctx, a, gen_cpopw);
- }
-+
-+static bool trans_packw(DisasContext *ctx, arg_packw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_packw);
-+}
-+
-+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_packuw);
-+}
---
-.31.1

-[PULL 21/32] target/riscv: rvb: min/max instructions
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20210505160620.15723-7-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  4 ++++
- target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
-files changed, 28 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ xnor       0100000 .......... 100 ..... 0110011 @r
- pack       0000100 .......... 100 ..... 0110011 @r
- packu      0100100 .......... 100 ..... 0110011 @r
- packh      0000100 .......... 111 ..... 0110011 @r
-+min        0000101 .......... 100 ..... 0110011 @r
-+minu       0000101 .......... 101 ..... 0110011 @r
-+max        0000101 .......... 110 ..... 0110011 @r
-+maxu       0000101 .......... 111 ..... 0110011 @r
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
-     return gen_arith(ctx, a, gen_packh);
- }
-+static bool trans_min(DisasContext *ctx, arg_min *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_smin_tl);
-+}
-+
-+static bool trans_max(DisasContext *ctx, arg_max *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_smax_tl);
-+}
-+
-+static bool trans_minu(DisasContext *ctx, arg_minu *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_umin_tl);
-+}
-+
-+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, tcg_gen_umax_tl);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
---
-.31.1

-[PULL 22/32] target/riscv: rvb: sign-extend instructions
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20210505160620.15723-8-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  3 +++
- target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
-files changed, 15 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
- clz        011000 000000 ..... 001 ..... 0010011 @r2
- ctz        011000 000001 ..... 001 ..... 0010011 @r2
- cpop       011000 000010 ..... 001 ..... 0010011 @r2
-+sext_b     011000 000100 ..... 001 ..... 0010011 @r2
-+sext_h     011000 000101 ..... 001 ..... 0010011 @r2
-+
- andn       0100000 .......... 111 ..... 0110011 @r
- orn        0100000 .......... 110 ..... 0110011 @r
- xnor       0100000 .......... 100 ..... 0110011 @r
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
-     return gen_arith(ctx, a, tcg_gen_umax_tl);
- }
-+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, tcg_gen_ext8s_tl);
-+}
-+
-+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_unary(ctx, a, tcg_gen_ext16s_tl);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
---
-.31.1

-[PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
-interfaces for immediate shift instructions.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-9-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/translate.c                | 39 ++++++++++++++++++
- target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
-files changed, 43 insertions(+), 50 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
-     return cpu_ldl_code(env, pc);
- }
-+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
-+                       void(*func)(TCGv, TCGv, TCGv))
-+{
-+    if (a->shamt >= TARGET_LONG_BITS) {
-+        return false;
-+    }
-+
-+    TCGv source1 = tcg_temp_new();
-+    TCGv source2 = tcg_temp_new();
-+
-+    gen_get_gpr(source1, a->rs1);
-+
-+    tcg_gen_movi_tl(source2, a->shamt);
-+    (*func)(source1, source1, source2);
-+
-+    gen_set_gpr(a->rd, source1);
-+    tcg_temp_free(source1);
-+    tcg_temp_free(source2);
-+    return true;
-+}
-+
-+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
-+                        void(*func)(TCGv, TCGv, TCGv))
-+{
-+    TCGv source1 = tcg_temp_new();
-+    TCGv source2 = tcg_temp_new();
-+
-+    gen_get_gpr(source1, a->rs1);
-+    tcg_gen_movi_tl(source2, a->shamt);
-+
-+    (*func)(source1, source1, source2);
-+    tcg_gen_ext32s_tl(source1, source1);
-+
-+    gen_set_gpr(a->rd, source1);
-+    tcg_temp_free(source1);
-+    tcg_temp_free(source2);
-+    return true;
-+}
-+
- static void gen_ctz(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
- }
- static bool trans_slli(DisasContext *ctx, arg_slli *a)
- {
--    if (a->shamt >= TARGET_LONG_BITS) {
--        return false;
--    }
--
--    if (a->rd != 0) {
--        TCGv t = tcg_temp_new();
--        gen_get_gpr(t, a->rs1);
--
--        tcg_gen_shli_tl(t, t, a->shamt);
--
--        gen_set_gpr(a->rd, t);
--        tcg_temp_free(t);
--    } /* NOP otherwise */
--    return true;
-+    return gen_shifti(ctx, a, tcg_gen_shl_tl);
- }
- static bool trans_srli(DisasContext *ctx, arg_srli *a)
- {
--    if (a->shamt >= TARGET_LONG_BITS) {
--        return false;
--    }
--
--    if (a->rd != 0) {
--        TCGv t = tcg_temp_new();
--        gen_get_gpr(t, a->rs1);
--
--        tcg_gen_shri_tl(t, t, a->shamt);
--        gen_set_gpr(a->rd, t);
--        tcg_temp_free(t);
--    } /* NOP otherwise */
--    return true;
-+    return gen_shifti(ctx, a, tcg_gen_shr_tl);
- }
- static bool trans_srai(DisasContext *ctx, arg_srai *a)
- {
--    if (a->shamt >= TARGET_LONG_BITS) {
--        return false;
--    }
--
--    if (a->rd != 0) {
--        TCGv t = tcg_temp_new();
--        gen_get_gpr(t, a->rs1);
--
--        tcg_gen_sari_tl(t, t, a->shamt);
--        gen_set_gpr(a->rd, t);
--        tcg_temp_free(t);
--    } /* NOP otherwise */
--    return true;
-+    return gen_shifti(ctx, a, tcg_gen_sar_tl);
- }
- static bool trans_add(DisasContext *ctx, arg_add *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
- static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
- {
-     REQUIRE_64BIT(ctx);
--    TCGv source1;
--    source1 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--
--    tcg_gen_shli_tl(source1, source1, a->shamt);
--    tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
--
--    tcg_temp_free(source1);
--    return true;
-+    return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
- }
- static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
---
-.31.1

-[PULL 24/32] target/riscv: rvb: single-bit instructions
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-10-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              | 17 +++++
- target/riscv/translate.c                | 61 ++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
-files changed, 175 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
- minu       0000101 .......... 101 ..... 0110011 @r
- max        0000101 .......... 110 ..... 0110011 @r
- maxu       0000101 .......... 111 ..... 0110011 @r
-+bset       0010100 .......... 001 ..... 0110011 @r
-+bclr       0100100 .......... 001 ..... 0110011 @r
-+binv       0110100 .......... 001 ..... 0110011 @r
-+bext       0100100 .......... 101 ..... 0110011 @r
-+
-+bseti      00101. ........... 001 ..... 0010011 @sh
-+bclri      01001. ........... 001 ..... 0010011 @sh
-+binvi      01101. ........... 001 ..... 0010011 @sh
-+bexti      01001. ........... 101 ..... 0010011 @sh
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
- packw      0000100 .......... 100 ..... 0111011 @r
- packuw     0100100 .......... 100 ..... 0111011 @r
-+bsetw      0010100 .......... 001 ..... 0111011 @r
-+bclrw      0100100 .......... 001 ..... 0111011 @r
-+binvw      0110100 .......... 001 ..... 0111011 @r
-+bextw      0100100 .......... 101 ..... 0111011 @r
-+
-+bsetiw     0010100 .......... 001 ..... 0011011 @sh5
-+bclriw     0100100 .......... 001 ..... 0011011 @sh5
-+binviw     0110100 .......... 001 ..... 0011011 @sh5
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-     tcg_temp_free(t);
- }
-+static void gen_sbop_mask(TCGv ret, TCGv shamt)
-+{
-+    tcg_gen_movi_tl(ret, 1);
-+    tcg_gen_shl_tl(ret, ret, shamt);
-+}
-+
-+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
-+{
-+    TCGv t = tcg_temp_new();
-+
-+    gen_sbop_mask(t, shamt);
-+    tcg_gen_or_tl(ret, arg1, t);
-+
-+    tcg_temp_free(t);
-+}
-+
-+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
-+{
-+    TCGv t = tcg_temp_new();
-+
-+    gen_sbop_mask(t, shamt);
-+    tcg_gen_andc_tl(ret, arg1, t);
-+
-+    tcg_temp_free(t);
-+}
-+
-+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
-+{
-+    TCGv t = tcg_temp_new();
-+
-+    gen_sbop_mask(t, shamt);
-+    tcg_gen_xor_tl(ret, arg1, t);
-+
-+    tcg_temp_free(t);
-+}
-+
-+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
-+{
-+    tcg_gen_shr_tl(ret, arg1, shamt);
-+    tcg_gen_andi_tl(ret, ret, 1);
-+}
-+
- static void gen_ctzw(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-@@ -XXX,XX +XXX,XX @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
-     return true;
- }
-+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
-+                       void(*func)(TCGv, TCGv, TCGv))
-+{
-+    TCGv source1 = tcg_temp_new();
-+    TCGv source2 = tcg_temp_new();
-+
-+    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(source2, a->rs2);
-+
-+    tcg_gen_andi_tl(source2, source2, 31);
-+    (*func)(source1, source1, source2);
-+    tcg_gen_ext32s_tl(source1, source1);
-+
-+    gen_set_gpr(a->rd, source1);
-+    tcg_temp_free(source1);
-+    tcg_temp_free(source2);
-+    return true;
-+}
-+
- static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
-                         void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
-     return gen_unary(ctx, a, tcg_gen_ext16s_tl);
- }
-+static bool trans_bset(DisasContext *ctx, arg_bset *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_bset);
-+}
-+
-+static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_bset);
-+}
-+
-+static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_bclr);
-+}
-+
-+static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_bclr);
-+}
-+
-+static bool trans_binv(DisasContext *ctx, arg_binv *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_binv);
-+}
-+
-+static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_binv);
-+}
-+
-+static bool trans_bext(DisasContext *ctx, arg_bext *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_bext);
-+}
-+
-+static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_bext);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_arith(ctx, a, gen_packuw);
- }
-+
-+static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_bset);
-+}
-+
-+static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_bset);
-+}
-+
-+static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_bclr);
-+}
-+
-+static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_bclr);
-+}
-+
-+static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_binv);
-+}
-+
-+static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_binv);
-+}
-+
-+static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_bext);
-+}
---
-.31.1

-[PULL 25/32] target/riscv: rvb: shift ones
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-11-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  8 ++++
- target/riscv/translate.c                | 14 +++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
-files changed, 74 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ bset       0010100 .......... 001 ..... 0110011 @r
- bclr       0100100 .......... 001 ..... 0110011 @r
- binv       0110100 .......... 001 ..... 0110011 @r
- bext       0100100 .......... 101 ..... 0110011 @r
-+slo        0010000 .......... 001 ..... 0110011 @r
-+sro        0010000 .......... 101 ..... 0110011 @r
- bseti      00101. ........... 001 ..... 0010011 @sh
- bclri      01001. ........... 001 ..... 0010011 @sh
- binvi      01101. ........... 001 ..... 0010011 @sh
- bexti      01001. ........... 101 ..... 0010011 @sh
-+sloi       00100. ........... 001 ..... 0010011 @sh
-+sroi       00100. ........... 101 ..... 0010011 @sh
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-@@ -XXX,XX +XXX,XX @@ bsetw      0010100 .......... 001 ..... 0111011 @r
- bclrw      0100100 .......... 001 ..... 0111011 @r
- binvw      0110100 .......... 001 ..... 0111011 @r
- bextw      0100100 .......... 101 ..... 0111011 @r
-+slow       0010000 .......... 001 ..... 0111011 @r
-+srow       0010000 .......... 101 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
- binviw     0110100 .......... 001 ..... 0011011 @sh5
-+sloiw      0010000 .......... 001 ..... 0011011 @sh5
-+sroiw      0010000 .......... 101 ..... 0011011 @sh5
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
-     tcg_gen_andi_tl(ret, ret, 1);
- }
-+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_not_tl(ret, arg1);
-+    tcg_gen_shl_tl(ret, ret, arg2);
-+    tcg_gen_not_tl(ret, ret);
-+}
-+
-+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_not_tl(ret, arg1);
-+    tcg_gen_shr_tl(ret, ret, arg2);
-+    tcg_gen_not_tl(ret, ret);
-+}
-+
- static void gen_ctzw(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
-     return gen_shifti(ctx, a, gen_bext);
- }
-+static bool trans_slo(DisasContext *ctx, arg_slo *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_slo);
-+}
-+
-+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_slo);
-+}
-+
-+static bool trans_sro(DisasContext *ctx, arg_sro *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_sro);
-+}
-+
-+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_sro);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_shiftw(ctx, a, gen_bext);
- }
-+
-+static bool trans_slow(DisasContext *ctx, arg_slow *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_slo);
-+}
-+
-+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_slo);
-+}
-+
-+static bool trans_srow(DisasContext *ctx, arg_srow *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_sro);
-+}
-+
-+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_sro);
-+}
---
-.31.1

-[PULL 26/32] target/riscv: rvb: rotate (left/right)
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-12-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  6 ++++
- target/riscv/translate.c                | 36 +++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
-files changed, 81 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ binv       0110100 .......... 001 ..... 0110011 @r
- bext       0100100 .......... 101 ..... 0110011 @r
- slo        0010000 .......... 001 ..... 0110011 @r
- sro        0010000 .......... 101 ..... 0110011 @r
-+ror        0110000 .......... 101 ..... 0110011 @r
-+rol        0110000 .......... 001 ..... 0110011 @r
- bseti      00101. ........... 001 ..... 0010011 @sh
- bclri      01001. ........... 001 ..... 0010011 @sh
-@@ -XXX,XX +XXX,XX @@ binvi      01101. ........... 001 ..... 0010011 @sh
- bexti      01001. ........... 101 ..... 0010011 @sh
- sloi       00100. ........... 001 ..... 0010011 @sh
- sroi       00100. ........... 101 ..... 0010011 @sh
-+rori       01100. ........... 101 ..... 0010011 @sh
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-@@ -XXX,XX +XXX,XX @@ binvw      0110100 .......... 001 ..... 0111011 @r
- bextw      0100100 .......... 101 ..... 0111011 @r
- slow       0010000 .......... 001 ..... 0111011 @r
- srow       0010000 .......... 101 ..... 0111011 @r
-+rorw       0110000 .......... 101 ..... 0111011 @r
-+rolw       0110000 .......... 001 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
- binviw     0110100 .......... 001 ..... 0011011 @sh5
- sloiw      0010000 .......... 001 ..... 0011011 @sh5
- sroiw      0010000 .......... 101 ..... 0011011 @sh5
-+roriw      0110000 .......... 101 ..... 0011011 @sh5
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
-     tcg_temp_free(t);
- }
-+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv_i32 t1 = tcg_temp_new_i32();
-+    TCGv_i32 t2 = tcg_temp_new_i32();
-+
-+    /* truncate to 32-bits */
-+    tcg_gen_trunc_tl_i32(t1, arg1);
-+    tcg_gen_trunc_tl_i32(t2, arg2);
-+
-+    tcg_gen_rotr_i32(t1, t1, t2);
-+
-+    /* sign-extend 64-bits */
-+    tcg_gen_ext_i32_tl(ret, t1);
-+
-+    tcg_temp_free_i32(t1);
-+    tcg_temp_free_i32(t2);
-+}
-+
-+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv_i32 t1 = tcg_temp_new_i32();
-+    TCGv_i32 t2 = tcg_temp_new_i32();
-+
-+    /* truncate to 32-bits */
-+    tcg_gen_trunc_tl_i32(t1, arg1);
-+    tcg_gen_trunc_tl_i32(t2, arg2);
-+
-+    tcg_gen_rotl_i32(t1, t1, t2);
-+
-+    /* sign-extend 64-bits */
-+    tcg_gen_ext_i32_tl(ret, t1);
-+
-+    tcg_temp_free_i32(t1);
-+    tcg_temp_free_i32(t2);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-     return gen_shifti(ctx, a, gen_sro);
- }
-+static bool trans_ror(DisasContext *ctx, arg_ror *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, tcg_gen_rotr_tl);
-+}
-+
-+static bool trans_rori(DisasContext *ctx, arg_rori *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, tcg_gen_rotr_tl);
-+}
-+
-+static bool trans_rol(DisasContext *ctx, arg_rol *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, tcg_gen_rotl_tl);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_shiftiw(ctx, a, gen_sro);
- }
-+
-+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_rorw);
-+}
-+
-+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_rorw);
-+}
-+
-+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_rolw);
-+}
---
-.31.1

-[PULL 27/32] target/riscv: rvb: generalized reverse
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210505160620.15723-13-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/helper.h                   |  4 ++
- target/riscv/insn32.decode              |  4 ++
- target/riscv/bitmanip_helper.c          | 64 +++++++++++++++++++++++++
- target/riscv/translate.c                | 28 +++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 31 ++++++++++++
- target/riscv/meson.build                |  1 +
-files changed, 132 insertions(+)
- create mode 100644 target/riscv/bitmanip_helper.c
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
-+++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
- DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
- DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
-+/* Bitmanip */
-+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+
- /* Special functions */
- DEF_HELPER_3(csrrw, tl, env, tl, tl)
- DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ slo        0010000 .......... 001 ..... 0110011 @r
- sro        0010000 .......... 101 ..... 0110011 @r
- ror        0110000 .......... 101 ..... 0110011 @r
- rol        0110000 .......... 001 ..... 0110011 @r
-+grev       0110100 .......... 101 ..... 0110011 @r
- bseti      00101. ........... 001 ..... 0010011 @sh
- bclri      01001. ........... 001 ..... 0010011 @sh
-@@ -XXX,XX +XXX,XX @@ bexti      01001. ........... 101 ..... 0010011 @sh
- sloi       00100. ........... 001 ..... 0010011 @sh
- sroi       00100. ........... 101 ..... 0010011 @sh
- rori       01100. ........... 101 ..... 0010011 @sh
-+grevi      01101. ........... 101 ..... 0010011 @sh
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-@@ -XXX,XX +XXX,XX @@ slow       0010000 .......... 001 ..... 0111011 @r
- srow       0010000 .......... 101 ..... 0111011 @r
- rorw       0110000 .......... 101 ..... 0111011 @r
- rolw       0110000 .......... 001 ..... 0111011 @r
-+grevw      0110100 .......... 101 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
-@@ -XXX,XX +XXX,XX @@ binviw     0110100 .......... 001 ..... 0011011 @sh5
- sloiw      0010000 .......... 001 ..... 0011011 @sh5
- sroiw      0010000 .......... 101 ..... 0011011 @sh5
- roriw      0110000 .......... 101 ..... 0011011 @sh5
-+greviw     0110100 .......... 101 ..... 0011011 @sh5
-diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/riscv/bitmanip_helper.c
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * RISC-V Bitmanip Extension Helpers for QEMU.
-+ *
-+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
-+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2 or later, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include "qemu/osdep.h"
-+#include "qemu/host-utils.h"
-+#include "exec/exec-all.h"
-+#include "exec/helper-proto.h"
-+#include "tcg/tcg.h"
-+
-+static const uint64_t adjacent_masks[] = {
-+    dup_const(MO_8, 0x55),
-+    dup_const(MO_8, 0x33),
-+    dup_const(MO_8, 0x0f),
-+    dup_const(MO_16, 0xff),
-+    dup_const(MO_32, 0xffff),
-+    UINT32_MAX
-+};
-+
-+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
-+{
-+    return ((x & mask) << shift) | ((x & ~mask) >> shift);
-+}
-+
-+static target_ulong do_grev(target_ulong rs1,
-+                            target_ulong rs2,
-+                            int bits)
-+{
-+    target_ulong x = rs1;
-+    int i, shift;
-+
-+    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-+        if (rs2 & shift) {
-+            x = do_swap(x, adjacent_masks[i], shift);
-+        }
-+    }
-+
-+    return x;
-+}
-+
-+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
-+{
-+    return do_grev(rs1, rs2, TARGET_LONG_BITS);
-+}
-+
-+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
-+{
-+    return do_grev(rs1, rs2, 32);
-+}
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-     tcg_gen_not_tl(ret, ret);
- }
-+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
-+{
-+    TCGv source1 = tcg_temp_new();
-+    TCGv source2;
-+
-+    gen_get_gpr(source1, a->rs1);
-+
-+    if (a->shamt == (TARGET_LONG_BITS - 8)) {
-+        /* rev8, byte swaps */
-+        tcg_gen_bswap_tl(source1, source1);
-+    } else {
-+        source2 = tcg_temp_new();
-+        tcg_gen_movi_tl(source2, a->shamt);
-+        gen_helper_grev(source1, source1, source2);
-+        tcg_temp_free(source2);
-+    }
-+
-+    gen_set_gpr(a->rd, source1);
-+    tcg_temp_free(source1);
-+    return true;
-+}
-+
- static void gen_ctzw(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-     tcg_temp_free_i32(t2);
- }
-+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_ext32u_tl(arg1, arg1);
-+    gen_helper_grev(ret, arg1, arg2);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
-     return gen_shift(ctx, a, tcg_gen_rotl_tl);
- }
-+static bool trans_grev(DisasContext *ctx, arg_grev *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_helper_grev);
-+}
-+
-+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+
-+    if (a->shamt >= TARGET_LONG_BITS) {
-+        return false;
-+    }
-+
-+    return gen_grevi(ctx, a);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_shiftw(ctx, a, gen_rolw);
- }
-+
-+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_grevw);
-+}
-+
-+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_grevw);
-+}
-diff --git a/target/riscv/meson.build b/target/riscv/meson.build
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/meson.build
-+++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
-   'gdbstub.c',
-   'op_helper.c',
-   'vector_helper.c',
-+  'bitmanip_helper.c',
-   'translate.c',
- ))
---
-.31.1

-[PULL 28/32] target/riscv: rvb: generalized or-combine
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210505160620.15723-14-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/helper.h                   |  2 ++
- target/riscv/insn32.decode              |  4 ++++
- target/riscv/bitmanip_helper.c          | 26 +++++++++++++++++++++++++
- target/riscv/translate.c                |  6 ++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
-files changed, 64 insertions(+)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
-+++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
- /* Bitmanip */
- DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- /* Special functions */
- DEF_HELPER_3(csrrw, tl, env, tl, tl)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ sro        0010000 .......... 101 ..... 0110011 @r
- ror        0110000 .......... 101 ..... 0110011 @r
- rol        0110000 .......... 001 ..... 0110011 @r
- grev       0110100 .......... 101 ..... 0110011 @r
-+gorc       0010100 .......... 101 ..... 0110011 @r
- bseti      00101. ........... 001 ..... 0010011 @sh
- bclri      01001. ........... 001 ..... 0010011 @sh
-@@ -XXX,XX +XXX,XX @@ sloi       00100. ........... 001 ..... 0010011 @sh
- sroi       00100. ........... 101 ..... 0010011 @sh
- rori       01100. ........... 101 ..... 0010011 @sh
- grevi      01101. ........... 101 ..... 0010011 @sh
-+gorci      00101. ........... 101 ..... 0010011 @sh
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-@@ -XXX,XX +XXX,XX @@ srow       0010000 .......... 101 ..... 0111011 @r
- rorw       0110000 .......... 101 ..... 0111011 @r
- rolw       0110000 .......... 001 ..... 0111011 @r
- grevw      0110100 .......... 101 ..... 0111011 @r
-+gorcw      0010100 .......... 101 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
-@@ -XXX,XX +XXX,XX @@ sloiw      0010000 .......... 001 ..... 0011011 @sh5
- sroiw      0010000 .......... 101 ..... 0011011 @sh5
- roriw      0110000 .......... 101 ..... 0011011 @sh5
- greviw     0110100 .......... 101 ..... 0011011 @sh5
-+gorciw     0010100 .......... 101 ..... 0011011 @sh5
-diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/bitmanip_helper.c
-+++ b/target/riscv/bitmanip_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
- {
-     return do_grev(rs1, rs2, 32);
- }
-+
-+static target_ulong do_gorc(target_ulong rs1,
-+                            target_ulong rs2,
-+                            int bits)
-+{
-+    target_ulong x = rs1;
-+    int i, shift;
-+
-+    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-+        if (rs2 & shift) {
-+            x |= do_swap(x, adjacent_masks[i], shift);
-+        }
-+    }
-+
-+    return x;
-+}
-+
-+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-+{
-+    return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-+}
-+
-+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-+{
-+    return do_gorc(rs1, rs2, 32);
-+}
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
-     gen_helper_grev(ret, arg1, arg2);
- }
-+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_ext32u_tl(arg1, arg1);
-+    gen_helper_gorcw(ret, arg1, arg2);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
-     return gen_grevi(ctx, a);
- }
-+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shift(ctx, a, gen_helper_gorc);
-+}
-+
-+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
-+{
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shifti(ctx, a, gen_helper_gorc);
-+}
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_shiftiw(ctx, a, gen_grevw);
- }
-+
-+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftw(ctx, a, gen_gorcw);
-+}
-+
-+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_shiftiw(ctx, a, gen_gorcw);
-+}
---
-.31.1

-[PULL 29/32] target/riscv: rvb: address calculation
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210505160620.15723-15-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  6 +++++
- target/riscv/translate.c                | 32 +++++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
-files changed, 62 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ ror        0110000 .......... 101 ..... 0110011 @r
- rol        0110000 .......... 001 ..... 0110011 @r
- grev       0110100 .......... 101 ..... 0110011 @r
- gorc       0010100 .......... 101 ..... 0110011 @r
-+sh1add     0010000 .......... 010 ..... 0110011 @r
-+sh2add     0010000 .......... 100 ..... 0110011 @r
-+sh3add     0010000 .......... 110 ..... 0110011 @r
- bseti      00101. ........... 001 ..... 0010011 @sh
- bclri      01001. ........... 001 ..... 0010011 @sh
-@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
- rolw       0110000 .......... 001 ..... 0111011 @r
- grevw      0110100 .......... 101 ..... 0111011 @r
- gorcw      0010100 .......... 101 ..... 0111011 @r
-+sh1add_uw  0010000 .......... 010 ..... 0111011 @r
-+sh2add_uw  0010000 .......... 100 ..... 0111011 @r
-+sh3add_uw  0010000 .......... 110 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
-     return true;
- }
-+#define GEN_SHADD(SHAMT)                                       \
-+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
-+{                                                              \
-+    TCGv t = tcg_temp_new();                                   \
-+                                                               \
-+    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
-+    tcg_gen_add_tl(ret, t, arg2);                              \
-+                                                               \
-+    tcg_temp_free(t);                                          \
-+}
-+
-+GEN_SHADD(1)
-+GEN_SHADD(2)
-+GEN_SHADD(3)
-+
- static void gen_ctzw(TCGv ret, TCGv arg1)
- {
-     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-@@ -XXX,XX +XXX,XX @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
-     gen_helper_gorcw(ret, arg1, arg2);
- }
-+#define GEN_SHADD_UW(SHAMT)                                       \
-+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
-+{                                                                 \
-+    TCGv t = tcg_temp_new();                                      \
-+                                                                  \
-+    tcg_gen_ext32u_tl(t, arg1);                                   \
-+                                                                  \
-+    tcg_gen_shli_tl(t, t, SHAMT);                                 \
-+    tcg_gen_add_tl(ret, t, arg2);                                 \
-+                                                                  \
-+    tcg_temp_free(t);                                             \
-+}
-+
-+GEN_SHADD_UW(1)
-+GEN_SHADD_UW(2)
-+GEN_SHADD_UW(3)
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
-     return gen_shifti(ctx, a, gen_helper_gorc);
- }
-+#define GEN_TRANS_SHADD(SHAMT)                                             \
-+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
-+{                                                                          \
-+    REQUIRE_EXT(ctx, RVB);                                                 \
-+    return gen_arith(ctx, a, gen_sh##SHAMT##add);                          \
-+}
-+
-+GEN_TRANS_SHADD(1)
-+GEN_TRANS_SHADD(2)
-+GEN_TRANS_SHADD(3)
-+
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-     REQUIRE_EXT(ctx, RVB);
-     return gen_shiftiw(ctx, a, gen_gorcw);
- }
-+
-+#define GEN_TRANS_SHADD_UW(SHAMT)                             \
-+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
-+                                    arg_sh##SHAMT##add_uw *a) \
-+{                                                             \
-+    REQUIRE_64BIT(ctx);                                       \
-+    REQUIRE_EXT(ctx, RVB);                                    \
-+    return gen_arith(ctx, a, gen_sh##SHAMT##add_uw);          \
-+}
-+
-+GEN_TRANS_SHADD_UW(1)
-+GEN_TRANS_SHADD_UW(2)
-+GEN_TRANS_SHADD_UW(3)
---
-.31.1

-[PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210505160620.15723-16-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn32.decode              |  3 +++
- target/riscv/translate.c                |  6 ++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
-files changed, 35 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
-+++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ gorcw      0010100 .......... 101 ..... 0111011 @r
- sh1add_uw  0010000 .......... 010 ..... 0111011 @r
- sh2add_uw  0010000 .......... 100 ..... 0111011 @r
- sh3add_uw  0010000 .......... 110 ..... 0111011 @r
-+add_uw     0000100 .......... 000 ..... 0111011 @r
- bsetiw     0010100 .......... 001 ..... 0011011 @sh5
- bclriw     0100100 .......... 001 ..... 0011011 @sh5
-@@ -XXX,XX +XXX,XX @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
- roriw      0110000 .......... 101 ..... 0011011 @sh5
- greviw     0110100 .......... 101 ..... 0011011 @sh5
- gorciw     0010100 .......... 101 ..... 0011011 @sh5
-+
-+slli_uw    00001. ........... 001 ..... 0011011 @sh
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ GEN_SHADD_UW(1)
- GEN_SHADD_UW(2)
- GEN_SHADD_UW(3)
-+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    tcg_gen_ext32u_tl(arg1, arg1);
-+    tcg_gen_add_tl(ret, arg1, arg2);
-+}
-+
- static bool gen_arith(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
- {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
- GEN_TRANS_SHADD_UW(1)
- GEN_TRANS_SHADD_UW(2)
- GEN_TRANS_SHADD_UW(3)
-+
-+static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+    return gen_arith(ctx, a, gen_add_uw);
-+}
-+
-+static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
-+{
-+    REQUIRE_64BIT(ctx);
-+    REQUIRE_EXT(ctx, RVB);
-+
-+    TCGv source1 = tcg_temp_new();
-+    gen_get_gpr(source1, a->rs1);
-+
-+    if (a->shamt < 32) {
-+        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
-+    } else {
-+        tcg_gen_shli_tl(source1, source1, a->shamt);
-+    }
-+
-+    gen_set_gpr(a->rd, source1);
-+    tcg_temp_free(source1);
-+    return true;
-+}
---
-.31.1

-[PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line
+Deleted patch
-From: Kito Cheng <kito.cheng@sifive.com>
-B-extension is default off, use cpu rv32 or rv64 with x-b=true to
-enable B-extension.
-Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210505160620.15723-17-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h | 1 +
- target/riscv/cpu.c | 4 ++++
-files changed, 5 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
-         bool ext_f;
-         bool ext_d;
-         bool ext_c;
-+        bool ext_b;
-         bool ext_s;
-         bool ext_u;
-         bool ext_h;
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-         if (cpu->cfg.ext_h) {
-             target_misa |= RVH;
-         }
-+        if (cpu->cfg.ext_b) {
-+            target_misa |= RVB;
-+        }
-         if (cpu->cfg.ext_v) {
-             target_misa |= RVV;
-             if (!is_power_of_2(cpu->cfg.vlen)) {
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
-     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
-     /* This is experimental so mark with 'x-' */
-+    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
-     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
-     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
-     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
---
-.31.1

-[PULL 32/32] target/riscv: rvb: add b-ext version cpu option
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-Default b-ext version is v0.93.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210505160620.15723-18-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h |  3 +++
- target/riscv/cpu.c | 23 +++++++++++++++++++++++
-files changed, 26 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum {
- #define PRIV_VERSION_1_10_0 0x00011000
- #define PRIV_VERSION_1_11_0 0x00011100
-+#define BEXT_VERSION_0_93_0 0x00009300
- #define VEXT_VERSION_0_07_1 0x00000701
- enum {
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     target_ulong guest_phys_fault_addr;
-     target_ulong priv_ver;
-+    target_ulong bext_ver;
-     target_ulong vext_ver;
-     target_ulong misa;
-     target_ulong misa_mask;
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
-         char *priv_spec;
-         char *user_spec;
-+        char *bext_spec;
-         char *vext_spec;
-         uint16_t vlen;
-         uint16_t elen;
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
-     env->priv_ver = priv_ver;
- }
-+static void set_bext_version(CPURISCVState *env, int bext_ver)
-+{
-+    env->bext_ver = bext_ver;
-+}
-+
- static void set_vext_version(CPURISCVState *env, int vext_ver)
- {
-     env->vext_ver = vext_ver;
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     CPURISCVState *env = &cpu->env;
-     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-     int priv_version = PRIV_VERSION_1_11_0;
-+    int bext_version = BEXT_VERSION_0_93_0;
-     int vext_version = VEXT_VERSION_0_07_1;
-     target_ulong target_misa = env->misa;
-     Error *local_err = NULL;
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     }
-     set_priv_version(env, priv_version);
-+    set_bext_version(env, bext_version);
-     set_vext_version(env, vext_version);
-     if (cpu->cfg.mmu) {
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-         }
-         if (cpu->cfg.ext_b) {
-             target_misa |= RVB;
-+
-+            if (cpu->cfg.bext_spec) {
-+                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
-+                    bext_version = BEXT_VERSION_0_93_0;
-+                } else {
-+                    error_setg(errp,
-+                           "Unsupported bitmanip spec version '%s'",
-+                           cpu->cfg.bext_spec);
-+                    return;
-+                }
-+            } else {
-+                qemu_log("bitmanip version is not specified, "
-+                         "use the default value v0.93\n");
-+            }
-+            set_bext_version(env, bext_version);
-         }
-         if (cpu->cfg.ext_v) {
-             target_misa |= RVV;
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-+    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
-     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
-     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
---
-.31.1

The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:

Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1

for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:

target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 6.1

- Update the PLIC and CLINT DT bindings
 - Improve documentation for RISC-V machines
 - Support direct kernel boot for microchip_pfsoc
 - Fix WFI exception behaviour
 - Improve CSR printing
 - Initial support for the experimental Bit Manip extension

----------------------------------------------------------------
Alistair Francis (2):
      docs/system: Move the RISC-V -bios information to removed
      target/riscv/pmp: Add assert for ePMP operations

Bin Meng (9):
      hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
      hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
      hw/riscv: Support the official CLINT DT bindings
      hw/riscv: Support the official PLIC DT bindings
      docs/system/riscv: Correct the indentation level of supported devices
      docs/system/riscv: sifive_u: Document '-dtb' usage
      hw/riscv: Use macros for BIOS image names
      hw/riscv: microchip_pfsoc: Support direct kernel boot
      target/riscv: Remove unnecessary riscv_*_names[] declaration

Changbin Du (1):
      target/riscv: Dump CSR mscratch/sscratch/satp

Frank Chang (6):
      target/riscv: rvb: count bits set
      target/riscv: add gen_shifti() and gen_shiftiw() helper functions
      target/riscv: rvb: single-bit instructions
      target/riscv: rvb: generalized reverse
      target/riscv: rvb: generalized or-combine
      target/riscv: rvb: add b-ext version cpu option

Jose Martins (1):
      target/riscv: fix wfi exception behavior

Kito Cheng (11):
      target/riscv: reformat @sh format encoding for B-extension
      target/riscv: rvb: count leading/trailing zeros
      target/riscv: rvb: logic-with-negate
      target/riscv: rvb: pack two words into one register
      target/riscv: rvb: min/max instructions
      target/riscv: rvb: sign-extend instructions
      target/riscv: rvb: shift ones
      target/riscv: rvb: rotate (left/right)
      target/riscv: rvb: address calculation
      target/riscv: rvb: add/shift with prefix zero-extend
      target/riscv: rvb: support and turn on B-extension from command line

LIU Zhiwei (1):
      target/riscv: Pass the same value to oprsz and maxsz.

Philippe Mathieu-Daudé (1):
      target/riscv: Do not include 'pmp.h' in user emulation

docs/system/deprecated.rst                 |  19 --
 docs/system/removed-features.rst           |   5 +
 docs/system/riscv/microchip-icicle-kit.rst |  50 +++-
 docs/system/riscv/sifive_u.rst             |  77 +++--
 docs/system/target-riscv.rst               |  13 +-
 include/hw/riscv/boot.h                    |   5 +
 target/riscv/cpu.h                         |   9 +-
 target/riscv/cpu_bits.h                    |   1 +
 target/riscv/helper.h                      |   6 +
 target/riscv/insn32.decode                 |  87 +++++-
 hw/riscv/microchip_pfsoc.c                 |  81 +++++-
 hw/riscv/sifive_u.c                        |  24 +-
 hw/riscv/spike.c                           |  12 +-
 hw/riscv/virt.c                            |  25 +-
 target/riscv/bitmanip_helper.c             |  90 ++++++
 target/riscv/cpu.c                         |  38 ++-
 target/riscv/op_helper.c                   |  11 +-
 target/riscv/pmp.c                         |   4 +
 target/riscv/translate.c                   | 306 ++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc    | 438 +++++++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc    |  54 +---
 target/riscv/insn_trans/trans_rvv.c.inc    |  89 +++---
 target/riscv/meson.build                   |   1 +
 23 files changed, 1260 insertions(+), 185 deletions(-)
 create mode 100644 target/riscv/bitmanip_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

From: Bin Meng <bin.meng@windriver.com>

Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the clock name for the ethernet
controller node.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

From: Bin Meng <bin.meng@windriver.com>

Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the compatible strings for the
SiFive test device node.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
         (long)memmap[VIRT_TEST].base);
     qemu_fdt_add_subnode(fdt, name);
     {
-        const char compat[] = "sifive,test1\0sifive,test0\0syscon";
-        qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
+        static const char * const compat[3] = {
+            "sifive,test1", "sifive,test0", "syscon"
+        };
+        qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
+                                      ARRAY_SIZE(compat));
     }
     qemu_fdt_setprop_cells(fdt, name, "reg",
         0x0, memmap[VIRT_TEST].base,
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 +++++-
 hw/riscv/spike.c    | 6 +++++-
 hw/riscv/virt.c     | 6 +++++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
     static const char * const ethclk_names[2] = { "pclk", "hclk" };
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     if (ms->dtb) {
         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     nodename = g_strdup_printf("/soc/clint@%lx",
         (long)memmap[SIFIVE_U_DEV_CLINT].base);
     qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
+        (char **)&clint_compat, ARRAY_SIZE(clint_compat));
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_DEV_CLINT].base,
         0x0, memmap[SIFIVE_U_DEV_CLINT].size);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     uint32_t cpu_phandle, intc_phandle, phandle = 1;
     char *name, *mem_name, *clint_name, *clust_name;
     char *core_name, *cpu_name, *intc_name;
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     fdt = s->fdt = create_device_tree(&s->fdt_size);
     if (!fdt) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             (memmap[SPIKE_CLINT].size * socket);
         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
         qemu_fdt_add_subnode(fdt, clint_name);
-        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     char *name, *clint_name, *plic_name, *clust_name;
     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     if (mc->dtb) {
         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
             (memmap[VIRT_CLINT].size * socket);
         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
         qemu_fdt_add_subnode(fdt, clint_name);
-        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
             0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 +++++-
 hw/riscv/virt.c     | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
     };
+    static const char * const plic_compat[2] = {
+        "sifive,plic-1.0.0", "riscv,plic0"
+    };
 
     if (ms->dtb) {
         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
         (long)memmap[SIFIVE_U_DEV_PLIC].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
+        (char **)&plic_compat, ARRAY_SIZE(plic_compat));
     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
     };
+    static const char * const plic_compat[2] = {
+        "sifive,plic-1.0.0", "riscv,plic0"
+    };
 
     if (mc->dtb) {
         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
             "#address-cells", FDT_PLIC_ADDR_CELLS);
         qemu_fdt_setprop_cell(fdt, plic_name,
             "#interrupt-cells", FDT_PLIC_INT_CELLS);
-        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+        qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
+            (char **)&plic_compat, ARRAY_SIZE(plic_compat));
         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

The supported device bullet list has an additional space before each
entry, which makes a wrong indentation level. Correct it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 20 +++++++--------
 docs/system/riscv/sifive_u.rst             | 30 +++++++++++-----------
 2 files changed, 25 insertions(+), 25 deletions(-)

From: Bin Meng <bin.meng@windriver.com>

Update the 'sifive_u' machine documentation to mention the '-dtb'
option that can be used to pass a custom DTB to QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/sifive_u.rst | 47 +++++++++++++++++++++++++++++-----
 1 file changed, 41 insertions(+), 6 deletions(-)

diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -XXX,XX +XXX,XX @@ Hardware configuration information
 ----------------------------------
 
 The ``sifive_u`` machine automatically generates a device tree blob ("dtb")
-which it passes to the guest. This provides information about the addresses,
-interrupt lines and other configuration of the various devices in the system.
-Guest software should discover the devices that are present in the generated
-DTB instead of using a DTB for the real hardware, as some of the devices are
-not modeled by QEMU and trying to access these devices may cause unexpected
-behavior.
+which it passes to the guest, if there is no ``-dtb`` option. This provides
+information about the addresses, interrupt lines and other configuration of
+the various devices in the system. Guest software should discover the devices
+that are present in the generated DTB instead of using a DTB for the real
+hardware, as some of the devices are not modeled by QEMU and trying to access
+these devices may cause unexpected behavior.
+
+If users want to provide their own DTB, they can use the ``-dtb`` option.
+These DTBs should have the following requirements:
+
+* The /cpus node should contain at least one subnode for E51 and the number
+  of subnodes should match QEMU's ``-smp`` option
+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
+* Should contain a node for the CLINT device with a compatible string
+  "riscv,clint0" if using with OpenSBI BIOS images
 
 Boot options
 ------------
@@ -XXX,XX +XXX,XX @@ To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine:
       -initrd /path/to/rootfs.ext4 \
       -append "root=/dev/ram"
 
+Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT
+node in fu540-c000.dtsi in the Linux kernel,
+
+.. code-block:: none
+
+    clint: clint@2000000 {
+        compatible = "riscv,clint0";
+        interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+                               &cpu1_intc 3 &cpu1_intc 7
+                               &cpu2_intc 3 &cpu2_intc 7
+                               &cpu3_intc 3 &cpu3_intc 7
+                               &cpu4_intc 3 &cpu4_intc 7>;
+        reg = <0x00 0x2000000 0x00 0x10000>;
+    };
+
+with the following command line options:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M sifive_u -smp 5 -m 8G \
+      -display none -serial stdio \
+      -kernel arch/riscv/boot/Image \
+      -dtb arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb \
+      -initrd /path/to/rootfs.ext4 \
+      -append "root=/dev/ram"
+
 To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine
 in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
 fix the 32-bit boot issue for Linux kernel v5.10.
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h | 5 +++++
 hw/riscv/sifive_u.c     | 6 ++----
 hw/riscv/spike.c        | 6 ++----
 hw/riscv/virt.c         | 6 ++----
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/loader.h"
 #include "hw/riscv/riscv_hart.h"
 
+#define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
+#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
+#define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
+#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
+
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
 
     if (riscv_is_32bit(&s->soc.u_cpus)) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv32-generic-fw_dynamic.bin",
-                                    start_addr, NULL);
+                                    RISCV32_BIOS_BIN, start_addr, NULL);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv64-generic-fw_dynamic.bin",
-                                    start_addr, NULL);
+                                    RISCV64_BIOS_BIN, start_addr, NULL);
     }
 
     if (machine->kernel_filename) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv32-generic-fw_dynamic.elf",
-                                    memmap[SPIKE_DRAM].base,
+                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv64-generic-fw_dynamic.elf",
-                                    memmap[SPIKE_DRAM].base,
+                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     }
 
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
 
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv32-generic-fw_dynamic.bin",
-                                    start_addr, NULL);
+                                    RISCV32_BIOS_BIN, start_addr, NULL);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    "opensbi-riscv64-generic-fw_dynamic.bin",
-                                    start_addr, NULL);
+                                    RISCV64_BIOS_BIN, start_addr, NULL);
     }
 
     if (machine->kernel_filename) {
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

At present the Microchip Icicle Kit machine only supports using
'-bios' to load the HSS, and does not support '-kernel' for direct
kernel booting just like other RISC-V machines do. One has to use
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
This is not so convenient.

Adding '-kernel' support together with the existing '-bios', we
follow the following table to select which payload we execute:

This ensures backwards compatibility with how we used to expose
'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
must be present to provide a valid device tree for the board,
as we don't generate device tree.

When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
is used to boot a payload like U-Boot or OS kernel directly.

Documentation is updated to describe the direct kernel boot. Note
as of today there is still no PolarFire SoC support in the upstream
Linux kernel hence the document does not include instructions for
that. It will be updated in the future.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 30 ++++++--
 hw/riscv/microchip_pfsoc.c                 | 81 +++++++++++++++++++++-
 2 files changed, 103 insertions(+), 8 deletions(-)

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/microchip-icicle-kit.rst
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@ Boot options
 
 The ``microchip-icicle-kit`` machine can start using the standard -bios
 functionality for loading its BIOS image, aka Hart Software Services (HSS_).
-HSS loads the second stage bootloader U-Boot from an SD card. It does not
-support direct kernel loading via the -kernel option. One has to load kernel
-from U-Boot.
+HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
+can be loaded from U-Boot. It also supports direct kernel booting via the
+-kernel option along with the device tree blob via -dtb. When direct kernel
+boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload
+like U-Boot or OS kernel directly.
+
+The user provided DTB should have the following requirements:
+
+* The /cpus node should contain at least one subnode for E51 and the number
+  of subnodes should match QEMU's ``-smp`` option
+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
+* Should contain a node for the CLINT device with a compatible string
+  "riscv,clint0"
+
+QEMU follows below truth table to select which payload to execute:
+
+=====  ========== =======
+-bios     -kernel payload
+=====  ========== =======
+    N           N     HSS
+    Y  don't care     HSS
+    N           Y  kernel
+=====  ========== =======
 
 The memory is set to 1537 MiB by default which is the minimum required high
 memory size by HSS. A sanity check on ram size is performed in the machine
 init routine to prompt user to increase the RAM size to > 1537 MiB when less
 than 1537 MiB ram is detected.
 
-Boot the machine
-----------------
+Running HSS
+-----------
 
 HSS 2020.12 release is tested at the time of writing. To build an HSS image
 that can be booted by the ``microchip-icicle-kit`` machine, type the following
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/microchip_pfsoc.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
+#include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
 
 /*
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
     uint64_t mem_high_size;
+    hwaddr firmware_load_addr;
+    const char *firmware_name;
+    bool kernel_as_payload = false;
+    target_ulong firmware_end_addr, kernel_start_addr;
+    uint64_t kernel_entry;
+    uint32_t fdt_load_addr;
     DriveInfo *dinfo = drive_get_next(IF_SD);
 
     /* Sanity check on RAM size */
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
                                 mem_high_alias);
 
-    /* Load the firmware */
-    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
-
     /* Attach an SD card */
     if (dinfo) {
         CadenceSDHCIState *sdhci = &(s->soc.sdhci);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                 &error_fatal);
         qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
     }
+
+    /*
+     * We follow the following table to select which payload we execute.
+     *
+     *  -bios |    -kernel | payload
+     * -------+------------+--------
+     *      N |          N | HSS
+     *      Y | don't care | HSS
+     *      N |          Y | kernel
+     *
+     * This ensures backwards compatibility with how we used to expose -bios
+     * to users but allows them to run through direct kernel booting as well.
+     *
+     * When -kernel is used for direct boot, -dtb must be present to provide
+     * a valid device tree for the board, as we don't generate device tree.
+     */
+
+    if (machine->kernel_filename && machine->dtb) {
+        int fdt_size;
+        machine->fdt = load_device_tree(machine->dtb, &fdt_size);
+        if (!machine->fdt) {
+            error_report("load_device_tree() failed");
+            exit(1);
+        }
+
+        firmware_name = RISCV64_BIOS_BIN;
+        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
+        kernel_as_payload = true;
+    }
+
+    if (!kernel_as_payload) {
+        firmware_name = BIOS_FILENAME;
+        firmware_load_addr = RESET_VECTOR;
+    }
+
+    /* Load the firmware */
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     firmware_load_addr, NULL);
+
+    if (kernel_as_payload) {
+        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+                                                         firmware_end_addr);
+
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
+                                         kernel_start_addr, NULL);
+
+        if (machine->initrd_filename) {
+            hwaddr start;
+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                           machine->ram_size, kernel_entry,
+                                           &start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+                                  "linux,initrd-start", start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+                                  "linux,initrd-end", end);
+        }
+
+        if (machine->kernel_cmdline) {
+            qemu_fdt_setprop_string(machine->fdt, "/chosen",
+                                    "bootargs", machine->kernel_cmdline);
+        }
+
+        /* Compute the fdt load address in dram */
+        fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+                                       machine->ram_size, machine->fdt);
+        /* Load the reset vector */
+        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
+                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
+                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+                                  kernel_entry, fdt_load_addr, machine->fdt);
+    }
 }
 
 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
-- 
2.31.1

From: Jose Martins <josemartins90@gmail.com>

The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:

If supervisor mode is not present:

- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.

If supervisor mode is present:

- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.

Plus, if the hypervisor extensions are enabled:

- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h  |  1 +
 target/riscv/op_helper.c | 11 ++++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define HSTATUS_HU           0x00000200
 #define HSTATUS_VGEIN        0x0003F000
 #define HSTATUS_VTVM         0x00100000
+#define HSTATUS_VTW          0x00200000
 #define HSTATUS_VTSR         0x00400000
 #define HSTATUS_VSXL         0x300000000
 
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
 void helper_wfi(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
+    bool rvs = riscv_has_ext(env, RVS);
+    bool prv_u = env->priv == PRV_U;
+    bool prv_s = env->priv == PRV_S;
 
-    if ((env->priv == PRV_S &&
-        get_field(env->mstatus, MSTATUS_TW)) ||
-        riscv_cpu_virt_enabled(env)) {
+    if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
+        (rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    } else if (riscv_cpu_virt_enabled(env) && (prv_u ||
+        (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
     } else {
         cs->halted = 1;
-- 
2.31.1

QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
---
 docs/system/deprecated.rst       | 19 -------------------
 docs/system/removed-features.rst |  5 +++++
 docs/system/target-riscv.rst     | 13 ++++++++++++-
 3 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ pcspk-audiodev=<name>``.
 ``tty`` and ``parport`` are aliases that will be removed. Instead, the
 actual backend names ``serial`` and ``parallel`` should be used.
 
-RISC-V ``-bios`` (since 5.1)
-''''''''''''''''''''''''''''
-
-QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
-RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
-default behaviour to avoid breakages.
-
-QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
-
-QEMU 5.1 has three options:
- 1. ``-bios default`` - This is the current default behavior if no -bios option
-      is included. This option will load the default OpenSBI firmware automatically.
-      The firmware is included with the QEMU release and no user interaction is
-      required. All a user needs to do is specify the kernel they want to boot
-      with the -kernel option
- 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
-      to the user to load all the images they need.
- 3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
-
 Short-form boolean options (since 6.0)
 ''''''''''''''''''''''''''''''''''''''
 
diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/removed-features.rst
+++ b/docs/system/removed-features.rst
@@ -XXX,XX +XXX,XX @@ devices.  Drives the board doesn't pick up can no longer be used with
 This option was undocumented and not used in the field.
 Use `-device usb-ccid`` instead.
 
+RISC-V firmware not booted by default (removed in 5.1)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``
+for the RISC-V ``virt`` machine and ``sifive_u`` machine.
 
 QEMU Machine Protocol (QMP) commands
 ------------------------------------
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    riscv/shakti-c
    riscv/sifive_u
 
-RISC-V CPU features
+RISC-V CPU firmware
 -------------------
+
+When using the ``sifive_u`` or ``virt`` machine there are three different
+firmware boot options:
+1. ``-bios default`` - This is the default behaviour if no -bios option
+is included. This option will load the default OpenSBI firmware automatically.
+The firmware is included with the QEMU release and no user interaction is
+required. All a user needs to do is specify the kernel they want to boot
+with the -kernel option
+2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
+to the user to load all the images they need.
+3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware.
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 --
 target/riscv/cpu.c | 4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
 
 extern const char * const riscv_int_regnames[];
 extern const char * const riscv_fpr_regnames[];
-extern const char * const riscv_excp_names[];
-extern const char * const riscv_intr_names[];
 
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 void riscv_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char * const riscv_fpr_regnames[] = {
   "f30/ft10", "f31/ft11"
 };
 
-const char * const riscv_excp_names[] = {
+static const char * const riscv_excp_names[] = {
     "misaligned_fetch",
     "fault_fetch",
     "illegal_instruction",
@@ -XXX,XX +XXX,XX @@ const char * const riscv_excp_names[] = {
     "guest_store_page_fault",
 };
 
-const char * const riscv_intr_names[] = {
+static const char * const riscv_intr_names[] = {
     "u_software",
     "s_software",
     "vs_software",
-- 
2.31.1

From: Changbin Du <changbin.du@gmail.com>

This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.

Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
     }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
     }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 #endif
 
     for (i = 0; i < 32; i++) {
-- 
2.31.1

Although we construct epmp_operation in such a way that it can only be
between 0 and 15 Coverity complains that we don't handle the other
possible cases. To fix Coverity and make it easier for humans to read
add a default case to the switch statement that calls
g_assert_not_reached().

Fixes: CID 1453108
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
                     case 15:
                         *allowed_privs = PMP_READ;
                         break;
+                    default:
+                        g_assert_not_reached();
                     }
                 } else {
                     switch (epmp_operation) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
                     case 7:
                         *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
                         break;
+                    default:
+                        g_assert_not_reached();
                     }
                 }
             }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
is still zero(as we don't use this field), simd_desc will trigger an
assert.

Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
Here we pass the value to maxsz and oprsz to bypass the assert.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 89 ++++++++++++++-----------
 1 file changed, 50 insertions(+), 39 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      * The first part is vlen in bytes, encoded in maxsz of simd_desc.
      * The second part is lmul, encoded in data of simd_desc.
      */
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     mask = tcg_temp_new_ptr();
     base = tcg_temp_new();
     stride = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     gen_get_gpr(stride, rs2);
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
-                           cpu_env, 0, s->vlen / 8, data, fn);
+                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
     }
     gen_set_label(over);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
-                           cpu_env, 0, s->vlen / 8,
+                           cpu_env, s->vlen / 8, s->vlen / 8,
                            data, fn);
         gen_set_label(over);
         return true;
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
-                           cpu_env, 0, s->vlen / 8, data, fn);
+                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
         gen_set_label(over);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew]);        \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew]);                           \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew]);        \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew]);                           \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             };
 
             tcg_gen_ext_tl_i64(s1_i64, s1);
-            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1_i64, cpu_env, desc);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
 
             s1 = tcg_const_i64(simm);
             dest = tcg_temp_new_ptr();
-            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1, cpu_env, desc);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew - 1]);    \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew - 1]);                       \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
-    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                            vreg_ofs(s, a->rs1),                  \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,      \
-                           s->vlen / 8, data, fns[s->sew - 1]);  \
+                           vreg_ofs(s, a->rs2), cpu_env,         \
+                           s->vlen / 8, s->vlen / 8, data,       \
+                           fns[s->sew - 1]);                     \
         gen_set_label(over);                                     \
         return true;                                             \
     }                                                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew - 1]);    \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew - 1]);                       \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew - 1]);    \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew - 1]);                       \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
             dest = tcg_temp_new_ptr();
-            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew - 1]);    \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew - 1]);                       \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fns[s->sew - 1]);    \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data,         \
+                           fns[s->sew - 1]);                       \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
-                           s->vlen / 8, data, fn);                 \
+                           vreg_ofs(s, a->rs2), cpu_env,           \
+                           s->vlen / 8, s->vlen / 8, data, fn);    \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = tcg_temp_new();
-        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = tcg_temp_new();
-        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
-                           cpu_env, 0, s->vlen / 8, data, fn);     \
+                           cpu_env, s->vlen / 8, s->vlen / 8,      \
+                           data, fn);                              \
         gen_set_label(over);                                       \
         return true;                                               \
     }                                                              \
@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
             gen_helper_viota_m_w, gen_helper_viota_m_d,
         };
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                           vreg_ofs(s, a->rs2), cpu_env, 0,
-                           s->vlen / 8, data, fns[s->sew]);
+                           vreg_ofs(s, a->rs2), cpu_env,
+                           s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
         gen_set_label(over);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
             gen_helper_vid_v_w, gen_helper_vid_v_d,
         };
         tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
-                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+                           cpu_env, s->vlen / 8, s->vlen / 8,
+                           data, fns[s->sew]);
         gen_set_label(over);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
-                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+                           cpu_env, s->vlen / 8, s->vlen / 8, data,
+                           fns[s->sew]);
         gen_set_label(over);
         return true;
     }
-- 
2.31.1

From: Kito Cheng <kito.cheng@sifive.com>

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %rd        7:5
 %sh5       20:5
 
-%sh10    20:10
+%sh7    20:7
 %csr    20:12
 %rm     12:3
 %nf     29:3                     !function=ex_plus_1
@@ -XXX,XX +XXX,XX @@
 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
 
-@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
+@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
 
 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@@ -XXX,XX +XXX,XX @@ sltiu    ............     ..... 011 ..... 0010011 @i
 xori     ............     ..... 100 ..... 0010011 @i
 ori      ............     ..... 110 ..... 0010011 @i
 andi     ............     ..... 111 ..... 0010011 @i
-slli     00.... ......    ..... 001 ..... 0010011 @sh
-srli     00.... ......    ..... 101 ..... 0010011 @sh
-srai     01.... ......    ..... 101 ..... 0010011 @sh
+slli     00000. ......    ..... 001 ..... 0010011 @sh
+srli     00000. ......    ..... 101 ..... 0010011 @sh
+srai     01000. ......    ..... 101 ..... 0010011 @sh
 add      0000000 .....    ..... 000 ..... 0110011 @r
 sub      0100000 .....    ..... 000 ..... 0110011 @r
 sll      0000000 .....    ..... 001 ..... 0110011 @r
-- 
2.31.1

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                      |  1 +
 target/riscv/insn32.decode              | 11 ++++++-
 target/riscv/translate.c                | 38 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
 4 files changed, 93 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
+#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 &i    imm rs1 rd
 &j    imm rd
 &r    rd rs1 rs2
+&r2   rd rs1
 &s    imm rs1 rs2
 &u    imm rd
 &shift     shamt rs1 rd
@@ -XXX,XX +XXX,XX @@
 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
+@r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -XXX,XX +XXX,XX @@ vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+
+# *** RV32B Standard Extension ***
+clz        011000 000000 ..... 001 ..... 0010011 @r2
+ctz        011000 000001 ..... 001 ..... 0010011 @r2
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw       0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
     return true;
 }
 
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
+    tcg_gen_ctzi_tl(ret, ret, 64);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(ret, arg1);
+    tcg_gen_clzi_tl(ret, ret, 64);
+    tcg_gen_subi_tl(ret, ret, 32);
+}
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
     return cpu_ldl_code(env, pc);
 }
 
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+                      void(*func)(TCGv, TCGv))
+{
+    TCGv source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+
+    (*func)(source, source);
+
+    gen_set_gpr(a->rd, source);
+    tcg_temp_free(source);
+    return true;
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvd.c.inc"
 #include "insn_trans/trans_rvh.c.inc"
 #include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, gen_ctz);
+}
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, gen_ctzw);
+}
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  2 ++
 target/riscv/translate.c                |  6 ++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 # *** RV32B Standard Extension ***
 clz        011000 000000 ..... 001 ..... 0010011 @r2
 ctz        011000 000001 ..... 001 ..... 0010011 @r2
+cpop       011000 000010 ..... 001 ..... 0010011 @r2
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
     tcg_gen_subi_tl(ret, ret, 32);
 }
 
+static void gen_cpopw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_ctpop_tl(ret, arg1);
+}
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
     return gen_unary(ctx, a, gen_ctz);
 }
 
+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+}
+
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_unary(ctx, a, gen_ctzw);
 }
+
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, gen_cpopw);
+}
-- 
2.31.1

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  3 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  6 ++++
 target/riscv/translate.c                | 40 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
 3 files changed, 78 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  4 ++++
 target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  3 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
 2 files changed, 15 insertions(+)

From: Frank Chang <frank.chang@sifive.com>

Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 39 ++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
 2 files changed, 43 insertions(+), 50 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
     return cpu_ldl_code(env, pc);
 }
 
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
+                       void(*func)(TCGv, TCGv, TCGv))
+{
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    TCGv source1 = tcg_temp_new();
+    TCGv source2 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+
+    tcg_gen_movi_tl(source2, a->shamt);
+    (*func)(source1, source1, source2);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+    return true;
+}
+
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+                        void(*func)(TCGv, TCGv, TCGv))
+{
+    TCGv source1 = tcg_temp_new();
+    TCGv source2 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+    tcg_gen_movi_tl(source2, a->shamt);
+
+    (*func)(source1, source1, source2);
+    tcg_gen_ext32s_tl(source1, source1);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+    return true;
+}
+
 static void gen_ctz(TCGv ret, TCGv arg1)
 {
     tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
 }
 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 {
-    if (a->shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    if (a->rd != 0) {
-        TCGv t = tcg_temp_new();
-        gen_get_gpr(t, a->rs1);
-
-        tcg_gen_shli_tl(t, t, a->shamt);
-
-        gen_set_gpr(a->rd, t);
-        tcg_temp_free(t);
-    } /* NOP otherwise */
-    return true;
+    return gen_shifti(ctx, a, tcg_gen_shl_tl);
 }
 
 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 {
-    if (a->shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    if (a->rd != 0) {
-        TCGv t = tcg_temp_new();
-        gen_get_gpr(t, a->rs1);
-
-        tcg_gen_shri_tl(t, t, a->shamt);
-        gen_set_gpr(a->rd, t);
-        tcg_temp_free(t);
-    } /* NOP otherwise */
-    return true;
+    return gen_shifti(ctx, a, tcg_gen_shr_tl);
 }
 
 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 {
-    if (a->shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    if (a->rd != 0) {
-        TCGv t = tcg_temp_new();
-        gen_get_gpr(t, a->rs1);
-
-        tcg_gen_sari_tl(t, t, a->shamt);
-        gen_set_gpr(a->rd, t);
-        tcg_temp_free(t);
-    } /* NOP otherwise */
-    return true;
+    return gen_shifti(ctx, a, tcg_gen_sar_tl);
 }
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv source1;
-    source1 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
-
-    tcg_gen_shli_tl(source1, source1, a->shamt);
-    tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(a->rd, source1);
-
-    tcg_temp_free(source1);
-    return true;
+    return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
 }
 
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 17 +++++
 target/riscv/translate.c                | 61 ++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
 3 files changed, 175 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 max        0000101 .......... 110 ..... 0110011 @r
 maxu       0000101 .......... 111 ..... 0110011 @r
+bset       0010100 .......... 001 ..... 0110011 @r
+bclr       0100100 .......... 001 ..... 0110011 @r
+binv       0110100 .......... 001 ..... 0110011 @r
+bext       0100100 .......... 101 ..... 0110011 @r
+
+bseti      00101. ........... 001 ..... 0010011 @sh
+bclri      01001. ........... 001 ..... 0010011 @sh
+binvi      01101. ........... 001 ..... 0010011 @sh
+bexti      01001. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
+bsetw      0010100 .......... 001 ..... 0111011 @r
+bclrw      0100100 .......... 001 ..... 0111011 @r
+binvw      0110100 .......... 001 ..... 0111011 @r
+bextw      0100100 .......... 101 ..... 0111011 @r
+
+bsetiw     0010100 .......... 001 ..... 0011011 @sh5
+bclriw     0100100 .......... 001 ..... 0011011 @sh5
+binviw     0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+    tcg_gen_movi_tl(ret, 1);
+    tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_or_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_andc_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_xor_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    tcg_gen_shr_tl(ret, arg1, shamt);
+    tcg_gen_andi_tl(ret, ret, 1);
+}
+
 static void gen_ctzw(TCGv ret, TCGv arg1)
 {
     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -XXX,XX +XXX,XX @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
     return true;
 }
 
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
+                       void(*func)(TCGv, TCGv, TCGv))
+{
+    TCGv source1 = tcg_temp_new();
+    TCGv source2 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(source2, a->rs2);
+
+    tcg_gen_andi_tl(source2, source2, 31);
+    (*func)(source1, source1, source2);
+    tcg_gen_ext32s_tl(source1, source1);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+    return true;
+}
+
 static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
                         void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
     return gen_unary(ctx, a, tcg_gen_ext16s_tl);
 }
 
+static bool trans_bset(DisasContext *ctx, arg_bset *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shift(ctx, a, gen_bset);
+}
+
+static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shifti(ctx, a, gen_bset);
+}
+
+static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shift(ctx, a, gen_bclr);
+}
+
+static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shifti(ctx, a, gen_bclr);
+}
+
+static bool trans_binv(DisasContext *ctx, arg_binv *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shift(ctx, a, gen_binv);
+}
+
+static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shifti(ctx, a, gen_binv);
+}
+
+static bool trans_bext(DisasContext *ctx, arg_bext *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shift(ctx, a, gen_bext);
+}
+
+static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shifti(ctx, a, gen_bext);
+}
+
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_arith(ctx, a, gen_packuw);
 }
+
+static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftw(ctx, a, gen_bset);
+}
+
+static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftiw(ctx, a, gen_bset);
+}
+
+static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftw(ctx, a, gen_bclr);
+}
+
+static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftiw(ctx, a, gen_bclr);
+}
+
+static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftw(ctx, a, gen_binv);
+}
+
+static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftiw(ctx, a, gen_binv);
+}
+
+static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftw(ctx, a, gen_bext);
+}
-- 
2.31.1

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  8 ++++
 target/riscv/translate.c                | 14 +++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
 3 files changed, 74 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  6 ++++
 target/riscv/translate.c                | 36 +++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
 3 files changed, 81 insertions(+)

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  4 ++
 target/riscv/insn32.decode              |  4 ++
 target/riscv/bitmanip_helper.c          | 64 +++++++++++++++++++++++++
 target/riscv/translate.c                | 28 +++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 31 ++++++++++++
 target/riscv/meson.build                |  1 +
 6 files changed, 132 insertions(+)
 create mode 100644 target/riscv/bitmanip_helper.c

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
 /* Special functions */
 DEF_HELPER_3(csrrw, tl, env, tl, tl)
 DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ slo        0010000 .......... 001 ..... 0110011 @r
 sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
+grev       0110100 .......... 101 ..... 0110011 @r
 
 bseti      00101. ........... 001 ..... 0010011 @sh
 bclri      01001. ........... 001 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ bexti      01001. ........... 101 ..... 0010011 @sh
 sloi       00100. ........... 001 ..... 0010011 @sh
 sroi       00100. ........... 101 ..... 0010011 @sh
 rori       01100. ........... 101 ..... 0010011 @sh
+grevi      01101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
@@ -XXX,XX +XXX,XX @@ slow       0010000 .......... 001 ..... 0111011 @r
 srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
+grevw      0110100 .......... 101 ..... 0111011 @r
 
 bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 bclriw     0100100 .......... 001 ..... 0011011 @sh5
@@ -XXX,XX +XXX,XX @@ binviw     0110100 .......... 001 ..... 0011011 @sh5
 sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
+greviw     0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+    dup_const(MO_8, 0x55),
+    dup_const(MO_8, 0x33),
+    dup_const(MO_8, 0x0f),
+    dup_const(MO_16, 0xff),
+    dup_const(MO_32, 0xffff),
+    UINT32_MAX
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+    return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+                            target_ulong rs2,
+                            int bits)
+{
+    target_ulong x = rs1;
+    int i, shift;
+
+    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+        if (rs2 & shift) {
+            x = do_swap(x, adjacent_masks[i], shift);
+        }
+    }
+
+    return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+    return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+    return do_grev(rs1, rs2, 32);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_gen_not_tl(ret, ret);
 }
 
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    TCGv source1 = tcg_temp_new();
+    TCGv source2;
+
+    gen_get_gpr(source1, a->rs1);
+
+    if (a->shamt == (TARGET_LONG_BITS - 8)) {
+        /* rev8, byte swaps */
+        tcg_gen_bswap_tl(source1, source1);
+    } else {
+        source2 = tcg_temp_new();
+        tcg_gen_movi_tl(source2, a->shamt);
+        gen_helper_grev(source1, source1, source2);
+        tcg_temp_free(source2);
+    }
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    return true;
+}
+
 static void gen_ctzw(TCGv ret, TCGv arg1)
 {
     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free_i32(t2);
 }
 
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    gen_helper_grev(ret, arg1, arg2);
+}
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, tcg_gen_rotl_tl);
 }
 
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shift(ctx, a, gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_grevi(ctx, a);
+}
+
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_shiftw(ctx, a, gen_rolw);
 }
+
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftw(ctx, a, gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_shiftiw(ctx, a, gen_grevw);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'gdbstub.c',
   'op_helper.c',
   'vector_helper.c',
+  'bitmanip_helper.c',
   'translate.c',
 ))
 
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 ++
 target/riscv/insn32.decode              |  4 ++++
 target/riscv/bitmanip_helper.c          | 26 +++++++++++++++++++++++++
 target/riscv/translate.c                |  6 ++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
 5 files changed, 64 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  6 +++++
 target/riscv/translate.c                | 32 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
 3 files changed, 62 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
 gorc       0010100 .......... 101 ..... 0110011 @r
+sh1add     0010000 .......... 010 ..... 0110011 @r
+sh2add     0010000 .......... 100 ..... 0110011 @r
+sh3add     0010000 .......... 110 ..... 0110011 @r
 
 bseti      00101. ........... 001 ..... 0010011 @sh
 bclri      01001. ........... 001 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
+sh1add_uw  0010000 .......... 010 ..... 0111011 @r
+sh2add_uw  0010000 .......... 100 ..... 0111011 @r
+sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 
 bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 bclriw     0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
     return true;
 }
 
+#define GEN_SHADD(SHAMT)                                       \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                              \
+    TCGv t = tcg_temp_new();                                   \
+                                                               \
+    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
+    tcg_gen_add_tl(ret, t, arg2);                              \
+                                                               \
+    tcg_temp_free(t);                                          \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
 static void gen_ctzw(TCGv ret, TCGv arg1)
 {
     tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -XXX,XX +XXX,XX @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
     gen_helper_gorcw(ret, arg1, arg2);
 }
 
+#define GEN_SHADD_UW(SHAMT)                                       \
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                                 \
+    TCGv t = tcg_temp_new();                                      \
+                                                                  \
+    tcg_gen_ext32u_tl(t, arg1);                                   \
+                                                                  \
+    tcg_gen_shli_tl(t, t, SHAMT);                                 \
+    tcg_gen_add_tl(ret, t, arg2);                                 \
+                                                                  \
+    tcg_temp_free(t);                                             \
+}
+
+GEN_SHADD_UW(1)
+GEN_SHADD_UW(2)
+GEN_SHADD_UW(3)
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
     return gen_shifti(ctx, a, gen_helper_gorc);
 }
 
+#define GEN_TRANS_SHADD(SHAMT)                                             \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{                                                                          \
+    REQUIRE_EXT(ctx, RVB);                                                 \
+    return gen_arith(ctx, a, gen_sh##SHAMT##add);                          \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_shiftiw(ctx, a, gen_gorcw);
 }
+
+#define GEN_TRANS_SHADD_UW(SHAMT)                             \
+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
+                                    arg_sh##SHAMT##add_uw *a) \
+{                                                             \
+    REQUIRE_64BIT(ctx);                                       \
+    REQUIRE_EXT(ctx, RVB);                                    \
+    return gen_arith(ctx, a, gen_sh##SHAMT##add_uw);          \
+}
+
+GEN_TRANS_SHADD_UW(1)
+GEN_TRANS_SHADD_UW(2)
+GEN_TRANS_SHADD_UW(3)
-- 
2.31.1

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  3 +++
 target/riscv/translate.c                |  6 ++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

From: Kito Cheng <kito.cheng@sifive.com>

B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
+        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
+        if (cpu->cfg.ext_b) {
+            target_misa |= RVB;
+        }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Default b-ext version is v0.93.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  3 +++
 target/riscv/cpu.c | 23 +++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
+#define BEXT_VERSION_0_93_0 0x00009300
 #define VEXT_VERSION_0_07_1 0x00000701
 
 enum {
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong guest_phys_fault_addr;
 
     target_ulong priv_ver;
+    target_ulong bext_ver;
     target_ulong vext_ver;
     target_ulong misa;
     target_ulong misa_mask;
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
 
         char *priv_spec;
         char *user_spec;
+        char *bext_spec;
         char *vext_spec;
         uint16_t vlen;
         uint16_t elen;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
     env->priv_ver = priv_ver;
 }
 
+static void set_bext_version(CPURISCVState *env, int bext_ver)
+{
+    env->bext_ver = bext_ver;
+}
+
 static void set_vext_version(CPURISCVState *env, int vext_ver)
 {
     env->vext_ver = vext_ver;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     int priv_version = PRIV_VERSION_1_11_0;
+    int bext_version = BEXT_VERSION_0_93_0;
     int vext_version = VEXT_VERSION_0_07_1;
     target_ulong target_misa = env->misa;
     Error *local_err = NULL;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     set_priv_version(env, priv_version);
+    set_bext_version(env, bext_version);
     set_vext_version(env, vext_version);
 
     if (cpu->cfg.mmu) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
         if (cpu->cfg.ext_b) {
             target_misa |= RVB;
+
+            if (cpu->cfg.bext_spec) {
+                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
+                    bext_version = BEXT_VERSION_0_93_0;
+                } else {
+                    error_setg(errp,
+                           "Unsupported bitmanip spec version '%s'",
+                           cpu->cfg.bext_spec);
+                    return;
+                }
+            } else {
+                qemu_log("bitmanip version is not specified, "
+                         "use the default value v0.93\n");
+            }
+            set_bext_version(env, bext_version);
         }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:

Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122

for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:

hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 6.2

- Deprecate IF_NONE for SiFive OTP
 - Don't reset SiFive OTP content

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset

Thomas Huth (1):
      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE

docs/about/deprecated.rst |  6 ++++++
 hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

From: Thomas Huth <thuth@redhat.com>

Configuring a drive with "if=none" is meant for creation of a backend
only, it should not get automatically assigned to a device frontend.
Use "if=pflash" for the One-Time-Programmable device instead (like
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).

Since the old way of configuring the device has already been published
with the previous QEMU versions, we cannot remove this immediately, but
have to deprecate it and support it for at least two more releases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211119102549.217755-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 6 ++++++
 hw/misc/sifive_u_otp.c    | 9 ++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
 However, short-form booleans are deprecated and full explicit ``arg_name=on``
 form is preferred.
 
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
+
 
 QEMU Machine Protocol (QMP) commands
 ------------------------------------
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
                           TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 
-    dinfo = drive_get_next(IF_NONE);
+    dinfo = drive_get_next(IF_PFLASH);
+    if (!dinfo) {
+        dinfo = drive_get_next(IF_NONE);
+        if (dinfo) {
+            warn_report("using \"-drive if=none\" for the OTP is deprecated, "
+                        "use \"-drive if=pflash\" instead.");
+        }
+    }
     if (dinfo) {
         int ret;
         uint64_t perm;
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Once a "One Time Programmable" is programmed, it shouldn't be reset.

Do not re-initialize the OTP content in the DeviceReset handler,
initialize it once in the DeviceRealize one.

Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_u_otp.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
 
             if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
                 error_setg(errp, "failed to read the initial flash content");
+                return;
             }
         }
     }
-}
-
-static void sifive_u_otp_reset(DeviceState *dev)
-{
-    SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
 
     /* Initialize all fuses' initial value to 0xFFs */
     memset(s->fuse, 0xff, sizeof(s->fuse));
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
         serial_data = s->serial;
         if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index);
+            error_setg(errp, "failed to write index<%d>", index);
+            return;
         }
 
         serial_data = ~(s->serial);
         if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
                        &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
-            error_report("write error index<%d>", index + 1);
+            error_setg(errp, "failed to write index<%d>", index + 1);
+            return;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
 
     device_class_set_props(dc, sifive_u_otp_properties);
     dc->realize = sifive_u_otp_realize;
-    dc->reset = sifive_u_otp_reset;
 }
 
 static const TypeInfo sifive_u_otp_info = {
-- 
2.31.1