Series comparison

-[PULL 00/15] tcg patch queue
+[PULL 00/20] tcg patch queue
-The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:
+TCG patch queue, plus one target/sh4 patch that
 Yoshinori Sato asked me to process.
-  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)
 r~
 The following changes since commit efbf38d73e5dcc4d5f8b98c6e7a12be1f3b91745:
   Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-10-03 15:06:07 -0400)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004
-for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:
+for you to fetch changes up to ab419fd8a035a65942de4e63effcd55ccbf1a9fe:
-  tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)
+  target/sh4: Fix TB_FLAG_UNALIGN (2022-10-04 12:33:05 -0700)
 ----------------------------------------------------------------
-Host vector support for arm neon.
+Cache CPUClass for use in hot code paths.
 Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
 Add generic support for TARGET_TB_PCREL.
 tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
 target/sh4: Fix TB_FLAG_UNALIGN
 ----------------------------------------------------------------
-Richard Henderson (15):
+Alex Bennée (3):
-      tcg: Change parameters for tcg_target_const_match
+      cpu: cache CPUClass in CPUState for hot code paths
-      tcg/arm: Add host vector framework
+      hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
-      tcg/arm: Implement tcg_out_ld/st for vector types
+      cputlb: used cached CPUClass in our hot-paths
       tcg/arm: Implement tcg_out_mov for vector types
       tcg/arm: Implement tcg_out_dup*_vec
       tcg/arm: Implement minimal vector operations
       tcg/arm: Implement andc, orc, abs, neg, not vector operations
       tcg/arm: Implement TCG_TARGET_HAS_shi_vec
       tcg/arm: Implement TCG_TARGET_HAS_mul_vec
       tcg/arm: Implement TCG_TARGET_HAS_sat_vec
       tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
       tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
       tcg/arm: Implement TCG_TARGET_HAS_shv_vec
       tcg/arm: Implement TCG_TARGET_HAS_roti_vec
       tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
- tcg/arm/tcg-target-con-set.h |  10 +
+Leandro Lupori (1):
- tcg/arm/tcg-target-con-str.h |   3 +
+      tcg/ppc: Optimize 26-bit jumps
  tcg/arm/tcg-target.h         |  52 ++-
  tcg/arm/tcg-target.opc.h     |  16 +
  tcg/tcg.c                    |   5 +-
  tcg/aarch64/tcg-target.c.inc |   5 +-
  tcg/arm/tcg-target.c.inc     | 956 +++++++++++++++++++++++++++++++++++++++++--
  tcg/i386/tcg-target.c.inc    |   4 +-
  tcg/mips/tcg-target.c.inc    |   5 +-
  tcg/ppc/tcg-target.c.inc     |   4 +-
  tcg/riscv/tcg-target.c.inc   |   4 +-
  tcg/s390/tcg-target.c.inc    |   5 +-
  tcg/sparc/tcg-target.c.inc   |   5 +-
  tcg/tci/tcg-target.c.inc     |   6 +-
 files changed, 1001 insertions(+), 79 deletions(-)
  create mode 100644 tcg/arm/tcg-target.opc.h
+Richard Henderson (16):
+      accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
+      accel/tcg: Drop addr member from SavedIOTLB
+      accel/tcg: Suppress auto-invalidate in probe_access_internal
+      accel/tcg: Introduce probe_access_full
+      accel/tcg: Introduce tlb_set_page_full
+      include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
+      accel/tcg: Remove PageDesc code_bitmap
+      accel/tcg: Use bool for page_find_alloc
+      accel/tcg: Use DisasContextBase in plugin_gen_tb_start
+      accel/tcg: Do not align tb->page_addr[0]
+      accel/tcg: Inline tb_flush_jmp_cache
+      include/hw/core: Create struct CPUJumpCache
+      hw/core: Add CPUClass.get_pc
+      accel/tcg: Introduce tb_pc and log_pc
+      accel/tcg: Introduce TARGET_TB_PCREL
+      target/sh4: Fix TB_FLAG_UNALIGN
+ accel/tcg/internal.h                    |  10 ++
+ accel/tcg/tb-hash.h                     |   1 +
+ accel/tcg/tb-jmp-cache.h                |  65 ++++++++
+ include/exec/cpu-common.h               |   1 +
+ include/exec/cpu-defs.h                 |  48 ++++--
+ include/exec/exec-all.h                 |  75 ++++++++-
+ include/exec/plugin-gen.h               |   7 +-
+ include/hw/core/cpu.h                   |  28 ++--
+ include/qemu/typedefs.h                 |   2 +
+ include/tcg/tcg.h                       |   2 +-
+ target/sh4/cpu.h                        |  56 ++++---
+ accel/stubs/tcg-stub.c                  |   4 +
+ accel/tcg/cpu-exec.c                    |  80 +++++-----
+ accel/tcg/cputlb.c                      | 259 ++++++++++++++++++--------------
+ accel/tcg/plugin-gen.c                  |  22 +--
+ accel/tcg/translate-all.c               | 214 ++++++++++++--------------
+ accel/tcg/translator.c                  |   2 +-
+ cpu.c                                   |   9 +-
+ hw/core/cpu-common.c                    |   3 +-
+ hw/core/cpu-sysemu.c                    |   5 +-
+ linux-user/sh4/signal.c                 |   6 +-
+ plugins/core.c                          |   2 +-
+ target/alpha/cpu.c                      |   9 ++
+ target/arm/cpu.c                        |  17 ++-
+ target/arm/mte_helper.c                 |  14 +-
+ target/arm/sve_helper.c                 |   4 +-
+ target/arm/translate-a64.c              |   2 +-
+ target/avr/cpu.c                        |  10 +-
+ target/cris/cpu.c                       |   8 +
+ target/hexagon/cpu.c                    |  10 +-
+ target/hppa/cpu.c                       |  12 +-
+ target/i386/cpu.c                       |   9 ++
+ target/i386/tcg/tcg-cpu.c               |   2 +-
+ target/loongarch/cpu.c                  |  11 +-
+ target/m68k/cpu.c                       |   8 +
+ target/microblaze/cpu.c                 |  10 +-
+ target/mips/cpu.c                       |   8 +
+ target/mips/tcg/exception.c             |   2 +-
+ target/mips/tcg/sysemu/special_helper.c |   2 +-
+ target/nios2/cpu.c                      |   9 ++
+ target/openrisc/cpu.c                   |  10 +-
+ target/ppc/cpu_init.c                   |   8 +
+ target/riscv/cpu.c                      |  17 ++-
+ target/rx/cpu.c                         |  10 +-
+ target/s390x/cpu.c                      |   8 +
+ target/s390x/tcg/mem_helper.c           |   4 -
+ target/sh4/cpu.c                        |  18 ++-
+ target/sh4/helper.c                     |   6 +-
+ target/sh4/translate.c                  |  90 +++++------
+ target/sparc/cpu.c                      |  10 +-
+ target/tricore/cpu.c                    |  11 +-
+ target/xtensa/cpu.c                     |   8 +
+ tcg/tcg.c                               |   8 +-
+ trace/control-target.c                  |   2 +-
+ tcg/ppc/tcg-target.c.inc                | 119 +++++++++++----
+files changed, 915 insertions(+), 462 deletions(-)
+ create mode 100644 accel/tcg/tb-jmp-cache.h

-New patch
+[PULL 01/20] cpu: cache CPUClass in CPUState for hot code paths
+From: Alex Bennée <alex.bennee@linaro.org>
+The class cast checkers are quite expensive and always on (unlike the
+dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
+avoid the overhead of repeatedly checking something which should never
+change we cache the CPUClass reference for use in the hot code paths.
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Message-Id: <20220923084803.498337-3-clg@kaod.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ include/hw/core/cpu.h | 9 +++++++++
+ cpu.c                 | 9 ++++-----
+files changed, 13 insertions(+), 5 deletions(-)
+diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/core/cpu.h
++++ b/include/hw/core/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
+  */
+ #define CPU(obj) ((CPUState *)(obj))
++/*
++ * The class checkers bring in CPU_GET_CLASS() which is potentially
++ * expensive given the eventual call to
++ * object_class_dynamic_cast_assert(). Because of this the CPUState
++ * has a cached value for the class in cs->cc which is set up in
++ * cpu_exec_realizefn() for use in hot code paths.
++ */
+ typedef struct CPUClass CPUClass;
+ DECLARE_CLASS_CHECKERS(CPUClass, CPU,
+                        TYPE_CPU)
+@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
+ struct CPUState {
+     /*< private >*/
+     DeviceState parent_obj;
++    /* cache to avoid expensive CPU_GET_CLASS */
++    CPUClass *cc;
+     /*< public >*/
+     int nr_cores;
+diff --git a/cpu.c b/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/cpu.c
++++ b/cpu.c
+@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_cpu_common = {
+ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
+ {
+-#ifndef CONFIG_USER_ONLY
+-    CPUClass *cc = CPU_GET_CLASS(cpu);
+-#endif
++    /* cache the cpu class for the hotpath */
++    cpu->cc = CPU_GET_CLASS(cpu);
+     cpu_list_add(cpu);
+     if (!accel_cpu_realizefn(cpu, errp)) {
+@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
+     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
+     }
+-    if (cc->sysemu_ops->legacy_vmsd != NULL) {
+-        vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
++    if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
++        vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
+     }
+ #endif /* CONFIG_USER_ONLY */
+ }
+--
+.34.1

-New patch
+[PULL 02/20] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
+From: Alex Bennée <alex.bennee@linaro.org>
+This is a heavily used function so lets avoid the cost of
+CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
+  Before: 36.812 s ±  0.506 s
+  After:  35.912 s ±  0.168 s
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Message-Id: <20220923084803.498337-4-clg@kaod.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ hw/core/cpu-sysemu.c | 5 ++---
+file changed, 2 insertions(+), 3 deletions(-)
+diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/core/cpu-sysemu.c
++++ b/hw/core/cpu-sysemu.c
+@@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+ {
+-    CPUClass *cc = CPU_GET_CLASS(cpu);
+     int ret = 0;
+-    if (cc->sysemu_ops->asidx_from_attrs) {
+-        ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
++    if (cpu->cc->sysemu_ops->asidx_from_attrs) {
++        ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
+         assert(ret < cpu->num_ases && ret >= 0);
+     }
+     return ret;
+--
+.34.1

-New patch
+[PULL 03/20] cputlb: used cached CPUClass in our hot-paths
+From: Alex Bennée <alex.bennee@linaro.org>
+Before: 35.912 s ±  0.168 s
+  After: 35.565 s ±  0.087 s
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Message-Id: <20220923084803.498337-5-clg@kaod.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ accel/tcg/cputlb.c | 15 ++++++---------
+file changed, 6 insertions(+), 9 deletions(-)
+diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/tcg/cputlb.c
++++ b/accel/tcg/cputlb.c
+@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
+ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
+                      MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+ {
+-    CPUClass *cc = CPU_GET_CLASS(cpu);
+     bool ok;
+     /*
+      * This is not a probe, so only valid return is success; failure
+      * should result in exception + longjmp to the cpu loop.
+      */
+-    ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
+-                               access_type, mmu_idx, false, retaddr);
++    ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size,
++                                    access_type, mmu_idx, false, retaddr);
+     assert(ok);
+ }
+@@ -XXX,XX +XXX,XX @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
+                                         MMUAccessType access_type,
+                                         int mmu_idx, uintptr_t retaddr)
+ {
+-    CPUClass *cc = CPU_GET_CLASS(cpu);
+-
+-    cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
++    cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type,
++                                          mmu_idx, retaddr);
+ }
+ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
+     if (!tlb_hit_page(tlb_addr, page_addr)) {
+         if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
+             CPUState *cs = env_cpu(env);
+-            CPUClass *cc = CPU_GET_CLASS(cs);
+-            if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
+-                                       mmu_idx, nonfault, retaddr)) {
++            if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
++                                           mmu_idx, nonfault, retaddr)) {
+                 /* Non-faulting page table read failed.  */
+                 *phost = NULL;
+                 return TLB_INVALID_MASK;
+--
+.34.1

-[PULL 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
+[PULL 04/20] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
-Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
+This structure will shortly contain more than just
 data for accessing MMIO.  Rename the 'addr' member
 to 'xlat_section' to more clearly indicate its purpose.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
+ include/exec/cpu-defs.h    |  22 ++++----
-file changed, 34 insertions(+), 1 deletion(-)
+ accel/tcg/cputlb.c         | 102 +++++++++++++++++++------------------
  target/arm/mte_helper.c    |  14 ++---
  target/arm/sve_helper.c    |   4 +-
  target/arm/translate-a64.c |   2 +-
 files changed, 73 insertions(+), 71 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/include/exec/cpu-defs.h
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/include/exec/cpu-defs.h
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+@@ -XXX,XX +XXX,XX @@ typedef uint64_t target_ulong;
-     case INDEX_op_shrv_vec:
+ #  endif
-     case INDEX_op_sarv_vec:
+ # endif
-     case INDEX_op_rotli_vec:
-+    case INDEX_op_rotlv_vec:
++/* Minimalized TLB entry for use by TCG fast path. */
-+    case INDEX_op_rotrv_vec:
+ typedef struct CPUTLBEntry {
-         return -1;
+     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
-     default:
+        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
-         return 0;
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-                        TCGArg a0, ...)
+ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 -/* The IOTLB is not accessed directly inline by generated TCG code,
 - * so the CPUIOTLBEntry layout is not as critical as that of the
 - * CPUTLBEntry. (This is also why we don't want to combine the two
 - * structs into one.)
 +/*
 + * The full TLB entry, which is not accessed by generated TCG code,
 + * so the layout is not as critical as that of CPUTLBEntry. This is
 + * also why we don't want to combine the two structs.
   */
 -typedef struct CPUIOTLBEntry {
 +typedef struct CPUTLBEntryFull {
      /*
 -     * @addr contains:
 +     * @xlat_section contains:
       *  - in the lower TARGET_PAGE_BITS, a physical section number
       *  - with the lower TARGET_PAGE_BITS masked off, an offset which
       *    must be added to the virtual address to obtain:
@@ -XXX,XX +XXX,XX @@ typedef struct CPUIOTLBEntry {
       *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
       *     + the offset within the target MemoryRegion (otherwise)
       */
 -    hwaddr addr;
 +    hwaddr xlat_section;
      MemTxAttrs attrs;
 -} CPUIOTLBEntry;
 +} CPUTLBEntryFull;
  /*
   * Data elements that are per MMU mode, minus the bits accessed by
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBDesc {
      size_t vindex;
      /* The tlb victim table, in two parts.  */
      CPUTLBEntry vtable[CPU_VTLB_SIZE];
 -    CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
 -    /* The iotlb.  */
 -    CPUIOTLBEntry *iotlb;
 +    CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
 +    CPUTLBEntryFull *fulltlb;
  } CPUTLBDesc;
  /*
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cputlb.c
 +++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
      }
      g_free(fast->table);
 -    g_free(desc->iotlb);
 +    g_free(desc->fulltlb);
      tlb_window_reset(desc, now, 0);
      /* desc->n_used_entries is cleared by the caller */
      fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
      fast->table = g_try_new(CPUTLBEntry, new_size);
 -    desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
 +    desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
      /*
       * If the allocations fail, try smaller sizes. We just freed some
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
       * allocations to fail though, so we progressively reduce the allocation
       * size, aborting if we cannot even allocate the smallest TLB we support.
       */
 -    while (fast->table == NULL || desc->iotlb == NULL) {
 +    while (fast->table == NULL || desc->fulltlb == NULL) {
          if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
              error_report("%s: %s", __func__, strerror(errno));
              abort();
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
          fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
          g_free(fast->table);
 -        g_free(desc->iotlb);
 +        g_free(desc->fulltlb);
          fast->table = g_try_new(CPUTLBEntry, new_size);
 -        desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
 +        desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
      desc->n_used_entries = 0;
      fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
      fast->table = g_new(CPUTLBEntry, n_entries);
 -    desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
 +    desc->fulltlb = g_new(CPUTLBEntryFull, n_entries);
      tlb_mmu_flush_locked(desc, fast);
  }
@@ -XXX,XX +XXX,XX @@ void tlb_destroy(CPUState *cpu)
          CPUTLBDescFast *fast = &env_tlb(env)->f[i];
          g_free(fast->table);
 -        g_free(desc->iotlb);
 +        g_free(desc->fulltlb);
      }
  }
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
          /* Evict the old entry into the victim tlb.  */
          copy_tlb_helper_locked(tv, te);
 -        desc->viotlb[vidx] = desc->iotlb[index];
 +        desc->vfulltlb[vidx] = desc->fulltlb[index];
          tlb_n_used_entries_dec(env, mmu_idx);
      }
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
       * subtract here is that of the page base, and not the same as the
       * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
       */
 -    desc->iotlb[index].addr = iotlb - vaddr_page;
 -    desc->iotlb[index].attrs = attrs;
 +    desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
 +    desc->fulltlb[index].attrs = attrs;
      /* Now calculate the new entry */
      tn.addend = addend - vaddr_page;
@@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
      }
  }
 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
 +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
                           int mmu_idx, target_ulong addr, uintptr_t retaddr,
                           MMUAccessType access_type, MemOp op)
  {
-     va_list va;
+@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
--    TCGv_vec v0, v1, v2, t1;
+     bool locked = false;
-+    TCGv_vec v0, v1, v2, t1, t2, c1;
+     MemTxResult r;
-     TCGArg a2;
+-    section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
-     va_start(va, a0);
++    section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+     mr = section->mr;
-         tcg_temp_free_vec(t1);
+-    mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
-         break;
++    mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
+     cpu->mem_io_pc = retaddr;
-+    case INDEX_op_rotlv_vec:
+     if (!cpu->can_do_io) {
-+        v2 = temp_tcgv_vec(arg_temp(a2));
+         cpu_io_recompile(cpu, retaddr);
-+        t1 = tcg_temp_new_vec(type);
+@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
-+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+         qemu_mutex_lock_iothread();
-+        tcg_gen_sub_vec(vece, t1, v2, c1);
+         locked = true;
-+        /* Right shifts are negative left shifts for NEON.  */
+     }
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+-    r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
++    r = memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs);
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+     if (r != MEMTX_OK) {
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+         hwaddr physaddr = mr_offset +
-+        tcg_gen_or_vec(vece, v0, v0, t1);
+             section->offset_within_address_space -
-+        tcg_temp_free_vec(t1);
+             section->offset_within_region;
-+        break;
-+
+         cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type,
-+    case INDEX_op_rotrv_vec:
+-                               mmu_idx, iotlbentry->attrs, r, retaddr);
-+        v2 = temp_tcgv_vec(arg_temp(a2));
++                               mmu_idx, full->attrs, r, retaddr);
-+        t1 = tcg_temp_new_vec(type);
+     }
-+        t2 = tcg_temp_new_vec(type);
+     if (locked) {
-+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+         qemu_mutex_unlock_iothread();
-+        tcg_gen_neg_vec(vece, t1, v2);
+@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
-+        tcg_gen_sub_vec(vece, t2, c1, v2);
+ }
-+        /* Right shifts are negative left shifts for NEON.  */
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+ /*
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+- * Save a potentially trashed IOTLB entry for later lookup by plugin.
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
+- * This is read by tlb_plugin_lookup if the iotlb entry doesn't match
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
++ * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
-+        tcg_gen_or_vec(vece, v0, t1, t2);
++ * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
-+        tcg_temp_free_vec(t1);
+  * because of the side effect of io_writex changing memory layout.
-+        tcg_temp_free_vec(t2);
+  */
-+        break;
+ static void save_iotlb_data(CPUState *cs, hwaddr addr,
-+
+@@ -XXX,XX +XXX,XX @@ static void save_iotlb_data(CPUState *cs, hwaddr addr,
-     default:
+ #endif
-         g_assert_not_reached();
+ }
-     }
 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
 +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
                        int mmu_idx, uint64_t val, target_ulong addr,
                        uintptr_t retaddr, MemOp op)
  {
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
      bool locked = false;
      MemTxResult r;
 -    section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
 +    section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
      mr = section->mr;
 -    mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
 +    mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
      if (!cpu->can_do_io) {
          cpu_io_recompile(cpu, retaddr);
      }
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
       * The memory_region_dispatch may trigger a flush/resize
       * so for plugins we save the iotlb_data just in case.
       */
 -    save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset);
 +    save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
      if (!qemu_mutex_iothread_locked()) {
          qemu_mutex_lock_iothread();
          locked = true;
      }
 -    r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
 +    r = memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs);
      if (r != MEMTX_OK) {
          hwaddr physaddr = mr_offset +
              section->offset_within_address_space -
              section->offset_within_region;
          cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
 -                               MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
 +                               MMU_DATA_STORE, mmu_idx, full->attrs, r,
                                 retaddr);
      }
      if (locked) {
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
              copy_tlb_helper_locked(vtlb, &tmptlb);
              qemu_spin_unlock(&env_tlb(env)->c.lock);
 -            CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index];
 -            CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx];
 -            tmpio = *io; *io = *vio; *vio = tmpio;
 +            CPUTLBEntryFull *f1 = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 +            CPUTLBEntryFull *f2 = &env_tlb(env)->d[mmu_idx].vfulltlb[vidx];
 +            CPUTLBEntryFull tmpf;
 +            tmpf = *f1; *f1 = *f2; *f2 = tmpf;
              return true;
          }
      }
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
                   (ADDR) & TARGET_PAGE_MASK)
  static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
 -                           CPUIOTLBEntry *iotlbentry, uintptr_t retaddr)
 +                           CPUTLBEntryFull *full, uintptr_t retaddr)
  {
 -    ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr;
 +    ram_addr_t ram_addr = mem_vaddr + full->xlat_section;
      trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size);
@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
      /* Handle clean RAM pages.  */
      if (unlikely(flags & TLB_NOTDIRTY)) {
          uintptr_t index = tlb_index(env, mmu_idx, addr);
 -        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 +        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 -        notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
 +        notdirty_write(env_cpu(env), addr, 1, full, retaddr);
          flags &= ~TLB_NOTDIRTY;
      }
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
      if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
          uintptr_t index = tlb_index(env, mmu_idx, addr);
 -        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 +        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
          /* Handle watchpoints.  */
          if (flags & TLB_WATCHPOINT) {
              int wp_access = (access_type == MMU_DATA_STORE
                               ? BP_MEM_WRITE : BP_MEM_READ);
              cpu_check_watchpoint(env_cpu(env), addr, size,
 -                                 iotlbentry->attrs, wp_access, retaddr);
 +                                 full->attrs, wp_access, retaddr);
          }
          /* Handle clean RAM pages.  */
          if (flags & TLB_NOTDIRTY) {
 -            notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
 +            notdirty_write(env_cpu(env), addr, 1, full, retaddr);
          }
      }
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
   * should have just filled the TLB. The one corner case is io_writex
   * which can cause TLB flushes and potential resizing of the TLBs
   * losing the information we need. In those cases we need to recover
 - * data from a copy of the iotlbentry. As long as this always occurs
 + * data from a copy of the CPUTLBEntryFull. As long as this always occurs
   * from the same thread (which a mem callback will be) this is safe.
   */
@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
      if (likely(tlb_hit(tlb_addr, addr))) {
          /* We must have an iotlb entry for MMIO */
          if (tlb_addr & TLB_MMIO) {
 -            CPUIOTLBEntry *iotlbentry;
 -            iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 +            CPUTLBEntryFull *full;
 +            full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
              data->is_io = true;
 -            data->v.io.section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
 -            data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
 +            data->v.io.section =
 +                iotlb_to_section(cpu, full->xlat_section, full->attrs);
 +            data->v.io.offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
          } else {
              data->is_io = false;
              data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
      if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
          notdirty_write(env_cpu(env), addr, size,
 -                       &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr);
 +                       &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr);
      }
      return hostaddr;
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
      /* Handle anything that isn't just a straight memory access.  */
      if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 -        CPUIOTLBEntry *iotlbentry;
 +        CPUTLBEntryFull *full;
          bool need_swap;
          /* For anything that is unaligned, recurse through full_load.  */
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
              goto do_unaligned_access;
          }
 -        iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 +        full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
          /* Handle watchpoints.  */
          if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
              /* On watchpoint hit, this will longjmp out.  */
              cpu_check_watchpoint(env_cpu(env), addr, size,
 -                                 iotlbentry->attrs, BP_MEM_READ, retaddr);
 +                                 full->attrs, BP_MEM_READ, retaddr);
          }
          need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
          /* Handle I/O access.  */
          if (likely(tlb_addr & TLB_MMIO)) {
 -            return io_readx(env, iotlbentry, mmu_idx, addr, retaddr,
 +            return io_readx(env, full, mmu_idx, addr, retaddr,
                              access_type, op ^ (need_swap * MO_BSWAP));
          }
@@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
       */
      if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
          cpu_check_watchpoint(env_cpu(env), addr, size - size2,
 -                             env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
 +                             env_tlb(env)->d[mmu_idx].fulltlb[index].attrs,
                               BP_MEM_WRITE, retaddr);
      }
      if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) {
          cpu_check_watchpoint(env_cpu(env), page2, size2,
 -                             env_tlb(env)->d[mmu_idx].iotlb[index2].attrs,
 +                             env_tlb(env)->d[mmu_idx].fulltlb[index2].attrs,
                               BP_MEM_WRITE, retaddr);
      }
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
      /* Handle anything that isn't just a straight memory access.  */
      if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 -        CPUIOTLBEntry *iotlbentry;
 +        CPUTLBEntryFull *full;
          bool need_swap;
          /* For anything that is unaligned, recurse through byte stores.  */
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
              goto do_unaligned_access;
          }
 -        iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 +        full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
          /* Handle watchpoints.  */
          if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
              /* On watchpoint hit, this will longjmp out.  */
              cpu_check_watchpoint(env_cpu(env), addr, size,
 -                                 iotlbentry->attrs, BP_MEM_WRITE, retaddr);
 +                                 full->attrs, BP_MEM_WRITE, retaddr);
          }
          need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
          /* Handle I/O access.  */
          if (tlb_addr & TLB_MMIO) {
 -            io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
 +            io_writex(env, full, mmu_idx, val, addr, retaddr,
                        op ^ (need_swap * MO_BSWAP));
              return;
          }
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
          /* Handle clean RAM pages.  */
          if (tlb_addr & TLB_NOTDIRTY) {
 -            notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
 +            notdirty_write(env_cpu(env), addr, size, full, retaddr);
          }
          haddr = (void *)((uintptr_t)addr + entry->addend);
 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mte_helper.c
 +++ b/target/arm/mte_helper.c
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      return tags + index;
  #else
      uintptr_t index;
 -    CPUIOTLBEntry *iotlbentry;
 +    CPUTLBEntryFull *full;
      int in_page, flags;
      ram_addr_t ptr_ra;
      hwaddr ptr_paddr, tag_paddr, xlat;
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      assert(!(flags & TLB_INVALID_MASK));
      /*
 -     * Find the iotlbentry for ptr.  This *must* be present in the TLB
 +     * Find the CPUTLBEntryFull for ptr.  This *must* be present in the TLB
       * because we just found the mapping.
       * TODO: Perhaps there should be a cputlb helper that returns a
       * matching tlb entry + iotlb entry.
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
          g_assert(tlb_hit(comparator, ptr));
      }
  # endif
 -    iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index];
 +    full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
      /* If the virtual page MemAttr != Tagged, access unchecked. */
 -    if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) {
 +    if (!arm_tlb_mte_tagged(&full->attrs)) {
          return NULL;
      }
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
          int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
          assert(ra != 0);
          cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
 -                             iotlbentry->attrs, wp, ra);
 +                             full->attrs, wp, ra);
      }
      /*
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
      /* Look up the address in tag space. */
 -    tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
 +    tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
      tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
      mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
                                   tag_access == MMU_DATA_STORE,
 -                                 iotlbentry->attrs);
 +                                 full->attrs);
      /*
       * Note that @mr will never be NULL.  If there is nothing in the address
 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve_helper.c
 +++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
          g_assert(tlb_hit(comparator, addr));
  # endif
 -        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
 -        info->attrs = iotlbentry->attrs;
 +        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 +        info->attrs = full->attrs;
      }
  #endif
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
       * table entry even for that case.
       */
      return (tlb_hit(entry->addr_code, addr) &&
 -            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs));
 +            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs));
  #endif
  }
 --
-.25.1
+.34.1

-[PULL 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
+[PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB
-NEON has 3 instructions implementing this 4 argument operation,
+This field is only written, not read; remove it.
 with each insn overlapping a different logical input onto the
 destination register.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+ include/hw/core/cpu.h | 1 -
- tcg/arm/tcg-target.h         |  2 +-
+ accel/tcg/cputlb.c    | 7 +++----
- tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
+files changed, 3 insertions(+), 5 deletions(-)
 files changed, 22 insertions(+), 3 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/include/hw/core/cpu.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/include/hw/core/cpu.h
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(w, w, w)
+@@ -XXX,XX +XXX,XX @@ struct CPUWatchpoint {
- C_O1_I2(w, w, wO)
+  * the memory regions get moved around  by io_writex.
- C_O1_I2(w, w, wV)
+  */
- C_O1_I2(w, w, wZ)
+ typedef struct SavedIOTLB {
-+C_O1_I3(w, w, w, w)
+-    hwaddr addr;
- C_O1_I4(r, r, r, rI, rI)
+     MemoryRegionSection *section;
- C_O1_I4(r, r, rIN, rIK, 0)
+     hwaddr mr_offset;
- C_O2_I1(r, r, l)
+ } SavedIOTLB;
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/accel/tcg/cputlb.c
-+++ b/tcg/arm/tcg-target.h
++++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
- #define TCG_TARGET_HAS_mul_vec          1
+  * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
- #define TCG_TARGET_HAS_sat_vec          1
+  * because of the side effect of io_writex changing memory layout.
- #define TCG_TARGET_HAS_minmax_vec       1
+  */
--#define TCG_TARGET_HAS_bitsel_vec       0
+-static void save_iotlb_data(CPUState *cs, hwaddr addr,
-+#define TCG_TARGET_HAS_bitsel_vec       1
+-                            MemoryRegionSection *section, hwaddr mr_offset)
- #define TCG_TARGET_HAS_cmpsel_vec       0
++static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
++                            hwaddr mr_offset)
  #define TCG_TARGET_DEFAULT_MO (0)
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VSARI     = 0xf2800010,  /* VSHR.S */
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VBSL      = 0xf3100110,
 +    INSN_VBIT      = 0xf3200110,
 +    INSN_VBIF      = 0xf3300110,
 +
      INSN_VTST      = 0xf2000810,
      INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
          return C_O1_I2(w, w, wV);
      case INDEX_op_cmp_vec:
          return C_O1_I2(w, w, wZ);
 -
 +    case INDEX_op_bitsel_vec:
 +        return C_O1_I3(w, w, w, w);
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
  {
-     TCGType type = vecl + TCG_TYPE_V64;
+ #ifdef CONFIG_PLUGIN
-     unsigned q = vecl;
+     SavedIOTLB *saved = &cs->saved_iotlb;
--    TCGArg a0, a1, a2;
+-    saved->addr = addr;
-+    TCGArg a0, a1, a2, a3;
+     saved->section = section;
-     int cmode, imm8;
+     saved->mr_offset = mr_offset;
+ #endif
-     a0 = args[0];
+@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+      * The memory_region_dispatch may trigger a flush/resize
-         }
+      * so for plugins we save the iotlb_data just in case.
-         return;
+      */
+-    save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
-+    case INDEX_op_bitsel_vec:
++    save_iotlb_data(cpu, section, mr_offset);
-+        a3 = args[3];
-+        if (a0 == a3) {
+     if (!qemu_mutex_iothread_locked()) {
-+            tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
+         qemu_mutex_lock_iothread();
 +        } else if (a0 == a2) {
 +            tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
 +        } else {
 +            tcg_out_mov(s, type, a0, a1);
 +            tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
 +        }
 +        return;
 +
      case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
      case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
      default:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_sssub_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
 +    case INDEX_op_bitsel_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
-.25.1
+.34.1

-[PULL 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
+[PULL 06/20] accel/tcg: Suppress auto-invalidate in probe_access_internal
-This is minimum and maximum, signed and unsigned.
+When PAGE_WRITE_INV is set when calling tlb_set_page,
 we immediately set TLB_INVALID_MASK in order to force
 tlb_fill to be called on the next lookup.  Here in
 probe_access_internal, we have just called tlb_fill
 and eliminated true misses, thus the lookup must be valid.
+This allows us to remove a warning comment from s390x.
+There doesn't seem to be a reason to change the code though.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: David Hildenbrand <david@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ accel/tcg/cputlb.c            | 10 +++++++++-
- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
+ target/s390x/tcg/mem_helper.c |  4 ----
-files changed, 25 insertions(+), 1 deletion(-)
+files changed, 9 insertions(+), 5 deletions(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/accel/tcg/cputlb.c
-+++ b/tcg/arm/tcg-target.h
++++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
- #define TCG_TARGET_HAS_shv_vec          0
+     }
- #define TCG_TARGET_HAS_mul_vec          1
+     tlb_addr = tlb_read_ofs(entry, elt_ofs);
- #define TCG_TARGET_HAS_sat_vec          1
--#define TCG_TARGET_HAS_minmax_vec       0
++    flags = TLB_FLAGS_MASK;
-+#define TCG_TARGET_HAS_minmax_vec       1
+     page_addr = addr & TARGET_PAGE_MASK;
- #define TCG_TARGET_HAS_bitsel_vec       0
+     if (!tlb_hit_page(tlb_addr, page_addr)) {
- #define TCG_TARGET_HAS_cmpsel_vec       0
+         if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
              /* TLB resize via tlb_fill may have moved the entry.  */
              entry = tlb_entry(env, mmu_idx, addr);
 +
 +            /*
 +             * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
 +             * to force the next access through tlb_fill.  We've just
 +             * called tlb_fill, so we know that this entry *is* valid.
 +             */
 +            flags &= ~TLB_INVALID_MASK;
          }
          tlb_addr = tlb_read_ofs(entry, elt_ofs);
      }
 -    flags = tlb_addr & TLB_FLAGS_MASK;
 +    flags &= tlb_addr;
      /* Fold all "mmio-like" bits into TLB_MMIO.  This is not RAM.  */
      if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/s390x/tcg/mem_helper.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/s390x/tcg/mem_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
-     INSN_VQADD_U   = 0xf3000010,
+ #else
-     INSN_VQSUB     = 0xf2000210,
+     int flags;
-     INSN_VQSUB_U   = 0xf3000210,
-+    INSN_VMAX      = 0xf2000600,
+-    /*
-+    INSN_VMAX_U    = 0xf3000600,
+-     * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
-+    INSN_VMIN      = 0xf2000610,
+-     * to detect if there was an exception during tlb_fill().
-+    INSN_VMIN_U    = 0xf3000610,
+-     */
+     env->tlb_fill_exc = 0;
-     INSN_VABS      = 0xf3b10300,
+     flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost,
-     INSN_VMVN      = 0xf3b00580,
+                                ra);
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
      case INDEX_op_mul_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
      case INDEX_op_ssadd_vec:
      case INDEX_op_sssub_vec:
      case INDEX_op_sub_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_mul_vec:
          tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_smax_vec:
 +        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_smin_vec:
 +        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sssub_vec:
          tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_umax_vec:
 +        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_umin_vec:
 +        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_usadd_vec:
          tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_cmp_vec:
      case INDEX_op_mul_vec:
      case INDEX_op_neg_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
          return vece < MO_64;
      default:
          return 0;
 --
-.25.1
+.34.1

-[PULL 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec
+[PULL 07/20] accel/tcg: Introduce probe_access_full
-Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
+Add an interface to return the CPUTLBEntryFull struct
-For NEON, this is shift-right followed by shift-left-and-insert.
+that goes with the lookup.  The result is not intended
 to be valid across multiple lookups, so the user must
 use the results immediately.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+ include/exec/exec-all.h | 15 +++++++++++++
- tcg/arm/tcg-target.opc.h     |  1 +
+ include/qemu/typedefs.h |  1 +
- tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
+ accel/tcg/cputlb.c      | 47 +++++++++++++++++++++++++----------------
-files changed, 17 insertions(+)
+files changed, 45 insertions(+), 18 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/include/exec/exec-all.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
+@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
- C_O1_I2(r, r, rIN)
+                        MMUAccessType access_type, int mmu_idx,
- C_O1_I2(r, r, ri)
+                        bool nonfault, void **phost, uintptr_t retaddr);
- C_O1_I2(r, rZ, rZ)
-+C_O1_I2(w, 0, w)
++#ifndef CONFIG_USER_ONLY
- C_O1_I2(w, w, w)
++/**
- C_O1_I2(w, w, wO)
++ * probe_access_full:
- C_O1_I2(w, w, wV)
++ * Like probe_access_flags, except also return into @pfull.
-diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
++ *
 + * The CPUTLBEntryFull structure returned via @pfull is transient
 + * and must be consumed or copied immediately, before any further
 + * access or changes to TLB @mmu_idx.
 + */
 +int probe_access_full(CPUArchState *env, target_ulong addr,
 +                      MMUAccessType access_type, int mmu_idx,
 +                      bool nonfault, void **phost,
 +                      CPUTLBEntryFull **pfull, uintptr_t retaddr);
 +#endif
 +
  #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  /* Estimated block size for TB allocation.  */
 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.opc.h
+--- a/include/qemu/typedefs.h
-+++ b/tcg/arm/tcg-target.opc.h
++++ b/include/qemu/typedefs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
-  * consider these to be UNSPEC with names.
+ typedef struct CPUAddressSpace CPUAddressSpace;
-  */
+ typedef struct CPUArchState CPUArchState;
+ typedef struct CPUState CPUState;
-+DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
++typedef struct CPUTLBEntryFull CPUTLBEntryFull;
- DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+ typedef struct DeviceListener DeviceListener;
- DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
+ typedef struct DeviceState DeviceState;
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+ typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot;
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/accel/tcg/cputlb.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
-     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
+ static int probe_access_internal(CPUArchState *env, target_ulong addr,
-     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+                                  int fault_size, MMUAccessType access_type,
-     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+                                  int mmu_idx, bool nonfault,
-+    INSN_VSLI      = 0xf3800510,
+-                                 void **phost, uintptr_t retaddr)
-     INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
++                                 void **phost, CPUTLBEntryFull **pfull,
-     INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
++                                 uintptr_t retaddr)
+ {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     uintptr_t index = tlb_index(env, mmu_idx, addr);
-     case INDEX_op_arm_sshl_vec:
+     CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
-     case INDEX_op_arm_ushl_vec:
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
-         return C_O1_I2(w, w, w);
+                                            mmu_idx, nonfault, retaddr)) {
-+    case INDEX_op_arm_sli_vec:
+                 /* Non-faulting page table read failed.  */
-+        return C_O1_I2(w, 0, w);
+                 *phost = NULL;
-     case INDEX_op_or_vec:
++                *pfull = NULL;
-     case INDEX_op_andc_vec:
+                 return TLB_INVALID_MASK;
-         return C_O1_I2(w, w, wO);
+             }
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-     case INDEX_op_sari_vec:
+             /* TLB resize via tlb_fill may have moved the entry.  */
-         tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
++            index = tlb_index(env, mmu_idx, addr);
-         return;
+             entry = tlb_entry(env, mmu_idx, addr);
-+    case INDEX_op_arm_sli_vec:
-+        tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
+             /*
-+        return;
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
+     }
-     case INDEX_op_andc_vec:
+     flags &= tlb_addr;
-         if (!const_args[2]) {
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
++    *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index];
-     case INDEX_op_shlv_vec:
++
-     case INDEX_op_shrv_vec:
+     /* Fold all "mmio-like" bits into TLB_MMIO.  This is not RAM.  */
-     case INDEX_op_sarv_vec:
+     if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
-+    case INDEX_op_rotli_vec:
+         *phost = NULL;
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
      return flags;
  }
 -int probe_access_flags(CPUArchState *env, target_ulong addr,
 -                       MMUAccessType access_type, int mmu_idx,
 -                       bool nonfault, void **phost, uintptr_t retaddr)
 +int probe_access_full(CPUArchState *env, target_ulong addr,
 +                      MMUAccessType access_type, int mmu_idx,
 +                      bool nonfault, void **phost, CPUTLBEntryFull **pfull,
 +                      uintptr_t retaddr)
  {
 -    int flags;
 -
 -    flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
 -                                  nonfault, phost, retaddr);
 +    int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
 +                                      nonfault, phost, pfull, retaddr);
      /* Handle clean RAM pages.  */
      if (unlikely(flags & TLB_NOTDIRTY)) {
 -        uintptr_t index = tlb_index(env, mmu_idx, addr);
 -        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 -
 -        notdirty_write(env_cpu(env), addr, 1, full, retaddr);
 +        notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr);
          flags &= ~TLB_NOTDIRTY;
      }
      return flags;
  }
 +int probe_access_flags(CPUArchState *env, target_ulong addr,
 +                       MMUAccessType access_type, int mmu_idx,
 +                       bool nonfault, void **phost, uintptr_t retaddr)
 +{
 +    CPUTLBEntryFull *full;
 +
 +    return probe_access_full(env, addr, access_type, mmu_idx,
 +                             nonfault, phost, &full, retaddr);
 +}
 +
  void *probe_access(CPUArchState *env, target_ulong addr, int size,
                     MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
  {
 +    CPUTLBEntryFull *full;
      void *host;
      int flags;
      g_assert(-(addr | TARGET_PAGE_MASK) >= size);
      flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
 -                                  false, &host, retaddr);
 +                                  false, &host, &full, retaddr);
      /* Per the interface, size == 0 merely faults the access. */
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
      }
      if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
 -        uintptr_t index = tlb_index(env, mmu_idx, addr);
 -        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 -
          /* Handle watchpoints.  */
          if (flags & TLB_WATCHPOINT) {
              int wp_access = (access_type == MMU_DATA_STORE
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
  void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
                          MMUAccessType access_type, int mmu_idx)
  {
 +    CPUTLBEntryFull *full;
      void *host;
      int flags;
      flags = probe_access_internal(env, addr, 0, access_type,
 -                                  mmu_idx, true, &host, 0);
 +                                  mmu_idx, true, &host, &full, 0);
      /* No combination of flags are expected by the caller. */
      return flags ? NULL : host;
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
  tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
                                          void **hostp)
  {
 +    CPUTLBEntryFull *full;
      void *p;
      (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
 -                                cpu_mmu_index(env, true), false, &p, 0);
 +                                cpu_mmu_index(env, true), false, &p, &full, 0);
      if (p == NULL) {
          return -1;
-     default:
-         return 0;
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-         tcg_temp_free_vec(t1);
-         break;
-+    case INDEX_op_rotli_vec:
-+        t1 = tcg_temp_new_vec(type);
-+        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
-+        vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
-+                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
-+        tcg_temp_free_vec(t1);
-+        break;
-+
-     default:
-         g_assert_not_reached();
      }
 --
-.25.1
+.34.1

-[PULL 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec
+[PULL 08/20] accel/tcg: Introduce tlb_set_page_full
-This consists of the three immediate shifts: shli, shri, sari.
+Now that we have collected all of the page data into
 CPUTLBEntryFull, provide an interface to record that
 all in one go, instead of using 4 arguments.  This interface
 allows CPUTLBEntryFull to be extended without having to
 change the number of arguments.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ include/exec/cpu-defs.h | 14 +++++++++++
- tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
+ include/exec/exec-all.h | 22 ++++++++++++++++++
-files changed, 28 insertions(+), 1 deletion(-)
+ accel/tcg/cputlb.c      | 51 ++++++++++++++++++++++++++---------------
 files changed, 69 insertions(+), 18 deletions(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/include/exec/cpu-defs.h
-+++ b/tcg/arm/tcg-target.h
++++ b/include/exec/cpu-defs.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
- #define TCG_TARGET_HAS_roti_vec         0
+      *     + the offset within the target MemoryRegion (otherwise)
- #define TCG_TARGET_HAS_rots_vec         0
+      */
- #define TCG_TARGET_HAS_rotv_vec         0
+     hwaddr xlat_section;
--#define TCG_TARGET_HAS_shi_vec          0
++
-+#define TCG_TARGET_HAS_shi_vec          1
++    /*
- #define TCG_TARGET_HAS_shs_vec          0
++     * @phys_addr contains the physical address in the address space
- #define TCG_TARGET_HAS_shv_vec          0
++     * given by cpu_asidx_from_attrs(cpu, @attrs).
- #define TCG_TARGET_HAS_mul_vec          0
++     */
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
++    hwaddr phys_addr;
 +
 +    /* @attrs contains the memory transaction attributes for the page. */
      MemTxAttrs attrs;
 +
 +    /* @prot contains the complete protections for the page. */
 +    uint8_t prot;
 +
 +    /* @lg_page_size contains the log2 of the page size. */
 +    uint8_t lg_page_size;
  } CPUTLBEntryFull;
  /*
 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/include/exec/exec-all.h
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
-     INSN_VCGE_U    = 0xf3000310,
+                                                uint16_t idxmap,
-     INSN_VCGT_U    = 0xf3000300,
+                                                unsigned bits);
-+    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
++/**
-+    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
++ * tlb_set_page_full:
-+    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
++ * @cpu: CPU context
 + * @mmu_idx: mmu index of the tlb to modify
 + * @vaddr: virtual address of the entry to add
 + * @full: the details of the tlb entry
 + *
 + * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 + * @full must be filled, except for xlat_section, and constitute
 + * the complete description of the translated page.
 + *
 + * This is generally called by the target tlb_fill function after
 + * having performed a successful page table walk to find the physical
 + * address and attributes for the translation.
 + *
 + * At most one entry for a given virtual address is permitted. Only a
 + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 + * used by tlb_flush_page.
 + */
 +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
 +                       CPUTLBEntryFull *full);
 +
-     INSN_VTST      = 0xf2000810,
+ /**
+  * tlb_set_page_with_attrs:
-     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+  * @cpu: CPU to add this TLB entry for
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
-               | (extract32(imm8, 7, 1) << 24));
+index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cputlb.c
 +++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
      env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
  }
-+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+-/* Add a new TLB entry. At most one entry for a given virtual address
-+                            TCGReg rd, TCGReg rm, int l_imm6)
++/*
 + * Add a new TLB entry. At most one entry for a given virtual address
   * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
   * supplied size is only used by tlb_flush_page.
   *
   * Called from TCG-generated code, which is under an RCU read-side
   * critical section.
   */
 -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 -                             hwaddr paddr, MemTxAttrs attrs, int prot,
 -                             int mmu_idx, target_ulong size)
 +void tlb_set_page_full(CPUState *cpu, int mmu_idx,
 +                       target_ulong vaddr, CPUTLBEntryFull *full)
  {
      CPUArchState *env = cpu->env_ptr;
      CPUTLB *tlb = env_tlb(env);
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
      CPUTLBEntry *te, tn;
      hwaddr iotlb, xlat, sz, paddr_page;
      target_ulong vaddr_page;
 -    int asidx = cpu_asidx_from_attrs(cpu, attrs);
 -    int wp_flags;
 +    int asidx, wp_flags, prot;
      bool is_ram, is_romd;
      assert_cpu_is_self(cpu);
 -    if (size <= TARGET_PAGE_SIZE) {
 +    if (full->lg_page_size <= TARGET_PAGE_BITS) {
          sz = TARGET_PAGE_SIZE;
      } else {
 -        tlb_add_large_page(env, mmu_idx, vaddr, size);
 -        sz = size;
 +        sz = (hwaddr)1 << full->lg_page_size;
 +        tlb_add_large_page(env, mmu_idx, vaddr, sz);
      }
      vaddr_page = vaddr & TARGET_PAGE_MASK;
 -    paddr_page = paddr & TARGET_PAGE_MASK;
 +    paddr_page = full->phys_addr & TARGET_PAGE_MASK;
 +    prot = full->prot;
 +    asidx = cpu_asidx_from_attrs(cpu, full->attrs);
      section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
 -                                                &xlat, &sz, attrs, &prot);
 +                                                &xlat, &sz, full->attrs, &prot);
      assert(sz >= TARGET_PAGE_SIZE);
      tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
                " prot=%x idx=%d\n",
 -              vaddr, paddr, prot, mmu_idx);
 +              vaddr, full->phys_addr, prot, mmu_idx);
      address = vaddr_page;
 -    if (size < TARGET_PAGE_SIZE) {
 +    if (full->lg_page_size < TARGET_PAGE_BITS) {
          /* Repeat the MMU check and TLB fill on every access.  */
          address |= TLB_INVALID_MASK;
      }
 -    if (attrs.byte_swap) {
 +    if (full->attrs.byte_swap) {
          address |= TLB_BSWAP;
      }
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
       * subtract here is that of the page base, and not the same as the
       * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
       */
 +    desc->fulltlb[index] = *full;
      desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
 -    desc->fulltlb[index].attrs = attrs;
 +    desc->fulltlb[index].phys_addr = paddr_page;
 +    desc->fulltlb[index].prot = prot;
      /* Now calculate the new entry */
      tn.addend = addend - vaddr_page;
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
      qemu_spin_unlock(&tlb->c.lock);
  }
 -/* Add a new TLB entry, but without specifying the memory
 - * transaction attributes to be used.
 - */
 +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 +                             hwaddr paddr, MemTxAttrs attrs, int prot,
 +                             int mmu_idx, target_ulong size)
 +{
-+    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
++    CPUTLBEntryFull full = {
-+              (extract32(l_imm6, 6, 1) << 7) |
++        .phys_addr = paddr,
-+              (extract32(l_imm6, 0, 6) << 16));
++        .attrs = attrs,
 +        .prot = prot,
 +        .lg_page_size = ctz64(size)
 +    };
 +
 +    assert(is_power_of_2(size));
 +    tlb_set_page_full(cpu, mmu_idx, vaddr, &full);
 +}
 +
- static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
-                           TCGReg rd, TCGReg rn, int offset)
+                   hwaddr paddr, int prot,
- {
+                   int mmu_idx, target_ulong size)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_abs_vec:
      case INDEX_op_neg_vec:
      case INDEX_op_not_vec:
 +    case INDEX_op_shli_vec:
 +    case INDEX_op_shri_vec:
 +    case INDEX_op_sari_vec:
          return C_O1_I1(w, w);
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_shli_vec:
 +        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
 +        return;
 +    case INDEX_op_shri_vec:
 +        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
 +        return;
 +    case INDEX_op_sari_vec:
 +        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
 +        return;
      case INDEX_op_andc_vec:
          if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_orc_vec:
      case INDEX_op_xor_vec:
      case INDEX_op_not_vec:
 +    case INDEX_op_shli_vec:
 +    case INDEX_op_shri_vec:
 +    case INDEX_op_sari_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
-.25.1
+.34.1

-[PULL 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec
+[PULL 09/20] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
-This is saturating add and subtract, signed and unsigned.
+Allow the target to cache items from the guest page tables.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ include/exec/cpu-defs.h | 9 +++++++++
- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
+file changed, 9 insertions(+)
 files changed, 25 insertions(+), 1 deletion(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/include/exec/cpu-defs.h
-+++ b/tcg/arm/tcg-target.h
++++ b/include/exec/cpu-defs.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
- #define TCG_TARGET_HAS_shs_vec          0
- #define TCG_TARGET_HAS_shv_vec          0
+     /* @lg_page_size contains the log2 of the page size. */
- #define TCG_TARGET_HAS_mul_vec          1
+     uint8_t lg_page_size;
--#define TCG_TARGET_HAS_sat_vec          0
++
-+#define TCG_TARGET_HAS_sat_vec          1
++    /*
- #define TCG_TARGET_HAS_minmax_vec       0
++     * Allow target-specific additions to this structure.
- #define TCG_TARGET_HAS_bitsel_vec       0
++     * This may be used to cache items from the guest cpu
- #define TCG_TARGET_HAS_cmpsel_vec       0
++     * page tables for later use by the implementation.
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
++     */
-index XXXXXXX..XXXXXXX 100644
++#ifdef TARGET_PAGE_ENTRY_EXTRA
---- a/tcg/arm/tcg-target.c.inc
++    TARGET_PAGE_ENTRY_EXTRA
-+++ b/tcg/arm/tcg-target.c.inc
++#endif
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+ } CPUTLBEntryFull;
-     INSN_VORR      = 0xf2200110,
-     INSN_VSUB      = 0xf3000800,
+ /*
      INSN_VMUL      = 0xf2000910,
 +    INSN_VQADD     = 0xf2000010,
 +    INSN_VQADD_U   = 0xf3000010,
 +    INSN_VQSUB     = 0xf2000210,
 +    INSN_VQSUB_U   = 0xf3000210,
      INSN_VABS      = 0xf3b10300,
      INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
      case INDEX_op_mul_vec:
 +    case INDEX_op_ssadd_vec:
 +    case INDEX_op_sssub_vec:
      case INDEX_op_sub_vec:
 +    case INDEX_op_usadd_vec:
 +    case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
          return C_O1_I2(w, w, w);
      case INDEX_op_or_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_ssadd_vec:
 +        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_sssub_vec:
 +        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_usadd_vec:
 +        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_ussub_vec:
 +        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_shli_vec:
      case INDEX_op_shri_vec:
      case INDEX_op_sari_vec:
 +    case INDEX_op_ssadd_vec:
 +    case INDEX_op_sssub_vec:
 +    case INDEX_op_usadd_vec:
 +    case INDEX_op_ussub_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
-.25.1
+.34.1

-New patch
+[PULL 10/20] accel/tcg: Remove PageDesc code_bitmap
+This bitmap is created and discarded immediately.
+We gain nothing by its existence.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org>
+---
+ accel/tcg/translate-all.c | 78 ++-------------------------------------
+file changed, 4 insertions(+), 74 deletions(-)
+diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/tcg/translate-all.c
++++ b/accel/tcg/translate-all.c
+@@ -XXX,XX +XXX,XX @@
+ #define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
+ #endif
+-#define SMC_BITMAP_USE_THRESHOLD 10
+-
+ typedef struct PageDesc {
+     /* list of TBs intersecting this ram page */
+     uintptr_t first_tb;
+-#ifdef CONFIG_SOFTMMU
+-    /* in order to optimize self modifying code, we count the number
+-       of lookups we do to a given page to use a bitmap */
+-    unsigned long *code_bitmap;
+-    unsigned int code_write_count;
+-#else
++#ifdef CONFIG_USER_ONLY
+     unsigned long flags;
+     void *target_data;
+ #endif
+-#ifndef CONFIG_USER_ONLY
++#ifdef CONFIG_SOFTMMU
+     QemuSpin lock;
+ #endif
+ } PageDesc;
+@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void)
+     qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode);
+ }
+-/* call with @p->lock held */
+-static inline void invalidate_page_bitmap(PageDesc *p)
+-{
+-    assert_page_locked(p);
+-#ifdef CONFIG_SOFTMMU
+-    g_free(p->code_bitmap);
+-    p->code_bitmap = NULL;
+-    p->code_write_count = 0;
+-#endif
+-}
+-
+ /* Set to NULL all the 'first_tb' fields in all PageDescs. */
+ static void page_flush_tb_1(int level, void **lp)
+ {
+@@ -XXX,XX +XXX,XX @@ static void page_flush_tb_1(int level, void **lp)
+         for (i = 0; i < V_L2_SIZE; ++i) {
+             page_lock(&pd[i]);
+             pd[i].first_tb = (uintptr_t)NULL;
+-            invalidate_page_bitmap(pd + i);
+             page_unlock(&pd[i]);
+         }
+     } else {
+@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
+     if (rm_from_page_list) {
+         p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
+         tb_page_remove(p, tb);
+-        invalidate_page_bitmap(p);
+         if (tb->page_addr[1] != -1) {
+             p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
+             tb_page_remove(p, tb);
+-            invalidate_page_bitmap(p);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
+     }
+ }
+-#ifdef CONFIG_SOFTMMU
+-/* call with @p->lock held */
+-static void build_page_bitmap(PageDesc *p)
+-{
+-    int n, tb_start, tb_end;
+-    TranslationBlock *tb;
+-
+-    assert_page_locked(p);
+-    p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE);
+-
+-    PAGE_FOR_EACH_TB(p, tb, n) {
+-        /* NOTE: this is subtle as a TB may span two physical pages */
+-        if (n == 0) {
+-            /* NOTE: tb_end may be after the end of the page, but
+-               it is not a problem */
+-            tb_start = tb->pc & ~TARGET_PAGE_MASK;
+-            tb_end = tb_start + tb->size;
+-            if (tb_end > TARGET_PAGE_SIZE) {
+-                tb_end = TARGET_PAGE_SIZE;
+-             }
+-        } else {
+-            tb_start = 0;
+-            tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
+-        }
+-        bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start);
+-    }
+-}
+-#endif
+-
+ /* add the tb in the target page and protect it if necessary
+  *
+  * Called with mmap_lock held for user-mode emulation.
+@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
+     page_already_protected = p->first_tb != (uintptr_t)NULL;
+ #endif
+     p->first_tb = (uintptr_t)tb | n;
+-    invalidate_page_bitmap(p);
+ #if defined(CONFIG_USER_ONLY)
+     /* translator_loop() must have made all TB pages non-writable */
+@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
+     /* remove TB from the page(s) if we couldn't insert it */
+     if (unlikely(existing_tb)) {
+         tb_page_remove(p, tb);
+-        invalidate_page_bitmap(p);
+         if (p2) {
+             tb_page_remove(p2, tb);
+-            invalidate_page_bitmap(p2);
+         }
+         tb = existing_tb;
+     }
+@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
+ #if !defined(CONFIG_USER_ONLY)
+     /* if no code remaining, no need to continue to use slow writes */
+     if (!p->first_tb) {
+-        invalidate_page_bitmap(p);
+         tlb_unprotect_code(start);
+     }
+ #endif
+@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_fast(struct page_collection *pages,
+     }
+     assert_page_locked(p);
+-    if (!p->code_bitmap &&
+-        ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) {
+-        build_page_bitmap(p);
+-    }
+-    if (p->code_bitmap) {
+-        unsigned int nr;
+-        unsigned long b;
+-
+-        nr = start & ~TARGET_PAGE_MASK;
+-        b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1));
+-        if (b & ((1 << len) - 1)) {
+-            goto do_invalidate;
+-        }
+-    } else {
+-    do_invalidate:
+-        tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
+-                                              retaddr);
+-    }
++    tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
++                                          retaddr);
+ }
+ #else
+ /* Called with mmap_lock held. If pc is not 0 then it indicates the
+--
+.34.1

-[PULL 06/15] tcg/arm: Implement minimal vector operations
+[PULL 11/20] accel/tcg: Use bool for page_find_alloc
-Implementing dup2, add, sub, and, or, xor as the minimal set.
+Bool is more appropriate type for the alloc parameter.
 This allows us to actually enable neon in the header file.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |   3 +
+ accel/tcg/translate-all.c | 14 +++++++-------
- tcg/arm/tcg-target-con-str.h |   2 +
+file changed, 7 insertions(+), 7 deletions(-)
  tcg/arm/tcg-target.h         |   6 +-
  tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
 files changed, 204 insertions(+), 8 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/accel/tcg/translate-all.c
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
+@@ -XXX,XX +XXX,XX @@ void page_init(void)
  C_O1_I2(r, r, ri)
  C_O1_I2(r, rZ, rZ)
  C_O1_I2(w, w, w)
 +C_O1_I2(w, w, wO)
 +C_O1_I2(w, w, wV)
 +C_O1_I2(w, w, wZ)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target-con-str.h
 +++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
  CONST('I', TCG_CT_CONST_ARM)
  CONST('K', TCG_CT_CONST_INV)
  CONST('N', TCG_CT_CONST_NEG)
 +CONST('O', TCG_CT_CONST_ORRI)
 +CONST('V', TCG_CT_CONST_ANDI)
  CONST('Z', TCG_CT_CONST_ZERO)
 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #else
  extern bool use_idiv_instructions;
  #endif
--#define use_neon_instructions  0
-+#ifdef __ARM_NEON__
-+#define use_neon_instructions  1
-+#else
-+extern bool use_neon_instructions;
-+#endif
- /* used for function call generation */
- #define TCG_TARGET_STACK_ALIGN        8
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
- #ifndef use_idiv_instructions
- bool use_idiv_instructions;
- #endif
-+#ifndef use_neon_instructions
-+bool use_neon_instructions;
-+#endif
- /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
- #ifdef CONFIG_SOFTMMU
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     /* Otherwise the assembler uses mov r0,r0 */
-     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
-+    INSN_VADD      = 0xf2000800,
-+    INSN_VAND      = 0xf2000110,
-+    INSN_VEOR      = 0xf3000110,
-     INSN_VORR      = 0xf2200110,
-+    INSN_VSUB      = 0xf3000800,
-+
-+    INSN_VMVN      = 0xf3b00580,
-+
-+    INSN_VCEQ0     = 0xf3b10100,
-+    INSN_VCGT0     = 0xf3b10000,
-+    INSN_VCGE0     = 0xf3b10080,
-+    INSN_VCLE0     = 0xf3b10180,
-+    INSN_VCLT0     = 0xf3b10200,
-+
-+    INSN_VCEQ      = 0xf3000810,
-+    INSN_VCGE      = 0xf2000310,
-+    INSN_VCGT      = 0xf2000300,
-+    INSN_VCGE_U    = 0xf3000310,
-+    INSN_VCGT_U    = 0xf3000300,
-+
-+    INSN_VTST      = 0xf2000810,
-     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
-     INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- #define TCG_CT_CONST_INV  0x200
- #define TCG_CT_CONST_NEG  0x400
- #define TCG_CT_CONST_ZERO 0x800
-+#define TCG_CT_CONST_ORRI 0x1000
-+#define TCG_CT_CONST_ANDI 0x2000
- #define ALL_GENERAL_REGS  0xffffu
- #define ALL_VECTOR_REGS   0xffff0000u
-@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
-     return i;
  }
-+/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
+-static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
-+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
++static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc)
-+{
+ {
-+    if (v32 == deposit32(v32, 16, 16, v32)) {
+     PageDesc *pd;
-+        return is_shimm16(v32, cmode, imm8);
+     void **lp;
-+    } else {
+@@ -XXX,XX +XXX,XX @@ static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
-+        return is_shimm32(v32, cmode, imm8);
-+    }
+ static inline PageDesc *page_find(tb_page_addr_t index)
-+}
+ {
-+
+-    return page_find_alloc(index, 0);
- /* Test if a constant matches the constraint.
++    return page_find_alloc(index, false);
   * TODO: define constraints for:
   *
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
          return 1;
      } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
          return 1;
 -    } else {
 -        return 0;
      }
 +
 +    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
 +    case 0:
 +        break;
 +    case TCG_CT_CONST_ANDI:
 +        val = ~val;
 +        /* fallthru */
 +    case TCG_CT_CONST_ORRI:
 +        if (val == deposit64(val, 32, 32, val)) {
 +            int cmode, imm8;
 +            return is_shimm1632(val, &cmode, &imm8);
 +        }
 +        break;
 +    default:
 +        /* Both bits should not be set for the same insn.  */
 +        g_assert_not_reached();
 +    }
 +
 +    return 0;
  }
- static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
+ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
-@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
+-                           PageDesc **ret_p2, tb_page_addr_t phys2, int alloc);
-     return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
++                           PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc);
  /* In user-mode page locks aren't used; mmap_lock is enough */
  #ifdef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static inline void page_unlock(PageDesc *pd)
  /* lock the page(s) of a TB in the correct acquisition order */
  static inline void page_lock_tb(const TranslationBlock *tb)
  {
 -    page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0);
 +    page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false);
  }
-+static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
+ static inline void page_unlock_tb(const TranslationBlock *tb)
-+                          TCGReg d, TCGReg m)
+@@ -XXX,XX +XXX,XX @@ void page_collection_unlock(struct page_collection *set)
-+{
+ #endif /* !CONFIG_USER_ONLY */
-+    tcg_out32(s, insn | (vece << 18) | (q << 6) |
-+              encode_vd(d) | encode_vm(m));
+ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
-+}
+-                           PageDesc **ret_p2, tb_page_addr_t phys2, int alloc)
-+
++                           PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc)
  static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                            TCGReg d, TCGReg n, TCGReg m)
  {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     PageDesc *p1, *p2;
-     case INDEX_op_add_vec:
+     tb_page_addr_t page1;
-     case INDEX_op_sub_vec:
+@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
-     case INDEX_op_xor_vec:
+      * Note that inserting into the hash table first isn't an option, since
--    case INDEX_op_or_vec:
+      * we can only insert TBs that are fully initialized.
--    case INDEX_op_and_vec:
+      */
--    case INDEX_op_cmp_vec:
+-    page_lock_pair(&p, phys_pc, &p2, phys_page2, 1);
-         return C_O1_I2(w, w, w);
++    page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
-+    case INDEX_op_or_vec:
+     tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
-+        return C_O1_I2(w, w, wO);
+     if (p2) {
-+    case INDEX_op_and_vec:
+         tb_page_add(p2, tb, 1, phys_page2);
-+        return C_O1_I2(w, w, wV);
+@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
-+    case INDEX_op_cmp_vec:
+     for (addr = start, len = end - start;
-+        return C_O1_I2(w, w, wZ);
+          len != 0;
+          len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
-     default:
+-        PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
-         g_assert_not_reached();
++        PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true);
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
-     }
+         /* If the write protection bit is set, then we invalidate
- }
+            the code inside.  */
 +static const ARMInsn vec_cmp_insn[16] = {
 +    [TCG_COND_EQ] = INSN_VCEQ,
 +    [TCG_COND_GT] = INSN_VCGT,
 +    [TCG_COND_GE] = INSN_VCGE,
 +    [TCG_COND_GTU] = INSN_VCGT_U,
 +    [TCG_COND_GEU] = INSN_VCGE_U,
 +};
 +
 +static const ARMInsn vec_cmp0_insn[16] = {
 +    [TCG_COND_EQ] = INSN_VCEQ0,
 +    [TCG_COND_GT] = INSN_VCGT0,
 +    [TCG_COND_GE] = INSN_VCGE0,
 +    [TCG_COND_LT] = INSN_VCLT0,
 +    [TCG_COND_LE] = INSN_VCLE0,
 +};
 +
  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                             unsigned vecl, unsigned vece,
                             const TCGArg *args, const int *const_args)
  {
 -    g_assert_not_reached();
 +    TCGType type = vecl + TCG_TYPE_V64;
 +    unsigned q = vecl;
 +    TCGArg a0, a1, a2;
 +    int cmode, imm8;
 +
 +    a0 = args[0];
 +    a1 = args[1];
 +    a2 = args[2];
 +
 +    switch (opc) {
 +    case INDEX_op_ld_vec:
 +        tcg_out_ld(s, type, a0, a1, a2);
 +        return;
 +    case INDEX_op_st_vec:
 +        tcg_out_st(s, type, a0, a1, a2);
 +        return;
 +    case INDEX_op_dupm_vec:
 +        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_dup2_vec:
 +        tcg_out_dup2_vec(s, a0, a1, a2);
 +        return;
 +    case INDEX_op_add_vec:
 +        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_sub_vec:
 +        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_xor_vec:
 +        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_and_vec:
 +        if (const_args[2]) {
 +            is_shimm1632(~a2, &cmode, &imm8);
 +            if (a0 == a1) {
 +                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
 +                return;
 +            }
 +            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
 +            a2 = a0;
 +        }
 +        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_or_vec:
 +        if (const_args[2]) {
 +            is_shimm1632(a2, &cmode, &imm8);
 +            if (a0 == a1) {
 +                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
 +                return;
 +            }
 +            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
 +            a2 = a0;
 +        }
 +        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_cmp_vec:
 +        {
 +            TCGCond cond = args[3];
 +
 +            if (cond == TCG_COND_NE) {
 +                if (const_args[2]) {
 +                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
 +                } else {
 +                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
 +                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
 +                }
 +            } else {
 +                ARMInsn insn;
 +
 +                if (const_args[2]) {
 +                    insn = vec_cmp0_insn[cond];
 +                    if (insn) {
 +                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
 +                        return;
 +                    }
 +                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
 +                    a2 = TCG_VEC_TMP;
 +                }
 +                insn = vec_cmp_insn[cond];
 +                if (insn == 0) {
 +                    TCGArg t;
 +                    t = a1, a1 = a2, a2 = t;
 +                    cond = tcg_swap_cond(cond);
 +                    insn = vec_cmp_insn[cond];
 +                    tcg_debug_assert(insn != 0);
 +                }
 +                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
 +            }
 +        }
 +        return;
 +
 +    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
 +    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
 +    default:
 +        g_assert_not_reached();
 +    }
  }
  int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
  {
 -    return 0;
 +    switch (opc) {
 +    case INDEX_op_add_vec:
 +    case INDEX_op_sub_vec:
 +    case INDEX_op_and_vec:
 +    case INDEX_op_or_vec:
 +    case INDEX_op_xor_vec:
 +        return 1;
 +    case INDEX_op_cmp_vec:
 +        return vece < MO_64;
 +    default:
 +        return 0;
 +    }
  }
  void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
 --
-.25.1
+.34.1

-[PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
+[PULL 12/20] accel/tcg: Use DisasContextBase in plugin_gen_tb_start
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Use the pc coming from db->pc_first rather than the TB.
 Use the cached host_addr rather than re-computing for the
 first page.  We still need a separate lookup for the second
 page because it won't be computed for DisasContextBase until
 the translator actually performs a read from the page.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     | 2 +-
+ include/exec/plugin-gen.h |  7 ++++---
- tcg/arm/tcg-target.c.inc | 6 ++++++
+ accel/tcg/plugin-gen.c    | 22 +++++++++++-----------
-files changed, 7 insertions(+), 1 deletion(-)
+ accel/tcg/translator.c    |  2 +-
 files changed, 16 insertions(+), 15 deletions(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/include/exec/plugin-gen.h
-+++ b/tcg/arm/tcg-target.h
++++ b/include/exec/plugin-gen.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ struct DisasContextBase;
- #define TCG_TARGET_HAS_shi_vec          1
- #define TCG_TARGET_HAS_shs_vec          0
+ #ifdef CONFIG_PLUGIN
- #define TCG_TARGET_HAS_shv_vec          0
--#define TCG_TARGET_HAS_mul_vec          0
+-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress);
-+#define TCG_TARGET_HAS_mul_vec          1
++bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db,
- #define TCG_TARGET_HAS_sat_vec          0
++                         bool supress);
- #define TCG_TARGET_HAS_minmax_vec       0
+ void plugin_gen_tb_end(CPUState *cpu);
- #define TCG_TARGET_HAS_bitsel_vec       0
+ void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *db);
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+ void plugin_gen_insn_end(void);
@@ -XXX,XX +XXX,XX @@ static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size)
  #else /* !CONFIG_PLUGIN */
 -static inline
 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress)
 +static inline bool
 +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool sup)
  {
      return false;
  }
 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/accel/tcg/plugin-gen.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/accel/tcg/plugin-gen.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(const struct qemu_plugin_tb *plugin_tb)
-     INSN_VORN      = 0xf2300110,
+     pr_ops();
-     INSN_VORR      = 0xf2200110,
+ }
-     INSN_VSUB      = 0xf3000800,
-+    INSN_VMUL      = 0xf2000910,
+-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_only)
++bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db,
-     INSN_VABS      = 0xf3b10300,
++                         bool mem_only)
-     INSN_VMVN      = 0xf3b00580,
+ {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     bool ret = false;
-         return C_O1_I1(w, w);
-     case INDEX_op_dup2_vec:
+@@ -XXX,XX +XXX,XX @@ bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_onl
-     case INDEX_op_add_vec:
-+    case INDEX_op_mul_vec:
+         ret = true;
-     case INDEX_op_sub_vec:
-     case INDEX_op_xor_vec:
+-        ptb->vaddr = tb->pc;
-         return C_O1_I2(w, w, w);
++        ptb->vaddr = db->pc_first;
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         ptb->vaddr2 = -1;
-     case INDEX_op_add_vec:
+-        get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1);
-         tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
++        ptb->haddr1 = db->host_addr[0];
-         return;
+         ptb->haddr2 = NULL;
-+    case INDEX_op_mul_vec:
+         ptb->mem_only = mem_only;
-+        tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
-+        return;
+@@ -XXX,XX +XXX,XX @@ void plugin_gen_insn_start(CPUState *cpu, const DisasContextBase *db)
-     case INDEX_op_sub_vec:
+      * Note that we skip this when haddr1 == NULL, e.g. when we're
-         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+      * fetching instructions from a region not backed by RAM.
-         return;
+      */
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+-    if (likely(ptb->haddr1 != NULL && ptb->vaddr2 == -1) &&
-         return 1;
+-        unlikely((db->pc_next & TARGET_PAGE_MASK) !=
-     case INDEX_op_abs_vec:
+-                 (db->pc_first & TARGET_PAGE_MASK))) {
-     case INDEX_op_cmp_vec:
+-        get_page_addr_code_hostp(cpu->env_ptr, db->pc_next,
-+    case INDEX_op_mul_vec:
+-                                 &ptb->haddr2);
-     case INDEX_op_neg_vec:
+-        ptb->vaddr2 = db->pc_next;
-         return vece < MO_64;
+-    }
-     default:
+-    if (likely(ptb->vaddr2 == -1)) {
 +    if (ptb->haddr1 == NULL) {
 +        pinsn->haddr = NULL;
 +    } else if (is_same_page(db, db->pc_next)) {
          pinsn->haddr = ptb->haddr1 + pinsn->vaddr - ptb->vaddr;
      } else {
 +        if (ptb->vaddr2 == -1) {
 +            ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first);
 +            get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2);
 +        }
          pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2;
      }
  }
 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translator.c
 +++ b/accel/tcg/translator.c
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
      ops->tb_start(db, cpu);
      tcg_debug_assert(db->is_jmp == DISAS_NEXT);  /* no early exit */
 -    plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY);
 +    plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY);
      while (true) {
          db->num_insns++;
 --
-.25.1
+.34.1

-[PULL 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec
+[PULL 13/20] accel/tcg: Do not align tb->page_addr[0]
-The three vector shift by vector operations are all implemented via
+Let tb->page_addr[0] contain the address of the first byte of the
-expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
+translated block, rather than the address of the page containing the
-as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
+start of the translated block.  We need to recover this value anyway
-instruction stream, and therefore also do not appear in tcg_target_op_def.
+at various points, and it is easier to discard a page offset when it
 is not needed, which happens naturally via the existing find_page shift.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.opc.h |  3 ++
+ accel/tcg/cpu-exec.c      | 16 ++++++++--------
- tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
+ accel/tcg/cputlb.c        |  3 ++-
-files changed, 63 insertions(+), 1 deletion(-)
+ accel/tcg/translate-all.c |  9 +++++----
 files changed, 15 insertions(+), 13 deletions(-)
-diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.opc.h
+--- a/accel/tcg/cpu-exec.c
-+++ b/tcg/arm/tcg-target.opc.h
++++ b/accel/tcg/cpu-exec.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct tb_desc {
-  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
+     target_ulong pc;
-  * consider these to be UNSPEC with names.
+     target_ulong cs_base;
-  */
+     CPUArchState *env;
-+
+-    tb_page_addr_t phys_page1;
-+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
++    tb_page_addr_t page_addr0;
-+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
+     uint32_t flags;
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+     uint32_t cflags;
      uint32_t trace_vcpu_dstate;
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
      const struct tb_desc *desc = d;
      if (tb->pc == desc->pc &&
 -        tb->page_addr[0] == desc->phys_page1 &&
 +        tb->page_addr[0] == desc->page_addr0 &&
          tb->cs_base == desc->cs_base &&
          tb->flags == desc->flags &&
          tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
          if (tb->page_addr[1] == -1) {
              return true;
          } else {
 -            tb_page_addr_t phys_page2;
 -            target_ulong virt_page2;
 +            tb_page_addr_t phys_page1;
 +            target_ulong virt_page1;
              /*
               * We know that the first page matched, and an otherwise valid TB
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
               * is different for the new TB.  Therefore any exception raised
               * here by the faulting lookup is not premature.
               */
 -            virt_page2 = TARGET_PAGE_ALIGN(desc->pc);
 -            phys_page2 = get_page_addr_code(desc->env, virt_page2);
 -            if (tb->page_addr[1] == phys_page2) {
 +            virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
 +            phys_page1 = get_page_addr_code(desc->env, virt_page1);
 +            if (tb->page_addr[1] == phys_page1) {
                  return true;
              }
          }
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
      if (phys_pc == -1) {
          return NULL;
      }
 -    desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
 +    desc.page_addr0 = phys_pc;
      h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
      return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
  }
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/accel/tcg/cputlb.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
-     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
+    can be detected */
-     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+ void tlb_protect_code(ram_addr_t ram_addr)
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
 +    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
      INSN_VBSL      = 0xf3100110,
      INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
 +    case INDEX_op_arm_sshl_vec:
 +    case INDEX_op_arm_ushl_vec:
          return C_O1_I2(w, w, w);
      case INDEX_op_or_vec:
      case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_arm_sshl_vec:
 +        /*
 +         * Note that Vm is the data and Vn is the shift count,
 +         * therefore the arguments appear reversed.
 +         */
 +        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
 +        return;
 +    case INDEX_op_arm_ushl_vec:
 +        /* See above. */
 +        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
 +        return;
      case INDEX_op_shli_vec:
          tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_umax_vec:
      case INDEX_op_umin_vec:
          return vece < MO_64;
 +    case INDEX_op_shlv_vec:
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        return -1;
      default:
          return 0;
      }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
  void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                         TCGArg a0, ...)
  {
--    g_assert_not_reached();
+-    cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
-+    va_list va;
++    cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK,
-+    TCGv_vec v0, v1, v2, t1;
++                                             TARGET_PAGE_SIZE,
-+    TCGArg a2;
+                                              DIRTY_MEMORY_CODE);
 +
 +    va_start(va, a0);
 +    v0 = temp_tcgv_vec(arg_temp(a0));
 +    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
 +    a2 = va_arg(va, TCGArg);
 +    va_end(va);
 +
 +    switch (opc) {
 +    case INDEX_op_shlv_vec:
 +        /*
 +         * Merely propagate shlv_vec to arm_ushl_vec.
 +         * In this way we don't set TCG_TARGET_HAS_shv_vec
 +         * because everything is done via expansion.
 +         */
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
 +        break;
 +
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        /* Right shifts are negative left shifts for NEON.  */
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        t1 = tcg_temp_new_vec(type);
 +        tcg_gen_neg_vec(vece, t1, v2);
 +        if (opc == INDEX_op_shrv_vec) {
 +            opc = INDEX_op_arm_ushl_vec;
 +        } else {
 +            opc = INDEX_op_arm_sshl_vec;
 +        }
 +        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
 +        tcg_temp_free_vec(t1);
 +        break;
 +
 +    default:
 +        g_assert_not_reached();
 +    }
  }
- static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translate-all.c
 +++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
      qemu_spin_unlock(&tb->jmp_lock);
      /* remove the TB from the hash list */
 -    phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
 +    phys_pc = tb->page_addr[0];
      h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
                       tb->trace_vcpu_dstate);
      if (!qht_remove(&tb_ctx.htable, tb, h)) {
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
       * we can only insert TBs that are fully initialized.
       */
      page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
 -    tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
 +    tb_page_add(p, tb, 0, phys_pc);
      if (p2) {
          tb_page_add(p2, tb, 1, phys_page2);
      } else {
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
          if (n == 0) {
              /* NOTE: tb_end may be after the end of the page, but
                 it is not a problem */
 -            tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
 +            tb_start = tb->page_addr[0];
              tb_end = tb_start + tb->size;
          } else {
              tb_start = tb->page_addr[1];
 -            tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
 +            tb_end = tb_start + ((tb->page_addr[0] + tb->size)
 +                                 & ~TARGET_PAGE_MASK);
          }
          if (!(tb_end <= start || tb_start >= end)) {
  #ifdef TARGET_HAS_PRECISE_SMC
 --
-.25.1
+.34.1

-[PULL 03/15] tcg/arm: Implement tcg_out_ld/st for vector types
+[PULL 14/20] accel/tcg: Inline tb_flush_jmp_cache
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+This function has two users, who use it incompatibly.
 In tlb_flush_page_by_mmuidx_async_0, when flushing a
 single page, we need to flush exactly two pages.
 In tlb_flush_range_by_mmuidx_async_0, when flushing a
 range of pages, we need to flush N+1 pages.
 This avoids double-flushing of jmp cache pages in a range.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
+ accel/tcg/cputlb.c | 25 ++++++++++++++-----------
-file changed, 64 insertions(+), 6 deletions(-)
+file changed, 14 insertions(+), 11 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/accel/tcg/cputlb.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
      INSN_NOP_v6k   = 0xe320f000,
      /* Otherwise the assembler uses mov r0,r0 */
      INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 +
 +    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
 +    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
  } ARMInsn;
  #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
      }
  }
-+/*
+-static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
-+ * Note that TCGReg references Q-registers.
+-{
-+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+-    /* Discard jump cache entries for any tb which might potentially
-+ */
+-       overlap the flushed page.  */
-+static uint32_t encode_vd(TCGReg rd)
+-    tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
-+{
+-    tb_jmp_cache_clear_page(cpu, addr);
-+    tcg_debug_assert(rd >= TCG_REG_Q0);
+-}
-+    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+-
-+}
+ /**
-+
+  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
-+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+  * @desc: The CPUTLBDesc portion of the TLB
-+                          TCGReg rd, TCGReg rn, int offset)
+@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
-+{
+     }
-+    if (offset != 0) {
+     qemu_spin_unlock(&env_tlb(env)->c.lock);
-+        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
-+            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+-    tb_flush_jmp_cache(cpu, addr);
-+                            TCG_REG_TMP, rn, offset, true);
++    /*
-+        } else {
++     * Discard jump cache entries for any tb which might potentially
-+            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
++     * overlap the flushed page, which includes the previous.
-+            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
++     */
-+                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
++    tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
-+        }
++    tb_jmp_cache_clear_page(cpu, addr);
 +        rn = TCG_REG_TMP;
 +    }
 +    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
 +}
 +
  #ifdef CONFIG_SOFTMMU
  #include "../tcg-ldst.c.inc"
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
      tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
  }
--static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ /**
--                              TCGReg arg1, intptr_t arg2)
+@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
-+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+         return;
-+                       TCGReg arg1, intptr_t arg2)
+     }
- {
--    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+-    for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) {
-+    switch (type) {
+-        tb_flush_jmp_cache(cpu, d.addr + i);
-+    case TCG_TYPE_I32:
++    /*
-+        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
++     * Discard jump cache entries for any tb which might potentially
-+        return;
++     * overlap the flushed pages, which includes the previous.
-+    case TCG_TYPE_V64:
++     */
-+        /* regs 1; size 8; align 8 */
++    d.addr -= TARGET_PAGE_SIZE;
-+        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
++    for (target_ulong i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) {
-+        return;
++        tb_jmp_cache_clear_page(cpu, d.addr);
-+    case TCG_TYPE_V128:
++        d.addr += TARGET_PAGE_SIZE;
-+        /* regs 2; size 8; align 16 */
+     }
 +        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
 +        return;
 +    default:
 +        g_assert_not_reached();
 +    }
  }
--static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
--                              TCGReg arg1, intptr_t arg2)
-+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
-+                       TCGReg arg1, intptr_t arg2)
- {
--    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
-+    switch (type) {
-+    case TCG_TYPE_I32:
-+        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
-+        return;
-+    case TCG_TYPE_V64:
-+        /* regs 1; size 8; align 8 */
-+        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
-+        return;
-+    case TCG_TYPE_V128:
-+        /* regs 2; size 8; align 16 */
-+        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
-+        return;
-+    default:
-+        g_assert_not_reached();
-+    }
- }
- static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 --
-.25.1
+.34.1

-[PULL 02/15] tcg/arm: Add host vector framework
+[PULL 15/20] include/hw/core: Create struct CPUJumpCache
-Add registers and function stubs.  The functionality
+Wrap the bare TranslationBlock pointer into a structure.
 is disabled via use_neon_instructions defined to 0.
-We must still include results for the mandatory opcodes in
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-tcg_target_op_def, as all opcodes are checked during tcg init.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |   4 ++
+ accel/tcg/tb-hash.h       |  1 +
- tcg/arm/tcg-target-con-str.h |   1 +
+ accel/tcg/tb-jmp-cache.h  | 24 ++++++++++++++++++++++++
- tcg/arm/tcg-target.h         |  48 ++++++++++++--
+ include/exec/cpu-common.h |  1 +
- tcg/arm/tcg-target.opc.h     |  12 ++++
+ include/hw/core/cpu.h     | 15 +--------------
- tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
+ include/qemu/typedefs.h   |  1 +
-files changed, 158 insertions(+), 24 deletions(-)
+ accel/stubs/tcg-stub.c    |  4 ++++
- create mode 100644 tcg/arm/tcg-target.opc.h
+ accel/tcg/cpu-exec.c      | 10 +++++++---
  accel/tcg/cputlb.c        |  9 +++++----
  accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++---
  hw/core/cpu-common.c      |  3 +--
  plugins/core.c            |  2 +-
  trace/control-target.c    |  2 +-
 files changed, 72 insertions(+), 28 deletions(-)
  create mode 100644 accel/tcg/tb-jmp-cache.h
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/accel/tcg/tb-hash.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/accel/tcg/tb-hash.h
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
  C_O0_I2(r, r)
  C_O0_I2(r, rIN)
  C_O0_I2(s, s)
 +C_O0_I2(w, r)
  C_O0_I3(s, s, s)
  C_O0_I4(r, r, rI, rI)
  C_O0_I4(s, s, s, s)
  C_O1_I1(r, l)
  C_O1_I1(r, r)
 +C_O1_I1(w, r)
 +C_O1_I1(w, wr)
  C_O1_I2(r, 0, rZ)
  C_O1_I2(r, l, l)
  C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
  C_O1_I2(r, r, rIN)
  C_O1_I2(r, r, ri)
  C_O1_I2(r, rZ, rZ)
 +C_O1_I2(w, w, w)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target-con-str.h
 +++ b/tcg/arm/tcg-target-con-str.h
 @@ -XXX,XX +XXX,XX @@
- REGS('r', ALL_GENERAL_REGS)
+ #include "exec/cpu-defs.h"
- REGS('l', ALL_QLOAD_REGS)
+ #include "exec/exec-all.h"
- REGS('s', ALL_QSTORE_REGS)
+ #include "qemu/xxhash.h"
-+REGS('w', ALL_VECTOR_REGS)
++#include "tb-jmp-cache.h"
- /*
+ #ifdef CONFIG_SOFTMMU
-  * Define constraint letters for constants:
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
      TCG_REG_R13,
      TCG_REG_R14,
      TCG_REG_PC,
 +
 +    TCG_REG_Q0,
 +    TCG_REG_Q1,
 +    TCG_REG_Q2,
 +    TCG_REG_Q3,
 +    TCG_REG_Q4,
 +    TCG_REG_Q5,
 +    TCG_REG_Q6,
 +    TCG_REG_Q7,
 +    TCG_REG_Q8,
 +    TCG_REG_Q9,
 +    TCG_REG_Q10,
 +    TCG_REG_Q11,
 +    TCG_REG_Q12,
 +    TCG_REG_Q13,
 +    TCG_REG_Q14,
 +    TCG_REG_Q15,
 +
 +    TCG_AREG0 = TCG_REG_R6,
 +    TCG_REG_CALL_STACK = TCG_REG_R13,
  } TCGReg;
 -#define TCG_TARGET_NB_REGS 16
 +#define TCG_TARGET_NB_REGS 32
  #ifdef __ARM_ARCH_EXT_IDIV__
  #define use_idiv_instructions  1
  #else
  extern bool use_idiv_instructions;
  #endif
 -
 +#define use_neon_instructions  0
  /* used for function call generation */
 -#define TCG_REG_CALL_STACK        TCG_REG_R13
  #define TCG_TARGET_STACK_ALIGN        8
  #define TCG_TARGET_CALL_ALIGN_ARGS    1
  #define TCG_TARGET_CALL_STACK_OFFSET    0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
  #define TCG_TARGET_HAS_direct_jump      0
  #define TCG_TARGET_HAS_qemu_st8_i32     0
 -enum {
 -    TCG_AREG0 = TCG_REG_R6,
 -};
 +#define TCG_TARGET_HAS_v64              use_neon_instructions
 +#define TCG_TARGET_HAS_v128             use_neon_instructions
 +#define TCG_TARGET_HAS_v256             0
 +
 +#define TCG_TARGET_HAS_andc_vec         0
 +#define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_not_vec          0
 +#define TCG_TARGET_HAS_neg_vec          0
 +#define TCG_TARGET_HAS_abs_vec          0
 +#define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rots_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
 +#define TCG_TARGET_HAS_shi_vec          0
 +#define TCG_TARGET_HAS_shs_vec          0
 +#define TCG_TARGET_HAS_shv_vec          0
 +#define TCG_TARGET_HAS_mul_vec          0
 +#define TCG_TARGET_HAS_sat_vec          0
 +#define TCG_TARGET_HAS_minmax_vec       0
 +#define TCG_TARGET_HAS_bitsel_vec       0
 +#define TCG_TARGET_HAS_cmpsel_vec       0
  #define TCG_TARGET_DEFAULT_MO (0)
  #define TCG_TARGET_HAS_MEMORY_BSWAP     1
 diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/tcg/arm/tcg-target.opc.h
++++ b/accel/tcg/tb-jmp-cache.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Copyright (c) 2019 Linaro
++ * The per-CPU TranslationBlock jump cache.
 + *
-+ * This work is licensed under the terms of the GNU GPL, version 2 or
++ *  Copyright (c) 2003 Fabrice Bellard
 + * (at your option) any later version.
 + *
-+ * See the COPYING file in the top-level directory for details.
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + *
 + * Target-specific opcodes for host vector expansion.  These will be
 + * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
 + * consider these to be UNSPEC with names.
 + */
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
++
-index XXXXXXX..XXXXXXX 100644
++#ifndef ACCEL_TCG_TB_JMP_CACHE_H
---- a/tcg/arm/tcg-target.c.inc
++#define ACCEL_TCG_TB_JMP_CACHE_H
-+++ b/tcg/arm/tcg-target.c.inc
++
-@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
++#define TB_JMP_CACHE_BITS 12
++#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
- #ifdef CONFIG_DEBUG_TCG
++
- static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
++/*
--    "%r0",
++ * Accessed in parallel; all accesses to 'tb' must be atomic.
--    "%r1",
++ */
--    "%r2",
++struct CPUJumpCache {
--    "%r3",
++    struct {
--    "%r4",
++        TranslationBlock *tb;
--    "%r5",
++    } array[TB_JMP_CACHE_SIZE];
--    "%r6",
++};
--    "%r7",
++
--    "%r8",
++#endif /* ACCEL_TCG_TB_JMP_CACHE_H */
--    "%r9",
+diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
--    "%r10",
+index XXXXXXX..XXXXXXX 100644
--    "%r11",
+--- a/include/exec/cpu-common.h
--    "%r12",
++++ b/include/exec/cpu-common.h
--    "%r13",
+@@ -XXX,XX +XXX,XX @@ void cpu_list_unlock(void);
--    "%r14",
+ unsigned int cpu_list_generation_id_get(void);
--    "%pc",
-+    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
+ void tcg_flush_softmmu_tlb(CPUState *cs);
-+    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
++void tcg_flush_jmp_cache(CPUState *cs);
-+    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
-+    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
+ void tcg_iommu_init_notifier_list(CPUState *cpu);
- };
+ void tcg_iommu_free_notifier_list(CPUState *cpu);
- #endif
+diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
+--- a/include/hw/core/cpu.h
-     TCG_REG_R3,
++++ b/include/hw/core/cpu.h
-     TCG_REG_R12,
+@@ -XXX,XX +XXX,XX @@ struct kvm_run;
-     TCG_REG_R14,
+ struct hax_vcpu_state;
-+
+ struct hvf_vcpu_state;
-+    TCG_REG_Q0,
-+    TCG_REG_Q1,
+-#define TB_JMP_CACHE_BITS 12
-+    TCG_REG_Q2,
+-#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
-+    TCG_REG_Q3,
+-
-+    /* Q4 - Q7 are call-saved, and skipped. */
+ /* work queue */
-+    TCG_REG_Q8,
-+    TCG_REG_Q9,
+ /* The union type allows passing of 64 bit target pointers on 32 bit
-+    TCG_REG_Q10,
+@@ -XXX,XX +XXX,XX @@ struct CPUState {
-+    TCG_REG_Q11,
+     CPUArchState *env_ptr;
-+    TCG_REG_Q12,
+     IcountDecr *icount_decr_ptr;
-+    TCG_REG_Q13,
-+    TCG_REG_Q14,
+-    /* Accessed in parallel; all accesses must be atomic */
-+    TCG_REG_Q15,
+-    TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
- };
++    CPUJumpCache *tb_jmp_cache;
- static const int tcg_target_call_iarg_regs[4] = {
+     struct GDBRegisterState *gdb_regs;
-@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
+     int gdb_num_regs;
- };
+@@ -XXX,XX +XXX,XX @@ extern CPUTailQ cpus;
- #define TCG_REG_TMP  TCG_REG_R12
+ extern __thread CPUState *current_cpu;
-+#define TCG_VEC_TMP  TCG_REG_Q15
+-static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
- enum arm_cond_code_e {
+-{
-     COND_EQ = 0x0,
+-    unsigned int i;
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+-
- #define TCG_CT_CONST_ZERO 0x800
+-    for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
+-        qatomic_set(&cpu->tb_jmp_cache[i], NULL);
- #define ALL_GENERAL_REGS  0xffffu
+-    }
-+#define ALL_VECTOR_REGS   0xffff0000u
+-}
+-
- /*
+ /**
-  * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
+  * qemu_tcg_mttcg_enabled:
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+  * Check whether we are running MultiThread TCG or not.
-     case INDEX_op_qemu_st_i64:
+diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
-         return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
+index XXXXXXX..XXXXXXX 100644
+--- a/include/qemu/typedefs.h
-+    case INDEX_op_st_vec:
++++ b/include/qemu/typedefs.h
-+        return C_O0_I2(w, r);
+@@ -XXX,XX +XXX,XX @@ typedef struct CoMutex CoMutex;
-+    case INDEX_op_ld_vec:
+ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
-+    case INDEX_op_dupm_vec:
+ typedef struct CPUAddressSpace CPUAddressSpace;
-+        return C_O1_I1(w, r);
+ typedef struct CPUArchState CPUArchState;
-+    case INDEX_op_dup_vec:
++typedef struct CPUJumpCache CPUJumpCache;
-+        return C_O1_I1(w, wr);
+ typedef struct CPUState CPUState;
-+    case INDEX_op_dup2_vec:
+ typedef struct CPUTLBEntryFull CPUTLBEntryFull;
-+    case INDEX_op_add_vec:
+ typedef struct DeviceListener DeviceListener;
-+    case INDEX_op_sub_vec:
+diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
-+    case INDEX_op_xor_vec:
+index XXXXXXX..XXXXXXX 100644
-+    case INDEX_op_or_vec:
+--- a/accel/stubs/tcg-stub.c
-+    case INDEX_op_and_vec:
++++ b/accel/stubs/tcg-stub.c
-+    case INDEX_op_cmp_vec:
+@@ -XXX,XX +XXX,XX @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
-+        return C_O1_I2(w, w, w);
+ {
-+
+ }
-     default:
-         g_assert_not_reached();
++void tcg_flush_jmp_cache(CPUState *cpu)
-     }
++{
-@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
++}
- {
++
-     /* Only probe for the platform and capabilities if we havn't already
+ int probe_access_flags(CPUArchState *env, target_ulong addr,
-        determined maximum values at compile time.  */
+                        MMUAccessType access_type, int mmu_idx,
--#ifndef use_idiv_instructions
+                        bool nonfault, void **phost, uintptr_t retaddr)
-+#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
-     {
+index XXXXXXX..XXXXXXX 100644
-         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+--- a/accel/tcg/cpu-exec.c
-+#ifndef use_idiv_instructions
++++ b/accel/tcg/cpu-exec.c
-         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+@@ -XXX,XX +XXX,XX @@
-+#endif
+ #include "sysemu/replay.h"
-+#ifndef use_neon_instructions
+ #include "sysemu/tcg.h"
-+        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
+ #include "exec/helper-proto.h"
-+#endif
++#include "tb-jmp-cache.h"
-     }
+ #include "tb-hash.h"
- #endif
+ #include "tb-context.h"
-+
+ #include "internal.h"
-     if (__ARM_ARCH < 7) {
+@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
-         const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
+     tcg_debug_assert(!(cflags & CF_INVALID));
-         if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
-@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
+     hash = tb_jmp_cache_hash_func(pc);
 -    tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
 +    tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
      if (likely(tb &&
                 tb->pc == pc &&
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
      if (tb == NULL) {
          return NULL;
      }
 -    qatomic_set(&cpu->tb_jmp_cache[hash], tb);
 +    qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
      return tb;
  }
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
              tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
              if (tb == NULL) {
 +                uint32_t h;
 +
                  mmap_lock();
                  tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
                  mmap_unlock();
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
                   * We add the TB in the virtual pc hash table
                   * for the fast lookup
                   */
 -                qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
 +                h = tb_jmp_cache_hash_func(pc);
 +                qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
              }
  #ifndef CONFIG_USER_ONLY
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cputlb.c
 +++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
  static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
  {
 -    unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
 +    int i, i0 = tb_jmp_cache_hash_page(page_addr);
 +    CPUJumpCache *jc = cpu->tb_jmp_cache;
      for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
 -        qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
 +        qatomic_set(&jc->array[i0 + i].tb, NULL);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
      qemu_spin_unlock(&env_tlb(env)->c.lock);
 -    cpu_tb_jmp_cache_clear(cpu);
 +    tcg_flush_jmp_cache(cpu);
      if (to_clean == ALL_MMUIDX_BITS) {
          qatomic_set(&env_tlb(env)->c.full_flush_count,
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
       * longer to clear each entry individually than it will to clear it all.
       */
      if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) {
 -        cpu_tb_jmp_cache_clear(cpu);
 +        tcg_flush_jmp_cache(cpu);
          return;
      }
 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translate-all.c
 +++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/tcg.h"
  #include "qapi/error.h"
  #include "hw/core/tcg-cpu-ops.h"
 +#include "tb-jmp-cache.h"
  #include "tb-hash.h"
  #include "tb-context.h"
  #include "internal.h"
@@ -XXX,XX +XXX,XX @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
      }
      CPU_FOREACH(cpu) {
 -        cpu_tb_jmp_cache_clear(cpu);
 +        tcg_flush_jmp_cache(cpu);
      }
      qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
      /* remove the TB from the hash list */
      h = tb_jmp_cache_hash_func(tb->pc);
      CPU_FOREACH(cpu) {
 -        if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) {
 -            qatomic_set(&cpu->tb_jmp_cache[h], NULL);
 +        CPUJumpCache *jc = cpu->tb_jmp_cache;
 +        if (qatomic_read(&jc->array[h].tb) == tb) {
 +            qatomic_set(&jc->array[h].tb, NULL);
          }
      }
--    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+@@ -XXX,XX +XXX,XX @@ int page_unprotect(target_ulong address, uintptr_t pc)
-+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
+ }
+ #endif /* CONFIG_USER_ONLY */
-     tcg_target_call_clobber_regs = 0;
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
++/*
-@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
++ * Called by generic code at e.g. cpu reset after cpu creation,
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
++ * therefore we must be prepared to allocate the jump cache.
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
++ */
++void tcg_flush_jmp_cache(CPUState *cpu)
-+    if (use_neon_instructions) {
++{
-+        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
++    CPUJumpCache *jc = cpu->tb_jmp_cache;
-+        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
++
-+
++    if (likely(jc)) {
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
++        for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
++            qatomic_set(&jc->array[i].tb, NULL);
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
++        }
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
++    } else {
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
++        /* This should happen once during realize, and thus never race. */
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
++        jc = g_new0(CPUJumpCache, 1);
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
++        jc = qatomic_xchg(&cpu->tb_jmp_cache, jc);
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
++        assert(jc == NULL);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
 +    }
-+
-     s->reserved_regs = 0;
-     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
-     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
-     tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
-+    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
- }
- static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
-     tcg_out_movi32(s, COND_AL, ret, arg);
- }
-+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
-+                            TCGReg rd, TCGReg rs)
-+{
-+    g_assert_not_reached();
 +}
 +
-+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
-+                             TCGReg rd, TCGReg base, intptr_t offset)
+ void tcg_flush_softmmu_tlb(CPUState *cs)
-+{
+ {
-+    g_assert_not_reached();
+diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
-+}
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/hw/core/cpu-common.c
-+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
++++ b/hw/core/cpu-common.c
-+                             TCGReg rd, int64_t v64)
+@@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(DeviceState *dev)
-+{
+     cpu->cflags_next_tb = -1;
-+    g_assert_not_reached();
-+}
+     if (tcg_enabled()) {
-+
+-        cpu_tb_jmp_cache_clear(cpu);
-+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+-
-+                           unsigned vecl, unsigned vece,
++        tcg_flush_jmp_cache(cpu);
-+                           const TCGArg *args, const int *const_args)
+         tcg_flush_softmmu_tlb(cpu);
-+{
+     }
-+    g_assert_not_reached();
+ }
-+}
+diff --git a/plugins/core.c b/plugins/core.c
-+
+index XXXXXXX..XXXXXXX 100644
-+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+--- a/plugins/core.c
-+{
++++ b/plugins/core.c
-+    return 0;
+@@ -XXX,XX +XXX,XX @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id)
-+}
+ static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data)
-+
+ {
-+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+     bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX);
-+                       TCGArg a0, ...)
+-    cpu_tb_jmp_cache_clear(cpu);
-+{
++    tcg_flush_jmp_cache(cpu);
-+    g_assert_not_reached();
+ }
-+}
-+
+ static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer udata)
- static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+diff --git a/trace/control-target.c b/trace/control-target.c
- {
+index XXXXXXX..XXXXXXX 100644
-     int i;
+--- a/trace/control-target.c
 +++ b/trace/control-target.c
@@ -XXX,XX +XXX,XX @@ static void trace_event_synchronize_vcpu_state_dynamic(
  {
      bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed,
                  CPU_TRACE_DSTATE_MAX_EVENTS);
 -    cpu_tb_jmp_cache_clear(vcpu);
 +    tcg_flush_jmp_cache(vcpu);
  }
  void trace_event_set_vcpu_state_dynamic(CPUState *vcpu,
 --
-.25.1
+.34.1

-[PULL 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations
+[PULL 16/20] hw/core: Add CPUClass.get_pc
-These logical and arithmetic operations are optional, but are
+Populate this new method for all targets.  Always match
-trivial to accomplish with the existing infrastructure.
+the result that would be given by cpu_get_tb_cpu_state,
 as we will want these values to correspond in the logs.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc)
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core)
- tcg/arm/tcg-target.h         | 10 +++++-----
+Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core)
- tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
+Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core)
-files changed, 44 insertions(+), 5 deletions(-)
+Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core)
 Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs)
 Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs)
 Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs)
 Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs)
 Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs)
 Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs)
 Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
 Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs)
 Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs)
 Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs)
 Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs)
 Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs)
 Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs)
 Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs)
 Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs)
 Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
 Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
 Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
 Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
 ---
  include/hw/core/cpu.h   |  3 +++
  target/alpha/cpu.c      |  9 +++++++++
  target/arm/cpu.c        | 13 +++++++++++++
  target/avr/cpu.c        |  8 ++++++++
  target/cris/cpu.c       |  8 ++++++++
  target/hexagon/cpu.c    |  8 ++++++++
  target/hppa/cpu.c       |  8 ++++++++
  target/i386/cpu.c       |  9 +++++++++
  target/loongarch/cpu.c  |  9 +++++++++
  target/m68k/cpu.c       |  8 ++++++++
  target/microblaze/cpu.c |  8 ++++++++
  target/mips/cpu.c       |  8 ++++++++
  target/nios2/cpu.c      |  9 +++++++++
  target/openrisc/cpu.c   |  8 ++++++++
  target/ppc/cpu_init.c   |  8 ++++++++
  target/riscv/cpu.c      | 13 +++++++++++++
  target/rx/cpu.c         |  8 ++++++++
  target/s390x/cpu.c      |  8 ++++++++
  target/sh4/cpu.c        |  8 ++++++++
  target/sparc/cpu.c      |  8 ++++++++
  target/tricore/cpu.c    |  9 +++++++++
  target/xtensa/cpu.c     |  8 ++++++++
 files changed, 186 insertions(+)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/include/hw/core/cpu.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/include/hw/core/cpu.h
-@@ -XXX,XX +XXX,XX @@ C_O0_I4(s, s, s, s)
+@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
- C_O1_I1(r, l)
+  *       If the target behaviour here is anything other than "set
- C_O1_I1(r, r)
+  *       the PC register to the value passed in" then the target must
- C_O1_I1(w, r)
+  *       also implement the synchronize_from_tb hook.
-+C_O1_I1(w, w)
++ * @get_pc: Callback for getting the Program Counter register.
- C_O1_I1(w, wr)
++ *       As above, with the semantics of the target architecture.
- C_O1_I2(r, 0, rZ)
+  * @gdb_read_register: Callback for letting GDB read a register.
- C_O1_I2(r, l, l)
+  * @gdb_write_register: Callback for letting GDB write a register.
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+  * @gdb_adjust_breakpoint: Callback for adjusting the address of a
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ struct CPUClass {
---- a/tcg/arm/tcg-target.h
+     void (*dump_state)(CPUState *cpu, FILE *, int flags);
-+++ b/tcg/arm/tcg-target.h
+     int64_t (*get_arch_id)(CPUState *cpu);
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+     void (*set_pc)(CPUState *cpu, vaddr value);
- #define TCG_TARGET_HAS_v128             use_neon_instructions
++    vaddr (*get_pc)(CPUState *cpu);
- #define TCG_TARGET_HAS_v256             0
+     int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
+     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
--#define TCG_TARGET_HAS_andc_vec         0
+     vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
--#define TCG_TARGET_HAS_orc_vec          0
+diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
--#define TCG_TARGET_HAS_not_vec          0
+index XXXXXXX..XXXXXXX 100644
--#define TCG_TARGET_HAS_neg_vec          0
+--- a/target/alpha/cpu.c
--#define TCG_TARGET_HAS_abs_vec          0
++++ b/target/alpha/cpu.c
-+#define TCG_TARGET_HAS_andc_vec         1
+@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
-+#define TCG_TARGET_HAS_orc_vec          1
+     cpu->env.pc = value;
-+#define TCG_TARGET_HAS_not_vec          1
+ }
-+#define TCG_TARGET_HAS_neg_vec          1
-+#define TCG_TARGET_HAS_abs_vec          1
++static vaddr alpha_cpu_get_pc(CPUState *cs)
- #define TCG_TARGET_HAS_roti_vec         0
++{
- #define TCG_TARGET_HAS_rots_vec         0
++    AlphaCPU *cpu = ALPHA_CPU(cs);
- #define TCG_TARGET_HAS_rotv_vec         0
++
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
++    return cpu->env.pc;
-index XXXXXXX..XXXXXXX 100644
++}
---- a/tcg/arm/tcg-target.c.inc
++
-+++ b/tcg/arm/tcg-target.c.inc
++
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+ static bool alpha_cpu_has_work(CPUState *cs)
+ {
-     INSN_VADD      = 0xf2000800,
+     /* Here we are checking to see if the CPU should wake up from HALT.
-     INSN_VAND      = 0xf2000110,
+@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
-+    INSN_VBIC      = 0xf2100110,
+     cc->has_work = alpha_cpu_has_work;
-     INSN_VEOR      = 0xf3000110,
+     cc->dump_state = alpha_cpu_dump_state;
-+    INSN_VORN      = 0xf2300110,
+     cc->set_pc = alpha_cpu_set_pc;
-     INSN_VORR      = 0xf2200110,
++    cc->get_pc = alpha_cpu_get_pc;
-     INSN_VSUB      = 0xf3000800,
+     cc->gdb_read_register = alpha_cpu_gdb_read_register;
+     cc->gdb_write_register = alpha_cpu_gdb_write_register;
-+    INSN_VABS      = 0xf3b10300,
+ #ifndef CONFIG_USER_ONLY
-     INSN_VMVN      = 0xf3b00580,
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-+    INSN_VNEG      = 0xf3b10380,
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
-     INSN_VCEQ0     = 0xf3b10100,
++++ b/target/arm/cpu.c
-     INSN_VCGT0     = 0xf3b10000,
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     }
-         return C_O1_I1(w, r);
+ }
-     case INDEX_op_dup_vec:
-         return C_O1_I1(w, wr);
++static vaddr arm_cpu_get_pc(CPUState *cs)
-+    case INDEX_op_abs_vec:
++{
-+    case INDEX_op_neg_vec:
++    ARMCPU *cpu = ARM_CPU(cs);
-+    case INDEX_op_not_vec:
++    CPUARMState *env = &cpu->env;
-+        return C_O1_I1(w, w);
++
-     case INDEX_op_dup2_vec:
++    if (is_a64(env)) {
-     case INDEX_op_add_vec:
++        return env->pc;
-     case INDEX_op_sub_vec:
++    } else {
-     case INDEX_op_xor_vec:
++        return env->regs[15];
-         return C_O1_I2(w, w, w);
++    }
-     case INDEX_op_or_vec:
++}
-+    case INDEX_op_andc_vec:
++
-         return C_O1_I2(w, w, wO);
+ #ifdef CONFIG_TCG
-     case INDEX_op_and_vec:
+ void arm_cpu_synchronize_from_tb(CPUState *cs,
-+    case INDEX_op_orc_vec:
+                                  const TranslationBlock *tb)
-         return C_O1_I2(w, w, wV);
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
-     case INDEX_op_cmp_vec:
+     cc->has_work = arm_cpu_has_work;
-         return C_O1_I2(w, w, wZ);
+     cc->dump_state = arm_cpu_dump_state;
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     cc->set_pc = arm_cpu_set_pc;
-     case INDEX_op_dup2_vec:
++    cc->get_pc = arm_cpu_get_pc;
-         tcg_out_dup2_vec(s, a0, a1, a2);
+     cc->gdb_read_register = arm_cpu_gdb_read_register;
-         return;
+     cc->gdb_write_register = arm_cpu_gdb_write_register;
-+    case INDEX_op_abs_vec:
+ #ifndef CONFIG_USER_ONLY
-+        tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
+diff --git a/target/avr/cpu.c b/target/avr/cpu.c
-+        return;
+index XXXXXXX..XXXXXXX 100644
-+    case INDEX_op_neg_vec:
+--- a/target/avr/cpu.c
-+        tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
++++ b/target/avr/cpu.c
-+        return;
+@@ -XXX,XX +XXX,XX @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value)
-+    case INDEX_op_not_vec:
+     cpu->env.pc_w = value / 2; /* internally PC points to words */
-+        tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
+ }
-+        return;
-     case INDEX_op_add_vec:
++static vaddr avr_cpu_get_pc(CPUState *cs)
-         tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
++{
-         return;
++    AVRCPU *cpu = AVR_CPU(cs);
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
++
-         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
++    return cpu->env.pc_w * 2;
-         return;
++}
++
-+    case INDEX_op_andc_vec:
+ static bool avr_cpu_has_work(CPUState *cs)
-+        if (!const_args[2]) {
+ {
-+            tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
+     AVRCPU *cpu = AVR_CPU(cs);
-+            return;
+@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
-+        }
+     cc->has_work = avr_cpu_has_work;
-+        a2 = ~a2;
+     cc->dump_state = avr_cpu_dump_state;
-+        /* fall through */
+     cc->set_pc = avr_cpu_set_pc;
-     case INDEX_op_and_vec:
++    cc->get_pc = avr_cpu_get_pc;
-         if (const_args[2]) {
+     dc->vmsd = &vms_avr_cpu;
-             is_shimm1632(~a2, &cmode, &imm8);
+     cc->sysemu_ops = &avr_sysemu_ops;
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     cc->disas_set_info = avr_cpu_disas_set_info;
-         tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+diff --git a/target/cris/cpu.c b/target/cris/cpu.c
-         return;
+index XXXXXXX..XXXXXXX 100644
+--- a/target/cris/cpu.c
-+    case INDEX_op_orc_vec:
++++ b/target/cris/cpu.c
-+        if (!const_args[2]) {
+@@ -XXX,XX +XXX,XX @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
-+            tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
+     cpu->env.pc = value;
-+            return;
+ }
-+        }
-+        a2 = ~a2;
++static vaddr cris_cpu_get_pc(CPUState *cs)
-+        /* fall through */
++{
-     case INDEX_op_or_vec:
++    CRISCPU *cpu = CRIS_CPU(cs);
-         if (const_args[2]) {
++
-             is_shimm1632(a2, &cmode, &imm8);
++    return cpu->env.pc;
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
++}
-     case INDEX_op_add_vec:
++
-     case INDEX_op_sub_vec:
+ static bool cris_cpu_has_work(CPUState *cs)
-     case INDEX_op_and_vec:
+ {
-+    case INDEX_op_andc_vec:
+     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-     case INDEX_op_or_vec:
+@@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
-+    case INDEX_op_orc_vec:
+     cc->has_work = cris_cpu_has_work;
-     case INDEX_op_xor_vec:
+     cc->dump_state = cris_cpu_dump_state;
-+    case INDEX_op_not_vec:
+     cc->set_pc = cris_cpu_set_pc;
-         return 1;
++    cc->get_pc = cris_cpu_get_pc;
-+    case INDEX_op_abs_vec:
+     cc->gdb_read_register = cris_cpu_gdb_read_register;
-     case INDEX_op_cmp_vec:
+     cc->gdb_write_register = cris_cpu_gdb_write_register;
-+    case INDEX_op_neg_vec:
+ #ifndef CONFIG_USER_ONLY
-         return vece < MO_64;
+diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
-     default:
+index XXXXXXX..XXXXXXX 100644
-         return 0;
+--- a/target/hexagon/cpu.c
 +++ b/target/hexagon/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
      env->gpr[HEX_REG_PC] = value;
  }
 +static vaddr hexagon_cpu_get_pc(CPUState *cs)
 +{
 +    HexagonCPU *cpu = HEXAGON_CPU(cs);
 +    CPUHexagonState *env = &cpu->env;
 +    return env->gpr[HEX_REG_PC];
 +}
 +
  static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
                                              const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
      cc->has_work = hexagon_cpu_has_work;
      cc->dump_state = hexagon_dump_state;
      cc->set_pc = hexagon_cpu_set_pc;
 +    cc->get_pc = hexagon_cpu_get_pc;
      cc->gdb_read_register = hexagon_gdb_read_register;
      cc->gdb_write_register = hexagon_gdb_write_register;
      cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/hppa/cpu.c
 +++ b/target/hppa/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.iaoq_b = value + 4;
  }
 +static vaddr hppa_cpu_get_pc(CPUState *cs)
 +{
 +    HPPACPU *cpu = HPPA_CPU(cs);
 +
 +    return cpu->env.iaoq_f;
 +}
 +
  static void hppa_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = hppa_cpu_has_work;
      cc->dump_state = hppa_cpu_dump_state;
      cc->set_pc = hppa_cpu_set_pc;
 +    cc->get_pc = hppa_cpu_get_pc;
      cc->gdb_read_register = hppa_cpu_gdb_read_register;
      cc->gdb_write_register = hppa_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/i386/cpu.c b/target/i386/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/i386/cpu.c
 +++ b/target/i386/cpu.c
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.eip = value;
  }
 +static vaddr x86_cpu_get_pc(CPUState *cs)
 +{
 +    X86CPU *cpu = X86_CPU(cs);
 +
 +    /* Match cpu_get_tb_cpu_state. */
 +    return cpu->env.eip + cpu->env.segs[R_CS].base;
 +}
 +
  int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
  {
      X86CPU *cpu = X86_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
      cc->has_work = x86_cpu_has_work;
      cc->dump_state = x86_cpu_dump_state;
      cc->set_pc = x86_cpu_set_pc;
 +    cc->get_pc = x86_cpu_get_pc;
      cc->gdb_read_register = x86_cpu_gdb_read_register;
      cc->gdb_write_register = x86_cpu_gdb_write_register;
      cc->get_arch_id = x86_cpu_get_arch_id;
 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/cpu.c
 +++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
      env->pc = value;
  }
 +static vaddr loongarch_cpu_get_pc(CPUState *cs)
 +{
 +    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 +    CPULoongArchState *env = &cpu->env;
 +
 +    return env->pc;
 +}
 +
  #ifndef CONFIG_USER_ONLY
  #include "hw/loongarch/virt.h"
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
      cc->has_work = loongarch_cpu_has_work;
      cc->dump_state = loongarch_cpu_dump_state;
      cc->set_pc = loongarch_cpu_set_pc;
 +    cc->get_pc = loongarch_cpu_get_pc;
  #ifndef CONFIG_USER_ONLY
      dc->vmsd = &vmstate_loongarch_cpu;
      cc->sysemu_ops = &loongarch_sysemu_ops;
 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/m68k/cpu.c
 +++ b/target/m68k/cpu.c
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.pc = value;
  }
 +static vaddr m68k_cpu_get_pc(CPUState *cs)
 +{
 +    M68kCPU *cpu = M68K_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static bool m68k_cpu_has_work(CPUState *cs)
  {
      return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
      cc->has_work = m68k_cpu_has_work;
      cc->dump_state = m68k_cpu_dump_state;
      cc->set_pc = m68k_cpu_set_pc;
 +    cc->get_pc = m68k_cpu_get_pc;
      cc->gdb_read_register = m68k_cpu_gdb_read_register;
      cc->gdb_write_register = m68k_cpu_gdb_write_register;
  #if defined(CONFIG_SOFTMMU)
 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/microblaze/cpu.c
 +++ b/target/microblaze/cpu.c
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.iflags = 0;
  }
 +static vaddr mb_cpu_get_pc(CPUState *cs)
 +{
 +    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static void mb_cpu_synchronize_from_tb(CPUState *cs,
                                         const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
      cc->dump_state = mb_cpu_dump_state;
      cc->set_pc = mb_cpu_set_pc;
 +    cc->get_pc = mb_cpu_get_pc;
      cc->gdb_read_register = mb_cpu_gdb_read_register;
      cc->gdb_write_register = mb_cpu_gdb_write_register;
 diff --git a/target/mips/cpu.c b/target/mips/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/mips/cpu.c
 +++ b/target/mips/cpu.c
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
      mips_env_set_pc(&cpu->env, value);
  }
 +static vaddr mips_cpu_get_pc(CPUState *cs)
 +{
 +    MIPSCPU *cpu = MIPS_CPU(cs);
 +
 +    return cpu->env.active_tc.PC;
 +}
 +
  static bool mips_cpu_has_work(CPUState *cs)
  {
      MIPSCPU *cpu = MIPS_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
      cc->has_work = mips_cpu_has_work;
      cc->dump_state = mips_cpu_dump_state;
      cc->set_pc = mips_cpu_set_pc;
 +    cc->get_pc = mips_cpu_get_pc;
      cc->gdb_read_register = mips_cpu_gdb_read_register;
      cc->gdb_write_register = mips_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/nios2/cpu.c
 +++ b/target/nios2/cpu.c
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
      env->pc = value;
  }
 +static vaddr nios2_cpu_get_pc(CPUState *cs)
 +{
 +    Nios2CPU *cpu = NIOS2_CPU(cs);
 +    CPUNios2State *env = &cpu->env;
 +
 +    return env->pc;
 +}
 +
  static bool nios2_cpu_has_work(CPUState *cs)
  {
      return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = nios2_cpu_has_work;
      cc->dump_state = nios2_cpu_dump_state;
      cc->set_pc = nios2_cpu_set_pc;
 +    cc->get_pc = nios2_cpu_get_pc;
      cc->disas_set_info = nios2_cpu_disas_set_info;
  #ifndef CONFIG_USER_ONLY
      cc->sysemu_ops = &nios2_sysemu_ops;
 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/openrisc/cpu.c
 +++ b/target/openrisc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.dflag = 0;
  }
 +static vaddr openrisc_cpu_get_pc(CPUState *cs)
 +{
 +    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
                                               const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = openrisc_cpu_has_work;
      cc->dump_state = openrisc_cpu_dump_state;
      cc->set_pc = openrisc_cpu_set_pc;
 +    cc->get_pc = openrisc_cpu_get_pc;
      cc->gdb_read_register = openrisc_cpu_gdb_read_register;
      cc->gdb_write_register = openrisc_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/ppc/cpu_init.c
 +++ b/target/ppc/cpu_init.c
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.nip = value;
  }
 +static vaddr ppc_cpu_get_pc(CPUState *cs)
 +{
 +    PowerPCCPU *cpu = POWERPC_CPU(cs);
 +
 +    return cpu->env.nip;
 +}
 +
  static bool ppc_cpu_has_work(CPUState *cs)
  {
      PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = ppc_cpu_has_work;
      cc->dump_state = ppc_cpu_dump_state;
      cc->set_pc = ppc_cpu_set_pc;
 +    cc->get_pc = ppc_cpu_get_pc;
      cc->gdb_read_register = ppc_cpu_gdb_read_register;
      cc->gdb_write_register = ppc_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
      }
  }
 +static vaddr riscv_cpu_get_pc(CPUState *cs)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    CPURISCVState *env = &cpu->env;
 +
 +    /* Match cpu_get_tb_cpu_state. */
 +    if (env->xl == MXL_RV32) {
 +        return env->pc & UINT32_MAX;
 +    }
 +    return env->pc;
 +}
 +
  static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                            const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
      cc->has_work = riscv_cpu_has_work;
      cc->dump_state = riscv_cpu_dump_state;
      cc->set_pc = riscv_cpu_set_pc;
 +    cc->get_pc = riscv_cpu_get_pc;
      cc->gdb_read_register = riscv_cpu_gdb_read_register;
      cc->gdb_write_register = riscv_cpu_gdb_write_register;
      cc->gdb_num_core_regs = 33;
 diff --git a/target/rx/cpu.c b/target/rx/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/rx/cpu.c
 +++ b/target/rx/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.pc = value;
  }
 +static vaddr rx_cpu_get_pc(CPUState *cs)
 +{
 +    RXCPU *cpu = RX_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static void rx_cpu_synchronize_from_tb(CPUState *cs,
                                         const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
      cc->has_work = rx_cpu_has_work;
      cc->dump_state = rx_cpu_dump_state;
      cc->set_pc = rx_cpu_set_pc;
 +    cc->get_pc = rx_cpu_get_pc;
  #ifndef CONFIG_USER_ONLY
      cc->sysemu_ops = &rx_sysemu_ops;
 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/cpu.c
 +++ b/target/s390x/cpu.c
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.psw.addr = value;
  }
 +static vaddr s390_cpu_get_pc(CPUState *cs)
 +{
 +    S390CPU *cpu = S390_CPU(cs);
 +
 +    return cpu->env.psw.addr;
 +}
 +
  static bool s390_cpu_has_work(CPUState *cs)
  {
      S390CPU *cpu = S390_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = s390_cpu_has_work;
      cc->dump_state = s390_cpu_dump_state;
      cc->set_pc = s390_cpu_set_pc;
 +    cc->get_pc = s390_cpu_get_pc;
      cc->gdb_read_register = s390_cpu_gdb_read_register;
      cc->gdb_write_register = s390_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/sh4/cpu.c
 +++ b/target/sh4/cpu.c
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.pc = value;
  }
 +static vaddr superh_cpu_get_pc(CPUState *cs)
 +{
 +    SuperHCPU *cpu = SUPERH_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static void superh_cpu_synchronize_from_tb(CPUState *cs,
                                             const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = superh_cpu_has_work;
      cc->dump_state = superh_cpu_dump_state;
      cc->set_pc = superh_cpu_set_pc;
 +    cc->get_pc = superh_cpu_get_pc;
      cc->gdb_read_register = superh_cpu_gdb_read_register;
      cc->gdb_write_register = superh_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/sparc/cpu.c
 +++ b/target/sparc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.npc = value + 4;
  }
 +static vaddr sparc_cpu_get_pc(CPUState *cs)
 +{
 +    SPARCCPU *cpu = SPARC_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static void sparc_cpu_synchronize_from_tb(CPUState *cs,
                                            const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
      cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
  #endif
      cc->set_pc = sparc_cpu_set_pc;
 +    cc->get_pc = sparc_cpu_get_pc;
      cc->gdb_read_register = sparc_cpu_gdb_read_register;
      cc->gdb_write_register = sparc_cpu_gdb_write_register;
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/tricore/cpu.c
 +++ b/target/tricore/cpu.c
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
      env->PC = value & ~(target_ulong)1;
  }
 +static vaddr tricore_cpu_get_pc(CPUState *cs)
 +{
 +    TriCoreCPU *cpu = TRICORE_CPU(cs);
 +    CPUTriCoreState *env = &cpu->env;
 +
 +    return env->PC;
 +}
 +
  static void tricore_cpu_synchronize_from_tb(CPUState *cs,
                                              const TranslationBlock *tb)
  {
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
      cc->dump_state = tricore_cpu_dump_state;
      cc->set_pc = tricore_cpu_set_pc;
 +    cc->get_pc = tricore_cpu_get_pc;
      cc->sysemu_ops = &tricore_sysemu_ops;
      cc->tcg_ops = &tricore_tcg_ops;
  }
 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/xtensa/cpu.c
 +++ b/target/xtensa/cpu.c
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
      cpu->env.pc = value;
  }
 +static vaddr xtensa_cpu_get_pc(CPUState *cs)
 +{
 +    XtensaCPU *cpu = XTENSA_CPU(cs);
 +
 +    return cpu->env.pc;
 +}
 +
  static bool xtensa_cpu_has_work(CPUState *cs)
  {
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
      cc->has_work = xtensa_cpu_has_work;
      cc->dump_state = xtensa_cpu_dump_state;
      cc->set_pc = xtensa_cpu_set_pc;
 +    cc->get_pc = xtensa_cpu_get_pc;
      cc->gdb_read_register = xtensa_cpu_gdb_read_register;
      cc->gdb_write_register = xtensa_cpu_gdb_write_register;
      cc->gdb_stop_before_watchpoint = true;
 --
-.25.1
+.34.1

-[PULL 01/15] tcg: Change parameters for tcg_target_const_match
+[PULL 17/20] accel/tcg: Introduce tb_pc and log_pc
-Change the return value to bool, because that's what is should
+The availability of tb->pc will shortly be conditional.
-have been from the start.  Pass the ct mask instead of the whole
+Introduce accessor functions to minimize ifdefs.
 TCGArgConstraint, as that's the only part that's relevant.
-Change the value argument to int64_t.  We will need the extra
+Pass around a known pc to places like tcg_gen_code,
-width for 32-bit hosts wanting to match vector constants.
+where the caller must already have the value.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/tcg.c                    | 5 ++---
+ accel/tcg/internal.h                    |  6 ++++
- tcg/aarch64/tcg-target.c.inc | 5 +----
+ include/exec/exec-all.h                 |  6 ++++
- tcg/arm/tcg-target.c.inc     | 5 +----
+ include/tcg/tcg.h                       |  2 +-
- tcg/i386/tcg-target.c.inc    | 4 +---
+ accel/tcg/cpu-exec.c                    | 46 ++++++++++++++-----------
- tcg/mips/tcg-target.c.inc    | 5 +----
+ accel/tcg/translate-all.c               | 37 +++++++++++---------
- tcg/ppc/tcg-target.c.inc     | 4 +---
+ target/arm/cpu.c                        |  4 +--
- tcg/riscv/tcg-target.c.inc   | 4 +---
+ target/avr/cpu.c                        |  2 +-
- tcg/s390/tcg-target.c.inc    | 5 +----
+ target/hexagon/cpu.c                    |  2 +-
- tcg/sparc/tcg-target.c.inc   | 5 +----
+ target/hppa/cpu.c                       |  4 +--
- tcg/tci/tcg-target.c.inc     | 6 ++----
+ target/i386/tcg/tcg-cpu.c               |  2 +-
-files changed, 12 insertions(+), 36 deletions(-)
+ target/loongarch/cpu.c                  |  2 +-
  target/microblaze/cpu.c                 |  2 +-
  target/mips/tcg/exception.c             |  2 +-
  target/mips/tcg/sysemu/special_helper.c |  2 +-
  target/openrisc/cpu.c                   |  2 +-
  target/riscv/cpu.c                      |  4 +--
  target/rx/cpu.c                         |  2 +-
  target/sh4/cpu.c                        |  4 +--
  target/sparc/cpu.c                      |  2 +-
  target/tricore/cpu.c                    |  2 +-
  tcg/tcg.c                               |  8 ++---
 files changed, 82 insertions(+), 61 deletions(-)
+diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/tcg/internal.h
++++ b/accel/tcg/internal.h
+@@ -XXX,XX +XXX,XX @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
+ void page_init(void);
+ void tb_htable_init(void);
++/* Return the current PC from CPU, which may be cached in TB. */
++static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
++{
++    return tb_pc(tb);
++}
++
+ #endif /* ACCEL_TCG_INTERNAL_H */
+diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/exec-all.h
++++ b/include/exec/exec-all.h
+@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
+     uintptr_t jmp_dest[2];
+ };
++/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
++static inline target_ulong tb_pc(const TranslationBlock *tb)
++{
++    return tb->pc;
++}
++
+ /* Hide the qatomic_read to make code a little easier on the eyes */
+ static inline uint32_t tb_cflags(const TranslationBlock *tb)
+ {
+diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/tcg/tcg.h
++++ b/include/tcg/tcg.h
+@@ -XXX,XX +XXX,XX @@ void tcg_register_thread(void);
+ void tcg_prologue_init(TCGContext *s);
+ void tcg_func_start(TCGContext *s);
+-int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
++int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start);
+ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/tcg/cpu-exec.c
++++ b/accel/tcg/cpu-exec.c
+@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
+     const TranslationBlock *tb = p;
+     const struct tb_desc *desc = d;
+-    if (tb->pc == desc->pc &&
++    if (tb_pc(tb) == desc->pc &&
+         tb->page_addr[0] == desc->page_addr0 &&
+         tb->cs_base == desc->cs_base &&
+         tb->flags == desc->flags &&
+@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
+     return tb;
+ }
+-static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
+-                                const TranslationBlock *tb)
++static void log_cpu_exec(target_ulong pc, CPUState *cpu,
++                         const TranslationBlock *tb)
+ {
+-    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))
+-        && qemu_log_in_addr_range(pc)) {
+-
++    if (qemu_log_in_addr_range(pc)) {
+         qemu_log_mask(CPU_LOG_EXEC,
+                       "Trace %d: %p [" TARGET_FMT_lx
+                       "/" TARGET_FMT_lx "/%08x/%08x] %s\n",
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
+         return tcg_code_gen_epilogue;
+     }
+-    log_cpu_exec(pc, cpu, tb);
++    if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
++        log_cpu_exec(pc, cpu, tb);
++    }
+     return tb->tc.ptr;
+ }
+@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
+     TranslationBlock *last_tb;
+     const void *tb_ptr = itb->tc.ptr;
+-    log_cpu_exec(itb->pc, cpu, itb);
++    if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
++        log_cpu_exec(log_pc(cpu, itb), cpu, itb);
++    }
+     qemu_thread_jit_execute();
+     ret = tcg_qemu_tb_exec(env, tb_ptr);
+@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
+          * of the start of the TB.
+          */
+         CPUClass *cc = CPU_GET_CLASS(cpu);
+-        qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
+-                               "Stopped execution of TB chain before %p ["
+-                               TARGET_FMT_lx "] %s\n",
+-                               last_tb->tc.ptr, last_tb->pc,
+-                               lookup_symbol(last_tb->pc));
++
+         if (cc->tcg_ops->synchronize_from_tb) {
+             cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
+         } else {
+             assert(cc->set_pc);
+-            cc->set_pc(cpu, last_tb->pc);
++            cc->set_pc(cpu, tb_pc(last_tb));
++        }
++        if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
++            target_ulong pc = log_pc(cpu, last_tb);
++            if (qemu_log_in_addr_range(pc)) {
++                qemu_log("Stopped execution of TB chain before %p ["
++                         TARGET_FMT_lx "] %s\n",
++                         last_tb->tc.ptr, pc, lookup_symbol(pc));
++            }
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
+     qemu_spin_unlock(&tb_next->jmp_lock);
+-    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
+-                           "Linking TBs %p [" TARGET_FMT_lx
+-                           "] index %d -> %p [" TARGET_FMT_lx "]\n",
+-                           tb->tc.ptr, tb->pc, n,
+-                           tb_next->tc.ptr, tb_next->pc);
++    qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n",
++                  tb->tc.ptr, n, tb_next->tc.ptr);
+     return;
+  out_unlock_next:
+@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
+ }
+ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
++                                    target_ulong pc,
+                                     TranslationBlock **last_tb, int *tb_exit)
+ {
+     int32_t insns_left;
+-    trace_exec_tb(tb, tb->pc);
++    trace_exec_tb(tb, pc);
+     tb = cpu_tb_exec(cpu, tb, tb_exit);
+     if (*tb_exit != TB_EXIT_REQUESTED) {
+         *last_tb = tb;
+@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
+                 tb_add_jump(last_tb, tb_exit, tb);
+             }
+-            cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
++            cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit);
+             /* Try to align the host and virtual clocks
+                if the guest is in advance */
+diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/tcg/translate-all.c
++++ b/accel/tcg/translate-all.c
+@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
+         for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+             if (i == 0) {
+-                prev = (j == 0 ? tb->pc : 0);
++                prev = (j == 0 ? tb_pc(tb) : 0);
+             } else {
+                 prev = tcg_ctx->gen_insn_data[i - 1][j];
+             }
+@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
+ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
+                                      uintptr_t searched_pc, bool reset_icount)
+ {
+-    target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc };
++    target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
+     uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
+     CPUArchState *env = cpu->env_ptr;
+     const uint8_t *p = tb->tc.ptr + tb->tc.size;
+@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
+     const TranslationBlock *a = ap;
+     const TranslationBlock *b = bp;
+-    return a->pc == b->pc &&
++    return tb_pc(a) == tb_pc(b) &&
+         a->cs_base == b->cs_base &&
+         a->flags == b->flags &&
+         (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
+@@ -XXX,XX +XXX,XX @@ static void do_tb_invalidate_check(void *p, uint32_t hash, void *userp)
+     TranslationBlock *tb = p;
+     target_ulong addr = *(target_ulong *)userp;
+-    if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) {
++    if (!(addr + TARGET_PAGE_SIZE <= tb_pc(tb) ||
++          addr >= tb_pc(tb) + tb->size)) {
+         printf("ERROR invalidate: address=" TARGET_FMT_lx
+-               " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size);
++               " PC=%08lx size=%04x\n", addr, (long)tb_pc(tb), tb->size);
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void do_tb_page_check(void *p, uint32_t hash, void *userp)
+     TranslationBlock *tb = p;
+     int flags1, flags2;
+-    flags1 = page_get_flags(tb->pc);
+-    flags2 = page_get_flags(tb->pc + tb->size - 1);
++    flags1 = page_get_flags(tb_pc(tb));
++    flags2 = page_get_flags(tb_pc(tb) + tb->size - 1);
+     if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
+         printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
+-               (long)tb->pc, tb->size, flags1, flags2);
++               (long)tb_pc(tb), tb->size, flags1, flags2);
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
+     /* remove the TB from the hash list */
+     phys_pc = tb->page_addr[0];
+-    h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
++    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
+                      tb->trace_vcpu_dstate);
+     if (!qht_remove(&tb_ctx.htable, tb, h)) {
+         return;
+@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
+     }
+     /* add in the hash table */
+-    h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,
++    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
+                      tb->trace_vcpu_dstate);
+     qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
+@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
+     tcg_ctx->cpu = NULL;
+     max_insns = tb->icount;
+-    trace_translate_block(tb, tb->pc, tb->tc.ptr);
++    trace_translate_block(tb, pc, tb->tc.ptr);
+     /* generate machine code */
+     tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;
+@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
+     ti = profile_getclock();
+ #endif
+-    gen_code_size = tcg_gen_code(tcg_ctx, tb);
++    gen_code_size = tcg_gen_code(tcg_ctx, tb, pc);
+     if (unlikely(gen_code_size < 0)) {
+  error_return:
+         switch (gen_code_size) {
+@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
+ #ifdef DEBUG_DISAS
+     if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
+-        qemu_log_in_addr_range(tb->pc)) {
++        qemu_log_in_addr_range(pc)) {
+         FILE *logfile = qemu_log_trylock();
+         if (logfile) {
+             int code_size, data_size;
+@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
+      */
+     cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n;
+-    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
+-                           "cpu_io_recompile: rewound execution of TB to "
+-                           TARGET_FMT_lx "\n", tb->pc);
++    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
++        target_ulong pc = log_pc(cpu, tb);
++        if (qemu_log_in_addr_range(pc)) {
++            qemu_log("cpu_io_recompile: rewound execution of TB to "
++                     TARGET_FMT_lx "\n", pc);
++        }
++    }
+     cpu_loop_exit_noexc(cpu);
+ }
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
+      * never possible for an AArch64 TB to chain to an AArch32 TB.
+      */
+     if (is_a64(env)) {
+-        env->pc = tb->pc;
++        env->pc = tb_pc(tb);
+     } else {
+-        env->regs[15] = tb->pc;
++        env->regs[15] = tb_pc(tb);
+     }
+ }
+ #endif /* CONFIG_TCG */
+diff --git a/target/avr/cpu.c b/target/avr/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/avr/cpu.c
++++ b/target/avr/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void avr_cpu_synchronize_from_tb(CPUState *cs,
+     AVRCPU *cpu = AVR_CPU(cs);
+     CPUAVRState *env = &cpu->env;
+-    env->pc_w = tb->pc / 2; /* internally PC points to words */
++    env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
+ }
+ static void avr_cpu_reset(DeviceState *ds)
+diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/hexagon/cpu.c
++++ b/target/hexagon/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     HexagonCPU *cpu = HEXAGON_CPU(cs);
+     CPUHexagonState *env = &cpu->env;
+-    env->gpr[HEX_REG_PC] = tb->pc;
++    env->gpr[HEX_REG_PC] = tb_pc(tb);
+ }
+ static bool hexagon_cpu_has_work(CPUState *cs)
+diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/hppa/cpu.c
++++ b/target/hppa/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
+     HPPACPU *cpu = HPPA_CPU(cs);
+ #ifdef CONFIG_USER_ONLY
+-    cpu->env.iaoq_f = tb->pc;
++    cpu->env.iaoq_f = tb_pc(tb);
+     cpu->env.iaoq_b = tb->cs_base;
+ #else
+     /* Recover the IAOQ values from the GVA + PRIV.  */
+@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
+     int32_t diff = cs_base;
+     cpu->env.iasq_f = iasq_f;
+-    cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
++    cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
+     if (diff) {
+         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
+     }
+diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/tcg/tcg-cpu.c
++++ b/target/i386/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     X86CPU *cpu = X86_CPU(cs);
+-    cpu->env.eip = tb->pc - tb->cs_base;
++    cpu->env.eip = tb_pc(tb) - tb->cs_base;
+ }
+ #ifndef CONFIG_USER_ONLY
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/cpu.c
++++ b/target/loongarch/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
+     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+     CPULoongArchState *env = &cpu->env;
+-    env->pc = tb->pc;
++    env->pc = tb_pc(tb);
+ }
+ #endif /* CONFIG_TCG */
+diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/microblaze/cpu.c
++++ b/target/microblaze/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+-    cpu->env.pc = tb->pc;
++    cpu->env.pc = tb_pc(tb);
+     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
+ }
+diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/mips/tcg/exception.c
++++ b/target/mips/tcg/exception.c
+@@ -XXX,XX +XXX,XX @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
+     MIPSCPU *cpu = MIPS_CPU(cs);
+     CPUMIPSState *env = &cpu->env;
+-    env->active_tc.PC = tb->pc;
++    env->active_tc.PC = tb_pc(tb);
+     env->hflags &= ~MIPS_HFLAG_BMASK;
+     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
+ }
+diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/mips/tcg/sysemu/special_helper.c
++++ b/target/mips/tcg/sysemu/special_helper.c
+@@ -XXX,XX +XXX,XX @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
+     CPUMIPSState *env = &cpu->env;
+     if ((env->hflags & MIPS_HFLAG_BMASK) != 0
+-        && env->active_tc.PC != tb->pc) {
++        && env->active_tc.PC != tb_pc(tb)) {
+         env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
+         env->hflags &= ~MIPS_HFLAG_BMASK;
+         return true;
+diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/openrisc/cpu.c
++++ b/target/openrisc/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+-    cpu->env.pc = tb->pc;
++    cpu->env.pc = tb_pc(tb);
+ }
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+     if (xl == MXL_RV32) {
+-        env->pc = (int32_t)tb->pc;
++        env->pc = (int32_t)tb_pc(tb);
+     } else {
+-        env->pc = tb->pc;
++        env->pc = tb_pc(tb);
+     }
+ }
+diff --git a/target/rx/cpu.c b/target/rx/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/rx/cpu.c
++++ b/target/rx/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     RXCPU *cpu = RX_CPU(cs);
+-    cpu->env.pc = tb->pc;
++    cpu->env.pc = tb_pc(tb);
+ }
+ static bool rx_cpu_has_work(CPUState *cs)
+diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sh4/cpu.c
++++ b/target/sh4/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     SuperHCPU *cpu = SUPERH_CPU(cs);
+-    cpu->env.pc = tb->pc;
++    cpu->env.pc = tb_pc(tb);
+     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
+ }
+@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
+     CPUSH4State *env = &cpu->env;
+     if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
+-        && env->pc != tb->pc) {
++        && env->pc != tb_pc(tb)) {
+         env->pc -= 2;
+         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
+         return true;
+diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sparc/cpu.c
++++ b/target/sparc/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     SPARCCPU *cpu = SPARC_CPU(cs);
+-    cpu->env.pc = tb->pc;
++    cpu->env.pc = tb_pc(tb);
+     cpu->env.npc = tb->cs_base;
+ }
+diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/tricore/cpu.c
++++ b/target/tricore/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs,
+     TriCoreCPU *cpu = TRICORE_CPU(cs);
+     CPUTriCoreState *env = &cpu->env;
+-    env->PC = tb->pc;
++    env->PC = tb_pc(tb);
+ }
+ static void tricore_cpu_reset(DeviceState *dev)
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
+@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void)
  static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
                          TCGReg base, intptr_t ofs);
  static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
 -static int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                  const TCGArgConstraint *arg_ct);
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
  #ifdef TCG_TARGET_NEED_LDST_LABELS
  static int tcg_out_ldst_finalize(TCGContext *s);
  #endif
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-         ts = arg_temp(arg);
+-int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
-         if (ts->val_type == TEMP_VAL_CONST
++int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start)
--            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+ {
-+            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
+ #ifdef CONFIG_PROFILER
-             /* constant is OK for instruction */
+     TCGProfile *prof = &s->prof;
-             const_args[i] = 1;
+@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
-             new_args[i] = ts->val;
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
+ #ifdef DEBUG_DISAS
-index XXXXXXX..XXXXXXX 100644
+     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
---- a/tcg/aarch64/tcg-target.c.inc
+-                 && qemu_log_in_addr_range(tb->pc))) {
-+++ b/tcg/aarch64/tcg-target.c.inc
++                 && qemu_log_in_addr_range(pc_start))) {
-@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+         FILE *logfile = qemu_log_trylock();
-     }
+         if (logfile) {
- }
+             fprintf(logfile, "OP:\n");
+@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
+     if (s->nb_indirects > 0) {
--                                  const TCGArgConstraint *arg_ct)
+ #ifdef DEBUG_DISAS
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
- {
+-                     && qemu_log_in_addr_range(tb->pc))) {
--    int ct = arg_ct->ct;
++                     && qemu_log_in_addr_range(pc_start))) {
--
+             FILE *logfile = qemu_log_trylock();
-     if (ct & TCG_CT_CONST) {
+             if (logfile) {
-         return 1;
+                 fprintf(logfile, "OP before indirect lowering:\n");
-     }
+@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
+ #ifdef DEBUG_DISAS
---- a/tcg/arm/tcg-target.c.inc
+     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
-+++ b/tcg/arm/tcg-target.c.inc
+-                 && qemu_log_in_addr_range(tb->pc))) {
-@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
++                 && qemu_log_in_addr_range(pc_start))) {
-  * mov operand2:     values represented with x << (2 * y), x < 0x100
+         FILE *logfile = qemu_log_trylock();
-  * add, sub, eor...: ditto
+         if (logfile) {
-  */
+             fprintf(logfile, "OP after optimization and liveness analysis:\n");
 -static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                         const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct;
 -    ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  }
  /* test if a constant matches the constraint */
 -static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                         const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      }
 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/mips/tcg-target.c.inc
 +++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
  }
  /* test if a constant matches the constraint */
 -static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                         const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct;
 -    ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.c.inc
 +++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
  }
  /* test if a constant matches the constraint */
 -static int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                  const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      }
 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/riscv/tcg-target.c.inc
 +++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
  }
  /* test if a constant matches the constraint */
 -static int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                  const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      }
 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390/tcg-target.c.inc
 +++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
  }
  /* Test if a constant matches the constraint. */
 -static int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                  const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct = arg_ct->ct;
 -
      if (ct & TCG_CT_CONST) {
          return 1;
      }
 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/sparc/tcg-target.c.inc
 +++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
  }
  /* test if a constant matches the constraint */
 -static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                         const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    int ct = arg_ct->ct;
 -
      if (ct & TCG_CT_CONST) {
          return 1;
      }
 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tci/tcg-target.c.inc
 +++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
  }
  /* Test if a constant matches the constraint. */
 -static int tcg_target_const_match(tcg_target_long val, TCGType type,
 -                                  const TCGArgConstraint *arg_ct)
 +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  {
 -    /* No need to return 0 or 1, 0 or != 0 is good enough. */
 -    return arg_ct->ct & TCG_CT_CONST;
 +    return ct & TCG_CT_CONST;
  }
  static void tcg_target_init(TCGContext *s)
 --
-.25.1
+.34.1

-[PULL 04/15] tcg/arm: Implement tcg_out_mov for vector types
+[PULL 18/20] accel/tcg: Introduce TARGET_TB_PCREL
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Prepare for targets to be able to produce TBs that can
 run in more than one virtual context.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
+ accel/tcg/internal.h      |  4 +++
-file changed, 46 insertions(+), 6 deletions(-)
+ accel/tcg/tb-jmp-cache.h  | 41 +++++++++++++++++++++++++
  include/exec/cpu-defs.h   |  3 ++
  include/exec/exec-all.h   | 32 ++++++++++++++++++--
  accel/tcg/cpu-exec.c      | 16 ++++++----
  accel/tcg/translate-all.c | 64 ++++++++++++++++++++++++++-------------
 files changed, 131 insertions(+), 29 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/accel/tcg/internal.h
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/accel/tcg/internal.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void);
-     /* Otherwise the assembler uses mov r0,r0 */
+ /* Return the current PC from CPU, which may be cached in TB. */
-     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
+ {
-+    INSN_VORR      = 0xf2200110,
++#if TARGET_TB_PCREL
-+
++    return cpu->cc->get_pc(cpu);
-     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
++#else
-     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+     return tb_pc(tb);
- } ARMInsn;
++#endif
-@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
+ }
-     return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
- }
+ #endif /* ACCEL_TCG_INTERNAL_H */
+diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
-+static uint32_t encode_vn(TCGReg rn)
+index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/tb-jmp-cache.h
 +++ b/accel/tcg/tb-jmp-cache.h
@@ -XXX,XX +XXX,XX @@
  /*
   * Accessed in parallel; all accesses to 'tb' must be atomic.
 + * For TARGET_TB_PCREL, accesses to 'pc' must be protected by
 + * a load_acquire/store_release to 'tb'.
   */
  struct CPUJumpCache {
      struct {
          TranslationBlock *tb;
 +#if TARGET_TB_PCREL
 +        target_ulong pc;
 +#endif
      } array[TB_JMP_CACHE_SIZE];
  };
 +static inline TranslationBlock *
 +tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash)
 +{
-+    tcg_debug_assert(rn >= TCG_REG_Q0);
++#if TARGET_TB_PCREL
-+    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
++    /* Use acquire to ensure current load of pc from jc. */
 +    return qatomic_load_acquire(&jc->array[hash].tb);
 +#else
 +    /* Use rcu_read to ensure current load of pc from *tb. */
 +    return qatomic_rcu_read(&jc->array[hash].tb);
 +#endif
 +}
 +
-+static uint32_t encode_vm(TCGReg rm)
++static inline target_ulong
 +tb_jmp_cache_get_pc(CPUJumpCache *jc, uint32_t hash, TranslationBlock *tb)
 +{
-+    tcg_debug_assert(rm >= TCG_REG_Q0);
++#if TARGET_TB_PCREL
-+    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
++    return jc->array[hash].pc;
 +#else
 +    return tb_pc(tb);
 +#endif
 +}
 +
-+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
++static inline void
-+                          TCGReg d, TCGReg n, TCGReg m)
++tb_jmp_cache_set(CPUJumpCache *jc, uint32_t hash,
 +                 TranslationBlock *tb, target_ulong pc)
 +{
-+    tcg_out32(s, insn | (vece << 20) | (q << 6) |
++#if TARGET_TB_PCREL
-+              encode_vd(d) | encode_vn(n) | encode_vm(m));
++    jc->array[hash].pc = pc;
 +    /* Use store_release on tb to ensure pc is written first. */
 +    qatomic_store_release(&jc->array[hash].tb, tb);
 +#else
 +    /* Use the pc value already stored in tb->pc. */
 +    qatomic_set(&jc->array[hash].tb, tb);
 +#endif
 +}
 +
- static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+ #endif /* ACCEL_TCG_TB_JMP_CACHE_H */
-                           TCGReg rd, TCGReg rn, int offset)
+diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
- {
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+--- a/include/exec/cpu-defs.h
-     return false;
++++ b/include/exec/cpu-defs.h
- }
+@@ -XXX,XX +XXX,XX @@
+ #  error TARGET_PAGE_BITS must be defined in cpu-param.h
--static inline bool tcg_out_mov(TCGContext *s, TCGType type,
+ # endif
--                               TCGReg ret, TCGReg arg)
+ #endif
-+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
++#ifndef TARGET_TB_PCREL
- {
++# define TARGET_TB_PCREL 0
--    tcg_out_mov_reg(s, COND_AL, ret, arg);
++#endif
--    return true;
-+    if (ret == arg) {
+ #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
-+        return true;
 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/exec/exec-all.h
 +++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ struct tb_tc {
  };
  struct TranslationBlock {
 -    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 -    target_ulong cs_base; /* CS base for this block */
 +#if !TARGET_TB_PCREL
 +    /*
 +     * Guest PC corresponding to this block.  This must be the true
 +     * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
 +     * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
 +     * privilege, must store those bits elsewhere.
 +     *
 +     * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
 +     * written such that the TB is associated only with the physical
 +     * page and may be run in any virtual address context.  In this case,
 +     * PC must always be taken from ENV in a target-specific manner.
 +     * Unwind information is taken as offsets from the page, to be
 +     * deposited into the "current" PC.
 +     */
 +    target_ulong pc;
 +#endif
 +
 +    /*
 +     * Target-specific data associated with the TranslationBlock, e.g.:
 +     * x86: the original user, the Code Segment virtual base,
 +     * arm: an extension of tb->flags,
 +     * s390x: instruction data for EXECUTE,
 +     * sparc: the next pc of the instruction queue (for delay slots).
 +     */
 +    target_ulong cs_base;
 +
      uint32_t flags; /* flags defining in which context the code was generated */
      uint32_t cflags;    /* compile flags */
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
  /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
  static inline target_ulong tb_pc(const TranslationBlock *tb)
  {
 +#if TARGET_TB_PCREL
 +    qemu_build_not_reached();
 +#else
      return tb->pc;
 +#endif
  }
  /* Hide the qatomic_read to make code a little easier on the eyes */
 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cpu-exec.c
 +++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
      const TranslationBlock *tb = p;
      const struct tb_desc *desc = d;
 -    if (tb_pc(tb) == desc->pc &&
 +    if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) &&
          tb->page_addr[0] == desc->page_addr0 &&
          tb->cs_base == desc->cs_base &&
          tb->flags == desc->flags &&
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
          return NULL;
      }
      desc.page_addr0 = phys_pc;
 -    h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
 +    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc),
 +                     flags, cflags, *cpu->trace_dstate);
      return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
  }
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
                                            uint32_t flags, uint32_t cflags)
  {
      TranslationBlock *tb;
 +    CPUJumpCache *jc;
      uint32_t hash;
      /* we should never be trying to look up an INVALID tb */
      tcg_debug_assert(!(cflags & CF_INVALID));
      hash = tb_jmp_cache_hash_func(pc);
 -    tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
 +    jc = cpu->tb_jmp_cache;
 +    tb = tb_jmp_cache_get_tb(jc, hash);
      if (likely(tb &&
 -               tb->pc == pc &&
 +               tb_jmp_cache_get_pc(jc, hash, tb) == pc &&
                 tb->cs_base == cs_base &&
                 tb->flags == flags &&
                 tb->trace_vcpu_dstate == *cpu->trace_dstate &&
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
      if (tb == NULL) {
          return NULL;
      }
 -    qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
 +    tb_jmp_cache_set(jc, hash, tb, pc);
      return tb;
  }
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
          if (cc->tcg_ops->synchronize_from_tb) {
              cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
          } else {
 +            assert(!TARGET_TB_PCREL);
              assert(cc->set_pc);
              cc->set_pc(cpu, tb_pc(last_tb));
          }
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
                   * for the fast lookup
                   */
                  h = tb_jmp_cache_hash_func(pc);
 -                qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
 +                tb_jmp_cache_set(cpu->tb_jmp_cache, h, tb, pc);
              }
  #ifndef CONFIG_USER_ONLY
 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translate-all.c
 +++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
          for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
              if (i == 0) {
 -                prev = (j == 0 ? tb_pc(tb) : 0);
 +                prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0);
              } else {
                  prev = tcg_ctx->gen_insn_data[i - 1][j];
              }
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
  static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
                                       uintptr_t searched_pc, bool reset_icount)
  {
 -    target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
 +    target_ulong data[TARGET_INSN_START_WORDS];
      uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
      CPUArchState *env = cpu->env_ptr;
      const uint8_t *p = tb->tc.ptr + tb->tc.size;
@@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
          return -1;
      }
 +    memset(data, 0, sizeof(data));
 +    if (!TARGET_TB_PCREL) {
 +        data[0] = tb_pc(tb);
 +    }
-+    switch (type) {
++
-+    case TCG_TYPE_I32:
+     /* Reconstruct the stored insn data while looking for the point at
-+        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+        which the end of the insn exceeds the searched_pc.  */
-+            tcg_out_mov_reg(s, COND_AL, ret, arg);
+     for (i = 0; i < num_insns; ++i) {
-+            return true;
+@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
      const TranslationBlock *a = ap;
      const TranslationBlock *b = bp;
 -    return tb_pc(a) == tb_pc(b) &&
 -        a->cs_base == b->cs_base &&
 -        a->flags == b->flags &&
 -        (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
 -        a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
 -        a->page_addr[0] == b->page_addr[0] &&
 -        a->page_addr[1] == b->page_addr[1];
 +    return ((TARGET_TB_PCREL || tb_pc(a) == tb_pc(b)) &&
 +            a->cs_base == b->cs_base &&
 +            a->flags == b->flags &&
 +            (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
 +            a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
 +            a->page_addr[0] == b->page_addr[0] &&
 +            a->page_addr[1] == b->page_addr[1]);
  }
  void tb_htable_init(void)
@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
      qemu_spin_unlock(&dest->jmp_lock);
  }
 +static void tb_jmp_cache_inval_tb(TranslationBlock *tb)
 +{
 +    CPUState *cpu;
 +
 +    if (TARGET_TB_PCREL) {
 +        /* A TB may be at any virtual address */
 +        CPU_FOREACH(cpu) {
 +            tcg_flush_jmp_cache(cpu);
 +        }
-+        return false;
++    } else {
-+
++        uint32_t h = tb_jmp_cache_hash_func(tb_pc(tb));
-+    case TCG_TYPE_V64:
++
-+    case TCG_TYPE_V128:
++        CPU_FOREACH(cpu) {
-+        /* "VMOV D,N" is an alias for "VORR D,N,N". */
++            CPUJumpCache *jc = cpu->tb_jmp_cache;
-+        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
++
-+        return true;
++            if (qatomic_read(&jc->array[h].tb) == tb) {
-+
++                qatomic_set(&jc->array[h].tb, NULL);
-+    default:
++            }
-+        g_assert_not_reached();
++        }
 +    }
- }
++}
++
--static inline void tcg_out_movi(TCGContext *s, TCGType type,
+ /*
--                                TCGReg ret, tcg_target_long arg)
+  * In user-mode, call with mmap_lock held.
-+static void tcg_out_movi(TCGContext *s, TCGType type,
+  * In !user-mode, if @rm_from_page_list is set, call with the TB's pages'
-+                         TCGReg ret, tcg_target_long arg)
+@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
- {
+  */
-+    tcg_debug_assert(type == TCG_TYPE_I32);
+ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
-+    tcg_debug_assert(ret < TCG_REG_Q0);
+ {
-     tcg_out_movi32(s, COND_AL, ret, arg);
+-    CPUState *cpu;
- }
+     PageDesc *p;
+     uint32_t h;
      tb_page_addr_t phys_pc;
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
      /* remove the TB from the hash list */
      phys_pc = tb->page_addr[0];
 -    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
 -                     tb->trace_vcpu_dstate);
 +    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
 +                     tb->flags, orig_cflags, tb->trace_vcpu_dstate);
      if (!qht_remove(&tb_ctx.htable, tb, h)) {
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
      }
      /* remove the TB from the hash list */
 -    h = tb_jmp_cache_hash_func(tb->pc);
 -    CPU_FOREACH(cpu) {
 -        CPUJumpCache *jc = cpu->tb_jmp_cache;
 -        if (qatomic_read(&jc->array[h].tb) == tb) {
 -            qatomic_set(&jc->array[h].tb, NULL);
 -        }
 -    }
 +    tb_jmp_cache_inval_tb(tb);
      /* suppress this TB from the two jump lists */
      tb_remove_from_jmp_list(tb, 0);
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
      }
      /* add in the hash table */
 -    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
 -                     tb->trace_vcpu_dstate);
 +    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
 +                     tb->flags, tb->cflags, tb->trace_vcpu_dstate);
      qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
      /* remove TB from the page(s) if we couldn't insert it */
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
      gen_code_buf = tcg_ctx->code_gen_ptr;
      tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
 +#if !TARGET_TB_PCREL
      tb->pc = pc;
 +#endif
      tb->cs_base = cs_base;
      tb->flags = flags;
      tb->cflags = cflags;
 --
-.25.1
+.34.1

-[PULL 05/15] tcg/arm: Implement tcg_out_dup*_vec
+[PULL 19/20] tcg/ppc: Optimize 26-bit jumps
-Most of dupi is copied from tcg/aarch64, which has the same
+From: Leandro Lupori <leandro.lupori@eldorado.org.br>
 encoding for AdvSimdExpandImm.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+PowerPC64 processors handle direct branches better than indirect
 ones, resulting in less stalled cycles and branch misses.
 However, PPC's tb_target_set_jmp_target() was only using direct
 branches for 16-bit jumps, while PowerPC64's unconditional branch
 instructions are able to handle displacements of up to 26 bits.
 To take advantage of this, now jumps whose displacements fit in
 between 17 and 26 bits are also converted to direct branches.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
 [rth: Expanded some commentary.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
+ tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++----------
-file changed, 275 insertions(+), 8 deletions(-)
+file changed, 88 insertions(+), 31 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/tcg/ppc/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
+     tcg_out32(s, insn);
      INSN_VORR      = 0xf2200110,
 +    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
 +    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
 +    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
      INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
 +    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
      INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 +    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
  } ARMInsn;
  #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
      [TCG_COND_GTU] = COND_HI,
  };
 +static int encode_imm(uint32_t imm);
 +
 +/* TCG private relocation type: add with pc+imm8 */
 +#define R_ARM_PC8  11
 +
 +/* TCG private relocation type: vldr with imm8 << 2 */
 +#define R_ARM_PC11 12
 +
  static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
  {
      const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
      return false;
  }
-+static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
++static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
 +{
-+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
++    if (HOST_BIG_ENDIAN) {
-+    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
++        return (uint64_t)i1 << 32 | i2;
 +
 +    if (offset >= -0xff && offset <= 0xff) {
 +        tcg_insn_unit insn = *src_rw;
 +        bool u = (offset >= 0);
 +        if (!u) {
 +            offset = -offset;
 +        }
 +        insn = deposit32(insn, 23, 1, u);
 +        insn = deposit32(insn, 0, 8, offset);
 +        *src_rw = insn;
 +        return true;
 +    }
-+    return false;
++    return (uint64_t)i2 << 32 | i1;
 +}
 +
-+static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
++static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
 +                                  tcg_insn_unit i0, tcg_insn_unit i1)
 +{
-+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
++#if TCG_TARGET_REG_BITS == 64
-+    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
++    qatomic_set((uint64_t *)rw, make_pair(i0, i1));
-+    int rot = encode_imm(offset);
++    flush_idcache_range(rx, rw, 8);
-+
++#else
-+    if (rot >= 0) {
++    qemu_build_not_reached();
-+        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
++#endif
 +        return true;
 +    }
 +    return false;
 +}
 +
- static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
++static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
-                         intptr_t value, intptr_t addend)
++                                  tcg_insn_unit i0, tcg_insn_unit i1,
- {
++                                  tcg_insn_unit i2, tcg_insn_unit i3)
      tcg_debug_assert(addend == 0);
 -
 -    if (type == R_ARM_PC24) {
 +    switch (type) {
 +    case R_ARM_PC24:
          return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
 -    } else if (type == R_ARM_PC13) {
 +    case R_ARM_PC13:
          return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
 -    } else {
 +    case R_ARM_PC11:
 +        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
 +    case R_ARM_PC8:
 +        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
 +    default:
          g_assert_not_reached();
      }
  }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
  /* ARM immediates for ALU instructions are made of an unsigned 8-bit
     right-rotated by an even amount between 0 and 30. */
 -static inline int encode_imm(uint32_t imm)
 +static int encode_imm(uint32_t imm)
  {
      int shift;
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
      return encode_imm(imm) >= 0;
  }
 +/* Return true if v16 is a valid 16-bit shifted immediate.  */
 +static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
 +{
-+    if (v16 == (v16 & 0xff)) {
++    uint64_t p[2];
-+        *cmode = 0x8;
++
-+        *imm8 = v16 & 0xff;
++    p[!HOST_BIG_ENDIAN] = make_pair(i0, i1);
-+        return true;
++    p[HOST_BIG_ENDIAN] = make_pair(i2, i3);
-+    } else if (v16 == (v16 & 0xff00)) {
++
-+        *cmode = 0xa;
++    /*
-+        *imm8 = v16 >> 8;
++     * There's no convenient way to get the compiler to allocate a pair
-+        return true;
++     * of registers at an even index, so copy into r6/r7 and clobber.
-+    }
++     */
-+    return false;
++    asm("mr  %%r6, %1\n\t"
 +        "mr  %%r7, %2\n\t"
 +        "stq %%r6, %0"
 +        : "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
 +    flush_idcache_range(rx, rw, 16);
 +}
 +
-+/* Return true if v32 is a valid 32-bit shifted immediate.  */
+ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
-+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+                               uintptr_t jmp_rw, uintptr_t addr)
-+{
+ {
-+    if (v32 == (v32 & 0xff)) {
+-    if (TCG_TARGET_REG_BITS == 64) {
-+        *cmode = 0x0;
+-        tcg_insn_unit i1, i2;
-+        *imm8 = v32 & 0xff;
+-        intptr_t tb_diff = addr - tc_ptr;
-+        return true;
+-        intptr_t br_diff = addr - (jmp_rx + 4);
-+    } else if (v32 == (v32 & 0xff00)) {
+-        uint64_t pair;
-+        *cmode = 0x2;
++    tcg_insn_unit i0, i1, i2, i3;
-+        *imm8 = (v32 >> 8) & 0xff;
++    intptr_t tb_diff = addr - tc_ptr;
-+        return true;
++    intptr_t br_diff = addr - (jmp_rx + 4);
-+    } else if (v32 == (v32 & 0xff0000)) {
++    intptr_t lo, hi;
-+        *cmode = 0x4;
-+        *imm8 = (v32 >> 16) & 0xff;
+-        /* This does not exercise the range of the branch, but we do
-+        return true;
+-           still need to be able to load the new value of TCG_REG_TB.
-+    } else if (v32 == (v32 & 0xff000000)) {
+-           But this does still happen quite often.  */
-+        *cmode = 0x6;
+-        if (tb_diff == (int16_t)tb_diff) {
-+        *imm8 = v32 >> 24;
+-            i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
-+        return true;
+-            i2 = B | (br_diff & 0x3fffffc);
 -        } else {
 -            intptr_t lo = (int16_t)tb_diff;
 -            intptr_t hi = (int32_t)(tb_diff - lo);
 -            assert(tb_diff == hi + lo);
 -            i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
 -            i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
 -        }
 -#if HOST_BIG_ENDIAN
 -        pair = (uint64_t)i1 << 32 | i2;
 -#else
 -        pair = (uint64_t)i2 << 32 | i1;
 -#endif
 -
 -        /* As per the enclosing if, this is ppc64.  Avoid the _Static_assert
 -           within qatomic_set that would fail to build a ppc32 host.  */
 -        qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
 -        flush_idcache_range(jmp_rx, jmp_rw, 8);
 -    } else {
 +    if (TCG_TARGET_REG_BITS == 32) {
          intptr_t diff = addr - jmp_rx;
          tcg_debug_assert(in_range_b(diff));
          qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
          flush_idcache_range(jmp_rx, jmp_rw, 4);
 +        return;
      }
 +
 +    /*
 +     * For 16-bit displacements, we can use a single add + branch.
 +     * This happens quite often.
 +     */
 +    if (tb_diff == (int16_t)tb_diff) {
 +        i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
 +        i1 = B | (br_diff & 0x3fffffc);
 +        ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
 +        return;
 +    }
-+    return false;
-+}
 +
-+/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
++    lo = (int16_t)tb_diff;
-+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
++    hi = (int32_t)(tb_diff - lo);
-+{
++    assert(tb_diff == hi + lo);
-+    if ((v32 & 0xffff00ff) == 0xff) {
++    i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
-+        *cmode = 0xc;
++    i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
 +        *imm8 = (v32 >> 8) & 0xff;
 +        return true;
 +    } else if ((v32 & 0xff00ffff) == 0xffff) {
 +        *cmode = 0xd;
 +        *imm8 = (v32 >> 16) & 0xff;
 +        return true;
 +    }
 +    return false;
 +}
 +
-+/*
++    /*
-+ * Return non-zero if v32 can be formed by MOVI+ORR.
++     * Without stq from 2.07, we can only update two insns,
-+ * Place the parameters for MOVI in (cmode, imm8).
++     * and those must be the ones that load the target address.
-+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
++     */
-+ */
++    if (!have_isa_2_07) {
-+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
++        ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
 +{
 +    int i;
 +
 +    for (i = 6; i > 0; i -= 2) {
 +        /* Mask out one byte we can add with ORR.  */
 +        uint32_t tmp = v32 & ~(0xffu << (i * 4));
 +        if (is_shimm32(tmp, cmode, imm8) ||
 +            is_soimm32(tmp, cmode, imm8)) {
 +            break;
 +        }
 +    }
 +    return i;
 +}
 +
  /* Test if a constant matches the constraint.
   * TODO: define constraints for:
   *
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                encode_vd(d) | encode_vn(n) | encode_vm(m));
  }
 +static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
 +                          int q, int op, int cmode, uint8_t imm8)
 +{
 +    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
 +              | (cmode << 8) | extract32(imm8, 0, 4)
 +              | (extract32(imm8, 4, 3) << 16)
 +              | (extract32(imm8, 7, 1) << 24));
 +}
 +
  static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                            TCGReg rd, TCGReg rn, int offset)
  {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
      tcg_out_movi32(s, COND_AL, ret, arg);
  }
 +/* Type is always V128, with I64 elements.  */
 +static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
 +{
 +    /* Move high element into place first. */
 +    /* VMOV Dd+1, Ds */
 +    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
 +    /* Move low element into place; tcg_out_mov will check for nop. */
 +    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
 +}
 +
  static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, TCGReg rs)
  {
 -    g_assert_not_reached();
 +    int q = type - TCG_TYPE_V64;
 +
 +    if (vece == MO_64) {
 +        if (type == TCG_TYPE_V128) {
 +            tcg_out_dup2_vec(s, rd, rs, rs);
 +        } else {
 +            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
 +        }
 +    } else if (rs < TCG_REG_Q0) {
 +        int b = (vece == MO_8);
 +        int e = (vece == MO_16);
 +        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
 +                  encode_vn(rd) | (rs << 12));
 +    } else {
 +        int imm4 = 1 << vece;
 +        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
 +                  encode_vd(rd) | encode_vm(rs));
 +    }
 +    return true;
  }
  static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                               TCGReg rd, TCGReg base, intptr_t offset)
  {
 -    g_assert_not_reached();
 +    if (vece == MO_64) {
 +        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
 +        if (type == TCG_TYPE_V128) {
 +            tcg_out_dup2_vec(s, rd, rd, rd);
 +        }
 +    } else {
 +        int q = type - TCG_TYPE_V64;
 +        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
 +                      rd, base, offset);
 +    }
 +    return true;
  }
  static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                               TCGReg rd, int64_t v64)
  {
 -    g_assert_not_reached();
 +    int q = type - TCG_TYPE_V64;
 +    int cmode, imm8, i;
 +
 +    /* Test all bytes equal first.  */
 +    if (vece == MO_8) {
 +        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
 +        return;
 +    }
 +
 +    /*
-+     * Test all bytes 0x00 or 0xff second.  This can match cases that
++     * For 26-bit displacements, we can use a direct branch.
-+     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
++     * Otherwise we still need the indirect branch, which we
 +     * must restore after a potential direct branch write.
 +     */
-+    for (i = imm8 = 0; i < 8; i++) {
++    br_diff -= 4;
-+        uint8_t byte = v64 >> (i * 8);
++    if (in_range_b(br_diff)) {
-+        if (byte == 0xff) {
++        i2 = B | (br_diff & 0x3fffffc);
-+            imm8 |= 1 << i;
++        i3 = NOP;
-+        } else if (byte != 0) {
++    } else {
-+            goto fail_bytes;
++        i2 = MTSPR | RS(TCG_REG_TB) | CTR;
-+        }
++        i3 = BCCTR | BO_ALWAYS;
 +    }
-+    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
++    ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
 +    return;
 + fail_bytes:
 +
 +    /*
 +     * Tests for various replications.  For each element width, if we
 +     * cannot find an expansion there's no point checking a larger
 +     * width because we already know by replication it cannot match.
 +     */
 +    if (vece == MO_16) {
 +        uint16_t v16 = v64;
 +
 +        if (is_shimm16(v16, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            return;
 +        }
 +        if (is_shimm16(~v16, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            return;
 +        }
 +
 +        /*
 +         * Otherwise, all remaining constants can be loaded in two insns:
 +         * rd = v16 & 0xff, rd |= v16 & 0xff00.
 +         */
 +        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
 +        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
 +        return;
 +    }
 +
 +    if (vece == MO_32) {
 +        uint32_t v32 = v64;
 +
 +        if (is_shimm32(v32, &cmode, &imm8) ||
 +            is_soimm32(v32, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            return;
 +        }
 +        if (is_shimm32(~v32, &cmode, &imm8) ||
 +            is_soimm32(~v32, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            return;
 +        }
 +
 +        /*
 +         * Restrict the set of constants to those we can load with
 +         * two instructions.  Others we load from the pool.
 +         */
 +        i = is_shimm32_pair(v32, &cmode, &imm8);
 +        if (i) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
 +            return;
 +        }
 +        i = is_shimm32_pair(~v32, &cmode, &imm8);
 +        if (i) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
 +            return;
 +        }
 +    }
 +
 +    /*
 +     * As a last resort, load from the constant pool.
 +     */
 +    if (!q || vece == MO_64) {
 +        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
 +        /* VLDR Dd, [pc + offset] */
 +        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
 +        if (q) {
 +            tcg_out_dup2_vec(s, rd, rd, rd);
 +        }
 +    } else {
 +        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
 +        /* add tmp, pc, offset */
 +        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
 +        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
 +    }
  }
- static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ static void tcg_out_call_int(TCGContext *s, int lk,
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
          if (s->tb_jmp_insn_offset) {
              /* Direct jump. */
              if (TCG_TARGET_REG_BITS == 64) {
 -                /* Ensure the next insns are 8-byte aligned. */
 -                if ((uintptr_t)s->code_ptr & 7) {
 +                /* Ensure the next insns are 8 or 16-byte aligned. */
 +                while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) {
                      tcg_out32(s, NOP);
                  }
                  s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
 --
-.25.1
+.34.1

-New patch
+[PULL 20/20] target/sh4: Fix TB_FLAG_UNALIGN
+The value previously chosen overlaps GUSA_MASK.
+Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
+that they are included in TB_FLAGs.  Add aliases for the
+FPSCR and SR bits that are included in TB_FLAGS, so that
+we don't accidentally reassign those bits.
+Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
+Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/sh4/cpu.h        | 56 +++++++++++++------------
+ linux-user/sh4/signal.c |  6 +--
+ target/sh4/cpu.c        |  6 +--
+ target/sh4/helper.c     |  6 +--
+ target/sh4/translate.c  | 90 ++++++++++++++++++++++-------------------
+files changed, 88 insertions(+), 76 deletions(-)
+diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sh4/cpu.h
++++ b/target/sh4/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ #define FPSCR_RM_NEAREST       (0 << 0)
+ #define FPSCR_RM_ZERO          (1 << 0)
+-#define DELAY_SLOT_MASK        0x7
+-#define DELAY_SLOT             (1 << 0)
+-#define DELAY_SLOT_CONDITIONAL (1 << 1)
+-#define DELAY_SLOT_RTE         (1 << 2)
++#define TB_FLAG_DELAY_SLOT       (1 << 0)
++#define TB_FLAG_DELAY_SLOT_COND  (1 << 1)
++#define TB_FLAG_DELAY_SLOT_RTE   (1 << 2)
++#define TB_FLAG_PENDING_MOVCA    (1 << 3)
++#define TB_FLAG_GUSA_SHIFT       4                      /* [11:4] */
++#define TB_FLAG_GUSA_EXCLUSIVE   (1 << 12)
++#define TB_FLAG_UNALIGN          (1 << 13)
++#define TB_FLAG_SR_FD            (1 << SR_FD)           /* 15 */
++#define TB_FLAG_FPSCR_PR         FPSCR_PR               /* 19 */
++#define TB_FLAG_FPSCR_SZ         FPSCR_SZ               /* 20 */
++#define TB_FLAG_FPSCR_FR         FPSCR_FR               /* 21 */
++#define TB_FLAG_SR_RB            (1 << SR_RB)           /* 29 */
++#define TB_FLAG_SR_MD            (1 << SR_MD)           /* 30 */
+-#define TB_FLAG_PENDING_MOVCA  (1 << 3)
+-#define TB_FLAG_UNALIGN        (1 << 4)
+-
+-#define GUSA_SHIFT             4
+-#ifdef CONFIG_USER_ONLY
+-#define GUSA_EXCLUSIVE         (1 << 12)
+-#define GUSA_MASK              ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
+-#else
+-/* Provide dummy versions of the above to allow tests against tbflags
+-   to be elided while avoiding ifdefs.  */
+-#define GUSA_EXCLUSIVE         0
+-#define GUSA_MASK              0
+-#endif
+-
+-#define TB_FLAG_ENVFLAGS_MASK  (DELAY_SLOT_MASK | GUSA_MASK)
++#define TB_FLAG_DELAY_SLOT_MASK  (TB_FLAG_DELAY_SLOT |       \
++                                  TB_FLAG_DELAY_SLOT_COND |  \
++                                  TB_FLAG_DELAY_SLOT_RTE)
++#define TB_FLAG_GUSA_MASK        ((0xff << TB_FLAG_GUSA_SHIFT) | \
++                                  TB_FLAG_GUSA_EXCLUSIVE)
++#define TB_FLAG_FPSCR_MASK       (TB_FLAG_FPSCR_PR | \
++                                  TB_FLAG_FPSCR_SZ | \
++                                  TB_FLAG_FPSCR_FR)
++#define TB_FLAG_SR_MASK          (TB_FLAG_SR_FD | \
++                                  TB_FLAG_SR_RB | \
++                                  TB_FLAG_SR_MD)
++#define TB_FLAG_ENVFLAGS_MASK    (TB_FLAG_DELAY_SLOT_MASK | \
++                                  TB_FLAG_GUSA_MASK)
+ typedef struct tlb_t {
+     uint32_t vpn;        /* virtual page number */
+@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
+ {
+     /* The instruction in a RTE delay slot is fetched in privileged
+        mode, but executed in user mode.  */
+-    if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
++    if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
+         return 0;
+     } else {
+         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
+@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
+ {
+     *pc = env->pc;
+     /* For a gUSA region, notice the end of the region.  */
+-    *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
+-    *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
+-            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
+-            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
+-            | (env->sr & (1u << SR_FD))                        /* Bit 15 */
++    *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
++    *flags = env->flags
++            | (env->fpscr & TB_FLAG_FPSCR_MASK)
++            | (env->sr & TB_FLAG_SR_MASK)
+             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+ #ifdef CONFIG_USER_ONLY
+     *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/sh4/signal.c
++++ b/linux-user/sh4/signal.c
+@@ -XXX,XX +XXX,XX @@ static void restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc)
+     __get_user(regs->fpul, &sc->sc_fpul);
+     regs->tra = -1;         /* disable syscall checks */
+-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
++    regs->flags = 0;
+ }
+ void setup_frame(int sig, struct target_sigaction *ka,
+@@ -XXX,XX +XXX,XX @@ void setup_frame(int sig, struct target_sigaction *ka,
+     regs->gregs[5] = 0;
+     regs->gregs[6] = frame_addr += offsetof(typeof(*frame), sc);
+     regs->pc = (unsigned long) ka->_sa_handler;
+-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
++    regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
+     unlock_user_struct(frame, frame_addr, 1);
+     return;
+@@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
+     regs->gregs[5] = frame_addr + offsetof(typeof(*frame), info);
+     regs->gregs[6] = frame_addr + offsetof(typeof(*frame), uc);
+     regs->pc = (unsigned long) ka->_sa_handler;
+-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
++    regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
+     unlock_user_struct(frame, frame_addr, 1);
+     return;
+diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sh4/cpu.c
++++ b/target/sh4/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
+     SuperHCPU *cpu = SUPERH_CPU(cs);
+     cpu->env.pc = tb_pc(tb);
+-    cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
++    cpu->env.flags = tb->flags;
+ }
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
+     SuperHCPU *cpu = SUPERH_CPU(cs);
+     CPUSH4State *env = &cpu->env;
+-    if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
++    if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
+         && env->pc != tb_pc(tb)) {
+         env->pc -= 2;
+-        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
++        env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
+         return true;
+     }
+     return false;
+diff --git a/target/sh4/helper.c b/target/sh4/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sh4/helper.c
++++ b/target/sh4/helper.c
+@@ -XXX,XX +XXX,XX @@ void superh_cpu_do_interrupt(CPUState *cs)
+     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
+     env->lock_addr = -1;
+-    if (env->flags & DELAY_SLOT_MASK) {
++    if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
+         /* Branch instruction should be executed again before delay slot. */
+     env->spc -= 2;
+     /* Clear flags for exception/interrupt routine. */
+-        env->flags &= ~DELAY_SLOT_MASK;
++        env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
+     }
+     if (do_exp) {
+@@ -XXX,XX +XXX,XX @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+         CPUSH4State *env = &cpu->env;
+         /* Delay slots are indivisible, ignore interrupts */
+-        if (env->flags & DELAY_SLOT_MASK) {
++        if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
+             return false;
+         } else {
+             superh_cpu_do_interrupt(cs);
+diff --git a/target/sh4/translate.c b/target/sh4/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/sh4/translate.c
++++ b/target/sh4/translate.c
+@@ -XXX,XX +XXX,XX @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+             i, env->gregs[i], i + 1, env->gregs[i + 1],
+             i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
+     }
+-    if (env->flags & DELAY_SLOT) {
++    if (env->flags & TB_FLAG_DELAY_SLOT) {
+         qemu_printf("in delay slot (delayed_pc=0x%08x)\n",
+             env->delayed_pc);
+-    } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
++    } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) {
+         qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n",
+             env->delayed_pc);
+-    } else if (env->flags & DELAY_SLOT_RTE) {
++    } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) {
+         qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n",
+                      env->delayed_pc);
+     }
+@@ -XXX,XX +XXX,XX @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
+ static inline bool use_exit_tb(DisasContext *ctx)
+ {
+-    return (ctx->tbflags & GUSA_EXCLUSIVE) != 0;
++    return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0;
+ }
+ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
+@@ -XXX,XX +XXX,XX @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
+     TCGLabel *l1 = gen_new_label();
+     TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE;
+-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
++    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
+         /* When in an exclusive region, we must continue to the end.
+            Therefore, exit the region on a taken branch, but otherwise
+            fall through to the next instruction.  */
+         tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);
+-        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
++        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
+         /* Note that this won't actually use a goto_tb opcode because we
+            disallow it in use_goto_tb, but it handles exit + singlestep.  */
+         gen_goto_tb(ctx, 0, dest);
+@@ -XXX,XX +XXX,XX @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
+     tcg_gen_mov_i32(ds, cpu_delayed_cond);
+     tcg_gen_discard_i32(cpu_delayed_cond);
+-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
++    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
+         /* When in an exclusive region, we must continue to the end.
+            Therefore, exit the region on a taken branch, but otherwise
+            fall through to the next instruction.  */
+         tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1);
+         /* Leave the gUSA region.  */
+-        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
++        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
+         gen_jump(ctx);
+         gen_set_label(l1);
+@@ -XXX,XX +XXX,XX @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+ #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
+ #define CHECK_NOT_DELAY_SLOT \
+-    if (ctx->envflags & DELAY_SLOT_MASK) {  \
+-        goto do_illegal_slot;               \
++    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {  \
++        goto do_illegal_slot;                       \
+     }
+ #define CHECK_PRIVILEGED \
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     case 0x000b:        /* rts */
+     CHECK_NOT_DELAY_SLOT
+     tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     ctx->delayed_pc = (uint32_t) - 1;
+     return;
+     case 0x0028:        /* clrmac */
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     CHECK_NOT_DELAY_SLOT
+         gen_write_sr(cpu_ssr);
+     tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
+-        ctx->envflags |= DELAY_SLOT_RTE;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT_RTE;
+     ctx->delayed_pc = (uint32_t) - 1;
+         ctx->base.is_jmp = DISAS_STOP;
+     return;
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     return;
+     case 0xe000:        /* mov #imm,Rn */
+ #ifdef CONFIG_USER_ONLY
+-        /* Detect the start of a gUSA region.  If so, update envflags
+-           and end the TB.  This will allow us to see the end of the
+-           region (stored in R0) in the next TB.  */
++        /*
++         * Detect the start of a gUSA region (mov #-n, r15).
++         * If so, update envflags and end the TB.  This will allow us
++         * to see the end of the region (stored in R0) in the next TB.
++         */
+         if (B11_8 == 15 && B7_0s < 0 &&
+             (tb_cflags(ctx->base.tb) & CF_PARALLEL)) {
+-            ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
++            ctx->envflags =
++                deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s);
+             ctx->base.is_jmp = DISAS_STOP;
+         }
+ #endif
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     case 0xa000:        /* bra disp */
+     CHECK_NOT_DELAY_SLOT
+         ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     return;
+     case 0xb000:        /* bsr disp */
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
+         ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1);
+         ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
+-        ctx->envflags |= DELAY_SLOT_CONDITIONAL;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
+     return;
+     case 0x8900:        /* bt label */
+     CHECK_NOT_DELAY_SLOT
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t);
+         ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
+-        ctx->envflags |= DELAY_SLOT_CONDITIONAL;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
+     return;
+     case 0x8800:        /* cmp/eq #imm,R0 */
+         tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s);
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     case 0x0023:        /* braf Rn */
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4);
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     ctx->delayed_pc = (uint32_t) - 1;
+     return;
+     case 0x0003:        /* bsrf Rn */
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
+     tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     ctx->delayed_pc = (uint32_t) - 1;
+     return;
+     case 0x4015:        /* cmp/pl Rn */
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     case 0x402b:        /* jmp @Rn */
+     CHECK_NOT_DELAY_SLOT
+     tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     ctx->delayed_pc = (uint32_t) - 1;
+     return;
+     case 0x400b:        /* jsr @Rn */
+     CHECK_NOT_DELAY_SLOT
+         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
+     tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
+-        ctx->envflags |= DELAY_SLOT;
++        ctx->envflags |= TB_FLAG_DELAY_SLOT;
+     ctx->delayed_pc = (uint32_t) - 1;
+     return;
+     case 0x400e:        /* ldc Rm,SR */
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+     fflush(stderr);
+ #endif
+  do_illegal:
+-    if (ctx->envflags & DELAY_SLOT_MASK) {
++    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
+  do_illegal_slot:
+         gen_save_cpu_state(ctx, true);
+         gen_helper_raise_slot_illegal_instruction(cpu_env);
+@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
+  do_fpu_disabled:
+     gen_save_cpu_state(ctx, true);
+-    if (ctx->envflags & DELAY_SLOT_MASK) {
++    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
+         gen_helper_raise_slot_fpu_disable(cpu_env);
+     } else {
+         gen_helper_raise_fpu_disable(cpu_env);
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(DisasContext * ctx)
+     _decode_opc(ctx);
+-    if (old_flags & DELAY_SLOT_MASK) {
++    if (old_flags & TB_FLAG_DELAY_SLOT_MASK) {
+         /* go out of the delay slot */
+-        ctx->envflags &= ~DELAY_SLOT_MASK;
++        ctx->envflags &= ~TB_FLAG_DELAY_SLOT_MASK;
+         /* When in an exclusive region, we must continue to the end
+            for conditional branches.  */
+-        if (ctx->tbflags & GUSA_EXCLUSIVE
+-            && old_flags & DELAY_SLOT_CONDITIONAL) {
++        if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE
++            && old_flags & TB_FLAG_DELAY_SLOT_COND) {
+             gen_delayed_conditional_jump(ctx);
+             return;
+         }
+         /* Otherwise this is probably an invalid gUSA region.
+            Drop the GUSA bits so the next TB doesn't see them.  */
+-        ctx->envflags &= ~GUSA_MASK;
++        ctx->envflags &= ~TB_FLAG_GUSA_MASK;
+         tcg_gen_movi_i32(cpu_flags, ctx->envflags);
+-        if (old_flags & DELAY_SLOT_CONDITIONAL) {
++        if (old_flags & TB_FLAG_DELAY_SLOT_COND) {
+         gen_delayed_conditional_jump(ctx);
+         } else {
+             gen_jump(ctx);
+@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
+     }
+     /* The entire region has been translated.  */
+-    ctx->envflags &= ~GUSA_MASK;
++    ctx->envflags &= ~TB_FLAG_GUSA_MASK;
+     ctx->base.pc_next = pc_end;
+     ctx->base.num_insns += max_insns - 1;
+     return;
+@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
+     /* Restart with the EXCLUSIVE bit set, within a TB run via
+        cpu_exec_step_atomic holding the exclusive lock.  */
+-    ctx->envflags |= GUSA_EXCLUSIVE;
++    ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE;
+     gen_save_cpu_state(ctx, false);
+     gen_helper_exclusive(cpu_env);
+     ctx->base.is_jmp = DISAS_NORETURN;
+@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+                   (tbflags & (1 << SR_RB))) * 0x10;
+     ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0;
+-    if (tbflags & GUSA_MASK) {
++#ifdef CONFIG_USER_ONLY
++    if (tbflags & TB_FLAG_GUSA_MASK) {
++        /* In gUSA exclusive region. */
+         uint32_t pc = ctx->base.pc_next;
+         uint32_t pc_end = ctx->base.tb->cs_base;
+-        int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);
++        int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8);
+         int max_insns = (pc_end - pc) / 2;
+         if (pc != pc_end + backup || max_insns < 2) {
+             /* This is a malformed gUSA region.  Don't do anything special,
+                since the interpreter is likely to get confused.  */
+-            ctx->envflags &= ~GUSA_MASK;
+-        } else if (tbflags & GUSA_EXCLUSIVE) {
++            ctx->envflags &= ~TB_FLAG_GUSA_MASK;
++        } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
+             /* Regardless of single-stepping or the end of the page,
+                we must complete execution of the gUSA region while
+                holding the exclusive lock.  */
+@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+             return;
+         }
+     }
++#endif
+     /* Since the ISA is fixed-width, we can bound by the number
+        of instructions remaining on the page.  */
+@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ #ifdef CONFIG_USER_ONLY
+-    if (unlikely(ctx->envflags & GUSA_MASK)
+-        && !(ctx->envflags & GUSA_EXCLUSIVE)) {
++    if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK)
++        && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) {
+         /* We're in an gUSA region, and we have not already fallen
+            back on using an exclusive region.  Attempt to parse the
+            region into a single supported atomic operation.  Failure
+@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+ {
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
++    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
+         /* Ending the region of exclusivity.  Clear the bits.  */
+-        ctx->envflags &= ~GUSA_MASK;
++        ctx->envflags &= ~TB_FLAG_GUSA_MASK;
+     }
+     switch (ctx->base.is_jmp) {
+--
+.34.1

The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604

for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:

tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)

----------------------------------------------------------------
Host vector support for arm neon.

----------------------------------------------------------------
Richard Henderson (15):
      tcg: Change parameters for tcg_target_const_match
      tcg/arm: Add host vector framework
      tcg/arm: Implement tcg_out_ld/st for vector types
      tcg/arm: Implement tcg_out_mov for vector types
      tcg/arm: Implement tcg_out_dup*_vec
      tcg/arm: Implement minimal vector operations
      tcg/arm: Implement andc, orc, abs, neg, not vector operations
      tcg/arm: Implement TCG_TARGET_HAS_shi_vec
      tcg/arm: Implement TCG_TARGET_HAS_mul_vec
      tcg/arm: Implement TCG_TARGET_HAS_sat_vec
      tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
      tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
      tcg/arm: Implement TCG_TARGET_HAS_shv_vec
      tcg/arm: Implement TCG_TARGET_HAS_roti_vec
      tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Change the return value to bool, because that's what is should
have been from the start.  Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.

Change the value argument to int64_t.  We will need the extra
width for 32-bit hosts wanting to match vector constants.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c                    | 5 ++---
 tcg/aarch64/tcg-target.c.inc | 5 +----
 tcg/arm/tcg-target.c.inc     | 5 +----
 tcg/i386/tcg-target.c.inc    | 4 +---
 tcg/mips/tcg-target.c.inc    | 5 +----
 tcg/ppc/tcg-target.c.inc     | 4 +---
 tcg/riscv/tcg-target.c.inc   | 4 +---
 tcg/s390/tcg-target.c.inc    | 5 +----
 tcg/sparc/tcg-target.c.inc   | 5 +----
 tcg/tci/tcg-target.c.inc     | 6 ++----
 10 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
                         TCGReg base, intptr_t ofs);
 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct);
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
 #ifdef TCG_TARGET_NEED_LDST_LABELS
 static int tcg_out_ldst_finalize(TCGContext *s);
 #endif
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         ts = arg_temp(arg);
 
         if (ts->val_type == TEMP_VAL_CONST
-            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
             /* constant is OK for instruction */
             const_args[i] = 1;
             new_args[i] = ts->val;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
     }
 }
 
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
  * mov operand2:     values represented with x << (2 * y), x < 0x100
  * add, sub, eor...: ditto
  */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    /* No need to return 0 or 1, 0 or != 0 is good enough. */
-    return arg_ct->ct & TCG_CT_CONST;
+    return ct & TCG_CT_CONST;
 }
 
 static void tcg_target_init(TCGContext *s)
-- 
2.25.1

Add registers and function stubs.  The functionality
is disabled via use_neon_instructions defined to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   4 ++
 tcg/arm/tcg-target-con-str.h |   1 +
 tcg/arm/tcg-target.h         |  48 ++++++++++++--
 tcg/arm/tcg-target.opc.h     |  12 ++++
 tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
 5 files changed, 158 insertions(+), 24 deletions(-)
 create mode 100644 tcg/arm/tcg-target.opc.h

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
 C_O0_I2(r, r)
 C_O0_I2(r, rIN)
 C_O0_I2(s, s)
+C_O0_I2(w, r)
 C_O0_I3(s, s, s)
 C_O0_I4(r, r, rI, rI)
 C_O0_I4(s, s, s, s)
 C_O1_I1(r, l)
 C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, wr)
 C_O1_I2(r, 0, rZ)
 C_O1_I2(r, l, l)
 C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
 C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, w, w)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
 REGS('r', ALL_GENERAL_REGS)
 REGS('l', ALL_QLOAD_REGS)
 REGS('s', ALL_QSTORE_REGS)
+REGS('w', ALL_VECTOR_REGS)
 
 /*
  * Define constraint letters for constants:
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     TCG_REG_R13,
     TCG_REG_R14,
     TCG_REG_PC,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    TCG_REG_Q4,
+    TCG_REG_Q5,
+    TCG_REG_Q6,
+    TCG_REG_Q7,
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
+
+    TCG_AREG0 = TCG_REG_R6,
+    TCG_REG_CALL_STACK = TCG_REG_R13,
 } TCGReg;
 
-#define TCG_TARGET_NB_REGS 16
+#define TCG_TARGET_NB_REGS 32
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define use_idiv_instructions  1
 #else
 extern bool use_idiv_instructions;
 #endif
-
+#define use_neon_instructions  0
 
 /* used for function call generation */
-#define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
 #define TCG_TARGET_CALL_ALIGN_ARGS	1
 #define TCG_TARGET_CALL_STACK_OFFSET	0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
 #define TCG_TARGET_HAS_direct_jump      0
 #define TCG_TARGET_HAS_qemu_st8_i32     0
 
-enum {
-    TCG_AREG0 = TCG_REG_R6,
-};
+#define TCG_TARGET_HAS_v64              use_neon_instructions
+#define TCG_TARGET_HAS_v128             use_neon_instructions
+#define TCG_TARGET_HAS_v256             0
+
+#define TCG_TARGET_HAS_andc_vec         0
+#define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_not_vec          0
+#define TCG_TARGET_HAS_neg_vec          0
+#define TCG_TARGET_HAS_abs_vec          0
+#define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
+#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shs_vec          0
+#define TCG_TARGET_HAS_shv_vec          0
+#define TCG_TARGET_HAS_mul_vec          0
+#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_bitsel_vec       0
+#define TCG_TARGET_HAS_cmpsel_vec       0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_HAS_MEMORY_BSWAP     1
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion.  These will be
+ * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-    "%r0",
-    "%r1",
-    "%r2",
-    "%r3",
-    "%r4",
-    "%r5",
-    "%r6",
-    "%r7",
-    "%r8",
-    "%r9",
-    "%r10",
-    "%r11",
-    "%r12",
-    "%r13",
-    "%r14",
-    "%pc",
+    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
+    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
+    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
+    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R3,
     TCG_REG_R12,
     TCG_REG_R14,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    /* Q4 - Q7 are call-saved, and skipped. */
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
 };
 
 static const int tcg_target_call_iarg_regs[4] = {
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
 };
 
 #define TCG_REG_TMP  TCG_REG_R12
+#define TCG_VEC_TMP  TCG_REG_Q15
 
 enum arm_cond_code_e {
     COND_EQ = 0x0,
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_ZERO 0x800
 
 #define ALL_GENERAL_REGS  0xffffu
+#define ALL_VECTOR_REGS   0xffff0000u
 
 /*
  * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_qemu_st_i64:
         return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 
+    case INDEX_op_st_vec:
+        return C_O0_I2(w, r);
+    case INDEX_op_ld_vec:
+    case INDEX_op_dupm_vec:
+        return C_O1_I1(w, r);
+    case INDEX_op_dup_vec:
+        return C_O1_I1(w, wr);
+    case INDEX_op_dup2_vec:
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_xor_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, w);
+
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
 {
     /* Only probe for the platform and capabilities if we havn't already
        determined maximum values at compile time.  */
-#ifndef use_idiv_instructions
+#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
     {
         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+#ifndef use_idiv_instructions
         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+#endif
+#ifndef use_neon_instructions
+        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
+#endif
     }
 #endif
+
     if (__ARM_ARCH < 7) {
         const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
         if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
         }
     }
 
-    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
 
     tcg_target_call_clobber_regs = 0;
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
 
+    if (use_neon_instructions) {
+        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
+        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
+    }
+
     s->reserved_regs = 0;
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
+    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+                            TCGReg rd, TCGReg rs)
+{
+    g_assert_not_reached();
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, TCGReg base, intptr_t offset)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, int64_t v64)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+                           unsigned vecl, unsigned vece,
+                           const TCGArg *args, const int *const_args)
+{
+    g_assert_not_reached();
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+    return 0;
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+                       TCGArg a0, ...)
+{
+    g_assert_not_reached();
+}
+
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 {
     int i;
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 64 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_NOP_v6k   = 0xe320f000,
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+
+    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
     }
 }
 
+/*
+ * Note that TCGReg references Q-registers.
+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ */
+static uint32_t encode_vd(TCGReg rd)
+{
+    tcg_debug_assert(rd >= TCG_REG_Q0);
+    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+}
+
+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+                          TCGReg rd, TCGReg rn, int offset)
+{
+    if (offset != 0) {
+        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
+            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+                            TCG_REG_TMP, rn, offset, true);
+        } else {
+            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
+        }
+        rn = TCG_REG_TMP;
+    }
+    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
+}
+
 #ifdef CONFIG_SOFTMMU
 #include "../tcg-ldst.c.inc"
 
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VORR      = 0xf2200110,
+
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
     return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
 }
 
+static uint32_t encode_vn(TCGReg rn)
+{
+    tcg_debug_assert(rn >= TCG_REG_Q0);
+    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+    tcg_debug_assert(rm >= TCG_REG_Q0);
+    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg n, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 20) | (q << 6) |
+              encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
     return false;
 }
 
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
-                               TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 {
-    tcg_out_mov_reg(s, COND_AL, ret, arg);
-    return true;
+    if (ret == arg) {
+        return true;
+    }
+    switch (type) {
+    case TCG_TYPE_I32:
+        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+            tcg_out_mov_reg(s, COND_AL, ret, arg);
+            return true;
+        }
+        return false;
+
+    case TCG_TYPE_V64:
+    case TCG_TYPE_V128:
+        /* "VMOV D,N" is an alias for "VORR D,N,N". */
+        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
+        return true;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
-                                TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+                         TCGReg ret, tcg_target_long arg)
 {
+    tcg_debug_assert(type == TCG_TYPE_I32);
+    tcg_debug_assert(ret < TCG_REG_Q0);
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
-- 
2.25.1

Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 275 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
 
     INSN_VORR      = 0xf2200110,
 
+    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
+    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
     [TCG_COND_GTU] = COND_HI,
 };
 
+static int encode_imm(uint32_t imm);
+
+/* TCG private relocation type: add with pc+imm8 */
+#define R_ARM_PC8  11
+
+/* TCG private relocation type: vldr with imm8 << 2 */
+#define R_ARM_PC11 12
+
 static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 {
     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
     return false;
 }
 
+static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
+
+    if (offset >= -0xff && offset <= 0xff) {
+        tcg_insn_unit insn = *src_rw;
+        bool u = (offset >= 0);
+        if (!u) {
+            offset = -offset;
+        }
+        insn = deposit32(insn, 23, 1, u);
+        insn = deposit32(insn, 0, 8, offset);
+        *src_rw = insn;
+        return true;
+    }
+    return false;
+}
+
+static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
+    int rot = encode_imm(offset);
+
+    if (rot >= 0) {
+        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
+        return true;
+    }
+    return false;
+}
+
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                         intptr_t value, intptr_t addend)
 {
     tcg_debug_assert(addend == 0);
-
-    if (type == R_ARM_PC24) {
+    switch (type) {
+    case R_ARM_PC24:
         return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
-    } else if (type == R_ARM_PC13) {
+    case R_ARM_PC13:
         return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
-    } else {
+    case R_ARM_PC11:
+        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
+    case R_ARM_PC8:
+        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
+    default:
         g_assert_not_reached();
     }
 }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
 
 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
    right-rotated by an even amount between 0 and 30. */
-static inline int encode_imm(uint32_t imm)
+static int encode_imm(uint32_t imm)
 {
     int shift;
 
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
     return encode_imm(imm) >= 0;
 }
 
+/* Return true if v16 is a valid 16-bit shifted immediate.  */
+static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
+{
+    if (v16 == (v16 & 0xff)) {
+        *cmode = 0x8;
+        *imm8 = v16 & 0xff;
+        return true;
+    } else if (v16 == (v16 & 0xff00)) {
+        *cmode = 0xa;
+        *imm8 = v16 >> 8;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifted immediate.  */
+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == (v32 & 0xff)) {
+        *cmode = 0x0;
+        *imm8 = v32 & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff00)) {
+        *cmode = 0x2;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff0000)) {
+        *cmode = 0x4;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff000000)) {
+        *cmode = 0x6;
+        *imm8 = v32 >> 24;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if ((v32 & 0xffff00ff) == 0xff) {
+        *cmode = 0xc;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if ((v32 & 0xff00ffff) == 0xffff) {
+        *cmode = 0xd;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    }
+    return false;
+}
+
+/*
+ * Return non-zero if v32 can be formed by MOVI+ORR.
+ * Place the parameters for MOVI in (cmode, imm8).
+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
+ */
+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
+{
+    int i;
+
+    for (i = 6; i > 0; i -= 2) {
+        /* Mask out one byte we can add with ORR.  */
+        uint32_t tmp = v32 & ~(0xffu << (i * 4));
+        if (is_shimm32(tmp, cmode, imm8) ||
+            is_soimm32(tmp, cmode, imm8)) {
+            break;
+        }
+    }
+    return i;
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
               encode_vd(d) | encode_vn(n) | encode_vm(m));
 }
 
+static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+                          int q, int op, int cmode, uint8_t imm8)
+{
+    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
+              | (cmode << 8) | extract32(imm8, 0, 4)
+              | (extract32(imm8, 4, 3) << 16)
+              | (extract32(imm8, 7, 1) << 24));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+/* Type is always V128, with I64 elements.  */
+static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
+{
+    /* Move high element into place first. */
+    /* VMOV Dd+1, Ds */
+    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
+    /* Move low element into place; tcg_out_mov will check for nop. */
+    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
+}
+
 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                             TCGReg rd, TCGReg rs)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+
+    if (vece == MO_64) {
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rs, rs);
+        } else {
+            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
+        }
+    } else if (rs < TCG_REG_Q0) {
+        int b = (vece == MO_8);
+        int e = (vece == MO_16);
+        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
+                  encode_vn(rd) | (rs << 12));
+    } else {
+        int imm4 = 1 << vece;
+        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
+                  encode_vd(rd) | encode_vm(rs));
+    }
+    return true;
 }
 
 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, TCGReg base, intptr_t offset)
 {
-    g_assert_not_reached();
+    if (vece == MO_64) {
+        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        int q = type - TCG_TYPE_V64;
+        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
+                      rd, base, offset);
+    }
+    return true;
 }
 
 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, int64_t v64)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+    int cmode, imm8, i;
+
+    /* Test all bytes equal first.  */
+    if (vece == MO_8) {
+        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
+        return;
+    }
+
+    /*
+     * Test all bytes 0x00 or 0xff second.  This can match cases that
+     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
+     */
+    for (i = imm8 = 0; i < 8; i++) {
+        uint8_t byte = v64 >> (i * 8);
+        if (byte == 0xff) {
+            imm8 |= 1 << i;
+        } else if (byte != 0) {
+            goto fail_bytes;
+        }
+    }
+    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
+    return;
+ fail_bytes:
+
+    /*
+     * Tests for various replications.  For each element width, if we
+     * cannot find an expansion there's no point checking a larger
+     * width because we already know by replication it cannot match.
+     */
+    if (vece == MO_16) {
+        uint16_t v16 = v64;
+
+        if (is_shimm16(v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm16(~v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Otherwise, all remaining constants can be loaded in two insns:
+         * rd = v16 & 0xff, rd |= v16 & 0xff00.
+         */
+        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
+        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
+        return;
+    }
+
+    if (vece == MO_32) {
+        uint32_t v32 = v64;
+
+        if (is_shimm32(v32, &cmode, &imm8) ||
+            is_soimm32(v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm32(~v32, &cmode, &imm8) ||
+            is_soimm32(~v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Restrict the set of constants to those we can load with
+         * two instructions.  Others we load from the pool.
+         */
+        i = is_shimm32_pair(v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
+            return;
+        }
+        i = is_shimm32_pair(~v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
+            return;
+        }
+    }
+
+    /*
+     * As a last resort, load from the constant pool.
+     */
+    if (!q || vece == MO_64) {
+        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
+        /* VLDR Dd, [pc + offset] */
+        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
+        if (q) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
+        /* add tmp, pc, offset */
+        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
+        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
+    }
 }
 
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-- 
2.25.1

Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   3 +
 tcg/arm/tcg-target-con-str.h |   2 +
 tcg/arm/tcg-target.h         |   6 +-
 tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
 4 files changed, 204 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
 C_O1_I2(w, w, w)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wV)
+C_O1_I2(w, w, wZ)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
 CONST('I', TCG_CT_CONST_ARM)
 CONST('K', TCG_CT_CONST_INV)
 CONST('N', TCG_CT_CONST_NEG)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('V', TCG_CT_CONST_ANDI)
 CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #else
 extern bool use_idiv_instructions;
 #endif
-#define use_neon_instructions  0
+#ifdef __ARM_NEON__
+#define use_neon_instructions  1
+#else
+extern bool use_neon_instructions;
+#endif
 
 /* used for function call generation */
 #define TCG_TARGET_STACK_ALIGN		8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
 #endif
+#ifndef use_neon_instructions
+bool use_neon_instructions;
+#endif
 
 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
 #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VADD      = 0xf2000800,
+    INSN_VAND      = 0xf2000110,
+    INSN_VEOR      = 0xf3000110,
     INSN_VORR      = 0xf2200110,
+    INSN_VSUB      = 0xf3000800,
+
+    INSN_VMVN      = 0xf3b00580,
+
+    INSN_VCEQ0     = 0xf3b10100,
+    INSN_VCGT0     = 0xf3b10000,
+    INSN_VCGE0     = 0xf3b10080,
+    INSN_VCLE0     = 0xf3b10180,
+    INSN_VCLT0     = 0xf3b10200,
+
+    INSN_VCEQ      = 0xf3000810,
+    INSN_VCGE      = 0xf2000310,
+    INSN_VCGT      = 0xf2000300,
+    INSN_VCGE_U    = 0xf3000310,
+    INSN_VCGT_U    = 0xf3000300,
+
+    INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
     INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_INV  0x200
 #define TCG_CT_CONST_NEG  0x400
 #define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_ORRI 0x1000
+#define TCG_CT_CONST_ANDI 0x2000
 
 #define ALL_GENERAL_REGS  0xffffu
 #define ALL_VECTOR_REGS   0xffff0000u
@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
     return i;
 }
 
+/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == deposit32(v32, 16, 16, v32)) {
+        return is_shimm16(v32, cmode, imm8);
+    } else {
+        return is_shimm32(v32, cmode, imm8);
+    }
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
         return 1;
-    } else {
-        return 0;
     }
+
+    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
+    case 0:
+        break;
+    case TCG_CT_CONST_ANDI:
+        val = ~val;
+        /* fallthru */
+    case TCG_CT_CONST_ORRI:
+        if (val == deposit64(val, 32, 32, val)) {
+            int cmode, imm8;
+            return is_shimm1632(val, &cmode, &imm8);
+        }
+        break;
+    default:
+        /* Both bits should not be set for the same insn.  */
+        g_assert_not_reached();
+    }
+
+    return 0;
 }
 
 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
     return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
 }
 
+static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 18) | (q << 6) |
+              encode_vd(d) | encode_vm(m));
+}
+
 static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                           TCGReg d, TCGReg n, TCGReg m)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_xor_vec:
-    case INDEX_op_or_vec:
-    case INDEX_op_and_vec:
-    case INDEX_op_cmp_vec:
         return C_O1_I2(w, w, w);
+    case INDEX_op_or_vec:
+        return C_O1_I2(w, w, wO);
+    case INDEX_op_and_vec:
+        return C_O1_I2(w, w, wV);
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, wZ);
 
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
     }
 }
 
+static const ARMInsn vec_cmp_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ,
+    [TCG_COND_GT] = INSN_VCGT,
+    [TCG_COND_GE] = INSN_VCGE,
+    [TCG_COND_GTU] = INSN_VCGT_U,
+    [TCG_COND_GEU] = INSN_VCGE_U,
+};
+
+static const ARMInsn vec_cmp0_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ0,
+    [TCG_COND_GT] = INSN_VCGT0,
+    [TCG_COND_GE] = INSN_VCGE0,
+    [TCG_COND_LT] = INSN_VCLT0,
+    [TCG_COND_LE] = INSN_VCLE0,
+};
+
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                            unsigned vecl, unsigned vece,
                            const TCGArg *args, const int *const_args)
 {
-    g_assert_not_reached();
+    TCGType type = vecl + TCG_TYPE_V64;
+    unsigned q = vecl;
+    TCGArg a0, a1, a2;
+    int cmode, imm8;
+
+    a0 = args[0];
+    a1 = args[1];
+    a2 = args[2];
+
+    switch (opc) {
+    case INDEX_op_ld_vec:
+        tcg_out_ld(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_st_vec:
+        tcg_out_st(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_dupm_vec:
+        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+        return;
+    case INDEX_op_dup2_vec:
+        tcg_out_dup2_vec(s, a0, a1, a2);
+        return;
+    case INDEX_op_add_vec:
+        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sub_vec:
+        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_xor_vec:
+        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_and_vec:
+        if (const_args[2]) {
+            is_shimm1632(~a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_or_vec:
+        if (const_args[2]) {
+            is_shimm1632(a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_cmp_vec:
+        {
+            TCGCond cond = args[3];
+
+            if (cond == TCG_COND_NE) {
+                if (const_args[2]) {
+                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
+                } else {
+                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
+                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+                }
+            } else {
+                ARMInsn insn;
+
+                if (const_args[2]) {
+                    insn = vec_cmp0_insn[cond];
+                    if (insn) {
+                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
+                        return;
+                    }
+                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
+                    a2 = TCG_VEC_TMP;
+                }
+                insn = vec_cmp_insn[cond];
+                if (insn == 0) {
+                    TCGArg t;
+                    t = a1, a1 = a2, a2 = t;
+                    cond = tcg_swap_cond(cond);
+                    insn = vec_cmp_insn[cond];
+                    tcg_debug_assert(insn != 0);
+                }
+                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+            }
+        }
+        return;
+
+    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
+    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
+    default:
+        g_assert_not_reached();
+    }
 }
 
 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 {
-    return 0;
+    switch (opc) {
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_xor_vec:
+        return 1;
+    case INDEX_op_cmp_vec:
+        return vece < MO_64;
+    default:
+        return 0;
+    }
 }
 
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-- 
2.25.1

These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         | 10 +++++-----
 tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 5 deletions(-)

This consists of the three immediate shifts: shli, shri, sari.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
-#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VCGE_U    = 0xf3000310,
     INSN_VCGT_U    = 0xf3000300,
 
+    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
+    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+
     INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
               | (extract32(imm8, 7, 1) << 24));
 }
 
+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+                            TCGReg rd, TCGReg rm, int l_imm6)
+{
+    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
+              (extract32(l_imm6, 6, 1) << 7) |
+              (extract32(l_imm6, 0, 6) << 16));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_abs_vec:
     case INDEX_op_neg_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return C_O1_I1(w, w);
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_shli_vec:
+        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
+        return;
+    case INDEX_op_shri_vec:
+        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
+        return;
+    case INDEX_op_sari_vec:
+        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
+        return;
 
     case INDEX_op_andc_vec:
         if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_orc_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     | 2 +-
 tcg/arm/tcg-target.c.inc | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

This is saturating add and subtract, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
-#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       0
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VORR      = 0xf2200110,
     INSN_VSUB      = 0xf3000800,
     INSN_VMUL      = 0xf2000910,
+    INSN_VQADD     = 0xf2000010,
+    INSN_VQADD_U   = 0xf3000010,
+    INSN_VQSUB     = 0xf2000210,
+    INSN_VQSUB_U   = 0xf3000210,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_ssadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sssub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_usadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_ussub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

This is minimum and maximum, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
-#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
 
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VQADD_U   = 0xf3000010,
     INSN_VQSUB     = 0xf2000210,
     INSN_VQSUB_U   = 0xf3000210,
+    INSN_VMAX      = 0xf2000600,
+    INSN_VMAX_U    = 0xf3000600,
+    INSN_VMIN      = 0xf2000610,
+    INSN_VMIN_U    = 0xf3000610,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
     case INDEX_op_ssadd_vec:
     case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_mul_vec:
         tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_smax_vec:
+        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_smin_vec:
+        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sssub_vec:
         tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_umax_vec:
+        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_umin_vec:
+        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_usadd_vec:
         tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_cmp_vec:
     case INDEX_op_mul_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
         return vece < MO_64;
     default:
         return 0;
-- 
2.25.1

NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         |  2 +-
 tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
 3 files changed, 22 insertions(+), 3 deletions(-)

The three vector shift by vector operations are all implemented via
expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.opc.h |  3 ++
 tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
  * consider these to be UNSPEC with names.
  */
+
+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
+    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
 
     INSN_VBSL      = 0xf3100110,
     INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
+    case INDEX_op_arm_sshl_vec:
+    case INDEX_op_arm_ushl_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
     case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_arm_sshl_vec:
+        /*
+         * Note that Vm is the data and Vn is the shift count,
+         * therefore the arguments appear reversed.
+         */
+        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
+        return;
+    case INDEX_op_arm_ushl_vec:
+        /* See above. */
+        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
+        return;
     case INDEX_op_shli_vec:
         tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_umax_vec:
     case INDEX_op_umin_vec:
         return vece < MO_64;
+    case INDEX_op_shlv_vec:
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        return -1;
     default:
         return 0;
     }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
-    g_assert_not_reached();
+    va_list va;
+    TCGv_vec v0, v1, v2, t1;
+    TCGArg a2;
+
+    va_start(va, a0);
+    v0 = temp_tcgv_vec(arg_temp(a0));
+    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+    a2 = va_arg(va, TCGArg);
+    va_end(va);
+
+    switch (opc) {
+    case INDEX_op_shlv_vec:
+        /*
+         * Merely propagate shlv_vec to arm_ushl_vec.
+         * In this way we don't set TCG_TARGET_HAS_shv_vec
+         * because everything is done via expansion.
+         */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        break;
+
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        /* Right shifts are negative left shifts for NEON.  */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_neg_vec(vece, t1, v2);
+        if (opc == INDEX_op_shrv_vec) {
+            opc = INDEX_op_arm_ushl_vec;
+        } else {
+            opc = INDEX_op_arm_sshl_vec;
+        }
+        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        tcg_temp_free_vec(t1);
+        break;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-- 
2.25.1

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.opc.h     |  1 +
 tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
 3 files changed, 17 insertions(+)

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
     case INDEX_op_rotli_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
         return -1;
     default:
         return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
     va_list va;
-    TCGv_vec v0, v1, v2, t1;
+    TCGv_vec v0, v1, v2, t1, t2, c1;
     TCGArg a2;
 
     va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         tcg_temp_free_vec(t1);
         break;
 
+    case INDEX_op_rotlv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_sub_vec(vece, t1, v2, c1);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        tcg_gen_or_vec(vece, v0, v0, t1);
+        tcg_temp_free_vec(t1);
+        break;
+
+    case INDEX_op_rotrv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        t2 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_neg_vec(vece, t1, v2);
+        tcg_gen_sub_vec(vece, t2, c1, v2);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+        tcg_gen_or_vec(vece, v0, t1, t2);
+        tcg_temp_free_vec(t1);
+        tcg_temp_free_vec(t2);
+        break;
+
     default:
         g_assert_not_reached();
     }
-- 
2.25.1

TCG patch queue, plus one target/sh4 patch that
Yoshinori Sato asked me to process.

The following changes since commit efbf38d73e5dcc4d5f8b98c6e7a12be1f3b91745:

Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-10-03 15:06:07 -0400)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004

for you to fetch changes up to ab419fd8a035a65942de4e63effcd55ccbf1a9fe:

target/sh4: Fix TB_FLAG_UNALIGN (2022-10-04 12:33:05 -0700)

----------------------------------------------------------------
Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN

----------------------------------------------------------------
Alex Bennée (3):
      cpu: cache CPUClass in CPUState for hot code paths
      hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
      cputlb: used cached CPUClass in our hot-paths

Leandro Lupori (1):
      tcg/ppc: Optimize 26-bit jumps

Richard Henderson (16):
      accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
      accel/tcg: Drop addr member from SavedIOTLB
      accel/tcg: Suppress auto-invalidate in probe_access_internal
      accel/tcg: Introduce probe_access_full
      accel/tcg: Introduce tlb_set_page_full
      include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
      accel/tcg: Remove PageDesc code_bitmap
      accel/tcg: Use bool for page_find_alloc
      accel/tcg: Use DisasContextBase in plugin_gen_tb_start
      accel/tcg: Do not align tb->page_addr[0]
      accel/tcg: Inline tb_flush_jmp_cache
      include/hw/core: Create struct CPUJumpCache
      hw/core: Add CPUClass.get_pc
      accel/tcg: Introduce tb_pc and log_pc
      accel/tcg: Introduce TARGET_TB_PCREL
      target/sh4: Fix TB_FLAG_UNALIGN

From: Alex Bennée <alex.bennee@linaro.org>

The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in the hot code paths.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-3-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h | 9 +++++++++
 cpu.c                 | 9 ++++-----
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  */
 #define CPU(obj) ((CPUState *)(obj))
 
+/*
+ * The class checkers bring in CPU_GET_CLASS() which is potentially
+ * expensive given the eventual call to
+ * object_class_dynamic_cast_assert(). Because of this the CPUState
+ * has a cached value for the class in cs->cc which is set up in
+ * cpu_exec_realizefn() for use in hot code paths.
+ */
 typedef struct CPUClass CPUClass;
 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
                        TYPE_CPU)
@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
 struct CPUState {
     /*< private >*/
     DeviceState parent_obj;
+    /* cache to avoid expensive CPU_GET_CLASS */
+    CPUClass *cc;
     /*< public >*/
 
     int nr_cores;
diff --git a/cpu.c b/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/cpu.c
+++ b/cpu.c
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_cpu_common = {
 
 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 {
-#ifndef CONFIG_USER_ONLY
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-#endif
+    /* cache the cpu class for the hotpath */
+    cpu->cc = CPU_GET_CLASS(cpu);
 
     cpu_list_add(cpu);
     if (!accel_cpu_realizefn(cpu, errp)) {
@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
     }
-    if (cc->sysemu_ops->legacy_vmsd != NULL) {
-        vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
+    if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
+        vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
     }
 #endif /* CONFIG_USER_ONLY */
 }
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a heavily used function so lets avoid the cost of
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:

Before: 36.812 s ±  0.506 s
  After:  35.912 s ±  0.168 s

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-4-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/core/cpu-sysemu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 
 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
     int ret = 0;
 
-    if (cc->sysemu_ops->asidx_from_attrs) {
-        ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
+    if (cpu->cc->sysemu_ops->asidx_from_attrs) {
+        ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
         assert(ret < cpu->num_ases && ret >= 0);
     }
     return ret;
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

Before: 35.912 s ±  0.168 s
  After: 35.565 s ±  0.087 s

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-5-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
                      MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
     bool ok;
 
     /*
      * This is not a probe, so only valid return is success; failure
      * should result in exception + longjmp to the cpu loop.
      */
-    ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
-                               access_type, mmu_idx, false, retaddr);
+    ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size,
+                                    access_type, mmu_idx, false, retaddr);
     assert(ok);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
                                         MMUAccessType access_type,
                                         int mmu_idx, uintptr_t retaddr)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-
-    cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+    cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type,
+                                          mmu_idx, retaddr);
 }
 
 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     if (!tlb_hit_page(tlb_addr, page_addr)) {
         if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
             CPUState *cs = env_cpu(env);
-            CPUClass *cc = CPU_GET_CLASS(cs);
 
-            if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
-                                       mmu_idx, nonfault, retaddr)) {
+            if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
+                                           mmu_idx, nonfault, retaddr)) {
                 /* Non-faulting page table read failed.  */
                 *phost = NULL;
                 return TLB_INVALID_MASK;
-- 
2.34.1

This structure will shortly contain more than just
data for accessing MMIO.  Rename the 'addr' member
to 'xlat_section' to more clearly indicate its purpose.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-defs.h    |  22 ++++----
 accel/tcg/cputlb.c         | 102 +++++++++++++++++++------------------
 target/arm/mte_helper.c    |  14 ++---
 target/arm/sve_helper.c    |   4 +-
 target/arm/translate-a64.c |   2 +-
 5 files changed, 73 insertions(+), 71 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t target_ulong;
 #  endif
 # endif
 
+/* Minimalized TLB entry for use by TCG fast path. */
 typedef struct CPUTLBEntry {
     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
 
 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 
-/* The IOTLB is not accessed directly inline by generated TCG code,
- * so the CPUIOTLBEntry layout is not as critical as that of the
- * CPUTLBEntry. (This is also why we don't want to combine the two
- * structs into one.)
+/*
+ * The full TLB entry, which is not accessed by generated TCG code,
+ * so the layout is not as critical as that of CPUTLBEntry. This is
+ * also why we don't want to combine the two structs.
  */
-typedef struct CPUIOTLBEntry {
+typedef struct CPUTLBEntryFull {
     /*
-     * @addr contains:
+     * @xlat_section contains:
      *  - in the lower TARGET_PAGE_BITS, a physical section number
      *  - with the lower TARGET_PAGE_BITS masked off, an offset which
      *    must be added to the virtual address to obtain:
@@ -XXX,XX +XXX,XX @@ typedef struct CPUIOTLBEntry {
      *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
      *     + the offset within the target MemoryRegion (otherwise)
      */
-    hwaddr addr;
+    hwaddr xlat_section;
     MemTxAttrs attrs;
-} CPUIOTLBEntry;
+} CPUTLBEntryFull;
 
 /*
  * Data elements that are per MMU mode, minus the bits accessed by
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBDesc {
     size_t vindex;
     /* The tlb victim table, in two parts.  */
     CPUTLBEntry vtable[CPU_VTLB_SIZE];
-    CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
-    /* The iotlb.  */
-    CPUIOTLBEntry *iotlb;
+    CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
+    CPUTLBEntryFull *fulltlb;
 } CPUTLBDesc;
 
 /*
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
     }
 
     g_free(fast->table);
-    g_free(desc->iotlb);
+    g_free(desc->fulltlb);
 
     tlb_window_reset(desc, now, 0);
     /* desc->n_used_entries is cleared by the caller */
     fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
     fast->table = g_try_new(CPUTLBEntry, new_size);
-    desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
+    desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
 
     /*
      * If the allocations fail, try smaller sizes. We just freed some
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
      * allocations to fail though, so we progressively reduce the allocation
      * size, aborting if we cannot even allocate the smallest TLB we support.
      */
-    while (fast->table == NULL || desc->iotlb == NULL) {
+    while (fast->table == NULL || desc->fulltlb == NULL) {
         if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
             error_report("%s: %s", __func__, strerror(errno));
             abort();
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
         fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 
         g_free(fast->table);
-        g_free(desc->iotlb);
+        g_free(desc->fulltlb);
         fast->table = g_try_new(CPUTLBEntry, new_size);
-        desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
+        desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
     desc->n_used_entries = 0;
     fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
     fast->table = g_new(CPUTLBEntry, n_entries);
-    desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
+    desc->fulltlb = g_new(CPUTLBEntryFull, n_entries);
     tlb_mmu_flush_locked(desc, fast);
 }
 
@@ -XXX,XX +XXX,XX @@ void tlb_destroy(CPUState *cpu)
         CPUTLBDescFast *fast = &env_tlb(env)->f[i];
 
         g_free(fast->table);
-        g_free(desc->iotlb);
+        g_free(desc->fulltlb);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 
         /* Evict the old entry into the victim tlb.  */
         copy_tlb_helper_locked(tv, te);
-        desc->viotlb[vidx] = desc->iotlb[index];
+        desc->vfulltlb[vidx] = desc->fulltlb[index];
         tlb_n_used_entries_dec(env, mmu_idx);
     }
 
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
      * subtract here is that of the page base, and not the same as the
      * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
      */
-    desc->iotlb[index].addr = iotlb - vaddr_page;
-    desc->iotlb[index].attrs = attrs;
+    desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
+    desc->fulltlb[index].attrs = attrs;
 
     /* Now calculate the new entry */
     tn.addend = addend - vaddr_page;
@@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
     }
 }
 
-static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
+static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
                          int mmu_idx, target_ulong addr, uintptr_t retaddr,
                          MMUAccessType access_type, MemOp op)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
     bool locked = false;
     MemTxResult r;
 
-    section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
+    section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
     mr = section->mr;
-    mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
+    mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
     cpu->mem_io_pc = retaddr;
     if (!cpu->can_do_io) {
         cpu_io_recompile(cpu, retaddr);
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
+    r = memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;
 
         cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type,
-                               mmu_idx, iotlbentry->attrs, r, retaddr);
+                               mmu_idx, full->attrs, r, retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
 }
 
 /*
- * Save a potentially trashed IOTLB entry for later lookup by plugin.
- * This is read by tlb_plugin_lookup if the iotlb entry doesn't match
+ * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
+ * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
  * because of the side effect of io_writex changing memory layout.
  */
 static void save_iotlb_data(CPUState *cs, hwaddr addr,
@@ -XXX,XX +XXX,XX @@ static void save_iotlb_data(CPUState *cs, hwaddr addr,
 #endif
 }
 
-static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
+static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
                       int mmu_idx, uint64_t val, target_ulong addr,
                       uintptr_t retaddr, MemOp op)
 {
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
     bool locked = false;
     MemTxResult r;
 
-    section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
+    section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
     mr = section->mr;
-    mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
+    mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
     if (!cpu->can_do_io) {
         cpu_io_recompile(cpu, retaddr);
     }
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
      * The memory_region_dispatch may trigger a flush/resize
      * so for plugins we save the iotlb_data just in case.
      */
-    save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset);
+    save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
 
     if (!qemu_mutex_iothread_locked()) {
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
+    r = memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;
 
         cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
-                               MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
+                               MMU_DATA_STORE, mmu_idx, full->attrs, r,
                                retaddr);
     }
     if (locked) {
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
             copy_tlb_helper_locked(vtlb, &tmptlb);
             qemu_spin_unlock(&env_tlb(env)->c.lock);
 
-            CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index];
-            CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx];
-            tmpio = *io; *io = *vio; *vio = tmpio;
+            CPUTLBEntryFull *f1 = &env_tlb(env)->d[mmu_idx].fulltlb[index];
+            CPUTLBEntryFull *f2 = &env_tlb(env)->d[mmu_idx].vfulltlb[vidx];
+            CPUTLBEntryFull tmpf;
+            tmpf = *f1; *f1 = *f2; *f2 = tmpf;
             return true;
         }
     }
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
                  (ADDR) & TARGET_PAGE_MASK)
 
 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
-                           CPUIOTLBEntry *iotlbentry, uintptr_t retaddr)
+                           CPUTLBEntryFull *full, uintptr_t retaddr)
 {
-    ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr;
+    ram_addr_t ram_addr = mem_vaddr + full->xlat_section;
 
     trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size);
 
@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
     /* Handle clean RAM pages.  */
     if (unlikely(flags & TLB_NOTDIRTY)) {
         uintptr_t index = tlb_index(env, mmu_idx, addr);
-        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 
-        notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
+        notdirty_write(env_cpu(env), addr, 1, full, retaddr);
         flags &= ~TLB_NOTDIRTY;
     }
 
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
 
     if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
         uintptr_t index = tlb_index(env, mmu_idx, addr);
-        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 
         /* Handle watchpoints.  */
         if (flags & TLB_WATCHPOINT) {
             int wp_access = (access_type == MMU_DATA_STORE
                              ? BP_MEM_WRITE : BP_MEM_READ);
             cpu_check_watchpoint(env_cpu(env), addr, size,
-                                 iotlbentry->attrs, wp_access, retaddr);
+                                 full->attrs, wp_access, retaddr);
         }
 
         /* Handle clean RAM pages.  */
         if (flags & TLB_NOTDIRTY) {
-            notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
+            notdirty_write(env_cpu(env), addr, 1, full, retaddr);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
  * should have just filled the TLB. The one corner case is io_writex
  * which can cause TLB flushes and potential resizing of the TLBs
  * losing the information we need. In those cases we need to recover
- * data from a copy of the iotlbentry. As long as this always occurs
+ * data from a copy of the CPUTLBEntryFull. As long as this always occurs
  * from the same thread (which a mem callback will be) this is safe.
  */
 
@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
     if (likely(tlb_hit(tlb_addr, addr))) {
         /* We must have an iotlb entry for MMIO */
         if (tlb_addr & TLB_MMIO) {
-            CPUIOTLBEntry *iotlbentry;
-            iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+            CPUTLBEntryFull *full;
+            full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
             data->is_io = true;
-            data->v.io.section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
-            data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
+            data->v.io.section =
+                iotlb_to_section(cpu, full->xlat_section, full->attrs);
+            data->v.io.offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
         } else {
             data->is_io = false;
             data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 
     if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
         notdirty_write(env_cpu(env), addr, size,
-                       &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr);
+                       &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr);
     }
 
     return hostaddr;
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
 
     /* Handle anything that isn't just a straight memory access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
+        CPUTLBEntryFull *full;
         bool need_swap;
 
         /* For anything that is unaligned, recurse through full_load.  */
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
             goto do_unaligned_access;
         }
 
-        iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+        full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 
         /* Handle watchpoints.  */
         if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
             /* On watchpoint hit, this will longjmp out.  */
             cpu_check_watchpoint(env_cpu(env), addr, size,
-                                 iotlbentry->attrs, BP_MEM_READ, retaddr);
+                                 full->attrs, BP_MEM_READ, retaddr);
         }
 
         need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
 
         /* Handle I/O access.  */
         if (likely(tlb_addr & TLB_MMIO)) {
-            return io_readx(env, iotlbentry, mmu_idx, addr, retaddr,
+            return io_readx(env, full, mmu_idx, addr, retaddr,
                             access_type, op ^ (need_swap * MO_BSWAP));
         }
 
@@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
      */
     if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
         cpu_check_watchpoint(env_cpu(env), addr, size - size2,
-                             env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
+                             env_tlb(env)->d[mmu_idx].fulltlb[index].attrs,
                              BP_MEM_WRITE, retaddr);
     }
     if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) {
         cpu_check_watchpoint(env_cpu(env), page2, size2,
-                             env_tlb(env)->d[mmu_idx].iotlb[index2].attrs,
+                             env_tlb(env)->d[mmu_idx].fulltlb[index2].attrs,
                              BP_MEM_WRITE, retaddr);
     }
 
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
 
     /* Handle anything that isn't just a straight memory access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
+        CPUTLBEntryFull *full;
         bool need_swap;
 
         /* For anything that is unaligned, recurse through byte stores.  */
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
             goto do_unaligned_access;
         }
 
-        iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+        full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 
         /* Handle watchpoints.  */
         if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
             /* On watchpoint hit, this will longjmp out.  */
             cpu_check_watchpoint(env_cpu(env), addr, size,
-                                 iotlbentry->attrs, BP_MEM_WRITE, retaddr);
+                                 full->attrs, BP_MEM_WRITE, retaddr);
         }
 
         need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
 
         /* Handle I/O access.  */
         if (tlb_addr & TLB_MMIO) {
-            io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
+            io_writex(env, full, mmu_idx, val, addr, retaddr,
                       op ^ (need_swap * MO_BSWAP));
             return;
         }
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
 
         /* Handle clean RAM pages.  */
         if (tlb_addr & TLB_NOTDIRTY) {
-            notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
+            notdirty_write(env_cpu(env), addr, size, full, retaddr);
         }
 
         haddr = (void *)((uintptr_t)addr + entry->addend);
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
     return tags + index;
 #else
     uintptr_t index;
-    CPUIOTLBEntry *iotlbentry;
+    CPUTLBEntryFull *full;
     int in_page, flags;
     ram_addr_t ptr_ra;
     hwaddr ptr_paddr, tag_paddr, xlat;
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
     assert(!(flags & TLB_INVALID_MASK));
 
     /*
-     * Find the iotlbentry for ptr.  This *must* be present in the TLB
+     * Find the CPUTLBEntryFull for ptr.  This *must* be present in the TLB
      * because we just found the mapping.
      * TODO: Perhaps there should be a cputlb helper that returns a
      * matching tlb entry + iotlb entry.
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
         g_assert(tlb_hit(comparator, ptr));
     }
 # endif
-    iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index];
+    full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
 
     /* If the virtual page MemAttr != Tagged, access unchecked. */
-    if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) {
+    if (!arm_tlb_mte_tagged(&full->attrs)) {
         return NULL;
     }
 
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
         int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
         assert(ra != 0);
         cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
-                             iotlbentry->attrs, wp, ra);
+                             full->attrs, wp, ra);
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
     tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
 
     /* Look up the address in tag space. */
-    tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
+    tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
     tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
     mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
                                  tag_access == MMU_DATA_STORE,
-                                 iotlbentry->attrs);
+                                 full->attrs);
 
     /*
      * Note that @mr will never be NULL.  If there is nothing in the address
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
         g_assert(tlb_hit(comparator, addr));
 # endif
 
-        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
-        info->attrs = iotlbentry->attrs;
+        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
+        info->attrs = full->attrs;
     }
 #endif
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
      * table entry even for that case.
      */
     return (tlb_hit(entry->addr_code, addr) &&
-            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs));
+            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs));
 #endif
 }
 
-- 
2.34.1

This field is only written, not read; remove it.

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPUWatchpoint {
  * the memory regions get moved around  by io_writex.
  */
 typedef struct SavedIOTLB {
-    hwaddr addr;
     MemoryRegionSection *section;
     hwaddr mr_offset;
 } SavedIOTLB;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
  * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
  * because of the side effect of io_writex changing memory layout.
  */
-static void save_iotlb_data(CPUState *cs, hwaddr addr,
-                            MemoryRegionSection *section, hwaddr mr_offset)
+static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
+                            hwaddr mr_offset)
 {
 #ifdef CONFIG_PLUGIN
     SavedIOTLB *saved = &cs->saved_iotlb;
-    saved->addr = addr;
     saved->section = section;
     saved->mr_offset = mr_offset;
 #endif
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
      * The memory_region_dispatch may trigger a flush/resize
      * so for plugins we save the iotlb_data just in case.
      */
-    save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
+    save_iotlb_data(cpu, section, mr_offset);
 
     if (!qemu_mutex_iothread_locked()) {
         qemu_mutex_lock_iothread();
-- 
2.34.1

When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup.  Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.

This allows us to remove a warning comment from s390x.
There doesn't seem to be a reason to change the code though.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c            | 10 +++++++++-
 target/s390x/tcg/mem_helper.c |  4 ----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     }
     tlb_addr = tlb_read_ofs(entry, elt_ofs);
 
+    flags = TLB_FLAGS_MASK;
     page_addr = addr & TARGET_PAGE_MASK;
     if (!tlb_hit_page(tlb_addr, page_addr)) {
         if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
 
             /* TLB resize via tlb_fill may have moved the entry.  */
             entry = tlb_entry(env, mmu_idx, addr);
+
+            /*
+             * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
+             * to force the next access through tlb_fill.  We've just
+             * called tlb_fill, so we know that this entry *is* valid.
+             */
+            flags &= ~TLB_INVALID_MASK;
         }
         tlb_addr = tlb_read_ofs(entry, elt_ofs);
     }
-    flags = tlb_addr & TLB_FLAGS_MASK;
+    flags &= tlb_addr;
 
     /* Fold all "mmio-like" bits into TLB_MMIO.  This is not RAM.  */
     if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -XXX,XX +XXX,XX @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
 #else
     int flags;
 
-    /*
-     * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
-     * to detect if there was an exception during tlb_fill().
-     */
     env->tlb_fill_exc = 0;
     flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost,
                                ra);
-- 
2.34.1

Add an interface to return the CPUTLBEntryFull struct
that goes with the lookup.  The result is not intended
to be valid across multiple lookups, so the user must
use the results immediately.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/exec-all.h | 15 +++++++++++++
 include/qemu/typedefs.h |  1 +
 accel/tcg/cputlb.c      | 47 +++++++++++++++++++++++++----------------
 3 files changed, 45 insertions(+), 18 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
                        MMUAccessType access_type, int mmu_idx,
                        bool nonfault, void **phost, uintptr_t retaddr);
 
+#ifndef CONFIG_USER_ONLY
+/**
+ * probe_access_full:
+ * Like probe_access_flags, except also return into @pfull.
+ *
+ * The CPUTLBEntryFull structure returned via @pfull is transient
+ * and must be consumed or copied immediately, before any further
+ * access or changes to TLB @mmu_idx.
+ */
+int probe_access_full(CPUArchState *env, target_ulong addr,
+                      MMUAccessType access_type, int mmu_idx,
+                      bool nonfault, void **phost,
+                      CPUTLBEntryFull **pfull, uintptr_t retaddr);
+#endif
+
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 
 /* Estimated block size for TB allocation.  */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
 typedef struct CPUAddressSpace CPUAddressSpace;
 typedef struct CPUArchState CPUArchState;
 typedef struct CPUState CPUState;
+typedef struct CPUTLBEntryFull CPUTLBEntryFull;
 typedef struct DeviceListener DeviceListener;
 typedef struct DeviceState DeviceState;
 typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
 static int probe_access_internal(CPUArchState *env, target_ulong addr,
                                  int fault_size, MMUAccessType access_type,
                                  int mmu_idx, bool nonfault,
-                                 void **phost, uintptr_t retaddr)
+                                 void **phost, CPUTLBEntryFull **pfull,
+                                 uintptr_t retaddr)
 {
     uintptr_t index = tlb_index(env, mmu_idx, addr);
     CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
                                            mmu_idx, nonfault, retaddr)) {
                 /* Non-faulting page table read failed.  */
                 *phost = NULL;
+                *pfull = NULL;
                 return TLB_INVALID_MASK;
             }
 
             /* TLB resize via tlb_fill may have moved the entry.  */
+            index = tlb_index(env, mmu_idx, addr);
             entry = tlb_entry(env, mmu_idx, addr);
 
             /*
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     }
     flags &= tlb_addr;
 
+    *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index];
+
     /* Fold all "mmio-like" bits into TLB_MMIO.  This is not RAM.  */
     if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
         *phost = NULL;
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     return flags;
 }
 
-int probe_access_flags(CPUArchState *env, target_ulong addr,
-                       MMUAccessType access_type, int mmu_idx,
-                       bool nonfault, void **phost, uintptr_t retaddr)
+int probe_access_full(CPUArchState *env, target_ulong addr,
+                      MMUAccessType access_type, int mmu_idx,
+                      bool nonfault, void **phost, CPUTLBEntryFull **pfull,
+                      uintptr_t retaddr)
 {
-    int flags;
-
-    flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
-                                  nonfault, phost, retaddr);
+    int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
+                                      nonfault, phost, pfull, retaddr);
 
     /* Handle clean RAM pages.  */
     if (unlikely(flags & TLB_NOTDIRTY)) {
-        uintptr_t index = tlb_index(env, mmu_idx, addr);
-        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
-
-        notdirty_write(env_cpu(env), addr, 1, full, retaddr);
+        notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr);
         flags &= ~TLB_NOTDIRTY;
     }
 
     return flags;
 }
 
+int probe_access_flags(CPUArchState *env, target_ulong addr,
+                       MMUAccessType access_type, int mmu_idx,
+                       bool nonfault, void **phost, uintptr_t retaddr)
+{
+    CPUTLBEntryFull *full;
+
+    return probe_access_full(env, addr, access_type, mmu_idx,
+                             nonfault, phost, &full, retaddr);
+}
+
 void *probe_access(CPUArchState *env, target_ulong addr, int size,
                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
 {
+    CPUTLBEntryFull *full;
     void *host;
     int flags;
 
     g_assert(-(addr | TARGET_PAGE_MASK) >= size);
 
     flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
-                                  false, &host, retaddr);
+                                  false, &host, &full, retaddr);
 
     /* Per the interface, size == 0 merely faults the access. */
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
     }
 
     if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
-        uintptr_t index = tlb_index(env, mmu_idx, addr);
-        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
-
         /* Handle watchpoints.  */
         if (flags & TLB_WATCHPOINT) {
             int wp_access = (access_type == MMU_DATA_STORE
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
                         MMUAccessType access_type, int mmu_idx)
 {
+    CPUTLBEntryFull *full;
     void *host;
     int flags;
 
     flags = probe_access_internal(env, addr, 0, access_type,
-                                  mmu_idx, true, &host, 0);
+                                  mmu_idx, true, &host, &full, 0);
 
     /* No combination of flags are expected by the caller. */
     return flags ? NULL : host;
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
                                         void **hostp)
 {
+    CPUTLBEntryFull *full;
     void *p;
 
     (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
-                                cpu_mmu_index(env, true), false, &p, 0);
+                                cpu_mmu_index(env, true), false, &p, &full, 0);
     if (p == NULL) {
         return -1;
     }
-- 
2.34.1

Now that we have collected all of the page data into
CPUTLBEntryFull, provide an interface to record that
all in one go, instead of using 4 arguments.  This interface
allows CPUTLBEntryFull to be extended without having to
change the number of arguments.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-defs.h | 14 +++++++++++
 include/exec/exec-all.h | 22 ++++++++++++++++++
 accel/tcg/cputlb.c      | 51 ++++++++++++++++++++++++++---------------
 3 files changed, 69 insertions(+), 18 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
      *     + the offset within the target MemoryRegion (otherwise)
      */
     hwaddr xlat_section;
+
+    /*
+     * @phys_addr contains the physical address in the address space
+     * given by cpu_asidx_from_attrs(cpu, @attrs).
+     */
+    hwaddr phys_addr;
+
+    /* @attrs contains the memory transaction attributes for the page. */
     MemTxAttrs attrs;
+
+    /* @prot contains the complete protections for the page. */
+    uint8_t prot;
+
+    /* @lg_page_size contains the log2 of the page size. */
+    uint8_t lg_page_size;
 } CPUTLBEntryFull;
 
 /*
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                uint16_t idxmap,
                                                unsigned bits);
 
+/**
+ * tlb_set_page_full:
+ * @cpu: CPU context
+ * @mmu_idx: mmu index of the tlb to modify
+ * @vaddr: virtual address of the entry to add
+ * @full: the details of the tlb entry
+ *
+ * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
+ * @full must be filled, except for xlat_section, and constitute
+ * the complete description of the translated page.
+ *
+ * This is generally called by the target tlb_fill function after
+ * having performed a successful page table walk to find the physical
+ * address and attributes for the translation.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
+ * used by tlb_flush_page.
+ */
+void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
+                       CPUTLBEntryFull *full);
+
 /**
  * tlb_set_page_with_attrs:
  * @cpu: CPU to add this TLB entry for
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
     env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
 }
 
-/* Add a new TLB entry. At most one entry for a given virtual address
+/*
+ * Add a new TLB entry. At most one entry for a given virtual address
  * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
  * supplied size is only used by tlb_flush_page.
  *
  * Called from TCG-generated code, which is under an RCU read-side
  * critical section.
  */
-void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
-                             hwaddr paddr, MemTxAttrs attrs, int prot,
-                             int mmu_idx, target_ulong size)
+void tlb_set_page_full(CPUState *cpu, int mmu_idx,
+                       target_ulong vaddr, CPUTLBEntryFull *full)
 {
     CPUArchState *env = cpu->env_ptr;
     CPUTLB *tlb = env_tlb(env);
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     CPUTLBEntry *te, tn;
     hwaddr iotlb, xlat, sz, paddr_page;
     target_ulong vaddr_page;
-    int asidx = cpu_asidx_from_attrs(cpu, attrs);
-    int wp_flags;
+    int asidx, wp_flags, prot;
     bool is_ram, is_romd;
 
     assert_cpu_is_self(cpu);
 
-    if (size <= TARGET_PAGE_SIZE) {
+    if (full->lg_page_size <= TARGET_PAGE_BITS) {
         sz = TARGET_PAGE_SIZE;
     } else {
-        tlb_add_large_page(env, mmu_idx, vaddr, size);
-        sz = size;
+        sz = (hwaddr)1 << full->lg_page_size;
+        tlb_add_large_page(env, mmu_idx, vaddr, sz);
     }
     vaddr_page = vaddr & TARGET_PAGE_MASK;
-    paddr_page = paddr & TARGET_PAGE_MASK;
+    paddr_page = full->phys_addr & TARGET_PAGE_MASK;
 
+    prot = full->prot;
+    asidx = cpu_asidx_from_attrs(cpu, full->attrs);
     section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
-                                                &xlat, &sz, attrs, &prot);
+                                                &xlat, &sz, full->attrs, &prot);
     assert(sz >= TARGET_PAGE_SIZE);
 
     tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
               " prot=%x idx=%d\n",
-              vaddr, paddr, prot, mmu_idx);
+              vaddr, full->phys_addr, prot, mmu_idx);
 
     address = vaddr_page;
-    if (size < TARGET_PAGE_SIZE) {
+    if (full->lg_page_size < TARGET_PAGE_BITS) {
         /* Repeat the MMU check and TLB fill on every access.  */
         address |= TLB_INVALID_MASK;
     }
-    if (attrs.byte_swap) {
+    if (full->attrs.byte_swap) {
         address |= TLB_BSWAP;
     }
 
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
      * subtract here is that of the page base, and not the same as the
      * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
      */
+    desc->fulltlb[index] = *full;
     desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
-    desc->fulltlb[index].attrs = attrs;
+    desc->fulltlb[index].phys_addr = paddr_page;
+    desc->fulltlb[index].prot = prot;
 
     /* Now calculate the new entry */
     tn.addend = addend - vaddr_page;
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     qemu_spin_unlock(&tlb->c.lock);
 }
 
-/* Add a new TLB entry, but without specifying the memory
- * transaction attributes to be used.
- */
+void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
+                             hwaddr paddr, MemTxAttrs attrs, int prot,
+                             int mmu_idx, target_ulong size)
+{
+    CPUTLBEntryFull full = {
+        .phys_addr = paddr,
+        .attrs = attrs,
+        .prot = prot,
+        .lg_page_size = ctz64(size)
+    };
+
+    assert(is_power_of_2(size));
+    tlb_set_page_full(cpu, mmu_idx, vaddr, &full);
+}
+
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size)
-- 
2.34.1

This bitmap is created and discarded immediately.
We gain nothing by its existence.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org>
---
 accel/tcg/translate-all.c | 78 ++-------------------------------------
 1 file changed, 4 insertions(+), 74 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@
 #define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
 #endif
 
-#define SMC_BITMAP_USE_THRESHOLD 10
-
 typedef struct PageDesc {
     /* list of TBs intersecting this ram page */
     uintptr_t first_tb;
-#ifdef CONFIG_SOFTMMU
-    /* in order to optimize self modifying code, we count the number
-       of lookups we do to a given page to use a bitmap */
-    unsigned long *code_bitmap;
-    unsigned int code_write_count;
-#else
+#ifdef CONFIG_USER_ONLY
     unsigned long flags;
     void *target_data;
 #endif
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_SOFTMMU
     QemuSpin lock;
 #endif
 } PageDesc;
@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void)
     qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode);
 }
 
-/* call with @p->lock held */
-static inline void invalidate_page_bitmap(PageDesc *p)
-{
-    assert_page_locked(p);
-#ifdef CONFIG_SOFTMMU
-    g_free(p->code_bitmap);
-    p->code_bitmap = NULL;
-    p->code_write_count = 0;
-#endif
-}
-
 /* Set to NULL all the 'first_tb' fields in all PageDescs. */
 static void page_flush_tb_1(int level, void **lp)
 {
@@ -XXX,XX +XXX,XX @@ static void page_flush_tb_1(int level, void **lp)
         for (i = 0; i < V_L2_SIZE; ++i) {
             page_lock(&pd[i]);
             pd[i].first_tb = (uintptr_t)NULL;
-            invalidate_page_bitmap(pd + i);
             page_unlock(&pd[i]);
         }
     } else {
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
     if (rm_from_page_list) {
         p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
         tb_page_remove(p, tb);
-        invalidate_page_bitmap(p);
         if (tb->page_addr[1] != -1) {
             p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
             tb_page_remove(p, tb);
-            invalidate_page_bitmap(p);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
     }
 }
 
-#ifdef CONFIG_SOFTMMU
-/* call with @p->lock held */
-static void build_page_bitmap(PageDesc *p)
-{
-    int n, tb_start, tb_end;
-    TranslationBlock *tb;
-
-    assert_page_locked(p);
-    p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE);
-
-    PAGE_FOR_EACH_TB(p, tb, n) {
-        /* NOTE: this is subtle as a TB may span two physical pages */
-        if (n == 0) {
-            /* NOTE: tb_end may be after the end of the page, but
-               it is not a problem */
-            tb_start = tb->pc & ~TARGET_PAGE_MASK;
-            tb_end = tb_start + tb->size;
-            if (tb_end > TARGET_PAGE_SIZE) {
-                tb_end = TARGET_PAGE_SIZE;
-             }
-        } else {
-            tb_start = 0;
-            tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
-        }
-        bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start);
-    }
-}
-#endif
-
 /* add the tb in the target page and protect it if necessary
  *
  * Called with mmap_lock held for user-mode emulation.
@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
     page_already_protected = p->first_tb != (uintptr_t)NULL;
 #endif
     p->first_tb = (uintptr_t)tb | n;
-    invalidate_page_bitmap(p);
 
 #if defined(CONFIG_USER_ONLY)
     /* translator_loop() must have made all TB pages non-writable */
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
     /* remove TB from the page(s) if we couldn't insert it */
     if (unlikely(existing_tb)) {
         tb_page_remove(p, tb);
-        invalidate_page_bitmap(p);
         if (p2) {
             tb_page_remove(p2, tb);
-            invalidate_page_bitmap(p2);
         }
         tb = existing_tb;
     }
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
 #if !defined(CONFIG_USER_ONLY)
     /* if no code remaining, no need to continue to use slow writes */
     if (!p->first_tb) {
-        invalidate_page_bitmap(p);
         tlb_unprotect_code(start);
     }
 #endif
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_fast(struct page_collection *pages,
     }
 
     assert_page_locked(p);
-    if (!p->code_bitmap &&
-        ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) {
-        build_page_bitmap(p);
-    }
-    if (p->code_bitmap) {
-        unsigned int nr;
-        unsigned long b;
-
-        nr = start & ~TARGET_PAGE_MASK;
-        b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1));
-        if (b & ((1 << len) - 1)) {
-            goto do_invalidate;
-        }
-    } else {
-    do_invalidate:
-        tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
-                                              retaddr);
-    }
+    tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
+                                          retaddr);
 }
 #else
 /* Called with mmap_lock held. If pc is not 0 then it indicates the
-- 
2.34.1

Bool is more appropriate type for the alloc parameter.

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void page_init(void)
 #endif
 }
 
-static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
+static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc)
 {
     PageDesc *pd;
     void **lp;
@@ -XXX,XX +XXX,XX @@ static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
 
 static inline PageDesc *page_find(tb_page_addr_t index)
 {
-    return page_find_alloc(index, 0);
+    return page_find_alloc(index, false);
 }
 
 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
-                           PageDesc **ret_p2, tb_page_addr_t phys2, int alloc);
+                           PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc);
 
 /* In user-mode page locks aren't used; mmap_lock is enough */
 #ifdef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static inline void page_unlock(PageDesc *pd)
 /* lock the page(s) of a TB in the correct acquisition order */
 static inline void page_lock_tb(const TranslationBlock *tb)
 {
-    page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0);
+    page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false);
 }
 
 static inline void page_unlock_tb(const TranslationBlock *tb)
@@ -XXX,XX +XXX,XX @@ void page_collection_unlock(struct page_collection *set)
 #endif /* !CONFIG_USER_ONLY */
 
 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
-                           PageDesc **ret_p2, tb_page_addr_t phys2, int alloc)
+                           PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc)
 {
     PageDesc *p1, *p2;
     tb_page_addr_t page1;
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
      * Note that inserting into the hash table first isn't an option, since
      * we can only insert TBs that are fully initialized.
      */
-    page_lock_pair(&p, phys_pc, &p2, phys_page2, 1);
+    page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
     tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
     if (p2) {
         tb_page_add(p2, tb, 1, phys_page2);
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
     for (addr = start, len = end - start;
          len != 0;
          len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
-        PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
+        PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true);
 
         /* If the write protection bit is set, then we invalidate
            the code inside.  */
-- 
2.34.1

Use the pc coming from db->pc_first rather than the TB.

Use the cached host_addr rather than re-computing for the
first page.  We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/plugin-gen.h |  7 ++++---
 accel/tcg/plugin-gen.c    | 22 +++++++++++-----------
 accel/tcg/translator.c    |  2 +-
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/plugin-gen.h
+++ b/include/exec/plugin-gen.h
@@ -XXX,XX +XXX,XX @@ struct DisasContextBase;
 
 #ifdef CONFIG_PLUGIN
 
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress);
+bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db,
+                         bool supress);
 void plugin_gen_tb_end(CPUState *cpu);
 void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *db);
 void plugin_gen_insn_end(void);
@@ -XXX,XX +XXX,XX @@ static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size)
 
 #else /* !CONFIG_PLUGIN */
 
-static inline
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress)
+static inline bool
+plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool sup)
 {
     return false;
 }
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(const struct qemu_plugin_tb *plugin_tb)
     pr_ops();
 }
 
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_only)
+bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db,
+                         bool mem_only)
 {
     bool ret = false;
 
@@ -XXX,XX +XXX,XX @@ bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_onl
 
         ret = true;
 
-        ptb->vaddr = tb->pc;
+        ptb->vaddr = db->pc_first;
         ptb->vaddr2 = -1;
-        get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1);
+        ptb->haddr1 = db->host_addr[0];
         ptb->haddr2 = NULL;
         ptb->mem_only = mem_only;
 
@@ -XXX,XX +XXX,XX @@ void plugin_gen_insn_start(CPUState *cpu, const DisasContextBase *db)
      * Note that we skip this when haddr1 == NULL, e.g. when we're
      * fetching instructions from a region not backed by RAM.
      */
-    if (likely(ptb->haddr1 != NULL && ptb->vaddr2 == -1) &&
-        unlikely((db->pc_next & TARGET_PAGE_MASK) !=
-                 (db->pc_first & TARGET_PAGE_MASK))) {
-        get_page_addr_code_hostp(cpu->env_ptr, db->pc_next,
-                                 &ptb->haddr2);
-        ptb->vaddr2 = db->pc_next;
-    }
-    if (likely(ptb->vaddr2 == -1)) {
+    if (ptb->haddr1 == NULL) {
+        pinsn->haddr = NULL;
+    } else if (is_same_page(db, db->pc_next)) {
         pinsn->haddr = ptb->haddr1 + pinsn->vaddr - ptb->vaddr;
     } else {
+        if (ptb->vaddr2 == -1) {
+            ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first);
+            get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2);
+        }
         pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2;
     }
 }
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
     ops->tb_start(db, cpu);
     tcg_debug_assert(db->is_jmp == DISAS_NEXT);  /* no early exit */
 
-    plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY);
+    plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY);
 
     while (true) {
         db->num_insns++;
-- 
2.34.1

Let tb->page_addr[0] contain the address of the first byte of the
translated block, rather than the address of the page containing the
start of the translated block.  We need to recover this value anyway
at various points, and it is easier to discard a page offset when it
is not needed, which happens naturally via the existing find_page shift.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cpu-exec.c      | 16 ++++++++--------
 accel/tcg/cputlb.c        |  3 ++-
 accel/tcg/translate-all.c |  9 +++++----
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ struct tb_desc {
     target_ulong pc;
     target_ulong cs_base;
     CPUArchState *env;
-    tb_page_addr_t phys_page1;
+    tb_page_addr_t page_addr0;
     uint32_t flags;
     uint32_t cflags;
     uint32_t trace_vcpu_dstate;
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
     const struct tb_desc *desc = d;
 
     if (tb->pc == desc->pc &&
-        tb->page_addr[0] == desc->phys_page1 &&
+        tb->page_addr[0] == desc->page_addr0 &&
         tb->cs_base == desc->cs_base &&
         tb->flags == desc->flags &&
         tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
         if (tb->page_addr[1] == -1) {
             return true;
         } else {
-            tb_page_addr_t phys_page2;
-            target_ulong virt_page2;
+            tb_page_addr_t phys_page1;
+            target_ulong virt_page1;
 
             /*
              * We know that the first page matched, and an otherwise valid TB
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
              * is different for the new TB.  Therefore any exception raised
              * here by the faulting lookup is not premature.
              */
-            virt_page2 = TARGET_PAGE_ALIGN(desc->pc);
-            phys_page2 = get_page_addr_code(desc->env, virt_page2);
-            if (tb->page_addr[1] == phys_page2) {
+            virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
+            phys_page1 = get_page_addr_code(desc->env, virt_page1);
+            if (tb->page_addr[1] == phys_page1) {
                 return true;
             }
         }
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
     if (phys_pc == -1) {
         return NULL;
     }
-    desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
+    desc.page_addr0 = phys_pc;
     h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
     return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
 }
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
    can be detected */
 void tlb_protect_code(ram_addr_t ram_addr)
 {
-    cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
+    cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK,
+                                             TARGET_PAGE_SIZE,
                                              DIRTY_MEMORY_CODE);
 }
 
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
     qemu_spin_unlock(&tb->jmp_lock);
 
     /* remove the TB from the hash list */
-    phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
+    phys_pc = tb->page_addr[0];
     h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
                      tb->trace_vcpu_dstate);
     if (!qht_remove(&tb_ctx.htable, tb, h)) {
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
      * we can only insert TBs that are fully initialized.
      */
     page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
-    tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
+    tb_page_add(p, tb, 0, phys_pc);
     if (p2) {
         tb_page_add(p2, tb, 1, phys_page2);
     } else {
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
         if (n == 0) {
             /* NOTE: tb_end may be after the end of the page, but
                it is not a problem */
-            tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
+            tb_start = tb->page_addr[0];
             tb_end = tb_start + tb->size;
         } else {
             tb_start = tb->page_addr[1];
-            tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
+            tb_end = tb_start + ((tb->page_addr[0] + tb->size)
+                                 & ~TARGET_PAGE_MASK);
         }
         if (!(tb_end <= start || tb_start >= end)) {
 #ifdef TARGET_HAS_PRECISE_SMC
-- 
2.34.1

This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.

This avoids double-flushing of jmp cache pages in a range.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
     }
 }
 
-static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
-{
-    /* Discard jump cache entries for any tb which might potentially
-       overlap the flushed page.  */
-    tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
-    tb_jmp_cache_clear_page(cpu, addr);
-}
-
 /**
  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
  * @desc: The CPUTLBDesc portion of the TLB
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
     }
     qemu_spin_unlock(&env_tlb(env)->c.lock);
 
-    tb_flush_jmp_cache(cpu, addr);
+    /*
+     * Discard jump cache entries for any tb which might potentially
+     * overlap the flushed page, which includes the previous.
+     */
+    tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
+    tb_jmp_cache_clear_page(cpu, addr);
 }
 
 /**
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
         return;
     }
 
-    for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) {
-        tb_flush_jmp_cache(cpu, d.addr + i);
+    /*
+     * Discard jump cache entries for any tb which might potentially
+     * overlap the flushed pages, which includes the previous.
+     */
+    d.addr -= TARGET_PAGE_SIZE;
+    for (target_ulong i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) {
+        tb_jmp_cache_clear_page(cpu, d.addr);
+        d.addr += TARGET_PAGE_SIZE;
     }
 }
 
-- 
2.34.1

Wrap the bare TranslationBlock pointer into a structure.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/tb-hash.h       |  1 +
 accel/tcg/tb-jmp-cache.h  | 24 ++++++++++++++++++++++++
 include/exec/cpu-common.h |  1 +
 include/hw/core/cpu.h     | 15 +--------------
 include/qemu/typedefs.h   |  1 +
 accel/stubs/tcg-stub.c    |  4 ++++
 accel/tcg/cpu-exec.c      | 10 +++++++---
 accel/tcg/cputlb.c        |  9 +++++----
 accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++---
 hw/core/cpu-common.c      |  3 +--
 plugins/core.c            |  2 +-
 trace/control-target.c    |  2 +-
 12 files changed, 72 insertions(+), 28 deletions(-)
 create mode 100644 accel/tcg/tb-jmp-cache.h

diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tb-hash.h
+++ b/accel/tcg/tb-hash.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu-defs.h"
 #include "exec/exec-all.h"
 #include "qemu/xxhash.h"
+#include "tb-jmp-cache.h"
 
 #ifdef CONFIG_SOFTMMU
 
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/accel/tcg/tb-jmp-cache.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * The per-CPU TranslationBlock jump cache.
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ACCEL_TCG_TB_JMP_CACHE_H
+#define ACCEL_TCG_TB_JMP_CACHE_H
+
+#define TB_JMP_CACHE_BITS 12
+#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
+
+/*
+ * Accessed in parallel; all accesses to 'tb' must be atomic.
+ */
+struct CPUJumpCache {
+    struct {
+        TranslationBlock *tb;
+    } array[TB_JMP_CACHE_SIZE];
+};
+
+#endif /* ACCEL_TCG_TB_JMP_CACHE_H */
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -XXX,XX +XXX,XX @@ void cpu_list_unlock(void);
 unsigned int cpu_list_generation_id_get(void);
 
 void tcg_flush_softmmu_tlb(CPUState *cs);
+void tcg_flush_jmp_cache(CPUState *cs);
 
 void tcg_iommu_init_notifier_list(CPUState *cpu);
 void tcg_iommu_free_notifier_list(CPUState *cpu);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -XXX,XX +XXX,XX @@ struct kvm_run;
 struct hax_vcpu_state;
 struct hvf_vcpu_state;
 
-#define TB_JMP_CACHE_BITS 12
-#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
-
 /* work queue */
 
 /* The union type allows passing of 64 bit target pointers on 32 bit
@@ -XXX,XX +XXX,XX @@ struct CPUState {
     CPUArchState *env_ptr;
     IcountDecr *icount_decr_ptr;
 
-    /* Accessed in parallel; all accesses must be atomic */
-    TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
+    CPUJumpCache *tb_jmp_cache;
 
     struct GDBRegisterState *gdb_regs;
     int gdb_num_regs;
@@ -XXX,XX +XXX,XX @@ extern CPUTailQ cpus;
 
 extern __thread CPUState *current_cpu;
 
-static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
-{
-    unsigned int i;
-
-    for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
-        qatomic_set(&cpu->tb_jmp_cache[i], NULL);
-    }
-}
-
 /**
  * qemu_tcg_mttcg_enabled:
  * Check whether we are running MultiThread TCG or not.
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct CoMutex CoMutex;
 typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
 typedef struct CPUAddressSpace CPUAddressSpace;
 typedef struct CPUArchState CPUArchState;
+typedef struct CPUJumpCache CPUJumpCache;
 typedef struct CPUState CPUState;
 typedef struct CPUTLBEntryFull CPUTLBEntryFull;
 typedef struct DeviceListener DeviceListener;
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -XXX,XX +XXX,XX @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
 {
 }
 
+void tcg_flush_jmp_cache(CPUState *cpu)
+{
+}
+
 int probe_access_flags(CPUArchState *env, target_ulong addr,
                        MMUAccessType access_type, int mmu_idx,
                        bool nonfault, void **phost, uintptr_t retaddr)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/replay.h"
 #include "sysemu/tcg.h"
 #include "exec/helper-proto.h"
+#include "tb-jmp-cache.h"
 #include "tb-hash.h"
 #include "tb-context.h"
 #include "internal.h"
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
     tcg_debug_assert(!(cflags & CF_INVALID));
 
     hash = tb_jmp_cache_hash_func(pc);
-    tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
+    tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
 
     if (likely(tb &&
                tb->pc == pc &&
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
     if (tb == NULL) {
         return NULL;
     }
-    qatomic_set(&cpu->tb_jmp_cache[hash], tb);
+    qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
     return tb;
 }
 
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
 
             tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
             if (tb == NULL) {
+                uint32_t h;
+
                 mmap_lock();
                 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
                 mmap_unlock();
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
                  * We add the TB in the virtual pc hash table
                  * for the fast lookup
                  */
-                qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
+                h = tb_jmp_cache_hash_func(pc);
+                qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
             }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
 
 static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
 {
-    unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
+    int i, i0 = tb_jmp_cache_hash_page(page_addr);
+    CPUJumpCache *jc = cpu->tb_jmp_cache;
 
     for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
-        qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
+        qatomic_set(&jc->array[i0 + i].tb, NULL);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
 
     qemu_spin_unlock(&env_tlb(env)->c.lock);
 
-    cpu_tb_jmp_cache_clear(cpu);
+    tcg_flush_jmp_cache(cpu);
 
     if (to_clean == ALL_MMUIDX_BITS) {
         qatomic_set(&env_tlb(env)->c.full_flush_count,
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
      * longer to clear each entry individually than it will to clear it all.
      */
     if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) {
-        cpu_tb_jmp_cache_clear(cpu);
+        tcg_flush_jmp_cache(cpu);
         return;
     }
 
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/tcg.h"
 #include "qapi/error.h"
 #include "hw/core/tcg-cpu-ops.h"
+#include "tb-jmp-cache.h"
 #include "tb-hash.h"
 #include "tb-context.h"
 #include "internal.h"
@@ -XXX,XX +XXX,XX @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
     }
 
     CPU_FOREACH(cpu) {
-        cpu_tb_jmp_cache_clear(cpu);
+        tcg_flush_jmp_cache(cpu);
     }
 
     qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
     /* remove the TB from the hash list */
     h = tb_jmp_cache_hash_func(tb->pc);
     CPU_FOREACH(cpu) {
-        if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) {
-            qatomic_set(&cpu->tb_jmp_cache[h], NULL);
+        CPUJumpCache *jc = cpu->tb_jmp_cache;
+        if (qatomic_read(&jc->array[h].tb) == tb) {
+            qatomic_set(&jc->array[h].tb, NULL);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ int page_unprotect(target_ulong address, uintptr_t pc)
 }
 #endif /* CONFIG_USER_ONLY */
 
+/*
+ * Called by generic code at e.g. cpu reset after cpu creation,
+ * therefore we must be prepared to allocate the jump cache.
+ */
+void tcg_flush_jmp_cache(CPUState *cpu)
+{
+    CPUJumpCache *jc = cpu->tb_jmp_cache;
+
+    if (likely(jc)) {
+        for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
+            qatomic_set(&jc->array[i].tb, NULL);
+        }
+    } else {
+        /* This should happen once during realize, and thus never race. */
+        jc = g_new0(CPUJumpCache, 1);
+        jc = qatomic_xchg(&cpu->tb_jmp_cache, jc);
+        assert(jc == NULL);
+    }
+}
+
 /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
 void tcg_flush_softmmu_tlb(CPUState *cs)
 {
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(DeviceState *dev)
     cpu->cflags_next_tb = -1;
 
     if (tcg_enabled()) {
-        cpu_tb_jmp_cache_clear(cpu);
-
+        tcg_flush_jmp_cache(cpu);
         tcg_flush_softmmu_tlb(cpu);
     }
 }
diff --git a/plugins/core.c b/plugins/core.c
index XXXXXXX..XXXXXXX 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -XXX,XX +XXX,XX @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id)
 static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data)
 {
     bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX);
-    cpu_tb_jmp_cache_clear(cpu);
+    tcg_flush_jmp_cache(cpu);
 }
 
 static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer udata)
diff --git a/trace/control-target.c b/trace/control-target.c
index XXXXXXX..XXXXXXX 100644
--- a/trace/control-target.c
+++ b/trace/control-target.c
@@ -XXX,XX +XXX,XX @@ static void trace_event_synchronize_vcpu_state_dynamic(
 {
     bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed,
                 CPU_TRACE_DSTATE_MAX_EVENTS);
-    cpu_tb_jmp_cache_clear(vcpu);
+    tcg_flush_jmp_cache(vcpu);
 }
 
 void trace_event_set_vcpu_state_dynamic(CPUState *vcpu,
-- 
2.34.1

Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core)
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core)
Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core)
Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs)
Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs)
Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
---
 include/hw/core/cpu.h   |  3 +++
 target/alpha/cpu.c      |  9 +++++++++
 target/arm/cpu.c        | 13 +++++++++++++
 target/avr/cpu.c        |  8 ++++++++
 target/cris/cpu.c       |  8 ++++++++
 target/hexagon/cpu.c    |  8 ++++++++
 target/hppa/cpu.c       |  8 ++++++++
 target/i386/cpu.c       |  9 +++++++++
 target/loongarch/cpu.c  |  9 +++++++++
 target/m68k/cpu.c       |  8 ++++++++
 target/microblaze/cpu.c |  8 ++++++++
 target/mips/cpu.c       |  8 ++++++++
 target/nios2/cpu.c      |  9 +++++++++
 target/openrisc/cpu.c   |  8 ++++++++
 target/ppc/cpu_init.c   |  8 ++++++++
 target/riscv/cpu.c      | 13 +++++++++++++
 target/rx/cpu.c         |  8 ++++++++
 target/s390x/cpu.c      |  8 ++++++++
 target/sh4/cpu.c        |  8 ++++++++
 target/sparc/cpu.c      |  8 ++++++++
 target/tricore/cpu.c    |  9 +++++++++
 target/xtensa/cpu.c     |  8 ++++++++
 22 files changed, 186 insertions(+)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
  *       If the target behaviour here is anything other than "set
  *       the PC register to the value passed in" then the target must
  *       also implement the synchronize_from_tb hook.
+ * @get_pc: Callback for getting the Program Counter register.
+ *       As above, with the semantics of the target architecture.
  * @gdb_read_register: Callback for letting GDB read a register.
  * @gdb_write_register: Callback for letting GDB write a register.
  * @gdb_adjust_breakpoint: Callback for adjusting the address of a
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
     void (*dump_state)(CPUState *cpu, FILE *, int flags);
     int64_t (*get_arch_id)(CPUState *cpu);
     void (*set_pc)(CPUState *cpu, vaddr value);
+    vaddr (*get_pc)(CPUState *cpu);
     int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
     vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr alpha_cpu_get_pc(CPUState *cs)
+{
+    AlphaCPU *cpu = ALPHA_CPU(cs);
+
+    return cpu->env.pc;
+}
+
+
 static bool alpha_cpu_has_work(CPUState *cs)
 {
     /* Here we are checking to see if the CPU should wake up from HALT.
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = alpha_cpu_has_work;
     cc->dump_state = alpha_cpu_dump_state;
     cc->set_pc = alpha_cpu_set_pc;
+    cc->get_pc = alpha_cpu_get_pc;
     cc->gdb_read_register = alpha_cpu_gdb_read_register;
     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
     }
 }
 
+static vaddr arm_cpu_get_pc(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    if (is_a64(env)) {
+        return env->pc;
+    } else {
+        return env->regs[15];
+    }
+}
+
 #ifdef CONFIG_TCG
 void arm_cpu_synchronize_from_tb(CPUState *cs,
                                  const TranslationBlock *tb)
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = arm_cpu_has_work;
     cc->dump_state = arm_cpu_dump_state;
     cc->set_pc = arm_cpu_set_pc;
+    cc->get_pc = arm_cpu_get_pc;
     cc->gdb_read_register = arm_cpu_gdb_read_register;
     cc->gdb_write_register = arm_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc_w = value / 2; /* internally PC points to words */
 }
 
+static vaddr avr_cpu_get_pc(CPUState *cs)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+
+    return cpu->env.pc_w * 2;
+}
+
 static bool avr_cpu_has_work(CPUState *cs)
 {
     AVRCPU *cpu = AVR_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = avr_cpu_has_work;
     cc->dump_state = avr_cpu_dump_state;
     cc->set_pc = avr_cpu_set_pc;
+    cc->get_pc = avr_cpu_get_pc;
     dc->vmsd = &vms_avr_cpu;
     cc->sysemu_ops = &avr_sysemu_ops;
     cc->disas_set_info = avr_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr cris_cpu_get_pc(CPUState *cs)
+{
+    CRISCPU *cpu = CRIS_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static bool cris_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = cris_cpu_has_work;
     cc->dump_state = cris_cpu_dump_state;
     cc->set_pc = cris_cpu_set_pc;
+    cc->get_pc = cris_cpu_get_pc;
     cc->gdb_read_register = cris_cpu_gdb_read_register;
     cc->gdb_write_register = cris_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
     env->gpr[HEX_REG_PC] = value;
 }
 
+static vaddr hexagon_cpu_get_pc(CPUState *cs)
+{
+    HexagonCPU *cpu = HEXAGON_CPU(cs);
+    CPUHexagonState *env = &cpu->env;
+    return env->gpr[HEX_REG_PC];
+}
+
 static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
                                             const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
     cc->has_work = hexagon_cpu_has_work;
     cc->dump_state = hexagon_dump_state;
     cc->set_pc = hexagon_cpu_set_pc;
+    cc->get_pc = hexagon_cpu_get_pc;
     cc->gdb_read_register = hexagon_gdb_read_register;
     cc->gdb_write_register = hexagon_gdb_write_register;
     cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.iaoq_b = value + 4;
 }
 
+static vaddr hppa_cpu_get_pc(CPUState *cs)
+{
+    HPPACPU *cpu = HPPA_CPU(cs);
+
+    return cpu->env.iaoq_f;
+}
+
 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
                                          const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = hppa_cpu_has_work;
     cc->dump_state = hppa_cpu_dump_state;
     cc->set_pc = hppa_cpu_set_pc;
+    cc->get_pc = hppa_cpu_get_pc;
     cc->gdb_read_register = hppa_cpu_gdb_read_register;
     cc->gdb_write_register = hppa_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.eip = value;
 }
 
+static vaddr x86_cpu_get_pc(CPUState *cs)
+{
+    X86CPU *cpu = X86_CPU(cs);
+
+    /* Match cpu_get_tb_cpu_state. */
+    return cpu->env.eip + cpu->env.segs[R_CS].base;
+}
+
 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
 {
     X86CPU *cpu = X86_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     cc->has_work = x86_cpu_has_work;
     cc->dump_state = x86_cpu_dump_state;
     cc->set_pc = x86_cpu_set_pc;
+    cc->get_pc = x86_cpu_get_pc;
     cc->gdb_read_register = x86_cpu_gdb_read_register;
     cc->gdb_write_register = x86_cpu_gdb_write_register;
     cc->get_arch_id = x86_cpu_get_arch_id;
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
     env->pc = value;
 }
 
+static vaddr loongarch_cpu_get_pc(CPUState *cs)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    CPULoongArchState *env = &cpu->env;
+
+    return env->pc;
+}
+
 #ifndef CONFIG_USER_ONLY
 #include "hw/loongarch/virt.h"
 
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
     cc->has_work = loongarch_cpu_has_work;
     cc->dump_state = loongarch_cpu_dump_state;
     cc->set_pc = loongarch_cpu_set_pc;
+    cc->get_pc = loongarch_cpu_get_pc;
 #ifndef CONFIG_USER_ONLY
     dc->vmsd = &vmstate_loongarch_cpu;
     cc->sysemu_ops = &loongarch_sysemu_ops;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr m68k_cpu_get_pc(CPUState *cs)
+{
+    M68kCPU *cpu = M68K_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static bool m68k_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     cc->has_work = m68k_cpu_has_work;
     cc->dump_state = m68k_cpu_dump_state;
     cc->set_pc = m68k_cpu_set_pc;
+    cc->get_pc = m68k_cpu_get_pc;
     cc->gdb_read_register = m68k_cpu_gdb_read_register;
     cc->gdb_write_register = m68k_cpu_gdb_write_register;
 #if defined(CONFIG_SOFTMMU)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.iflags = 0;
 }
 
+static vaddr mb_cpu_get_pc(CPUState *cs)
+{
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static void mb_cpu_synchronize_from_tb(CPUState *cs,
                                        const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->dump_state = mb_cpu_dump_state;
     cc->set_pc = mb_cpu_set_pc;
+    cc->get_pc = mb_cpu_get_pc;
     cc->gdb_read_register = mb_cpu_gdb_read_register;
     cc->gdb_write_register = mb_cpu_gdb_write_register;
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
     mips_env_set_pc(&cpu->env, value);
 }
 
+static vaddr mips_cpu_get_pc(CPUState *cs)
+{
+    MIPSCPU *cpu = MIPS_CPU(cs);
+
+    return cpu->env.active_tc.PC;
+}
+
 static bool mips_cpu_has_work(CPUState *cs)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
     cc->has_work = mips_cpu_has_work;
     cc->dump_state = mips_cpu_dump_state;
     cc->set_pc = mips_cpu_set_pc;
+    cc->get_pc = mips_cpu_get_pc;
     cc->gdb_read_register = mips_cpu_gdb_read_register;
     cc->gdb_write_register = mips_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
     env->pc = value;
 }
 
+static vaddr nios2_cpu_get_pc(CPUState *cs)
+{
+    Nios2CPU *cpu = NIOS2_CPU(cs);
+    CPUNios2State *env = &cpu->env;
+
+    return env->pc;
+}
+
 static bool nios2_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = nios2_cpu_has_work;
     cc->dump_state = nios2_cpu_dump_state;
     cc->set_pc = nios2_cpu_set_pc;
+    cc->get_pc = nios2_cpu_get_pc;
     cc->disas_set_info = nios2_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
     cc->sysemu_ops = &nios2_sysemu_ops;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.dflag = 0;
 }
 
+static vaddr openrisc_cpu_get_pc(CPUState *cs)
+{
+    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
                                              const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = openrisc_cpu_has_work;
     cc->dump_state = openrisc_cpu_dump_state;
     cc->set_pc = openrisc_cpu_set_pc;
+    cc->get_pc = openrisc_cpu_get_pc;
     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.nip = value;
 }
 
+static vaddr ppc_cpu_get_pc(CPUState *cs)
+{
+    PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+    return cpu->env.nip;
+}
+
 static bool ppc_cpu_has_work(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = ppc_cpu_has_work;
     cc->dump_state = ppc_cpu_dump_state;
     cc->set_pc = ppc_cpu_set_pc;
+    cc->get_pc = ppc_cpu_get_pc;
     cc->gdb_read_register = ppc_cpu_gdb_read_register;
     cc->gdb_write_register = ppc_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
     }
 }
 
+static vaddr riscv_cpu_get_pc(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    /* Match cpu_get_tb_cpu_state. */
+    if (env->xl == MXL_RV32) {
+        return env->pc & UINT32_MAX;
+    }
+    return env->pc;
+}
+
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->has_work = riscv_cpu_has_work;
     cc->dump_state = riscv_cpu_dump_state;
     cc->set_pc = riscv_cpu_set_pc;
+    cc->get_pc = riscv_cpu_get_pc;
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
     cc->gdb_write_register = riscv_cpu_gdb_write_register;
     cc->gdb_num_core_regs = 33;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr rx_cpu_get_pc(CPUState *cs)
+{
+    RXCPU *cpu = RX_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static void rx_cpu_synchronize_from_tb(CPUState *cs,
                                        const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
     cc->has_work = rx_cpu_has_work;
     cc->dump_state = rx_cpu_dump_state;
     cc->set_pc = rx_cpu_set_pc;
+    cc->get_pc = rx_cpu_get_pc;
 
 #ifndef CONFIG_USER_ONLY
     cc->sysemu_ops = &rx_sysemu_ops;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.psw.addr = value;
 }
 
+static vaddr s390_cpu_get_pc(CPUState *cs)
+{
+    S390CPU *cpu = S390_CPU(cs);
+
+    return cpu->env.psw.addr;
+}
+
 static bool s390_cpu_has_work(CPUState *cs)
 {
     S390CPU *cpu = S390_CPU(cs);
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = s390_cpu_has_work;
     cc->dump_state = s390_cpu_dump_state;
     cc->set_pc = s390_cpu_set_pc;
+    cc->get_pc = s390_cpu_get_pc;
     cc->gdb_read_register = s390_cpu_gdb_read_register;
     cc->gdb_write_register = s390_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr superh_cpu_get_pc(CPUState *cs)
+{
+    SuperHCPU *cpu = SUPERH_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static void superh_cpu_synchronize_from_tb(CPUState *cs,
                                            const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = superh_cpu_has_work;
     cc->dump_state = superh_cpu_dump_state;
     cc->set_pc = superh_cpu_set_pc;
+    cc->get_pc = superh_cpu_get_pc;
     cc->gdb_read_register = superh_cpu_gdb_read_register;
     cc->gdb_write_register = superh_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.npc = value + 4;
 }
 
+static vaddr sparc_cpu_get_pc(CPUState *cs)
+{
+    SPARCCPU *cpu = SPARC_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
 #endif
     cc->set_pc = sparc_cpu_set_pc;
+    cc->get_pc = sparc_cpu_get_pc;
     cc->gdb_read_register = sparc_cpu_gdb_read_register;
     cc->gdb_write_register = sparc_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
     env->PC = value & ~(target_ulong)1;
 }
 
+static vaddr tricore_cpu_get_pc(CPUState *cs)
+{
+    TriCoreCPU *cpu = TRICORE_CPU(cs);
+    CPUTriCoreState *env = &cpu->env;
+
+    return env->PC;
+}
+
 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
                                             const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
 
     cc->dump_state = tricore_cpu_dump_state;
     cc->set_pc = tricore_cpu_set_pc;
+    cc->get_pc = tricore_cpu_get_pc;
     cc->sysemu_ops = &tricore_sysemu_ops;
     cc->tcg_ops = &tricore_tcg_ops;
 }
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
+static vaddr xtensa_cpu_get_pc(CPUState *cs)
+{
+    XtensaCPU *cpu = XTENSA_CPU(cs);
+
+    return cpu->env.pc;
+}
+
 static bool xtensa_cpu_has_work(CPUState *cs)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
     cc->has_work = xtensa_cpu_has_work;
     cc->dump_state = xtensa_cpu_dump_state;
     cc->set_pc = xtensa_cpu_set_pc;
+    cc->get_pc = xtensa_cpu_get_pc;
     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
     cc->gdb_write_register = xtensa_cpu_gdb_write_register;
     cc->gdb_stop_before_watchpoint = true;
-- 
2.34.1

The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.

Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.

diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/internal.h
+++ b/accel/tcg/internal.h
@@ -XXX,XX +XXX,XX @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
 void page_init(void);
 void tb_htable_init(void);
 
+/* Return the current PC from CPU, which may be cached in TB. */
+static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
+{
+    return tb_pc(tb);
+}
+
 #endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
     uintptr_t jmp_dest[2];
 };
 
+/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
+static inline target_ulong tb_pc(const TranslationBlock *tb)
+{
+    return tb->pc;
+}
+
 /* Hide the qatomic_read to make code a little easier on the eyes */
 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 {
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_register_thread(void);
 void tcg_prologue_init(TCGContext *s);
 void tcg_func_start(TCGContext *s);
 
-int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
+int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start);
 
 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
     const TranslationBlock *tb = p;
     const struct tb_desc *desc = d;
 
-    if (tb->pc == desc->pc &&
+    if (tb_pc(tb) == desc->pc &&
         tb->page_addr[0] == desc->page_addr0 &&
         tb->cs_base == desc->cs_base &&
         tb->flags == desc->flags &&
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
     return tb;
 }
 
-static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
-                                const TranslationBlock *tb)
+static void log_cpu_exec(target_ulong pc, CPUState *cpu,
+                         const TranslationBlock *tb)
 {
-    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))
-        && qemu_log_in_addr_range(pc)) {
-
+    if (qemu_log_in_addr_range(pc)) {
         qemu_log_mask(CPU_LOG_EXEC,
                       "Trace %d: %p [" TARGET_FMT_lx
                       "/" TARGET_FMT_lx "/%08x/%08x] %s\n",
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
         return tcg_code_gen_epilogue;
     }
 
-    log_cpu_exec(pc, cpu, tb);
+    if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
+        log_cpu_exec(pc, cpu, tb);
+    }
 
     return tb->tc.ptr;
 }
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
     TranslationBlock *last_tb;
     const void *tb_ptr = itb->tc.ptr;
 
-    log_cpu_exec(itb->pc, cpu, itb);
+    if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
+        log_cpu_exec(log_pc(cpu, itb), cpu, itb);
+    }
 
     qemu_thread_jit_execute();
     ret = tcg_qemu_tb_exec(env, tb_ptr);
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
          * of the start of the TB.
          */
         CPUClass *cc = CPU_GET_CLASS(cpu);
-        qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
-                               "Stopped execution of TB chain before %p ["
-                               TARGET_FMT_lx "] %s\n",
-                               last_tb->tc.ptr, last_tb->pc,
-                               lookup_symbol(last_tb->pc));
+
         if (cc->tcg_ops->synchronize_from_tb) {
             cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
         } else {
             assert(cc->set_pc);
-            cc->set_pc(cpu, last_tb->pc);
+            cc->set_pc(cpu, tb_pc(last_tb));
+        }
+        if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+            target_ulong pc = log_pc(cpu, last_tb);
+            if (qemu_log_in_addr_range(pc)) {
+                qemu_log("Stopped execution of TB chain before %p ["
+                         TARGET_FMT_lx "] %s\n",
+                         last_tb->tc.ptr, pc, lookup_symbol(pc));
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
 
     qemu_spin_unlock(&tb_next->jmp_lock);
 
-    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
-                           "Linking TBs %p [" TARGET_FMT_lx
-                           "] index %d -> %p [" TARGET_FMT_lx "]\n",
-                           tb->tc.ptr, tb->pc, n,
-                           tb_next->tc.ptr, tb_next->pc);
+    qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n",
+                  tb->tc.ptr, n, tb_next->tc.ptr);
     return;
 
  out_unlock_next:
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
 }
 
 static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
+                                    target_ulong pc,
                                     TranslationBlock **last_tb, int *tb_exit)
 {
     int32_t insns_left;
 
-    trace_exec_tb(tb, tb->pc);
+    trace_exec_tb(tb, pc);
     tb = cpu_tb_exec(cpu, tb, tb_exit);
     if (*tb_exit != TB_EXIT_REQUESTED) {
         *last_tb = tb;
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
                 tb_add_jump(last_tb, tb_exit, tb);
             }
 
-            cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
+            cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit);
 
             /* Try to align the host and virtual clocks
                if the guest is in advance */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
 
         for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
             if (i == 0) {
-                prev = (j == 0 ? tb->pc : 0);
+                prev = (j == 0 ? tb_pc(tb) : 0);
             } else {
                 prev = tcg_ctx->gen_insn_data[i - 1][j];
             }
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
 static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
                                      uintptr_t searched_pc, bool reset_icount)
 {
-    target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc };
+    target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
     uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
     CPUArchState *env = cpu->env_ptr;
     const uint8_t *p = tb->tc.ptr + tb->tc.size;
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
     const TranslationBlock *a = ap;
     const TranslationBlock *b = bp;
 
-    return a->pc == b->pc &&
+    return tb_pc(a) == tb_pc(b) &&
         a->cs_base == b->cs_base &&
         a->flags == b->flags &&
         (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
@@ -XXX,XX +XXX,XX @@ static void do_tb_invalidate_check(void *p, uint32_t hash, void *userp)
     TranslationBlock *tb = p;
     target_ulong addr = *(target_ulong *)userp;
 
-    if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) {
+    if (!(addr + TARGET_PAGE_SIZE <= tb_pc(tb) ||
+          addr >= tb_pc(tb) + tb->size)) {
         printf("ERROR invalidate: address=" TARGET_FMT_lx
-               " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size);
+               " PC=%08lx size=%04x\n", addr, (long)tb_pc(tb), tb->size);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_tb_page_check(void *p, uint32_t hash, void *userp)
     TranslationBlock *tb = p;
     int flags1, flags2;
 
-    flags1 = page_get_flags(tb->pc);
-    flags2 = page_get_flags(tb->pc + tb->size - 1);
+    flags1 = page_get_flags(tb_pc(tb));
+    flags2 = page_get_flags(tb_pc(tb) + tb->size - 1);
     if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
         printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
-               (long)tb->pc, tb->size, flags1, flags2);
+               (long)tb_pc(tb), tb->size, flags1, flags2);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
 
     /* remove the TB from the hash list */
     phys_pc = tb->page_addr[0];
-    h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
+    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
                      tb->trace_vcpu_dstate);
     if (!qht_remove(&tb_ctx.htable, tb, h)) {
         return;
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
     }
 
     /* add in the hash table */
-    h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,
+    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
                      tb->trace_vcpu_dstate);
     qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
 
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     tcg_ctx->cpu = NULL;
     max_insns = tb->icount;
 
-    trace_translate_block(tb, tb->pc, tb->tc.ptr);
+    trace_translate_block(tb, pc, tb->tc.ptr);
 
     /* generate machine code */
     tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     ti = profile_getclock();
 #endif
 
-    gen_code_size = tcg_gen_code(tcg_ctx, tb);
+    gen_code_size = tcg_gen_code(tcg_ctx, tb, pc);
     if (unlikely(gen_code_size < 0)) {
  error_return:
         switch (gen_code_size) {
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
-        qemu_log_in_addr_range(tb->pc)) {
+        qemu_log_in_addr_range(pc)) {
         FILE *logfile = qemu_log_trylock();
         if (logfile) {
             int code_size, data_size;
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
      */
     cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n;
 
-    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
-                           "cpu_io_recompile: rewound execution of TB to "
-                           TARGET_FMT_lx "\n", tb->pc);
+    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+        target_ulong pc = log_pc(cpu, tb);
+        if (qemu_log_in_addr_range(pc)) {
+            qemu_log("cpu_io_recompile: rewound execution of TB to "
+                     TARGET_FMT_lx "\n", pc);
+        }
+    }
 
     cpu_loop_exit_noexc(cpu);
 }
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
      * never possible for an AArch64 TB to chain to an AArch32 TB.
      */
     if (is_a64(env)) {
-        env->pc = tb->pc;
+        env->pc = tb_pc(tb);
     } else {
-        env->regs[15] = tb->pc;
+        env->regs[15] = tb_pc(tb);
     }
 }
 #endif /* CONFIG_TCG */
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_synchronize_from_tb(CPUState *cs,
     AVRCPU *cpu = AVR_CPU(cs);
     CPUAVRState *env = &cpu->env;
 
-    env->pc_w = tb->pc / 2; /* internally PC points to words */
+    env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
 }
 
 static void avr_cpu_reset(DeviceState *ds)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
 {
     HexagonCPU *cpu = HEXAGON_CPU(cs);
     CPUHexagonState *env = &cpu->env;
-    env->gpr[HEX_REG_PC] = tb->pc;
+    env->gpr[HEX_REG_PC] = tb_pc(tb);
 }
 
 static bool hexagon_cpu_has_work(CPUState *cs)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
     HPPACPU *cpu = HPPA_CPU(cs);
 
 #ifdef CONFIG_USER_ONLY
-    cpu->env.iaoq_f = tb->pc;
+    cpu->env.iaoq_f = tb_pc(tb);
     cpu->env.iaoq_b = tb->cs_base;
 #else
     /* Recover the IAOQ values from the GVA + PRIV.  */
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
     int32_t diff = cs_base;
 
     cpu->env.iasq_f = iasq_f;
-    cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
+    cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
     if (diff) {
         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
     }
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
 {
     X86CPU *cpu = X86_CPU(cs);
 
-    cpu->env.eip = tb->pc - tb->cs_base;
+    cpu->env.eip = tb_pc(tb) - tb->cs_base;
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     CPULoongArchState *env = &cpu->env;
 
-    env->pc = tb->pc;
+    env->pc = tb_pc(tb);
 }
 #endif /* CONFIG_TCG */
 
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 
-    cpu->env.pc = tb->pc;
+    cpu->env.pc = tb_pc(tb);
     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
 }
 
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -XXX,XX +XXX,XX @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
     MIPSCPU *cpu = MIPS_CPU(cs);
     CPUMIPSState *env = &cpu->env;
 
-    env->active_tc.PC = tb->pc;
+    env->active_tc.PC = tb_pc(tb);
     env->hflags &= ~MIPS_HFLAG_BMASK;
     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 }
diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -XXX,XX +XXX,XX @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
     CPUMIPSState *env = &cpu->env;
 
     if ((env->hflags & MIPS_HFLAG_BMASK) != 0
-        && env->active_tc.PC != tb->pc) {
+        && env->active_tc.PC != tb_pc(tb)) {
         env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
         env->hflags &= ~MIPS_HFLAG_BMASK;
         return true;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
 {
     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 
-    cpu->env.pc = tb->pc;
+    cpu->env.pc = tb_pc(tb);
 }
 
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 
     if (xl == MXL_RV32) {
-        env->pc = (int32_t)tb->pc;
+        env->pc = (int32_t)tb_pc(tb);
     } else {
-        env->pc = tb->pc;
+        env->pc = tb_pc(tb);
     }
 }
 
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
 {
     RXCPU *cpu = RX_CPU(cs);
 
-    cpu->env.pc = tb->pc;
+    cpu->env.pc = tb_pc(tb);
 }
 
 static bool rx_cpu_has_work(CPUState *cs)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
 {
     SuperHCPU *cpu = SUPERH_CPU(cs);
 
-    cpu->env.pc = tb->pc;
+    cpu->env.pc = tb_pc(tb);
     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
     CPUSH4State *env = &cpu->env;
 
     if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
-        && env->pc != tb->pc) {
+        && env->pc != tb_pc(tb)) {
         env->pc -= 2;
         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
         return true;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
 {
     SPARCCPU *cpu = SPARC_CPU(cs);
 
-    cpu->env.pc = tb->pc;
+    cpu->env.pc = tb_pc(tb);
     cpu->env.npc = tb->cs_base;
 }
 
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs,
     TriCoreCPU *cpu = TRICORE_CPU(cs);
     CPUTriCoreState *env = &cpu->env;
 
-    env->PC = tb->pc;
+    env->PC = tb_pc(tb);
 }
 
 static void tricore_cpu_reset(DeviceState *dev)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void)
 #endif
 
 
-int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
+int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start)
 {
 #ifdef CONFIG_PROFILER
     TCGProfile *prof = &s->prof;
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
 
 #ifdef DEBUG_DISAS
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
-                 && qemu_log_in_addr_range(tb->pc))) {
+                 && qemu_log_in_addr_range(pc_start))) {
         FILE *logfile = qemu_log_trylock();
         if (logfile) {
             fprintf(logfile, "OP:\n");
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
     if (s->nb_indirects > 0) {
 #ifdef DEBUG_DISAS
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
-                     && qemu_log_in_addr_range(tb->pc))) {
+                     && qemu_log_in_addr_range(pc_start))) {
             FILE *logfile = qemu_log_trylock();
             if (logfile) {
                 fprintf(logfile, "OP before indirect lowering:\n");
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
 
 #ifdef DEBUG_DISAS
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
-                 && qemu_log_in_addr_range(tb->pc))) {
+                 && qemu_log_in_addr_range(pc_start))) {
         FILE *logfile = qemu_log_trylock();
         if (logfile) {
             fprintf(logfile, "OP after optimization and liveness analysis:\n");
-- 
2.34.1

Prepare for targets to be able to produce TBs that can
run in more than one virtual context.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/internal.h      |  4 +++
 accel/tcg/tb-jmp-cache.h  | 41 +++++++++++++++++++++++++
 include/exec/cpu-defs.h   |  3 ++
 include/exec/exec-all.h   | 32 ++++++++++++++++++--
 accel/tcg/cpu-exec.c      | 16 ++++++----
 accel/tcg/translate-all.c | 64 ++++++++++++++++++++++++++-------------
 6 files changed, 131 insertions(+), 29 deletions(-)

diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/internal.h
+++ b/accel/tcg/internal.h
@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void);
 /* Return the current PC from CPU, which may be cached in TB. */
 static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
 {
+#if TARGET_TB_PCREL
+    return cpu->cc->get_pc(cpu);
+#else
     return tb_pc(tb);
+#endif
 }
 
 #endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tb-jmp-cache.h
+++ b/accel/tcg/tb-jmp-cache.h
@@ -XXX,XX +XXX,XX @@
 
 /*
  * Accessed in parallel; all accesses to 'tb' must be atomic.
+ * For TARGET_TB_PCREL, accesses to 'pc' must be protected by
+ * a load_acquire/store_release to 'tb'.
  */
 struct CPUJumpCache {
     struct {
         TranslationBlock *tb;
+#if TARGET_TB_PCREL
+        target_ulong pc;
+#endif
     } array[TB_JMP_CACHE_SIZE];
 };
 
+static inline TranslationBlock *
+tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash)
+{
+#if TARGET_TB_PCREL
+    /* Use acquire to ensure current load of pc from jc. */
+    return qatomic_load_acquire(&jc->array[hash].tb);
+#else
+    /* Use rcu_read to ensure current load of pc from *tb. */
+    return qatomic_rcu_read(&jc->array[hash].tb);
+#endif
+}
+
+static inline target_ulong
+tb_jmp_cache_get_pc(CPUJumpCache *jc, uint32_t hash, TranslationBlock *tb)
+{
+#if TARGET_TB_PCREL
+    return jc->array[hash].pc;
+#else
+    return tb_pc(tb);
+#endif
+}
+
+static inline void
+tb_jmp_cache_set(CPUJumpCache *jc, uint32_t hash,
+                 TranslationBlock *tb, target_ulong pc)
+{
+#if TARGET_TB_PCREL
+    jc->array[hash].pc = pc;
+    /* Use store_release on tb to ensure pc is written first. */
+    qatomic_store_release(&jc->array[hash].tb, tb);
+#else
+    /* Use the pc value already stored in tb->pc. */
+    qatomic_set(&jc->array[hash].tb, tb);
+#endif
+}
+
 #endif /* ACCEL_TCG_TB_JMP_CACHE_H */
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -XXX,XX +XXX,XX @@
 #  error TARGET_PAGE_BITS must be defined in cpu-param.h
 # endif
 #endif
+#ifndef TARGET_TB_PCREL
+# define TARGET_TB_PCREL 0
+#endif
 
 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
 
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ struct tb_tc {
 };
 
 struct TranslationBlock {
-    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
-    target_ulong cs_base; /* CS base for this block */
+#if !TARGET_TB_PCREL
+    /*
+     * Guest PC corresponding to this block.  This must be the true
+     * virtual address.  Therefore e.g. x86 stores EIP + CS_BASE, and
+     * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
+     * privilege, must store those bits elsewhere.
+     *
+     * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
+     * written such that the TB is associated only with the physical
+     * page and may be run in any virtual address context.  In this case,
+     * PC must always be taken from ENV in a target-specific manner.
+     * Unwind information is taken as offsets from the page, to be
+     * deposited into the "current" PC.
+     */
+    target_ulong pc;
+#endif
+
+    /*
+     * Target-specific data associated with the TranslationBlock, e.g.:
+     * x86: the original user, the Code Segment virtual base,
+     * arm: an extension of tb->flags,
+     * s390x: instruction data for EXECUTE,
+     * sparc: the next pc of the instruction queue (for delay slots).
+     */
+    target_ulong cs_base;
+
     uint32_t flags; /* flags defining in which context the code was generated */
     uint32_t cflags;    /* compile flags */
 
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
 /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
 static inline target_ulong tb_pc(const TranslationBlock *tb)
 {
+#if TARGET_TB_PCREL
+    qemu_build_not_reached();
+#else
     return tb->pc;
+#endif
 }
 
 /* Hide the qatomic_read to make code a little easier on the eyes */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
     const TranslationBlock *tb = p;
     const struct tb_desc *desc = d;
 
-    if (tb_pc(tb) == desc->pc &&
+    if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) &&
         tb->page_addr[0] == desc->page_addr0 &&
         tb->cs_base == desc->cs_base &&
         tb->flags == desc->flags &&
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
         return NULL;
     }
     desc.page_addr0 = phys_pc;
-    h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
+    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc),
+                     flags, cflags, *cpu->trace_dstate);
     return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
                                           uint32_t flags, uint32_t cflags)
 {
     TranslationBlock *tb;
+    CPUJumpCache *jc;
     uint32_t hash;
 
     /* we should never be trying to look up an INVALID tb */
     tcg_debug_assert(!(cflags & CF_INVALID));
 
     hash = tb_jmp_cache_hash_func(pc);
-    tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
+    jc = cpu->tb_jmp_cache;
+    tb = tb_jmp_cache_get_tb(jc, hash);
 
     if (likely(tb &&
-               tb->pc == pc &&
+               tb_jmp_cache_get_pc(jc, hash, tb) == pc &&
                tb->cs_base == cs_base &&
                tb->flags == flags &&
                tb->trace_vcpu_dstate == *cpu->trace_dstate &&
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
     if (tb == NULL) {
         return NULL;
     }
-    qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
+    tb_jmp_cache_set(jc, hash, tb, pc);
     return tb;
 }
 
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
         if (cc->tcg_ops->synchronize_from_tb) {
             cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
         } else {
+            assert(!TARGET_TB_PCREL);
             assert(cc->set_pc);
             cc->set_pc(cpu, tb_pc(last_tb));
         }
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
                  * for the fast lookup
                  */
                 h = tb_jmp_cache_hash_func(pc);
-                qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
+                tb_jmp_cache_set(cpu->tb_jmp_cache, h, tb, pc);
             }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
 
         for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
             if (i == 0) {
-                prev = (j == 0 ? tb_pc(tb) : 0);
+                prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0);
             } else {
                 prev = tcg_ctx->gen_insn_data[i - 1][j];
             }
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
 static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
                                      uintptr_t searched_pc, bool reset_icount)
 {
-    target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
+    target_ulong data[TARGET_INSN_START_WORDS];
     uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
     CPUArchState *env = cpu->env_ptr;
     const uint8_t *p = tb->tc.ptr + tb->tc.size;
@@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
         return -1;
     }
 
+    memset(data, 0, sizeof(data));
+    if (!TARGET_TB_PCREL) {
+        data[0] = tb_pc(tb);
+    }
+
     /* Reconstruct the stored insn data while looking for the point at
        which the end of the insn exceeds the searched_pc.  */
     for (i = 0; i < num_insns; ++i) {
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
     const TranslationBlock *a = ap;
     const TranslationBlock *b = bp;
 
-    return tb_pc(a) == tb_pc(b) &&
-        a->cs_base == b->cs_base &&
-        a->flags == b->flags &&
-        (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
-        a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
-        a->page_addr[0] == b->page_addr[0] &&
-        a->page_addr[1] == b->page_addr[1];
+    return ((TARGET_TB_PCREL || tb_pc(a) == tb_pc(b)) &&
+            a->cs_base == b->cs_base &&
+            a->flags == b->flags &&
+            (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
+            a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
+            a->page_addr[0] == b->page_addr[0] &&
+            a->page_addr[1] == b->page_addr[1]);
 }
 
 void tb_htable_init(void)
@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
     qemu_spin_unlock(&dest->jmp_lock);
 }
 
+static void tb_jmp_cache_inval_tb(TranslationBlock *tb)
+{
+    CPUState *cpu;
+
+    if (TARGET_TB_PCREL) {
+        /* A TB may be at any virtual address */
+        CPU_FOREACH(cpu) {
+            tcg_flush_jmp_cache(cpu);
+        }
+    } else {
+        uint32_t h = tb_jmp_cache_hash_func(tb_pc(tb));
+
+        CPU_FOREACH(cpu) {
+            CPUJumpCache *jc = cpu->tb_jmp_cache;
+
+            if (qatomic_read(&jc->array[h].tb) == tb) {
+                qatomic_set(&jc->array[h].tb, NULL);
+            }
+        }
+    }
+}
+
 /*
  * In user-mode, call with mmap_lock held.
  * In !user-mode, if @rm_from_page_list is set, call with the TB's pages'
@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
  */
 static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
 {
-    CPUState *cpu;
     PageDesc *p;
     uint32_t h;
     tb_page_addr_t phys_pc;
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
 
     /* remove the TB from the hash list */
     phys_pc = tb->page_addr[0];
-    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
-                     tb->trace_vcpu_dstate);
+    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
+                     tb->flags, orig_cflags, tb->trace_vcpu_dstate);
     if (!qht_remove(&tb_ctx.htable, tb, h)) {
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
     }
 
     /* remove the TB from the hash list */
-    h = tb_jmp_cache_hash_func(tb->pc);
-    CPU_FOREACH(cpu) {
-        CPUJumpCache *jc = cpu->tb_jmp_cache;
-        if (qatomic_read(&jc->array[h].tb) == tb) {
-            qatomic_set(&jc->array[h].tb, NULL);
-        }
-    }
+    tb_jmp_cache_inval_tb(tb);
 
     /* suppress this TB from the two jump lists */
     tb_remove_from_jmp_list(tb, 0);
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
     }
 
     /* add in the hash table */
-    h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
-                     tb->trace_vcpu_dstate);
+    h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
+                     tb->flags, tb->cflags, tb->trace_vcpu_dstate);
     qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
 
     /* remove TB from the page(s) if we couldn't insert it */
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 
     gen_code_buf = tcg_ctx->code_gen_ptr;
     tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
+#if !TARGET_TB_PCREL
     tb->pc = pc;
+#endif
     tb->cs_base = cs_base;
     tb->flags = flags;
     tb->cflags = cflags;
-- 
2.34.1

From: Leandro Lupori <leandro.lupori@eldorado.org.br>

PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.

However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
[rth: Expanded some commentary.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++----------
 1 file changed, 88 insertions(+), 31 deletions(-)

diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
     tcg_out32(s, insn);
 }
 
+static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
+{
+    if (HOST_BIG_ENDIAN) {
+        return (uint64_t)i1 << 32 | i2;
+    }
+    return (uint64_t)i2 << 32 | i1;
+}
+
+static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
+                                  tcg_insn_unit i0, tcg_insn_unit i1)
+{
+#if TCG_TARGET_REG_BITS == 64
+    qatomic_set((uint64_t *)rw, make_pair(i0, i1));
+    flush_idcache_range(rx, rw, 8);
+#else
+    qemu_build_not_reached();
+#endif
+}
+
+static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
+                                  tcg_insn_unit i0, tcg_insn_unit i1,
+                                  tcg_insn_unit i2, tcg_insn_unit i3)
+{
+    uint64_t p[2];
+
+    p[!HOST_BIG_ENDIAN] = make_pair(i0, i1);
+    p[HOST_BIG_ENDIAN] = make_pair(i2, i3);
+
+    /*
+     * There's no convenient way to get the compiler to allocate a pair
+     * of registers at an even index, so copy into r6/r7 and clobber.
+     */
+    asm("mr  %%r6, %1\n\t"
+        "mr  %%r7, %2\n\t"
+        "stq %%r6, %0"
+        : "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
+    flush_idcache_range(rx, rw, 16);
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
                               uintptr_t jmp_rw, uintptr_t addr)
 {
-    if (TCG_TARGET_REG_BITS == 64) {
-        tcg_insn_unit i1, i2;
-        intptr_t tb_diff = addr - tc_ptr;
-        intptr_t br_diff = addr - (jmp_rx + 4);
-        uint64_t pair;
+    tcg_insn_unit i0, i1, i2, i3;
+    intptr_t tb_diff = addr - tc_ptr;
+    intptr_t br_diff = addr - (jmp_rx + 4);
+    intptr_t lo, hi;
 
-        /* This does not exercise the range of the branch, but we do
-           still need to be able to load the new value of TCG_REG_TB.
-           But this does still happen quite often.  */
-        if (tb_diff == (int16_t)tb_diff) {
-            i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
-            i2 = B | (br_diff & 0x3fffffc);
-        } else {
-            intptr_t lo = (int16_t)tb_diff;
-            intptr_t hi = (int32_t)(tb_diff - lo);
-            assert(tb_diff == hi + lo);
-            i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
-            i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
-        }
-#if HOST_BIG_ENDIAN
-        pair = (uint64_t)i1 << 32 | i2;
-#else
-        pair = (uint64_t)i2 << 32 | i1;
-#endif
-
-        /* As per the enclosing if, this is ppc64.  Avoid the _Static_assert
-           within qatomic_set that would fail to build a ppc32 host.  */
-        qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
-        flush_idcache_range(jmp_rx, jmp_rw, 8);
-    } else {
+    if (TCG_TARGET_REG_BITS == 32) {
         intptr_t diff = addr - jmp_rx;
         tcg_debug_assert(in_range_b(diff));
         qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
         flush_idcache_range(jmp_rx, jmp_rw, 4);
+        return;
     }
+
+    /*
+     * For 16-bit displacements, we can use a single add + branch.
+     * This happens quite often.
+     */
+    if (tb_diff == (int16_t)tb_diff) {
+        i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
+        i1 = B | (br_diff & 0x3fffffc);
+        ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+        return;
+    }
+
+    lo = (int16_t)tb_diff;
+    hi = (int32_t)(tb_diff - lo);
+    assert(tb_diff == hi + lo);
+    i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
+    i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
+
+    /*
+     * Without stq from 2.07, we can only update two insns,
+     * and those must be the ones that load the target address.
+     */
+    if (!have_isa_2_07) {
+        ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+        return;
+    }
+
+    /*
+     * For 26-bit displacements, we can use a direct branch.
+     * Otherwise we still need the indirect branch, which we
+     * must restore after a potential direct branch write.
+     */
+    br_diff -= 4;
+    if (in_range_b(br_diff)) {
+        i2 = B | (br_diff & 0x3fffffc);
+        i3 = NOP;
+    } else {
+        i2 = MTSPR | RS(TCG_REG_TB) | CTR;
+        i3 = BCCTR | BO_ALWAYS;
+    }
+    ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
 }
 
 static void tcg_out_call_int(TCGContext *s, int lk,
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         if (s->tb_jmp_insn_offset) {
             /* Direct jump. */
             if (TCG_TARGET_REG_BITS == 64) {
-                /* Ensure the next insns are 8-byte aligned. */
-                if ((uintptr_t)s->code_ptr & 7) {
+                /* Ensure the next insns are 8 or 16-byte aligned. */
+                while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) {
                     tcg_out32(s, NOP);
                 }
                 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
-- 
2.34.1

The value previously chosen overlaps GUSA_MASK.

Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
that they are included in TB_FLAGs.  Add aliases for the
FPSCR and SR bits that are included in TB_FLAGS, so that
we don't accidentally reassign those bits.

Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/cpu.h        | 56 +++++++++++++------------
 linux-user/sh4/signal.c |  6 +--
 target/sh4/cpu.c        |  6 +--
 target/sh4/helper.c     |  6 +--
 target/sh4/translate.c  | 90 ++++++++++++++++++++++-------------------
 5 files changed, 88 insertions(+), 76 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define FPSCR_RM_NEAREST       (0 << 0)
 #define FPSCR_RM_ZERO          (1 << 0)
 
-#define DELAY_SLOT_MASK        0x7
-#define DELAY_SLOT             (1 << 0)
-#define DELAY_SLOT_CONDITIONAL (1 << 1)
-#define DELAY_SLOT_RTE         (1 << 2)
+#define TB_FLAG_DELAY_SLOT       (1 << 0)
+#define TB_FLAG_DELAY_SLOT_COND  (1 << 1)
+#define TB_FLAG_DELAY_SLOT_RTE   (1 << 2)
+#define TB_FLAG_PENDING_MOVCA    (1 << 3)
+#define TB_FLAG_GUSA_SHIFT       4                      /* [11:4] */
+#define TB_FLAG_GUSA_EXCLUSIVE   (1 << 12)
+#define TB_FLAG_UNALIGN          (1 << 13)
+#define TB_FLAG_SR_FD            (1 << SR_FD)           /* 15 */
+#define TB_FLAG_FPSCR_PR         FPSCR_PR               /* 19 */
+#define TB_FLAG_FPSCR_SZ         FPSCR_SZ               /* 20 */
+#define TB_FLAG_FPSCR_FR         FPSCR_FR               /* 21 */
+#define TB_FLAG_SR_RB            (1 << SR_RB)           /* 29 */
+#define TB_FLAG_SR_MD            (1 << SR_MD)           /* 30 */
 
-#define TB_FLAG_PENDING_MOVCA  (1 << 3)
-#define TB_FLAG_UNALIGN        (1 << 4)
-
-#define GUSA_SHIFT             4
-#ifdef CONFIG_USER_ONLY
-#define GUSA_EXCLUSIVE         (1 << 12)
-#define GUSA_MASK              ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
-#else
-/* Provide dummy versions of the above to allow tests against tbflags
-   to be elided while avoiding ifdefs.  */
-#define GUSA_EXCLUSIVE         0
-#define GUSA_MASK              0
-#endif
-
-#define TB_FLAG_ENVFLAGS_MASK  (DELAY_SLOT_MASK | GUSA_MASK)
+#define TB_FLAG_DELAY_SLOT_MASK  (TB_FLAG_DELAY_SLOT |       \
+                                  TB_FLAG_DELAY_SLOT_COND |  \
+                                  TB_FLAG_DELAY_SLOT_RTE)
+#define TB_FLAG_GUSA_MASK        ((0xff << TB_FLAG_GUSA_SHIFT) | \
+                                  TB_FLAG_GUSA_EXCLUSIVE)
+#define TB_FLAG_FPSCR_MASK       (TB_FLAG_FPSCR_PR | \
+                                  TB_FLAG_FPSCR_SZ | \
+                                  TB_FLAG_FPSCR_FR)
+#define TB_FLAG_SR_MASK          (TB_FLAG_SR_FD | \
+                                  TB_FLAG_SR_RB | \
+                                  TB_FLAG_SR_MD)
+#define TB_FLAG_ENVFLAGS_MASK    (TB_FLAG_DELAY_SLOT_MASK | \
+                                  TB_FLAG_GUSA_MASK)
 
 typedef struct tlb_t {
     uint32_t vpn;		/* virtual page number */
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
 {
     /* The instruction in a RTE delay slot is fetched in privileged
        mode, but executed in user mode.  */
-    if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
+    if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
         return 0;
     } else {
         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
 {
     *pc = env->pc;
     /* For a gUSA region, notice the end of the region.  */
-    *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
-    *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
-            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
-            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
-            | (env->sr & (1u << SR_FD))                        /* Bit 15 */
+    *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
+    *flags = env->flags
+            | (env->fpscr & TB_FLAG_FPSCR_MASK)
+            | (env->sr & TB_FLAG_SR_MASK)
             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
 #ifdef CONFIG_USER_ONLY
     *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/sh4/signal.c
+++ b/linux-user/sh4/signal.c
@@ -XXX,XX +XXX,XX @@ static void restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc)
     __get_user(regs->fpul, &sc->sc_fpul);
 
     regs->tra = -1;         /* disable syscall checks */
-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
+    regs->flags = 0;
 }
 
 void setup_frame(int sig, struct target_sigaction *ka,
@@ -XXX,XX +XXX,XX @@ void setup_frame(int sig, struct target_sigaction *ka,
     regs->gregs[5] = 0;
     regs->gregs[6] = frame_addr += offsetof(typeof(*frame), sc);
     regs->pc = (unsigned long) ka->_sa_handler;
-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
+    regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
 
     unlock_user_struct(frame, frame_addr, 1);
     return;
@@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
     regs->gregs[5] = frame_addr + offsetof(typeof(*frame), info);
     regs->gregs[6] = frame_addr + offsetof(typeof(*frame), uc);
     regs->pc = (unsigned long) ka->_sa_handler;
-    regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
+    regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
 
     unlock_user_struct(frame, frame_addr, 1);
     return;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
     SuperHCPU *cpu = SUPERH_CPU(cs);
 
     cpu->env.pc = tb_pc(tb);
-    cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
+    cpu->env.flags = tb->flags;
 }
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
     SuperHCPU *cpu = SUPERH_CPU(cs);
     CPUSH4State *env = &cpu->env;
 
-    if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
+    if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
         && env->pc != tb_pc(tb)) {
         env->pc -= 2;
-        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
+        env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
         return true;
     }
     return false;
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -XXX,XX +XXX,XX @@ void superh_cpu_do_interrupt(CPUState *cs)
     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
     env->lock_addr = -1;
 
-    if (env->flags & DELAY_SLOT_MASK) {
+    if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
         /* Branch instruction should be executed again before delay slot. */
 	env->spc -= 2;
 	/* Clear flags for exception/interrupt routine. */
-        env->flags &= ~DELAY_SLOT_MASK;
+        env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
     }
 
     if (do_exp) {
@@ -XXX,XX +XXX,XX @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
         CPUSH4State *env = &cpu->env;
 
         /* Delay slots are indivisible, ignore interrupts */
-        if (env->flags & DELAY_SLOT_MASK) {
+        if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
             return false;
         } else {
             superh_cpu_do_interrupt(cs);
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -XXX,XX +XXX,XX @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 		    i, env->gregs[i], i + 1, env->gregs[i + 1],
 		    i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
     }
-    if (env->flags & DELAY_SLOT) {
+    if (env->flags & TB_FLAG_DELAY_SLOT) {
         qemu_printf("in delay slot (delayed_pc=0x%08x)\n",
 		    env->delayed_pc);
-    } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
+    } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) {
         qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n",
 		    env->delayed_pc);
-    } else if (env->flags & DELAY_SLOT_RTE) {
+    } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) {
         qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n",
                      env->delayed_pc);
     }
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
 
 static inline bool use_exit_tb(DisasContext *ctx)
 {
-    return (ctx->tbflags & GUSA_EXCLUSIVE) != 0;
+    return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0;
 }
 
 static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
@@ -XXX,XX +XXX,XX @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
     TCGLabel *l1 = gen_new_label();
     TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE;
 
-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
+    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
         /* When in an exclusive region, we must continue to the end.
            Therefore, exit the region on a taken branch, but otherwise
            fall through to the next instruction.  */
         tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);
-        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
+        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
         /* Note that this won't actually use a goto_tb opcode because we
            disallow it in use_goto_tb, but it handles exit + singlestep.  */
         gen_goto_tb(ctx, 0, dest);
@@ -XXX,XX +XXX,XX @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
     tcg_gen_mov_i32(ds, cpu_delayed_cond);
     tcg_gen_discard_i32(cpu_delayed_cond);
 
-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
+    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
         /* When in an exclusive region, we must continue to the end.
            Therefore, exit the region on a taken branch, but otherwise
            fall through to the next instruction.  */
         tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1);
 
         /* Leave the gUSA region.  */
-        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
+        tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
         gen_jump(ctx);
 
         gen_set_label(l1);
@@ -XXX,XX +XXX,XX @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 
 #define CHECK_NOT_DELAY_SLOT \
-    if (ctx->envflags & DELAY_SLOT_MASK) {  \
-        goto do_illegal_slot;               \
+    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {  \
+        goto do_illegal_slot;                       \
     }
 
 #define CHECK_PRIVILEGED \
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
     case 0x000b:		/* rts */
 	CHECK_NOT_DELAY_SLOT
 	tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x0028:		/* clrmac */
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
 	CHECK_NOT_DELAY_SLOT
         gen_write_sr(cpu_ssr);
 	tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
-        ctx->envflags |= DELAY_SLOT_RTE;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT_RTE;
 	ctx->delayed_pc = (uint32_t) - 1;
         ctx->base.is_jmp = DISAS_STOP;
 	return;
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
 	return;
     case 0xe000:		/* mov #imm,Rn */
 #ifdef CONFIG_USER_ONLY
-        /* Detect the start of a gUSA region.  If so, update envflags
-           and end the TB.  This will allow us to see the end of the
-           region (stored in R0) in the next TB.  */
+        /*
+         * Detect the start of a gUSA region (mov #-n, r15).
+         * If so, update envflags and end the TB.  This will allow us
+         * to see the end of the region (stored in R0) in the next TB.
+         */
         if (B11_8 == 15 && B7_0s < 0 &&
             (tb_cflags(ctx->base.tb) & CF_PARALLEL)) {
-            ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
+            ctx->envflags =
+                deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s);
             ctx->base.is_jmp = DISAS_STOP;
         }
 #endif
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
     case 0xa000:		/* bra disp */
 	CHECK_NOT_DELAY_SLOT
         ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	return;
     case 0xb000:		/* bsr disp */
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
         ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1);
         ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
-        ctx->envflags |= DELAY_SLOT_CONDITIONAL;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
 	return;
     case 0x8900:		/* bt label */
 	CHECK_NOT_DELAY_SLOT
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t);
         ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
-        ctx->envflags |= DELAY_SLOT_CONDITIONAL;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
 	return;
     case 0x8800:		/* cmp/eq #imm,R0 */
         tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s);
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
     case 0x0023:		/* braf Rn */
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4);
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x0003:		/* bsrf Rn */
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
 	tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x4015:		/* cmp/pl Rn */
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
     case 0x402b:		/* jmp @Rn */
 	CHECK_NOT_DELAY_SLOT
 	tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x400b:		/* jsr @Rn */
 	CHECK_NOT_DELAY_SLOT
         tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
 	tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
-        ctx->envflags |= DELAY_SLOT;
+        ctx->envflags |= TB_FLAG_DELAY_SLOT;
 	ctx->delayed_pc = (uint32_t) - 1;
 	return;
     case 0x400e:		/* ldc Rm,SR */
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
     fflush(stderr);
 #endif
  do_illegal:
-    if (ctx->envflags & DELAY_SLOT_MASK) {
+    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
  do_illegal_slot:
         gen_save_cpu_state(ctx, true);
         gen_helper_raise_slot_illegal_instruction(cpu_env);
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
 
  do_fpu_disabled:
     gen_save_cpu_state(ctx, true);
-    if (ctx->envflags & DELAY_SLOT_MASK) {
+    if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
         gen_helper_raise_slot_fpu_disable(cpu_env);
     } else {
         gen_helper_raise_fpu_disable(cpu_env);
@@ -XXX,XX +XXX,XX @@ static void decode_opc(DisasContext * ctx)
 
     _decode_opc(ctx);
 
-    if (old_flags & DELAY_SLOT_MASK) {
+    if (old_flags & TB_FLAG_DELAY_SLOT_MASK) {
         /* go out of the delay slot */
-        ctx->envflags &= ~DELAY_SLOT_MASK;
+        ctx->envflags &= ~TB_FLAG_DELAY_SLOT_MASK;
 
         /* When in an exclusive region, we must continue to the end
            for conditional branches.  */
-        if (ctx->tbflags & GUSA_EXCLUSIVE
-            && old_flags & DELAY_SLOT_CONDITIONAL) {
+        if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE
+            && old_flags & TB_FLAG_DELAY_SLOT_COND) {
             gen_delayed_conditional_jump(ctx);
             return;
         }
         /* Otherwise this is probably an invalid gUSA region.
            Drop the GUSA bits so the next TB doesn't see them.  */
-        ctx->envflags &= ~GUSA_MASK;
+        ctx->envflags &= ~TB_FLAG_GUSA_MASK;
 
         tcg_gen_movi_i32(cpu_flags, ctx->envflags);
-        if (old_flags & DELAY_SLOT_CONDITIONAL) {
+        if (old_flags & TB_FLAG_DELAY_SLOT_COND) {
 	    gen_delayed_conditional_jump(ctx);
         } else {
             gen_jump(ctx);
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
     }
 
     /* The entire region has been translated.  */
-    ctx->envflags &= ~GUSA_MASK;
+    ctx->envflags &= ~TB_FLAG_GUSA_MASK;
     ctx->base.pc_next = pc_end;
     ctx->base.num_insns += max_insns - 1;
     return;
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
 
     /* Restart with the EXCLUSIVE bit set, within a TB run via
        cpu_exec_step_atomic holding the exclusive lock.  */
-    ctx->envflags |= GUSA_EXCLUSIVE;
+    ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE;
     gen_save_cpu_state(ctx, false);
     gen_helper_exclusive(cpu_env);
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
                   (tbflags & (1 << SR_RB))) * 0x10;
     ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0;
 
-    if (tbflags & GUSA_MASK) {
+#ifdef CONFIG_USER_ONLY
+    if (tbflags & TB_FLAG_GUSA_MASK) {
+        /* In gUSA exclusive region. */
         uint32_t pc = ctx->base.pc_next;
         uint32_t pc_end = ctx->base.tb->cs_base;
-        int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);
+        int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8);
         int max_insns = (pc_end - pc) / 2;
 
         if (pc != pc_end + backup || max_insns < 2) {
             /* This is a malformed gUSA region.  Don't do anything special,
                since the interpreter is likely to get confused.  */
-            ctx->envflags &= ~GUSA_MASK;
-        } else if (tbflags & GUSA_EXCLUSIVE) {
+            ctx->envflags &= ~TB_FLAG_GUSA_MASK;
+        } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
             /* Regardless of single-stepping or the end of the page,
                we must complete execution of the gUSA region while
                holding the exclusive lock.  */
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
             return;
         }
     }
+#endif
 
     /* Since the ISA is fixed-width, we can bound by the number
        of instructions remaining on the page.  */
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
 #ifdef CONFIG_USER_ONLY
-    if (unlikely(ctx->envflags & GUSA_MASK)
-        && !(ctx->envflags & GUSA_EXCLUSIVE)) {
+    if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK)
+        && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) {
         /* We're in an gUSA region, and we have not already fallen
            back on using an exclusive region.  Attempt to parse the
            region into a single supported atomic operation.  Failure
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    if (ctx->tbflags & GUSA_EXCLUSIVE) {
+    if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
         /* Ending the region of exclusivity.  Clear the bits.  */
-        ctx->envflags &= ~GUSA_MASK;
+        ctx->envflags &= ~TB_FLAG_GUSA_MASK;
     }
 
     switch (ctx->base.is_jmp) {
-- 
2.34.1