Series comparison

-[PULL 00/15] tcg patch queue
+[PULL 00/24] tcg patch queue
-The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:
+The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
-  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)
+  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
-for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:
+for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
-  tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)
+  Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
 ----------------------------------------------------------------
-Host vector support for arm neon.
+Move gdb singlestep to generic code
 Fix cpu_common_props
 ----------------------------------------------------------------
-Richard Henderson (15):
+Richard Henderson (24):
-      tcg: Change parameters for tcg_target_const_match
+      accel/tcg: Handle gdb singlestep in cpu_tb_exec
-      tcg/arm: Add host vector framework
+      target/alpha: Drop checks for singlestep_enabled
-      tcg/arm: Implement tcg_out_ld/st for vector types
+      target/avr: Drop checks for singlestep_enabled
-      tcg/arm: Implement tcg_out_mov for vector types
+      target/cris: Drop checks for singlestep_enabled
-      tcg/arm: Implement tcg_out_dup*_vec
+      target/hexagon: Drop checks for singlestep_enabled
-      tcg/arm: Implement minimal vector operations
+      target/arm: Drop checks for singlestep_enabled
-      tcg/arm: Implement andc, orc, abs, neg, not vector operations
+      target/hppa: Drop checks for singlestep_enabled
-      tcg/arm: Implement TCG_TARGET_HAS_shi_vec
+      target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
-      tcg/arm: Implement TCG_TARGET_HAS_mul_vec
+      target/i386: Drop check for singlestep_enabled
-      tcg/arm: Implement TCG_TARGET_HAS_sat_vec
+      target/m68k: Drop checks for singlestep_enabled
-      tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
+      target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
-      tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
+      target/microblaze: Drop checks for singlestep_enabled
-      tcg/arm: Implement TCG_TARGET_HAS_shv_vec
+      target/mips: Fix single stepping
-      tcg/arm: Implement TCG_TARGET_HAS_roti_vec
+      target/mips: Drop exit checks for singlestep_enabled
-      tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
+      target/openrisc: Drop checks for singlestep_enabled
       target/ppc: Drop exit checks for singlestep_enabled
       target/riscv: Remove dead code after exception
       target/riscv: Remove exit_tb and lookup_and_goto_ptr
       target/rx: Drop checks for singlestep_enabled
       target/s390x: Drop check for singlestep_enabled
       target/sh4: Drop check for singlestep_enabled
       target/tricore: Drop check for singlestep_enabled
       target/xtensa: Drop check for singlestep_enabled
       Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
- tcg/arm/tcg-target-con-set.h |  10 +
+ include/hw/core/cpu.h                          |  1 +
- tcg/arm/tcg-target-con-str.h |   3 +
+ target/i386/helper.h                           |  1 -
- tcg/arm/tcg-target.h         |  52 ++-
+ target/rx/helper.h                             |  1 -
- tcg/arm/tcg-target.opc.h     |  16 +
+ target/sh4/helper.h                            |  1 -
- tcg/tcg.c                    |   5 +-
+ target/tricore/helper.h                        |  1 -
- tcg/aarch64/tcg-target.c.inc |   5 +-
+ accel/tcg/cpu-exec.c                           | 11 ++++
- tcg/arm/tcg-target.c.inc     | 956 +++++++++++++++++++++++++++++++++++++++++--
+ cpu.c                                          | 21 ++++++++
- tcg/i386/tcg-target.c.inc    |   4 +-
+ hw/core/cpu-common.c                           | 17 +-----
- tcg/mips/tcg-target.c.inc    |   5 +-
+ target/alpha/translate.c                       | 13 ++---
- tcg/ppc/tcg-target.c.inc     |   4 +-
+ target/arm/translate-a64.c                     | 10 +---
- tcg/riscv/tcg-target.c.inc   |   4 +-
+ target/arm/translate.c                         | 36 +++----------
- tcg/s390/tcg-target.c.inc    |   5 +-
+ target/avr/translate.c                         | 19 ++-----
- tcg/sparc/tcg-target.c.inc   |   5 +-
+ target/cris/translate.c                        | 16 ------
- tcg/tci/tcg-target.c.inc     |   6 +-
+ target/hexagon/translate.c                     | 12 +----
-files changed, 1001 insertions(+), 79 deletions(-)
+ target/hppa/translate.c                        | 17 ++----
- create mode 100644 tcg/arm/tcg-target.opc.h
+ target/i386/tcg/misc_helper.c                  |  8 ---
  target/i386/tcg/translate.c                    |  9 ++--
  target/m68k/translate.c                        | 44 ++++-----------
  target/microblaze/translate.c                  | 18 ++-----
  target/mips/tcg/translate.c                    | 75 ++++++++++++--------------
  target/openrisc/translate.c                    | 18 ++-----
  target/ppc/translate.c                         | 38 +++----------
  target/riscv/translate.c                       | 27 +---------
  target/rx/op_helper.c                          |  8 ---
  target/rx/translate.c                          | 12 +----
  target/s390x/tcg/translate.c                   |  8 +--
  target/sh4/op_helper.c                         |  5 --
  target/sh4/translate.c                         | 14 ++---
  target/tricore/op_helper.c                     |  7 ---
  target/tricore/translate.c                     | 14 +----
  target/xtensa/translate.c                      | 25 +++------
  target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
  target/riscv/insn_trans/trans_rvi.c.inc        |  8 ++-
  target/riscv/insn_trans/trans_rvv.c.inc        |  2 +-
 files changed, 141 insertions(+), 386 deletions(-)

-[PULL 02/15] tcg/arm: Add host vector framework
+[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec
-Add registers and function stubs.  The functionality
+Currently the change in cpu_tb_exec is masked by the debug exception
-is disabled via use_neon_instructions defined to 0.
+being raised by the translators.  But this allows us to remove that code.
-We must still include results for the mandatory opcodes in
-tcg_target_op_def, as all opcodes are checked during tcg init.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |   4 ++
+ accel/tcg/cpu-exec.c | 11 +++++++++++
- tcg/arm/tcg-target-con-str.h |   1 +
+file changed, 11 insertions(+)
  tcg/arm/tcg-target.h         |  48 ++++++++++++--
  tcg/arm/tcg-target.opc.h     |  12 ++++
  tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
 files changed, 158 insertions(+), 24 deletions(-)
  create mode 100644 tcg/arm/tcg-target.opc.h
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/accel/tcg/cpu-exec.c
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/accel/tcg/cpu-exec.c
-@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
+@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
- C_O0_I2(r, r)
+             cc->set_pc(cpu, last_tb->pc);
  C_O0_I2(r, rIN)
  C_O0_I2(s, s)
 +C_O0_I2(w, r)
  C_O0_I3(s, s, s)
  C_O0_I4(r, r, rI, rI)
  C_O0_I4(s, s, s, s)
  C_O1_I1(r, l)
  C_O1_I1(r, r)
 +C_O1_I1(w, r)
 +C_O1_I1(w, wr)
  C_O1_I2(r, 0, rZ)
  C_O1_I2(r, l, l)
  C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
  C_O1_I2(r, r, rIN)
  C_O1_I2(r, r, ri)
  C_O1_I2(r, rZ, rZ)
 +C_O1_I2(w, w, w)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target-con-str.h
 +++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
  REGS('r', ALL_GENERAL_REGS)
  REGS('l', ALL_QLOAD_REGS)
  REGS('s', ALL_QSTORE_REGS)
 +REGS('w', ALL_VECTOR_REGS)
  /*
   * Define constraint letters for constants:
 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
      TCG_REG_R13,
      TCG_REG_R14,
      TCG_REG_PC,
 +
 +    TCG_REG_Q0,
 +    TCG_REG_Q1,
 +    TCG_REG_Q2,
 +    TCG_REG_Q3,
 +    TCG_REG_Q4,
 +    TCG_REG_Q5,
 +    TCG_REG_Q6,
 +    TCG_REG_Q7,
 +    TCG_REG_Q8,
 +    TCG_REG_Q9,
 +    TCG_REG_Q10,
 +    TCG_REG_Q11,
 +    TCG_REG_Q12,
 +    TCG_REG_Q13,
 +    TCG_REG_Q14,
 +    TCG_REG_Q15,
 +
 +    TCG_AREG0 = TCG_REG_R6,
 +    TCG_REG_CALL_STACK = TCG_REG_R13,
  } TCGReg;
 -#define TCG_TARGET_NB_REGS 16
 +#define TCG_TARGET_NB_REGS 32
  #ifdef __ARM_ARCH_EXT_IDIV__
  #define use_idiv_instructions  1
  #else
  extern bool use_idiv_instructions;
  #endif
 -
 +#define use_neon_instructions  0
  /* used for function call generation */
 -#define TCG_REG_CALL_STACK        TCG_REG_R13
  #define TCG_TARGET_STACK_ALIGN        8
  #define TCG_TARGET_CALL_ALIGN_ARGS    1
  #define TCG_TARGET_CALL_STACK_OFFSET    0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
  #define TCG_TARGET_HAS_direct_jump      0
  #define TCG_TARGET_HAS_qemu_st8_i32     0
 -enum {
 -    TCG_AREG0 = TCG_REG_R6,
 -};
 +#define TCG_TARGET_HAS_v64              use_neon_instructions
 +#define TCG_TARGET_HAS_v128             use_neon_instructions
 +#define TCG_TARGET_HAS_v256             0
 +
 +#define TCG_TARGET_HAS_andc_vec         0
 +#define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_not_vec          0
 +#define TCG_TARGET_HAS_neg_vec          0
 +#define TCG_TARGET_HAS_abs_vec          0
 +#define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rots_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
 +#define TCG_TARGET_HAS_shi_vec          0
 +#define TCG_TARGET_HAS_shs_vec          0
 +#define TCG_TARGET_HAS_shv_vec          0
 +#define TCG_TARGET_HAS_mul_vec          0
 +#define TCG_TARGET_HAS_sat_vec          0
 +#define TCG_TARGET_HAS_minmax_vec       0
 +#define TCG_TARGET_HAS_bitsel_vec       0
 +#define TCG_TARGET_HAS_cmpsel_vec       0
  #define TCG_TARGET_DEFAULT_MO (0)
  #define TCG_TARGET_HAS_MEMORY_BSWAP     1
 diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Copyright (c) 2019 Linaro
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or
 + * (at your option) any later version.
 + *
 + * See the COPYING file in the top-level directory for details.
 + *
 + * Target-specific opcodes for host vector expansion.  These will be
 + * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
 + * consider these to be UNSPEC with names.
 + */
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
  #ifdef CONFIG_DEBUG_TCG
  static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 -    "%r0",
 -    "%r1",
 -    "%r2",
 -    "%r3",
 -    "%r4",
 -    "%r5",
 -    "%r6",
 -    "%r7",
 -    "%r8",
 -    "%r9",
 -    "%r10",
 -    "%r11",
 -    "%r12",
 -    "%r13",
 -    "%r14",
 -    "%pc",
 +    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
 +    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
 +    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
 +    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
      TCG_REG_R3,
      TCG_REG_R12,
      TCG_REG_R14,
 +
 +    TCG_REG_Q0,
 +    TCG_REG_Q1,
 +    TCG_REG_Q2,
 +    TCG_REG_Q3,
 +    /* Q4 - Q7 are call-saved, and skipped. */
 +    TCG_REG_Q8,
 +    TCG_REG_Q9,
 +    TCG_REG_Q10,
 +    TCG_REG_Q11,
 +    TCG_REG_Q12,
 +    TCG_REG_Q13,
 +    TCG_REG_Q14,
 +    TCG_REG_Q15,
  };
  static const int tcg_target_call_iarg_regs[4] = {
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
  };
  #define TCG_REG_TMP  TCG_REG_R12
 +#define TCG_VEC_TMP  TCG_REG_Q15
  enum arm_cond_code_e {
      COND_EQ = 0x0,
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  #define TCG_CT_CONST_ZERO 0x800
  #define ALL_GENERAL_REGS  0xffffu
 +#define ALL_VECTOR_REGS   0xffff0000u
  /*
   * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_qemu_st_i64:
          return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 +    case INDEX_op_st_vec:
 +        return C_O0_I2(w, r);
 +    case INDEX_op_ld_vec:
 +    case INDEX_op_dupm_vec:
 +        return C_O1_I1(w, r);
 +    case INDEX_op_dup_vec:
 +        return C_O1_I1(w, wr);
 +    case INDEX_op_dup2_vec:
 +    case INDEX_op_add_vec:
 +    case INDEX_op_sub_vec:
 +    case INDEX_op_xor_vec:
 +    case INDEX_op_or_vec:
 +    case INDEX_op_and_vec:
 +    case INDEX_op_cmp_vec:
 +        return C_O1_I2(w, w, w);
 +
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
  {
      /* Only probe for the platform and capabilities if we havn't already
         determined maximum values at compile time.  */
 -#ifndef use_idiv_instructions
 +#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
      {
          unsigned long hwcap = qemu_getauxval(AT_HWCAP);
 +#ifndef use_idiv_instructions
          use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
 +#endif
 +#ifndef use_neon_instructions
 +        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
 +#endif
      }
  #endif
 +
      if (__ARM_ARCH < 7) {
          const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
          if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
          }
      }
--    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
-+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
-     tcg_target_call_clobber_regs = 0;
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
-@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
-+    if (use_neon_instructions) {
-+        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
-+        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
 +
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
++    /*
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
++     * If gdb single-step, and we haven't raised another exception,
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
++     * raise a debug exception.  Single-step with another exception
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
++     * is handled in cpu_handle_exception.
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
++     */
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
++    if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
++        cpu->exception_index = EXCP_DEBUG;
-+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
++        cpu_loop_exit(cpu);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
 +        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
 +    }
 +
-     s->reserved_regs = 0;
+     return last_tb;
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
 +    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
  }
- static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
-     tcg_out_movi32(s, COND_AL, ret, arg);
- }
-+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
-+                            TCGReg rd, TCGReg rs)
-+{
-+    g_assert_not_reached();
-+}
-+
-+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
-+                             TCGReg rd, TCGReg base, intptr_t offset)
-+{
-+    g_assert_not_reached();
-+}
-+
-+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
-+                             TCGReg rd, int64_t v64)
-+{
-+    g_assert_not_reached();
-+}
-+
-+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-+                           unsigned vecl, unsigned vece,
-+                           const TCGArg *args, const int *const_args)
-+{
-+    g_assert_not_reached();
-+}
-+
-+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-+{
-+    return 0;
-+}
-+
-+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-+                       TCGArg a0, ...)
-+{
-+    g_assert_not_reached();
-+}
-+
- static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
- {
-     int i;
 --
 .25.1

-New patch
+[PULL 02/24] target/alpha: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/alpha/translate.c | 13 +++----------
+file changed, 3 insertions(+), 10 deletions(-)
+diff --git a/target/alpha/translate.c b/target/alpha/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/alpha/translate.c
++++ b/target/alpha/translate.c
+@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
+         /* FALLTHRU */
+     case DISAS_PC_UPDATED:
+-        if (!ctx->base.singlestep_enabled) {
+-            tcg_gen_lookup_and_goto_ptr();
+-            break;
+-        }
+-        /* FALLTHRU */
++        tcg_gen_lookup_and_goto_ptr();
++        break;
+     case DISAS_PC_UPDATED_NOCHAIN:
+-        if (ctx->base.singlestep_enabled) {
+-            gen_excp_1(EXCP_DEBUG, 0);
+-        } else {
+-            tcg_gen_exit_tb(NULL, 0);
+-        }
++        tcg_gen_exit_tb(NULL, 0);
+         break;
+     default:
+         g_assert_not_reached();
+--
+.25.1

-New patch
+[PULL 03/24] target/avr: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Tested-by: Michael Rolnik <mrolnik@gmail.com>
+Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/avr/translate.c | 19 ++++---------------
+file changed, 4 insertions(+), 15 deletions(-)
+diff --git a/target/avr/translate.c b/target/avr/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/avr/translate.c
++++ b/target/avr/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+         tcg_gen_exit_tb(tb, n);
+     } else {
+         tcg_gen_movi_i32(cpu_pc, dest);
+-        if (ctx->base.singlestep_enabled) {
+-            gen_helper_debug(cpu_env);
+-        } else {
+-            tcg_gen_lookup_and_goto_ptr();
+-        }
++        tcg_gen_lookup_and_goto_ptr();
+     }
+     ctx->base.is_jmp = DISAS_NORETURN;
+ }
+@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+         tcg_gen_movi_tl(cpu_pc, ctx->npc);
+         /* fall through */
+     case DISAS_LOOKUP:
+-        if (!ctx->base.singlestep_enabled) {
+-            tcg_gen_lookup_and_goto_ptr();
+-            break;
+-        }
+-        /* fall through */
++        tcg_gen_lookup_and_goto_ptr();
++        break;
+     case DISAS_EXIT:
+-        if (ctx->base.singlestep_enabled) {
+-            gen_helper_debug(cpu_env);
+-        } else {
+-            tcg_gen_exit_tb(NULL, 0);
+-        }
++        tcg_gen_exit_tb(NULL, 0);
+         break;
+     default:
+         g_assert_not_reached();
+--
+.25.1

-New patch
+[PULL 04/24] target/cris: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/cris/translate.c | 16 ----------------
+file changed, 16 deletions(-)
+diff --git a/target/cris/translate.c b/target/cris/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/cris/translate.c
++++ b/target/cris/translate.c
+@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         }
+     }
+-    if (unlikely(dc->base.singlestep_enabled)) {
+-        switch (is_jmp) {
+-        case DISAS_TOO_MANY:
+-        case DISAS_UPDATE_NEXT:
+-            tcg_gen_movi_tl(env_pc, npc);
+-            /* fall through */
+-        case DISAS_JUMP:
+-        case DISAS_UPDATE:
+-            t_gen_raise_exception(EXCP_DEBUG);
+-            return;
+-        default:
+-            break;
+-        }
+-        g_assert_not_reached();
+-    }
+-
+     switch (is_jmp) {
+     case DISAS_TOO_MANY:
+         gen_goto_tb(dc, 0, npc);
+--
+.25.1

-New patch
+[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/hexagon/translate.c | 12 ++----------
+file changed, 2 insertions(+), 10 deletions(-)
+diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/hexagon/translate.c
++++ b/target/hexagon/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
+ {
+     gen_exec_counters(ctx);
+     tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
+-    if (ctx->base.singlestep_enabled) {
+-        gen_exception_raw(EXCP_DEBUG);
+-    } else {
+-        tcg_gen_exit_tb(NULL, 0);
+-    }
++    tcg_gen_exit_tb(NULL, 0);
+     ctx->base.is_jmp = DISAS_NORETURN;
+ }
+@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+     case DISAS_TOO_MANY:
+         gen_exec_counters(ctx);
+         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
+-        if (ctx->base.singlestep_enabled) {
+-            gen_exception_raw(EXCP_DEBUG);
+-        } else {
+-            tcg_gen_exit_tb(NULL, 0);
+-        }
++        tcg_gen_exit_tb(NULL, 0);
+         break;
+     case DISAS_NORETURN:
+         break;
+--
+.25.1

-New patch
+[PULL 06/24] target/arm: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/arm/translate-a64.c | 10 ++--------
+ target/arm/translate.c     | 36 ++++++------------------------------
+files changed, 8 insertions(+), 38 deletions(-)
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
+         gen_a64_set_pc_im(dest);
+         if (s->ss_active) {
+             gen_step_complete_exception(s);
+-        } else if (s->base.singlestep_enabled) {
+-            gen_exception_internal(EXCP_DEBUG);
+         } else {
+             tcg_gen_lookup_and_goto_ptr();
+             s->base.is_jmp = DISAS_NORETURN;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+ {
+     DisasContext *dc = container_of(dcbase, DisasContext, base);
+-    if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
++    if (unlikely(dc->ss_active)) {
+         /* Note that this means single stepping WFI doesn't halt the CPU.
+          * For conditional branch insns this is harmless unreachable code as
+          * gen_goto_tb() has already handled emitting the debug exception
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+             /* fall through */
+         case DISAS_EXIT:
+         case DISAS_JUMP:
+-            if (dc->base.singlestep_enabled) {
+-                gen_exception_internal(EXCP_DEBUG);
+-            } else {
+-                gen_step_complete_exception(dc);
+-            }
++            gen_step_complete_exception(dc);
+             break;
+         case DISAS_NORETURN:
+             break;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
+     tcg_temp_free_i32(tcg_excp);
+ }
+-static void gen_step_complete_exception(DisasContext *s)
++static void gen_singlestep_exception(DisasContext *s)
+ {
+     /* We just completed step of an insn. Move from Active-not-pending
+      * to Active-pending, and then also take the swstep exception.
+@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-static void gen_singlestep_exception(DisasContext *s)
+-{
+-    /* Generate the right kind of exception for singlestep, which is
+-     * either the architectural singlestep or EXCP_DEBUG for QEMU's
+-     * gdb singlestepping.
+-     */
+-    if (s->ss_active) {
+-        gen_step_complete_exception(s);
+-    } else {
+-        gen_exception_internal(EXCP_DEBUG);
+-    }
+-}
+-
+-static inline bool is_singlestepping(DisasContext *s)
+-{
+-    /* Return true if we are singlestepping either because of
+-     * architectural singlestep or QEMU gdbstub singlestep. This does
+-     * not include the command line '-singlestep' mode which is rather
+-     * misnamed as it only means "one instruction per TB" and doesn't
+-     * affect the code we generate.
+-     */
+-    return s->base.singlestep_enabled || s->ss_active;
+-}
+-
+ void clear_eci_state(DisasContext *s)
+ {
+     /*
+@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
+     /* Is the new PC value in the magic range indicating exception return? */
+     tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
+     /* No: end the TB as we would for a DISAS_JMP */
+-    if (is_singlestepping(s)) {
++    if (s->ss_active) {
+         gen_singlestep_exception(s);
+     } else {
+         tcg_gen_exit_tb(NULL, 0);
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
+ /* Jump, specifying which TB number to use if we gen_goto_tb() */
+ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
+ {
+-    if (unlikely(is_singlestepping(s))) {
++    if (unlikely(s->ss_active)) {
+         /* An indirect jump so that we still trigger the debug exception.  */
+         gen_set_pc_im(s, dest);
+         s->base.is_jmp = DISAS_JUMP;
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
+     /* If architectural single step active, limit to 1.  */
+-    if (is_singlestepping(dc)) {
++    if (dc->ss_active) {
+         dc->base.max_insns = 1;
+     }
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+          * insn codepath itself.
+          */
+         gen_bx_excret_final_code(dc);
+-    } else if (unlikely(is_singlestepping(dc))) {
++    } else if (unlikely(dc->ss_active)) {
+         /* Unconditional and "condition passed" instruction codepath. */
+         switch (dc->base.is_jmp) {
+         case DISAS_SWI:
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         /* "Condition failed" instruction codepath for the branch/trap insn */
+         gen_set_label(dc->condlabel);
+         gen_set_condexec(dc);
+-        if (unlikely(is_singlestepping(dc))) {
++        if (unlikely(dc->ss_active)) {
+             gen_set_pc_im(dc, dc->base.pc_next);
+             gen_singlestep_exception(dc);
+         } else {
+--
+.25.1

-New patch
+[PULL 07/24] target/hppa: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/hppa/translate.c | 17 ++++-------------
+file changed, 4 insertions(+), 13 deletions(-)
+diff --git a/target/hppa/translate.c b/target/hppa/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/hppa/translate.c
++++ b/target/hppa/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
+     } else {
+         copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
+         copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
+-        if (ctx->base.singlestep_enabled) {
+-            gen_excp_1(EXCP_DEBUG);
+-        } else {
+-            tcg_gen_lookup_and_goto_ptr();
+-        }
++        tcg_gen_lookup_and_goto_ptr();
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
+         gen_helper_rfi(cpu_env);
+     }
+     /* Exit the TB to recognize new interrupts.  */
+-    if (ctx->base.singlestep_enabled) {
+-        gen_excp_1(EXCP_DEBUG);
+-    } else {
+-        tcg_gen_exit_tb(NULL, 0);
+-    }
++    tcg_gen_exit_tb(NULL, 0);
+     ctx->base.is_jmp = DISAS_NORETURN;
+     return nullify_end(ctx);
+@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+         nullify_save(ctx);
+         /* FALLTHRU */
+     case DISAS_IAQ_N_UPDATED:
+-        if (ctx->base.singlestep_enabled) {
+-            gen_excp_1(EXCP_DEBUG);
+-        } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
++        if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
+             tcg_gen_lookup_and_goto_ptr();
++            break;
+         }
+         /* FALLTHRU */
+     case DISAS_EXIT:
+--
+.25.1

-New patch
+[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
+We were using singlestep_enabled as a proxy for whether
+translator_use_goto_tb would always return false.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/i386/tcg/translate.c | 5 +++--
+file changed, 3 insertions(+), 2 deletions(-)
+diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/tcg/translate.c
++++ b/target/i386/tcg/translate.c
+@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
+     DisasContext *dc = container_of(dcbase, DisasContext, base);
+     CPUX86State *env = cpu->env_ptr;
+     uint32_t flags = dc->base.tb->flags;
++    uint32_t cflags = tb_cflags(dc->base.tb);
+     int cpl = (flags >> HF_CPL_SHIFT) & 3;
+     int iopl = (flags >> IOPL_SHIFT) & 3;
+@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
+     dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
+     dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
+     dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
+-    dc->jmp_opt = !(dc->base.singlestep_enabled ||
++    dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
+                     (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
+     /*
+      * If jmp_opt, we want to handle each string instruction individually.
+      * For icount also disable repz optimization so that each iteration
+      * is accounted separately.
+      */
+-    dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
++    dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
+     dc->T0 = tcg_temp_new();
+     dc->T1 = tcg_temp_new();
+--
+.25.1

-New patch
+[PULL 09/24] target/i386: Drop check for singlestep_enabled
+GDB single-stepping is now handled generically.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/i386/helper.h          | 1 -
+ target/i386/tcg/misc_helper.c | 8 --------
+ target/i386/tcg/translate.c   | 4 +---
+files changed, 1 insertion(+), 12 deletions(-)
+diff --git a/target/i386/helper.h b/target/i386/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/helper.h
++++ b/target/i386/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
+ DEF_HELPER_2(sysret, void, env, int)
+ #endif
+ DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
+-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
+ DEF_HELPER_1(reset_rf, void, env)
+ DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
+ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
+diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/tcg/misc_helper.c
++++ b/target/i386/tcg/misc_helper.c
+@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
+     do_pause(env);
+ }
+-void QEMU_NORETURN helper_debug(CPUX86State *env)
+-{
+-    CPUState *cs = env_cpu(env);
+-
+-    cs->exception_index = EXCP_DEBUG;
+-    cpu_loop_exit(cs);
+-}
+-
+ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
+ {
+     if ((env->cr[4] & CR4_PKE_MASK) == 0) {
+diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/tcg/translate.c
++++ b/target/i386/tcg/translate.c
+@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
+     if (s->base.tb->flags & HF_RF_MASK) {
+         gen_helper_reset_rf(cpu_env);
+     }
+-    if (s->base.singlestep_enabled) {
+-        gen_helper_debug(cpu_env);
+-    } else if (recheck_tf) {
++    if (recheck_tf) {
+         gen_helper_rechecking_single_step(cpu_env);
+         tcg_gen_exit_tb(NULL, 0);
+     } else if (s->flags & HF_TF_MASK) {
+--
+.25.1

-New patch
+[PULL 10/24] target/m68k: Drop checks for singlestep_enabled
+GDB single-stepping is now handled generically.
+Acked-by: Laurent Vivier <laurent@vivier.eu>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ target/m68k/translate.c | 44 +++++++++--------------------------------
+file changed, 9 insertions(+), 35 deletions(-)
+diff --git a/target/m68k/translate.c b/target/m68k/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/m68k/translate.c
++++ b/target/m68k/translate.c
+@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
+     }
+ }
+-static bool is_singlestepping(DisasContext *s)
+-{
+-    /*
+-     * Return true if we are singlestepping either because of
+-     * architectural singlestep or QEMU gdbstub singlestep. This does
+-     * not include the command line '-singlestep' mode which is rather
+-     * misnamed as it only means "one instruction per TB" and doesn't
+-     * affect the code we generate.
+-     */
+-    return s->base.singlestep_enabled || s->ss_active;
+-}
+-
+ /* is_jmp field values */
+ #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
+ #define DISAS_EXIT      DISAS_TARGET_1 /* cpu state was modified dynamically */
+@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-static void gen_singlestep_exception(DisasContext *s)
+-{
+-    /*
+-     * Generate the right kind of exception for singlestep, which is
+-     * either the architectural singlestep or EXCP_DEBUG for QEMU's
+-     * gdb singlestepping.
+-     */
+-    if (s->ss_active) {
+-        gen_raise_exception(EXCP_TRACE);
+-    } else {
+-        gen_raise_exception(EXCP_DEBUG);
+-    }
+-}
+-
+ static inline void gen_addr_fault(DisasContext *s)
+ {
+     gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
+@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
+ /* Generate a jump to an immediate address.  */
+ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
+ {
+-    if (unlikely(is_singlestepping(s))) {
++    if (unlikely(s->ss_active)) {
+         update_cc_op(s);
+         tcg_gen_movi_i32(QREG_PC, dest);
+-        gen_singlestep_exception(s);
++        gen_raise_exception(EXCP_TRACE);
+     } else if (translator_use_goto_tb(&s->base, dest)) {
+         tcg_gen_goto_tb(n);
+         tcg_gen_movi_i32(QREG_PC, dest);
+@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
+     dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
+     /* If architectural single step active, limit to 1 */
+-    if (is_singlestepping(dc)) {
++    if (dc->ss_active) {
+         dc->base.max_insns = 1;
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         break;
+     case DISAS_TOO_MANY:
+         update_cc_op(dc);
+-        if (is_singlestepping(dc)) {
++        if (dc->ss_active) {
+             tcg_gen_movi_i32(QREG_PC, dc->pc);
+-            gen_singlestep_exception(dc);
++            gen_raise_exception(EXCP_TRACE);
+         } else {
+             gen_jmp_tb(dc, 0, dc->pc);
+         }
+         break;
+     case DISAS_JUMP:
+         /* We updated CC_OP and PC in gen_jmp/gen_jmp_im.  */
+-        if (is_singlestepping(dc)) {
+-            gen_singlestep_exception(dc);
++        if (dc->ss_active) {
++            gen_raise_exception(EXCP_TRACE);
+         } else {
+             tcg_gen_lookup_and_goto_ptr();
+         }
+@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+          * We updated CC_OP and PC in gen_exit_tb, but also modified
+          * other state that may require returning to the main loop.
+          */
+-        if (is_singlestepping(dc)) {
+-            gen_singlestep_exception(dc);
++        if (dc->ss_active) {
++            gen_raise_exception(EXCP_TRACE);
+         } else {
+             tcg_gen_exit_tb(NULL, 0);
+         }
+--
+.25.1

-[PULL 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
+[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
-Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
+We were using singlestep_enabled as a proxy for whether
 translator_use_goto_tb would always return false.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
+ target/microblaze/translate.c | 4 ++--
-file changed, 34 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/microblaze/translate.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/microblaze/translate.c
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
      case INDEX_op_shrv_vec:
      case INDEX_op_sarv_vec:
      case INDEX_op_rotli_vec:
 +    case INDEX_op_rotlv_vec:
 +    case INDEX_op_rotrv_vec:
          return -1;
      default:
          return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                         TCGArg a0, ...)
  {
      va_list va;
 -    TCGv_vec v0, v1, v2, t1;
 +    TCGv_vec v0, v1, v2, t1, t2, c1;
      TCGArg a2;
      va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
          tcg_temp_free_vec(t1);
          break;
-+    case INDEX_op_rotlv_vec:
+     case DISAS_JUMP:
-+        v2 = temp_tcgv_vec(arg_temp(a2));
+-        if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
-+        t1 = tcg_temp_new_vec(type);
++        if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
-+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+             /* Direct jump. */
-+        tcg_gen_sub_vec(vece, t1, v2, c1);
+             tcg_gen_discard_i32(cpu_btarget);
-+        /* Right shifts are negative left shifts for NEON.  */
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+             return;
-+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+         }
-+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
-+        tcg_gen_or_vec(vece, v0, v0, t1);
+-        /* Indirect jump (or direct jump w/ singlestep) */
-+        tcg_temp_free_vec(t1);
++        /* Indirect jump (or direct jump w/ goto_tb disabled) */
-+        break;
+         tcg_gen_mov_i32(cpu_pc, cpu_btarget);
-+
+         tcg_gen_discard_i32(cpu_btarget);
-+    case INDEX_op_rotrv_vec:
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        t1 = tcg_temp_new_vec(type);
 +        t2 = tcg_temp_new_vec(type);
 +        c1 = tcg_constant_vec(type, vece, 8 << vece);
 +        tcg_gen_neg_vec(vece, t1, v2);
 +        tcg_gen_sub_vec(vece, t2, c1, v2);
 +        /* Right shifts are negative left shifts for NEON.  */
 +        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
 +        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
 +        tcg_gen_or_vec(vece, v0, t1, t2);
 +        tcg_temp_free_vec(t1);
 +        tcg_temp_free_vec(t2);
 +        break;
 +
      default:
          g_assert_not_reached();
      }
 --
 .25.1

-[PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
+[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+GDB single-stepping is now handled generically.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     | 2 +-
+ target/microblaze/translate.c | 14 ++------------
- tcg/arm/tcg-target.c.inc | 6 ++++++
+file changed, 2 insertions(+), 12 deletions(-)
 files changed, 7 insertions(+), 1 deletion(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/microblaze/translate.c
-+++ b/tcg/arm/tcg-target.h
++++ b/target/microblaze/translate.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
- #define TCG_TARGET_HAS_shi_vec          1
- #define TCG_TARGET_HAS_shs_vec          0
+ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
- #define TCG_TARGET_HAS_shv_vec          0
+ {
--#define TCG_TARGET_HAS_mul_vec          0
+-    if (dc->base.singlestep_enabled) {
-+#define TCG_TARGET_HAS_mul_vec          1
+-        TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
- #define TCG_TARGET_HAS_sat_vec          0
+-        tcg_gen_movi_i32(cpu_pc, dest);
- #define TCG_TARGET_HAS_minmax_vec       0
+-        gen_helper_raise_exception(cpu_env, tmp);
- #define TCG_TARGET_HAS_bitsel_vec       0
+-        tcg_temp_free_i32(tmp);
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+-    } else if (translator_use_goto_tb(&dc->base, dest)) {
-index XXXXXXX..XXXXXXX 100644
++    if (translator_use_goto_tb(&dc->base, dest)) {
---- a/tcg/arm/tcg-target.c.inc
+         tcg_gen_goto_tb(n);
-+++ b/tcg/arm/tcg-target.c.inc
+         tcg_gen_movi_i32(cpu_pc, dest);
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+         tcg_gen_exit_tb(dc->base.tb, n);
-     INSN_VORN      = 0xf2300110,
+@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
-     INSN_VORR      = 0xf2200110,
+         /* Indirect jump (or direct jump w/ goto_tb disabled) */
-     INSN_VSUB      = 0xf3000800,
+         tcg_gen_mov_i32(cpu_pc, cpu_btarget);
-+    INSN_VMUL      = 0xf2000910,
+         tcg_gen_discard_i32(cpu_btarget);
+-
-     INSN_VABS      = 0xf3b10300,
+-        if (unlikely(cs->singlestep_enabled)) {
-     INSN_VMVN      = 0xf3b00580,
+-            gen_raise_exception(dc, EXCP_DEBUG);
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+-        } else {
-         return C_O1_I1(w, w);
+-            tcg_gen_lookup_and_goto_ptr();
-     case INDEX_op_dup2_vec:
+-        }
-     case INDEX_op_add_vec:
++        tcg_gen_lookup_and_goto_ptr();
 +    case INDEX_op_mul_vec:
      case INDEX_op_sub_vec:
      case INDEX_op_xor_vec:
          return C_O1_I2(w, w, w);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_add_vec:
          tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
          return;
-+    case INDEX_op_mul_vec:
 +        tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 +    case INDEX_op_mul_vec:
      case INDEX_op_neg_vec:
          return vece < MO_64;
      default:
 --
 .25.1

-[PULL 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
+[PULL 13/24] target/mips: Fix single stepping
-This is minimum and maximum, signed and unsigned.
+As per an ancient comment in mips_tr_translate_insn about the
 expectations of gdb, when restarting the insn in a delay slot
 we also re-execute the branch.  Which means that we are
 expected to execute two insns in this case.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+This has been broken since 8b86d6d2580, where we forced max_insns
 to 1 while single-stepping.  This resulted in an exit from the
 translator loop after the branch but before the delay slot is
 translated.
 Increase the max_insns to 2 for this case.  In addition, bypass
 the end-of-page check, for when the branch itself ends the page.
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ target/mips/tcg/translate.c | 25 ++++++++++++++++---------
- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
+file changed, 16 insertions(+), 9 deletions(-)
 files changed, 25 insertions(+), 1 deletion(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/mips/tcg/translate.c
-+++ b/tcg/arm/tcg-target.h
++++ b/target/mips/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- #define TCG_TARGET_HAS_shv_vec          0
+     ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
- #define TCG_TARGET_HAS_mul_vec          1
+                                   INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
- #define TCG_TARGET_HAS_sat_vec          1
--#define TCG_TARGET_HAS_minmax_vec       0
++    /*
-+#define TCG_TARGET_HAS_minmax_vec       1
++     * Execute a branch and its delay slot as a single instruction.
- #define TCG_TARGET_HAS_bitsel_vec       0
++     * This is what GDB expects and is consistent with what the
- #define TCG_TARGET_HAS_cmpsel_vec       0
++     * hardware does (e.g. if a delay slot instruction faults, the
++     * reported PC is the PC of the branch).
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
++     */
-index XXXXXXX..XXXXXXX 100644
++    if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
---- a/tcg/arm/tcg-target.c.inc
++        ctx->base.max_insns = 2;
-+++ b/tcg/arm/tcg-target.c.inc
++    }
-@@ -XXX,XX +XXX,XX @@ typedef enum {
++
-     INSN_VQADD_U   = 0xf3000010,
+     LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
-     INSN_VQSUB     = 0xf2000210,
+               ctx->hflags);
-     INSN_VQSUB_U   = 0xf3000210,
+ }
-+    INSN_VMAX      = 0xf2000600,
+@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
-+    INSN_VMAX_U    = 0xf3000600,
+     if (ctx->base.is_jmp != DISAS_NEXT) {
 +    INSN_VMIN      = 0xf2000610,
 +    INSN_VMIN_U    = 0xf3000610,
      INSN_VABS      = 0xf3b10300,
      INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
      case INDEX_op_mul_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
      case INDEX_op_ssadd_vec:
      case INDEX_op_sssub_vec:
      case INDEX_op_sub_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_mul_vec:
          tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
          return;
-+    case INDEX_op_smax_vec:
+     }
-+        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
++
-+        return;
+     /*
-+    case INDEX_op_smin_vec:
+-     * Execute a branch and its delay slot as a single instruction.
-+        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
+-     * This is what GDB expects and is consistent with what the
-+        return;
+-     * hardware does (e.g. if a delay slot instruction faults, the
-     case INDEX_op_sub_vec:
+-     * reported PC is the PC of the branch).
-         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
++     * End the TB on (most) page crossings.
-         return;
++     * See mips_tr_init_disas_context about single-stepping a branch
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
++     * together with its delay slot.
-     case INDEX_op_sssub_vec:
+      */
-         tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
+-    if (ctx->base.singlestep_enabled &&
-         return;
+-        (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
-+    case INDEX_op_umax_vec:
+-        ctx->base.is_jmp = DISAS_TOO_MANY;
-+        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
+-    }
-+        return;
+-    if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
-+    case INDEX_op_umin_vec:
++    if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
-+        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
++        && !ctx->base.singlestep_enabled) {
-+        return;
+         ctx->base.is_jmp = DISAS_TOO_MANY;
-     case INDEX_op_usadd_vec:
+     }
-         tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
+ }
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_cmp_vec:
      case INDEX_op_mul_vec:
      case INDEX_op_neg_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
          return vece < MO_64;
      default:
          return 0;
 --
 .25.1

-[PULL 03/15] tcg/arm: Implement tcg_out_ld/st for vector types
+[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+GDB single-stepping is now handled generically.
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
+ target/mips/tcg/translate.c | 50 +++++++++++++------------------------
-file changed, 64 insertions(+), 6 deletions(-)
+file changed, 18 insertions(+), 32 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/mips/tcg/translate.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/mips/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
-     INSN_NOP_v6k   = 0xe320f000,
+         tcg_gen_exit_tb(ctx->base.tb, n);
-     /* Otherwise the assembler uses mov r0,r0 */
+     } else {
-     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+         gen_save_pc(dest);
-+
+-        if (ctx->base.singlestep_enabled) {
-+    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+-            save_cpu_state(ctx, 0);
-+    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+-            gen_helper_raise_exception_debug(cpu_env);
- } ARMInsn;
+-        } else {
+-            tcg_gen_lookup_and_goto_ptr();
- #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
+-        }
-@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
++        tcg_gen_lookup_and_goto_ptr();
      }
  }
-+/*
+@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
-+ * Note that TCGReg references Q-registers.
+             } else {
-+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+                 tcg_gen_mov_tl(cpu_PC, btarget);
-+ */
+             }
-+static uint32_t encode_vd(TCGReg rd)
+-            if (ctx->base.singlestep_enabled) {
-+{
+-                save_cpu_state(ctx, 0);
-+    tcg_debug_assert(rd >= TCG_REG_Q0);
+-                gen_helper_raise_exception_debug(cpu_env);
-+    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+-            }
-+}
+             tcg_gen_lookup_and_goto_ptr();
-+
+             break;
-+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+         default:
-+                          TCGReg rd, TCGReg rn, int offset)
+@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
 +{
 +    if (offset != 0) {
 +        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
 +            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
 +                            TCG_REG_TMP, rn, offset, true);
 +        } else {
 +            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
 +            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
 +                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
 +        }
 +        rn = TCG_REG_TMP;
 +    }
 +    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
 +}
 +
  #ifdef CONFIG_SOFTMMU
  #include "../tcg-ldst.c.inc"
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
      tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
  }
 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
 -                              TCGReg arg1, intptr_t arg2)
 +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
 +                       TCGReg arg1, intptr_t arg2)
  {
--    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
-+    switch (type) {
-+    case TCG_TYPE_I32:
+-    if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
-+        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+-        save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
-+        return;
+-        gen_helper_raise_exception_debug(cpu_env);
-+    case TCG_TYPE_V64:
+-    } else {
-+        /* regs 1; size 8; align 8 */
+-        switch (ctx->base.is_jmp) {
-+        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
+-        case DISAS_STOP:
-+        return;
+-            gen_save_pc(ctx->base.pc_next);
-+    case TCG_TYPE_V128:
+-            tcg_gen_lookup_and_goto_ptr();
-+        /* regs 2; size 8; align 16 */
+-            break;
-+        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
+-        case DISAS_NEXT:
-+        return;
+-        case DISAS_TOO_MANY:
 -            save_cpu_state(ctx, 0);
 -            gen_goto_tb(ctx, 0, ctx->base.pc_next);
 -            break;
 -        case DISAS_EXIT:
 -            tcg_gen_exit_tb(NULL, 0);
 -            break;
 -        case DISAS_NORETURN:
 -            break;
 -        default:
 -            g_assert_not_reached();
 -        }
 +    switch (ctx->base.is_jmp) {
 +    case DISAS_STOP:
 +        gen_save_pc(ctx->base.pc_next);
 +        tcg_gen_lookup_and_goto_ptr();
 +        break;
 +    case DISAS_NEXT:
 +    case DISAS_TOO_MANY:
 +        save_cpu_state(ctx, 0);
 +        gen_goto_tb(ctx, 0, ctx->base.pc_next);
 +        break;
 +    case DISAS_EXIT:
 +        tcg_gen_exit_tb(NULL, 0);
 +        break;
 +    case DISAS_NORETURN:
 +        break;
 +    default:
 +        g_assert_not_reached();
-+    }
+     }
  }
--static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
--                              TCGReg arg1, intptr_t arg2)
-+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
-+                       TCGReg arg1, intptr_t arg2)
- {
--    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
-+    switch (type) {
-+    case TCG_TYPE_I32:
-+        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
-+        return;
-+    case TCG_TYPE_V64:
-+        /* regs 1; size 8; align 8 */
-+        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
-+        return;
-+    case TCG_TYPE_V128:
-+        /* regs 2; size 8; align 16 */
-+        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
-+        return;
-+    default:
-+        g_assert_not_reached();
-+    }
- }
- static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 --
 .25.1

-[PULL 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec
+[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled
-Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
+GDB single-stepping is now handled generically.
 For NEON, this is shift-right followed by shift-left-and-insert.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+ target/openrisc/translate.c | 18 +++---------------
- tcg/arm/tcg-target.opc.h     |  1 +
+file changed, 3 insertions(+), 15 deletions(-)
  tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
 files changed, 17 insertions(+)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/target/openrisc/translate.c
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/target/openrisc/translate.c
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
+@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
- C_O1_I2(r, r, rIN)
+             /* The jump destination is indirect/computed; use jmp_pc.  */
- C_O1_I2(r, r, ri)
+             tcg_gen_mov_tl(cpu_pc, jmp_pc);
- C_O1_I2(r, rZ, rZ)
+             tcg_gen_discard_tl(jmp_pc);
-+C_O1_I2(w, 0, w)
+-            if (unlikely(dc->base.singlestep_enabled)) {
- C_O1_I2(w, w, w)
+-                gen_exception(dc, EXCP_DEBUG);
- C_O1_I2(w, w, wO)
+-            } else {
- C_O1_I2(w, w, wV)
+-                tcg_gen_lookup_and_goto_ptr();
-diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
+-            }
-index XXXXXXX..XXXXXXX 100644
++            tcg_gen_lookup_and_goto_ptr();
---- a/tcg/arm/tcg-target.opc.h
+             break;
-+++ b/tcg/arm/tcg-target.opc.h
+         }
-@@ -XXX,XX +XXX,XX @@
+         /* The jump destination is direct; use jmp_pc_imm.
-  * consider these to be UNSPEC with names.
+@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
-  */
+             break;
+         }
-+DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
+         tcg_gen_movi_tl(cpu_pc, jmp_dest);
- DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+-        if (unlikely(dc->base.singlestep_enabled)) {
- DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
+-            gen_exception(dc, EXCP_DEBUG);
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+-        } else {
-index XXXXXXX..XXXXXXX 100644
+-            tcg_gen_lookup_and_goto_ptr();
---- a/tcg/arm/tcg-target.c.inc
+-        }
-+++ b/tcg/arm/tcg-target.c.inc
++        tcg_gen_lookup_and_goto_ptr();
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
      INSN_VSARI     = 0xf2800010,  /* VSHR.S */
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VSLI      = 0xf3800510,
      INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
      INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_arm_sshl_vec:
      case INDEX_op_arm_ushl_vec:
          return C_O1_I2(w, w, w);
 +    case INDEX_op_arm_sli_vec:
 +        return C_O1_I2(w, 0, w);
      case INDEX_op_or_vec:
      case INDEX_op_andc_vec:
          return C_O1_I2(w, w, wO);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sari_vec:
          tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
          return;
 +    case INDEX_op_arm_sli_vec:
 +        tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
 +        return;
      case INDEX_op_andc_vec:
          if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_shlv_vec:
      case INDEX_op_shrv_vec:
      case INDEX_op_sarv_vec:
 +    case INDEX_op_rotli_vec:
          return -1;
      default:
          return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
          tcg_temp_free_vec(t1);
          break;
-+    case INDEX_op_rotli_vec:
+     case DISAS_EXIT:
-+        t1 = tcg_temp_new_vec(type);
+-        if (unlikely(dc->base.singlestep_enabled)) {
-+        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
+-            gen_exception(dc, EXCP_DEBUG);
-+        vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
+-        } else {
-+                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
+-            tcg_gen_exit_tb(NULL, 0);
-+        tcg_temp_free_vec(t1);
+-        }
-+        break;
++        tcg_gen_exit_tb(NULL, 0);
-+
+         break;
      default:
          g_assert_not_reached();
-     }
 --
 .25.1

-[PULL 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec
+[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled
-This is saturating add and subtract, signed and unsigned.
+GDB single-stepping is now handled generically.
 Reuse gen_debug_exception to handle architectural debug exceptions.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ target/ppc/translate.c | 38 ++++++++------------------------------
- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
+file changed, 8 insertions(+), 30 deletions(-)
 files changed, 25 insertions(+), 1 deletion(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/target/ppc/translate.c b/target/ppc/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/ppc/translate.c
-+++ b/tcg/arm/tcg-target.h
++++ b/target/ppc/translate.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@
- #define TCG_TARGET_HAS_shs_vec          0
- #define TCG_TARGET_HAS_shv_vec          0
+ #define CPU_SINGLE_STEP 0x1
- #define TCG_TARGET_HAS_mul_vec          1
+ #define CPU_BRANCH_STEP 0x2
--#define TCG_TARGET_HAS_sat_vec          0
+-#define GDBSTUB_SINGLE_STEP 0x4
-+#define TCG_TARGET_HAS_sat_vec          1
- #define TCG_TARGET_HAS_minmax_vec       0
+ /* Include definitions for instructions classes and implementations flags */
- #define TCG_TARGET_HAS_bitsel_vec       0
+ /* #define PPC_DEBUG_DISAS */
- #define TCG_TARGET_HAS_cmpsel_vec       0
+@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
+ static void gen_debug_exception(DisasContext *ctx)
---- a/tcg/arm/tcg-target.c.inc
+ {
-+++ b/tcg/arm/tcg-target.c.inc
+-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
-@@ -XXX,XX +XXX,XX @@ typedef enum {
++    gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
-     INSN_VORR      = 0xf2200110,
+     ctx->base.is_jmp = DISAS_NORETURN;
-     INSN_VSUB      = 0xf3000800,
+ }
-     INSN_VMUL      = 0xf2000910,
-+    INSN_VQADD     = 0xf2000010,
+@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
-+    INSN_VQADD_U   = 0xf3000010,
-+    INSN_VQSUB     = 0xf2000210,
+ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
-+    INSN_VQSUB_U   = 0xf3000210,
+ {
+-    int sse = ctx->singlestep_enabled;
-     INSN_VABS      = 0xf3b10300,
+-    if (unlikely(sse)) {
-     INSN_VMVN      = 0xf3b00580,
+-        if (sse & GDBSTUB_SINGLE_STEP) {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+-            gen_debug_exception(ctx);
-     case INDEX_op_dup2_vec:
+-        } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
-     case INDEX_op_add_vec:
+-            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
-     case INDEX_op_mul_vec:
+-        } else {
-+    case INDEX_op_ssadd_vec:
+-            tcg_gen_exit_tb(NULL, 0);
-+    case INDEX_op_sssub_vec:
+-        }
-     case INDEX_op_sub_vec:
++    if (unlikely(ctx->singlestep_enabled)) {
-+    case INDEX_op_usadd_vec:
++        gen_debug_exception(ctx);
-+    case INDEX_op_ussub_vec:
+     } else {
-     case INDEX_op_xor_vec:
+         tcg_gen_lookup_and_goto_ptr();
-         return C_O1_I2(w, w, w);
+     }
-     case INDEX_op_or_vec:
+@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     ctx->singlestep_enabled = 0;
-     case INDEX_op_sub_vec:
+     if ((hflags >> HFLAGS_SE) & 1) {
-         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+         ctx->singlestep_enabled |= CPU_SINGLE_STEP;
-         return;
++        ctx->base.max_insns = 1;
-+    case INDEX_op_ssadd_vec:
+     }
-+        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
+     if ((hflags >> HFLAGS_BE) & 1) {
          ctx->singlestep_enabled |= CPU_BRANCH_STEP;
      }
 -    if (unlikely(ctx->base.singlestep_enabled)) {
 -        ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
 -    }
 -
 -    if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
 -        ctx->base.max_insns = 1;
 -    }
  }
  static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
      DisasContext *ctx = container_of(dcbase, DisasContext, base);
      DisasJumpType is_jmp = ctx->base.is_jmp;
      target_ulong nip = ctx->base.pc_next;
 -    int sse;
      if (is_jmp == DISAS_NORETURN) {
          /* We have already exited the TB. */
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
      }
      /* Honor single stepping. */
 -    sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
 -    if (unlikely(sse)) {
 +    if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
 +        && (nip <= 0x100 || nip > 0xf00)) {
          switch (is_jmp) {
          case DISAS_TOO_MANY:
          case DISAS_EXIT_UPDATE:
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
              g_assert_not_reached();
          }
 -        if (sse & GDBSTUB_SINGLE_STEP) {
 -            gen_debug_exception(ctx);
 -            return;
 -        }
 -        /* else CPU_SINGLE_STEP... */
 -        if (nip <= 0x100 || nip > 0xf00) {
 -            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
 -            return;
 -        }
 +        gen_debug_exception(ctx);
 +        return;
-+    case INDEX_op_sssub_vec:
+     }
-+        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
-+        return;
+     switch (is_jmp) {
 +    case INDEX_op_usadd_vec:
 +        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_ussub_vec:
 +        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_shli_vec:
      case INDEX_op_shri_vec:
      case INDEX_op_sari_vec:
 +    case INDEX_op_ssadd_vec:
 +    case INDEX_op_sssub_vec:
 +    case INDEX_op_usadd_vec:
 +    case INDEX_op_ussub_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
 .25.1

-[PULL 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec
+[PULL 17/24] target/riscv: Remove dead code after exception
-The three vector shift by vector operations are all implemented via
+We have already set DISAS_NORETURN in generate_exception,
-expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
+which makes the exit_tb unreachable.
 as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
 instruction stream, and therefore also do not appear in tcg_target_op_def.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.opc.h |  3 ++
+ target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
- tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
+file changed, 1 insertion(+), 5 deletions(-)
 files changed, 63 insertions(+), 1 deletion(-)
-diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.opc.h
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/tcg/arm/tcg-target.opc.h
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
-  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
+ {
-  * consider these to be UNSPEC with names.
+     /* always generates U-level ECALL, fixed in do_interrupt handler */
-  */
+     generate_exception(ctx, RISCV_EXCP_U_ECALL);
-+
+-    exit_tb(ctx); /* no chaining */
-+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+-    ctx->base.is_jmp = DISAS_NORETURN;
-+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
+     return true;
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+ }
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
-+++ b/tcg/arm/tcg-target.c.inc
+         post   = opcode_at(&ctx->base, post_addr);
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
      INSN_VSARI     = 0xf2800010,  /* VSHR.S */
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
 +    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
      INSN_VBSL      = 0xf3100110,
      INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
 +    case INDEX_op_arm_sshl_vec:
 +    case INDEX_op_arm_ushl_vec:
          return C_O1_I2(w, w, w);
      case INDEX_op_or_vec:
      case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_arm_sshl_vec:
 +        /*
 +         * Note that Vm is the data and Vn is the shift count,
 +         * therefore the arguments appear reversed.
 +         */
 +        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
 +        return;
 +    case INDEX_op_arm_ushl_vec:
 +        /* See above. */
 +        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
 +        return;
      case INDEX_op_shli_vec:
          tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_umax_vec:
      case INDEX_op_umin_vec:
          return vece < MO_64;
 +    case INDEX_op_shlv_vec:
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        return -1;
      default:
          return 0;
      }
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
- void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+-    if  (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
-                        TCGArg a0, ...)
++    if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
- {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
--    g_assert_not_reached();
+     } else {
-+    va_list va;
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-+    TCGv_vec v0, v1, v2, t1;
+     }
-+    TCGArg a2;
+-    exit_tb(ctx); /* no chaining */
-+
+-    ctx->base.is_jmp = DISAS_NORETURN;
-+    va_start(va, a0);
+     return true;
 +    v0 = temp_tcgv_vec(arg_temp(a0));
 +    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
 +    a2 = va_arg(va, TCGArg);
 +    va_end(va);
 +
 +    switch (opc) {
 +    case INDEX_op_shlv_vec:
 +        /*
 +         * Merely propagate shlv_vec to arm_ushl_vec.
 +         * In this way we don't set TCG_TARGET_HAS_shv_vec
 +         * because everything is done via expansion.
 +         */
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
 +        break;
 +
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        /* Right shifts are negative left shifts for NEON.  */
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        t1 = tcg_temp_new_vec(type);
 +        tcg_gen_neg_vec(vece, t1, v2);
 +        if (opc == INDEX_op_shrv_vec) {
 +            opc = INDEX_op_arm_ushl_vec;
 +        } else {
 +            opc = INDEX_op_arm_sshl_vec;
 +        }
 +        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
 +        tcg_temp_free_vec(t1);
 +        break;
 +
 +    default:
 +        g_assert_not_reached();
 +    }
  }
- static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 --
 .25.1

-[PULL 01/15] tcg: Change parameters for tcg_target_const_match
+[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr
-Change the return value to bool, because that's what is should
+GDB single-stepping is now handled generically, which means
-have been from the start.  Pass the ct mask instead of the whole
+we don't need to do anything in the wrappers.
 TCGArgConstraint, as that's the only part that's relevant.
-Change the value argument to int64_t.  We will need the extra
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 width for 32-bit hosts wanting to match vector constants.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/tcg.c                    | 5 ++---
+ target/riscv/translate.c                      | 27 +------------------
- tcg/aarch64/tcg-target.c.inc | 5 +----
+ .../riscv/insn_trans/trans_privileged.c.inc   |  4 +--
- tcg/arm/tcg-target.c.inc     | 5 +----
+ target/riscv/insn_trans/trans_rvi.c.inc       |  8 +++---
- tcg/i386/tcg-target.c.inc    | 4 +---
+ target/riscv/insn_trans/trans_rvv.c.inc       |  2 +-
- tcg/mips/tcg-target.c.inc    | 5 +----
+files changed, 7 insertions(+), 34 deletions(-)
  tcg/ppc/tcg-target.c.inc     | 4 +---
  tcg/riscv/tcg-target.c.inc   | 4 +---
  tcg/s390/tcg-target.c.inc    | 5 +----
  tcg/sparc/tcg-target.c.inc   | 5 +----
  tcg/tci/tcg-target.c.inc     | 6 ++----
 files changed, 12 insertions(+), 36 deletions(-)
-diff --git a/tcg/tcg.c b/tcg/tcg.c
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
+--- a/target/riscv/translate.c
-+++ b/tcg/tcg.c
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
+@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
- static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+     ctx->base.is_jmp = DISAS_NORETURN;
-                         TCGReg base, intptr_t ofs);
+ }
- static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
+-static void gen_exception_debug(void)
--                                  const TCGArgConstraint *arg_ct);
+-{
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
+-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
- #ifdef TCG_TARGET_NEED_LDST_LABELS
+-}
- static int tcg_out_ldst_finalize(TCGContext *s);
+-
- #endif
+-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
+-static void exit_tb(DisasContext *ctx)
-         ts = arg_temp(arg);
+-{
+-    if (ctx->base.singlestep_enabled) {
-         if (ts->val_type == TEMP_VAL_CONST
+-        gen_exception_debug();
--            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+-    } else {
-+            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
+-        tcg_gen_exit_tb(NULL, 0);
-             /* constant is OK for instruction */
+-    }
-             const_args[i] = 1;
+-}
-             new_args[i] = ts->val;
+-
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
+-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
-index XXXXXXX..XXXXXXX 100644
+-static void lookup_and_goto_ptr(DisasContext *ctx)
---- a/tcg/aarch64/tcg-target.c.inc
+-{
-+++ b/tcg/aarch64/tcg-target.c.inc
+-    if (ctx->base.singlestep_enabled) {
-@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+-        gen_exception_debug();
 -    } else {
 -        tcg_gen_lookup_and_goto_ptr();
 -    }
 -}
 -
  static void gen_exception_illegal(DisasContext *ctx)
  {
      generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
          tcg_gen_exit_tb(ctx->base.tb, n);
      } else {
          tcg_gen_movi_tl(cpu_pc, dest);
 -        lookup_and_goto_ptr(ctx);
 +        tcg_gen_lookup_and_goto_ptr();
      }
  }
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
--                                  const TCGArgConstraint *arg_ct)
+index XXXXXXX..XXXXXXX 100644
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
 +++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
      if (has_ext(ctx, RVS)) {
          gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
 -        exit_tb(ctx); /* no chaining */
 +        tcg_gen_exit_tb(NULL, 0); /* no chaining */
          ctx->base.is_jmp = DISAS_NORETURN;
      } else {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
  #ifndef CONFIG_USER_ONLY
      tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
      gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
 -    exit_tb(ctx); /* no chaining */
 +    tcg_gen_exit_tb(NULL, 0); /* no chaining */
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
  #else
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
      if (a->rd != 0) {
          tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
      }
 -
 -    /* No chaining with JALR. */
 -    lookup_and_goto_ptr(ctx);
 +    tcg_gen_lookup_and_goto_ptr();
      if (misaligned) {
          gen_set_label(misaligned);
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
       * however we need to end the translation block
       */
      tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
 -    exit_tb(ctx);
 +    tcg_gen_exit_tb(NULL, 0);
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
  {
--    int ct = arg_ct->ct;
+     /* We may have changed important cpu state -- exit to main loop. */
--
+     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-     if (ct & TCG_CT_CONST) {
+-    exit_tb(ctx);
-         return 1;
++    tcg_gen_exit_tb(NULL, 0);
-     }
+     ctx->base.is_jmp = DISAS_NORETURN;
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+     return true;
  }
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
+@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
-  * mov operand2:     values represented with x << (2 * y), x < 0x100
+     gen_set_gpr(ctx, a->rd, dst);
-  * add, sub, eor...: ditto
-  */
+     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
--static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+-    lookup_and_goto_ptr(ctx);
--                                         const TCGArgConstraint *arg_ct)
++    tcg_gen_lookup_and_goto_ptr();
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+     ctx->base.is_jmp = DISAS_NORETURN;
- {
+     return true;
 -    int ct;
 -    ct = arg_ct->ct;
      if (ct & TCG_CT_CONST) {
          return 1;
      } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  }
- /* test if a constant matches the constraint */
--static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                         const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct = arg_ct->ct;
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
-diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.c.inc
-+++ b/tcg/mips/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
- }
- /* test if a constant matches the constraint */
--static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                         const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct;
--    ct = arg_ct->ct;
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
-diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.c.inc
-+++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
- }
- /* test if a constant matches the constraint */
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                  const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct = arg_ct->ct;
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
- }
- /* test if a constant matches the constraint */
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                  const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct = arg_ct->ct;
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
-diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.c.inc
-+++ b/tcg/s390/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
- }
- /* Test if a constant matches the constraint. */
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                  const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct = arg_ct->ct;
--
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
-diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.c.inc
-+++ b/tcg/sparc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
- }
- /* test if a constant matches the constraint */
--static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                         const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    int ct = arg_ct->ct;
--
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- }
- /* Test if a constant matches the constraint. */
--static int tcg_target_const_match(tcg_target_long val, TCGType type,
--                                  const TCGArgConstraint *arg_ct)
-+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- {
--    /* No need to return 0 or 1, 0 or != 0 is good enough. */
--    return arg_ct->ct & TCG_CT_CONST;
-+    return ct & TCG_CT_CONST;
- }
- static void tcg_target_init(TCGContext *s)
 --
 .25.1

-[PULL 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec
+[PULL 19/24] target/rx: Drop checks for singlestep_enabled
-This consists of the three immediate shifts: shli, shri, sari.
+GDB single-stepping is now handled generically.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ target/rx/helper.h    |  1 -
- tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
+ target/rx/op_helper.c |  8 --------
-files changed, 28 insertions(+), 1 deletion(-)
+ target/rx/translate.c | 12 ++----------
 files changed, 2 insertions(+), 19 deletions(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/target/rx/helper.h b/target/rx/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/rx/helper.h
-+++ b/tcg/arm/tcg-target.h
++++ b/target/rx/helper.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
- #define TCG_TARGET_HAS_roti_vec         0
+ DEF_HELPER_1(raise_access_fault, noreturn, env)
- #define TCG_TARGET_HAS_rots_vec         0
+ DEF_HELPER_1(raise_privilege_violation, noreturn, env)
- #define TCG_TARGET_HAS_rotv_vec         0
+ DEF_HELPER_1(wait, noreturn, env)
--#define TCG_TARGET_HAS_shi_vec          0
+-DEF_HELPER_1(debug, noreturn, env)
-+#define TCG_TARGET_HAS_shi_vec          1
+ DEF_HELPER_2(rxint, noreturn, env, i32)
- #define TCG_TARGET_HAS_shs_vec          0
+ DEF_HELPER_1(rxbrk, noreturn, env)
- #define TCG_TARGET_HAS_shv_vec          0
+ DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
- #define TCG_TARGET_HAS_mul_vec          0
+diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/rx/op_helper.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/rx/op_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
-     INSN_VCGE_U    = 0xf3000310,
+     raise_exception(env, EXCP_HLT, 0);
      INSN_VCGT_U    = 0xf3000300,
 +    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
 +    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
 +    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +
      INSN_VTST      = 0xf2000810,
      INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
                | (extract32(imm8, 7, 1) << 24));
  }
-+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+-void QEMU_NORETURN helper_debug(CPURXState *env)
-+                            TCGReg rd, TCGReg rm, int l_imm6)
+-{
-+{
+-    CPUState *cs = env_cpu(env);
-+    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
+-
-+              (extract32(l_imm6, 6, 1) << 7) |
+-    cs->exception_index = EXCP_DEBUG;
-+              (extract32(l_imm6, 0, 6) << 16));
+-    cpu_loop_exit(cs);
-+}
+-}
-+
+-
- static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+ void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
                            TCGReg rd, TCGReg rn, int offset)
  {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     raise_exception(env, 0x100 + vec, 0);
-     case INDEX_op_abs_vec:
+diff --git a/target/rx/translate.c b/target/rx/translate.c
-     case INDEX_op_neg_vec:
+index XXXXXXX..XXXXXXX 100644
-     case INDEX_op_not_vec:
+--- a/target/rx/translate.c
-+    case INDEX_op_shli_vec:
++++ b/target/rx/translate.c
-+    case INDEX_op_shri_vec:
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
-+    case INDEX_op_sari_vec:
+         tcg_gen_exit_tb(dc->base.tb, n);
-         return C_O1_I1(w, w);
+     } else {
-     case INDEX_op_dup2_vec:
+         tcg_gen_movi_i32(cpu_pc, dest);
-     case INDEX_op_add_vec:
+-        if (dc->base.singlestep_enabled) {
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+-            gen_helper_debug(cpu_env);
-     case INDEX_op_xor_vec:
+-        } else {
-         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+-            tcg_gen_lookup_and_goto_ptr();
-         return;
+-        }
-+    case INDEX_op_shli_vec:
++        tcg_gen_lookup_and_goto_ptr();
-+        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
+     }
-+        return;
+     dc->base.is_jmp = DISAS_NORETURN;
-+    case INDEX_op_shri_vec:
+ }
-+        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
+@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
-+        return;
+         gen_goto_tb(ctx, 0, dcbase->pc_next);
-+    case INDEX_op_sari_vec:
+         break;
-+        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
+     case DISAS_JUMP:
-+        return;
+-        if (ctx->base.singlestep_enabled) {
+-            gen_helper_debug(cpu_env);
-     case INDEX_op_andc_vec:
+-        } else {
-         if (!const_args[2]) {
+-            tcg_gen_lookup_and_goto_ptr();
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+-        }
-     case INDEX_op_orc_vec:
++        tcg_gen_lookup_and_goto_ptr();
-     case INDEX_op_xor_vec:
+         break;
-     case INDEX_op_not_vec:
+     case DISAS_UPDATE:
-+    case INDEX_op_shli_vec:
+         tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
 +    case INDEX_op_shri_vec:
 +    case INDEX_op_sari_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
 .25.1

-[PULL 05/15] tcg/arm: Implement tcg_out_dup*_vec
+[PULL 20/24] target/s390x: Drop check for singlestep_enabled
-Most of dupi is copied from tcg/aarch64, which has the same
+GDB single-stepping is now handled generically.
 encoding for AdvSimdExpandImm.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
+ target/s390x/tcg/translate.c | 8 ++------
-file changed, 275 insertions(+), 8 deletions(-)
+file changed, 2 insertions(+), 6 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/s390x/tcg/translate.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/s390x/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ struct DisasContext {
+     uint64_t pc_tmp;
-     INSN_VORR      = 0xf2200110,
+     uint32_t ilen;
+     enum cc_op cc_op;
-+    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+-    bool do_debug;
 +    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
 +    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
      INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
 +    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
      INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 +    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
  } ARMInsn;
  #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
      [TCG_COND_GTU] = COND_HI,
  };
-+static int encode_imm(uint32_t imm);
+ /* Information carried about a condition to be evaluated.  */
-+
+@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-+/* TCG private relocation type: add with pc+imm8 */
-+#define R_ARM_PC8  11
+     dc->cc_op = CC_OP_DYNAMIC;
-+
+     dc->ex_value = dc->base.tb->cs_base;
-+/* TCG private relocation type: vldr with imm8 << 2 */
+-    dc->do_debug = dc->base.singlestep_enabled;
 +#define R_ARM_PC11 12
 +
  static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
  {
      const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
      return false;
  }
-+static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
-+{
+@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
-+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+         /* FALLTHRU */
-+    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
+     case DISAS_PC_CC_UPDATED:
-+
+         /* Exit the TB, either by raising a debug exception or by return.  */
-+    if (offset >= -0xff && offset <= 0xff) {
+-        if (dc->do_debug) {
-+        tcg_insn_unit insn = *src_rw;
+-            gen_exception(EXCP_DEBUG);
-+        bool u = (offset >= 0);
+-        } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
-+        if (!u) {
+-                   dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
-+            offset = -offset;
++        if ((dc->base.tb->flags & FLAG_MASK_PER) ||
-+        }
++             dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
-+        insn = deposit32(insn, 23, 1, u);
+             tcg_gen_exit_tb(NULL, 0);
-+        insn = deposit32(insn, 0, 8, offset);
+         } else {
-+        *src_rw = insn;
+             tcg_gen_lookup_and_goto_ptr();
 +        return true;
 +    }
 +    return false;
 +}
 +
 +static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 +{
 +    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
 +    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
 +    int rot = encode_imm(offset);
 +
 +    if (rot >= 0) {
 +        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
 +        return true;
 +    }
 +    return false;
 +}
 +
  static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                          intptr_t value, intptr_t addend)
  {
      tcg_debug_assert(addend == 0);
 -
 -    if (type == R_ARM_PC24) {
 +    switch (type) {
 +    case R_ARM_PC24:
          return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
 -    } else if (type == R_ARM_PC13) {
 +    case R_ARM_PC13:
          return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
 -    } else {
 +    case R_ARM_PC11:
 +        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
 +    case R_ARM_PC8:
 +        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
 +    default:
          g_assert_not_reached();
      }
  }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
  /* ARM immediates for ALU instructions are made of an unsigned 8-bit
     right-rotated by an even amount between 0 and 30. */
 -static inline int encode_imm(uint32_t imm)
 +static int encode_imm(uint32_t imm)
  {
      int shift;
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
      return encode_imm(imm) >= 0;
  }
 +/* Return true if v16 is a valid 16-bit shifted immediate.  */
 +static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
 +{
 +    if (v16 == (v16 & 0xff)) {
 +        *cmode = 0x8;
 +        *imm8 = v16 & 0xff;
 +        return true;
 +    } else if (v16 == (v16 & 0xff00)) {
 +        *cmode = 0xa;
 +        *imm8 = v16 >> 8;
 +        return true;
 +    }
 +    return false;
 +}
 +
 +/* Return true if v32 is a valid 32-bit shifted immediate.  */
 +static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
 +{
 +    if (v32 == (v32 & 0xff)) {
 +        *cmode = 0x0;
 +        *imm8 = v32 & 0xff;
 +        return true;
 +    } else if (v32 == (v32 & 0xff00)) {
 +        *cmode = 0x2;
 +        *imm8 = (v32 >> 8) & 0xff;
 +        return true;
 +    } else if (v32 == (v32 & 0xff0000)) {
 +        *cmode = 0x4;
 +        *imm8 = (v32 >> 16) & 0xff;
 +        return true;
 +    } else if (v32 == (v32 & 0xff000000)) {
 +        *cmode = 0x6;
 +        *imm8 = v32 >> 24;
 +        return true;
 +    }
 +    return false;
 +}
 +
 +/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
 +static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
 +{
 +    if ((v32 & 0xffff00ff) == 0xff) {
 +        *cmode = 0xc;
 +        *imm8 = (v32 >> 8) & 0xff;
 +        return true;
 +    } else if ((v32 & 0xff00ffff) == 0xffff) {
 +        *cmode = 0xd;
 +        *imm8 = (v32 >> 16) & 0xff;
 +        return true;
 +    }
 +    return false;
 +}
 +
 +/*
 + * Return non-zero if v32 can be formed by MOVI+ORR.
 + * Place the parameters for MOVI in (cmode, imm8).
 + * Return the cmode for ORR; the imm8 can be had via extraction from v32.
 + */
 +static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
 +{
 +    int i;
 +
 +    for (i = 6; i > 0; i -= 2) {
 +        /* Mask out one byte we can add with ORR.  */
 +        uint32_t tmp = v32 & ~(0xffu << (i * 4));
 +        if (is_shimm32(tmp, cmode, imm8) ||
 +            is_soimm32(tmp, cmode, imm8)) {
 +            break;
 +        }
 +    }
 +    return i;
 +}
 +
  /* Test if a constant matches the constraint.
   * TODO: define constraints for:
   *
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                encode_vd(d) | encode_vn(n) | encode_vm(m));
  }
 +static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
 +                          int q, int op, int cmode, uint8_t imm8)
 +{
 +    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
 +              | (cmode << 8) | extract32(imm8, 0, 4)
 +              | (extract32(imm8, 4, 3) << 16)
 +              | (extract32(imm8, 7, 1) << 24));
 +}
 +
  static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                            TCGReg rd, TCGReg rn, int offset)
  {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
      tcg_out_movi32(s, COND_AL, ret, arg);
  }
 +/* Type is always V128, with I64 elements.  */
 +static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
 +{
 +    /* Move high element into place first. */
 +    /* VMOV Dd+1, Ds */
 +    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
 +    /* Move low element into place; tcg_out_mov will check for nop. */
 +    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
 +}
 +
  static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, TCGReg rs)
  {
 -    g_assert_not_reached();
 +    int q = type - TCG_TYPE_V64;
 +
 +    if (vece == MO_64) {
 +        if (type == TCG_TYPE_V128) {
 +            tcg_out_dup2_vec(s, rd, rs, rs);
 +        } else {
 +            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
 +        }
 +    } else if (rs < TCG_REG_Q0) {
 +        int b = (vece == MO_8);
 +        int e = (vece == MO_16);
 +        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
 +                  encode_vn(rd) | (rs << 12));
 +    } else {
 +        int imm4 = 1 << vece;
 +        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
 +                  encode_vd(rd) | encode_vm(rs));
 +    }
 +    return true;
  }
  static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                               TCGReg rd, TCGReg base, intptr_t offset)
  {
 -    g_assert_not_reached();
 +    if (vece == MO_64) {
 +        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
 +        if (type == TCG_TYPE_V128) {
 +            tcg_out_dup2_vec(s, rd, rd, rd);
 +        }
 +    } else {
 +        int q = type - TCG_TYPE_V64;
 +        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
 +                      rd, base, offset);
 +    }
 +    return true;
  }
  static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                               TCGReg rd, int64_t v64)
  {
 -    g_assert_not_reached();
 +    int q = type - TCG_TYPE_V64;
 +    int cmode, imm8, i;
 +
 +    /* Test all bytes equal first.  */
 +    if (vece == MO_8) {
 +        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
 +        return;
 +    }
 +
 +    /*
 +     * Test all bytes 0x00 or 0xff second.  This can match cases that
 +     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
 +     */
 +    for (i = imm8 = 0; i < 8; i++) {
 +        uint8_t byte = v64 >> (i * 8);
 +        if (byte == 0xff) {
 +            imm8 |= 1 << i;
 +        } else if (byte != 0) {
 +            goto fail_bytes;
 +        }
 +    }
 +    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
 +    return;
 + fail_bytes:
 +
 +    /*
 +     * Tests for various replications.  For each element width, if we
 +     * cannot find an expansion there's no point checking a larger
 +     * width because we already know by replication it cannot match.
 +     */
 +    if (vece == MO_16) {
 +        uint16_t v16 = v64;
 +
 +        if (is_shimm16(v16, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            return;
 +        }
 +        if (is_shimm16(~v16, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            return;
 +        }
 +
 +        /*
 +         * Otherwise, all remaining constants can be loaded in two insns:
 +         * rd = v16 & 0xff, rd |= v16 & 0xff00.
 +         */
 +        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
 +        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
 +        return;
 +    }
 +
 +    if (vece == MO_32) {
 +        uint32_t v32 = v64;
 +
 +        if (is_shimm32(v32, &cmode, &imm8) ||
 +            is_soimm32(v32, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            return;
 +        }
 +        if (is_shimm32(~v32, &cmode, &imm8) ||
 +            is_soimm32(~v32, &cmode, &imm8)) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            return;
 +        }
 +
 +        /*
 +         * Restrict the set of constants to those we can load with
 +         * two instructions.  Others we load from the pool.
 +         */
 +        i = is_shimm32_pair(v32, &cmode, &imm8);
 +        if (i) {
 +            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
 +            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
 +            return;
 +        }
 +        i = is_shimm32_pair(~v32, &cmode, &imm8);
 +        if (i) {
 +            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
 +            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
 +            return;
 +        }
 +    }
 +
 +    /*
 +     * As a last resort, load from the constant pool.
 +     */
 +    if (!q || vece == MO_64) {
 +        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
 +        /* VLDR Dd, [pc + offset] */
 +        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
 +        if (q) {
 +            tcg_out_dup2_vec(s, rd, rd, rd);
 +        }
 +    } else {
 +        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
 +        /* add tmp, pc, offset */
 +        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
 +        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
 +    }
  }
  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
 --
 .25.1

-[PULL 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations
+[PULL 21/24] target/sh4: Drop check for singlestep_enabled
-These logical and arithmetic operations are optional, but are
+GDB single-stepping is now handled generically.
 trivial to accomplish with the existing infrastructure.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+ target/sh4/helper.h    |  1 -
- tcg/arm/tcg-target.h         | 10 +++++-----
+ target/sh4/op_helper.c |  5 -----
- tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
+ target/sh4/translate.c | 14 +++-----------
-files changed, 44 insertions(+), 5 deletions(-)
+files changed, 3 insertions(+), 17 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/target/sh4/helper.h b/target/sh4/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/target/sh4/helper.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/target/sh4/helper.h
-@@ -XXX,XX +XXX,XX @@ C_O0_I4(s, s, s, s)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
- C_O1_I1(r, l)
+ DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
- C_O1_I1(r, r)
+ DEF_HELPER_1(raise_fpu_disable, noreturn, env)
- C_O1_I1(w, r)
+ DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
-+C_O1_I1(w, w)
+-DEF_HELPER_1(debug, noreturn, env)
- C_O1_I1(w, wr)
+ DEF_HELPER_1(sleep, noreturn, env)
- C_O1_I2(r, 0, rZ)
+ DEF_HELPER_2(trapa, noreturn, env, i32)
- C_O1_I2(r, l, l)
+ DEF_HELPER_1(exclusive, noreturn, env)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/sh4/op_helper.c
-+++ b/tcg/arm/tcg-target.h
++++ b/target/sh4/op_helper.c
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
- #define TCG_TARGET_HAS_v128             use_neon_instructions
+     raise_exception(env, 0x820, 0);
- #define TCG_TARGET_HAS_v256             0
+ }
--#define TCG_TARGET_HAS_andc_vec         0
+-void helper_debug(CPUSH4State *env)
--#define TCG_TARGET_HAS_orc_vec          0
+-{
--#define TCG_TARGET_HAS_not_vec          0
+-    raise_exception(env, EXCP_DEBUG, 0);
--#define TCG_TARGET_HAS_neg_vec          0
+-}
--#define TCG_TARGET_HAS_abs_vec          0
+-
-+#define TCG_TARGET_HAS_andc_vec         1
+ void helper_sleep(CPUSH4State *env)
-+#define TCG_TARGET_HAS_orc_vec          1
+ {
-+#define TCG_TARGET_HAS_not_vec          1
+     CPUState *cs = env_cpu(env);
-+#define TCG_TARGET_HAS_neg_vec          1
+diff --git a/target/sh4/translate.c b/target/sh4/translate.c
 +#define TCG_TARGET_HAS_abs_vec          1
  #define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_rots_vec         0
  #define TCG_TARGET_HAS_rotv_vec         0
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/target/sh4/translate.c
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/target/sh4/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+         tcg_gen_exit_tb(ctx->base.tb, n);
-     INSN_VADD      = 0xf2000800,
+     } else {
-     INSN_VAND      = 0xf2000110,
+         tcg_gen_movi_i32(cpu_pc, dest);
-+    INSN_VBIC      = 0xf2100110,
+-        if (ctx->base.singlestep_enabled) {
-     INSN_VEOR      = 0xf3000110,
+-            gen_helper_debug(cpu_env);
-+    INSN_VORN      = 0xf2300110,
+-        } else if (use_exit_tb(ctx)) {
-     INSN_VORR      = 0xf2200110,
++        if (use_exit_tb(ctx)) {
-     INSN_VSUB      = 0xf3000800,
+             tcg_gen_exit_tb(NULL, 0);
+         } else {
-+    INSN_VABS      = 0xf3b10300,
+             tcg_gen_lookup_and_goto_ptr();
-     INSN_VMVN      = 0xf3b00580,
+@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
-+    INSN_VNEG      = 0xf3b10380,
+        delayed jump as immediate jump are conditinal jumps */
+     tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
-     INSN_VCEQ0     = 0xf3b10100,
+         tcg_gen_discard_i32(cpu_delayed_pc);
-     INSN_VCGT0     = 0xf3b10000,
+-        if (ctx->base.singlestep_enabled) {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+-            gen_helper_debug(cpu_env);
-         return C_O1_I1(w, r);
+-        } else if (use_exit_tb(ctx)) {
-     case INDEX_op_dup_vec:
++        if (use_exit_tb(ctx)) {
-         return C_O1_I1(w, wr);
+             tcg_gen_exit_tb(NULL, 0);
-+    case INDEX_op_abs_vec:
+         } else {
-+    case INDEX_op_neg_vec:
+             tcg_gen_lookup_and_goto_ptr();
-+    case INDEX_op_not_vec:
+@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
-+        return C_O1_I1(w, w);
+     switch (ctx->base.is_jmp) {
-     case INDEX_op_dup2_vec:
+     case DISAS_STOP:
-     case INDEX_op_add_vec:
+         gen_save_cpu_state(ctx, true);
-     case INDEX_op_sub_vec:
+-        if (ctx->base.singlestep_enabled) {
-     case INDEX_op_xor_vec:
+-            gen_helper_debug(cpu_env);
-         return C_O1_I2(w, w, w);
+-        } else {
-     case INDEX_op_or_vec:
+-            tcg_gen_exit_tb(NULL, 0);
-+    case INDEX_op_andc_vec:
+-        }
-         return C_O1_I2(w, w, wO);
++        tcg_gen_exit_tb(NULL, 0);
-     case INDEX_op_and_vec:
+         break;
-+    case INDEX_op_orc_vec:
+     case DISAS_NEXT:
-         return C_O1_I2(w, w, wV);
+     case DISAS_TOO_MANY:
      case INDEX_op_cmp_vec:
          return C_O1_I2(w, w, wZ);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_dup2_vec:
          tcg_out_dup2_vec(s, a0, a1, a2);
          return;
 +    case INDEX_op_abs_vec:
 +        tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
 +        return;
 +    case INDEX_op_neg_vec:
 +        tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
 +        return;
 +    case INDEX_op_not_vec:
 +        tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
 +        return;
      case INDEX_op_add_vec:
          tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_andc_vec:
 +        if (!const_args[2]) {
 +            tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
 +            return;
 +        }
 +        a2 = ~a2;
 +        /* fall through */
      case INDEX_op_and_vec:
          if (const_args[2]) {
              is_shimm1632(~a2, &cmode, &imm8);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_orc_vec:
 +        if (!const_args[2]) {
 +            tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
 +            return;
 +        }
 +        a2 = ~a2;
 +        /* fall through */
      case INDEX_op_or_vec:
          if (const_args[2]) {
              is_shimm1632(a2, &cmode, &imm8);
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_add_vec:
      case INDEX_op_sub_vec:
      case INDEX_op_and_vec:
 +    case INDEX_op_andc_vec:
      case INDEX_op_or_vec:
 +    case INDEX_op_orc_vec:
      case INDEX_op_xor_vec:
 +    case INDEX_op_not_vec:
          return 1;
 +    case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 +    case INDEX_op_neg_vec:
          return vece < MO_64;
      default:
          return 0;
 --
 .25.1

-[PULL 06/15] tcg/arm: Implement minimal vector operations
+[PULL 22/24] target/tricore: Drop check for singlestep_enabled
-Implementing dup2, add, sub, and, or, xor as the minimal set.
+GDB single-stepping is now handled generically.
 This allows us to actually enable neon in the header file.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |   3 +
+ target/tricore/helper.h    |  1 -
- tcg/arm/tcg-target-con-str.h |   2 +
+ target/tricore/op_helper.c |  7 -------
- tcg/arm/tcg-target.h         |   6 +-
+ target/tricore/translate.c | 14 +-------------
- tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
+files changed, 1 insertion(+), 21 deletions(-)
 files changed, 204 insertions(+), 8 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/target/tricore/helper.h b/target/tricore/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/target/tricore/helper.h
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/target/tricore/helper.h
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
- C_O1_I2(r, r, ri)
+ DEF_HELPER_1(psw_read, i32, env)
- C_O1_I2(r, rZ, rZ)
+ /* Exceptions */
- C_O1_I2(w, w, w)
+ DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
-+C_O1_I2(w, w, wO)
+-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
-+C_O1_I2(w, w, wV)
+diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
 +C_O1_I2(w, w, wZ)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-str.h
+--- a/target/tricore/op_helper.c
-+++ b/tcg/arm/tcg-target-con-str.h
++++ b/target/tricore/op_helper.c
-@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
+@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
- CONST('I', TCG_CT_CONST_ARM)
+     raise_exception_sync_internal(env, class, tin, pc, 0);
- CONST('K', TCG_CT_CONST_INV)
+ }
- CONST('N', TCG_CT_CONST_NEG)
-+CONST('O', TCG_CT_CONST_ORRI)
+-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
-+CONST('V', TCG_CT_CONST_ANDI)
+-{
- CONST('Z', TCG_CT_CONST_ZERO)
+-    CPUState *cs = env_cpu(env);
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+-    cs->exception_index = excp;
 -    cpu_loop_exit(cs);
 -}
 -
  /* Addressing mode helper */
  static uint16_t reverse16(uint16_t val)
 diff --git a/target/tricore/translate.c b/target/tricore/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/target/tricore/translate.c
-+++ b/tcg/arm/tcg-target.h
++++ b/target/tricore/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
- #else
+     tcg_gen_movi_tl(cpu_PC, pc);
  extern bool use_idiv_instructions;
  #endif
 -#define use_neon_instructions  0
 +#ifdef __ARM_NEON__
 +#define use_neon_instructions  1
 +#else
 +extern bool use_neon_instructions;
 +#endif
  /* used for function call generation */
  #define TCG_TARGET_STACK_ALIGN        8
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
  #ifndef use_idiv_instructions
  bool use_idiv_instructions;
  #endif
 +#ifndef use_neon_instructions
 +bool use_neon_instructions;
 +#endif
  /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
  #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ typedef enum {
      /* Otherwise the assembler uses mov r0,r0 */
      INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 +    INSN_VADD      = 0xf2000800,
 +    INSN_VAND      = 0xf2000110,
 +    INSN_VEOR      = 0xf3000110,
      INSN_VORR      = 0xf2200110,
 +    INSN_VSUB      = 0xf3000800,
 +
 +    INSN_VMVN      = 0xf3b00580,
 +
 +    INSN_VCEQ0     = 0xf3b10100,
 +    INSN_VCGT0     = 0xf3b10000,
 +    INSN_VCGE0     = 0xf3b10080,
 +    INSN_VCLE0     = 0xf3b10180,
 +    INSN_VCLT0     = 0xf3b10200,
 +
 +    INSN_VCEQ      = 0xf3000810,
 +    INSN_VCGE      = 0xf2000310,
 +    INSN_VCGT      = 0xf2000300,
 +    INSN_VCGE_U    = 0xf3000310,
 +    INSN_VCGT_U    = 0xf3000300,
 +
 +    INSN_VTST      = 0xf2000810,
      INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
      INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  #define TCG_CT_CONST_INV  0x200
  #define TCG_CT_CONST_NEG  0x400
  #define TCG_CT_CONST_ZERO 0x800
 +#define TCG_CT_CONST_ORRI 0x1000
 +#define TCG_CT_CONST_ANDI 0x2000
  #define ALL_GENERAL_REGS  0xffffu
  #define ALL_VECTOR_REGS   0xffff0000u
@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
      return i;
  }
-+/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
+-static void generate_qemu_excp(DisasContext *ctx, int excp)
-+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+-{
-+{
+-    TCGv_i32 tmp = tcg_const_i32(excp);
-+    if (v32 == deposit32(v32, 16, 16, v32)) {
+-    gen_helper_qemu_excp(cpu_env, tmp);
-+        return is_shimm16(v32, cmode, imm8);
+-    ctx->base.is_jmp = DISAS_NORETURN;
-+    } else {
+-    tcg_temp_free(tmp);
-+        return is_shimm32(v32, cmode, imm8);
+-}
-+    }
+-
-+}
+ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 +
  /* Test if a constant matches the constraint.
   * TODO: define constraints for:
   *
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
          return 1;
      } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
          return 1;
 -    } else {
 -        return 0;
      }
 +
 +    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
 +    case 0:
 +        break;
 +    case TCG_CT_CONST_ANDI:
 +        val = ~val;
 +        /* fallthru */
 +    case TCG_CT_CONST_ORRI:
 +        if (val == deposit64(val, 32, 32, val)) {
 +            int cmode, imm8;
 +            return is_shimm1632(val, &cmode, &imm8);
 +        }
 +        break;
 +    default:
 +        /* Both bits should not be set for the same insn.  */
 +        g_assert_not_reached();
 +    }
 +
 +    return 0;
  }
  static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
      return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
  }
 +static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
 +                          TCGReg d, TCGReg m)
 +{
 +    tcg_out32(s, insn | (vece << 18) | (q << 6) |
 +              encode_vd(d) | encode_vm(m));
 +}
 +
  static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                            TCGReg d, TCGReg n, TCGReg m)
  {
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     if (translator_use_goto_tb(&ctx->base, dest)) {
-     case INDEX_op_add_vec:
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
-     case INDEX_op_sub_vec:
+         tcg_gen_exit_tb(ctx->base.tb, n);
-     case INDEX_op_xor_vec:
+     } else {
--    case INDEX_op_or_vec:
+         gen_save_pc(dest);
--    case INDEX_op_and_vec:
+-        if (ctx->base.singlestep_enabled) {
--    case INDEX_op_cmp_vec:
+-            generate_qemu_excp(ctx, EXCP_DEBUG);
-         return C_O1_I2(w, w, w);
+-        } else {
-+    case INDEX_op_or_vec:
+-            tcg_gen_lookup_and_goto_ptr();
-+        return C_O1_I2(w, w, wO);
+-        }
-+    case INDEX_op_and_vec:
++        tcg_gen_lookup_and_goto_ptr();
 +        return C_O1_I2(w, w, wV);
 +    case INDEX_op_cmp_vec:
 +        return C_O1_I2(w, w, wZ);
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
      }
  }
-+static const ARMInsn vec_cmp_insn[16] = {
-+    [TCG_COND_EQ] = INSN_VCEQ,
-+    [TCG_COND_GT] = INSN_VCGT,
-+    [TCG_COND_GE] = INSN_VCGE,
-+    [TCG_COND_GTU] = INSN_VCGT_U,
-+    [TCG_COND_GEU] = INSN_VCGE_U,
-+};
-+
-+static const ARMInsn vec_cmp0_insn[16] = {
-+    [TCG_COND_EQ] = INSN_VCEQ0,
-+    [TCG_COND_GT] = INSN_VCGT0,
-+    [TCG_COND_GE] = INSN_VCGE0,
-+    [TCG_COND_LT] = INSN_VCLT0,
-+    [TCG_COND_LE] = INSN_VCLE0,
-+};
-+
- static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-                            unsigned vecl, unsigned vece,
-                            const TCGArg *args, const int *const_args)
- {
--    g_assert_not_reached();
-+    TCGType type = vecl + TCG_TYPE_V64;
-+    unsigned q = vecl;
-+    TCGArg a0, a1, a2;
-+    int cmode, imm8;
-+
-+    a0 = args[0];
-+    a1 = args[1];
-+    a2 = args[2];
-+
-+    switch (opc) {
-+    case INDEX_op_ld_vec:
-+        tcg_out_ld(s, type, a0, a1, a2);
-+        return;
-+    case INDEX_op_st_vec:
-+        tcg_out_st(s, type, a0, a1, a2);
-+        return;
-+    case INDEX_op_dupm_vec:
-+        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
-+        return;
-+    case INDEX_op_dup2_vec:
-+        tcg_out_dup2_vec(s, a0, a1, a2);
-+        return;
-+    case INDEX_op_add_vec:
-+        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
-+        return;
-+    case INDEX_op_sub_vec:
-+        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
-+        return;
-+    case INDEX_op_xor_vec:
-+        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
-+        return;
-+
-+    case INDEX_op_and_vec:
-+        if (const_args[2]) {
-+            is_shimm1632(~a2, &cmode, &imm8);
-+            if (a0 == a1) {
-+                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
-+                return;
-+            }
-+            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
-+            a2 = a0;
-+        }
-+        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
-+        return;
-+
-+    case INDEX_op_or_vec:
-+        if (const_args[2]) {
-+            is_shimm1632(a2, &cmode, &imm8);
-+            if (a0 == a1) {
-+                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
-+                return;
-+            }
-+            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
-+            a2 = a0;
-+        }
-+        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
-+        return;
-+
-+    case INDEX_op_cmp_vec:
-+        {
-+            TCGCond cond = args[3];
-+
-+            if (cond == TCG_COND_NE) {
-+                if (const_args[2]) {
-+                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
-+                } else {
-+                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
-+                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
-+                }
-+            } else {
-+                ARMInsn insn;
-+
-+                if (const_args[2]) {
-+                    insn = vec_cmp0_insn[cond];
-+                    if (insn) {
-+                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
-+                        return;
-+                    }
-+                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
-+                    a2 = TCG_VEC_TMP;
-+                }
-+                insn = vec_cmp_insn[cond];
-+                if (insn == 0) {
-+                    TCGArg t;
-+                    t = a1, a1 = a2, a2 = t;
-+                    cond = tcg_swap_cond(cond);
-+                    insn = vec_cmp_insn[cond];
-+                    tcg_debug_assert(insn != 0);
-+                }
-+                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
-+            }
-+        }
-+        return;
-+
-+    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
-+    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
-+    default:
-+        g_assert_not_reached();
-+    }
- }
- int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
- {
--    return 0;
-+    switch (opc) {
-+    case INDEX_op_add_vec:
-+    case INDEX_op_sub_vec:
-+    case INDEX_op_and_vec:
-+    case INDEX_op_or_vec:
-+    case INDEX_op_xor_vec:
-+        return 1;
-+    case INDEX_op_cmp_vec:
-+        return vece < MO_64;
-+    default:
-+        return 0;
-+    }
- }
- void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
 --
 .25.1

-[PULL 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
+[PULL 23/24] target/xtensa: Drop check for singlestep_enabled
-NEON has 3 instructions implementing this 4 argument operation,
+GDB single-stepping is now handled generically.
 with each insn overlapping a different logical input onto the
 destination register.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target-con-set.h |  1 +
+ target/xtensa/translate.c | 25 ++++++++-----------------
- tcg/arm/tcg-target.h         |  2 +-
+file changed, 8 insertions(+), 17 deletions(-)
  tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
 files changed, 22 insertions(+), 3 deletions(-)
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target-con-set.h
+--- a/target/xtensa/translate.c
-+++ b/tcg/arm/tcg-target-con-set.h
++++ b/target/xtensa/translate.c
-@@ -XXX,XX +XXX,XX @@ C_O1_I2(w, w, w)
+@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
- C_O1_I2(w, w, wO)
+     if (dc->icount) {
- C_O1_I2(w, w, wV)
+         tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
- C_O1_I2(w, w, wZ)
+     }
-+C_O1_I3(w, w, w, w)
+-    if (dc->base.singlestep_enabled) {
- C_O1_I4(r, r, r, rI, rI)
+-        gen_exception(dc, EXCP_DEBUG);
- C_O1_I4(r, r, rIN, rIK, 0)
++    if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
- C_O2_I1(r, r, l)
++        slot = gen_postprocess(dc, slot);
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
++    }
-index XXXXXXX..XXXXXXX 100644
++    if (slot >= 0) {
---- a/tcg/arm/tcg-target.h
++        tcg_gen_goto_tb(slot);
-+++ b/tcg/arm/tcg-target.h
++        tcg_gen_exit_tb(dc->base.tb, slot);
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+     } else {
- #define TCG_TARGET_HAS_mul_vec          1
+-        if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
- #define TCG_TARGET_HAS_sat_vec          1
+-            slot = gen_postprocess(dc, slot);
- #define TCG_TARGET_HAS_minmax_vec       1
+-        }
--#define TCG_TARGET_HAS_bitsel_vec       0
+-        if (slot >= 0) {
-+#define TCG_TARGET_HAS_bitsel_vec       1
+-            tcg_gen_goto_tb(slot);
- #define TCG_TARGET_HAS_cmpsel_vec       0
+-            tcg_gen_exit_tb(dc->base.tb, slot);
+-        } else {
- #define TCG_TARGET_DEFAULT_MO (0)
+-            tcg_gen_exit_tb(NULL, 0);
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+-        }
-index XXXXXXX..XXXXXXX 100644
++        tcg_gen_exit_tb(NULL, 0);
---- a/tcg/arm/tcg-target.c.inc
+     }
-+++ b/tcg/arm/tcg-target.c.inc
+     dc->base.is_jmp = DISAS_NORETURN;
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+ }
-     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
-     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+     case DISAS_NORETURN:
+         break;
-+    INSN_VBSL      = 0xf3100110,
+     case DISAS_TOO_MANY:
-+    INSN_VBIT      = 0xf3200110,
+-        if (dc->base.singlestep_enabled) {
-+    INSN_VBIF      = 0xf3300110,
+-            tcg_gen_movi_i32(cpu_pc, dc->pc);
-+
+-            gen_exception(dc, EXCP_DEBUG);
-     INSN_VTST      = 0xf2000810,
+-        } else {
+-            gen_jumpi(dc, dc->pc, 0);
-     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+-        }
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
++        gen_jumpi(dc, dc->pc, 0);
-         return C_O1_I2(w, w, wV);
+         break;
      case INDEX_op_cmp_vec:
          return C_O1_I2(w, w, wZ);
 -
 +    case INDEX_op_bitsel_vec:
 +        return C_O1_I3(w, w, w, w);
      default:
          g_assert_not_reached();
-     }
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
- {
-     TCGType type = vecl + TCG_TYPE_V64;
-     unsigned q = vecl;
--    TCGArg a0, a1, a2;
-+    TCGArg a0, a1, a2, a3;
-     int cmode, imm8;
-     a0 = args[0];
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-         }
-         return;
-+    case INDEX_op_bitsel_vec:
-+        a3 = args[3];
-+        if (a0 == a3) {
-+            tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
-+        } else if (a0 == a2) {
-+            tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
-+        } else {
-+            tcg_out_mov(s, type, a0, a1);
-+            tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
-+        }
-+        return;
-+
-     case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
-     case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
-     default:
-@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     case INDEX_op_sssub_vec:
-     case INDEX_op_usadd_vec:
-     case INDEX_op_ussub_vec:
-+    case INDEX_op_bitsel_vec:
-         return 1;
-     case INDEX_op_abs_vec:
-     case INDEX_op_cmp_vec:
 --
 .25.1

-[PULL 04/15] tcg/arm: Implement tcg_out_mov for vector types
+[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
 Despite a comment saying why cpu_common_props cannot be placed in
 a file that is compiled once, it was moved anyway.  Revert that.
 Since then, Property is not defined in hw/core/cpu.h, so it is now
 easier to declare a function to install the properties rather than
 the Property array itself.
 Cc: Eduardo Habkost <ehabkost@redhat.com>
 Suggested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
+ include/hw/core/cpu.h |  1 +
-file changed, 46 insertions(+), 6 deletions(-)
+ cpu.c                 | 21 +++++++++++++++++++++
  hw/core/cpu-common.c  | 17 +----------------
 files changed, 23 insertions(+), 16 deletions(-)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/include/hw/core/cpu.h
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/include/hw/core/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
-     /* Otherwise the assembler uses mov r0,r0 */
+     GCC_FMT_ATTR(2, 3);
-     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+ /* $(top_srcdir)/cpu.c */
-+    INSN_VORR      = 0xf2200110,
++void cpu_class_init_props(DeviceClass *dc);
  void cpu_exec_initfn(CPUState *cpu);
  void cpu_exec_realizefn(CPUState *cpu, Error **errp);
  void cpu_exec_unrealizefn(CPUState *cpu);
 diff --git a/cpu.c b/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/cpu.c
 +++ b/cpu.c
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
      cpu_list_remove(cpu);
  }
 +static Property cpu_common_props[] = {
 +#ifndef CONFIG_USER_ONLY
 +    /*
 +     * Create a memory property for softmmu CPU object,
 +     * so users can wire up its memory. (This can't go in hw/core/cpu.c
 +     * because that file is compiled only once for both user-mode
 +     * and system builds.) The default if no link is set up is to use
 +     * the system address space.
 +     */
 +    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +#endif
 +    DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
++void cpu_class_init_props(DeviceClass *dc)
      INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
  } ARMInsn;
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
      return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
  }
 +static uint32_t encode_vn(TCGReg rn)
 +{
-+    tcg_debug_assert(rn >= TCG_REG_Q0);
++    device_class_set_props(dc, cpu_common_props);
 +    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
 +}
 +
-+static uint32_t encode_vm(TCGReg rm)
+ void cpu_exec_initfn(CPUState *cpu)
 +{
 +    tcg_debug_assert(rm >= TCG_REG_Q0);
 +    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
 +}
 +
 +static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
 +                          TCGReg d, TCGReg n, TCGReg m)
 +{
 +    tcg_out32(s, insn | (vece << 20) | (q << 6) |
 +              encode_vd(d) | encode_vn(n) | encode_vm(m));
 +}
 +
  static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                            TCGReg rd, TCGReg rn, int offset)
  {
-@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+     cpu->as = NULL;
-     return false;
+diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/cpu-common.c
 +++ b/hw/core/cpu-common.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
      return cpu->cpu_index;
  }
--static inline bool tcg_out_mov(TCGContext *s, TCGType type,
+-static Property cpu_common_props[] = {
--                               TCGReg ret, TCGReg arg)
+-#ifndef CONFIG_USER_ONLY
-+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+-    /* Create a memory property for softmmu CPU object,
 -     * so users can wire up its memory. (This can't go in hw/core/cpu.c
 -     * because that file is compiled only once for both user-mode
 -     * and system builds.) The default if no link is set up is to use
 -     * the system address space.
 -     */
 -    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -#endif
 -    DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
  static void cpu_class_init(ObjectClass *klass, void *data)
  {
--    tcg_out_mov_reg(s, COND_AL, ret, arg);
+     DeviceClass *dc = DEVICE_CLASS(klass);
--    return true;
+@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
-+    if (ret == arg) {
+     dc->realize = cpu_common_realizefn;
-+        return true;
+     dc->unrealize = cpu_common_unrealizefn;
-+    }
+     dc->reset = cpu_common_reset;
-+    switch (type) {
+-    device_class_set_props(dc, cpu_common_props);
-+    case TCG_TYPE_I32:
++    cpu_class_init_props(dc);
-+        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+     /*
-+            tcg_out_mov_reg(s, COND_AL, ret, arg);
+      * Reason: CPUs still need special care by board code: wiring up
-+            return true;
+      * IRQs, adding reset handlers, halting non-first CPUs, ...
 +        }
 +        return false;
 +
 +    case TCG_TYPE_V64:
 +    case TCG_TYPE_V128:
 +        /* "VMOV D,N" is an alias for "VORR D,N,N". */
 +        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
 +        return true;
 +
 +    default:
 +        g_assert_not_reached();
 +    }
  }
 -static inline void tcg_out_movi(TCGContext *s, TCGType type,
 -                                TCGReg ret, tcg_target_long arg)
 +static void tcg_out_movi(TCGContext *s, TCGType type,
 +                         TCGReg ret, tcg_target_long arg)
  {
 +    tcg_debug_assert(type == TCG_TYPE_I32);
 +    tcg_debug_assert(ret < TCG_REG_Q0);
      tcg_out_movi32(s, COND_AL, ret, arg);
  }
 --
 .25.1

The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604

for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:

tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)

----------------------------------------------------------------
Host vector support for arm neon.

----------------------------------------------------------------
Richard Henderson (15):
      tcg: Change parameters for tcg_target_const_match
      tcg/arm: Add host vector framework
      tcg/arm: Implement tcg_out_ld/st for vector types
      tcg/arm: Implement tcg_out_mov for vector types
      tcg/arm: Implement tcg_out_dup*_vec
      tcg/arm: Implement minimal vector operations
      tcg/arm: Implement andc, orc, abs, neg, not vector operations
      tcg/arm: Implement TCG_TARGET_HAS_shi_vec
      tcg/arm: Implement TCG_TARGET_HAS_mul_vec
      tcg/arm: Implement TCG_TARGET_HAS_sat_vec
      tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
      tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
      tcg/arm: Implement TCG_TARGET_HAS_shv_vec
      tcg/arm: Implement TCG_TARGET_HAS_roti_vec
      tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Change the return value to bool, because that's what is should
have been from the start.  Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.

Change the value argument to int64_t.  We will need the extra
width for 32-bit hosts wanting to match vector constants.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c                    | 5 ++---
 tcg/aarch64/tcg-target.c.inc | 5 +----
 tcg/arm/tcg-target.c.inc     | 5 +----
 tcg/i386/tcg-target.c.inc    | 4 +---
 tcg/mips/tcg-target.c.inc    | 5 +----
 tcg/ppc/tcg-target.c.inc     | 4 +---
 tcg/riscv/tcg-target.c.inc   | 4 +---
 tcg/s390/tcg-target.c.inc    | 5 +----
 tcg/sparc/tcg-target.c.inc   | 5 +----
 tcg/tci/tcg-target.c.inc     | 6 ++----
 10 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
                         TCGReg base, intptr_t ofs);
 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct);
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
 #ifdef TCG_TARGET_NEED_LDST_LABELS
 static int tcg_out_ldst_finalize(TCGContext *s);
 #endif
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         ts = arg_temp(arg);
 
         if (ts->val_type == TEMP_VAL_CONST
-            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
             /* constant is OK for instruction */
             const_args[i] = 1;
             new_args[i] = ts->val;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
     }
 }
 
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
  * mov operand2:     values represented with x << (2 * y), x < 0x100
  * add, sub, eor...: ditto
  */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    /* No need to return 0 or 1, 0 or != 0 is good enough. */
-    return arg_ct->ct & TCG_CT_CONST;
+    return ct & TCG_CT_CONST;
 }
 
 static void tcg_target_init(TCGContext *s)
-- 
2.25.1

Add registers and function stubs.  The functionality
is disabled via use_neon_instructions defined to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   4 ++
 tcg/arm/tcg-target-con-str.h |   1 +
 tcg/arm/tcg-target.h         |  48 ++++++++++++--
 tcg/arm/tcg-target.opc.h     |  12 ++++
 tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
 5 files changed, 158 insertions(+), 24 deletions(-)
 create mode 100644 tcg/arm/tcg-target.opc.h

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
 C_O0_I2(r, r)
 C_O0_I2(r, rIN)
 C_O0_I2(s, s)
+C_O0_I2(w, r)
 C_O0_I3(s, s, s)
 C_O0_I4(r, r, rI, rI)
 C_O0_I4(s, s, s, s)
 C_O1_I1(r, l)
 C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, wr)
 C_O1_I2(r, 0, rZ)
 C_O1_I2(r, l, l)
 C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
 C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, w, w)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
 REGS('r', ALL_GENERAL_REGS)
 REGS('l', ALL_QLOAD_REGS)
 REGS('s', ALL_QSTORE_REGS)
+REGS('w', ALL_VECTOR_REGS)
 
 /*
  * Define constraint letters for constants:
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     TCG_REG_R13,
     TCG_REG_R14,
     TCG_REG_PC,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    TCG_REG_Q4,
+    TCG_REG_Q5,
+    TCG_REG_Q6,
+    TCG_REG_Q7,
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
+
+    TCG_AREG0 = TCG_REG_R6,
+    TCG_REG_CALL_STACK = TCG_REG_R13,
 } TCGReg;
 
-#define TCG_TARGET_NB_REGS 16
+#define TCG_TARGET_NB_REGS 32
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define use_idiv_instructions  1
 #else
 extern bool use_idiv_instructions;
 #endif
-
+#define use_neon_instructions  0
 
 /* used for function call generation */
-#define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
 #define TCG_TARGET_CALL_ALIGN_ARGS	1
 #define TCG_TARGET_CALL_STACK_OFFSET	0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
 #define TCG_TARGET_HAS_direct_jump      0
 #define TCG_TARGET_HAS_qemu_st8_i32     0
 
-enum {
-    TCG_AREG0 = TCG_REG_R6,
-};
+#define TCG_TARGET_HAS_v64              use_neon_instructions
+#define TCG_TARGET_HAS_v128             use_neon_instructions
+#define TCG_TARGET_HAS_v256             0
+
+#define TCG_TARGET_HAS_andc_vec         0
+#define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_not_vec          0
+#define TCG_TARGET_HAS_neg_vec          0
+#define TCG_TARGET_HAS_abs_vec          0
+#define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
+#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shs_vec          0
+#define TCG_TARGET_HAS_shv_vec          0
+#define TCG_TARGET_HAS_mul_vec          0
+#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_bitsel_vec       0
+#define TCG_TARGET_HAS_cmpsel_vec       0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_HAS_MEMORY_BSWAP     1
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion.  These will be
+ * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-    "%r0",
-    "%r1",
-    "%r2",
-    "%r3",
-    "%r4",
-    "%r5",
-    "%r6",
-    "%r7",
-    "%r8",
-    "%r9",
-    "%r10",
-    "%r11",
-    "%r12",
-    "%r13",
-    "%r14",
-    "%pc",
+    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
+    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
+    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
+    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R3,
     TCG_REG_R12,
     TCG_REG_R14,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    /* Q4 - Q7 are call-saved, and skipped. */
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
 };
 
 static const int tcg_target_call_iarg_regs[4] = {
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
 };
 
 #define TCG_REG_TMP  TCG_REG_R12
+#define TCG_VEC_TMP  TCG_REG_Q15
 
 enum arm_cond_code_e {
     COND_EQ = 0x0,
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_ZERO 0x800
 
 #define ALL_GENERAL_REGS  0xffffu
+#define ALL_VECTOR_REGS   0xffff0000u
 
 /*
  * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_qemu_st_i64:
         return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 
+    case INDEX_op_st_vec:
+        return C_O0_I2(w, r);
+    case INDEX_op_ld_vec:
+    case INDEX_op_dupm_vec:
+        return C_O1_I1(w, r);
+    case INDEX_op_dup_vec:
+        return C_O1_I1(w, wr);
+    case INDEX_op_dup2_vec:
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_xor_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, w);
+
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
 {
     /* Only probe for the platform and capabilities if we havn't already
        determined maximum values at compile time.  */
-#ifndef use_idiv_instructions
+#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
     {
         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+#ifndef use_idiv_instructions
         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+#endif
+#ifndef use_neon_instructions
+        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
+#endif
     }
 #endif
+
     if (__ARM_ARCH < 7) {
         const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
         if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
         }
     }
 
-    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
 
     tcg_target_call_clobber_regs = 0;
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
 
+    if (use_neon_instructions) {
+        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
+        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
+    }
+
     s->reserved_regs = 0;
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
+    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+                            TCGReg rd, TCGReg rs)
+{
+    g_assert_not_reached();
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, TCGReg base, intptr_t offset)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, int64_t v64)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+                           unsigned vecl, unsigned vece,
+                           const TCGArg *args, const int *const_args)
+{
+    g_assert_not_reached();
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+    return 0;
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+                       TCGArg a0, ...)
+{
+    g_assert_not_reached();
+}
+
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 {
     int i;
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 64 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_NOP_v6k   = 0xe320f000,
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+
+    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
     }
 }
 
+/*
+ * Note that TCGReg references Q-registers.
+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ */
+static uint32_t encode_vd(TCGReg rd)
+{
+    tcg_debug_assert(rd >= TCG_REG_Q0);
+    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+}
+
+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+                          TCGReg rd, TCGReg rn, int offset)
+{
+    if (offset != 0) {
+        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
+            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+                            TCG_REG_TMP, rn, offset, true);
+        } else {
+            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
+        }
+        rn = TCG_REG_TMP;
+    }
+    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
+}
+
 #ifdef CONFIG_SOFTMMU
 #include "../tcg-ldst.c.inc"
 
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VORR      = 0xf2200110,
+
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
     return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
 }
 
+static uint32_t encode_vn(TCGReg rn)
+{
+    tcg_debug_assert(rn >= TCG_REG_Q0);
+    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+    tcg_debug_assert(rm >= TCG_REG_Q0);
+    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg n, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 20) | (q << 6) |
+              encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
     return false;
 }
 
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
-                               TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 {
-    tcg_out_mov_reg(s, COND_AL, ret, arg);
-    return true;
+    if (ret == arg) {
+        return true;
+    }
+    switch (type) {
+    case TCG_TYPE_I32:
+        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+            tcg_out_mov_reg(s, COND_AL, ret, arg);
+            return true;
+        }
+        return false;
+
+    case TCG_TYPE_V64:
+    case TCG_TYPE_V128:
+        /* "VMOV D,N" is an alias for "VORR D,N,N". */
+        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
+        return true;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
-                                TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+                         TCGReg ret, tcg_target_long arg)
 {
+    tcg_debug_assert(type == TCG_TYPE_I32);
+    tcg_debug_assert(ret < TCG_REG_Q0);
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
-- 
2.25.1

Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 275 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
 
     INSN_VORR      = 0xf2200110,
 
+    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
+    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
     [TCG_COND_GTU] = COND_HI,
 };
 
+static int encode_imm(uint32_t imm);
+
+/* TCG private relocation type: add with pc+imm8 */
+#define R_ARM_PC8  11
+
+/* TCG private relocation type: vldr with imm8 << 2 */
+#define R_ARM_PC11 12
+
 static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 {
     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
     return false;
 }
 
+static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
+
+    if (offset >= -0xff && offset <= 0xff) {
+        tcg_insn_unit insn = *src_rw;
+        bool u = (offset >= 0);
+        if (!u) {
+            offset = -offset;
+        }
+        insn = deposit32(insn, 23, 1, u);
+        insn = deposit32(insn, 0, 8, offset);
+        *src_rw = insn;
+        return true;
+    }
+    return false;
+}
+
+static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
+    int rot = encode_imm(offset);
+
+    if (rot >= 0) {
+        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
+        return true;
+    }
+    return false;
+}
+
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                         intptr_t value, intptr_t addend)
 {
     tcg_debug_assert(addend == 0);
-
-    if (type == R_ARM_PC24) {
+    switch (type) {
+    case R_ARM_PC24:
         return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
-    } else if (type == R_ARM_PC13) {
+    case R_ARM_PC13:
         return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
-    } else {
+    case R_ARM_PC11:
+        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
+    case R_ARM_PC8:
+        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
+    default:
         g_assert_not_reached();
     }
 }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
 
 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
    right-rotated by an even amount between 0 and 30. */
-static inline int encode_imm(uint32_t imm)
+static int encode_imm(uint32_t imm)
 {
     int shift;
 
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
     return encode_imm(imm) >= 0;
 }
 
+/* Return true if v16 is a valid 16-bit shifted immediate.  */
+static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
+{
+    if (v16 == (v16 & 0xff)) {
+        *cmode = 0x8;
+        *imm8 = v16 & 0xff;
+        return true;
+    } else if (v16 == (v16 & 0xff00)) {
+        *cmode = 0xa;
+        *imm8 = v16 >> 8;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifted immediate.  */
+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == (v32 & 0xff)) {
+        *cmode = 0x0;
+        *imm8 = v32 & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff00)) {
+        *cmode = 0x2;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff0000)) {
+        *cmode = 0x4;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff000000)) {
+        *cmode = 0x6;
+        *imm8 = v32 >> 24;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if ((v32 & 0xffff00ff) == 0xff) {
+        *cmode = 0xc;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if ((v32 & 0xff00ffff) == 0xffff) {
+        *cmode = 0xd;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    }
+    return false;
+}
+
+/*
+ * Return non-zero if v32 can be formed by MOVI+ORR.
+ * Place the parameters for MOVI in (cmode, imm8).
+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
+ */
+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
+{
+    int i;
+
+    for (i = 6; i > 0; i -= 2) {
+        /* Mask out one byte we can add with ORR.  */
+        uint32_t tmp = v32 & ~(0xffu << (i * 4));
+        if (is_shimm32(tmp, cmode, imm8) ||
+            is_soimm32(tmp, cmode, imm8)) {
+            break;
+        }
+    }
+    return i;
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
               encode_vd(d) | encode_vn(n) | encode_vm(m));
 }
 
+static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+                          int q, int op, int cmode, uint8_t imm8)
+{
+    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
+              | (cmode << 8) | extract32(imm8, 0, 4)
+              | (extract32(imm8, 4, 3) << 16)
+              | (extract32(imm8, 7, 1) << 24));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+/* Type is always V128, with I64 elements.  */
+static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
+{
+    /* Move high element into place first. */
+    /* VMOV Dd+1, Ds */
+    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
+    /* Move low element into place; tcg_out_mov will check for nop. */
+    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
+}
+
 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                             TCGReg rd, TCGReg rs)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+
+    if (vece == MO_64) {
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rs, rs);
+        } else {
+            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
+        }
+    } else if (rs < TCG_REG_Q0) {
+        int b = (vece == MO_8);
+        int e = (vece == MO_16);
+        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
+                  encode_vn(rd) | (rs << 12));
+    } else {
+        int imm4 = 1 << vece;
+        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
+                  encode_vd(rd) | encode_vm(rs));
+    }
+    return true;
 }
 
 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, TCGReg base, intptr_t offset)
 {
-    g_assert_not_reached();
+    if (vece == MO_64) {
+        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        int q = type - TCG_TYPE_V64;
+        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
+                      rd, base, offset);
+    }
+    return true;
 }
 
 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, int64_t v64)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+    int cmode, imm8, i;
+
+    /* Test all bytes equal first.  */
+    if (vece == MO_8) {
+        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
+        return;
+    }
+
+    /*
+     * Test all bytes 0x00 or 0xff second.  This can match cases that
+     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
+     */
+    for (i = imm8 = 0; i < 8; i++) {
+        uint8_t byte = v64 >> (i * 8);
+        if (byte == 0xff) {
+            imm8 |= 1 << i;
+        } else if (byte != 0) {
+            goto fail_bytes;
+        }
+    }
+    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
+    return;
+ fail_bytes:
+
+    /*
+     * Tests for various replications.  For each element width, if we
+     * cannot find an expansion there's no point checking a larger
+     * width because we already know by replication it cannot match.
+     */
+    if (vece == MO_16) {
+        uint16_t v16 = v64;
+
+        if (is_shimm16(v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm16(~v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Otherwise, all remaining constants can be loaded in two insns:
+         * rd = v16 & 0xff, rd |= v16 & 0xff00.
+         */
+        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
+        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
+        return;
+    }
+
+    if (vece == MO_32) {
+        uint32_t v32 = v64;
+
+        if (is_shimm32(v32, &cmode, &imm8) ||
+            is_soimm32(v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm32(~v32, &cmode, &imm8) ||
+            is_soimm32(~v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Restrict the set of constants to those we can load with
+         * two instructions.  Others we load from the pool.
+         */
+        i = is_shimm32_pair(v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
+            return;
+        }
+        i = is_shimm32_pair(~v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
+            return;
+        }
+    }
+
+    /*
+     * As a last resort, load from the constant pool.
+     */
+    if (!q || vece == MO_64) {
+        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
+        /* VLDR Dd, [pc + offset] */
+        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
+        if (q) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
+        /* add tmp, pc, offset */
+        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
+        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
+    }
 }
 
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-- 
2.25.1

Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   3 +
 tcg/arm/tcg-target-con-str.h |   2 +
 tcg/arm/tcg-target.h         |   6 +-
 tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
 4 files changed, 204 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
 C_O1_I2(w, w, w)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wV)
+C_O1_I2(w, w, wZ)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
 CONST('I', TCG_CT_CONST_ARM)
 CONST('K', TCG_CT_CONST_INV)
 CONST('N', TCG_CT_CONST_NEG)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('V', TCG_CT_CONST_ANDI)
 CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #else
 extern bool use_idiv_instructions;
 #endif
-#define use_neon_instructions  0
+#ifdef __ARM_NEON__
+#define use_neon_instructions  1
+#else
+extern bool use_neon_instructions;
+#endif
 
 /* used for function call generation */
 #define TCG_TARGET_STACK_ALIGN		8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
 #endif
+#ifndef use_neon_instructions
+bool use_neon_instructions;
+#endif
 
 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
 #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VADD      = 0xf2000800,
+    INSN_VAND      = 0xf2000110,
+    INSN_VEOR      = 0xf3000110,
     INSN_VORR      = 0xf2200110,
+    INSN_VSUB      = 0xf3000800,
+
+    INSN_VMVN      = 0xf3b00580,
+
+    INSN_VCEQ0     = 0xf3b10100,
+    INSN_VCGT0     = 0xf3b10000,
+    INSN_VCGE0     = 0xf3b10080,
+    INSN_VCLE0     = 0xf3b10180,
+    INSN_VCLT0     = 0xf3b10200,
+
+    INSN_VCEQ      = 0xf3000810,
+    INSN_VCGE      = 0xf2000310,
+    INSN_VCGT      = 0xf2000300,
+    INSN_VCGE_U    = 0xf3000310,
+    INSN_VCGT_U    = 0xf3000300,
+
+    INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
     INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_INV  0x200
 #define TCG_CT_CONST_NEG  0x400
 #define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_ORRI 0x1000
+#define TCG_CT_CONST_ANDI 0x2000
 
 #define ALL_GENERAL_REGS  0xffffu
 #define ALL_VECTOR_REGS   0xffff0000u
@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
     return i;
 }
 
+/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == deposit32(v32, 16, 16, v32)) {
+        return is_shimm16(v32, cmode, imm8);
+    } else {
+        return is_shimm32(v32, cmode, imm8);
+    }
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
         return 1;
-    } else {
-        return 0;
     }
+
+    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
+    case 0:
+        break;
+    case TCG_CT_CONST_ANDI:
+        val = ~val;
+        /* fallthru */
+    case TCG_CT_CONST_ORRI:
+        if (val == deposit64(val, 32, 32, val)) {
+            int cmode, imm8;
+            return is_shimm1632(val, &cmode, &imm8);
+        }
+        break;
+    default:
+        /* Both bits should not be set for the same insn.  */
+        g_assert_not_reached();
+    }
+
+    return 0;
 }
 
 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
     return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
 }
 
+static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 18) | (q << 6) |
+              encode_vd(d) | encode_vm(m));
+}
+
 static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                           TCGReg d, TCGReg n, TCGReg m)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_xor_vec:
-    case INDEX_op_or_vec:
-    case INDEX_op_and_vec:
-    case INDEX_op_cmp_vec:
         return C_O1_I2(w, w, w);
+    case INDEX_op_or_vec:
+        return C_O1_I2(w, w, wO);
+    case INDEX_op_and_vec:
+        return C_O1_I2(w, w, wV);
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, wZ);
 
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
     }
 }
 
+static const ARMInsn vec_cmp_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ,
+    [TCG_COND_GT] = INSN_VCGT,
+    [TCG_COND_GE] = INSN_VCGE,
+    [TCG_COND_GTU] = INSN_VCGT_U,
+    [TCG_COND_GEU] = INSN_VCGE_U,
+};
+
+static const ARMInsn vec_cmp0_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ0,
+    [TCG_COND_GT] = INSN_VCGT0,
+    [TCG_COND_GE] = INSN_VCGE0,
+    [TCG_COND_LT] = INSN_VCLT0,
+    [TCG_COND_LE] = INSN_VCLE0,
+};
+
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                            unsigned vecl, unsigned vece,
                            const TCGArg *args, const int *const_args)
 {
-    g_assert_not_reached();
+    TCGType type = vecl + TCG_TYPE_V64;
+    unsigned q = vecl;
+    TCGArg a0, a1, a2;
+    int cmode, imm8;
+
+    a0 = args[0];
+    a1 = args[1];
+    a2 = args[2];
+
+    switch (opc) {
+    case INDEX_op_ld_vec:
+        tcg_out_ld(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_st_vec:
+        tcg_out_st(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_dupm_vec:
+        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+        return;
+    case INDEX_op_dup2_vec:
+        tcg_out_dup2_vec(s, a0, a1, a2);
+        return;
+    case INDEX_op_add_vec:
+        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sub_vec:
+        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_xor_vec:
+        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_and_vec:
+        if (const_args[2]) {
+            is_shimm1632(~a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_or_vec:
+        if (const_args[2]) {
+            is_shimm1632(a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_cmp_vec:
+        {
+            TCGCond cond = args[3];
+
+            if (cond == TCG_COND_NE) {
+                if (const_args[2]) {
+                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
+                } else {
+                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
+                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+                }
+            } else {
+                ARMInsn insn;
+
+                if (const_args[2]) {
+                    insn = vec_cmp0_insn[cond];
+                    if (insn) {
+                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
+                        return;
+                    }
+                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
+                    a2 = TCG_VEC_TMP;
+                }
+                insn = vec_cmp_insn[cond];
+                if (insn == 0) {
+                    TCGArg t;
+                    t = a1, a1 = a2, a2 = t;
+                    cond = tcg_swap_cond(cond);
+                    insn = vec_cmp_insn[cond];
+                    tcg_debug_assert(insn != 0);
+                }
+                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+            }
+        }
+        return;
+
+    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
+    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
+    default:
+        g_assert_not_reached();
+    }
 }
 
 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 {
-    return 0;
+    switch (opc) {
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_xor_vec:
+        return 1;
+    case INDEX_op_cmp_vec:
+        return vece < MO_64;
+    default:
+        return 0;
+    }
 }
 
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-- 
2.25.1

These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         | 10 +++++-----
 tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 5 deletions(-)

This consists of the three immediate shifts: shli, shri, sari.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
-#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VCGE_U    = 0xf3000310,
     INSN_VCGT_U    = 0xf3000300,
 
+    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
+    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+
     INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
               | (extract32(imm8, 7, 1) << 24));
 }
 
+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+                            TCGReg rd, TCGReg rm, int l_imm6)
+{
+    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
+              (extract32(l_imm6, 6, 1) << 7) |
+              (extract32(l_imm6, 0, 6) << 16));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_abs_vec:
     case INDEX_op_neg_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return C_O1_I1(w, w);
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_shli_vec:
+        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
+        return;
+    case INDEX_op_shri_vec:
+        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
+        return;
+    case INDEX_op_sari_vec:
+        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
+        return;
 
     case INDEX_op_andc_vec:
         if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_orc_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     | 2 +-
 tcg/arm/tcg-target.c.inc | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

This is saturating add and subtract, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
-#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       0
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VORR      = 0xf2200110,
     INSN_VSUB      = 0xf3000800,
     INSN_VMUL      = 0xf2000910,
+    INSN_VQADD     = 0xf2000010,
+    INSN_VQADD_U   = 0xf3000010,
+    INSN_VQSUB     = 0xf2000210,
+    INSN_VQSUB_U   = 0xf3000210,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_ssadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sssub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_usadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_ussub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

This is minimum and maximum, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
-#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
 
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VQADD_U   = 0xf3000010,
     INSN_VQSUB     = 0xf2000210,
     INSN_VQSUB_U   = 0xf3000210,
+    INSN_VMAX      = 0xf2000600,
+    INSN_VMAX_U    = 0xf3000600,
+    INSN_VMIN      = 0xf2000610,
+    INSN_VMIN_U    = 0xf3000610,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
     case INDEX_op_ssadd_vec:
     case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_mul_vec:
         tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_smax_vec:
+        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_smin_vec:
+        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sssub_vec:
         tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_umax_vec:
+        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_umin_vec:
+        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_usadd_vec:
         tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_cmp_vec:
     case INDEX_op_mul_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
         return vece < MO_64;
     default:
         return 0;
-- 
2.25.1

NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         |  2 +-
 tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
 3 files changed, 22 insertions(+), 3 deletions(-)

The three vector shift by vector operations are all implemented via
expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.opc.h |  3 ++
 tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
  * consider these to be UNSPEC with names.
  */
+
+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
+    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
 
     INSN_VBSL      = 0xf3100110,
     INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
+    case INDEX_op_arm_sshl_vec:
+    case INDEX_op_arm_ushl_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
     case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_arm_sshl_vec:
+        /*
+         * Note that Vm is the data and Vn is the shift count,
+         * therefore the arguments appear reversed.
+         */
+        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
+        return;
+    case INDEX_op_arm_ushl_vec:
+        /* See above. */
+        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
+        return;
     case INDEX_op_shli_vec:
         tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_umax_vec:
     case INDEX_op_umin_vec:
         return vece < MO_64;
+    case INDEX_op_shlv_vec:
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        return -1;
     default:
         return 0;
     }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
-    g_assert_not_reached();
+    va_list va;
+    TCGv_vec v0, v1, v2, t1;
+    TCGArg a2;
+
+    va_start(va, a0);
+    v0 = temp_tcgv_vec(arg_temp(a0));
+    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+    a2 = va_arg(va, TCGArg);
+    va_end(va);
+
+    switch (opc) {
+    case INDEX_op_shlv_vec:
+        /*
+         * Merely propagate shlv_vec to arm_ushl_vec.
+         * In this way we don't set TCG_TARGET_HAS_shv_vec
+         * because everything is done via expansion.
+         */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        break;
+
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        /* Right shifts are negative left shifts for NEON.  */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_neg_vec(vece, t1, v2);
+        if (opc == INDEX_op_shrv_vec) {
+            opc = INDEX_op_arm_ushl_vec;
+        } else {
+            opc = INDEX_op_arm_sshl_vec;
+        }
+        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        tcg_temp_free_vec(t1);
+        break;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-- 
2.25.1

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.opc.h     |  1 +
 tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
 3 files changed, 17 insertions(+)

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
     case INDEX_op_rotli_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
         return -1;
     default:
         return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
     va_list va;
-    TCGv_vec v0, v1, v2, t1;
+    TCGv_vec v0, v1, v2, t1, t2, c1;
     TCGArg a2;
 
     va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         tcg_temp_free_vec(t1);
         break;
 
+    case INDEX_op_rotlv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_sub_vec(vece, t1, v2, c1);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        tcg_gen_or_vec(vece, v0, v0, t1);
+        tcg_temp_free_vec(t1);
+        break;
+
+    case INDEX_op_rotrv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        t2 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_neg_vec(vece, t1, v2);
+        tcg_gen_sub_vec(vece, t2, c1, v2);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+        tcg_gen_or_vec(vece, v0, t1, t2);
+        tcg_temp_free_vec(t1);
+        tcg_temp_free_vec(t2);
+        break;
+
     default:
         g_assert_not_reached();
     }
-- 
2.25.1

The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016

for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:

Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)

----------------------------------------------------------------
Move gdb singlestep to generic code
Fix cpu_common_props

----------------------------------------------------------------
Richard Henderson (24):
      accel/tcg: Handle gdb singlestep in cpu_tb_exec
      target/alpha: Drop checks for singlestep_enabled
      target/avr: Drop checks for singlestep_enabled
      target/cris: Drop checks for singlestep_enabled
      target/hexagon: Drop checks for singlestep_enabled
      target/arm: Drop checks for singlestep_enabled
      target/hppa: Drop checks for singlestep_enabled
      target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
      target/i386: Drop check for singlestep_enabled
      target/m68k: Drop checks for singlestep_enabled
      target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
      target/microblaze: Drop checks for singlestep_enabled
      target/mips: Fix single stepping
      target/mips: Drop exit checks for singlestep_enabled
      target/openrisc: Drop checks for singlestep_enabled
      target/ppc: Drop exit checks for singlestep_enabled
      target/riscv: Remove dead code after exception
      target/riscv: Remove exit_tb and lookup_and_goto_ptr
      target/rx: Drop checks for singlestep_enabled
      target/s390x: Drop check for singlestep_enabled
      target/sh4: Drop check for singlestep_enabled
      target/tricore: Drop check for singlestep_enabled
      target/xtensa: Drop check for singlestep_enabled
      Revert "cpu: Move cpu_common_props to hw/core/cpu.c"

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/translate.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
         /* FALLTHRU */
     case DISAS_PC_UPDATED:
-        if (!ctx->base.singlestep_enabled) {
-            tcg_gen_lookup_and_goto_ptr();
-            break;
-        }
-        /* FALLTHRU */
+        tcg_gen_lookup_and_goto_ptr();
+        break;
     case DISAS_PC_UPDATED_NOCHAIN:
-        if (ctx->base.singlestep_enabled) {
-            gen_excp_1(EXCP_DEBUG, 0);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
         break;
     default:
         g_assert_not_reached();
-- 
2.25.1

GDB single-stepping is now handled generically.

Tested-by: Michael Rolnik <mrolnik@gmail.com>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/avr/translate.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         tcg_gen_exit_tb(tb, n);
     } else {
         tcg_gen_movi_i32(cpu_pc, dest);
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
         tcg_gen_movi_tl(cpu_pc, ctx->npc);
         /* fall through */
     case DISAS_LOOKUP:
-        if (!ctx->base.singlestep_enabled) {
-            tcg_gen_lookup_and_goto_ptr();
-            break;
-        }
-        /* fall through */
+        tcg_gen_lookup_and_goto_ptr();
+        break;
     case DISAS_EXIT:
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
         break;
     default:
         g_assert_not_reached();
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hexagon/translate.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
 {
     gen_exec_counters(ctx);
     tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
-    if (ctx->base.singlestep_enabled) {
-        gen_exception_raw(EXCP_DEBUG);
-    } else {
-        tcg_gen_exit_tb(NULL, 0);
-    }
+    tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
     case DISAS_TOO_MANY:
         gen_exec_counters(ctx);
         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
-        if (ctx->base.singlestep_enabled) {
-            gen_exception_raw(EXCP_DEBUG);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
         break;
     case DISAS_NORETURN:
         break;
-- 
2.25.1

GDB single-stepping is now handled generically.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 10 ++--------
 target/arm/translate.c     | 36 ++++++------------------------------
 2 files changed, 8 insertions(+), 38 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
         gen_a64_set_pc_im(dest);
         if (s->ss_active) {
             gen_step_complete_exception(s);
-        } else if (s->base.singlestep_enabled) {
-            gen_exception_internal(EXCP_DEBUG);
         } else {
             tcg_gen_lookup_and_goto_ptr();
             s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
 
-    if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
+    if (unlikely(dc->ss_active)) {
         /* Note that this means single stepping WFI doesn't halt the CPU.
          * For conditional branch insns this is harmless unreachable code as
          * gen_goto_tb() has already handled emitting the debug exception
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             /* fall through */
         case DISAS_EXIT:
         case DISAS_JUMP:
-            if (dc->base.singlestep_enabled) {
-                gen_exception_internal(EXCP_DEBUG);
-            } else {
-                gen_step_complete_exception(dc);
-            }
+            gen_step_complete_exception(dc);
             break;
         case DISAS_NORETURN:
             break;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
     tcg_temp_free_i32(tcg_excp);
 }
 
-static void gen_step_complete_exception(DisasContext *s)
+static void gen_singlestep_exception(DisasContext *s)
 {
     /* We just completed step of an insn. Move from Active-not-pending
      * to Active-pending, and then also take the swstep exception.
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_singlestep_exception(DisasContext *s)
-{
-    /* Generate the right kind of exception for singlestep, which is
-     * either the architectural singlestep or EXCP_DEBUG for QEMU's
-     * gdb singlestepping.
-     */
-    if (s->ss_active) {
-        gen_step_complete_exception(s);
-    } else {
-        gen_exception_internal(EXCP_DEBUG);
-    }
-}
-
-static inline bool is_singlestepping(DisasContext *s)
-{
-    /* Return true if we are singlestepping either because of
-     * architectural singlestep or QEMU gdbstub singlestep. This does
-     * not include the command line '-singlestep' mode which is rather
-     * misnamed as it only means "one instruction per TB" and doesn't
-     * affect the code we generate.
-     */
-    return s->base.singlestep_enabled || s->ss_active;
-}
-
 void clear_eci_state(DisasContext *s)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
     /* Is the new PC value in the magic range indicating exception return? */
     tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
     /* No: end the TB as we would for a DISAS_JMP */
-    if (is_singlestepping(s)) {
+    if (s->ss_active) {
         gen_singlestep_exception(s);
     } else {
         tcg_gen_exit_tb(NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
 /* Jump, specifying which TB number to use if we gen_goto_tb() */
 static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
 {
-    if (unlikely(is_singlestepping(s))) {
+    if (unlikely(s->ss_active)) {
         /* An indirect jump so that we still trigger the debug exception.  */
         gen_set_pc_im(s, dest);
         s->base.is_jmp = DISAS_JUMP;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
 
     /* If architectural single step active, limit to 1.  */
-    if (is_singlestepping(dc)) {
+    if (dc->ss_active) {
         dc->base.max_insns = 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          * insn codepath itself.
          */
         gen_bx_excret_final_code(dc);
-    } else if (unlikely(is_singlestepping(dc))) {
+    } else if (unlikely(dc->ss_active)) {
         /* Unconditional and "condition passed" instruction codepath. */
         switch (dc->base.is_jmp) {
         case DISAS_SWI:
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         /* "Condition failed" instruction codepath for the branch/trap insn */
         gen_set_label(dc->condlabel);
         gen_set_condexec(dc);
-        if (unlikely(is_singlestepping(dc))) {
+        if (unlikely(dc->ss_active)) {
             gen_set_pc_im(dc, dc->base.pc_next);
             gen_singlestep_exception(dc);
         } else {
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
     } else {
         copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
         copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
-        if (ctx->base.singlestep_enabled) {
-            gen_excp_1(EXCP_DEBUG);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
         gen_helper_rfi(cpu_env);
     }
     /* Exit the TB to recognize new interrupts.  */
-    if (ctx->base.singlestep_enabled) {
-        gen_excp_1(EXCP_DEBUG);
-    } else {
-        tcg_gen_exit_tb(NULL, 0);
-    }
+    tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
 
     return nullify_end(ctx);
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
         nullify_save(ctx);
         /* FALLTHRU */
     case DISAS_IAQ_N_UPDATED:
-        if (ctx->base.singlestep_enabled) {
-            gen_excp_1(EXCP_DEBUG);
-        } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
+        if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
             tcg_gen_lookup_and_goto_ptr();
+            break;
         }
         /* FALLTHRU */
     case DISAS_EXIT:
-- 
2.25.1

We were using singlestep_enabled as a proxy for whether
translator_use_goto_tb would always return false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/tcg/translate.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUX86State *env = cpu->env_ptr;
     uint32_t flags = dc->base.tb->flags;
+    uint32_t cflags = tb_cflags(dc->base.tb);
     int cpl = (flags >> HF_CPL_SHIFT) & 3;
     int iopl = (flags >> IOPL_SHIFT) & 3;
 
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
     dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
     dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
     dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
-    dc->jmp_opt = !(dc->base.singlestep_enabled ||
+    dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
                     (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
     /*
      * If jmp_opt, we want to handle each string instruction individually.
      * For icount also disable repz optimization so that each iteration
      * is accounted separately.
      */
-    dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
+    dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
 
     dc->T0 = tcg_temp_new();
     dc->T1 = tcg_temp_new();
-- 
2.25.1

GDB single-stepping is now handled generically.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/helper.h          | 1 -
 target/i386/tcg/misc_helper.c | 8 --------
 target/i386/tcg/translate.c   | 4 +---
 3 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/target/i386/helper.h b/target/i386/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
 DEF_HELPER_2(sysret, void, env, int)
 #endif
 DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
 DEF_HELPER_1(reset_rf, void, env)
 DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
     do_pause(env);
 }
 
-void QEMU_NORETURN helper_debug(CPUX86State *env)
-{
-    CPUState *cs = env_cpu(env);
-
-    cs->exception_index = EXCP_DEBUG;
-    cpu_loop_exit(cs);
-}
-
 uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
 {
     if ((env->cr[4] & CR4_PKE_MASK) == 0) {
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
     if (s->base.tb->flags & HF_RF_MASK) {
         gen_helper_reset_rf(cpu_env);
     }
-    if (s->base.singlestep_enabled) {
-        gen_helper_debug(cpu_env);
-    } else if (recheck_tf) {
+    if (recheck_tf) {
         gen_helper_rechecking_single_step(cpu_env);
         tcg_gen_exit_tb(NULL, 0);
     } else if (s->flags & HF_TF_MASK) {
-- 
2.25.1

GDB single-stepping is now handled generically.

Acked-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/m68k/translate.c | 44 +++++++++--------------------------------
 1 file changed, 9 insertions(+), 35 deletions(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
     }
 }
 
-static bool is_singlestepping(DisasContext *s)
-{
-    /*
-     * Return true if we are singlestepping either because of
-     * architectural singlestep or QEMU gdbstub singlestep. This does
-     * not include the command line '-singlestep' mode which is rather
-     * misnamed as it only means "one instruction per TB" and doesn't
-     * affect the code we generate.
-     */
-    return s->base.singlestep_enabled || s->ss_active;
-}
-
 /* is_jmp field values */
 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 #define DISAS_EXIT      DISAS_TARGET_1 /* cpu state was modified dynamically */
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_singlestep_exception(DisasContext *s)
-{
-    /*
-     * Generate the right kind of exception for singlestep, which is
-     * either the architectural singlestep or EXCP_DEBUG for QEMU's
-     * gdb singlestepping.
-     */
-    if (s->ss_active) {
-        gen_raise_exception(EXCP_TRACE);
-    } else {
-        gen_raise_exception(EXCP_DEBUG);
-    }
-}
-
 static inline void gen_addr_fault(DisasContext *s)
 {
     gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
 /* Generate a jump to an immediate address.  */
 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
 {
-    if (unlikely(is_singlestepping(s))) {
+    if (unlikely(s->ss_active)) {
         update_cc_op(s);
         tcg_gen_movi_i32(QREG_PC, dest);
-        gen_singlestep_exception(s);
+        gen_raise_exception(EXCP_TRACE);
     } else if (translator_use_goto_tb(&s->base, dest)) {
         tcg_gen_goto_tb(n);
         tcg_gen_movi_i32(QREG_PC, dest);
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
 
     dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
     /* If architectural single step active, limit to 1 */
-    if (is_singlestepping(dc)) {
+    if (dc->ss_active) {
         dc->base.max_insns = 1;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         break;
     case DISAS_TOO_MANY:
         update_cc_op(dc);
-        if (is_singlestepping(dc)) {
+        if (dc->ss_active) {
             tcg_gen_movi_i32(QREG_PC, dc->pc);
-            gen_singlestep_exception(dc);
+            gen_raise_exception(EXCP_TRACE);
         } else {
             gen_jmp_tb(dc, 0, dc->pc);
         }
         break;
     case DISAS_JUMP:
         /* We updated CC_OP and PC in gen_jmp/gen_jmp_im.  */
-        if (is_singlestepping(dc)) {
-            gen_singlestep_exception(dc);
+        if (dc->ss_active) {
+            gen_raise_exception(EXCP_TRACE);
         } else {
             tcg_gen_lookup_and_goto_ptr();
         }
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          * We updated CC_OP and PC in gen_exit_tb, but also modified
          * other state that may require returning to the main loop.
          */
-        if (is_singlestepping(dc)) {
-            gen_singlestep_exception(dc);
+        if (dc->ss_active) {
+            gen_raise_exception(EXCP_TRACE);
         } else {
             tcg_gen_exit_tb(NULL, 0);
         }
-- 
2.25.1

We were using singlestep_enabled as a proxy for whether
translator_use_goto_tb would always return false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
         break;
 
     case DISAS_JUMP:
-        if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
+        if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
             /* Direct jump. */
             tcg_gen_discard_i32(cpu_btarget);
 
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
             return;
         }
 
-        /* Indirect jump (or direct jump w/ singlestep) */
+        /* Indirect jump (or direct jump w/ goto_tb disabled) */
         tcg_gen_mov_i32(cpu_pc, cpu_btarget);
         tcg_gen_discard_i32(cpu_btarget);
 
-- 
2.25.1

GDB single-stepping is now handled generically.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
 
 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
 {
-    if (dc->base.singlestep_enabled) {
-        TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
-        tcg_gen_movi_i32(cpu_pc, dest);
-        gen_helper_raise_exception(cpu_env, tmp);
-        tcg_temp_free_i32(tmp);
-    } else if (translator_use_goto_tb(&dc->base, dest)) {
+    if (translator_use_goto_tb(&dc->base, dest)) {
         tcg_gen_goto_tb(n);
         tcg_gen_movi_i32(cpu_pc, dest);
         tcg_gen_exit_tb(dc->base.tb, n);
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
         /* Indirect jump (or direct jump w/ goto_tb disabled) */
         tcg_gen_mov_i32(cpu_pc, cpu_btarget);
         tcg_gen_discard_i32(cpu_btarget);
-
-        if (unlikely(cs->singlestep_enabled)) {
-            gen_raise_exception(dc, EXCP_DEBUG);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
         return;
 
     default:
-- 
2.25.1

As per an ancient comment in mips_tr_translate_insn about the
expectations of gdb, when restarting the insn in a delay slot
we also re-execute the branch.  Which means that we are
expected to execute two insns in this case.

This has been broken since 8b86d6d2580, where we forced max_insns
to 1 while single-stepping.  This resulted in an exit from the
translator loop after the branch but before the delay slot is
translated.

Increase the max_insns to 2 for this case.  In addition, bypass
the end-of-page check, for when the branch itself ends the page.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/translate.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
                                   INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
 
+    /*
+     * Execute a branch and its delay slot as a single instruction.
+     * This is what GDB expects and is consistent with what the
+     * hardware does (e.g. if a delay slot instruction faults, the
+     * reported PC is the PC of the branch).
+     */
+    if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
+        ctx->base.max_insns = 2;
+    }
+
     LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
               ctx->hflags);
 }
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     if (ctx->base.is_jmp != DISAS_NEXT) {
         return;
     }
+
     /*
-     * Execute a branch and its delay slot as a single instruction.
-     * This is what GDB expects and is consistent with what the
-     * hardware does (e.g. if a delay slot instruction faults, the
-     * reported PC is the PC of the branch).
+     * End the TB on (most) page crossings.
+     * See mips_tr_init_disas_context about single-stepping a branch
+     * together with its delay slot.
      */
-    if (ctx->base.singlestep_enabled &&
-        (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
-        ctx->base.is_jmp = DISAS_TOO_MANY;
-    }
-    if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
+    if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
+        && !ctx->base.singlestep_enabled) {
         ctx->base.is_jmp = DISAS_TOO_MANY;
     }
 }
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/translate.c | 50 +++++++++++++------------------------
 1 file changed, 18 insertions(+), 32 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         gen_save_pc(dest);
-        if (ctx->base.singlestep_enabled) {
-            save_cpu_state(ctx, 0);
-            gen_helper_raise_exception_debug(cpu_env);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
             } else {
                 tcg_gen_mov_tl(cpu_PC, btarget);
             }
-            if (ctx->base.singlestep_enabled) {
-                save_cpu_state(ctx, 0);
-                gen_helper_raise_exception_debug(cpu_env);
-            }
             tcg_gen_lookup_and_goto_ptr();
             break;
         default:
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
-        save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
-        gen_helper_raise_exception_debug(cpu_env);
-    } else {
-        switch (ctx->base.is_jmp) {
-        case DISAS_STOP:
-            gen_save_pc(ctx->base.pc_next);
-            tcg_gen_lookup_and_goto_ptr();
-            break;
-        case DISAS_NEXT:
-        case DISAS_TOO_MANY:
-            save_cpu_state(ctx, 0);
-            gen_goto_tb(ctx, 0, ctx->base.pc_next);
-            break;
-        case DISAS_EXIT:
-            tcg_gen_exit_tb(NULL, 0);
-            break;
-        case DISAS_NORETURN:
-            break;
-        default:
-            g_assert_not_reached();
-        }
+    switch (ctx->base.is_jmp) {
+    case DISAS_STOP:
+        gen_save_pc(ctx->base.pc_next);
+        tcg_gen_lookup_and_goto_ptr();
+        break;
+    case DISAS_NEXT:
+    case DISAS_TOO_MANY:
+        save_cpu_state(ctx, 0);
+        gen_goto_tb(ctx, 0, ctx->base.pc_next);
+        break;
+    case DISAS_EXIT:
+        tcg_gen_exit_tb(NULL, 0);
+        break;
+    case DISAS_NORETURN:
+        break;
+    default:
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/translate.c | 18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
             /* The jump destination is indirect/computed; use jmp_pc.  */
             tcg_gen_mov_tl(cpu_pc, jmp_pc);
             tcg_gen_discard_tl(jmp_pc);
-            if (unlikely(dc->base.singlestep_enabled)) {
-                gen_exception(dc, EXCP_DEBUG);
-            } else {
-                tcg_gen_lookup_and_goto_ptr();
-            }
+            tcg_gen_lookup_and_goto_ptr();
             break;
         }
         /* The jump destination is direct; use jmp_pc_imm.
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
             break;
         }
         tcg_gen_movi_tl(cpu_pc, jmp_dest);
-        if (unlikely(dc->base.singlestep_enabled)) {
-            gen_exception(dc, EXCP_DEBUG);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
         break;
 
     case DISAS_EXIT:
-        if (unlikely(dc->base.singlestep_enabled)) {
-            gen_exception(dc, EXCP_DEBUG);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
         break;
     default:
         g_assert_not_reached();
-- 
2.25.1

GDB single-stepping is now handled generically.
Reuse gen_debug_exception to handle architectural debug exceptions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c | 38 ++++++++------------------------------
 1 file changed, 8 insertions(+), 30 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -XXX,XX +XXX,XX @@
 
 #define CPU_SINGLE_STEP 0x1
 #define CPU_BRANCH_STEP 0x2
-#define GDBSTUB_SINGLE_STEP 0x4
 
 /* Include definitions for instructions classes and implementations flags */
 /* #define PPC_DEBUG_DISAS */
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
 
 static void gen_debug_exception(DisasContext *ctx)
 {
-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
+    gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 
 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
 {
-    int sse = ctx->singlestep_enabled;
-    if (unlikely(sse)) {
-        if (sse & GDBSTUB_SINGLE_STEP) {
-            gen_debug_exception(ctx);
-        } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
-            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+    if (unlikely(ctx->singlestep_enabled)) {
+        gen_debug_exception(ctx);
     } else {
         tcg_gen_lookup_and_goto_ptr();
     }
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->singlestep_enabled = 0;
     if ((hflags >> HFLAGS_SE) & 1) {
         ctx->singlestep_enabled |= CPU_SINGLE_STEP;
+        ctx->base.max_insns = 1;
     }
     if ((hflags >> HFLAGS_BE) & 1) {
         ctx->singlestep_enabled |= CPU_BRANCH_STEP;
     }
-    if (unlikely(ctx->base.singlestep_enabled)) {
-        ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
-    }
-
-    if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
-        ctx->base.max_insns = 1;
-    }
 }
 
 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     DisasJumpType is_jmp = ctx->base.is_jmp;
     target_ulong nip = ctx->base.pc_next;
-    int sse;
 
     if (is_jmp == DISAS_NORETURN) {
         /* We have already exited the TB. */
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
     }
 
     /* Honor single stepping. */
-    sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
-    if (unlikely(sse)) {
+    if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
+        && (nip <= 0x100 || nip > 0xf00)) {
         switch (is_jmp) {
         case DISAS_TOO_MANY:
         case DISAS_EXIT_UPDATE:
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
             g_assert_not_reached();
         }
 
-        if (sse & GDBSTUB_SINGLE_STEP) {
-            gen_debug_exception(ctx);
-            return;
-        }
-        /* else CPU_SINGLE_STEP... */
-        if (nip <= 0x100 || nip > 0xf00) {
-            gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
-            return;
-        }
+        gen_debug_exception(ctx);
+        return;
     }
 
     switch (is_jmp) {
-- 
2.25.1

We have already set DISAS_NORETURN in generate_exception,
which makes the exit_tb unreachable.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
 {
     /* always generates U-level ECALL, fixed in do_interrupt handler */
     generate_exception(ctx, RISCV_EXCP_U_ECALL);
-    exit_tb(ctx); /* no chaining */
-    ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
         post   = opcode_at(&ctx->base, post_addr);
     }
 
-    if  (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+    if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
-    exit_tb(ctx); /* no chaining */
-    ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
 
-- 
2.25.1

GDB single-stepping is now handled generically, which means
we don't need to do anything in the wrappers.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/translate.c                      | 27 +------------------
 .../riscv/insn_trans/trans_privileged.c.inc   |  4 +--
 target/riscv/insn_trans/trans_rvi.c.inc       |  8 +++---
 target/riscv/insn_trans/trans_rvv.c.inc       |  2 +-
 4 files changed, 7 insertions(+), 34 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception_debug(void)
-{
-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
-}
-
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
-static void exit_tb(DisasContext *ctx)
-{
-    if (ctx->base.singlestep_enabled) {
-        gen_exception_debug();
-    } else {
-        tcg_gen_exit_tb(NULL, 0);
-    }
-}
-
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
-static void lookup_and_goto_ptr(DisasContext *ctx)
-{
-    if (ctx->base.singlestep_enabled) {
-        gen_exception_debug();
-    } else {
-        tcg_gen_lookup_and_goto_ptr();
-    }
-}
-
 static void gen_exception_illegal(DisasContext *ctx)
 {
     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         tcg_gen_movi_tl(cpu_pc, dest);
-        lookup_and_goto_ptr(ctx);
+        tcg_gen_lookup_and_goto_ptr();
     }
 }
 
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 
     if (has_ext(ctx, RVS)) {
         gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
-        exit_tb(ctx); /* no chaining */
+        tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 #ifndef CONFIG_USER_ONLY
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
     gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
-    exit_tb(ctx); /* no chaining */
+    tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     if (a->rd != 0) {
         tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
     }
-
-    /* No chaining with JALR. */
-    lookup_and_goto_ptr(ctx);
+    tcg_gen_lookup_and_goto_ptr();
 
     if (misaligned) {
         gen_set_label(misaligned);
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * however we need to end the translation block
      */
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-    exit_tb(ctx);
+    tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
 {
     /* We may have changed important cpu state -- exit to main loop. */
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-    exit_tb(ctx);
+    tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
     gen_set_gpr(ctx, a->rd, dst);
 
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-    lookup_and_goto_ptr(ctx);
+    tcg_gen_lookup_and_goto_ptr();
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/rx/helper.h    |  1 -
 target/rx/op_helper.c |  8 --------
 target/rx/translate.c | 12 ++----------
 3 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/target/rx/helper.h b/target/rx/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/helper.h
+++ b/target/rx/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
 DEF_HELPER_1(raise_access_fault, noreturn, env)
 DEF_HELPER_1(raise_privilege_violation, noreturn, env)
 DEF_HELPER_1(wait, noreturn, env)
-DEF_HELPER_1(debug, noreturn, env)
 DEF_HELPER_2(rxint, noreturn, env, i32)
 DEF_HELPER_1(rxbrk, noreturn, env)
 DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
     raise_exception(env, EXCP_HLT, 0);
 }
 
-void QEMU_NORETURN helper_debug(CPURXState *env)
-{
-    CPUState *cs = env_cpu(env);
-
-    cs->exception_index = EXCP_DEBUG;
-    cpu_loop_exit(cs);
-}
-
 void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
 {
     raise_exception(env, 0x100 + vec, 0);
diff --git a/target/rx/translate.c b/target/rx/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
         tcg_gen_exit_tb(dc->base.tb, n);
     } else {
         tcg_gen_movi_i32(cpu_pc, dest);
-        if (dc->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
     }
     dc->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
         gen_goto_tb(ctx, 0, dcbase->pc_next);
         break;
     case DISAS_JUMP:
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
         break;
     case DISAS_UPDATE:
         tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
-- 
2.25.1

GDB single-stepping is now handled generically.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/tcg/translate.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
     uint64_t pc_tmp;
     uint32_t ilen;
     enum cc_op cc_op;
-    bool do_debug;
 };
 
 /* Information carried about a condition to be evaluated.  */
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 
     dc->cc_op = CC_OP_DYNAMIC;
     dc->ex_value = dc->base.tb->cs_base;
-    dc->do_debug = dc->base.singlestep_enabled;
 }
 
 static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
         /* FALLTHRU */
     case DISAS_PC_CC_UPDATED:
         /* Exit the TB, either by raising a debug exception or by return.  */
-        if (dc->do_debug) {
-            gen_exception(EXCP_DEBUG);
-        } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
-                   dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
+        if ((dc->base.tb->flags & FLAG_MASK_PER) ||
+             dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
             tcg_gen_exit_tb(NULL, 0);
         } else {
             tcg_gen_lookup_and_goto_ptr();
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/helper.h    |  1 -
 target/sh4/op_helper.c |  5 -----
 target/sh4/translate.c | 14 +++-----------
 3 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/target/sh4/helper.h b/target/sh4/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/helper.h
+++ b/target/sh4/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
 DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
 DEF_HELPER_1(raise_fpu_disable, noreturn, env)
 DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
-DEF_HELPER_1(debug, noreturn, env)
 DEF_HELPER_1(sleep, noreturn, env)
 DEF_HELPER_2(trapa, noreturn, env, i32)
 DEF_HELPER_1(exclusive, noreturn, env)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
     raise_exception(env, 0x820, 0);
 }
 
-void helper_debug(CPUSH4State *env)
-{
-    raise_exception(env, EXCP_DEBUG, 0);
-}
-
 void helper_sleep(CPUSH4State *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         tcg_gen_movi_i32(cpu_pc, dest);
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else if (use_exit_tb(ctx)) {
+        if (use_exit_tb(ctx)) {
             tcg_gen_exit_tb(NULL, 0);
         } else {
             tcg_gen_lookup_and_goto_ptr();
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
 	   delayed jump as immediate jump are conditinal jumps */
 	tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
         tcg_gen_discard_i32(cpu_delayed_pc);
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else if (use_exit_tb(ctx)) {
+        if (use_exit_tb(ctx)) {
             tcg_gen_exit_tb(NULL, 0);
         } else {
             tcg_gen_lookup_and_goto_ptr();
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
     switch (ctx->base.is_jmp) {
     case DISAS_STOP:
         gen_save_cpu_state(ctx, true);
-        if (ctx->base.singlestep_enabled) {
-            gen_helper_debug(cpu_env);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
         break;
     case DISAS_NEXT:
     case DISAS_TOO_MANY:
-- 
2.25.1

GDB single-stepping is now handled generically.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/tricore/helper.h    |  1 -
 target/tricore/op_helper.c |  7 -------
 target/tricore/translate.c | 14 +-------------
 3 files changed, 1 insertion(+), 21 deletions(-)

diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
 DEF_HELPER_1(psw_read, i32, env)
 /* Exceptions */
 DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
     raise_exception_sync_internal(env, class, tin, pc, 0);
 }
 
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
-{
-    CPUState *cs = env_cpu(env);
-    cs->exception_index = excp;
-    cpu_loop_exit(cs);
-}
-
 /* Addressing mode helper */
 
 static uint16_t reverse16(uint16_t val)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
     tcg_gen_movi_tl(cpu_PC, pc);
 }
 
-static void generate_qemu_excp(DisasContext *ctx, int excp)
-{
-    TCGv_i32 tmp = tcg_const_i32(excp);
-    gen_helper_qemu_excp(cpu_env, tmp);
-    ctx->base.is_jmp = DISAS_NORETURN;
-    tcg_temp_free(tmp);
-}
-
 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         gen_save_pc(dest);
-        if (ctx->base.singlestep_enabled) {
-            generate_qemu_excp(ctx, EXCP_DEBUG);
-        } else {
-            tcg_gen_lookup_and_goto_ptr();
-        }
+        tcg_gen_lookup_and_goto_ptr();
     }
 }
 
-- 
2.25.1

GDB single-stepping is now handled generically.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/translate.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
     if (dc->icount) {
         tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
     }
-    if (dc->base.singlestep_enabled) {
-        gen_exception(dc, EXCP_DEBUG);
+    if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
+        slot = gen_postprocess(dc, slot);
+    }
+    if (slot >= 0) {
+        tcg_gen_goto_tb(slot);
+        tcg_gen_exit_tb(dc->base.tb, slot);
     } else {
-        if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
-            slot = gen_postprocess(dc, slot);
-        }
-        if (slot >= 0) {
-            tcg_gen_goto_tb(slot);
-            tcg_gen_exit_tb(dc->base.tb, slot);
-        } else {
-            tcg_gen_exit_tb(NULL, 0);
-        }
+        tcg_gen_exit_tb(NULL, 0);
     }
     dc->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
     case DISAS_NORETURN:
         break;
     case DISAS_TOO_MANY:
-        if (dc->base.singlestep_enabled) {
-            tcg_gen_movi_i32(cpu_pc, dc->pc);
-            gen_exception(dc, EXCP_DEBUG);
-        } else {
-            gen_jumpi(dc, dc->pc, 0);
-        }
+        gen_jumpi(dc, dc->pc, 0);
         break;
     default:
         g_assert_not_reached();
-- 
2.25.1

This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.

Despite a comment saying why cpu_common_props cannot be placed in
a file that is compiled once, it was moved anyway.  Revert that.

Since then, Property is not defined in hw/core/cpu.h, so it is now
easier to declare a function to install the properties rather than
the Property array itself.

Cc: Eduardo Habkost <ehabkost@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h |  1 +
 cpu.c                 | 21 +++++++++++++++++++++
 hw/core/cpu-common.c  | 17 +----------------
 3 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
     GCC_FMT_ATTR(2, 3);
 
 /* $(top_srcdir)/cpu.c */
+void cpu_class_init_props(DeviceClass *dc);
 void cpu_exec_initfn(CPUState *cpu);
 void cpu_exec_realizefn(CPUState *cpu, Error **errp);
 void cpu_exec_unrealizefn(CPUState *cpu);
diff --git a/cpu.c b/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/cpu.c
+++ b/cpu.c
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
     cpu_list_remove(cpu);
 }
 
+static Property cpu_common_props[] = {
+#ifndef CONFIG_USER_ONLY
+    /*
+     * Create a memory property for softmmu CPU object,
+     * so users can wire up its memory. (This can't go in hw/core/cpu.c
+     * because that file is compiled only once for both user-mode
+     * and system builds.) The default if no link is set up is to use
+     * the system address space.
+     */
+    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+#endif
+    DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+void cpu_class_init_props(DeviceClass *dc)
+{
+    device_class_set_props(dc, cpu_common_props);
+}
+
 void cpu_exec_initfn(CPUState *cpu)
 {
     cpu->as = NULL;
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
-static Property cpu_common_props[] = {
-#ifndef CONFIG_USER_ONLY
-    /* Create a memory property for softmmu CPU object,
-     * so users can wire up its memory. (This can't go in hw/core/cpu.c
-     * because that file is compiled only once for both user-mode
-     * and system builds.) The default if no link is set up is to use
-     * the system address space.
-     */
-    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-#endif
-    DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
     dc->realize = cpu_common_realizefn;
     dc->unrealize = cpu_common_unrealizefn;
     dc->reset = cpu_common_reset;
-    device_class_set_props(dc, cpu_common_props);
+    cpu_class_init_props(dc);
     /*
      * Reason: CPUs still need special care by board code: wiring up
      * IRQs, adding reset handlers, halting non-first CPUs, ...
-- 
2.25.1