Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/riscv/cpu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..0619b491a42 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,7 +97,9 @@ enum {
 
 typedef struct CPURISCVState CPURISCVState;
 
+#if !defined(CONFIG_USER_ONLY)
 #include "pmp.h"
+#endif
 
 #define RV_VLEN_MAX 256
 
-- 
2.26.3

Oops this is v1, not v2.

On Sun, May 16, 2021 at 10:53 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/riscv/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
>  typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
>  #include "pmp.h"
> +#endif
>
>  #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>

On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
>  typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
>  #include "pmp.h"
> +#endif
>
>  #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>

On Mon, May 17, 2021 at 4:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/riscv/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
>  typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
>  #include "pmp.h"
> +#endif
>
>  #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>

Le 16/05/2021 à 22:53, Philippe Mathieu-Daudé a écrit :
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/riscv/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>  
>  typedef struct CPURISCVState CPURISCVState;
>  
> +#if !defined(CONFIG_USER_ONLY)
>  #include "pmp.h"
> +#endif
>  
>  #define RV_VLEN_MAX 256
>  
> 

Applied to my trivial-patches branch.

Thanks,
Laurent