[PULL v2 0/4] tcg patch queue
[PULL v3 00/44] tcg patch queue
1
Version 2 drops the bsd cleanup and includes a minor improvement
1
Version 3: Rebase and fix a minor patch conflict.
2
to the dump of the constant pool.
3
2
4
3
5
r~
4
r~
6
5
7
6
8
The following changes since commit 2d3fc4e2b069494b1e9e2e4a1e3de24cbc036426:
7
The following changes since commit c6f5e042d89e79206cd1ce5525d3df219f13c3cc:
9
8
10
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into staging (2021-05-13 20:13:24 +0100)
9
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-3' into staging (2021-09-13 21:06:15 +0100)
11
10
12
are available in the Git repository at:
11
are available in the Git repository at:
13
12
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210516
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914
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14
16
for you to fetch changes up to 6c6a4a76eea900112c343ba4f9c5737e298feddf:
15
for you to fetch changes up to a5b759b6dca7daf87fa5007a7f5784bf22f3830f:
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16
18
accel/tcg: Align data dumped at end of TB (2021-05-16 09:05:14 -0500)
17
tcg/arm: More use of the TCGReg enum (2021-09-14 07:59:43 -0700)
19
18
20
----------------------------------------------------------------
19
----------------------------------------------------------------
21
Minor MAINTAINERS update.
20
Fix translation race condition for user-only.
22
Tweak to includes.
21
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
23
Add tcg_constant_tl.
22
Fix tcg/arm tcg_out_vec_op signature.
24
Improve constant pool dump.
23
Fix tcg/ppc (32bit) build with clang.
24
Remove dupluate TCG_KICK_PERIOD definition.
25
Remove unused tcg_global_reg_new.
26
Restrict cpu_exec_interrupt and its callees to sysemu.
27
Cleanups for tcg/arm.
25
28
26
----------------------------------------------------------------
29
----------------------------------------------------------------
27
Matheus Ferst (1):
30
Bin Meng (1):
28
tcg: Add tcg_constant_tl
31
tcg: Remove tcg_global_reg_new defines
29
32
30
Philippe Mathieu-Daudé (3):
33
Ilya Leoshkevich (3):
31
MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section
34
accel/tcg: Add DisasContextBase argument to translator_ld*
32
exec/gen-icount.h: Add missing "exec/exec-all.h" include
35
accel/tcg: Clear PAGE_WRITE before translation
33
accel/tcg: Align data dumped at end of TB
36
accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
34
37
35
include/exec/gen-icount.h | 1 +
38
Jose R. Ziviani (1):
36
include/tcg/tcg-op.h | 2 ++
39
tcg/arm: Fix tcg_out_vec_op function signature
37
accel/tcg/translate-all.c | 11 +++++++++--
38
MAINTAINERS | 1 +
39
4 files changed, 13 insertions(+), 2 deletions(-)
40
40
41
Luc Michel (1):
42
accel/tcg: remove redundant TCG_KICK_PERIOD define
43
44
Philippe Mathieu-Daudé (25):
45
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
46
target/i386: Restrict sysemu-only fpu_helper helpers
47
target/i386: Simplify TARGET_X86_64 #ifdef'ry
48
target/xtensa: Restrict do_transaction_failed() to sysemu
49
accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
50
target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
51
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
52
target/cris: Restrict cpu_exec_interrupt() handler to sysemu
53
target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
54
target/i386: Restrict cpu_exec_interrupt() handler to sysemu
55
target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
56
target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
57
target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
58
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
59
target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
60
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
61
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
62
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
63
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
64
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
65
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
66
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
67
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
68
user: Remove cpu_get_pic_interrupt() stubs
69
user: Mark cpu_loop() with noreturn attribute
70
71
Richard Henderson (13):
72
tcg/i386: Split P_VEXW from P_REXW
73
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
74
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
75
tcg/arm: Remove fallback definition of __ARM_ARCH
76
tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
77
tcg/arm: Simplify use_armv5t_instructions
78
tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
79
tcg/arm: Split out tcg_out_ldstm
80
tcg/arm: Simplify usage of encode_imm
81
tcg/arm: Drop inline markers
82
tcg/arm: Give enum arm_cond_code_e a typedef and use it
83
tcg/arm: More use of the ARMInsn enum
84
tcg/arm: More use of the TCGReg enum
85
86
bsd-user/qemu.h | 2 +-
87
include/exec/translate-all.h | 1 +
88
include/exec/translator.h | 44 +--
89
include/hw/core/tcg-cpu-ops.h | 26 +-
90
include/tcg/tcg-op.h | 2 -
91
linux-user/qemu.h | 2 +-
92
target/alpha/cpu.h | 2 +-
93
target/arm/arm_ldst.h | 12 +-
94
target/arm/cpu.h | 3 +-
95
target/cris/cpu.h | 2 +-
96
target/hppa/cpu.h | 4 +-
97
target/i386/cpu.h | 3 +
98
target/i386/tcg/helper-tcg.h | 2 +
99
target/m68k/cpu.h | 2 +
100
target/microblaze/cpu.h | 2 +
101
target/mips/tcg/tcg-internal.h | 5 +-
102
target/openrisc/cpu.h | 5 +-
103
target/ppc/cpu.h | 4 +-
104
target/riscv/cpu.h | 2 +-
105
target/rx/cpu.h | 2 +
106
target/sh4/cpu.h | 4 +-
107
target/xtensa/cpu.h | 2 +
108
tcg/arm/tcg-target.h | 27 +-
109
accel/tcg/cpu-exec.c | 14 +-
110
accel/tcg/tcg-accel-ops-rr.c | 2 -
111
accel/tcg/translate-all.c | 59 ++--
112
accel/tcg/translator.c | 39 +++
113
accel/tcg/user-exec.c | 48 ++-
114
bsd-user/i386/target_arch_cpu.c | 5 -
115
bsd-user/x86_64/target_arch_cpu.c | 5 -
116
linux-user/main.c | 7 -
117
target/alpha/cpu.c | 2 +-
118
target/alpha/helper.c | 5 +-
119
target/alpha/translate.c | 2 +-
120
target/arm/cpu.c | 7 +-
121
target/arm/cpu_tcg.c | 6 +-
122
target/arm/translate-a64.c | 2 +-
123
target/arm/translate.c | 9 +-
124
target/avr/cpu.c | 3 -
125
target/cris/cpu.c | 4 +-
126
target/cris/helper.c | 17 +-
127
target/hexagon/translate.c | 3 +-
128
target/hppa/cpu.c | 2 +-
129
target/hppa/int_helper.c | 7 +-
130
target/hppa/translate.c | 5 +-
131
target/i386/tcg/seg_helper.c | 74 +----
132
target/i386/tcg/sysemu/seg_helper.c | 62 ++++
133
target/i386/tcg/tcg-cpu.c | 8 +-
134
target/i386/tcg/translate.c | 10 +-
135
target/m68k/cpu.c | 2 +-
136
target/m68k/op_helper.c | 16 +-
137
target/m68k/translate.c | 2 +-
138
target/microblaze/cpu.c | 2 +-
139
target/microblaze/helper.c | 13 +-
140
target/mips/cpu.c | 2 +-
141
target/mips/tcg/exception.c | 18 --
142
target/mips/tcg/sysemu/tlb_helper.c | 18 ++
143
target/mips/tcg/translate.c | 8 +-
144
target/mips/tcg/user/tlb_helper.c | 5 -
145
target/nios2/cpu.c | 5 +-
146
target/openrisc/cpu.c | 2 +-
147
target/openrisc/interrupt.c | 2 -
148
target/openrisc/translate.c | 2 +-
149
target/ppc/cpu_init.c | 2 +-
150
target/ppc/excp_helper.c | 21 +-
151
target/ppc/translate.c | 5 +-
152
target/riscv/cpu.c | 2 +-
153
target/riscv/cpu_helper.c | 5 -
154
target/riscv/translate.c | 5 +-
155
target/rx/cpu.c | 2 +-
156
target/rx/helper.c | 4 +
157
target/s390x/tcg/translate.c | 16 +-
158
target/sh4/cpu.c | 2 +-
159
target/sh4/helper.c | 9 +-
160
target/sh4/translate.c | 4 +-
161
target/sparc/cpu.c | 4 +-
162
target/sparc/translate.c | 2 +-
163
target/xtensa/cpu.c | 2 +-
164
target/xtensa/exc_helper.c | 7 +-
165
target/xtensa/translate.c | 5 +-
166
target/mips/tcg/micromips_translate.c.inc | 2 +-
167
target/mips/tcg/mips16e_translate.c.inc | 4 +-
168
target/mips/tcg/nanomips_translate.c.inc | 4 +-
169
tcg/arm/tcg-target.c.inc | 517 ++++++++++++++++--------------
170
tcg/i386/tcg-target.c.inc | 13 +-
171
tcg/ppc/tcg-target.c.inc | 25 +-
172
target/openrisc/meson.build | 6 +-
173
87 files changed, 702 insertions(+), 630 deletions(-)
174
diff view generated by jsdifflib
[PULL v2 1/4] MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
As the 'Main Loop' section covers softmmu/icount.c,
4
add "exec/gen-icount.h" there too.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-Id: <20210422064128.2318616-2-f4bug@amsat.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
MAINTAINERS | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/MAINTAINERS b/MAINTAINERS
14
index XXXXXXX..XXXXXXX 100644
15
--- a/MAINTAINERS
16
+++ b/MAINTAINERS
17
@@ -XXX,XX +XXX,XX @@ F: ui/cocoa.m
18
Main loop
19
M: Paolo Bonzini <pbonzini@redhat.com>
20
S: Maintained
21
+F: include/exec/gen-icount.h
22
F: include/qemu/main-loop.h
23
F: include/sysemu/runstate.h
24
F: include/sysemu/runstate-action.h
25
--
26
2.25.1
27
28
diff view generated by jsdifflib
[PULL v2 2/4] exec/gen-icount.h: Add missing "exec/exec-all.h" include
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When including "exec/gen-icount.h" we get:
4
5
include/exec/gen-icount.h: In function ‘gen_tb_start’:
6
include/exec/gen-icount.h:40:9: error: implicit declaration of function ‘tb_cflags’ [-Werror=implicit-function-declaration]
7
40 | if (tb_cflags(tb) & CF_USE_ICOUNT) {
8
| ^~~~~~~~~
9
include/exec/gen-icount.h:40:9: error: nested extern declaration of ‘tb_cflags’ [-Werror=nested-externs]
10
include/exec/gen-icount.h:40:25: error: ‘CF_USE_ICOUNT’ undeclared (first use in this function); did you mean ‘CPU_COUNT’?
11
40 | if (tb_cflags(tb) & CF_USE_ICOUNT) {
12
| ^~~~~~~~~~~~~
13
| CPU_COUNT
14
15
Since tb_cflags() is declared in "exec/exec-all.h", include this
16
header in "exec/gen-icount.h".
17
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-Id: <20210422064128.2318616-3-f4bug@amsat.org>
20
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
21
---
22
include/exec/gen-icount.h | 1 +
23
1 file changed, 1 insertion(+)
24
25
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/exec/gen-icount.h
28
+++ b/include/exec/gen-icount.h
29
@@ -XXX,XX +XXX,XX @@
30
#ifndef GEN_ICOUNT_H
31
#define GEN_ICOUNT_H
32
33
+#include "exec/exec-all.h"
34
#include "qemu/timer.h"
35
36
/* Helpers for instruction counting code generation. */
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
[PULL v2 3/4] tcg: Add tcg_constant_tl
Deleted patch
1
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
2
1
3
Used in ppc D/DS/X-form load/store implementation.
4
5
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
6
Message-Id: <20210512185441.3619828-24-matheus.ferst@eldorado.org.br>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/tcg/tcg-op.h | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/tcg/tcg-op.h
15
+++ b/include/tcg/tcg-op.h
16
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
17
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
18
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
19
#define tcg_const_tl tcg_const_i64
20
+#define tcg_constant_tl tcg_constant_i64
21
#define tcg_const_local_tl tcg_const_local_i64
22
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
23
#define tcg_gen_add2_tl tcg_gen_add2_i64
24
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
25
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
26
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
27
#define tcg_const_tl tcg_const_i32
28
+#define tcg_constant_tl tcg_constant_i32
29
#define tcg_const_local_tl tcg_const_local_i32
30
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
31
#define tcg_gen_add2_tl tcg_gen_add2_i32
32
--
33
2.25.1
34
35
diff view generated by jsdifflib
[PULL v2 4/4] accel/tcg: Align data dumped at end of TB
[PULL v3 01/44] accel/tcg: Add DisasContextBase argument to translator_ld*
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
2
3
To better visualize the data dumped at the end of a TB, left-align it
3
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
(padding it with 0). Print ".long" instead of ".quad" on 32-bit hosts.
4
[rth: Split out of a larger patch.]
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-Id: <20210515104202.241504-1-f4bug@amsat.org>
8
[rth: Split the qemu_log and print .long for 32-bit hosts.]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
6
---
11
accel/tcg/translate-all.c | 11 +++++++++--
7
include/exec/translator.h | 9 +++++----
12
1 file changed, 9 insertions(+), 2 deletions(-)
8
target/arm/arm_ldst.h | 12 ++++++------
9
target/alpha/translate.c | 2 +-
10
target/arm/translate-a64.c | 2 +-
11
target/arm/translate.c | 9 +++++----
12
target/hexagon/translate.c | 3 ++-
13
target/hppa/translate.c | 2 +-
14
target/i386/tcg/translate.c | 10 +++++-----
15
target/m68k/translate.c | 2 +-
16
target/mips/tcg/translate.c | 8 ++++----
17
target/openrisc/translate.c | 2 +-
18
target/ppc/translate.c | 5 +++--
19
target/riscv/translate.c | 5 +++--
20
target/s390x/tcg/translate.c | 16 +++++++++-------
21
target/sh4/translate.c | 4 ++--
22
target/sparc/translate.c | 2 +-
23
target/xtensa/translate.c | 5 +++--
24
target/mips/tcg/micromips_translate.c.inc | 2 +-
25
target/mips/tcg/mips16e_translate.c.inc | 4 ++--
26
target/mips/tcg/nanomips_translate.c.inc | 4 ++--
27
20 files changed, 58 insertions(+), 50 deletions(-)
13
28
14
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
29
diff --git a/include/exec/translator.h b/include/exec/translator.h
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/accel/tcg/translate-all.c
31
--- a/include/exec/translator.h
17
+++ b/accel/tcg/translate-all.c
32
+++ b/include/exec/translator.h
18
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
33
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
19
int i;
34
20
qemu_log(" data: [size=%d]\n", data_size);
35
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
21
for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) {
36
static inline type \
22
- qemu_log("0x%08" PRIxPTR ": .quad 0x%" TCG_PRIlx "\n",
37
- fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \
23
- (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
38
+ fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
24
+ if (sizeof(tcg_target_ulong) == 8) {
39
+ abi_ptr pc, bool do_swap) \
25
+ qemu_log("0x%08" PRIxPTR ": .quad 0x%016" TCG_PRIlx "\n",
40
{ \
26
+ (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
41
type ret = load_fn(env, pc); \
27
+ } else if (sizeof(tcg_target_ulong) == 4) {
42
if (do_swap) { \
28
+ qemu_log("0x%08" PRIxPTR ": .long 0x%08" TCG_PRIlx "\n",
43
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
29
+ (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
44
plugin_insn_append(&ret, sizeof(ret)); \
30
+ } else {
45
return ret; \
31
+ qemu_build_not_reached();
46
} \
32
+ }
47
- \
33
}
48
- static inline type fullname(CPUArchState *env, abi_ptr pc) \
34
}
49
+ static inline type fullname(CPUArchState *env, \
35
qemu_log("\n");
50
+ DisasContextBase *dcbase, abi_ptr pc) \
51
{ \
52
- return fullname ## _swap(env, pc, false); \
53
+ return fullname ## _swap(env, dcbase, pc, false); \
54
}
55
56
GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
57
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/arm_ldst.h
60
+++ b/target/arm/arm_ldst.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "qemu/bswap.h"
63
64
/* Load an instruction and return it in the standard little-endian order */
65
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
66
- bool sctlr_b)
67
+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
68
+ target_ulong addr, bool sctlr_b)
69
{
70
- return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
71
+ return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
72
}
73
74
/* Ditto, for a halfword (Thumb) instruction */
75
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
76
- bool sctlr_b)
77
+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
78
+ target_ulong addr, bool sctlr_b)
79
{
80
#ifndef CONFIG_USER_ONLY
81
/* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
82
@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
83
addr ^= 2;
84
}
85
#endif
86
- return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
87
+ return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
88
}
89
90
#endif
91
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/alpha/translate.c
94
+++ b/target/alpha/translate.c
95
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
96
{
97
DisasContext *ctx = container_of(dcbase, DisasContext, base);
98
CPUAlphaState *env = cpu->env_ptr;
99
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
100
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
101
102
ctx->base.pc_next += 4;
103
ctx->base.is_jmp = translate_one(ctx, insn);
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
109
}
110
111
s->pc_curr = s->base.pc_next;
112
- insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
113
+ insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
114
s->insn = insn;
115
s->base.pc_next += 4;
116
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
122
* boundary, so we cross the page if the first 16 bits indicate
123
* that this is a 32 bit insn.
124
*/
125
- uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
126
+ uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
127
128
return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
129
}
130
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
131
}
132
133
dc->pc_curr = dc->base.pc_next;
134
- insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
135
+ insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
136
dc->insn = insn;
137
dc->base.pc_next += 4;
138
disas_arm_insn(dc, insn);
139
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
140
}
141
142
dc->pc_curr = dc->base.pc_next;
143
- insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
144
+ insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
145
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
146
dc->base.pc_next += 2;
147
if (!is_16bit) {
148
- uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
149
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
150
+ dc->sctlr_b);
151
152
insn = insn << 16 | insn2;
153
dc->base.pc_next += 2;
154
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/hexagon/translate.c
157
+++ b/target/hexagon/translate.c
158
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
159
memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
160
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
161
words[nwords] =
162
- translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
163
+ translator_ldl(env, &ctx->base,
164
+ ctx->base.pc_next + nwords * sizeof(uint32_t));
165
found_end = is_packet_end(words[nwords]);
166
}
167
if (!found_end) {
168
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/hppa/translate.c
171
+++ b/target/hppa/translate.c
172
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
173
{
174
/* Always fetch the insn, even if nullified, so that we check
175
the page permissions for execute. */
176
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
177
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
178
179
/* Set up the IA queue for the next insn.
180
This will be overwritten by a branch. */
181
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/i386/tcg/translate.c
184
+++ b/target/i386/tcg/translate.c
185
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
186
187
static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
188
{
189
- return translator_ldub(env, advance_pc(env, s, 1));
190
+ return translator_ldub(env, &s->base, advance_pc(env, s, 1));
191
}
192
193
static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
194
{
195
- return translator_ldsw(env, advance_pc(env, s, 2));
196
+ return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
197
}
198
199
static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
200
{
201
- return translator_lduw(env, advance_pc(env, s, 2));
202
+ return translator_lduw(env, &s->base, advance_pc(env, s, 2));
203
}
204
205
static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
206
{
207
- return translator_ldl(env, advance_pc(env, s, 4));
208
+ return translator_ldl(env, &s->base, advance_pc(env, s, 4));
209
}
210
211
#ifdef TARGET_X86_64
212
static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
213
{
214
- return translator_ldq(env, advance_pc(env, s, 8));
215
+ return translator_ldq(env, &s->base, advance_pc(env, s, 8));
216
}
217
#endif
218
219
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/target/m68k/translate.c
222
+++ b/target/m68k/translate.c
223
@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
224
static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
225
{
226
uint16_t im;
227
- im = translator_lduw(env, s->pc);
228
+ im = translator_lduw(env, &s->base, s->pc);
229
s->pc += 2;
230
return im;
231
}
232
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/target/mips/tcg/translate.c
235
+++ b/target/mips/tcg/translate.c
236
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
237
238
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
239
if (ctx->insn_flags & ISA_NANOMIPS32) {
240
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
241
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
242
insn_bytes = decode_isa_nanomips(env, ctx);
243
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
244
- ctx->opcode = translator_ldl(env, ctx->base.pc_next);
245
+ ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
246
insn_bytes = 4;
247
decode_opc(env, ctx);
248
} else if (ctx->insn_flags & ASE_MICROMIPS) {
249
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
250
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
251
insn_bytes = decode_isa_micromips(env, ctx);
252
} else if (ctx->insn_flags & ASE_MIPS16) {
253
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
254
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
255
insn_bytes = decode_ase_mips16e(env, ctx);
256
} else {
257
gen_reserved_instruction(ctx);
258
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
259
index XXXXXXX..XXXXXXX 100644
260
--- a/target/openrisc/translate.c
261
+++ b/target/openrisc/translate.c
262
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
263
{
264
DisasContext *dc = container_of(dcbase, DisasContext, base);
265
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
266
- uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
267
+ uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
268
269
if (!decode(dc, insn)) {
270
gen_illegal_exception(dc);
271
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
272
index XXXXXXX..XXXXXXX 100644
273
--- a/target/ppc/translate.c
274
+++ b/target/ppc/translate.c
275
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
276
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
277
278
ctx->cia = pc = ctx->base.pc_next;
279
- insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
280
+ insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
281
ctx->base.pc_next = pc += 4;
282
283
if (!is_prefix_insn(ctx, insn)) {
284
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
285
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
286
ok = true;
287
} else {
288
- uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
289
+ uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
290
+ need_byteswap(ctx));
291
ctx->base.pc_next = pc += 4;
292
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
293
}
294
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
295
index XXXXXXX..XXXXXXX 100644
296
--- a/target/riscv/translate.c
297
+++ b/target/riscv/translate.c
298
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
299
} else {
300
uint32_t opcode32 = opcode;
301
opcode32 = deposit32(opcode32, 16, 16,
302
- translator_lduw(env, ctx->base.pc_next + 2));
303
+ translator_lduw(env, &ctx->base,
304
+ ctx->base.pc_next + 2));
305
ctx->pc_succ_insn = ctx->base.pc_next + 4;
306
if (!decode_insn32(ctx, opcode32)) {
307
gen_exception_illegal(ctx);
308
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
309
{
310
DisasContext *ctx = container_of(dcbase, DisasContext, base);
311
CPURISCVState *env = cpu->env_ptr;
312
- uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
313
+ uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
314
315
decode_opc(env, ctx, opcode16);
316
ctx->base.pc_next = ctx->pc_succ_insn;
317
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
318
index XXXXXXX..XXXXXXX 100644
319
--- a/target/s390x/tcg/translate.c
320
+++ b/target/s390x/tcg/translate.c
321
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
322
}
323
}
324
325
-static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
326
+static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
327
+ uint64_t pc)
328
{
329
- return (uint64_t)cpu_lduw_code(env, pc);
330
+ return (uint64_t)translator_lduw(env, &s->base, pc);
331
}
332
333
-static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
334
+static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
335
+ uint64_t pc)
336
{
337
- return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
338
+ return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
339
}
340
341
static int get_mem_index(DisasContext *s)
342
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
343
ilen = s->ex_value & 0xf;
344
op = insn >> 56;
345
} else {
346
- insn = ld_code2(env, pc);
347
+ insn = ld_code2(env, s, pc);
348
op = (insn >> 8) & 0xff;
349
ilen = get_ilen(op);
350
switch (ilen) {
351
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
352
insn = insn << 48;
353
break;
354
case 4:
355
- insn = ld_code4(env, pc) << 32;
356
+ insn = ld_code4(env, s, pc) << 32;
357
break;
358
case 6:
359
- insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
360
+ insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
361
break;
362
default:
363
g_assert_not_reached();
364
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
365
index XXXXXXX..XXXXXXX 100644
366
--- a/target/sh4/translate.c
367
+++ b/target/sh4/translate.c
368
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
369
370
/* Read all of the insns for the region. */
371
for (i = 0; i < max_insns; ++i) {
372
- insns[i] = translator_lduw(env, pc + i * 2);
373
+ insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
374
}
375
376
ld_adr = ld_dst = ld_mop = -1;
377
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
378
}
379
#endif
380
381
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
382
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
383
decode_opc(ctx);
384
ctx->base.pc_next += 2;
385
}
386
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/target/sparc/translate.c
389
+++ b/target/sparc/translate.c
390
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
391
CPUSPARCState *env = cs->env_ptr;
392
unsigned int insn;
393
394
- insn = translator_ldl(env, dc->pc);
395
+ insn = translator_ldl(env, &dc->base, dc->pc);
396
dc->base.pc_next += 4;
397
disas_sparc_insn(dc, insn);
398
399
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
400
index XXXXXXX..XXXXXXX 100644
401
--- a/target/xtensa/translate.c
402
+++ b/target/xtensa/translate.c
403
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
404
static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
405
{
406
xtensa_isa isa = dc->config->isa;
407
- unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
408
+ unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
409
+ dc->pc)};
410
unsigned len = xtensa_op0_insn_len(dc, b[0]);
411
xtensa_format fmt;
412
int slot, slots;
413
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
414
415
dc->base.pc_next = dc->pc + len;
416
for (i = 1; i < len; ++i) {
417
- b[i] = translator_ldub(env, dc->pc + i);
418
+ b[i] = translator_ldub(env, &dc->base, dc->pc + i);
419
}
420
xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
421
fmt = xtensa_format_decode(isa, dc->insnbuf);
422
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
423
index XXXXXXX..XXXXXXX 100644
424
--- a/target/mips/tcg/micromips_translate.c.inc
425
+++ b/target/mips/tcg/micromips_translate.c.inc
426
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
427
uint32_t op, minor, minor2, mips32_op;
428
uint32_t cond, fmt, cc;
429
430
- insn = translator_lduw(env, ctx->base.pc_next + 2);
431
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
432
ctx->opcode = (ctx->opcode << 16) | insn;
433
434
rt = (ctx->opcode >> 21) & 0x1f;
435
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
436
index XXXXXXX..XXXXXXX 100644
437
--- a/target/mips/tcg/mips16e_translate.c.inc
438
+++ b/target/mips/tcg/mips16e_translate.c.inc
439
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
440
441
static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
442
{
443
- int extend = translator_lduw(env, ctx->base.pc_next + 2);
444
+ int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
445
int op, rx, ry, funct, sa;
446
int16_t imm, offset;
447
448
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
449
/* No delay slot, so just process as a normal instruction */
450
break;
451
case M16_OPC_JAL:
452
- offset = translator_lduw(env, ctx->base.pc_next + 2);
453
+ offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
454
offset = (((ctx->opcode & 0x1f) << 21)
455
| ((ctx->opcode >> 5) & 0x1f) << 16
456
| offset) << 2;
457
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
458
index XXXXXXX..XXXXXXX 100644
459
--- a/target/mips/tcg/nanomips_translate.c.inc
460
+++ b/target/mips/tcg/nanomips_translate.c.inc
461
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
462
int offset;
463
int imm;
464
465
- insn = translator_lduw(env, ctx->base.pc_next + 2);
466
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
467
ctx->opcode = (ctx->opcode << 16) | insn;
468
469
rt = extract32(ctx->opcode, 21, 5);
470
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
471
break;
472
case NM_P48I:
473
{
474
- insn = translator_lduw(env, ctx->base.pc_next + 4);
475
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
476
target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
477
switch (extract32(ctx->opcode, 16, 5)) {
478
case NM_LI48:
36
--
479
--
37
2.25.1
480
2.25.1
38
481
39
482
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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