On Fri, Jun 11, 2021 at 4:48 PM Anup Patel <anup@brainfault.org> wrote:
>
> Hi Alistair,
>
> On Fri, May 14, 2021 at 8:03 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The advanced interrupt architecture (AIA) extends the per-HART local
> > interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> > and Advanced PLIC (wired interrupt controller).
> >
> > The latest AIA draft specification can be found here:
> > http://jhauser.us/private/RISCV-AIA/riscv-interrupts-021.pdf
> >
> > This series adds initial AIA support in QEMU which includes emulating all
> > AIA local CSR. To enable AIA in QEMU, we just need to pass "x-aia=true"
> > paramenter in "-cpu" QEMU command-line.
> >
> > To test series, we require OpenSBI and Linux with AIA support which
> > can be found in riscv_aia_v1 branch at:
> > https://github.com/avpatel/opensbi.git
> > https://github.com/avpatel/linux.git
> >
> > Anup Patel (4):
> > target/riscv: Add defines for AIA local interrupt CSRs
> > target/riscv: Add CPU feature for AIA CSRs
> > target/riscv: Implement AIA local interrupt CSRs
> > hw/riscv: virt: Use AIA INTC compatible string when available
>
> The ACLINT specification will be frozen soon (probably early next
> month). The ACLINT QEMU support patches are also ready and don't
> depend on the AIA QEMU support patches.
>
> Is it okay to target ACLINT support in QEMU first ?
Yeah, go for it.
Alistair
>
> I can rebase this series on ACLINT support patches and also include
> more AIA emulation patches (APLIC and IMSIC) in the AIA series.
>
> Regards,
> Anup
>
> >
> > hw/riscv/virt.c | 11 +-
> > target/riscv/cpu.c | 32 +-
> > target/riscv/cpu.h | 56 +-
> > target/riscv/cpu_bits.h | 128 +++++
> > target/riscv/cpu_helper.c | 245 ++++++++-
> > target/riscv/csr.c | 1059 +++++++++++++++++++++++++++++++++++--
> > target/riscv/machine.c | 26 +-
> > 7 files changed, 1454 insertions(+), 103 deletions(-)
> >
> > --
> > 2.25.1
> >
>