1 | The following changes since commit 4cc10cae64c51e17844dc4358481c393d7bf1ed4: | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
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2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-05-06 18:56:17 +0100) | 3 | -- PMM |
4 | |||
5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | ||
6 | |||
7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
4 | 8 | ||
5 | are available in the Git repository at: | 9 | are available in the Git repository at: |
6 | 10 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210510 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
8 | 12 | ||
9 | for you to fetch changes up to 8f96812baa53005f32aece3e30b140826c20aa19: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
10 | 14 | ||
11 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 (2021-05-10 13:24:09 +0100) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
12 | 16 | ||
13 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
14 | target-arm queue: | 18 | target-arm queue: |
15 | * docs: fix link in sbsa description | 19 | * Fix KVM SVE ID register probe code |
16 | * linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | ||
17 | * target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | ||
18 | * target/arm: Split neon and vfp translation to their own | ||
19 | compilation units | ||
20 | * target/arm: Make WFI a NOP for userspace emulators | ||
21 | * hw/sd/omap_mmc: Use device_cold_reset() instead of | ||
22 | device_legacy_reset() | ||
23 | * include: More fixes for 'extern "C"' block use | ||
24 | * hw/arm/imx25_pdk: Fix error message for invalid RAM size | ||
25 | * hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
26 | * hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 | ||
27 | 20 | ||
28 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
29 | Alex Bennée (1): | 22 | Richard Henderson (3): |
30 | docs: fix link in sbsa description | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
31 | 26 | ||
32 | Guenter Roeck (1): | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
33 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
34 | |||
35 | Peter Maydell (22): | ||
36 | target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | ||
37 | target/arm: Move constant expanders to translate.h | ||
38 | target/arm: Share unallocated_encoding() and gen_exception_insn() | ||
39 | target/arm: Make functions used by m-nocp global | ||
40 | target/arm: Split m-nocp trans functions into their own file | ||
41 | target/arm: Move gen_aa32 functions to translate-a32.h | ||
42 | target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc | ||
43 | target/arm: Make functions used by translate-vfp global | ||
44 | target/arm: Make translate-vfp.c.inc its own compilation unit | ||
45 | target/arm: Move vfp_reg_ptr() to translate-neon.c.inc | ||
46 | target/arm: Delete unused typedef | ||
47 | target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h | ||
48 | target/arm: Make functions used by translate-neon global | ||
49 | target/arm: Make translate-neon.c.inc its own compilation unit | ||
50 | target/arm: Make WFI a NOP for userspace emulators | ||
51 | hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset() | ||
52 | osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves | ||
53 | include/qemu/bswap.h: Handle being included outside extern "C" block | ||
54 | include/disas/dis-asm.h: Handle being included outside 'extern "C"' | ||
55 | hw/misc/mps2-scc: Add "QEMU interface" comment | ||
56 | hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping | ||
57 | hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
58 | |||
59 | Philippe Mathieu-Daudé (1): | ||
60 | hw/arm/imx25_pdk: Fix error message for invalid RAM size | ||
61 | |||
62 | Richard Henderson (1): | ||
63 | linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | ||
64 | |||
65 | docs/system/arm/mps2.rst | 10 + | ||
66 | docs/system/arm/sbsa.rst | 2 +- | ||
67 | include/disas/dis-asm.h | 12 +- | ||
68 | include/hw/misc/mps2-scc.h | 21 ++ | ||
69 | include/qemu/bswap.h | 26 ++- | ||
70 | include/qemu/osdep.h | 8 +- | ||
71 | include/sysemu/os-posix.h | 8 + | ||
72 | include/sysemu/os-win32.h | 8 + | ||
73 | target/arm/translate-a32.h | 144 +++++++++++++ | ||
74 | target/arm/translate-a64.h | 2 - | ||
75 | target/arm/translate.h | 29 +++ | ||
76 | hw/arm/imx25_pdk.c | 5 +- | ||
77 | hw/arm/mps2-tz.c | 108 +++++++++- | ||
78 | hw/arm/xilinx_zynq.c | 2 +- | ||
79 | hw/misc/mps2-scc.c | 13 +- | ||
80 | hw/sd/omap_mmc.c | 2 +- | ||
81 | linux-user/elfload.c | 13 ++ | ||
82 | target/arm/helper.c | 2 +- | ||
83 | target/arm/op_helper.c | 12 ++ | ||
84 | target/arm/translate-a64.c | 15 -- | ||
85 | target/arm/translate-m-nocp.c | 221 ++++++++++++++++++++ | ||
86 | .../arm/{translate-neon.c.inc => translate-neon.c} | 19 +- | ||
87 | .../arm/{translate-vfp.c.inc => translate-vfp.c} | 230 +++------------------ | ||
88 | target/arm/translate.c | 200 ++++-------------- | ||
89 | disas/arm-a64.cc | 2 - | ||
90 | disas/nanomips.cpp | 2 - | ||
91 | target/arm/meson.build | 15 +- | ||
92 | 27 files changed, 718 insertions(+), 413 deletions(-) | ||
93 | create mode 100644 target/arm/translate-a32.h | ||
94 | create mode 100644 target/arm/translate-m-nocp.c | ||
95 | rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) | ||
96 | rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (94%) | ||
97 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | A trailing _ makes all the difference to the rendered link. | 3 | Indication for support for SVE will not depend on whether we |
4 | perform the query on the main kvm_state or the temp vcpu. | ||
4 | 5 | ||
5 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20210428131316.31390-1-alex.bennee@linaro.org | 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | docs/system/arm/sbsa.rst | 2 +- | 11 | target/arm/kvm64.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 13 | ||
13 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/arm/sbsa.rst | 16 | --- a/target/arm/kvm64.c |
16 | +++ b/docs/system/arm/sbsa.rst | 17 | +++ b/target/arm/kvm64.c |
17 | @@ -XXX,XX +XXX,XX @@ Arm Server Base System Architecture Reference board (``sbsa-ref``) | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
18 | While the `virt` board is a generic board platform that doesn't match | 19 | } |
19 | any real hardware the `sbsa-ref` board intends to look like real | 20 | } |
20 | hardware. The `Server Base System Architecture | 21 | |
21 | -<https://developer.arm.com/documentation/den0029/latest>` defines a | 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; |
22 | +<https://developer.arm.com/documentation/den0029/latest>`_ defines a | 23 | + sve_supported = kvm_arm_sve_supported(); |
23 | minimum base line of hardware support and importantly how the firmware | 24 | |
24 | reports that to any operating system. It is a static system that | 25 | /* Add feature bits that can't appear until after VCPU init. */ |
25 | reports a very minimal DT to the firmware for non-discoverable | 26 | if (sve_supported) { |
26 | -- | 27 | -- |
27 | 2.20.1 | 28 | 2.25.1 |
28 | |||
29 | diff view generated by jsdifflib |
1 | The AN524 FPGA image supports two memory maps, which differ in where | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | the QSPI and BRAM are. In the default map, the BRAM is at | ||
3 | 0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they | ||
4 | are the other way around. | ||
5 | 2 | ||
6 | In hardware, the initial mapping can be selected by the user by | 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 |
7 | writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the | 4 | was always returning zero. This also obviates the adjustment |
8 | board configuration file. The board config file is acted on by the | 5 | of ID_AA64PFR0, which had sanitized the SVE field. |
9 | "Motherboard Configuration Controller", which is an entirely separate | ||
10 | microcontroller on the dev board but outside the FPGA. | ||
11 | 6 | ||
12 | The guest can also dynamically change the mapping via the SCC | 7 | The effects of the bug are not visible, because the only thing that |
13 | CFG_REG0 register. | 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. |
9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
14 | 10 | ||
15 | Implement this functionality for QEMU, using a machine property | 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> |
16 | "remap" with valid values "BRAM" and "QSPI" to allow the user to set | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
17 | the initial mapping, in the same way they can on the FPGA, and | 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org |
18 | wiring up the bit from the SCC register to also switch the mapping. | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
19 | 19 | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
22 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
23 | Message-id: 20210504120912.23094-4-peter.maydell@linaro.org | ||
24 | --- | ||
25 | docs/system/arm/mps2.rst | 10 ++++ | ||
26 | hw/arm/mps2-tz.c | 108 ++++++++++++++++++++++++++++++++++++++- | ||
27 | 2 files changed, 117 insertions(+), 1 deletion(-) | ||
28 | |||
29 | diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst | ||
30 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/docs/system/arm/mps2.rst | 22 | --- a/target/arm/kvm64.c |
32 | +++ b/docs/system/arm/mps2.rst | 23 | +++ b/target/arm/kvm64.c |
33 | @@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware: | 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
34 | flash, but only as simple ROM, so attempting to rewrite the flash | 25 | bool sve_supported; |
35 | from the guest will fail | 26 | bool pmu_supported = false; |
36 | - QEMU does not model the USB controller in MPS3 boards | 27 | uint64_t features = 0; |
37 | + | 28 | - uint64_t t; |
38 | +Machine-specific options | 29 | int err; |
39 | +"""""""""""""""""""""""" | 30 | |
40 | + | 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however |
41 | +The following machine-specific options are supported: | 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
42 | + | 33 | struct kvm_vcpu_init init = { .target = -1, }; |
43 | +remap | 34 | |
44 | + Supported for ``mps3-an524`` only. | 35 | /* |
45 | + Set ``BRAM``/``QSPI`` to select the initial memory mapping. The | 36 | - * Ask for Pointer Authentication if supported. We can't play the |
46 | + default is ``BRAM``. | 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us |
47 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 38 | - * whether we have the architected or IMPDEF version of PAuth, so |
48 | index XXXXXXX..XXXXXXX 100644 | 39 | - * we have to use the actual ID regs. |
49 | --- a/hw/arm/mps2-tz.c | 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, |
50 | +++ b/hw/arm/mps2-tz.c | 41 | + * which is otherwise RAZ. |
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | #include "hw/boards.h" | ||
53 | #include "exec/address-spaces.h" | ||
54 | #include "sysemu/sysemu.h" | ||
55 | +#include "sysemu/reset.h" | ||
56 | #include "hw/misc/unimp.h" | ||
57 | #include "hw/char/cmsdk-apb-uart.h" | ||
58 | #include "hw/timer/cmsdk-apb-timer.h" | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | #include "hw/core/split-irq.h" | ||
61 | #include "hw/qdev-clock.h" | ||
62 | #include "qom/object.h" | ||
63 | +#include "hw/irq.h" | ||
64 | |||
65 | #define MPS2TZ_NUMIRQ_MAX 96 | ||
66 | #define MPS2TZ_RAM_MAX 5 | ||
67 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { | ||
68 | SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; | ||
69 | Clock *sysclk; | ||
70 | Clock *s32kclk; | ||
71 | + | ||
72 | + bool remap; | ||
73 | + qemu_irq remap_irq; | ||
74 | }; | ||
75 | |||
76 | #define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
77 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an505_raminfo[] = { { | ||
78 | }, | ||
79 | }; | ||
80 | |||
81 | +/* | ||
82 | + * Note that the addresses and MPC numbering here should match up | ||
83 | + * with those used in remap_memory(), which can swap the BRAM and QSPI. | ||
84 | + */ | ||
85 | static const RAMInfo an524_raminfo[] = { { | ||
86 | .name = "bram", | ||
87 | .base = 0x00000000, | ||
88 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
89 | |||
90 | object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); | ||
91 | sccdev = DEVICE(scc); | ||
92 | + qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); | ||
93 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
94 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); | ||
95 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
96 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, | ||
97 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); | ||
98 | } | ||
99 | |||
100 | +static hwaddr boot_mem_base(MPS2TZMachineState *mms) | ||
101 | +{ | ||
102 | + /* | ||
103 | + * Return the canonical address of the block which will be mapped | ||
104 | + * at address 0x0 (i.e. where the vector table is). | ||
105 | + * This is usually 0, but if the AN524 alternate memory map is | ||
106 | + * enabled it will be the base address of the QSPI block. | ||
107 | + */ | 42 | + */ |
108 | + return mms->remap ? 0x28000000 : 0; | 43 | + sve_supported = kvm_arm_sve_supported(); |
109 | +} | 44 | + if (sve_supported) { |
110 | + | 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; |
111 | +static void remap_memory(MPS2TZMachineState *mms, int map) | ||
112 | +{ | ||
113 | + /* | ||
114 | + * Remap the memory for the AN524. 'map' is the value of | ||
115 | + * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 | ||
116 | + * for the "option 1" mapping where QSPI is at address 0. | ||
117 | + * | ||
118 | + * Effectively we need to swap around the "upstream" ends of | ||
119 | + * MPC 0 and MPC 1. | ||
120 | + */ | ||
121 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
122 | + int i; | ||
123 | + | ||
124 | + if (mmc->fpga_type != FPGA_AN524) { | ||
125 | + return; | ||
126 | + } | 46 | + } |
127 | + | 47 | + |
128 | + memory_region_transaction_begin(); | 48 | + /* |
129 | + for (i = 0; i < 2; i++) { | 49 | + * Ask for Pointer Authentication if supported, so that we get |
130 | + TZMPC *mpc = &mms->mpc[i]; | 50 | + * the unsanitized field values for AA64ISAR1_EL1. |
131 | + MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); | 51 | */ |
132 | + hwaddr addr = (i ^ map) ? 0x28000000 : 0; | 52 | if (kvm_arm_pauth_supported()) { |
133 | + | 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | |
134 | + memory_region_set_address(upstream, addr); | 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
135 | + } | ||
136 | + memory_region_transaction_commit(); | ||
137 | +} | ||
138 | + | ||
139 | +static void remap_irq_fn(void *opaque, int n, int level) | ||
140 | +{ | ||
141 | + MPS2TZMachineState *mms = opaque; | ||
142 | + | ||
143 | + remap_memory(mms, level); | ||
144 | +} | ||
145 | + | ||
146 | static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, | ||
147 | const char *name, hwaddr size, | ||
148 | const int *irqs) | ||
149 | @@ -XXX,XX +XXX,XX @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) | ||
150 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
151 | |||
152 | for (p = mmc->raminfo; p->name; p++) { | ||
153 | - if (p->base == 0) { | ||
154 | + if (p->base == boot_mem_base(mms)) { | ||
155 | return p->size; | ||
156 | } | 55 | } |
157 | } | 56 | } |
158 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | 57 | |
159 | 58 | - sve_supported = kvm_arm_sve_supported(); | |
160 | create_non_mpc_ram(mms); | 59 | - |
161 | 60 | - /* Add feature bits that can't appear until after VCPU init. */ | |
162 | + if (mmc->fpga_type == FPGA_AN524) { | 61 | if (sve_supported) { |
163 | + /* | 62 | - t = ahcf->isar.id_aa64pfr0; |
164 | + * Connect the line from the SCC so that we can remap when the | 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
165 | + * guest updates that register. | 64 | - ahcf->isar.id_aa64pfr0 = t; |
166 | + */ | 65 | - |
167 | + mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); | 66 | /* |
168 | + qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, | 67 | * There is a range of kernels between kernel commit 73433762fcae |
169 | + mms->remap_irq); | 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
170 | + } | 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
171 | + | 70 | - * SVE support, so we only read it here, rather than together with all |
172 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, | 71 | - * the other ID registers earlier. |
173 | boot_ram_size(mms)); | 72 | + * SVE support, which resulted in an error rather than RAZ. |
174 | } | 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. |
175 | @@ -XXX,XX +XXX,XX @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, | 74 | */ |
176 | *iregion = region; | 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
177 | } | 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); |
178 | |||
179 | +static char *mps2_get_remap(Object *obj, Error **errp) | ||
180 | +{ | ||
181 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); | ||
182 | + const char *val = mms->remap ? "QSPI" : "BRAM"; | ||
183 | + return g_strdup(val); | ||
184 | +} | ||
185 | + | ||
186 | +static void mps2_set_remap(Object *obj, const char *value, Error **errp) | ||
187 | +{ | ||
188 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); | ||
189 | + | ||
190 | + if (!strcmp(value, "BRAM")) { | ||
191 | + mms->remap = false; | ||
192 | + } else if (!strcmp(value, "QSPI")) { | ||
193 | + mms->remap = true; | ||
194 | + } else { | ||
195 | + error_setg(errp, "Invalid remap value"); | ||
196 | + error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); | ||
197 | + } | ||
198 | +} | ||
199 | + | ||
200 | +static void mps2_machine_reset(MachineState *machine) | ||
201 | +{ | ||
202 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
203 | + | ||
204 | + /* | ||
205 | + * Set the initial memory mapping before triggering the reset of | ||
206 | + * the rest of the system, so that the guest image loader and CPU | ||
207 | + * reset see the correct mapping. | ||
208 | + */ | ||
209 | + remap_memory(mms, mms->remap); | ||
210 | + qemu_devices_reset(); | ||
211 | +} | ||
212 | + | ||
213 | static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
214 | { | ||
215 | MachineClass *mc = MACHINE_CLASS(oc); | ||
216 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
217 | |||
218 | mc->init = mps2tz_common_init; | ||
219 | + mc->reset = mps2_machine_reset; | ||
220 | iic->check = mps2_tz_idau_check; | ||
221 | } | ||
222 | |||
223 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) | ||
224 | mmc->raminfo = an524_raminfo; | ||
225 | mmc->armsse_type = TYPE_SSE200; | ||
226 | mps2tz_set_default_ram_info(mmc); | ||
227 | + | ||
228 | + object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); | ||
229 | + object_class_property_set_description(oc, "remap", | ||
230 | + "Set memory mapping. Valid values " | ||
231 | + "are BRAM (default) and QSPI."); | ||
232 | } | ||
233 | |||
234 | static void mps3tz_an547_class_init(ObjectClass *oc, void *data) | ||
235 | -- | 77 | -- |
236 | 2.20.1 | 78 | 2.25.1 |
237 | |||
238 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These three features are already enabled by TCG, but are missing | 3 | The test for the IF block indicates no ID registers are exposed, much |
4 | their hwcap bits. Update HWCAP2 from linux v5.12. | 4 | less host support for SVE. Move the SVE probe into the ELSE block. |
5 | 5 | ||
6 | Cc: qemu-stable@nongnu.org (for 6.0.1) | ||
7 | Buglink: https://bugs.launchpad.net/bugs/1926044 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210427214108.88503-1-richard.henderson@linaro.org | 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | linux-user/elfload.c | 13 +++++++++++++ | 11 | target/arm/kvm64.c | 22 +++++++++++----------- |
13 | 1 file changed, 13 insertions(+) | 12 | 1 file changed, 11 insertions(+), 11 deletions(-) |
14 | 13 | ||
15 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/linux-user/elfload.c | 16 | --- a/target/arm/kvm64.c |
18 | +++ b/linux-user/elfload.c | 17 | +++ b/target/arm/kvm64.c |
19 | @@ -XXX,XX +XXX,XX @@ enum { | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
20 | ARM_HWCAP2_A64_SVESM4 = 1 << 6, | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, |
21 | ARM_HWCAP2_A64_FLAGM2 = 1 << 7, | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
22 | ARM_HWCAP2_A64_FRINT = 1 << 8, | 21 | } |
23 | + ARM_HWCAP2_A64_SVEI8MM = 1 << 9, | 22 | - } |
24 | + ARM_HWCAP2_A64_SVEF32MM = 1 << 10, | 23 | |
25 | + ARM_HWCAP2_A64_SVEF64MM = 1 << 11, | 24 | - if (sve_supported) { |
26 | + ARM_HWCAP2_A64_SVEBF16 = 1 << 12, | 25 | - /* |
27 | + ARM_HWCAP2_A64_I8MM = 1 << 13, | 26 | - * There is a range of kernels between kernel commit 73433762fcae |
28 | + ARM_HWCAP2_A64_BF16 = 1 << 14, | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
29 | + ARM_HWCAP2_A64_DGH = 1 << 15, | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
30 | + ARM_HWCAP2_A64_RNG = 1 << 16, | 29 | - * SVE support, which resulted in an error rather than RAZ. |
31 | + ARM_HWCAP2_A64_BTI = 1 << 17, | 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. |
32 | + ARM_HWCAP2_A64_MTE = 1 << 18, | 31 | - */ |
33 | }; | 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
34 | 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | |
35 | #define ELF_HWCAP get_elf_hwcap() | 34 | + if (sve_supported) { |
36 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void) | 35 | + /* |
37 | GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); | 36 | + * There is a range of kernels between kernel commit 73433762fcae |
38 | GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); | 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't |
39 | GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); | 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has |
40 | + GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); | 39 | + * enabled SVE support, which resulted in an error rather than RAZ. |
41 | + GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); | 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. |
42 | + GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); | 41 | + */ |
43 | 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | |
44 | return hwcaps; | 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); |
45 | } | 44 | + } |
45 | } | ||
46 | |||
47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
46 | -- | 48 | -- |
47 | 2.20.1 | 49 | 2.25.1 |
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In tlbi_aa64_vae2is_write() the calculation | ||
2 | bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, | ||
3 | pageaddr) | ||
4 | 1 | ||
5 | has the two arms of the ?: expression reversed. Fix the bug. | ||
6 | |||
7 | Fixes: b6ad6062f1e5 | ||
8 | Reported-by: Rebecca Cran <rebecca@nuviainc.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
12 | Reviewed-by: Rebecca Cran <rebecca@nuviainc.com> | ||
13 | Message-id: 20210420123106.10861-1-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/arm/helper.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper.c | ||
21 | +++ b/target/arm/helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
23 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | ||
24 | bool secure = arm_is_secure_below_el3(env); | ||
25 | int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; | ||
26 | - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, | ||
27 | + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, | ||
28 | pageaddr); | ||
29 | |||
30 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); | ||
31 | -- | ||
32 | 2.20.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Some of the constant expanders defined in translate.c are generically | ||
2 | useful and will be used by the separate C files for VFP and Neon once | ||
3 | they are created; move the expander definitions to translate.h. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210430132740.10391-2-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate.h | 24 ++++++++++++++++++++++++ | ||
11 | target/arm/translate.c | 24 ------------------------ | ||
12 | 2 files changed, 24 insertions(+), 24 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.h | ||
17 | +++ b/target/arm/translate.h | ||
18 | @@ -XXX,XX +XXX,XX @@ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; | ||
19 | extern TCGv_i64 cpu_exclusive_addr; | ||
20 | extern TCGv_i64 cpu_exclusive_val; | ||
21 | |||
22 | +/* | ||
23 | + * Constant expanders for the decoders. | ||
24 | + */ | ||
25 | + | ||
26 | +static inline int negate(DisasContext *s, int x) | ||
27 | +{ | ||
28 | + return -x; | ||
29 | +} | ||
30 | + | ||
31 | +static inline int plus_2(DisasContext *s, int x) | ||
32 | +{ | ||
33 | + return x + 2; | ||
34 | +} | ||
35 | + | ||
36 | +static inline int times_2(DisasContext *s, int x) | ||
37 | +{ | ||
38 | + return x * 2; | ||
39 | +} | ||
40 | + | ||
41 | +static inline int times_4(DisasContext *s, int x) | ||
42 | +{ | ||
43 | + return x * 4; | ||
44 | +} | ||
45 | + | ||
46 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
47 | { | ||
48 | return (dc->features & (1ULL << feature)) != 0; | ||
49 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/translate.c | ||
52 | +++ b/target/arm/translate.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s) | ||
54 | } | ||
55 | } | ||
56 | |||
57 | -/* | ||
58 | - * Constant expanders for the decoders. | ||
59 | - */ | ||
60 | - | ||
61 | -static int negate(DisasContext *s, int x) | ||
62 | -{ | ||
63 | - return -x; | ||
64 | -} | ||
65 | - | ||
66 | -static int plus_2(DisasContext *s, int x) | ||
67 | -{ | ||
68 | - return x + 2; | ||
69 | -} | ||
70 | - | ||
71 | -static int times_2(DisasContext *s, int x) | ||
72 | -{ | ||
73 | - return x * 2; | ||
74 | -} | ||
75 | - | ||
76 | -static int times_4(DisasContext *s, int x) | ||
77 | -{ | ||
78 | - return x * 4; | ||
79 | -} | ||
80 | - | ||
81 | /* Flags for the disas_set_da_iss info argument: | ||
82 | * lower bits hold the Rt register number, higher bits are flags. | ||
83 | */ | ||
84 | -- | ||
85 | 2.20.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The unallocated_encoding() function is the same in both | ||
2 | translate-a64.c and translate.c; make the translate.c function global | ||
3 | and drop the translate-a64.c version. To do this we need to also | ||
4 | share gen_exception_insn(), which currently exists in two slightly | ||
5 | different versions for A32 and A64: merge those into a single | ||
6 | function that can work for both. | ||
7 | 1 | ||
8 | This will be useful for splitting up translate.c, which will require | ||
9 | unallocated_encoding() to no longer be file-local. It's also | ||
10 | hopefully less confusing to have only one version of the function | ||
11 | rather than two. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20210430132740.10391-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/arm/translate-a64.h | 2 -- | ||
18 | target/arm/translate.h | 3 +++ | ||
19 | target/arm/translate-a64.c | 15 --------------- | ||
20 | target/arm/translate.c | 14 +++++++++----- | ||
21 | 4 files changed, 12 insertions(+), 22 deletions(-) | ||
22 | |||
23 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/translate-a64.h | ||
26 | +++ b/target/arm/translate-a64.h | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | #ifndef TARGET_ARM_TRANSLATE_A64_H | ||
29 | #define TARGET_ARM_TRANSLATE_A64_H | ||
30 | |||
31 | -void unallocated_encoding(DisasContext *s); | ||
32 | - | ||
33 | #define unsupported_encoding(s, insn) \ | ||
34 | do { \ | ||
35 | qemu_log_mask(LOG_UNIMP, \ | ||
36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/translate.h | ||
39 | +++ b/target/arm/translate.h | ||
40 | @@ -XXX,XX +XXX,XX @@ void arm_free_cc(DisasCompare *cmp); | ||
41 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); | ||
42 | void arm_gen_test_cc(int cc, TCGLabel *label); | ||
43 | MemOp pow2_align(unsigned i); | ||
44 | +void unallocated_encoding(DisasContext *s); | ||
45 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
46 | + uint32_t syn, uint32_t target_el); | ||
47 | |||
48 | /* Return state of Alternate Half-precision flag, caller frees result */ | ||
49 | static inline TCGv_i32 get_ahp_flag(void) | ||
50 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/translate-a64.c | ||
53 | +++ b/target/arm/translate-a64.c | ||
54 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) | ||
55 | s->base.is_jmp = DISAS_NORETURN; | ||
56 | } | ||
57 | |||
58 | -static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
59 | - uint32_t syndrome, uint32_t target_el) | ||
60 | -{ | ||
61 | - gen_a64_set_pc_im(pc); | ||
62 | - gen_exception(excp, syndrome, target_el); | ||
63 | - s->base.is_jmp = DISAS_NORETURN; | ||
64 | -} | ||
65 | - | ||
66 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) | ||
67 | { | ||
68 | TCGv_i32 tcg_syn; | ||
69 | @@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | ||
70 | } | ||
71 | } | ||
72 | |||
73 | -void unallocated_encoding(DisasContext *s) | ||
74 | -{ | ||
75 | - /* Unallocated and reserved encodings are uncategorized */ | ||
76 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
77 | - default_exception_el(s)); | ||
78 | -} | ||
79 | - | ||
80 | static void init_tmp_a64_array(DisasContext *s) | ||
81 | { | ||
82 | #ifdef CONFIG_DEBUG_TCG | ||
83 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/translate.c | ||
86 | +++ b/target/arm/translate.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | ||
88 | s->base.is_jmp = DISAS_NORETURN; | ||
89 | } | ||
90 | |||
91 | -static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp, | ||
92 | - int syn, uint32_t target_el) | ||
93 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
94 | + uint32_t syn, uint32_t target_el) | ||
95 | { | ||
96 | - gen_set_condexec(s); | ||
97 | - gen_set_pc_im(s, pc); | ||
98 | + if (s->aarch64) { | ||
99 | + gen_a64_set_pc_im(pc); | ||
100 | + } else { | ||
101 | + gen_set_condexec(s); | ||
102 | + gen_set_pc_im(s, pc); | ||
103 | + } | ||
104 | gen_exception(excp, syn, target_el); | ||
105 | s->base.is_jmp = DISAS_NORETURN; | ||
106 | } | ||
107 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
108 | s->base.is_jmp = DISAS_NORETURN; | ||
109 | } | ||
110 | |||
111 | -static void unallocated_encoding(DisasContext *s) | ||
112 | +void unallocated_encoding(DisasContext *s) | ||
113 | { | ||
114 | /* Unallocated and reserved encodings are uncategorized */ | ||
115 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
116 | -- | ||
117 | 2.20.1 | ||
118 | |||
119 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | We want to split out the .c.inc files which are currently included | ||
2 | into translate.c so they are separate compilation units. To do this | ||
3 | we need to make some functions which are currently file-local to | ||
4 | translate.c have global scope; create a translate-a32.h paralleling | ||
5 | the existing translate-a64.h as a place for these declarations to | ||
6 | live, so that code moved into the new compilation units can call | ||
7 | them. | ||
8 | 1 | ||
9 | The functions made global here are those required by the | ||
10 | m-nocp.decode functions, except that I have converted the whole | ||
11 | family of {read,write}_neon_element* and also both the load_cpu and | ||
12 | store_cpu functions for consistency, even though m-nocp only wants a | ||
13 | few functions from each. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20210430132740.10391-4-peter.maydell@linaro.org | ||
18 | --- | ||
19 | target/arm/translate-a32.h | 57 ++++++++++++++++++++++++++++++++++ | ||
20 | target/arm/translate.c | 39 +++++------------------ | ||
21 | target/arm/translate-vfp.c.inc | 2 +- | ||
22 | 3 files changed, 65 insertions(+), 33 deletions(-) | ||
23 | create mode 100644 target/arm/translate-a32.h | ||
24 | |||
25 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
26 | new file mode 100644 | ||
27 | index XXXXXXX..XXXXXXX | ||
28 | --- /dev/null | ||
29 | +++ b/target/arm/translate-a32.h | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | +/* | ||
32 | + * AArch32 translation, common definitions. | ||
33 | + * | ||
34 | + * Copyright (c) 2021 Linaro, Ltd. | ||
35 | + * | ||
36 | + * This library is free software; you can redistribute it and/or | ||
37 | + * modify it under the terms of the GNU Lesser General Public | ||
38 | + * License as published by the Free Software Foundation; either | ||
39 | + * version 2.1 of the License, or (at your option) any later version. | ||
40 | + * | ||
41 | + * This library is distributed in the hope that it will be useful, | ||
42 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
43 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
44 | + * Lesser General Public License for more details. | ||
45 | + * | ||
46 | + * You should have received a copy of the GNU Lesser General Public | ||
47 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
48 | + */ | ||
49 | + | ||
50 | +#ifndef TARGET_ARM_TRANSLATE_A64_H | ||
51 | +#define TARGET_ARM_TRANSLATE_A64_H | ||
52 | + | ||
53 | +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | ||
54 | +void arm_gen_condlabel(DisasContext *s); | ||
55 | +bool vfp_access_check(DisasContext *s); | ||
56 | +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); | ||
57 | +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); | ||
58 | +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); | ||
59 | +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); | ||
60 | + | ||
61 | +static inline TCGv_i32 load_cpu_offset(int offset) | ||
62 | +{ | ||
63 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
64 | + tcg_gen_ld_i32(tmp, cpu_env, offset); | ||
65 | + return tmp; | ||
66 | +} | ||
67 | + | ||
68 | +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) | ||
69 | + | ||
70 | +static inline void store_cpu_offset(TCGv_i32 var, int offset) | ||
71 | +{ | ||
72 | + tcg_gen_st_i32(var, cpu_env, offset); | ||
73 | + tcg_temp_free_i32(var); | ||
74 | +} | ||
75 | + | ||
76 | +#define store_cpu_field(var, name) \ | ||
77 | + store_cpu_offset(var, offsetof(CPUARMState, name)) | ||
78 | + | ||
79 | +/* Create a new temporary and set it to the value of a CPU register. */ | ||
80 | +static inline TCGv_i32 load_reg(DisasContext *s, int reg) | ||
81 | +{ | ||
82 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
83 | + load_reg_var(s, tmp, reg); | ||
84 | + return tmp; | ||
85 | +} | ||
86 | + | ||
87 | +#endif | ||
88 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/arm/translate.c | ||
91 | +++ b/target/arm/translate.c | ||
92 | @@ -XXX,XX +XXX,XX @@ | ||
93 | #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) | ||
94 | |||
95 | #include "translate.h" | ||
96 | +#include "translate-a32.h" | ||
97 | |||
98 | #if defined(CONFIG_USER_ONLY) | ||
99 | #define IS_USER(s) 1 | ||
100 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
101 | } | ||
102 | |||
103 | /* Generate a label used for skipping this instruction */ | ||
104 | -static void arm_gen_condlabel(DisasContext *s) | ||
105 | +void arm_gen_condlabel(DisasContext *s) | ||
106 | { | ||
107 | if (!s->condjmp) { | ||
108 | s->condlabel = gen_new_label(); | ||
109 | @@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s) | ||
110 | } | ||
111 | } | ||
112 | |||
113 | -static inline TCGv_i32 load_cpu_offset(int offset) | ||
114 | -{ | ||
115 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
116 | - tcg_gen_ld_i32(tmp, cpu_env, offset); | ||
117 | - return tmp; | ||
118 | -} | ||
119 | - | ||
120 | -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) | ||
121 | - | ||
122 | -static inline void store_cpu_offset(TCGv_i32 var, int offset) | ||
123 | -{ | ||
124 | - tcg_gen_st_i32(var, cpu_env, offset); | ||
125 | - tcg_temp_free_i32(var); | ||
126 | -} | ||
127 | - | ||
128 | -#define store_cpu_field(var, name) \ | ||
129 | - store_cpu_offset(var, offsetof(CPUARMState, name)) | ||
130 | - | ||
131 | /* The architectural value of PC. */ | ||
132 | static uint32_t read_pc(DisasContext *s) | ||
133 | { | ||
134 | @@ -XXX,XX +XXX,XX @@ static uint32_t read_pc(DisasContext *s) | ||
135 | } | ||
136 | |||
137 | /* Set a variable to the value of a CPU register. */ | ||
138 | -static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
139 | +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
140 | { | ||
141 | if (reg == 15) { | ||
142 | tcg_gen_movi_i32(var, read_pc(s)); | ||
143 | @@ -XXX,XX +XXX,XX @@ static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
144 | } | ||
145 | } | ||
146 | |||
147 | -/* Create a new temporary and set it to the value of a CPU register. */ | ||
148 | -static inline TCGv_i32 load_reg(DisasContext *s, int reg) | ||
149 | -{ | ||
150 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
151 | - load_reg_var(s, tmp, reg); | ||
152 | - return tmp; | ||
153 | -} | ||
154 | - | ||
155 | /* | ||
156 | * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4). | ||
157 | * This is used for load/store for which use of PC implies (literal), | ||
158 | @@ -XXX,XX +XXX,XX @@ static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
159 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
160 | } | ||
161 | |||
162 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
163 | +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
164 | { | ||
165 | long off = neon_element_offset(reg, ele, memop); | ||
166 | |||
167 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
168 | } | ||
169 | } | ||
170 | |||
171 | -static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
172 | +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
173 | { | ||
174 | long off = neon_element_offset(reg, ele, memop); | ||
175 | |||
176 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
177 | } | ||
178 | } | ||
179 | |||
180 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
181 | +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
182 | { | ||
183 | long off = neon_element_offset(reg, ele, memop); | ||
184 | |||
185 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
186 | } | ||
187 | } | ||
188 | |||
189 | -static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
190 | +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
191 | { | ||
192 | long off = neon_element_offset(reg, ele, memop); | ||
193 | |||
194 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/target/arm/translate-vfp.c.inc | ||
197 | +++ b/target/arm/translate-vfp.c.inc | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
199 | * The most usual kind of VFP access check, for everything except | ||
200 | * FMXR/FMRX to the always-available special registers. | ||
201 | */ | ||
202 | -static bool vfp_access_check(DisasContext *s) | ||
203 | +bool vfp_access_check(DisasContext *s) | ||
204 | { | ||
205 | return full_vfp_access_check(s, false); | ||
206 | } | ||
207 | -- | ||
208 | 2.20.1 | ||
209 | |||
210 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Currently the trans functions for m-nocp.decode all live in | ||
2 | translate-vfp.inc.c; move them out into their own translation unit, | ||
3 | translate-m-nocp.c. | ||
4 | 1 | ||
5 | The trans_* functions here are pure code motion with no changes. | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210430132740.10391-5-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/translate-a32.h | 3 + | ||
12 | target/arm/translate-m-nocp.c | 221 +++++++++++++++++++++++++++++++++ | ||
13 | target/arm/translate.c | 1 - | ||
14 | target/arm/translate-vfp.c.inc | 196 ----------------------------- | ||
15 | target/arm/meson.build | 3 +- | ||
16 | 5 files changed, 226 insertions(+), 198 deletions(-) | ||
17 | create mode 100644 target/arm/translate-m-nocp.c | ||
18 | |||
19 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/translate-a32.h | ||
22 | +++ b/target/arm/translate-a32.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | #ifndef TARGET_ARM_TRANSLATE_A64_H | ||
25 | #define TARGET_ARM_TRANSLATE_A64_H | ||
26 | |||
27 | +/* Prototypes for autogenerated disassembler functions */ | ||
28 | +bool disas_m_nocp(DisasContext *dc, uint32_t insn); | ||
29 | + | ||
30 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | ||
31 | void arm_gen_condlabel(DisasContext *s); | ||
32 | bool vfp_access_check(DisasContext *s); | ||
33 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
34 | new file mode 100644 | ||
35 | index XXXXXXX..XXXXXXX | ||
36 | --- /dev/null | ||
37 | +++ b/target/arm/translate-m-nocp.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | +/* | ||
40 | + * ARM translation: M-profile NOCP special-case instructions | ||
41 | + * | ||
42 | + * Copyright (c) 2020 Linaro, Ltd. | ||
43 | + * | ||
44 | + * This library is free software; you can redistribute it and/or | ||
45 | + * modify it under the terms of the GNU Lesser General Public | ||
46 | + * License as published by the Free Software Foundation; either | ||
47 | + * version 2.1 of the License, or (at your option) any later version. | ||
48 | + * | ||
49 | + * This library is distributed in the hope that it will be useful, | ||
50 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
51 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
52 | + * Lesser General Public License for more details. | ||
53 | + * | ||
54 | + * You should have received a copy of the GNU Lesser General Public | ||
55 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
56 | + */ | ||
57 | + | ||
58 | +#include "qemu/osdep.h" | ||
59 | +#include "tcg/tcg-op.h" | ||
60 | +#include "translate.h" | ||
61 | +#include "translate-a32.h" | ||
62 | + | ||
63 | +#include "decode-m-nocp.c.inc" | ||
64 | + | ||
65 | +/* | ||
66 | + * Decode VLLDM and VLSTM are nonstandard because: | ||
67 | + * * if there is no FPU then these insns must NOP in | ||
68 | + * Secure state and UNDEF in Nonsecure state | ||
69 | + * * if there is an FPU then these insns do not have | ||
70 | + * the usual behaviour that vfp_access_check() provides of | ||
71 | + * being controlled by CPACR/NSACR enable bits or the | ||
72 | + * lazy-stacking logic. | ||
73 | + */ | ||
74 | +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | ||
75 | +{ | ||
76 | + TCGv_i32 fptr; | ||
77 | + | ||
78 | + if (!arm_dc_feature(s, ARM_FEATURE_M) || | ||
79 | + !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
80 | + return false; | ||
81 | + } | ||
82 | + | ||
83 | + if (a->op) { | ||
84 | + /* | ||
85 | + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not | ||
86 | + * to take the IMPDEF option to make memory accesses to the stack | ||
87 | + * slots that correspond to the D16-D31 registers (discarding | ||
88 | + * read data and writing UNKNOWN values), so for us the T2 | ||
89 | + * encoding behaves identically to the T1 encoding. | ||
90 | + */ | ||
91 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
92 | + return false; | ||
93 | + } | ||
94 | + } else { | ||
95 | + /* | ||
96 | + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. | ||
97 | + * This is currently architecturally impossible, but we add the | ||
98 | + * check to stay in line with the pseudocode. Note that we must | ||
99 | + * emit code for the UNDEF so it takes precedence over the NOCP. | ||
100 | + */ | ||
101 | + if (dc_isar_feature(aa32_simd_r32, s)) { | ||
102 | + unallocated_encoding(s); | ||
103 | + return true; | ||
104 | + } | ||
105 | + } | ||
106 | + | ||
107 | + /* | ||
108 | + * If not secure, UNDEF. We must emit code for this | ||
109 | + * rather than returning false so that this takes | ||
110 | + * precedence over the m-nocp.decode NOCP fallback. | ||
111 | + */ | ||
112 | + if (!s->v8m_secure) { | ||
113 | + unallocated_encoding(s); | ||
114 | + return true; | ||
115 | + } | ||
116 | + /* If no fpu, NOP. */ | ||
117 | + if (!dc_isar_feature(aa32_vfp, s)) { | ||
118 | + return true; | ||
119 | + } | ||
120 | + | ||
121 | + fptr = load_reg(s, a->rn); | ||
122 | + if (a->l) { | ||
123 | + gen_helper_v7m_vlldm(cpu_env, fptr); | ||
124 | + } else { | ||
125 | + gen_helper_v7m_vlstm(cpu_env, fptr); | ||
126 | + } | ||
127 | + tcg_temp_free_i32(fptr); | ||
128 | + | ||
129 | + /* End the TB, because we have updated FP control bits */ | ||
130 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
131 | + return true; | ||
132 | +} | ||
133 | + | ||
134 | +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
135 | +{ | ||
136 | + int btmreg, topreg; | ||
137 | + TCGv_i64 zero; | ||
138 | + TCGv_i32 aspen, sfpa; | ||
139 | + | ||
140 | + if (!dc_isar_feature(aa32_m_sec_state, s)) { | ||
141 | + /* Before v8.1M, fall through in decode to NOCP check */ | ||
142 | + return false; | ||
143 | + } | ||
144 | + | ||
145 | + /* Explicitly UNDEF because this takes precedence over NOCP */ | ||
146 | + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return true; | ||
149 | + } | ||
150 | + | ||
151 | + if (!dc_isar_feature(aa32_vfp_simd, s)) { | ||
152 | + /* NOP if we have neither FP nor MVE */ | ||
153 | + return true; | ||
154 | + } | ||
155 | + | ||
156 | + /* | ||
157 | + * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no | ||
158 | + * active floating point context so we must NOP (without doing | ||
159 | + * any lazy state preservation or the NOCP check). | ||
160 | + */ | ||
161 | + aspen = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
162 | + sfpa = load_cpu_field(v7m.control[M_REG_S]); | ||
163 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
164 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
165 | + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); | ||
166 | + tcg_gen_or_i32(sfpa, sfpa, aspen); | ||
167 | + arm_gen_condlabel(s); | ||
168 | + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
169 | + | ||
170 | + if (s->fp_excp_el != 0) { | ||
171 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
172 | + syn_uncategorized(), s->fp_excp_el); | ||
173 | + return true; | ||
174 | + } | ||
175 | + | ||
176 | + topreg = a->vd + a->imm - 1; | ||
177 | + btmreg = a->vd; | ||
178 | + | ||
179 | + /* Convert to Sreg numbers if the insn specified in Dregs */ | ||
180 | + if (a->size == 3) { | ||
181 | + topreg = topreg * 2 + 1; | ||
182 | + btmreg *= 2; | ||
183 | + } | ||
184 | + | ||
185 | + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { | ||
186 | + /* UNPREDICTABLE: we choose to undef */ | ||
187 | + unallocated_encoding(s); | ||
188 | + return true; | ||
189 | + } | ||
190 | + | ||
191 | + /* Silently ignore requests to clear D16-D31 if they don't exist */ | ||
192 | + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { | ||
193 | + topreg = 31; | ||
194 | + } | ||
195 | + | ||
196 | + if (!vfp_access_check(s)) { | ||
197 | + return true; | ||
198 | + } | ||
199 | + | ||
200 | + /* Zero the Sregs from btmreg to topreg inclusive. */ | ||
201 | + zero = tcg_const_i64(0); | ||
202 | + if (btmreg & 1) { | ||
203 | + write_neon_element64(zero, btmreg >> 1, 1, MO_32); | ||
204 | + btmreg++; | ||
205 | + } | ||
206 | + for (; btmreg + 1 <= topreg; btmreg += 2) { | ||
207 | + write_neon_element64(zero, btmreg >> 1, 0, MO_64); | ||
208 | + } | ||
209 | + if (btmreg == topreg) { | ||
210 | + write_neon_element64(zero, btmreg >> 1, 0, MO_32); | ||
211 | + btmreg++; | ||
212 | + } | ||
213 | + assert(btmreg == topreg + 1); | ||
214 | + /* TODO: when MVE is implemented, zero VPR here */ | ||
215 | + return true; | ||
216 | +} | ||
217 | + | ||
218 | +static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
219 | +{ | ||
220 | + /* | ||
221 | + * Handle M-profile early check for disabled coprocessor: | ||
222 | + * all we need to do here is emit the NOCP exception if | ||
223 | + * the coprocessor is disabled. Otherwise we return false | ||
224 | + * and the real VFP/etc decode will handle the insn. | ||
225 | + */ | ||
226 | + assert(arm_dc_feature(s, ARM_FEATURE_M)); | ||
227 | + | ||
228 | + if (a->cp == 11) { | ||
229 | + a->cp = 10; | ||
230 | + } | ||
231 | + if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && | ||
232 | + (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { | ||
233 | + /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ | ||
234 | + a->cp = 10; | ||
235 | + } | ||
236 | + | ||
237 | + if (a->cp != 10) { | ||
238 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
239 | + syn_uncategorized(), default_exception_el(s)); | ||
240 | + return true; | ||
241 | + } | ||
242 | + | ||
243 | + if (s->fp_excp_el != 0) { | ||
244 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
245 | + syn_uncategorized(), s->fp_excp_el); | ||
246 | + return true; | ||
247 | + } | ||
248 | + | ||
249 | + return false; | ||
250 | +} | ||
251 | + | ||
252 | +static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) | ||
253 | +{ | ||
254 | + /* This range needs a coprocessor check for v8.1M and later only */ | ||
255 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
256 | + return false; | ||
257 | + } | ||
258 | + return trans_NOCP(s, a); | ||
259 | +} | ||
260 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
261 | index XXXXXXX..XXXXXXX 100644 | ||
262 | --- a/target/arm/translate.c | ||
263 | +++ b/target/arm/translate.c | ||
264 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
265 | #define ARM_CP_RW_BIT (1 << 20) | ||
266 | |||
267 | /* Include the VFP and Neon decoders */ | ||
268 | -#include "decode-m-nocp.c.inc" | ||
269 | #include "translate-vfp.c.inc" | ||
270 | #include "translate-neon.c.inc" | ||
271 | |||
272 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
273 | index XXXXXXX..XXXXXXX 100644 | ||
274 | --- a/target/arm/translate-vfp.c.inc | ||
275 | +++ b/target/arm/translate-vfp.c.inc | ||
276 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
277 | return true; | ||
278 | } | ||
279 | |||
280 | -/* | ||
281 | - * Decode VLLDM and VLSTM are nonstandard because: | ||
282 | - * * if there is no FPU then these insns must NOP in | ||
283 | - * Secure state and UNDEF in Nonsecure state | ||
284 | - * * if there is an FPU then these insns do not have | ||
285 | - * the usual behaviour that vfp_access_check() provides of | ||
286 | - * being controlled by CPACR/NSACR enable bits or the | ||
287 | - * lazy-stacking logic. | ||
288 | - */ | ||
289 | -static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | ||
290 | -{ | ||
291 | - TCGv_i32 fptr; | ||
292 | - | ||
293 | - if (!arm_dc_feature(s, ARM_FEATURE_M) || | ||
294 | - !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
295 | - return false; | ||
296 | - } | ||
297 | - | ||
298 | - if (a->op) { | ||
299 | - /* | ||
300 | - * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not | ||
301 | - * to take the IMPDEF option to make memory accesses to the stack | ||
302 | - * slots that correspond to the D16-D31 registers (discarding | ||
303 | - * read data and writing UNKNOWN values), so for us the T2 | ||
304 | - * encoding behaves identically to the T1 encoding. | ||
305 | - */ | ||
306 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
307 | - return false; | ||
308 | - } | ||
309 | - } else { | ||
310 | - /* | ||
311 | - * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. | ||
312 | - * This is currently architecturally impossible, but we add the | ||
313 | - * check to stay in line with the pseudocode. Note that we must | ||
314 | - * emit code for the UNDEF so it takes precedence over the NOCP. | ||
315 | - */ | ||
316 | - if (dc_isar_feature(aa32_simd_r32, s)) { | ||
317 | - unallocated_encoding(s); | ||
318 | - return true; | ||
319 | - } | ||
320 | - } | ||
321 | - | ||
322 | - /* | ||
323 | - * If not secure, UNDEF. We must emit code for this | ||
324 | - * rather than returning false so that this takes | ||
325 | - * precedence over the m-nocp.decode NOCP fallback. | ||
326 | - */ | ||
327 | - if (!s->v8m_secure) { | ||
328 | - unallocated_encoding(s); | ||
329 | - return true; | ||
330 | - } | ||
331 | - /* If no fpu, NOP. */ | ||
332 | - if (!dc_isar_feature(aa32_vfp, s)) { | ||
333 | - return true; | ||
334 | - } | ||
335 | - | ||
336 | - fptr = load_reg(s, a->rn); | ||
337 | - if (a->l) { | ||
338 | - gen_helper_v7m_vlldm(cpu_env, fptr); | ||
339 | - } else { | ||
340 | - gen_helper_v7m_vlstm(cpu_env, fptr); | ||
341 | - } | ||
342 | - tcg_temp_free_i32(fptr); | ||
343 | - | ||
344 | - /* End the TB, because we have updated FP control bits */ | ||
345 | - s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
346 | - return true; | ||
347 | -} | ||
348 | - | ||
349 | -static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
350 | -{ | ||
351 | - int btmreg, topreg; | ||
352 | - TCGv_i64 zero; | ||
353 | - TCGv_i32 aspen, sfpa; | ||
354 | - | ||
355 | - if (!dc_isar_feature(aa32_m_sec_state, s)) { | ||
356 | - /* Before v8.1M, fall through in decode to NOCP check */ | ||
357 | - return false; | ||
358 | - } | ||
359 | - | ||
360 | - /* Explicitly UNDEF because this takes precedence over NOCP */ | ||
361 | - if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { | ||
362 | - unallocated_encoding(s); | ||
363 | - return true; | ||
364 | - } | ||
365 | - | ||
366 | - if (!dc_isar_feature(aa32_vfp_simd, s)) { | ||
367 | - /* NOP if we have neither FP nor MVE */ | ||
368 | - return true; | ||
369 | - } | ||
370 | - | ||
371 | - /* | ||
372 | - * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no | ||
373 | - * active floating point context so we must NOP (without doing | ||
374 | - * any lazy state preservation or the NOCP check). | ||
375 | - */ | ||
376 | - aspen = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
377 | - sfpa = load_cpu_field(v7m.control[M_REG_S]); | ||
378 | - tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
379 | - tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
380 | - tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); | ||
381 | - tcg_gen_or_i32(sfpa, sfpa, aspen); | ||
382 | - arm_gen_condlabel(s); | ||
383 | - tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
384 | - | ||
385 | - if (s->fp_excp_el != 0) { | ||
386 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
387 | - syn_uncategorized(), s->fp_excp_el); | ||
388 | - return true; | ||
389 | - } | ||
390 | - | ||
391 | - topreg = a->vd + a->imm - 1; | ||
392 | - btmreg = a->vd; | ||
393 | - | ||
394 | - /* Convert to Sreg numbers if the insn specified in Dregs */ | ||
395 | - if (a->size == 3) { | ||
396 | - topreg = topreg * 2 + 1; | ||
397 | - btmreg *= 2; | ||
398 | - } | ||
399 | - | ||
400 | - if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { | ||
401 | - /* UNPREDICTABLE: we choose to undef */ | ||
402 | - unallocated_encoding(s); | ||
403 | - return true; | ||
404 | - } | ||
405 | - | ||
406 | - /* Silently ignore requests to clear D16-D31 if they don't exist */ | ||
407 | - if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { | ||
408 | - topreg = 31; | ||
409 | - } | ||
410 | - | ||
411 | - if (!vfp_access_check(s)) { | ||
412 | - return true; | ||
413 | - } | ||
414 | - | ||
415 | - /* Zero the Sregs from btmreg to topreg inclusive. */ | ||
416 | - zero = tcg_const_i64(0); | ||
417 | - if (btmreg & 1) { | ||
418 | - write_neon_element64(zero, btmreg >> 1, 1, MO_32); | ||
419 | - btmreg++; | ||
420 | - } | ||
421 | - for (; btmreg + 1 <= topreg; btmreg += 2) { | ||
422 | - write_neon_element64(zero, btmreg >> 1, 0, MO_64); | ||
423 | - } | ||
424 | - if (btmreg == topreg) { | ||
425 | - write_neon_element64(zero, btmreg >> 1, 0, MO_32); | ||
426 | - btmreg++; | ||
427 | - } | ||
428 | - assert(btmreg == topreg + 1); | ||
429 | - /* TODO: when MVE is implemented, zero VPR here */ | ||
430 | - return true; | ||
431 | -} | ||
432 | - | ||
433 | -static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
434 | -{ | ||
435 | - /* | ||
436 | - * Handle M-profile early check for disabled coprocessor: | ||
437 | - * all we need to do here is emit the NOCP exception if | ||
438 | - * the coprocessor is disabled. Otherwise we return false | ||
439 | - * and the real VFP/etc decode will handle the insn. | ||
440 | - */ | ||
441 | - assert(arm_dc_feature(s, ARM_FEATURE_M)); | ||
442 | - | ||
443 | - if (a->cp == 11) { | ||
444 | - a->cp = 10; | ||
445 | - } | ||
446 | - if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && | ||
447 | - (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { | ||
448 | - /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ | ||
449 | - a->cp = 10; | ||
450 | - } | ||
451 | - | ||
452 | - if (a->cp != 10) { | ||
453 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
454 | - syn_uncategorized(), default_exception_el(s)); | ||
455 | - return true; | ||
456 | - } | ||
457 | - | ||
458 | - if (s->fp_excp_el != 0) { | ||
459 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
460 | - syn_uncategorized(), s->fp_excp_el); | ||
461 | - return true; | ||
462 | - } | ||
463 | - | ||
464 | - return false; | ||
465 | -} | ||
466 | - | ||
467 | -static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) | ||
468 | -{ | ||
469 | - /* This range needs a coprocessor check for v8.1M and later only */ | ||
470 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
471 | - return false; | ||
472 | - } | ||
473 | - return trans_NOCP(s, a); | ||
474 | -} | ||
475 | - | ||
476 | static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
477 | { | ||
478 | TCGv_i32 rd, rm; | ||
479 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
480 | index XXXXXXX..XXXXXXX 100644 | ||
481 | --- a/target/arm/meson.build | ||
482 | +++ b/target/arm/meson.build | ||
483 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
484 | decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
485 | decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), | ||
486 | decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), | ||
487 | - decodetree.process('m-nocp.decode', extra_args: '--static-decode=disas_m_nocp'), | ||
488 | + decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
489 | decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), | ||
490 | decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
491 | decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), | ||
492 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
493 | 'op_helper.c', | ||
494 | 'tlb_helper.c', | ||
495 | 'translate.c', | ||
496 | + 'translate-m-nocp.c', | ||
497 | 'vec_helper.c', | ||
498 | 'vfp_helper.c', | ||
499 | 'cpu_tcg.c', | ||
500 | -- | ||
501 | 2.20.1 | ||
502 | |||
503 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the various gen_aa32* functions and macros out of translate.c | ||
2 | and into translate-a32.h. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-6-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 51 ++++++++++++------------------------ | ||
11 | 2 files changed, 69 insertions(+), 35 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a32.h | ||
16 | +++ b/target/arm/translate-a32.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) | ||
18 | return tmp; | ||
19 | } | ||
20 | |||
21 | +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | ||
22 | + TCGv_i32 a32, int index, MemOp opc); | ||
23 | +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | ||
24 | + TCGv_i32 a32, int index, MemOp opc); | ||
25 | +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
26 | + TCGv_i32 a32, int index, MemOp opc); | ||
27 | +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
28 | + TCGv_i32 a32, int index, MemOp opc); | ||
29 | +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
30 | + int index, MemOp opc); | ||
31 | +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
32 | + int index, MemOp opc); | ||
33 | +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
34 | + int index, MemOp opc); | ||
35 | +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
36 | + int index, MemOp opc); | ||
37 | + | ||
38 | +#define DO_GEN_LD(SUFF, OPC) \ | ||
39 | + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ | ||
40 | + TCGv_i32 a32, int index) \ | ||
41 | + { \ | ||
42 | + gen_aa32_ld_i32(s, val, a32, index, OPC); \ | ||
43 | + } | ||
44 | + | ||
45 | +#define DO_GEN_ST(SUFF, OPC) \ | ||
46 | + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ | ||
47 | + TCGv_i32 a32, int index) \ | ||
48 | + { \ | ||
49 | + gen_aa32_st_i32(s, val, a32, index, OPC); \ | ||
50 | + } | ||
51 | + | ||
52 | +static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, | ||
53 | + TCGv_i32 a32, int index) | ||
54 | +{ | ||
55 | + gen_aa32_ld_i64(s, val, a32, index, MO_Q); | ||
56 | +} | ||
57 | + | ||
58 | +static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, | ||
59 | + TCGv_i32 a32, int index) | ||
60 | +{ | ||
61 | + gen_aa32_st_i64(s, val, a32, index, MO_Q); | ||
62 | +} | ||
63 | + | ||
64 | +DO_GEN_LD(8u, MO_UB) | ||
65 | +DO_GEN_LD(16u, MO_UW) | ||
66 | +DO_GEN_LD(32u, MO_UL) | ||
67 | +DO_GEN_ST(8, MO_UB) | ||
68 | +DO_GEN_ST(16, MO_UW) | ||
69 | +DO_GEN_ST(32, MO_UL) | ||
70 | + | ||
71 | +#undef DO_GEN_LD | ||
72 | +#undef DO_GEN_ST | ||
73 | + | ||
74 | #endif | ||
75 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate.c | ||
78 | +++ b/target/arm/translate.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) | ||
80 | * Internal routines are used for NEON cases where the endianness | ||
81 | * and/or alignment has already been taken into account and manipulated. | ||
82 | */ | ||
83 | -static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | ||
84 | - TCGv_i32 a32, int index, MemOp opc) | ||
85 | +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | ||
86 | + TCGv_i32 a32, int index, MemOp opc) | ||
87 | { | ||
88 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
89 | tcg_gen_qemu_ld_i32(val, addr, index, opc); | ||
90 | tcg_temp_free(addr); | ||
91 | } | ||
92 | |||
93 | -static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | ||
94 | - TCGv_i32 a32, int index, MemOp opc) | ||
95 | +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | ||
96 | + TCGv_i32 a32, int index, MemOp opc) | ||
97 | { | ||
98 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
99 | tcg_gen_qemu_st_i32(val, addr, index, opc); | ||
100 | tcg_temp_free(addr); | ||
101 | } | ||
102 | |||
103 | -static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
104 | - TCGv_i32 a32, int index, MemOp opc) | ||
105 | +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
106 | + TCGv_i32 a32, int index, MemOp opc) | ||
107 | { | ||
108 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
111 | tcg_temp_free(addr); | ||
112 | } | ||
113 | |||
114 | -static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
115 | - TCGv_i32 a32, int index, MemOp opc) | ||
116 | +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
117 | + TCGv_i32 a32, int index, MemOp opc) | ||
118 | { | ||
119 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
122 | tcg_temp_free(addr); | ||
123 | } | ||
124 | |||
125 | -static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
126 | - int index, MemOp opc) | ||
127 | +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
128 | + int index, MemOp opc) | ||
129 | { | ||
130 | gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); | ||
131 | } | ||
132 | |||
133 | -static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
134 | - int index, MemOp opc) | ||
135 | +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
136 | + int index, MemOp opc) | ||
137 | { | ||
138 | gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); | ||
139 | } | ||
140 | |||
141 | -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
142 | - int index, MemOp opc) | ||
143 | +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
144 | + int index, MemOp opc) | ||
145 | { | ||
146 | gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); | ||
147 | } | ||
148 | |||
149 | -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
150 | - int index, MemOp opc) | ||
151 | +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
152 | + int index, MemOp opc) | ||
153 | { | ||
154 | gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); | ||
155 | } | ||
156 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
157 | gen_aa32_st_i32(s, val, a32, index, OPC); \ | ||
158 | } | ||
159 | |||
160 | -static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, | ||
161 | - TCGv_i32 a32, int index) | ||
162 | -{ | ||
163 | - gen_aa32_ld_i64(s, val, a32, index, MO_Q); | ||
164 | -} | ||
165 | - | ||
166 | -static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, | ||
167 | - TCGv_i32 a32, int index) | ||
168 | -{ | ||
169 | - gen_aa32_st_i64(s, val, a32, index, MO_Q); | ||
170 | -} | ||
171 | - | ||
172 | -DO_GEN_LD(8u, MO_UB) | ||
173 | -DO_GEN_LD(16u, MO_UW) | ||
174 | -DO_GEN_LD(32u, MO_UL) | ||
175 | -DO_GEN_ST(8, MO_UB) | ||
176 | -DO_GEN_ST(16, MO_UW) | ||
177 | -DO_GEN_ST(32, MO_UL) | ||
178 | - | ||
179 | static inline void gen_hvc(DisasContext *s, int imm16) | ||
180 | { | ||
181 | /* The pre HVC helper handles cases when HVC gets trapped | ||
182 | -- | ||
183 | 2.20.1 | ||
184 | |||
185 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() | ||
2 | and vfp_store_reg64() are used only in translate-vfp.c.inc. Move | ||
3 | them to that file. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210430132740.10391-7-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate.c | 20 -------------------- | ||
11 | target/arm/translate-vfp.c.inc | 20 ++++++++++++++++++++ | ||
12 | 2 files changed, 20 insertions(+), 20 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.c | ||
17 | +++ b/target/arm/translate.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | -static inline void vfp_load_reg64(TCGv_i64 var, int reg) | ||
23 | -{ | ||
24 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
25 | -} | ||
26 | - | ||
27 | -static inline void vfp_store_reg64(TCGv_i64 var, int reg) | ||
28 | -{ | ||
29 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
30 | -} | ||
31 | - | ||
32 | -static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
33 | -{ | ||
34 | - tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
35 | -} | ||
36 | - | ||
37 | -static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
38 | -{ | ||
39 | - tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
40 | -} | ||
41 | - | ||
42 | void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
43 | { | ||
44 | long off = neon_element_offset(reg, ele, memop); | ||
45 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-vfp.c.inc | ||
48 | +++ b/target/arm/translate-vfp.c.inc | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #include "decode-vfp.c.inc" | ||
51 | #include "decode-vfp-uncond.c.inc" | ||
52 | |||
53 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) | ||
54 | +{ | ||
55 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
56 | +} | ||
57 | + | ||
58 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) | ||
59 | +{ | ||
60 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
61 | +} | ||
62 | + | ||
63 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
64 | +{ | ||
65 | + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
66 | +} | ||
67 | + | ||
68 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
69 | +{ | ||
70 | + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
71 | +} | ||
72 | + | ||
73 | /* | ||
74 | * The imm8 encodes the sign bit, enough bits to represent an exponent in | ||
75 | * the range 01....1xx to 10....0xx, and the most significant 4 bits of | ||
76 | -- | ||
77 | 2.20.1 | ||
78 | |||
79 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make the remaining functions which are needed by translate-vfp.c.inc | ||
2 | global. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-8-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-a32.h | 18 ++++++++++++++++++ | ||
10 | target/arm/translate.c | 25 ++++++++----------------- | ||
11 | 2 files changed, 26 insertions(+), 17 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a32.h | ||
16 | +++ b/target/arm/translate-a32.h | ||
17 | @@ -XXX,XX +XXX,XX @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); | ||
18 | void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); | ||
19 | void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); | ||
20 | void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); | ||
21 | +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); | ||
22 | +void gen_set_cpsr(TCGv_i32 var, uint32_t mask); | ||
23 | +void gen_set_condexec(DisasContext *s); | ||
24 | +void gen_set_pc_im(DisasContext *s, target_ulong val); | ||
25 | +void gen_lookup_tb(DisasContext *s); | ||
26 | +long vfp_reg_offset(bool dp, unsigned reg); | ||
27 | +long neon_full_reg_offset(unsigned reg); | ||
28 | |||
29 | static inline TCGv_i32 load_cpu_offset(int offset) | ||
30 | { | ||
31 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) | ||
32 | return tmp; | ||
33 | } | ||
34 | |||
35 | +void store_reg(DisasContext *s, int reg, TCGv_i32 var); | ||
36 | + | ||
37 | void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | ||
38 | TCGv_i32 a32, int index, MemOp opc); | ||
39 | void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | ||
40 | @@ -XXX,XX +XXX,XX @@ DO_GEN_ST(32, MO_UL) | ||
41 | #undef DO_GEN_LD | ||
42 | #undef DO_GEN_ST | ||
43 | |||
44 | +#if defined(CONFIG_USER_ONLY) | ||
45 | +#define IS_USER(s) 1 | ||
46 | +#else | ||
47 | +#define IS_USER(s) (s->user) | ||
48 | +#endif | ||
49 | + | ||
50 | +/* Set NZCV flags from the high 4 bits of var. */ | ||
51 | +#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | ||
52 | + | ||
53 | #endif | ||
54 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/translate.c | ||
57 | +++ b/target/arm/translate.c | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "translate.h" | ||
60 | #include "translate-a32.h" | ||
61 | |||
62 | -#if defined(CONFIG_USER_ONLY) | ||
63 | -#define IS_USER(s) 1 | ||
64 | -#else | ||
65 | -#define IS_USER(s) (s->user) | ||
66 | -#endif | ||
67 | - | ||
68 | /* These are TCG temporaries used only by the legacy iwMMXt decoder */ | ||
69 | static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; | ||
70 | /* These are TCG globals which alias CPUARMState fields */ | ||
71 | @@ -XXX,XX +XXX,XX @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
72 | * This is used for load/store for which use of PC implies (literal), | ||
73 | * or ADD that implies ADR. | ||
74 | */ | ||
75 | -static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
76 | +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
77 | { | ||
78 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
81 | |||
82 | /* Set a CPU register. The source must be a temporary and will be | ||
83 | marked as dead. */ | ||
84 | -static void store_reg(DisasContext *s, int reg, TCGv_i32 var) | ||
85 | +void store_reg(DisasContext *s, int reg, TCGv_i32 var) | ||
86 | { | ||
87 | if (reg == 15) { | ||
88 | /* In Thumb mode, we must ignore bit 0. | ||
89 | @@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var) | ||
90 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) | ||
91 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) | ||
92 | |||
93 | - | ||
94 | -static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask) | ||
95 | +void gen_set_cpsr(TCGv_i32 var, uint32_t mask) | ||
96 | { | ||
97 | TCGv_i32 tmp_mask = tcg_const_i32(mask); | ||
98 | gen_helper_cpsr_write(cpu_env, var, tmp_mask); | ||
99 | tcg_temp_free_i32(tmp_mask); | ||
100 | } | ||
101 | -/* Set NZCV flags from the high 4 bits of var. */ | ||
102 | -#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | ||
103 | |||
104 | static void gen_exception_internal(int excp) | ||
105 | { | ||
106 | @@ -XXX,XX +XXX,XX @@ void arm_gen_test_cc(int cc, TCGLabel *label) | ||
107 | arm_free_cc(&cmp); | ||
108 | } | ||
109 | |||
110 | -static inline void gen_set_condexec(DisasContext *s) | ||
111 | +void gen_set_condexec(DisasContext *s) | ||
112 | { | ||
113 | if (s->condexec_mask) { | ||
114 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); | ||
115 | @@ -XXX,XX +XXX,XX @@ static inline void gen_set_condexec(DisasContext *s) | ||
116 | } | ||
117 | } | ||
118 | |||
119 | -static inline void gen_set_pc_im(DisasContext *s, target_ulong val) | ||
120 | +void gen_set_pc_im(DisasContext *s, target_ulong val) | ||
121 | { | ||
122 | tcg_gen_movi_i32(cpu_R[15], val); | ||
123 | } | ||
124 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | ||
125 | } | ||
126 | |||
127 | /* Force a TB lookup after an instruction that changes the CPU state. */ | ||
128 | -static inline void gen_lookup_tb(DisasContext *s) | ||
129 | +void gen_lookup_tb(DisasContext *s) | ||
130 | { | ||
131 | tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); | ||
132 | s->base.is_jmp = DISAS_EXIT; | ||
133 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) | ||
134 | /* | ||
135 | * Return the offset of a "full" NEON Dreg. | ||
136 | */ | ||
137 | -static long neon_full_reg_offset(unsigned reg) | ||
138 | +long neon_full_reg_offset(unsigned reg) | ||
139 | { | ||
140 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | ||
141 | } | ||
142 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp memop) | ||
143 | } | ||
144 | |||
145 | /* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ | ||
146 | -static long vfp_reg_offset(bool dp, unsigned reg) | ||
147 | +long vfp_reg_offset(bool dp, unsigned reg) | ||
148 | { | ||
149 | if (dp) { | ||
150 | return neon_element_offset(reg, 0, MO_64); | ||
151 | -- | ||
152 | 2.20.1 | ||
153 | |||
154 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch translate-vfp.c.inc from being #included into translate.c | ||
2 | to being its own compilation unit. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-9-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-a32.h | 2 ++ | ||
10 | target/arm/{translate-vfp.c.inc => translate-vfp.c} | 12 +++++++----- | ||
11 | target/arm/translate.c | 3 +-- | ||
12 | target/arm/meson.build | 5 +++-- | ||
13 | 4 files changed, 13 insertions(+), 9 deletions(-) | ||
14 | rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (99%) | ||
15 | |||
16 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate-a32.h | ||
19 | +++ b/target/arm/translate-a32.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | |||
22 | /* Prototypes for autogenerated disassembler functions */ | ||
23 | bool disas_m_nocp(DisasContext *dc, uint32_t insn); | ||
24 | +bool disas_vfp(DisasContext *s, uint32_t insn); | ||
25 | +bool disas_vfp_uncond(DisasContext *s, uint32_t insn); | ||
26 | |||
27 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | ||
28 | void arm_gen_condlabel(DisasContext *s); | ||
29 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c | ||
30 | similarity index 99% | ||
31 | rename from target/arm/translate-vfp.c.inc | ||
32 | rename to target/arm/translate-vfp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-vfp.c.inc | ||
35 | +++ b/target/arm/translate-vfp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
38 | */ | ||
39 | |||
40 | -/* | ||
41 | - * This file is intended to be included from translate.c; it uses | ||
42 | - * some macros and definitions provided by that file. | ||
43 | - * It might be possible to convert it to a standalone .c file eventually. | ||
44 | - */ | ||
45 | +#include "qemu/osdep.h" | ||
46 | +#include "tcg/tcg-op.h" | ||
47 | +#include "tcg/tcg-op-gvec.h" | ||
48 | +#include "exec/exec-all.h" | ||
49 | +#include "exec/gen-icount.h" | ||
50 | +#include "translate.h" | ||
51 | +#include "translate-a32.h" | ||
52 | |||
53 | /* Include the generated VFP decoder */ | ||
54 | #include "decode-vfp.c.inc" | ||
55 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/translate.c | ||
58 | +++ b/target/arm/translate.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
60 | |||
61 | #define ARM_CP_RW_BIT (1 << 20) | ||
62 | |||
63 | -/* Include the VFP and Neon decoders */ | ||
64 | -#include "translate-vfp.c.inc" | ||
65 | +/* Include the Neon decoder */ | ||
66 | #include "translate-neon.c.inc" | ||
67 | |||
68 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | ||
69 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/meson.build | ||
72 | +++ b/target/arm/meson.build | ||
73 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
74 | decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), | ||
75 | decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), | ||
76 | decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
77 | - decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), | ||
78 | - decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), | ||
79 | + decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), | ||
80 | + decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), | ||
81 | decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
82 | decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), | ||
83 | decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
84 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
85 | 'tlb_helper.c', | ||
86 | 'translate.c', | ||
87 | 'translate-m-nocp.c', | ||
88 | + 'translate-vfp.c', | ||
89 | 'vec_helper.c', | ||
90 | 'vfp_helper.c', | ||
91 | 'cpu_tcg.c', | ||
92 | -- | ||
93 | 2.20.1 | ||
94 | |||
95 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function vfp_reg_ptr() is used only in translate-neon.c.inc; | ||
2 | move it there. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-10-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate.c | 7 ------- | ||
10 | target/arm/translate-neon.c.inc | 7 +++++++ | ||
11 | 2 files changed, 7 insertions(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate.c | ||
16 | +++ b/target/arm/translate.c | ||
17 | @@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
18 | } | ||
19 | } | ||
20 | |||
21 | -static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
22 | -{ | ||
23 | - TCGv_ptr ret = tcg_temp_new_ptr(); | ||
24 | - tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); | ||
25 | - return ret; | ||
26 | -} | ||
27 | - | ||
28 | #define ARM_CP_RW_BIT (1 << 20) | ||
29 | |||
30 | /* Include the Neon decoder */ | ||
31 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate-neon.c.inc | ||
34 | +++ b/target/arm/translate-neon.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
36 | #include "decode-neon-ls.c.inc" | ||
37 | #include "decode-neon-shared.c.inc" | ||
38 | |||
39 | +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
40 | +{ | ||
41 | + TCGv_ptr ret = tcg_temp_new_ptr(); | ||
42 | + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); | ||
43 | + return ret; | ||
44 | +} | ||
45 | + | ||
46 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
47 | { | ||
48 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
49 | -- | ||
50 | 2.20.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The VFPGenFixPointFn typedef is unused; delete it. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Message-id: 20210430132740.10391-11-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/translate.c | 2 -- | ||
9 | 1 file changed, 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static const char * const regnames[] = | ||
16 | /* Function prototypes for gen_ functions calling Neon helpers. */ | ||
17 | typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
18 | TCGv_i32, TCGv_i32); | ||
19 | -/* Function prototypes for gen_ functions for fix point conversions */ | ||
20 | -typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
21 | |||
22 | /* initialize TCG globals. */ | ||
23 | void arm_translate_init(void) | ||
24 | -- | ||
25 | 2.20.1 | ||
26 | |||
27 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the NeonGenThreeOpEnvFn typedef to translate.h together | ||
2 | with the other similar typedefs. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Message-id: 20210430132740.10391-12-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate.h | 2 ++ | ||
10 | target/arm/translate.c | 3 --- | ||
11 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate.h | ||
16 | +++ b/target/arm/translate.h | ||
17 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); | ||
18 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); | ||
19 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | ||
20 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | ||
21 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
22 | + TCGv_i32, TCGv_i32); | ||
23 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); | ||
24 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); | ||
25 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | ||
26 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/translate.c | ||
29 | +++ b/target/arm/translate.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static const char * const regnames[] = | ||
31 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | ||
32 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | ||
33 | |||
34 | -/* Function prototypes for gen_ functions calling Neon helpers. */ | ||
35 | -typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
36 | - TCGv_i32, TCGv_i32); | ||
37 | |||
38 | /* initialize TCG globals. */ | ||
39 | void arm_translate_init(void) | ||
40 | -- | ||
41 | 2.20.1 | ||
42 | |||
43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make the remaining functions needed by the translate-neon code | ||
2 | global. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-13-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-a32.h | 8 ++++++++ | ||
10 | target/arm/translate.c | 10 ++-------- | ||
11 | 2 files changed, 10 insertions(+), 8 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a32.h | ||
16 | +++ b/target/arm/translate-a32.h | ||
17 | @@ -XXX,XX +XXX,XX @@ void gen_set_pc_im(DisasContext *s, target_ulong val); | ||
18 | void gen_lookup_tb(DisasContext *s); | ||
19 | long vfp_reg_offset(bool dp, unsigned reg); | ||
20 | long neon_full_reg_offset(unsigned reg); | ||
21 | +long neon_element_offset(int reg, int element, MemOp memop); | ||
22 | +void gen_rev16(TCGv_i32 dest, TCGv_i32 var); | ||
23 | |||
24 | static inline TCGv_i32 load_cpu_offset(int offset) | ||
25 | { | ||
26 | @@ -XXX,XX +XXX,XX @@ DO_GEN_ST(32, MO_UL) | ||
27 | /* Set NZCV flags from the high 4 bits of var. */ | ||
28 | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | ||
29 | |||
30 | +/* Swap low and high halfwords. */ | ||
31 | +static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) | ||
32 | +{ | ||
33 | + tcg_gen_rotri_i32(dest, var, 16); | ||
34 | +} | ||
35 | + | ||
36 | #endif | ||
37 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/translate.c | ||
40 | +++ b/target/arm/translate.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) | ||
42 | } | ||
43 | |||
44 | /* Byteswap each halfword. */ | ||
45 | -static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) | ||
46 | +void gen_rev16(TCGv_i32 dest, TCGv_i32 var) | ||
47 | { | ||
48 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
49 | TCGv_i32 mask = tcg_const_i32(0x00ff00ff); | ||
50 | @@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) | ||
51 | tcg_gen_ext16s_i32(dest, var); | ||
52 | } | ||
53 | |||
54 | -/* Swap low and high halfwords. */ | ||
55 | -static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) | ||
56 | -{ | ||
57 | - tcg_gen_rotri_i32(dest, var, 16); | ||
58 | -} | ||
59 | - | ||
60 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. | ||
61 | tmp = (t0 ^ t1) & 0x8000; | ||
62 | t0 &= ~0x8000; | ||
63 | @@ -XXX,XX +XXX,XX @@ long neon_full_reg_offset(unsigned reg) | ||
64 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
65 | * where 0 is the least significant end of the register. | ||
66 | */ | ||
67 | -static long neon_element_offset(int reg, int element, MemOp memop) | ||
68 | +long neon_element_offset(int reg, int element, MemOp memop) | ||
69 | { | ||
70 | int element_size = 1 << (memop & MO_SIZE); | ||
71 | int ofs = element * element_size; | ||
72 | -- | ||
73 | 2.20.1 | ||
74 | |||
75 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch translate-neon.c.inc from being #included into translate.c | ||
2 | to being its own compilation unit. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-14-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-a32.h | 3 +++ | ||
10 | .../arm/{translate-neon.c.inc => translate-neon.c} | 12 +++++++----- | ||
11 | target/arm/translate.c | 3 --- | ||
12 | target/arm/meson.build | 7 ++++--- | ||
13 | 4 files changed, 14 insertions(+), 11 deletions(-) | ||
14 | rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) | ||
15 | |||
16 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate-a32.h | ||
19 | +++ b/target/arm/translate-a32.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | bool disas_m_nocp(DisasContext *dc, uint32_t insn); | ||
22 | bool disas_vfp(DisasContext *s, uint32_t insn); | ||
23 | bool disas_vfp_uncond(DisasContext *s, uint32_t insn); | ||
24 | +bool disas_neon_dp(DisasContext *s, uint32_t insn); | ||
25 | +bool disas_neon_ls(DisasContext *s, uint32_t insn); | ||
26 | +bool disas_neon_shared(DisasContext *s, uint32_t insn); | ||
27 | |||
28 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | ||
29 | void arm_gen_condlabel(DisasContext *s); | ||
30 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c | ||
31 | similarity index 99% | ||
32 | rename from target/arm/translate-neon.c.inc | ||
33 | rename to target/arm/translate-neon.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/translate-neon.c.inc | ||
36 | +++ b/target/arm/translate-neon.c | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
39 | */ | ||
40 | |||
41 | -/* | ||
42 | - * This file is intended to be included from translate.c; it uses | ||
43 | - * some macros and definitions provided by that file. | ||
44 | - * It might be possible to convert it to a standalone .c file eventually. | ||
45 | - */ | ||
46 | +#include "qemu/osdep.h" | ||
47 | +#include "tcg/tcg-op.h" | ||
48 | +#include "tcg/tcg-op-gvec.h" | ||
49 | +#include "exec/exec-all.h" | ||
50 | +#include "exec/gen-icount.h" | ||
51 | +#include "translate.h" | ||
52 | +#include "translate-a32.h" | ||
53 | |||
54 | static inline int plus1(DisasContext *s, int x) | ||
55 | { | ||
56 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/translate.c | ||
59 | +++ b/target/arm/translate.c | ||
60 | @@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
61 | |||
62 | #define ARM_CP_RW_BIT (1 << 20) | ||
63 | |||
64 | -/* Include the Neon decoder */ | ||
65 | -#include "translate-neon.c.inc" | ||
66 | - | ||
67 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | ||
68 | { | ||
69 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); | ||
70 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/meson.build | ||
73 | +++ b/target/arm/meson.build | ||
74 | @@ -XXX,XX +XXX,XX @@ | ||
75 | gen = [ | ||
76 | decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), | ||
77 | - decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), | ||
78 | - decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), | ||
79 | - decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
80 | + decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), | ||
81 | + decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), | ||
82 | + decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), | ||
83 | decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), | ||
84 | decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), | ||
85 | decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
86 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
87 | 'tlb_helper.c', | ||
88 | 'translate.c', | ||
89 | 'translate-m-nocp.c', | ||
90 | + 'translate-neon.c', | ||
91 | 'translate-vfp.c', | ||
92 | 'vec_helper.c', | ||
93 | 'vfp_helper.c', | ||
94 | -- | ||
95 | 2.20.1 | ||
96 | |||
97 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The WFI insn is not system-mode only, though it doesn't usually make | ||
2 | a huge amount of sense for userspace code to execute it. Currently | ||
3 | if you try it in qemu-arm then the helper function will raise an | ||
4 | EXCP_HLT exception, which is not covered by the switch in cpu_loop() | ||
5 | and results in an abort: | ||
6 | 1 | ||
7 | qemu: unhandled CPU exception 0x10001 - aborting | ||
8 | R00=00000001 R01=408003e4 R02=408003ec R03=000102ec | ||
9 | R04=00010a28 R05=00010158 R06=00087460 R07=00010158 | ||
10 | R08=00000000 R09=00000000 R10=00085b7c R11=408002a4 | ||
11 | R12=408002b8 R13=408002a0 R14=0001057c R15=000102f8 | ||
12 | PSR=60000010 -ZC- A usr32 | ||
13 | qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x7fcbfa4f0a12 | ||
14 | |||
15 | Make the WFI helper function return immediately in the usermode | ||
16 | emulator. This turns WFI into a NOP, which is OK because: | ||
17 | * architecturally "WFI is a NOP" is a permitted implementation | ||
18 | * aarch64 Linux kernels use the SCTLR_EL1.nTWI bit to trap | ||
19 | userspace WFI and NOP it (though aarch32 kernels currently | ||
20 | just let WFI do whatever it would do) | ||
21 | |||
22 | We could in theory make the translate.c code special case user-mode | ||
23 | emulation and NOP the insn entirely rather than making the helper | ||
24 | do nothing, but because no real world code will be trying to | ||
25 | execute WFI we don't care about efficiency and the helper provides | ||
26 | a single place where we can make the change rather than having | ||
27 | to touch multiple places in translate.c and translate-a64.c. | ||
28 | |||
29 | Fixes: https://bugs.launchpad.net/qemu/+bug/1926759 | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
32 | Message-id: 20210430162212.825-1-peter.maydell@linaro.org | ||
33 | --- | ||
34 | target/arm/op_helper.c | 12 ++++++++++++ | ||
35 | 1 file changed, 12 insertions(+) | ||
36 | |||
37 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/op_helper.c | ||
40 | +++ b/target/arm/op_helper.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) | ||
42 | |||
43 | void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) | ||
44 | { | ||
45 | +#ifdef CONFIG_USER_ONLY | ||
46 | + /* | ||
47 | + * WFI in the user-mode emulator is technically permitted but not | ||
48 | + * something any real-world code would do. AArch64 Linux kernels | ||
49 | + * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; | ||
50 | + * AArch32 kernels don't trap it so it will delay a bit. | ||
51 | + * For QEMU, make it NOP here, because trying to raise EXCP_HLT | ||
52 | + * would trigger an abort. | ||
53 | + */ | ||
54 | + return; | ||
55 | +#else | ||
56 | CPUState *cs = env_cpu(env); | ||
57 | int target_el = check_wfx_trap(env, false); | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) | ||
60 | cs->exception_index = EXCP_HLT; | ||
61 | cs->halted = 1; | ||
62 | cpu_loop_exit(cs); | ||
63 | +#endif | ||
64 | } | ||
65 | |||
66 | void HELPER(wfe)(CPUARMState *env) | ||
67 | -- | ||
68 | 2.20.1 | ||
69 | |||
70 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The omap_mmc_reset() function resets its SD card via | ||
2 | device_legacy_reset(). We know that the SD card does not have a qbus | ||
3 | of its own, so the new device_cold_reset() function (which resets | ||
4 | both the device and its child buses) is equivalent here to | ||
5 | device_legacy_reset() and we can just switch to the new API. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20210430222348.8514-1-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/sd/omap_mmc.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/sd/omap_mmc.c | ||
17 | +++ b/hw/sd/omap_mmc.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) | ||
19 | * into any bus, and we must reset it manually. When omap_mmc is | ||
20 | * QOMified this must move into the QOM reset function. | ||
21 | */ | ||
22 | - device_legacy_reset(DEVICE(host->card)); | ||
23 | + device_cold_reset(DEVICE(host->card)); | ||
24 | } | ||
25 | |||
26 | static uint64_t omap_mmc_read(void *opaque, hwaddr offset, | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Both os-win32.h and os-posix.h include system header files. Instead | ||
2 | of having osdep.h include them inside its 'extern "C"' block, make | ||
3 | these headers handle that themselves, so that we don't include the | ||
4 | system headers inside 'extern "C"'. | ||
5 | 1 | ||
6 | This doesn't fix any current problems, but it's conceptually the | ||
7 | right way to handle system headers. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | include/qemu/osdep.h | 8 ++++---- | ||
13 | include/sysemu/os-posix.h | 8 ++++++++ | ||
14 | include/sysemu/os-win32.h | 8 ++++++++ | ||
15 | 3 files changed, 20 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/qemu/osdep.h | ||
20 | +++ b/include/qemu/osdep.h | ||
21 | @@ -XXX,XX +XXX,XX @@ QEMU_EXTERN_C int daemon(int, int); | ||
22 | */ | ||
23 | #include "glib-compat.h" | ||
24 | |||
25 | -#ifdef __cplusplus | ||
26 | -extern "C" { | ||
27 | -#endif | ||
28 | - | ||
29 | #ifdef _WIN32 | ||
30 | #include "sysemu/os-win32.h" | ||
31 | #endif | ||
32 | @@ -XXX,XX +XXX,XX @@ extern "C" { | ||
33 | #include "sysemu/os-posix.h" | ||
34 | #endif | ||
35 | |||
36 | +#ifdef __cplusplus | ||
37 | +extern "C" { | ||
38 | +#endif | ||
39 | + | ||
40 | #include "qemu/typedefs.h" | ||
41 | |||
42 | /* | ||
43 | diff --git a/include/sysemu/os-posix.h b/include/sysemu/os-posix.h | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/include/sysemu/os-posix.h | ||
46 | +++ b/include/sysemu/os-posix.h | ||
47 | @@ -XXX,XX +XXX,XX @@ | ||
48 | #include <sys/sysmacros.h> | ||
49 | #endif | ||
50 | |||
51 | +#ifdef __cplusplus | ||
52 | +extern "C" { | ||
53 | +#endif | ||
54 | + | ||
55 | void os_set_line_buffering(void); | ||
56 | void os_set_proc_name(const char *s); | ||
57 | void os_setup_signal_handling(void); | ||
58 | @@ -XXX,XX +XXX,XX @@ static inline void qemu_funlockfile(FILE *f) | ||
59 | funlockfile(f); | ||
60 | } | ||
61 | |||
62 | +#ifdef __cplusplus | ||
63 | +} | ||
64 | +#endif | ||
65 | + | ||
66 | #endif | ||
67 | diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/include/sysemu/os-win32.h | ||
70 | +++ b/include/sysemu/os-win32.h | ||
71 | @@ -XXX,XX +XXX,XX @@ | ||
72 | #include <windows.h> | ||
73 | #include <ws2tcpip.h> | ||
74 | |||
75 | +#ifdef __cplusplus | ||
76 | +extern "C" { | ||
77 | +#endif | ||
78 | + | ||
79 | #if defined(_WIN64) | ||
80 | /* On w64, setjmp is implemented by _setjmp which needs a second parameter. | ||
81 | * If this parameter is NULL, longjump does no stack unwinding. | ||
82 | @@ -XXX,XX +XXX,XX @@ ssize_t qemu_recv_wrap(int sockfd, void *buf, size_t len, int flags); | ||
83 | ssize_t qemu_recvfrom_wrap(int sockfd, void *buf, size_t len, int flags, | ||
84 | struct sockaddr *addr, socklen_t *addrlen); | ||
85 | |||
86 | +#ifdef __cplusplus | ||
87 | +} | ||
88 | +#endif | ||
89 | + | ||
90 | #endif | ||
91 | -- | ||
92 | 2.20.1 | ||
93 | |||
94 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make bswap.h handle being included outside an 'extern "C"' block: | ||
2 | all system headers are included first, then all declarations are | ||
3 | put inside an 'extern "C"' block. | ||
4 | 1 | ||
5 | This requires a little rearrangement as currently we have an ifdef | ||
6 | ladder that has some system includes and some local declarations | ||
7 | or definitions, and we need to separate those out. | ||
8 | |||
9 | We want to do this because dis-asm.h includes bswap.h, dis-asm.h | ||
10 | may need to be included from C++ files, and system headers should | ||
11 | not be included within 'extern "C"' blocks. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | --- | ||
16 | include/qemu/bswap.h | 26 ++++++++++++++++++++++---- | ||
17 | 1 file changed, 22 insertions(+), 4 deletions(-) | ||
18 | |||
19 | diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/qemu/bswap.h | ||
22 | +++ b/include/qemu/bswap.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | #ifndef BSWAP_H | ||
25 | #define BSWAP_H | ||
26 | |||
27 | -#include "fpu/softfloat-types.h" | ||
28 | - | ||
29 | #ifdef CONFIG_MACHINE_BSWAP_H | ||
30 | # include <sys/endian.h> | ||
31 | # include <machine/bswap.h> | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | # include <endian.h> | ||
34 | #elif defined(CONFIG_BYTESWAP_H) | ||
35 | # include <byteswap.h> | ||
36 | +#define BSWAP_FROM_BYTESWAP | ||
37 | +# else | ||
38 | +#define BSWAP_FROM_FALLBACKS | ||
39 | +#endif /* ! CONFIG_MACHINE_BSWAP_H */ | ||
40 | |||
41 | +#ifdef __cplusplus | ||
42 | +extern "C" { | ||
43 | +#endif | ||
44 | + | ||
45 | +#include "fpu/softfloat-types.h" | ||
46 | + | ||
47 | +#ifdef BSWAP_FROM_BYTESWAP | ||
48 | static inline uint16_t bswap16(uint16_t x) | ||
49 | { | ||
50 | return bswap_16(x); | ||
51 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t bswap64(uint64_t x) | ||
52 | { | ||
53 | return bswap_64(x); | ||
54 | } | ||
55 | -# else | ||
56 | +#endif | ||
57 | + | ||
58 | +#ifdef BSWAP_FROM_FALLBACKS | ||
59 | static inline uint16_t bswap16(uint16_t x) | ||
60 | { | ||
61 | return (((x & 0x00ff) << 8) | | ||
62 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t bswap64(uint64_t x) | ||
63 | ((x & 0x00ff000000000000ULL) >> 40) | | ||
64 | ((x & 0xff00000000000000ULL) >> 56)); | ||
65 | } | ||
66 | -#endif /* ! CONFIG_MACHINE_BSWAP_H */ | ||
67 | +#endif | ||
68 | + | ||
69 | +#undef BSWAP_FROM_BYTESWAP | ||
70 | +#undef BSWAP_FROM_FALLBACKS | ||
71 | |||
72 | static inline void bswap16s(uint16_t *s) | ||
73 | { | ||
74 | @@ -XXX,XX +XXX,XX @@ DO_STN_LDN_P(be) | ||
75 | #undef le_bswaps | ||
76 | #undef be_bswaps | ||
77 | |||
78 | +#ifdef __cplusplus | ||
79 | +} | ||
80 | +#endif | ||
81 | + | ||
82 | #endif /* BSWAP_H */ | ||
83 | -- | ||
84 | 2.20.1 | ||
85 | |||
86 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make dis-asm.h handle being included outside an 'extern "C"' block; | ||
2 | this allows us to remove the 'extern "C"' blocks that our two C++ | ||
3 | files that include it are using. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | include/disas/dis-asm.h | 12 ++++++++++-- | ||
9 | disas/arm-a64.cc | 2 -- | ||
10 | disas/nanomips.cpp | 2 -- | ||
11 | 3 files changed, 10 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/disas/dis-asm.h | ||
16 | +++ b/include/disas/dis-asm.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | #ifndef DISAS_DIS_ASM_H | ||
19 | #define DISAS_DIS_ASM_H | ||
20 | |||
21 | +#include "qemu/bswap.h" | ||
22 | + | ||
23 | +#ifdef __cplusplus | ||
24 | +extern "C" { | ||
25 | +#endif | ||
26 | + | ||
27 | typedef void *PTR; | ||
28 | typedef uint64_t bfd_vma; | ||
29 | typedef int64_t bfd_signed_vma; | ||
30 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); | ||
31 | |||
32 | /* from libbfd */ | ||
33 | |||
34 | -#include "qemu/bswap.h" | ||
35 | - | ||
36 | static inline bfd_vma bfd_getl64(const bfd_byte *addr) | ||
37 | { | ||
38 | return ldq_le_p(addr); | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline bfd_vma bfd_getb16(const bfd_byte *addr) | ||
40 | |||
41 | typedef bool bfd_boolean; | ||
42 | |||
43 | +#ifdef __cplusplus | ||
44 | +} | ||
45 | +#endif | ||
46 | + | ||
47 | #endif /* DISAS_DIS_ASM_H */ | ||
48 | diff --git a/disas/arm-a64.cc b/disas/arm-a64.cc | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/disas/arm-a64.cc | ||
51 | +++ b/disas/arm-a64.cc | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | */ | ||
54 | |||
55 | #include "qemu/osdep.h" | ||
56 | -extern "C" { | ||
57 | #include "disas/dis-asm.h" | ||
58 | -} | ||
59 | |||
60 | #include "vixl/a64/disasm-a64.h" | ||
61 | |||
62 | diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/disas/nanomips.cpp | ||
65 | +++ b/disas/nanomips.cpp | ||
66 | @@ -XXX,XX +XXX,XX @@ | ||
67 | */ | ||
68 | |||
69 | #include "qemu/osdep.h" | ||
70 | -extern "C" { | ||
71 | #include "disas/dis-asm.h" | ||
72 | -} | ||
73 | |||
74 | #include <cstring> | ||
75 | #include <stdexcept> | ||
76 | -- | ||
77 | 2.20.1 | ||
78 | |||
79 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | The i.MX25 PDK board has 2 banks for SDRAM, each can | ||
4 | address up to 256 MiB. So the total RAM usable for this | ||
5 | board is 512M. When we ask for more we get a misleading | ||
6 | error message: | ||
7 | |||
8 | $ qemu-system-arm -M imx25-pdk -m 513M | ||
9 | qemu-system-arm: Invalid RAM size, should be 128 MiB | ||
10 | |||
11 | Update the error message to better match the reality: | ||
12 | |||
13 | $ qemu-system-arm -M imx25-pdk -m 513M | ||
14 | qemu-system-arm: RAM size more than 512 MiB is not supported | ||
15 | |||
16 | Fixes: bf350daae02 ("arm/imx25_pdk: drop RAM size fixup") | ||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
20 | Message-id: 20210407225608.1882855-1-f4bug@amsat.org | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | hw/arm/imx25_pdk.c | 5 ++--- | ||
24 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
25 | |||
26 | diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/arm/imx25_pdk.c | ||
29 | +++ b/hw/arm/imx25_pdk.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info imx25_pdk_binfo; | ||
31 | |||
32 | static void imx25_pdk_init(MachineState *machine) | ||
33 | { | ||
34 | - MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
35 | IMX25PDK *s = g_new0(IMX25PDK, 1); | ||
36 | unsigned int ram_size; | ||
37 | unsigned int alias_offset; | ||
38 | @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine) | ||
39 | |||
40 | /* We need to initialize our memory */ | ||
41 | if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { | ||
42 | - char *sz = size_to_str(mc->default_ram_size); | ||
43 | - error_report("Invalid RAM size, should be %s", sz); | ||
44 | + char *sz = size_to_str(FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); | ||
45 | + error_report("RAM size more than %s is not supported", sz); | ||
46 | g_free(sz); | ||
47 | exit(EXIT_FAILURE); | ||
48 | } | ||
49 | -- | ||
50 | 2.20.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The MPS2 SCC device doesn't have any documentation of its properties; | ||
2 | add a "QEMU interface" format comment describing them. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20210504120912.23094-2-peter.maydell@linaro.org | ||
7 | --- | ||
8 | include/hw/misc/mps2-scc.h | 12 ++++++++++++ | ||
9 | 1 file changed, 12 insertions(+) | ||
10 | |||
11 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/include/hw/misc/mps2-scc.h | ||
14 | +++ b/include/hw/misc/mps2-scc.h | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | * (at your option) any later version. | ||
17 | */ | ||
18 | |||
19 | +/* | ||
20 | + * This is a model of the Serial Communication Controller (SCC) | ||
21 | + * block found in most MPS FPGA images. | ||
22 | + * | ||
23 | + * QEMU interface: | ||
24 | + * + sysbus MMIO region 0: the register bank | ||
25 | + * + QOM property "scc-cfg4": value of the read-only CFG4 register | ||
26 | + * + QOM property "scc-aid": value of the read-only SCC_AID register | ||
27 | + * + QOM property "scc-id": value of the read-only SCC_ID register | ||
28 | + * + QOM property array "oscclk": reset values of the OSCCLK registers | ||
29 | + * (which are accessed via the SYS_CFG channel provided by this device) | ||
30 | + */ | ||
31 | #ifndef MPS2_SCC_H | ||
32 | #define MPS2_SCC_H | ||
33 | |||
34 | -- | ||
35 | 2.20.1 | ||
36 | |||
37 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | On some boards, SCC config register CFG0 bit 0 controls whether | ||
2 | parts of the board memory map are remapped. Support this with: | ||
3 | * a device property scc-cfg0 so the board can specify the | ||
4 | initial value of the CFG0 register | ||
5 | * an outbound GPIO line which tracks bit 0 and which the board | ||
6 | can wire up to provide the remapping | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 20210504120912.23094-3-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/misc/mps2-scc.h | 9 +++++++++ | ||
14 | hw/misc/mps2-scc.c | 13 ++++++++++--- | ||
15 | 2 files changed, 19 insertions(+), 3 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/misc/mps2-scc.h | ||
20 | +++ b/include/hw/misc/mps2-scc.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | * + QOM property "scc-cfg4": value of the read-only CFG4 register | ||
23 | * + QOM property "scc-aid": value of the read-only SCC_AID register | ||
24 | * + QOM property "scc-id": value of the read-only SCC_ID register | ||
25 | + * + QOM property "scc-cfg0": reset value of the CFG0 register | ||
26 | * + QOM property array "oscclk": reset values of the OSCCLK registers | ||
27 | * (which are accessed via the SYS_CFG channel provided by this device) | ||
28 | + * + named GPIO output "remap": this tracks the value of CFG0 register | ||
29 | + * bit 0. Boards where this bit controls memory remapping should | ||
30 | + * connect this GPIO line to a function performing that mapping. | ||
31 | + * Boards where bit 0 has no special function should leave the GPIO | ||
32 | + * output disconnected. | ||
33 | */ | ||
34 | #ifndef MPS2_SCC_H | ||
35 | #define MPS2_SCC_H | ||
36 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { | ||
37 | uint32_t num_oscclk; | ||
38 | uint32_t *oscclk; | ||
39 | uint32_t *oscclk_reset; | ||
40 | + uint32_t cfg0_reset; | ||
41 | + | ||
42 | + qemu_irq remap; | ||
43 | }; | ||
44 | |||
45 | #endif | ||
46 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/misc/mps2-scc.c | ||
49 | +++ b/hw/misc/mps2-scc.c | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | #include "qemu/bitops.h" | ||
52 | #include "trace.h" | ||
53 | #include "hw/sysbus.h" | ||
54 | +#include "hw/irq.h" | ||
55 | #include "migration/vmstate.h" | ||
56 | #include "hw/registerfields.h" | ||
57 | #include "hw/misc/mps2-scc.h" | ||
58 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
59 | switch (offset) { | ||
60 | case A_CFG0: | ||
61 | /* | ||
62 | - * TODO on some boards bit 0 controls RAM remapping; | ||
63 | - * on others bit 1 is CPU_WAIT. | ||
64 | + * On some boards bit 0 controls board-specific remapping; | ||
65 | + * we always reflect bit 0 in the 'remap' GPIO output line, | ||
66 | + * and let the board wire it up or not as it chooses. | ||
67 | + * TODO on some boards bit 1 is CPU_WAIT. | ||
68 | */ | ||
69 | s->cfg0 = value; | ||
70 | + qemu_set_irq(s->remap, s->cfg0 & 1); | ||
71 | break; | ||
72 | case A_CFG1: | ||
73 | s->cfg1 = value; | ||
74 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) | ||
75 | int i; | ||
76 | |||
77 | trace_mps2_scc_reset(); | ||
78 | - s->cfg0 = 0; | ||
79 | + s->cfg0 = s->cfg0_reset; | ||
80 | s->cfg1 = 0; | ||
81 | s->cfg2 = 0; | ||
82 | s->cfg5 = 0; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_init(Object *obj) | ||
84 | |||
85 | memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); | ||
86 | sysbus_init_mmio(sbd, &s->iomem); | ||
87 | + qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); | ||
88 | } | ||
89 | |||
90 | static void mps2_scc_realize(DeviceState *dev, Error **errp) | ||
91 | @@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = { | ||
92 | DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), | ||
93 | DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), | ||
94 | DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), | ||
95 | + /* Reset value for CFG0 register */ | ||
96 | + DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), | ||
97 | /* | ||
98 | * These are the initial settings for the source clocks on the board. | ||
99 | * In hardware they can be configured via a config file read by the | ||
100 | -- | ||
101 | 2.20.1 | ||
102 | |||
103 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Guenter Roeck <linux@roeck-us.net> | ||
2 | 1 | ||
3 | Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr' | ||
4 | property value to 23") configured the PHY address for xilinx-zynq-a9 | ||
5 | to 23. When trying to boot xilinx-zynq-a9 with zynq-zc702.dtb or | ||
6 | zynq-zc706.dtb, this results in the following error message when | ||
7 | trying to use the Ethernet interface. | ||
8 | |||
9 | macb e000b000.ethernet eth0: Could not attach PHY (-19) | ||
10 | |||
11 | The devicetree files for ZC702 and ZC706 configure PHY address 7. The | ||
12 | documentation for the ZC702 and ZC706 evaluation boards suggest that the | ||
13 | PHY address is 7, not 23. Other boards use PHY address 0, 1, 3, or 7. | ||
14 | I was unable to find a documentation or a devicetree file suggesting | ||
15 | or using PHY address 23. The Ethernet interface starts working with | ||
16 | zynq-zc702.dtb and zynq-zc706.dtb when setting the PHY address to 7, | ||
17 | so let's use it. | ||
18 | |||
19 | Cc: Bin Meng <bin.meng@windriver.com> | ||
20 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
21 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | ||
22 | Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
23 | Message-id: 20210504124140.1100346-1-linux@roeck-us.net | ||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | --- | ||
26 | hw/arm/xilinx_zynq.c | 2 +- | ||
27 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
28 | |||
29 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/xilinx_zynq.c | ||
32 | +++ b/hw/arm/xilinx_zynq.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) | ||
34 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | ||
35 | qdev_set_nic_properties(dev, nd); | ||
36 | } | ||
37 | - object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); | ||
38 | + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); | ||
39 | s = SYS_BUS_DEVICE(dev); | ||
40 | sysbus_realize_and_unref(s, &error_fatal); | ||
41 | sysbus_mmio_map(s, 0, base); | ||
42 | -- | ||
43 | 2.20.1 | ||
44 | |||
45 | diff view generated by jsdifflib |