[PULL 00/42] riscv-to-apply queue
[PULL v2 00/45] riscv-to-apply queue
1
The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
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The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:
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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into staging (2021-05-02 16:23:05 +0100)
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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210504-2
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911
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for you to fetch changes up to 7a98eab3a704139020bdad35bfae0356d2a31fa0:
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for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a:
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target/riscv: Fix the RV64H decode comment (2021-05-04 08:03:43 +1000)
11
target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000)
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
A large collection of RISC-V fixes, improvements and features
14
First RISC-V PR for 8.2
15
15
16
- Clenaup some left over v1.9 code
16
* Remove 'host' CPU from TCG
17
- Documentation improvements
17
* riscv_htif Fixup printing on big endian hosts
18
- Support for the shakti_c machine
18
* Add zmmul isa string
19
- Internal cleanup of the CSR accesses
19
* Add smepmp isa string
20
- Updates to the OpenTitan platform
20
* Fix page_check_range use in fault-only-first
21
- Support for the virtio-vga
21
* Use existing lookup tables for MixColumns
22
- Fix for the saturate subtract in vector extensions
22
* Add RISC-V vector cryptographic instruction set support
23
- Experimental support for the ePMP spec
23
* Implement WARL behaviour for mcountinhibit/mcounteren
24
- A range of other internal code cleanups and bug fixes
24
* Add Zihintntl extension ISA string to DTS
25
* Fix zfa fleq.d and fltq.d
26
* Fix upper/lower mtime write calculation
27
* Make rtc variable names consistent
28
* Use abi type for linux-user target_ucontext
29
* Add RISC-V KVM AIA Support
30
* Fix riscv,pmu DT node path in the virt machine
31
* Update CSR bits name for svadu extension
32
* Mark zicond non-experimental
33
* Fix satp_mode_finalize() when satp_mode.supported = 0
34
* Fix non-KVM --enable-debug build
35
* Add new extensions to hwprobe
36
* Use accelerated helper for AES64KS1I
37
* Allocate itrigger timers only once
38
* Respect mseccfg.RLB for pmpaddrX changes
39
* Align the AIA model to v1.0 ratified spec
40
* Don't read the CSR in riscv_csrrw_do64
25
41
26
----------------------------------------------------------------
42
----------------------------------------------------------------
27
Alexander Wagner (1):
43
Akihiko Odaki (1):
28
hw/riscv: Fix OT IBEX reset vector
44
target/riscv: Allocate itrigger timers only once
29
45
30
Alistair Francis (22):
46
Ard Biesheuvel (2):
31
target/riscv: Convert the RISC-V exceptions to an enum
47
target/riscv: Use existing lookup tables for MixColumns
32
target/riscv: Use the RISCVException enum for CSR predicates
48
target/riscv: Use accelerated helper for AES64KS1I
33
target/riscv: Fix 32-bit HS mode access permissions
34
target/riscv: Use the RISCVException enum for CSR operations
35
target/riscv: Use RISCVException enum for CSR access
36
MAINTAINERS: Update the RISC-V CPU Maintainers
37
hw/opentitan: Update the interrupt layout
38
hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
39
target/riscv: Fix the PMP is locked check when using TOR
40
target/riscv: Add the ePMP feature
41
target/riscv/pmp: Remove outdated comment
42
target/riscv: Add ePMP support for the Ibex CPU
43
target/riscv: Remove the hardcoded RVXLEN macro
44
target/riscv: Remove the hardcoded SSTATUS_SD macro
45
target/riscv: Remove the hardcoded HGATP_MODE macro
46
target/riscv: Remove the hardcoded MSTATUS_SD macro
47
target/riscv: Remove the hardcoded SATP_MODE macro
48
target/riscv: Remove the unused HSTATUS_WPRI macro
49
target/riscv: Remove an unused CASE_OP_32_64 macro
50
target/riscv: Consolidate RV32/64 32-bit instructions
51
target/riscv: Consolidate RV32/64 16-bit instructions
52
target/riscv: Fix the RV64H decode comment
53
49
54
Atish Patra (1):
50
Conor Dooley (1):
55
target/riscv: Remove privilege v1.9 specific CSR related code
51
hw/riscv: virt: Fix riscv,pmu DT node path
56
52
57
Axel Heider (1):
53
Daniel Henrique Barboza (6):
58
docs/system/generic-loader.rst: Fix style
54
target/riscv/cpu.c: do not run 'host' CPU with TCG
55
target/riscv/cpu.c: add zmmul isa string
56
target/riscv/cpu.c: add smepmp isa string
57
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
58
hw/riscv/virt.c: fix non-KVM --enable-debug build
59
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
59
60
60
Bin Meng (1):
61
Dickon Hood (2):
61
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
62
target/riscv: Refactor translation of vector-widening instruction
63
target/riscv: Add Zvbb ISA extension support
62
64
63
Dylan Jhong (1):
65
Jason Chien (3):
64
target/riscv: Align the data type of reset vector address
66
target/riscv: Add Zihintntl extension ISA string to DTS
67
hw/intc: Fix upper/lower mtime write calculation
68
hw/intc: Make rtc variable names consistent
65
69
66
Emmanuel Blot (2):
70
Kiran Ostrolenk (4):
67
target/riscv: fix exception index on instruction access fault
71
target/riscv: Refactor some of the generic vector functionality
68
target/riscv: fix a typo with interrupt names
72
target/riscv: Refactor vector-vector translation macro
73
target/riscv: Refactor some of the generic vector functionality
74
target/riscv: Add Zvknh ISA extension support
69
75
70
Frank Chang (2):
76
LIU Zhiwei (3):
71
target/riscv: fix vrgather macro index variable type bug
77
target/riscv: Fix page_check_range use in fault-only-first
72
fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
78
target/riscv: Fix zfa fleq.d and fltq.d
79
linux-user/riscv: Use abi type for target_ucontext
73
80
74
Hou Weiying (4):
81
Lawrence Hunter (2):
75
target/riscv: Define ePMP mseccfg
82
target/riscv: Add Zvbc ISA extension support
76
target/riscv: Add ePMP CSR access functions
83
target/riscv: Add Zvksh ISA extension support
77
target/riscv: Implementation of enhanced PMP (ePMP)
78
target/riscv: Add a config option for ePMP
79
84
80
Jade Fink (1):
85
Leon Schuermann (1):
81
riscv: don't look at SUM when accessing memory from a debugger context
86
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
82
87
83
LIU Zhiwei (1):
88
Max Chou (3):
84
target/riscv: Fixup saturate subtract function
89
crypto: Create sm4_subword
90
crypto: Add SM4 constant parameter CK
91
target/riscv: Add Zvksed ISA extension support
85
92
86
Vijai Kumar K (5):
93
Nazar Kazakov (4):
87
target/riscv: Add Shakti C class CPU
94
target/riscv: Remove redundant "cpu_vl == 0" checks
88
riscv: Add initial support for Shakti C machine
95
target/riscv: Move vector translation checks
89
hw/char: Add Shakti UART emulation
96
target/riscv: Add Zvkned ISA extension support
90
hw/riscv: Connect Shakti UART to Shakti platform
97
target/riscv: Add Zvkg ISA extension support
91
docs: Add documentation for shakti_c machine
92
98
93
docs/system/generic-loader.rst | 9 +-
99
Nikita Shubin (1):
94
docs/system/riscv/shakti-c.rst | 82 +++
100
target/riscv: don't read CSR in riscv_csrrw_do64
95
default-configs/devices/riscv64-softmmu.mak | 1 +
96
include/hw/char/shakti_uart.h | 74 +++
97
include/hw/riscv/opentitan.h | 16 +-
98
include/hw/riscv/shakti_c.h | 75 +++
99
target/riscv/cpu.h | 42 +-
100
target/riscv/cpu_bits.h | 114 +---
101
target/riscv/helper.h | 18 +-
102
target/riscv/pmp.h | 14 +
103
target/riscv/insn16-32.decode | 28 -
104
target/riscv/insn16-64.decode | 36 --
105
target/riscv/insn16.decode | 30 +
106
target/riscv/insn32-64.decode | 88 ---
107
target/riscv/insn32.decode | 67 ++-
108
hw/char/shakti_uart.c | 185 +++++++
109
hw/intc/ibex_plic.c | 20 +-
110
hw/riscv/opentitan.c | 10 +-
111
hw/riscv/shakti_c.c | 178 ++++++
112
hw/riscv/sifive_e.c | 2 +-
113
target/riscv/cpu.c | 26 +-
114
target/riscv/cpu_helper.c | 88 ++-
115
target/riscv/csr.c | 824 +++++++++++++++++-----------
116
target/riscv/fpu_helper.c | 16 +-
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/machine.c | 8 +-
119
target/riscv/monitor.c | 22 +-
120
target/riscv/op_helper.c | 18 +-
121
target/riscv/pmp.c | 218 +++++++-
122
target/riscv/translate.c | 38 +-
123
target/riscv/vector_helper.c | 18 +-
124
fpu/softfloat-specialize.c.inc | 6 +
125
target/riscv/insn_trans/trans_rva.c.inc | 14 +-
126
target/riscv/insn_trans/trans_rvd.c.inc | 17 +-
127
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
128
target/riscv/insn_trans/trans_rvh.c.inc | 8 +-
129
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-
130
target/riscv/insn_trans/trans_rvm.c.inc | 12 +-
131
target/riscv/insn_trans/trans_rvv.c.inc | 39 +-
132
MAINTAINERS | 14 +-
133
hw/char/meson.build | 1 +
134
hw/char/trace-events | 4 +
135
hw/riscv/Kconfig | 11 +
136
hw/riscv/meson.build | 1 +
137
target/riscv/meson.build | 13 +-
138
target/riscv/trace-events | 3 +
139
46 files changed, 1755 insertions(+), 789 deletions(-)
140
create mode 100644 docs/system/riscv/shakti-c.rst
141
create mode 100644 include/hw/char/shakti_uart.h
142
create mode 100644 include/hw/riscv/shakti_c.h
143
delete mode 100644 target/riscv/insn16-32.decode
144
delete mode 100644 target/riscv/insn16-64.decode
145
delete mode 100644 target/riscv/insn32-64.decode
146
create mode 100644 hw/char/shakti_uart.c
147
create mode 100644 hw/riscv/shakti_c.c
148
101
102
Rob Bradford (1):
103
target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
104
105
Robbin Ehn (1):
106
linux-user/riscv: Add new extensions to hwprobe
107
108
Thomas Huth (2):
109
hw/char/riscv_htif: Fix printing of console characters on big endian hosts
110
hw/char/riscv_htif: Fix the console syscall on big endian hosts
111
112
Tommy Wu (1):
113
target/riscv: Align the AIA model to v1.0 ratified spec
114
115
Vineet Gupta (1):
116
riscv: zicond: make non-experimental
117
118
Weiwei Li (1):
119
target/riscv: Update CSR bits name for svadu extension
120
121
Yong-Xuan Wang (5):
122
target/riscv: support the AIA device emulation with KVM enabled
123
target/riscv: check the in-kernel irqchip support
124
target/riscv: Create an KVM AIA irqchip
125
target/riscv: update APLIC and IMSIC to support KVM AIA
126
target/riscv: select KVM AIA in riscv virt machine
127
128
include/crypto/aes.h | 7 +
129
include/crypto/sm4.h | 9 +
130
target/riscv/cpu_bits.h | 8 +-
131
target/riscv/cpu_cfg.h | 9 +
132
target/riscv/debug.h | 3 +-
133
target/riscv/helper.h | 98 +++
134
target/riscv/kvm_riscv.h | 5 +
135
target/riscv/vector_internals.h | 228 +++++++
136
target/riscv/insn32.decode | 58 ++
137
crypto/aes.c | 4 +-
138
crypto/sm4.c | 10 +
139
hw/char/riscv_htif.c | 12 +-
140
hw/intc/riscv_aclint.c | 11 +-
141
hw/intc/riscv_aplic.c | 52 +-
142
hw/intc/riscv_imsic.c | 25 +-
143
hw/riscv/virt.c | 374 ++++++------
144
linux-user/riscv/signal.c | 4 +-
145
linux-user/syscall.c | 14 +-
146
target/arm/tcg/crypto_helper.c | 10 +-
147
target/riscv/cpu.c | 83 ++-
148
target/riscv/cpu_helper.c | 6 +-
149
target/riscv/crypto_helper.c | 51 +-
150
target/riscv/csr.c | 54 +-
151
target/riscv/debug.c | 15 +-
152
target/riscv/kvm.c | 201 ++++++-
153
target/riscv/pmp.c | 4 +
154
target/riscv/translate.c | 1 +
155
target/riscv/vcrypto_helper.c | 970 ++++++++++++++++++++++++++++++
156
target/riscv/vector_helper.c | 245 +-------
157
target/riscv/vector_internals.c | 81 +++
158
target/riscv/insn_trans/trans_rvv.c.inc | 171 +++---
159
target/riscv/insn_trans/trans_rvvk.c.inc | 606 +++++++++++++++++++
160
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 +-
161
target/riscv/meson.build | 4 +-
162
34 files changed, 2785 insertions(+), 652 deletions(-)
163
create mode 100644 target/riscv/vector_internals.h
164
create mode 100644 target/riscv/vcrypto_helper.c
165
create mode 100644 target/riscv/vector_internals.c
166
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
diff view generated by jsdifflib
[PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform
[PULL v2 01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG
1
From: Vijai Kumar K <vijai@behindbytes.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Connect one shakti uart to the shakti_c machine.
3
The 'host' CPU is available in a CONFIG_KVM build and it's currently
4
available for all accels, but is a KVM only CPU. This means that in a
5
RISC-V KVM capable host we can do things like this:
4
6
5
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
7
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
8
qemu-system-riscv64: H extension requires priv spec 1.12.0
9
10
This CPU does not have a priv spec because we don't filter its extensions
11
via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
12
with the 'host' CPU.
13
14
We don't have a way to filter the 'host' CPU out of the available CPU
15
options (-cpu help) if the build includes both KVM and TCG. What we can
16
do is to error out during riscv_cpu_realize_tcg() if the user chooses
17
the 'host' CPU with accel=tcg:
18
19
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
20
qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
24
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
25
Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
27
---
10
include/hw/riscv/shakti_c.h | 2 ++
28
target/riscv/cpu.c | 5 +++++
11
hw/riscv/shakti_c.c | 8 ++++++++
29
1 file changed, 5 insertions(+)
12
2 files changed, 10 insertions(+)
13
30
14
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
15
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/riscv/shakti_c.h
33
--- a/target/riscv/cpu.c
17
+++ b/include/hw/riscv/shakti_c.h
34
+++ b/target/riscv/cpu.c
18
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
19
36
CPURISCVState *env = &cpu->env;
20
#include "hw/riscv/riscv_hart.h"
37
Error *local_err = NULL;
21
#include "hw/boards.h"
38
22
+#include "hw/char/shakti_uart.h"
39
+ if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
23
40
+ error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
24
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
25
#define RISCV_SHAKTI_SOC(obj) \
26
@@ -XXX,XX +XXX,XX @@ typedef struct ShaktiCSoCState {
27
/*< public >*/
28
RISCVHartArrayState cpus;
29
DeviceState *plic;
30
+ ShaktiUartState uart;
31
MemoryRegion rom;
32
33
} ShaktiCSoCState;
34
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/riscv/shakti_c.c
37
+++ b/hw/riscv/shakti_c.c
38
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
39
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
40
SIFIVE_CLINT_TIMEBASE_FREQ, false);
41
42
+ qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
43
+ if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
44
+ return;
41
+ return;
45
+ }
42
+ }
46
+ sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
47
+ shakti_c_memmap[SHAKTI_C_UART].base);
48
+
43
+
49
/* ROM */
44
riscv_cpu_validate_misa_mxl(cpu, &local_err);
50
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
45
if (local_err != NULL) {
51
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
46
error_propagate(errp, local_err);
52
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_instance_init(Object *obj)
53
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
54
55
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
56
+ object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
57
58
/*
59
* CPU type is fixed and we are not supporting passing from commandline yet.
60
--
47
--
61
2.31.1
48
2.41.0
62
49
63
50
diff view generated by jsdifflib
[PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro
[PULL v2 02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts
1
From: Thomas Huth <thuth@redhat.com>
2
3
The character that should be printed is stored in the 64 bit "payload"
4
variable. The code currently tries to print it by taking the address
5
of the variable and passing this pointer to qemu_chr_fe_write(). However,
6
this only works on little endian hosts where the least significant bits
7
are stored on the lowest address. To do this in a portable way, we have
8
to store the value in an uint8_t variable instead.
9
10
Fixes: 5033606780 ("RISC-V HTIF Console")
11
Signed-off-by: Thomas Huth <thuth@redhat.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Bin Meng <bmeng@tinylab.org>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Message-Id: <20230721094720.902454-2-thuth@redhat.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: 4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
5
---
18
---
6
target/riscv/translate.c | 6 ------
19
hw/char/riscv_htif.c | 3 ++-
7
1 file changed, 6 deletions(-)
20
1 file changed, 2 insertions(+), 1 deletion(-)
8
21
9
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
22
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
10
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
11
--- a/target/riscv/translate.c
24
--- a/hw/char/riscv_htif.c
12
+++ b/target/riscv/translate.c
25
+++ b/hw/char/riscv_htif.c
13
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
26
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
14
CPUState *cs;
27
s->tohost = 0; /* clear to indicate we read */
15
} DisasContext;
28
return;
16
29
} else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
17
-#ifdef TARGET_RISCV64
30
- qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
18
-#define CASE_OP_32_64(X) case X: case glue(X, W)
31
+ uint8_t ch = (uint8_t)payload;
19
-#else
32
+ qemu_chr_fe_write(&s->chr, &ch, 1);
20
-#define CASE_OP_32_64(X) case X
33
resp = 0x100 | (uint8_t)payload;
21
-#endif
34
} else {
22
-
35
qemu_log("HTIF device %d: unknown command\n", device);
23
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
24
{
25
return ctx->misa & ext;
26
--
36
--
27
2.31.1
37
2.41.0
28
38
29
39
diff view generated by jsdifflib
New patch
[PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
Values that have been read via cpu_physical_memory_read() from the
4
guest's memory have to be swapped in case the host endianess differs
5
from the guest.
6
7
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Bin Meng <bmeng@tinylab.org>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-Id: <20230721094720.902454-3-thuth@redhat.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
hw/char/riscv_htif.c | 9 +++++----
16
1 file changed, 5 insertions(+), 4 deletions(-)
17
18
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/riscv_htif.c
21
+++ b/hw/char/riscv_htif.c
22
@@ -XXX,XX +XXX,XX @@
23
#include "qemu/timer.h"
24
#include "qemu/error-report.h"
25
#include "exec/address-spaces.h"
26
+#include "exec/tswap.h"
27
#include "sysemu/dma.h"
28
29
#define RISCV_DEBUG_HTIF 0
30
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
31
} else {
32
uint64_t syscall[8];
33
cpu_physical_memory_read(payload, syscall, sizeof(syscall));
34
- if (syscall[0] == PK_SYS_WRITE &&
35
- syscall[1] == HTIF_DEV_CONSOLE &&
36
- syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
37
+ if (tswap64(syscall[0]) == PK_SYS_WRITE &&
38
+ tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
39
+ tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
40
uint8_t ch;
41
- cpu_physical_memory_read(syscall[2], &ch, 1);
42
+ cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
43
qemu_chr_fe_write(&s->chr, &ch, 1);
44
resp = 0x100 | (uint8_t)payload;
45
} else {
46
--
47
2.41.0
diff view generated by jsdifflib
[PULL 27/42] target/riscv: Add ePMP support for the Ibex CPU
[PULL v2 04/45] target/riscv/cpu.c: add zmmul isa string
1
The physical Ibex CPU has ePMP support and it's enabled for the
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
3
2
3
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
4
Add a riscv,isa string for it.
5
6
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties")
7
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com>
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
7
---
12
---
8
target/riscv/cpu.c | 1 +
13
target/riscv/cpu.c | 1 +
9
1 file changed, 1 insertion(+)
14
1 file changed, 1 insertion(+)
10
15
11
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
16
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.c
18
--- a/target/riscv/cpu.c
14
+++ b/target/riscv/cpu.c
19
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
16
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
21
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
17
set_priv_version(env, PRIV_VERSION_1_10_0);
22
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
18
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
23
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
19
+ qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
24
+ ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
20
}
25
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
21
26
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
22
static void rv32_imafcu_nommu_cpu_init(Object *obj)
27
ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
23
--
28
--
24
2.31.1
29
2.41.0
25
26
diff view generated by jsdifflib
[PULL 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
[PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string
1
imply VIRTIO_VGA for the virt machine, this fixes the following error
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
when specifying `-vga virtio` as a command line argument:
3
2
4
qemu-system-riscv64: Virtio VGA not available
3
The cpu->cfg.epmp extension is still experimental, but it already has a
4
'smepmp' riscv,isa string. Add it.
5
5
6
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Message-id: 7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
9
---
11
---
10
hw/riscv/Kconfig | 1 +
12
target/riscv/cpu.c | 1 +
11
1 file changed, 1 insertion(+)
13
1 file changed, 1 insertion(+)
12
14
13
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
15
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/riscv/Kconfig
17
--- a/target/riscv/cpu.c
16
+++ b/hw/riscv/Kconfig
18
+++ b/target/riscv/cpu.c
17
@@ -XXX,XX +XXX,XX @@ config SHAKTI_C
19
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
18
config RISCV_VIRT
20
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
19
bool
21
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
20
imply PCI_DEVICES
22
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
21
+ imply VIRTIO_VGA
23
+ ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
22
imply TEST_DEVICES
24
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
23
select GOLDFISH_RTC
25
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
24
select MSI_NONBROKEN
26
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
25
--
27
--
26
2.31.1
28
2.41.0
27
28
diff view generated by jsdifflib
[PULL 28/42] target/riscv: fix vrgather macro index variable type bug
[PULL v2 06/45] target/riscv: Fix page_check_range use in fault-only-first
1
From: Frank Chang <frank.chang@sifive.com>
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
2
2
3
ETYPE may be type of uint64_t, thus index variable has to be declared as
3
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
4
type of uint64_t, too. Otherwise the value read from vs1 register may be
4
integer return value to bool type. However, it wrongly converted the use
5
truncated to type of uint32_t.
5
of the API in riscv fault-only-first, where page_check_range < = 0, should
6
be converted to !page_check_range.
6
7
7
Signed-off-by: Frank Chang <frank.chang@sifive.com>
8
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
10
Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
target/riscv/vector_helper.c | 6 ++++--
13
target/riscv/vector_helper.c | 2 +-
13
1 file changed, 4 insertions(+), 2 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
16
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/vector_helper.c
18
--- a/target/riscv/vector_helper.c
18
+++ b/target/riscv/vector_helper.c
19
+++ b/target/riscv/vector_helper.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
20
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
20
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
21
cpu_mmu_index(env, false));
21
uint32_t vm = vext_vm(desc); \
22
if (host) {
22
uint32_t vl = env->vl; \
23
#ifdef CONFIG_USER_ONLY
23
- uint32_t index, i; \
24
- if (page_check_range(addr, offset, PAGE_READ)) {
24
+ uint64_t index; \
25
+ if (!page_check_range(addr, offset, PAGE_READ)) {
25
+ uint32_t i; \
26
vl = i;
26
\
27
goto ProbeSuccess;
27
for (i = 0; i < vl; i++) { \
28
}
28
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
29
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
30
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
31
uint32_t vm = vext_vm(desc); \
32
uint32_t vl = env->vl; \
33
- uint32_t index = s1, i; \
34
+ uint64_t index = s1; \
35
+ uint32_t i; \
36
\
37
for (i = 0; i < vl; i++) { \
38
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
39
--
29
--
40
2.31.1
30
2.41.0
41
42
diff view generated by jsdifflib
[PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro
[PULL v2 07/45] target/riscv: Use existing lookup tables for MixColumns
1
From: Ard Biesheuvel <ardb@kernel.org>
2
3
The AES MixColumns and InvMixColumns operations are relatively
4
expensive 4x4 matrix multiplications in GF(2^8), which is why C
5
implementations usually rely on precomputed lookup tables rather than
6
performing the calculations on demand.
7
8
Given that we already carry those tables in QEMU, we can just grab the
9
right value in the implementation of the RISC-V AES32 instructions. Note
10
that the tables in question are permuted according to the respective
11
Sbox, so we can omit the Sbox lookup as well in this case.
12
13
Cc: Richard Henderson <richard.henderson@linaro.org>
14
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Cc: Zewen Ye <lustrew@foxmail.com>
16
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
17
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
18
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
5
---
22
---
6
target/riscv/cpu_bits.h | 6 ------
23
include/crypto/aes.h | 7 +++++++
7
1 file changed, 6 deletions(-)
24
crypto/aes.c | 4 ++--
25
target/riscv/crypto_helper.c | 34 ++++------------------------------
26
3 files changed, 13 insertions(+), 32 deletions(-)
8
27
9
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
28
diff --git a/include/crypto/aes.h b/include/crypto/aes.h
10
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
11
--- a/target/riscv/cpu_bits.h
30
--- a/include/crypto/aes.h
12
+++ b/target/riscv/cpu_bits.h
31
+++ b/include/crypto/aes.h
32
@@ -XXX,XX +XXX,XX @@ void AES_decrypt(const unsigned char *in, unsigned char *out,
33
extern const uint8_t AES_sbox[256];
34
extern const uint8_t AES_isbox[256];
35
36
+/*
37
+AES_Te0[x] = S [x].[02, 01, 01, 03];
38
+AES_Td0[x] = Si[x].[0e, 09, 0d, 0b];
39
+*/
40
+
41
+extern const uint32_t AES_Te0[256], AES_Td0[256];
42
+
43
#endif
44
diff --git a/crypto/aes.c b/crypto/aes.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/crypto/aes.c
47
+++ b/crypto/aes.c
48
@@ -XXX,XX +XXX,XX @@ AES_Td3[x] = Si[x].[09, 0d, 0b, 0e];
49
AES_Td4[x] = Si[x].[01, 01, 01, 01];
50
*/
51
52
-static const uint32_t AES_Te0[256] = {
53
+const uint32_t AES_Te0[256] = {
54
0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
55
0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
56
0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
57
@@ -XXX,XX +XXX,XX @@ static const uint32_t AES_Te4[256] = {
58
0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
59
};
60
61
-static const uint32_t AES_Td0[256] = {
62
+const uint32_t AES_Td0[256] = {
63
0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
64
0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
65
0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
66
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/crypto_helper.c
69
+++ b/target/riscv/crypto_helper.c
13
@@ -XXX,XX +XXX,XX @@
70
@@ -XXX,XX +XXX,XX @@
14
#define HSTATUS32_WPRI 0xFF8FF87E
71
#include "crypto/aes-round.h"
15
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
72
#include "crypto/sm4.h"
16
73
17
-#if defined(TARGET_RISCV32)
74
-#define AES_XTIME(a) \
18
-#define HSTATUS_WPRI HSTATUS32_WPRI
75
- ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
19
-#elif defined(TARGET_RISCV64)
20
-#define HSTATUS_WPRI HSTATUS64_WPRI
21
-#endif
22
-
76
-
23
#define HCOUNTEREN_CY (1 << 0)
77
-#define AES_GFMUL(a, b) (( \
24
#define HCOUNTEREN_TM (1 << 1)
78
- (((b) & 0x1) ? (a) : 0) ^ \
25
#define HCOUNTEREN_IR (1 << 2)
79
- (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
80
- (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
81
- (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
82
-
83
-static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
84
-{
85
- uint32_t u;
86
-
87
- if (fwd) {
88
- u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
89
- (AES_GFMUL(x, 2) << 0);
90
- } else {
91
- u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
92
- (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
93
- }
94
- return u;
95
-}
96
-
97
#define sext32_xlen(x) (target_ulong)(int32_t)(x)
98
99
static inline target_ulong aes32_operation(target_ulong shamt,
100
@@ -XXX,XX +XXX,XX @@ static inline target_ulong aes32_operation(target_ulong shamt,
101
bool enc, bool mix)
102
{
103
uint8_t si = rs2 >> shamt;
104
- uint8_t so;
105
uint32_t mixed;
106
target_ulong res;
107
108
if (enc) {
109
- so = AES_sbox[si];
110
if (mix) {
111
- mixed = aes_mixcolumn_byte(so, true);
112
+ mixed = be32_to_cpu(AES_Te0[si]);
113
} else {
114
- mixed = so;
115
+ mixed = AES_sbox[si];
116
}
117
} else {
118
- so = AES_isbox[si];
119
if (mix) {
120
- mixed = aes_mixcolumn_byte(so, false);
121
+ mixed = be32_to_cpu(AES_Td0[si]);
122
} else {
123
- mixed = so;
124
+ mixed = AES_isbox[si];
125
}
126
}
127
mixed = rol32(mixed, shamt);
26
--
128
--
27
2.31.1
129
2.41.0
28
130
29
131
diff view generated by jsdifflib
[PULL 06/42] riscv: Add initial support for Shakti C machine
[PULL v2 08/45] target/riscv: Refactor some of the generic vector functionality
1
From: Vijai Kumar K <vijai@behindbytes.com>
1
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
2
2
3
Add support for emulating Shakti reference platform based on C-class
3
Take some functions/macros out of `vector_helper` and put them in a new
4
running on arty-100T board.
4
module called `vector_internals`. This ensures they can be used by both
5
vector and vector-crypto helpers (latter implemented in proceeding
6
commits).
5
7
6
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
8
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
7
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
10
Signed-off-by: Max Chou <max.chou@sifive.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
12
Message-ID: <20230711165917.2629866-2-max.chou@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
14
---
13
default-configs/devices/riscv64-softmmu.mak | 1 +
15
target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++
14
include/hw/riscv/shakti_c.h | 73 +++++++++
16
target/riscv/vector_helper.c | 201 +-------------------------------
15
hw/riscv/shakti_c.c | 170 ++++++++++++++++++++
17
target/riscv/vector_internals.c | 81 +++++++++++++
16
MAINTAINERS | 7 +
18
target/riscv/meson.build | 1 +
17
hw/riscv/Kconfig | 10 ++
19
4 files changed, 265 insertions(+), 200 deletions(-)
18
hw/riscv/meson.build | 1 +
20
create mode 100644 target/riscv/vector_internals.h
19
6 files changed, 262 insertions(+)
21
create mode 100644 target/riscv/vector_internals.c
20
create mode 100644 include/hw/riscv/shakti_c.h
21
create mode 100644 hw/riscv/shakti_c.c
22
22
23
diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
23
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/default-configs/devices/riscv64-softmmu.mak
26
+++ b/default-configs/devices/riscv64-softmmu.mak
27
@@ -XXX,XX +XXX,XX @@ CONFIG_SIFIVE_E=y
28
CONFIG_SIFIVE_U=y
29
CONFIG_RISCV_VIRT=y
30
CONFIG_MICROCHIP_PFSOC=y
31
+CONFIG_SHAKTI_C=y
32
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
33
new file mode 100644
24
new file mode 100644
34
index XXXXXXX..XXXXXXX
25
index XXXXXXX..XXXXXXX
35
--- /dev/null
26
--- /dev/null
36
+++ b/include/hw/riscv/shakti_c.h
27
+++ b/target/riscv/vector_internals.h
37
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
38
+/*
29
+/*
39
+ * Shakti C-class SoC emulation
30
+ * RISC-V Vector Extension Internals
40
+ *
31
+ *
41
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
32
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
42
+ *
33
+ *
43
+ * This program is free software; you can redistribute it and/or modify it
34
+ * This program is free software; you can redistribute it and/or modify it
44
+ * under the terms and conditions of the GNU General Public License,
35
+ * under the terms and conditions of the GNU General Public License,
45
+ * version 2 or later, as published by the Free Software Foundation.
36
+ * version 2 or later, as published by the Free Software Foundation.
46
+ *
37
+ *
...
...
51
+ *
42
+ *
52
+ * You should have received a copy of the GNU General Public License along with
43
+ * You should have received a copy of the GNU General Public License along with
53
+ * this program. If not, see <http://www.gnu.org/licenses/>.
44
+ * this program. If not, see <http://www.gnu.org/licenses/>.
54
+ */
45
+ */
55
+
46
+
56
+#ifndef HW_SHAKTI_H
47
+#ifndef TARGET_RISCV_VECTOR_INTERNALS_H
57
+#define HW_SHAKTI_H
48
+#define TARGET_RISCV_VECTOR_INTERNALS_H
58
+
49
+
59
+#include "hw/riscv/riscv_hart.h"
50
+#include "qemu/osdep.h"
60
+#include "hw/boards.h"
51
+#include "qemu/bitops.h"
61
+
52
+#include "cpu.h"
62
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
53
+#include "tcg/tcg-gvec-desc.h"
63
+#define RISCV_SHAKTI_SOC(obj) \
54
+#include "internals.h"
64
+ OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
55
+
65
+
56
+static inline uint32_t vext_nf(uint32_t desc)
66
+typedef struct ShaktiCSoCState {
57
+{
67
+ /*< private >*/
58
+ return FIELD_EX32(simd_data(desc), VDATA, NF);
68
+ DeviceState parent_obj;
59
+}
69
+
60
+
70
+ /*< public >*/
61
+/*
71
+ RISCVHartArrayState cpus;
62
+ * Note that vector data is stored in host-endian 64-bit chunks,
72
+ DeviceState *plic;
63
+ * so addressing units smaller than that needs a host-endian fixup.
73
+ MemoryRegion rom;
64
+ */
74
+
65
+#if HOST_BIG_ENDIAN
75
+} ShaktiCSoCState;
66
+#define H1(x) ((x) ^ 7)
76
+
67
+#define H1_2(x) ((x) ^ 6)
77
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
68
+#define H1_4(x) ((x) ^ 4)
78
+#define RISCV_SHAKTI_MACHINE(obj) \
69
+#define H2(x) ((x) ^ 3)
79
+ OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
70
+#define H4(x) ((x) ^ 1)
80
+typedef struct ShaktiCMachineState {
71
+#define H8(x) ((x))
81
+ /*< private >*/
72
+#else
82
+ MachineState parent_obj;
73
+#define H1(x) (x)
83
+
74
+#define H1_2(x) (x)
84
+ /*< public >*/
75
+#define H1_4(x) (x)
85
+ ShaktiCSoCState soc;
76
+#define H2(x) (x)
86
+} ShaktiCMachineState;
77
+#define H4(x) (x)
87
+
78
+#define H8(x) (x)
88
+enum {
89
+ SHAKTI_C_ROM,
90
+ SHAKTI_C_RAM,
91
+ SHAKTI_C_UART,
92
+ SHAKTI_C_GPIO,
93
+ SHAKTI_C_PLIC,
94
+ SHAKTI_C_CLINT,
95
+ SHAKTI_C_I2C,
96
+};
97
+
98
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
99
+/* Including Interrupt ID 0 (no interrupt)*/
100
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
101
+/* Excluding Priority 0 */
102
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
103
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
104
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
105
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
106
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
107
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
108
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
109
+
110
+#endif
79
+#endif
111
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
80
+
81
+/*
82
+ * Encode LMUL to lmul as following:
83
+ * LMUL vlmul lmul
84
+ * 1 000 0
85
+ * 2 001 1
86
+ * 4 010 2
87
+ * 8 011 3
88
+ * - 100 -
89
+ * 1/8 101 -3
90
+ * 1/4 110 -2
91
+ * 1/2 111 -1
92
+ */
93
+static inline int32_t vext_lmul(uint32_t desc)
94
+{
95
+ return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
96
+}
97
+
98
+static inline uint32_t vext_vm(uint32_t desc)
99
+{
100
+ return FIELD_EX32(simd_data(desc), VDATA, VM);
101
+}
102
+
103
+static inline uint32_t vext_vma(uint32_t desc)
104
+{
105
+ return FIELD_EX32(simd_data(desc), VDATA, VMA);
106
+}
107
+
108
+static inline uint32_t vext_vta(uint32_t desc)
109
+{
110
+ return FIELD_EX32(simd_data(desc), VDATA, VTA);
111
+}
112
+
113
+static inline uint32_t vext_vta_all_1s(uint32_t desc)
114
+{
115
+ return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
116
+}
117
+
118
+/*
119
+ * Earlier designs (pre-0.9) had a varying number of bits
120
+ * per mask value (MLEN). In the 0.9 design, MLEN=1.
121
+ * (Section 4.5)
122
+ */
123
+static inline int vext_elem_mask(void *v0, int index)
124
+{
125
+ int idx = index / 64;
126
+ int pos = index % 64;
127
+ return (((uint64_t *)v0)[idx] >> pos) & 1;
128
+}
129
+
130
+/*
131
+ * Get number of total elements, including prestart, body and tail elements.
132
+ * Note that when LMUL < 1, the tail includes the elements past VLMAX that
133
+ * are held in the same vector register.
134
+ */
135
+static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
136
+ uint32_t esz)
137
+{
138
+ uint32_t vlenb = simd_maxsz(desc);
139
+ uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
140
+ int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
141
+ ctzl(esz) - ctzl(sew) + vext_lmul(desc);
142
+ return (vlenb << emul) / esz;
143
+}
144
+
145
+/* set agnostic elements to 1s */
146
+void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
147
+ uint32_t tot);
148
+
149
+/* expand macro args before macro */
150
+#define RVVCALL(macro, ...) macro(__VA_ARGS__)
151
+
152
+/* (TD, T1, T2, TX1, TX2) */
153
+#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
154
+#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
155
+#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
156
+#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
157
+
158
+/* operation of two vector elements */
159
+typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
160
+
161
+#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
162
+static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
163
+{ \
164
+ TX1 s1 = *((T1 *)vs1 + HS1(i)); \
165
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
166
+ *((TD *)vd + HD(i)) = OP(s2, s1); \
167
+}
168
+
169
+void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
170
+ CPURISCVState *env, uint32_t desc,
171
+ opivv2_fn *fn, uint32_t esz);
172
+
173
+/* generate the helpers for OPIVV */
174
+#define GEN_VEXT_VV(NAME, ESZ) \
175
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
176
+ void *vs2, CPURISCVState *env, \
177
+ uint32_t desc) \
178
+{ \
179
+ do_vext_vv(vd, v0, vs1, vs2, env, desc, \
180
+ do_##NAME, ESZ); \
181
+}
182
+
183
+typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
184
+
185
+/*
186
+ * (T1)s1 gives the real operator type.
187
+ * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
188
+ */
189
+#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
190
+static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
191
+{ \
192
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
193
+ *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
194
+}
195
+
196
+void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
197
+ CPURISCVState *env, uint32_t desc,
198
+ opivx2_fn fn, uint32_t esz);
199
+
200
+/* generate the helpers for OPIVX */
201
+#define GEN_VEXT_VX(NAME, ESZ) \
202
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
203
+ void *vs2, CPURISCVState *env, \
204
+ uint32_t desc) \
205
+{ \
206
+ do_vext_vx(vd, v0, s1, vs2, env, desc, \
207
+ do_##NAME, ESZ); \
208
+}
209
+
210
+#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
211
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/riscv/vector_helper.c
214
+++ b/target/riscv/vector_helper.c
215
@@ -XXX,XX +XXX,XX @@
216
#include "fpu/softfloat.h"
217
#include "tcg/tcg-gvec-desc.h"
218
#include "internals.h"
219
+#include "vector_internals.h"
220
#include <math.h>
221
222
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
223
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
224
return vl;
225
}
226
227
-/*
228
- * Note that vector data is stored in host-endian 64-bit chunks,
229
- * so addressing units smaller than that needs a host-endian fixup.
230
- */
231
-#if HOST_BIG_ENDIAN
232
-#define H1(x) ((x) ^ 7)
233
-#define H1_2(x) ((x) ^ 6)
234
-#define H1_4(x) ((x) ^ 4)
235
-#define H2(x) ((x) ^ 3)
236
-#define H4(x) ((x) ^ 1)
237
-#define H8(x) ((x))
238
-#else
239
-#define H1(x) (x)
240
-#define H1_2(x) (x)
241
-#define H1_4(x) (x)
242
-#define H2(x) (x)
243
-#define H4(x) (x)
244
-#define H8(x) (x)
245
-#endif
246
-
247
-static inline uint32_t vext_nf(uint32_t desc)
248
-{
249
- return FIELD_EX32(simd_data(desc), VDATA, NF);
250
-}
251
-
252
-static inline uint32_t vext_vm(uint32_t desc)
253
-{
254
- return FIELD_EX32(simd_data(desc), VDATA, VM);
255
-}
256
-
257
-/*
258
- * Encode LMUL to lmul as following:
259
- * LMUL vlmul lmul
260
- * 1 000 0
261
- * 2 001 1
262
- * 4 010 2
263
- * 8 011 3
264
- * - 100 -
265
- * 1/8 101 -3
266
- * 1/4 110 -2
267
- * 1/2 111 -1
268
- */
269
-static inline int32_t vext_lmul(uint32_t desc)
270
-{
271
- return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
272
-}
273
-
274
-static inline uint32_t vext_vta(uint32_t desc)
275
-{
276
- return FIELD_EX32(simd_data(desc), VDATA, VTA);
277
-}
278
-
279
-static inline uint32_t vext_vma(uint32_t desc)
280
-{
281
- return FIELD_EX32(simd_data(desc), VDATA, VMA);
282
-}
283
-
284
-static inline uint32_t vext_vta_all_1s(uint32_t desc)
285
-{
286
- return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
287
-}
288
-
289
/*
290
* Get the maximum number of elements can be operated.
291
*
292
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
293
return scale < 0 ? vlenb >> -scale : vlenb << scale;
294
}
295
296
-/*
297
- * Get number of total elements, including prestart, body and tail elements.
298
- * Note that when LMUL < 1, the tail includes the elements past VLMAX that
299
- * are held in the same vector register.
300
- */
301
-static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
302
- uint32_t esz)
303
-{
304
- uint32_t vlenb = simd_maxsz(desc);
305
- uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
306
- int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
307
- ctzl(esz) - ctzl(sew) + vext_lmul(desc);
308
- return (vlenb << emul) / esz;
309
-}
310
-
311
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
312
{
313
return (addr & ~env->cur_pmmask) | env->cur_pmbase;
314
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
315
}
316
}
317
318
-/* set agnostic elements to 1s */
319
-static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
320
- uint32_t tot)
321
-{
322
- if (is_agnostic == 0) {
323
- /* policy undisturbed */
324
- return;
325
- }
326
- if (tot - cnt == 0) {
327
- return;
328
- }
329
- memset(base + cnt, -1, tot - cnt);
330
-}
331
-
332
static inline void vext_set_elem_mask(void *v0, int index,
333
uint8_t value)
334
{
335
@@ -XXX,XX +XXX,XX @@ static inline void vext_set_elem_mask(void *v0, int index,
336
((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
337
}
338
339
-/*
340
- * Earlier designs (pre-0.9) had a varying number of bits
341
- * per mask value (MLEN). In the 0.9 design, MLEN=1.
342
- * (Section 4.5)
343
- */
344
-static inline int vext_elem_mask(void *v0, int index)
345
-{
346
- int idx = index / 64;
347
- int pos = index % 64;
348
- return (((uint64_t *)v0)[idx] >> pos) & 1;
349
-}
350
-
351
/* elements operations for load and store */
352
typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr,
353
uint32_t idx, void *vd, uintptr_t retaddr);
354
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
355
* Vector Integer Arithmetic Instructions
356
*/
357
358
-/* expand macro args before macro */
359
-#define RVVCALL(macro, ...) macro(__VA_ARGS__)
360
-
361
/* (TD, T1, T2, TX1, TX2) */
362
#define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
363
#define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
364
#define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
365
#define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
366
-#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
367
-#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
368
-#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
369
-#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
370
#define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
371
#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
372
#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
373
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
374
#define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
375
#define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
376
377
-/* operation of two vector elements */
378
-typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
379
-
380
-#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
381
-static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
382
-{ \
383
- TX1 s1 = *((T1 *)vs1 + HS1(i)); \
384
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
385
- *((TD *)vd + HD(i)) = OP(s2, s1); \
386
-}
387
#define DO_SUB(N, M) (N - M)
388
#define DO_RSUB(N, M) (M - N)
389
390
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
391
RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
392
RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
393
394
-static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
395
- CPURISCVState *env, uint32_t desc,
396
- opivv2_fn *fn, uint32_t esz)
397
-{
398
- uint32_t vm = vext_vm(desc);
399
- uint32_t vl = env->vl;
400
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
401
- uint32_t vta = vext_vta(desc);
402
- uint32_t vma = vext_vma(desc);
403
- uint32_t i;
404
-
405
- for (i = env->vstart; i < vl; i++) {
406
- if (!vm && !vext_elem_mask(v0, i)) {
407
- /* set masked-off elements to 1s */
408
- vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
409
- continue;
410
- }
411
- fn(vd, vs1, vs2, i);
412
- }
413
- env->vstart = 0;
414
- /* set tail elements to 1s */
415
- vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
416
-}
417
-
418
-/* generate the helpers for OPIVV */
419
-#define GEN_VEXT_VV(NAME, ESZ) \
420
-void HELPER(NAME)(void *vd, void *v0, void *vs1, \
421
- void *vs2, CPURISCVState *env, \
422
- uint32_t desc) \
423
-{ \
424
- do_vext_vv(vd, v0, vs1, vs2, env, desc, \
425
- do_##NAME, ESZ); \
426
-}
427
-
428
GEN_VEXT_VV(vadd_vv_b, 1)
429
GEN_VEXT_VV(vadd_vv_h, 2)
430
GEN_VEXT_VV(vadd_vv_w, 4)
431
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VV(vsub_vv_h, 2)
432
GEN_VEXT_VV(vsub_vv_w, 4)
433
GEN_VEXT_VV(vsub_vv_d, 8)
434
435
-typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
436
-
437
-/*
438
- * (T1)s1 gives the real operator type.
439
- * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
440
- */
441
-#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
442
-static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
443
-{ \
444
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
445
- *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
446
-}
447
448
RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
449
RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
450
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
451
RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
452
RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
453
454
-static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
455
- CPURISCVState *env, uint32_t desc,
456
- opivx2_fn fn, uint32_t esz)
457
-{
458
- uint32_t vm = vext_vm(desc);
459
- uint32_t vl = env->vl;
460
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
461
- uint32_t vta = vext_vta(desc);
462
- uint32_t vma = vext_vma(desc);
463
- uint32_t i;
464
-
465
- for (i = env->vstart; i < vl; i++) {
466
- if (!vm && !vext_elem_mask(v0, i)) {
467
- /* set masked-off elements to 1s */
468
- vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
469
- continue;
470
- }
471
- fn(vd, s1, vs2, i);
472
- }
473
- env->vstart = 0;
474
- /* set tail elements to 1s */
475
- vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
476
-}
477
-
478
-/* generate the helpers for OPIVX */
479
-#define GEN_VEXT_VX(NAME, ESZ) \
480
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
481
- void *vs2, CPURISCVState *env, \
482
- uint32_t desc) \
483
-{ \
484
- do_vext_vx(vd, v0, s1, vs2, env, desc, \
485
- do_##NAME, ESZ); \
486
-}
487
-
488
GEN_VEXT_VX(vadd_vx_b, 1)
489
GEN_VEXT_VX(vadd_vx_h, 2)
490
GEN_VEXT_VX(vadd_vx_w, 4)
491
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
112
new file mode 100644
492
new file mode 100644
113
index XXXXXXX..XXXXXXX
493
index XXXXXXX..XXXXXXX
114
--- /dev/null
494
--- /dev/null
115
+++ b/hw/riscv/shakti_c.c
495
+++ b/target/riscv/vector_internals.c
116
@@ -XXX,XX +XXX,XX @@
496
@@ -XXX,XX +XXX,XX @@
117
+/*
497
+/*
118
+ * Shakti C-class SoC emulation
498
+ * RISC-V Vector Extension Internals
119
+ *
499
+ *
120
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
500
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
121
+ *
501
+ *
122
+ * This program is free software; you can redistribute it and/or modify it
502
+ * This program is free software; you can redistribute it and/or modify it
123
+ * under the terms and conditions of the GNU General Public License,
503
+ * under the terms and conditions of the GNU General Public License,
124
+ * version 2 or later, as published by the Free Software Foundation.
504
+ * version 2 or later, as published by the Free Software Foundation.
125
+ *
505
+ *
...
...
130
+ *
510
+ *
131
+ * You should have received a copy of the GNU General Public License along with
511
+ * You should have received a copy of the GNU General Public License along with
132
+ * this program. If not, see <http://www.gnu.org/licenses/>.
512
+ * this program. If not, see <http://www.gnu.org/licenses/>.
133
+ */
513
+ */
134
+
514
+
135
+#include "qemu/osdep.h"
515
+#include "vector_internals.h"
136
+#include "hw/boards.h"
516
+
137
+#include "hw/riscv/shakti_c.h"
517
+/* set agnostic elements to 1s */
138
+#include "qapi/error.h"
518
+void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
139
+#include "hw/intc/sifive_plic.h"
519
+ uint32_t tot)
140
+#include "hw/intc/sifive_clint.h"
520
+{
141
+#include "sysemu/sysemu.h"
521
+ if (is_agnostic == 0) {
142
+#include "hw/qdev-properties.h"
522
+ /* policy undisturbed */
143
+#include "exec/address-spaces.h"
523
+ return;
144
+#include "hw/riscv/boot.h"
145
+
146
+
147
+static const struct MemmapEntry {
148
+ hwaddr base;
149
+ hwaddr size;
150
+} shakti_c_memmap[] = {
151
+ [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
152
+ [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
153
+ [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
154
+ [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
155
+ [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
156
+ [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
157
+ [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
158
+};
159
+
160
+static void shakti_c_machine_state_init(MachineState *mstate)
161
+{
162
+ ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
163
+ MemoryRegion *system_memory = get_system_memory();
164
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
165
+
166
+ /* Allow only Shakti C CPU for this platform */
167
+ if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
168
+ error_report("This board can only be used with Shakti C CPU");
169
+ exit(1);
170
+ }
524
+ }
171
+
525
+ if (tot - cnt == 0) {
172
+ /* Initialize SoC */
526
+ return ;
173
+ object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
527
+ }
174
+ TYPE_RISCV_SHAKTI_SOC);
528
+ memset(base + cnt, -1, tot - cnt);
175
+ qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
529
+}
176
+
530
+
177
+ /* register RAM */
531
+void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
178
+ memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
532
+ CPURISCVState *env, uint32_t desc,
179
+ mstate->ram_size, &error_fatal);
533
+ opivv2_fn *fn, uint32_t esz)
180
+ memory_region_add_subregion(system_memory,
534
+{
181
+ shakti_c_memmap[SHAKTI_C_RAM].base,
535
+ uint32_t vm = vext_vm(desc);
182
+ main_mem);
536
+ uint32_t vl = env->vl;
183
+
537
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
184
+ /* ROM reset vector */
538
+ uint32_t vta = vext_vta(desc);
185
+ riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
539
+ uint32_t vma = vext_vma(desc);
186
+ shakti_c_memmap[SHAKTI_C_RAM].base,
540
+ uint32_t i;
187
+ shakti_c_memmap[SHAKTI_C_ROM].base,
541
+
188
+ shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
542
+ for (i = env->vstart; i < vl; i++) {
189
+ NULL);
543
+ if (!vm && !vext_elem_mask(v0, i)) {
190
+ riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
544
+ /* set masked-off elements to 1s */
191
+ NULL);
545
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
192
+}
546
+ continue;
193
+
547
+ }
194
+static void shakti_c_machine_instance_init(Object *obj)
548
+ fn(vd, vs1, vs2, i);
195
+{
549
+ }
196
+}
550
+ env->vstart = 0;
197
+
551
+ /* set tail elements to 1s */
198
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
552
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
199
+{
553
+}
200
+ MachineClass *mc = MACHINE_CLASS(klass);
554
+
201
+ mc->desc = "RISC-V Board compatible with Shakti SDK";
555
+void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
202
+ mc->init = shakti_c_machine_state_init;
556
+ CPURISCVState *env, uint32_t desc,
203
+ mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
557
+ opivx2_fn fn, uint32_t esz)
204
+}
558
+{
205
+
559
+ uint32_t vm = vext_vm(desc);
206
+static const TypeInfo shakti_c_machine_type_info = {
560
+ uint32_t vl = env->vl;
207
+ .name = TYPE_RISCV_SHAKTI_MACHINE,
561
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
208
+ .parent = TYPE_MACHINE,
562
+ uint32_t vta = vext_vta(desc);
209
+ .class_init = shakti_c_machine_class_init,
563
+ uint32_t vma = vext_vma(desc);
210
+ .instance_init = shakti_c_machine_instance_init,
564
+ uint32_t i;
211
+ .instance_size = sizeof(ShaktiCMachineState),
565
+
212
+};
566
+ for (i = env->vstart; i < vl; i++) {
213
+
567
+ if (!vm && !vext_elem_mask(v0, i)) {
214
+static void shakti_c_machine_type_info_register(void)
568
+ /* set masked-off elements to 1s */
215
+{
569
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
216
+ type_register_static(&shakti_c_machine_type_info);
570
+ continue;
217
+}
571
+ }
218
+type_init(shakti_c_machine_type_info_register)
572
+ fn(vd, s1, vs2, i);
219
+
573
+ }
220
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
574
+ env->vstart = 0;
221
+{
575
+ /* set tail elements to 1s */
222
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
576
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
223
+ MemoryRegion *system_memory = get_system_memory();
577
+}
224
+
578
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
225
+ sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
226
+
227
+ sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
228
+ (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
229
+ SHAKTI_C_PLIC_NUM_SOURCES,
230
+ SHAKTI_C_PLIC_NUM_PRIORITIES,
231
+ SHAKTI_C_PLIC_PRIORITY_BASE,
232
+ SHAKTI_C_PLIC_PENDING_BASE,
233
+ SHAKTI_C_PLIC_ENABLE_BASE,
234
+ SHAKTI_C_PLIC_ENABLE_STRIDE,
235
+ SHAKTI_C_PLIC_CONTEXT_BASE,
236
+ SHAKTI_C_PLIC_CONTEXT_STRIDE,
237
+ shakti_c_memmap[SHAKTI_C_PLIC].size);
238
+
239
+ sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
240
+ shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
241
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
242
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
243
+
244
+ /* ROM */
245
+ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
246
+ shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
247
+ memory_region_add_subregion(system_memory,
248
+ shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
249
+}
250
+
251
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
252
+{
253
+ DeviceClass *dc = DEVICE_CLASS(klass);
254
+ dc->realize = shakti_c_soc_state_realize;
255
+}
256
+
257
+static void shakti_c_soc_instance_init(Object *obj)
258
+{
259
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
260
+
261
+ object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
262
+
263
+ /*
264
+ * CPU type is fixed and we are not supporting passing from commandline yet.
265
+ * So let it be in instance_init. When supported should use ms->cpu_type
266
+ * instead of TYPE_RISCV_CPU_SHAKTI_C
267
+ */
268
+ object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
269
+ TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
270
+ object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
271
+ &error_abort);
272
+}
273
+
274
+static const TypeInfo shakti_c_type_info = {
275
+ .name = TYPE_RISCV_SHAKTI_SOC,
276
+ .parent = TYPE_DEVICE,
277
+ .class_init = shakti_c_soc_class_init,
278
+ .instance_init = shakti_c_soc_instance_init,
279
+ .instance_size = sizeof(ShaktiCSoCState),
280
+};
281
+
282
+static void shakti_c_type_info_register(void)
283
+{
284
+ type_register_static(&shakti_c_type_info);
285
+}
286
+type_init(shakti_c_type_info_register)
287
diff --git a/MAINTAINERS b/MAINTAINERS
288
index XXXXXXX..XXXXXXX 100644
579
index XXXXXXX..XXXXXXX 100644
289
--- a/MAINTAINERS
580
--- a/target/riscv/meson.build
290
+++ b/MAINTAINERS
581
+++ b/target/riscv/meson.build
291
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_dmc.h
582
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
292
F: include/hw/misc/mchp_pfsoc_ioscb.h
583
'gdbstub.c',
293
F: include/hw/misc/mchp_pfsoc_sysreg.h
584
'op_helper.c',
294
585
'vector_helper.c',
295
+Shakti C class SoC
586
+ 'vector_internals.c',
296
+M: Vijai Kumar K <vijai@behindbytes.com>
587
'bitmanip_helper.c',
297
+L: qemu-riscv@nongnu.org
588
'translate.c',
298
+S: Supported
589
'm128_helper.c',
299
+F: hw/riscv/shakti_c.c
300
+F: include/hw/riscv/shakti_c.h
301
+
302
SiFive Machines
303
M: Alistair Francis <Alistair.Francis@wdc.com>
304
M: Bin Meng <bin.meng@windriver.com>
305
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
306
index XXXXXXX..XXXXXXX 100644
307
--- a/hw/riscv/Kconfig
308
+++ b/hw/riscv/Kconfig
309
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
310
select IBEX
311
select UNIMP
312
313
+config SHAKTI
314
+ bool
315
+
316
+config SHAKTI_C
317
+ bool
318
+ select UNIMP
319
+ select SHAKTI
320
+ select SIFIVE_CLINT
321
+ select SIFIVE_PLIC
322
+
323
config RISCV_VIRT
324
bool
325
imply PCI_DEVICES
326
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
327
index XXXXXXX..XXXXXXX 100644
328
--- a/hw/riscv/meson.build
329
+++ b/hw/riscv/meson.build
330
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
331
riscv_ss.add(files('riscv_hart.c'))
332
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
333
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
334
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
335
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
336
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
337
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
338
--
590
--
339
2.31.1
591
2.41.0
340
341
diff view generated by jsdifflib
New patch
[PULL v2 09/45] target/riscv: Refactor vector-vector translation macro
1
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
1
2
3
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
4
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
5
used in proceeding vector-crypto commits.
6
7
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
16
1 file changed, 32 insertions(+), 30 deletions(-)
17
18
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn_trans/trans_rvv.c.inc
21
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
22
@@ -XXX,XX +XXX,XX @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
23
GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
24
GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
25
26
+static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
27
+ gen_helper_gvec_4_ptr *fn, DisasContext *s)
28
+{
29
+ uint32_t data = 0;
30
+ TCGLabel *over = gen_new_label();
31
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
32
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
33
+
34
+ data = FIELD_DP32(data, VDATA, VM, vm);
35
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
36
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
37
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
38
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
39
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
40
+ vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
41
+ s->cfg_ptr->vlen / 8, data, fn);
42
+ mark_vs_dirty(s);
43
+ gen_set_label(over);
44
+ return true;
45
+}
46
+
47
/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
48
/* OPIVV without GVEC IR */
49
-#define GEN_OPIVV_TRANS(NAME, CHECK) \
50
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
51
-{ \
52
- if (CHECK(s, a)) { \
53
- uint32_t data = 0; \
54
- static gen_helper_gvec_4_ptr * const fns[4] = { \
55
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
56
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
57
- }; \
58
- TCGLabel *over = gen_new_label(); \
59
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
60
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
61
- \
62
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
63
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
64
- data = FIELD_DP32(data, VDATA, VTA, s->vta); \
65
- data = \
66
- FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
67
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
68
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
69
- vreg_ofs(s, a->rs1), \
70
- vreg_ofs(s, a->rs2), cpu_env, \
71
- s->cfg_ptr->vlen / 8, \
72
- s->cfg_ptr->vlen / 8, data, \
73
- fns[s->sew]); \
74
- mark_vs_dirty(s); \
75
- gen_set_label(over); \
76
- return true; \
77
- } \
78
- return false; \
79
+#define GEN_OPIVV_TRANS(NAME, CHECK) \
80
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
81
+{ \
82
+ if (CHECK(s, a)) { \
83
+ static gen_helper_gvec_4_ptr * const fns[4] = { \
84
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
85
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
86
+ }; \
87
+ return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
88
+ } \
89
+ return false; \
90
}
91
92
/*
93
--
94
2.41.0
diff view generated by jsdifflib
New patch
[PULL v2 10/45] target/riscv: Remove redundant "cpu_vl == 0" checks
1
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
1
2
3
Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0.
4
5
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
6
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20230711165917.2629866-4-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------
13
1 file changed, 1 insertion(+), 30 deletions(-)
14
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
20
TCGv_i32 desc;
21
22
TCGLabel *over = gen_new_label();
23
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
24
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
25
26
dest = tcg_temp_new_ptr();
27
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
28
TCGv_i32 desc;
29
30
TCGLabel *over = gen_new_label();
31
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
32
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
33
34
dest = tcg_temp_new_ptr();
35
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
36
TCGv_i32 desc;
37
38
TCGLabel *over = gen_new_label();
39
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
40
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
41
42
dest = tcg_temp_new_ptr();
43
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
44
TCGv_i32 desc;
45
46
TCGLabel *over = gen_new_label();
47
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
48
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
49
50
dest = tcg_temp_new_ptr();
51
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
52
return false;
53
}
54
55
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
56
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
57
58
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
59
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
60
uint32_t data = 0;
61
62
TCGLabel *over = gen_new_label();
63
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
64
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
65
66
dest = tcg_temp_new_ptr();
67
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
68
uint32_t data = 0;
69
70
TCGLabel *over = gen_new_label();
71
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
72
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
73
74
dest = tcg_temp_new_ptr();
75
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
76
if (checkfn(s, a)) {
77
uint32_t data = 0;
78
TCGLabel *over = gen_new_label();
79
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
80
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
81
82
data = FIELD_DP32(data, VDATA, VM, a->vm);
83
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
84
if (opiwv_widen_check(s, a)) {
85
uint32_t data = 0;
86
TCGLabel *over = gen_new_label();
87
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
88
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
89
90
data = FIELD_DP32(data, VDATA, VM, a->vm);
91
@@ -XXX,XX +XXX,XX @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
92
{
93
uint32_t data = 0;
94
TCGLabel *over = gen_new_label();
95
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
96
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
97
98
data = FIELD_DP32(data, VDATA, VM, vm);
99
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
100
gen_helper_##NAME##_w, \
101
}; \
102
TCGLabel *over = gen_new_label(); \
103
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
104
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
105
\
106
data = FIELD_DP32(data, VDATA, VM, a->vm); \
107
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
108
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
109
};
110
TCGLabel *over = gen_new_label();
111
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
112
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
113
114
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
115
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
116
vext_check_ss(s, a->rd, 0, 1)) {
117
TCGv s1;
118
TCGLabel *over = gen_new_label();
119
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
120
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
121
122
s1 = get_gpr(s, a->rs1, EXT_SIGN);
123
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
124
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
125
};
126
TCGLabel *over = gen_new_label();
127
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
128
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
129
130
s1 = tcg_constant_i64(simm);
131
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
132
}; \
133
TCGLabel *over = gen_new_label(); \
134
gen_set_rm(s, RISCV_FRM_DYN); \
135
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
136
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
137
\
138
data = FIELD_DP32(data, VDATA, VM, a->vm); \
139
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
140
TCGv_i64 t1;
141
142
TCGLabel *over = gen_new_label();
143
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
144
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
145
146
dest = tcg_temp_new_ptr();
147
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
148
}; \
149
TCGLabel *over = gen_new_label(); \
150
gen_set_rm(s, RISCV_FRM_DYN); \
151
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
152
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
153
\
154
data = FIELD_DP32(data, VDATA, VM, a->vm); \
155
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
156
}; \
157
TCGLabel *over = gen_new_label(); \
158
gen_set_rm(s, RISCV_FRM_DYN); \
159
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
160
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
161
\
162
data = FIELD_DP32(data, VDATA, VM, a->vm); \
163
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
164
uint32_t data = 0;
165
TCGLabel *over = gen_new_label();
166
gen_set_rm_chkfrm(s, rm);
167
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
168
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
169
170
data = FIELD_DP32(data, VDATA, VM, a->vm);
171
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
172
gen_helper_vmv_v_x_d,
173
};
174
TCGLabel *over = gen_new_label();
175
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
176
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
177
178
t1 = tcg_temp_new_i64();
179
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
180
}; \
181
TCGLabel *over = gen_new_label(); \
182
gen_set_rm_chkfrm(s, FRM); \
183
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
184
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
185
\
186
data = FIELD_DP32(data, VDATA, VM, a->vm); \
187
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
188
}; \
189
TCGLabel *over = gen_new_label(); \
190
gen_set_rm(s, RISCV_FRM_DYN); \
191
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
192
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
193
\
194
data = FIELD_DP32(data, VDATA, VM, a->vm); \
195
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
196
}; \
197
TCGLabel *over = gen_new_label(); \
198
gen_set_rm_chkfrm(s, FRM); \
199
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
200
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
201
\
202
data = FIELD_DP32(data, VDATA, VM, a->vm); \
203
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
204
}; \
205
TCGLabel *over = gen_new_label(); \
206
gen_set_rm_chkfrm(s, FRM); \
207
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
208
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
209
\
210
data = FIELD_DP32(data, VDATA, VM, a->vm); \
211
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
212
uint32_t data = 0; \
213
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
214
TCGLabel *over = gen_new_label(); \
215
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
216
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
217
\
218
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
219
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
220
require_vm(a->vm, a->rd)) {
221
uint32_t data = 0;
222
TCGLabel *over = gen_new_label();
223
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
224
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
225
226
data = FIELD_DP32(data, VDATA, VM, a->vm);
227
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
228
TCGv s1;
229
TCGLabel *over = gen_new_label();
230
231
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
232
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
233
234
t1 = tcg_temp_new_i64();
235
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
236
TCGv_i64 t1;
237
TCGLabel *over = gen_new_label();
238
239
- /* if vl == 0 or vstart >= vl, skip vector register write back */
240
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
241
+ /* if vstart >= vl, skip vector register write back */
242
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
243
244
/* NaN-box f[rs1] */
245
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
246
uint32_t data = 0;
247
gen_helper_gvec_3_ptr *fn;
248
TCGLabel *over = gen_new_label();
249
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
250
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
251
252
static gen_helper_gvec_3_ptr * const fns[6][4] = {
253
--
254
2.41.0
diff view generated by jsdifflib
[PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions
[PULL v2 11/45] target/riscv: Add Zvbc ISA extension support
1
This patch removes the insn32-64.decode decode file and consolidates the
1
From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
2
instructions into the general RISC-V insn32.decode decode tree.
2
3
3
This commit adds support for the Zvbc vector-crypto extension, which
4
This means that all of the instructions are avaliable in both the 32-bit
4
consists of the following instructions:
5
and 64-bit builds. This also means that we run a check to ensure we are
5
6
running a 64-bit softmmu before we execute the 64-bit only instructions.
6
* vclmulh.[vx,vv]
7
This allows us to include the 32-bit instructions in the 64-bit build,
7
* vclmul.[vx,vv]
8
while also ensuring that 32-bit only software can not execute the
8
9
instructions.
9
Translation functions are defined in
10
10
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
11
`target/riscv/vcrypto_helper.c`.
12
13
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
14
Co-authored-by: Max Chou <max.chou@sifive.com>
15
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
16
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
17
Signed-off-by: Max Chou <max.chou@sifive.com>
18
[max.chou@sifive.com: Exposed x-zvbc property]
19
Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
14
---
21
---
15
target/riscv/helper.h | 18 +++--
22
target/riscv/cpu_cfg.h | 1 +
16
target/riscv/insn32-64.decode | 88 -------------------------
23
target/riscv/helper.h | 6 +++
17
target/riscv/insn32.decode | 67 ++++++++++++++++++-
24
target/riscv/insn32.decode | 6 +++
18
target/riscv/fpu_helper.c | 16 ++---
25
target/riscv/cpu.c | 9 ++++
19
target/riscv/translate.c | 9 ++-
26
target/riscv/translate.c | 1 +
20
target/riscv/vector_helper.c | 4 --
27
target/riscv/vcrypto_helper.c | 59 ++++++++++++++++++++++
21
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
28
target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++
22
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
29
target/riscv/meson.build | 3 +-
23
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
30
8 files changed, 146 insertions(+), 1 deletion(-)
24
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
31
create mode 100644 target/riscv/vcrypto_helper.c
25
target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
32
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
26
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
33
27
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
34
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
28
target/riscv/meson.build | 2 +-
35
index XXXXXXX..XXXXXXX 100644
29
14 files changed, 166 insertions(+), 150 deletions(-)
36
--- a/target/riscv/cpu_cfg.h
30
delete mode 100644 target/riscv/insn32-64.decode
37
+++ b/target/riscv/cpu_cfg.h
31
38
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
39
bool ext_zve32f;
40
bool ext_zve64f;
41
bool ext_zve64d;
42
+ bool ext_zvbc;
43
bool ext_zmmul;
44
bool ext_zvfbfmin;
45
bool ext_zvfbfwma;
32
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
46
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
33
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/helper.h
48
--- a/target/riscv/helper.h
35
+++ b/target/riscv/helper.h
49
+++ b/target/riscv/helper.h
36
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
50
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
37
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
51
38
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
52
DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32)
39
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
53
DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32)
40
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
54
+
41
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
55
+/* Vector crypto functions */
42
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
56
+DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
43
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
57
+DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
44
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
58
+DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
45
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
59
+DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
46
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
47
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
48
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
49
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
50
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
51
52
/* Floating Point - Double Precision */
53
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
54
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
55
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
56
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
57
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
58
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
59
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
60
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
61
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
62
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
63
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
64
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
65
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
66
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
67
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
68
69
/* Special functions */
70
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
71
DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
72
DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
73
DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
74
-#ifdef TARGET_RISCV64
75
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
76
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
77
DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
78
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
79
DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
80
DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
81
DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
82
-#endif
83
DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
84
DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
85
DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
86
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
87
deleted file mode 100644
88
index XXXXXXX..XXXXXXX
89
--- a/target/riscv/insn32-64.decode
90
+++ /dev/null
91
@@ -XXX,XX +XXX,XX @@
92
-#
93
-# RISC-V translation routines for the RV Instruction Set.
94
-#
95
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
96
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
97
-#
98
-# This program is free software; you can redistribute it and/or modify it
99
-# under the terms and conditions of the GNU General Public License,
100
-# version 2 or later, as published by the Free Software Foundation.
101
-#
102
-# This program is distributed in the hope it will be useful, but WITHOUT
103
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
104
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
105
-# more details.
106
-#
107
-# You should have received a copy of the GNU General Public License along with
108
-# this program. If not, see <http://www.gnu.org/licenses/>.
109
-
110
-# This is concatenated with insn32.decode for risc64 targets.
111
-# Most of the fields and formats are there.
112
-
113
-%sh5 20:5
114
-
115
-@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
116
-
117
-# *** RV64I Base Instruction Set (in addition to RV32I) ***
118
-lwu ............ ..... 110 ..... 0000011 @i
119
-ld ............ ..... 011 ..... 0000011 @i
120
-sd ....... ..... ..... 011 ..... 0100011 @s
121
-addiw ............ ..... 000 ..... 0011011 @i
122
-slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
123
-srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
124
-sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
125
-addw 0000000 ..... ..... 000 ..... 0111011 @r
126
-subw 0100000 ..... ..... 000 ..... 0111011 @r
127
-sllw 0000000 ..... ..... 001 ..... 0111011 @r
128
-srlw 0000000 ..... ..... 101 ..... 0111011 @r
129
-sraw 0100000 ..... ..... 101 ..... 0111011 @r
130
-
131
-# *** RV64M Standard Extension (in addition to RV32M) ***
132
-mulw 0000001 ..... ..... 000 ..... 0111011 @r
133
-divw 0000001 ..... ..... 100 ..... 0111011 @r
134
-divuw 0000001 ..... ..... 101 ..... 0111011 @r
135
-remw 0000001 ..... ..... 110 ..... 0111011 @r
136
-remuw 0000001 ..... ..... 111 ..... 0111011 @r
137
-
138
-# *** RV64A Standard Extension (in addition to RV32A) ***
139
-lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
140
-sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
141
-amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
142
-amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
143
-amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
144
-amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
145
-amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
146
-amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
147
-amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
148
-amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
149
-amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
150
-
151
-#*** Vector AMO operations (in addition to Zvamo) ***
152
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
153
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
154
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
155
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
156
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
157
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
158
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
159
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
160
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
161
-
162
-# *** RV64F Standard Extension (in addition to RV32F) ***
163
-fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
164
-fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
165
-fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
166
-fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
167
-
168
-# *** RV64D Standard Extension (in addition to RV32D) ***
169
-fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
170
-fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
171
-fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
172
-fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
173
-fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
174
-fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
175
-
176
-# *** RV32H Base Instruction Set ***
177
-hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
178
-hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
179
-hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
180
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
60
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
181
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
182
--- a/target/riscv/insn32.decode
62
--- a/target/riscv/insn32.decode
183
+++ b/target/riscv/insn32.decode
63
+++ b/target/riscv/insn32.decode
184
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
185
%rs2 20:5
65
# *** Zvfbfwma Standard Extension ***
186
%rs1 15:5
66
vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm
187
%rd 7:5
67
vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm
188
+%sh5 20:5
68
+
189
69
+# *** Zvbc vector crypto extension ***
190
%sh10 20:10
70
+vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
191
%csr 20:12
71
+vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
192
@@ -XXX,XX +XXX,XX @@
72
+vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
193
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
73
+vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
194
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
74
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
195
75
index XXXXXXX..XXXXXXX 100644
196
+# Formats 64:
76
--- a/target/riscv/cpu.c
197
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
77
+++ b/target/riscv/cpu.c
198
78
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
199
# *** Privileged Instructions ***
79
ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
200
ecall 000000000000 00000 000 00000 1110011
80
ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
201
@@ -XXX,XX +XXX,XX @@ csrrwi ............ ..... 101 ..... 1110011 @csr
81
ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
202
csrrsi ............ ..... 110 ..... 1110011 @csr
82
+ ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
203
csrrci ............ ..... 111 ..... 1110011 @csr
83
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
204
84
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
205
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
85
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
206
+lwu ............ ..... 110 ..... 0000011 @i
86
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
207
+ld ............ ..... 011 ..... 0000011 @i
87
return;
208
+sd ....... ..... ..... 011 ..... 0100011 @s
88
}
209
+addiw ............ ..... 000 ..... 0011011 @i
89
210
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
90
+ if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
211
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
91
+ error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
212
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
92
+ return;
213
+addw 0000000 ..... ..... 000 ..... 0111011 @r
93
+ }
214
+subw 0100000 ..... ..... 000 ..... 0111011 @r
94
+
215
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
95
if (cpu->cfg.ext_zk) {
216
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
96
cpu->cfg.ext_zkn = true;
217
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
97
cpu->cfg.ext_zkr = true;
218
+
98
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
219
# *** RV32M Standard Extension ***
99
DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
220
mul 0000001 ..... ..... 000 ..... 0110011 @r
100
DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
221
mulh 0000001 ..... ..... 001 ..... 0110011 @r
101
222
@@ -XXX,XX +XXX,XX @@ divu 0000001 ..... ..... 101 ..... 0110011 @r
102
+ /* Vector cryptography extensions */
223
rem 0000001 ..... ..... 110 ..... 0110011 @r
103
+ DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
224
remu 0000001 ..... ..... 111 ..... 0110011 @r
104
+
225
105
DEFINE_PROP_END_OF_LIST(),
226
+# *** RV64M Standard Extension (in addition to RV32M) ***
106
};
227
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
107
228
+divw 0000001 ..... ..... 100 ..... 0111011 @r
229
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
230
+remw 0000001 ..... ..... 110 ..... 0111011 @r
231
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
232
+
233
# *** RV32A Standard Extension ***
234
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
235
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
236
@@ -XXX,XX +XXX,XX @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
237
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
238
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
239
240
+# *** RV64A Standard Extension (in addition to RV32A) ***
241
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
242
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
243
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
244
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
245
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
246
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
247
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
248
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
249
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
250
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
251
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
252
+
253
# *** RV32F Standard Extension ***
254
flw ............ ..... 010 ..... 0000111 @i
255
fsw ....... ..... ..... 010 ..... 0100111 @s
256
@@ -XXX,XX +XXX,XX @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
257
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
258
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
259
260
+# *** RV64F Standard Extension (in addition to RV32F) ***
261
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
262
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
263
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
264
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
265
+
266
# *** RV32D Standard Extension ***
267
fld ............ ..... 011 ..... 0000111 @i
268
fsd ....... ..... ..... 011 ..... 0100111 @s
269
@@ -XXX,XX +XXX,XX @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
270
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
271
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
272
273
+# *** RV64D Standard Extension (in addition to RV32D) ***
274
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
275
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
276
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
277
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
278
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
279
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
280
+
281
# *** RV32H Base Instruction Set ***
282
hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
283
hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
284
@@ -XXX,XX +XXX,XX @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
285
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
286
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
287
288
-# *** RV32V Extension ***
289
+# *** RV32H Base Instruction Set ***
290
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
291
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
292
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
293
294
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
295
vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
296
@@ -XXX,XX +XXX,XX @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
297
298
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
299
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
300
+
301
+#*** Vector AMO operations (in addition to Zvamo) ***
302
+vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
303
+vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
304
+vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
305
+vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
306
+vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
307
+vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
308
+vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
309
+vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
310
+vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
311
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
312
index XXXXXXX..XXXXXXX 100644
313
--- a/target/riscv/fpu_helper.c
314
+++ b/target/riscv/fpu_helper.c
315
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
316
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
317
}
318
319
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
320
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
321
{
322
float32 frs1 = check_nanbox_s(rs1);
323
return float32_to_int64(frs1, &env->fp_status);
324
}
325
326
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
327
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
328
{
329
float32 frs1 = check_nanbox_s(rs1);
330
return float32_to_uint64(frs1, &env->fp_status);
331
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
332
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
333
}
334
335
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
336
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
337
{
338
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
339
}
340
341
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
342
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
343
{
344
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
345
}
346
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
347
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
348
}
349
350
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
351
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
352
{
353
return float64_to_int64(frs1, &env->fp_status);
354
}
355
356
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
357
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
358
{
359
return float64_to_uint64(frs1, &env->fp_status);
360
}
361
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
362
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
363
}
364
365
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
366
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
367
{
368
return int64_to_float64(rs1, &env->fp_status);
369
}
370
371
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
372
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
373
{
374
return uint64_to_float64(rs1, &env->fp_status);
375
}
376
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
108
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
377
index XXXXXXX..XXXXXXX 100644
109
index XXXXXXX..XXXXXXX 100644
378
--- a/target/riscv/translate.c
110
--- a/target/riscv/translate.c
379
+++ b/target/riscv/translate.c
111
+++ b/target/riscv/translate.c
380
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
112
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
381
} \
113
#include "insn_trans/trans_rvzfa.c.inc"
382
} while (0)
114
#include "insn_trans/trans_rvzfh.c.inc"
383
115
#include "insn_trans/trans_rvk.c.inc"
384
+#define REQUIRE_64BIT(ctx) do { \
116
+#include "insn_trans/trans_rvvk.c.inc"
385
+ if (is_32bit(ctx)) { \
117
#include "insn_trans/trans_privileged.c.inc"
386
+ return false; \
118
#include "insn_trans/trans_svinval.c.inc"
387
+ } \
119
#include "insn_trans/trans_rvbf16.c.inc"
388
+} while (0)
120
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
389
+
121
new file mode 100644
390
static int ex_rvc_register(DisasContext *ctx, int reg)
122
index XXXXXXX..XXXXXXX
391
{
123
--- /dev/null
392
return 8 + reg;
124
+++ b/target/riscv/vcrypto_helper.c
393
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
125
@@ -XXX,XX +XXX,XX @@
394
return true;
126
+/*
395
}
127
+ * RISC-V Vector Crypto Extension Helpers for QEMU.
396
128
+ *
397
-#ifdef TARGET_RISCV64
129
+ * Copyright (C) 2023 SiFive, Inc.
398
static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
130
+ * Written by Codethink Ltd and SiFive.
399
{
131
+ *
400
tcg_gen_add_tl(ret, arg1, arg2);
132
+ * This program is free software; you can redistribute it and/or modify it
401
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
133
+ * under the terms and conditions of the GNU General Public License,
402
return true;
134
+ * version 2 or later, as published by the Free Software Foundation.
403
}
135
+ *
404
136
+ * This program is distributed in the hope it will be useful, but WITHOUT
405
-#endif
137
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
406
-
138
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
407
static bool gen_arith(DisasContext *ctx, arg_r *a,
139
+ * more details.
408
void(*func)(TCGv, TCGv, TCGv))
140
+ *
409
{
141
+ * You should have received a copy of the GNU General Public License along with
410
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
142
+ * this program. If not, see <http://www.gnu.org/licenses/>.
411
index XXXXXXX..XXXXXXX 100644
143
+ */
412
--- a/target/riscv/vector_helper.c
144
+
413
+++ b/target/riscv/vector_helper.c
145
+#include "qemu/osdep.h"
414
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
146
+#include "qemu/host-utils.h"
415
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
147
+#include "qemu/bitops.h"
416
GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
148
+#include "cpu.h"
417
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
149
+#include "exec/memop.h"
418
-#ifdef TARGET_RISCV64
150
+#include "exec/exec-all.h"
419
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
151
+#include "exec/helper-proto.h"
420
GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
152
+#include "internals.h"
421
GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
153
+#include "vector_internals.h"
422
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
154
+
423
GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
155
+static uint64_t clmul64(uint64_t y, uint64_t x)
424
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
156
+{
425
GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
157
+ uint64_t result = 0;
426
-#endif
158
+ for (int j = 63; j >= 0; j--) {
427
159
+ if ((y >> j) & 1) {
428
static inline void
160
+ result ^= (x << j);
429
vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
161
+ }
430
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
162
+ }
431
GETPC()); \
163
+ return result;
432
}
164
+}
433
165
+
434
-#ifdef TARGET_RISCV64
166
+static uint64_t clmulh64(uint64_t y, uint64_t x)
435
GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
167
+{
436
GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
168
+ uint64_t result = 0;
437
GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
169
+ for (int j = 63; j >= 1; j--) {
438
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
170
+ if ((y >> j) & 1) {
439
GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
171
+ result ^= (x >> (64 - j));
440
GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
172
+ }
441
GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
173
+ }
442
-#endif
174
+ return result;
443
GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
175
+}
444
GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
176
+
445
GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
177
+RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64)
446
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
178
+GEN_VEXT_VV(vclmul_vv, 8)
447
index XXXXXXX..XXXXXXX 100644
179
+RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64)
448
--- a/target/riscv/insn_trans/trans_rva.c.inc
180
+GEN_VEXT_VX(vclmul_vx, 8)
449
+++ b/target/riscv/insn_trans/trans_rva.c.inc
181
+RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
450
@@ -XXX,XX +XXX,XX @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
182
+GEN_VEXT_VV(vclmulh_vv, 8)
451
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
183
+RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
452
}
184
+GEN_VEXT_VX(vclmulh_vx, 8)
453
185
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
454
-#ifdef TARGET_RISCV64
186
new file mode 100644
455
-
187
index XXXXXXX..XXXXXXX
456
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
188
--- /dev/null
457
{
189
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
458
+ REQUIRE_64BIT(ctx);
190
@@ -XXX,XX +XXX,XX @@
459
return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
191
+/*
460
}
192
+ * RISC-V translation routines for the vector crypto extension.
461
193
+ *
462
static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
194
+ * Copyright (C) 2023 SiFive, Inc.
463
{
195
+ * Written by Codethink Ltd and SiFive.
464
+ REQUIRE_64BIT(ctx);
196
+ *
465
return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
197
+ * This program is free software; you can redistribute it and/or modify it
466
}
198
+ * under the terms and conditions of the GNU General Public License,
467
199
+ * version 2 or later, as published by the Free Software Foundation.
468
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
200
+ *
469
{
201
+ * This program is distributed in the hope it will be useful, but WITHOUT
470
+ REQUIRE_64BIT(ctx);
202
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
471
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
203
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
472
}
204
+ * more details.
473
205
+ *
474
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
206
+ * You should have received a copy of the GNU General Public License along with
475
{
207
+ * this program. If not, see <http://www.gnu.org/licenses/>.
476
+ REQUIRE_64BIT(ctx);
208
+ */
477
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
209
+
478
}
210
+/*
479
211
+ * Zvbc
480
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
212
+ */
481
{
213
+
482
+ REQUIRE_64BIT(ctx);
214
+#define GEN_VV_MASKED_TRANS(NAME, CHECK) \
483
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
215
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
484
}
216
+ { \
485
217
+ if (CHECK(s, a)) { \
486
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
218
+ return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
487
{
219
+ gen_helper_##NAME, s); \
488
+ REQUIRE_64BIT(ctx);
220
+ } \
489
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
221
+ return false; \
490
}
222
+ }
491
223
+
492
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
224
+static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
493
{
225
+{
494
+ REQUIRE_64BIT(ctx);
226
+ return opivv_check(s, a) &&
495
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
227
+ s->cfg_ptr->ext_zvbc == true &&
496
}
228
+ s->sew == MO_64;
497
229
+}
498
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
230
+
499
{
231
+GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check)
500
+ REQUIRE_64BIT(ctx);
232
+GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check)
501
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
233
+
502
}
234
+#define GEN_VX_MASKED_TRANS(NAME, CHECK) \
503
235
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
504
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
236
+ { \
505
{
237
+ if (CHECK(s, a)) { \
506
+ REQUIRE_64BIT(ctx);
238
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
507
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
239
+ gen_helper_##NAME, s); \
508
}
240
+ } \
509
241
+ return false; \
510
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
242
+ }
511
{
243
+
512
+ REQUIRE_64BIT(ctx);
244
+static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
513
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
245
+{
514
}
246
+ return opivx_check(s, a) &&
515
247
+ s->cfg_ptr->ext_zvbc == true &&
516
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
248
+ s->sew == MO_64;
517
{
249
+}
518
+ REQUIRE_64BIT(ctx);
250
+
519
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
251
+GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
520
}
252
+GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
521
-#endif
522
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
523
index XXXXXXX..XXXXXXX 100644
524
--- a/target/riscv/insn_trans/trans_rvd.c.inc
525
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
526
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
527
return true;
528
}
529
530
-#ifdef TARGET_RISCV64
531
-
532
static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
533
{
534
+ REQUIRE_64BIT(ctx);
535
REQUIRE_FPU;
536
REQUIRE_EXT(ctx, RVD);
537
538
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
539
540
static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
541
{
542
+ REQUIRE_64BIT(ctx);
543
REQUIRE_FPU;
544
REQUIRE_EXT(ctx, RVD);
545
546
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
547
548
static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
549
{
550
+ REQUIRE_64BIT(ctx);
551
REQUIRE_FPU;
552
REQUIRE_EXT(ctx, RVD);
553
554
+#ifdef TARGET_RISCV64
555
gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
556
return true;
557
+#else
558
+ qemu_build_not_reached();
559
+#endif
560
}
561
562
static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
563
{
564
+ REQUIRE_64BIT(ctx);
565
REQUIRE_FPU;
566
REQUIRE_EXT(ctx, RVD);
567
568
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
569
570
static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
571
{
572
+ REQUIRE_64BIT(ctx);
573
REQUIRE_FPU;
574
REQUIRE_EXT(ctx, RVD);
575
576
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
577
578
static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
579
{
580
+ REQUIRE_64BIT(ctx);
581
REQUIRE_FPU;
582
REQUIRE_EXT(ctx, RVD);
583
584
+#ifdef TARGET_RISCV64
585
TCGv t0 = tcg_temp_new();
586
gen_get_gpr(t0, a->rs1);
587
588
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
589
tcg_temp_free(t0);
590
mark_fs_dirty(ctx);
591
return true;
592
-}
593
+#else
594
+ qemu_build_not_reached();
595
#endif
596
+}
597
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
598
index XXXXXXX..XXXXXXX 100644
599
--- a/target/riscv/insn_trans/trans_rvf.c.inc
600
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
601
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
602
return true;
603
}
604
605
-#ifdef TARGET_RISCV64
606
static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
607
{
608
+ REQUIRE_64BIT(ctx);
609
REQUIRE_FPU;
610
REQUIRE_EXT(ctx, RVF);
611
612
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
613
614
static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
615
{
616
+ REQUIRE_64BIT(ctx);
617
REQUIRE_FPU;
618
REQUIRE_EXT(ctx, RVF);
619
620
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
621
622
static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
623
{
624
+ REQUIRE_64BIT(ctx);
625
REQUIRE_FPU;
626
REQUIRE_EXT(ctx, RVF);
627
628
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
629
630
static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
631
{
632
+ REQUIRE_64BIT(ctx);
633
REQUIRE_FPU;
634
REQUIRE_EXT(ctx, RVF);
635
636
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
637
tcg_temp_free(t0);
638
return true;
639
}
640
-#endif
641
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
642
index XXXXXXX..XXXXXXX 100644
643
--- a/target/riscv/insn_trans/trans_rvh.c.inc
644
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
645
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
646
#endif
647
}
648
649
-#ifdef TARGET_RISCV64
650
static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
651
{
652
+ REQUIRE_64BIT(ctx);
653
REQUIRE_EXT(ctx, RVH);
654
+
655
#ifndef CONFIG_USER_ONLY
656
TCGv t0 = tcg_temp_new();
657
TCGv t1 = tcg_temp_new();
658
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
659
660
static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
661
{
662
+ REQUIRE_64BIT(ctx);
663
REQUIRE_EXT(ctx, RVH);
664
+
665
#ifndef CONFIG_USER_ONLY
666
TCGv t0 = tcg_temp_new();
667
TCGv t1 = tcg_temp_new();
668
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
669
670
static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
671
{
672
+ REQUIRE_64BIT(ctx);
673
REQUIRE_EXT(ctx, RVH);
674
+
675
#ifndef CONFIG_USER_ONLY
676
TCGv t0 = tcg_temp_new();
677
TCGv dat = tcg_temp_new();
678
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
679
return false;
680
#endif
681
}
682
-#endif
683
684
static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
685
{
686
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
687
index XXXXXXX..XXXXXXX 100644
688
--- a/target/riscv/insn_trans/trans_rvi.c.inc
689
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
690
@@ -XXX,XX +XXX,XX @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
691
return gen_store(ctx, a, MO_TESL);
692
}
693
694
-#ifdef TARGET_RISCV64
695
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
696
{
697
+ REQUIRE_64BIT(ctx);
698
return gen_load(ctx, a, MO_TEUL);
699
}
700
701
static bool trans_ld(DisasContext *ctx, arg_ld *a)
702
{
703
+ REQUIRE_64BIT(ctx);
704
return gen_load(ctx, a, MO_TEQ);
705
}
706
707
static bool trans_sd(DisasContext *ctx, arg_sd *a)
708
{
709
+ REQUIRE_64BIT(ctx);
710
return gen_store(ctx, a, MO_TEQ);
711
}
712
-#endif
713
714
static bool trans_addi(DisasContext *ctx, arg_addi *a)
715
{
716
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
717
return gen_arith(ctx, a, &tcg_gen_and_tl);
718
}
719
720
-#ifdef TARGET_RISCV64
721
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
722
{
723
+ REQUIRE_64BIT(ctx);
724
return gen_arith_imm_tl(ctx, a, &gen_addw);
725
}
726
727
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
728
{
729
+ REQUIRE_64BIT(ctx);
730
TCGv source1;
731
source1 = tcg_temp_new();
732
gen_get_gpr(source1, a->rs1);
733
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
734
735
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
736
{
737
+ REQUIRE_64BIT(ctx);
738
TCGv t = tcg_temp_new();
739
gen_get_gpr(t, a->rs1);
740
tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
741
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
742
743
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
744
{
745
+ REQUIRE_64BIT(ctx);
746
TCGv t = tcg_temp_new();
747
gen_get_gpr(t, a->rs1);
748
tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
749
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
750
751
static bool trans_addw(DisasContext *ctx, arg_addw *a)
752
{
753
+ REQUIRE_64BIT(ctx);
754
return gen_arith(ctx, a, &gen_addw);
755
}
756
757
static bool trans_subw(DisasContext *ctx, arg_subw *a)
758
{
759
+ REQUIRE_64BIT(ctx);
760
return gen_arith(ctx, a, &gen_subw);
761
}
762
763
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
764
{
765
+ REQUIRE_64BIT(ctx);
766
TCGv source1 = tcg_temp_new();
767
TCGv source2 = tcg_temp_new();
768
769
@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
770
771
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
772
{
773
+ REQUIRE_64BIT(ctx);
774
TCGv source1 = tcg_temp_new();
775
TCGv source2 = tcg_temp_new();
776
777
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
778
779
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
780
{
781
+ REQUIRE_64BIT(ctx);
782
TCGv source1 = tcg_temp_new();
783
TCGv source2 = tcg_temp_new();
784
785
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
786
787
return true;
788
}
789
-#endif
790
791
static bool trans_fence(DisasContext *ctx, arg_fence *a)
792
{
793
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
794
index XXXXXXX..XXXXXXX 100644
795
--- a/target/riscv/insn_trans/trans_rvm.c.inc
796
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
797
@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
798
return gen_arith(ctx, a, &gen_remu);
799
}
800
801
-#ifdef TARGET_RISCV64
802
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
803
{
804
+ REQUIRE_64BIT(ctx);
805
REQUIRE_EXT(ctx, RVM);
806
+
807
return gen_arith(ctx, a, &gen_mulw);
808
}
809
810
static bool trans_divw(DisasContext *ctx, arg_divw *a)
811
{
812
+ REQUIRE_64BIT(ctx);
813
REQUIRE_EXT(ctx, RVM);
814
+
815
return gen_arith_div_w(ctx, a, &gen_div);
816
}
817
818
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
819
{
820
+ REQUIRE_64BIT(ctx);
821
REQUIRE_EXT(ctx, RVM);
822
+
823
return gen_arith_div_uw(ctx, a, &gen_divu);
824
}
825
826
static bool trans_remw(DisasContext *ctx, arg_remw *a)
827
{
828
+ REQUIRE_64BIT(ctx);
829
REQUIRE_EXT(ctx, RVM);
830
+
831
return gen_arith_div_w(ctx, a, &gen_rem);
832
}
833
834
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
835
{
836
+ REQUIRE_64BIT(ctx);
837
REQUIRE_EXT(ctx, RVM);
838
+
839
return gen_arith_div_uw(ctx, a, &gen_remu);
840
}
841
-#endif
842
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
843
index XXXXXXX..XXXXXXX 100644
844
--- a/target/riscv/insn_trans/trans_rvv.c.inc
845
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
846
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
847
gen_helper_vamominuw_v_w,
848
gen_helper_vamomaxuw_v_w
849
};
850
-#ifdef TARGET_RISCV64
851
static gen_helper_amo *const fnsd[18] = {
852
gen_helper_vamoswapw_v_d,
853
gen_helper_vamoaddw_v_d,
854
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
855
gen_helper_vamominud_v_d,
856
gen_helper_vamomaxud_v_d
857
};
858
-#endif
859
860
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
861
gen_helper_exit_atomic(cpu_env);
862
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
863
return true;
864
} else {
865
if (s->sew == 3) {
866
-#ifdef TARGET_RISCV64
867
- fn = fnsd[seq];
868
-#else
869
- /* Check done in amo_check(). */
870
- g_assert_not_reached();
871
-#endif
872
+ if (!is_32bit(s)) {
873
+ fn = fnsd[seq];
874
+ } else {
875
+ /* Check done in amo_check(). */
876
+ g_assert_not_reached();
877
+ }
878
} else {
879
assert(seq < ARRAY_SIZE(fnsw));
880
fn = fnsw[seq];
881
@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
882
((1 << s->sew) >= 4));
883
}
884
885
+static bool amo_check64(DisasContext *s, arg_rwdvm* a)
886
+{
887
+ return !is_32bit(s) && amo_check(s, a);
888
+}
889
+
890
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
891
GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
892
GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
893
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
894
GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
895
GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
896
GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
897
-#ifdef TARGET_RISCV64
898
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
899
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
900
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
901
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
902
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
903
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
904
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
905
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
906
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
907
-#endif
908
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
909
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
910
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
911
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
912
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
913
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
914
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
915
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
916
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
917
918
/*
919
*** Vector Integer Arithmetic Instructions
920
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
253
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
921
index XXXXXXX..XXXXXXX 100644
254
index XXXXXXX..XXXXXXX 100644
922
--- a/target/riscv/meson.build
255
--- a/target/riscv/meson.build
923
+++ b/target/riscv/meson.build
256
+++ b/target/riscv/meson.build
924
@@ -XXX,XX +XXX,XX @@ gen32 = [
257
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
925
258
'translate.c',
926
gen64 = [
259
'm128_helper.c',
927
decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
260
'crypto_helper.c',
928
- decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
261
- 'zce_helper.c'
929
+ decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
262
+ 'zce_helper.c',
930
]
263
+ 'vcrypto_helper.c'
931
264
))
932
riscv_ss = ss.source_set()
265
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
266
933
--
267
--
934
2.31.1
268
2.41.0
935
936
diff view generated by jsdifflib
[PULL 20/42] target/riscv: Fix the PMP is locked check when using TOR
[PULL v2 12/45] target/riscv: Move vector translation checks
1
The RISC-V spec says:
1
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
2
if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
3
pmpaddri-1 are ignored.
4
2
5
The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
3
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
6
is incorrect.
4
and into the corresponding macros. This enables the functions to be
5
reused in proceeding commits without check duplication.
7
6
8
Update the pmp_is_locked() function to not check the supporting fields
7
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
9
and instead enforce the lock functionality in the pmpaddr write operation.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
Signed-off-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20230711165917.2629866-6-max.chou@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++--------------
15
1 file changed, 12 insertions(+), 16 deletions(-)
10
16
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
12
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
13
Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
14
---
15
target/riscv/pmp.c | 26 ++++++++++++++++----------
16
1 file changed, 16 insertions(+), 10 deletions(-)
17
18
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/pmp.c
19
--- a/target/riscv/insn_trans/trans_rvv.c.inc
21
+++ b/target/riscv/pmp.c
20
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
22
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
21
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
23
return 0;
22
gen_helper_gvec_4_ptr *fn)
24
}
23
{
25
24
TCGLabel *over = gen_new_label();
26
- /* In TOR mode, need to check the lock bit of the next pmp
25
- if (!opivv_check(s, a)) {
27
- * (if there is a next)
26
- return false;
28
- */
27
- }
29
- const uint8_t a_field =
28
30
- pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
29
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
31
- if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
30
32
- (PMP_AMATCH_TOR == a_field)) {
31
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
33
- return 1;
32
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
33
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
34
}; \
35
+ if (!opivv_check(s, a)) { \
36
+ return false; \
37
+ } \
38
return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
39
}
40
41
@@ -XXX,XX +XXX,XX @@ static inline bool
42
do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
43
gen_helper_opivx *fn)
44
{
45
- if (!opivx_check(s, a)) {
46
- return false;
34
- }
47
- }
35
-
48
-
36
return 0;
49
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
50
TCGv_i64 src1 = tcg_temp_new_i64();
51
52
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
53
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
54
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
55
}; \
56
+ if (!opivx_check(s, a)) { \
57
+ return false; \
58
+ } \
59
return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
37
}
60
}
38
61
39
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
62
@@ -XXX,XX +XXX,XX @@ static inline bool
40
target_ulong val)
63
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
64
gen_helper_opivx *fn, imm_mode_t imm_mode)
41
{
65
{
42
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
66
- if (!opivx_check(s, a)) {
43
+
67
- return false;
44
if (addr_index < MAX_RISCV_PMPS) {
68
- }
45
+ /*
69
-
46
+ * In TOR mode, need to check the lock bit of the next pmp
70
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
47
+ * (if there is a next).
71
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
48
+ */
72
extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
49
+ if (addr_index + 1 < MAX_RISCV_PMPS) {
73
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
50
+ uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
74
gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
51
+
75
gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
52
+ if (pmp_cfg & PMP_LOCK &&
76
}; \
53
+ PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
77
+ if (!opivx_check(s, a)) { \
54
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ return false; \
55
+ "ignoring pmpaddr write - pmpcfg + 1 locked\n");
79
+ } \
56
+ return;
80
return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
57
+ }
81
fns[s->sew], IMM_MODE); \
58
+ }
82
}
59
+
83
@@ -XXX,XX +XXX,XX @@ static inline bool
60
if (!pmp_is_locked(env, addr_index)) {
84
do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
61
env->pmp_state.pmp[addr_index].addr_reg = val;
85
gen_helper_opivx *fn)
62
pmp_update_rule(env, addr_index);
86
{
87
- if (!opivx_check(s, a)) {
88
- return false;
89
- }
90
-
91
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
92
TCGv_i32 src1 = tcg_temp_new_i32();
93
94
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
95
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
96
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
97
}; \
98
- \
99
+ if (!opivx_check(s, a)) { \
100
+ return false; \
101
+ } \
102
return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
103
}
104
63
--
105
--
64
2.31.1
106
2.41.0
65
66
diff view generated by jsdifflib
[PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro
[PULL v2 13/45] target/riscv: Refactor translation of vector-widening instruction
1
From: Dickon Hood <dickon.hood@codethink.co.uk>
2
3
Zvbb (implemented in later commit) has a widening instruction, which
4
requires an extra check on the enabled extensions. Refactor
5
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
6
it.
7
8
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Message-ID: <20230711165917.2629866-7-max.chou@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
5
---
14
---
6
target/riscv/cpu_bits.h | 11 -----------
15
target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++--------------
7
target/riscv/cpu_helper.c | 24 +++++++++++++++---------
16
1 file changed, 23 insertions(+), 29 deletions(-)
8
2 files changed, 15 insertions(+), 20 deletions(-)
9
17
10
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
18
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
11
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu_bits.h
20
--- a/target/riscv/insn_trans/trans_rvv.c.inc
13
+++ b/target/riscv/cpu_bits.h
21
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
14
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
15
#define CSR_HTIMEDELTA 0x605
23
vext_check_ds(s, a->rd, a->rs2, a->vm);
16
#define CSR_HTIMEDELTAH 0x615
24
}
17
25
18
-#if defined(TARGET_RISCV32)
26
-static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
19
-#define HGATP_MODE SATP32_MODE
27
- gen_helper_opivx *fn)
20
-#define HGATP_VMID SATP32_ASID
28
-{
21
-#define HGATP_PPN SATP32_PPN
29
- if (opivx_widen_check(s, a)) {
22
-#endif
30
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
23
-#if defined(TARGET_RISCV64)
31
- }
24
-#define HGATP_MODE SATP64_MODE
32
- return false;
25
-#define HGATP_VMID SATP64_ASID
33
-}
26
-#define HGATP_PPN SATP64_PPN
27
-#endif
28
-
34
-
29
/* Virtual CSRs */
35
-#define GEN_OPIVX_WIDEN_TRANS(NAME) \
30
#define CSR_VSSTATUS 0x200
36
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
31
#define CSR_VSIE 0x204
37
-{ \
32
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
38
- static gen_helper_opivx * const fns[3] = { \
33
index XXXXXXX..XXXXXXX 100644
39
- gen_helper_##NAME##_b, \
34
--- a/target/riscv/cpu_helper.c
40
- gen_helper_##NAME##_h, \
35
+++ b/target/riscv/cpu_helper.c
41
- gen_helper_##NAME##_w \
36
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
42
- }; \
37
}
43
- return do_opivx_widen(s, a, fns[s->sew]); \
38
widened = 0;
44
+#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
39
} else {
45
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
40
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
46
+{ \
41
- vm = get_field(env->hgatp, HGATP_MODE);
47
+ if (CHECK(s, a)) { \
42
+ if (riscv_cpu_is_32bit(env)) {
48
+ static gen_helper_opivx * const fns[3] = { \
43
+ base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
49
+ gen_helper_##NAME##_b, \
44
+ vm = get_field(env->hgatp, SATP32_MODE);
50
+ gen_helper_##NAME##_h, \
45
+ } else {
51
+ gen_helper_##NAME##_w \
46
+ base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
52
+ }; \
47
+ vm = get_field(env->hgatp, SATP64_MODE);
53
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \
48
+ }
54
+ } \
49
widened = 2;
55
+ return false; \
50
}
56
}
51
/* status.SUM will be ignored if execute on background */
57
52
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
58
-GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
53
bool first_stage, bool two_stage)
59
-GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
54
{
60
-GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
55
CPUState *cs = env_cpu(env);
61
-GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
56
- int page_fault_exceptions;
62
+GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check)
57
+ int page_fault_exceptions, vm;
63
+GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check)
58
+
64
+GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check)
59
if (first_stage) {
65
+GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check)
60
- page_fault_exceptions =
66
61
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
67
/* WIDEN OPIVV with WIDEN */
62
- !pmp_violation;
68
static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
63
+ vm = get_field(env->satp, SATP_MODE);
69
@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check)
64
+ } else if (riscv_cpu_is_32bit(env)) {
70
GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
65
+ vm = get_field(env->hgatp, SATP32_MODE);
71
GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
66
} else {
72
GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
67
- page_fault_exceptions =
73
-GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
68
- get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
74
-GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
69
- !pmp_violation;
75
-GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
70
+ vm = get_field(env->hgatp, SATP64_MODE);
76
+GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check)
71
}
77
+GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check)
72
+ page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
78
+GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check)
73
+
79
74
switch (access_type) {
80
/* Vector Single-Width Integer Multiply-Add Instructions */
75
case MMU_INST_FETCH:
81
GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
76
if (riscv_cpu_virt_enabled(env) && !first_stage) {
82
@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
83
GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
84
GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
85
GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
86
-GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
87
-GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
88
-GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
89
-GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
90
+GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
91
+GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
92
+GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
93
+GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
94
95
/* Vector Integer Merge and Move Instructions */
96
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
77
--
97
--
78
2.31.1
98
2.41.0
79
80
diff view generated by jsdifflib
[PULL 18/42] target/riscv: Fixup saturate subtract function
[PULL v2 14/45] target/riscv: Refactor some of the generic vector functionality
1
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
1
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
2
2
3
The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
3
Move some macros out of `vector_helper` and into `vector_internals`.
4
However, when the predication is ture and a is 0, it should return maximum.
4
This ensures they can be used by both vector and vector-crypto helpers
5
(latter implemented in proceeding commits).
5
6
6
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
7
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Max Chou <max.chou@sifive.com>
9
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
10
Message-ID: <20230711165917.2629866-8-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
target/riscv/vector_helper.c | 8 ++++----
13
target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++
13
1 file changed, 4 insertions(+), 4 deletions(-)
14
target/riscv/vector_helper.c | 42 ------------------------------
15
2 files changed, 46 insertions(+), 42 deletions(-)
14
16
17
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/vector_internals.h
20
+++ b/target/riscv/vector_internals.h
21
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
22
/* expand macro args before macro */
23
#define RVVCALL(macro, ...) macro(__VA_ARGS__)
24
25
+/* (TD, T2, TX2) */
26
+#define OP_UU_B uint8_t, uint8_t, uint8_t
27
+#define OP_UU_H uint16_t, uint16_t, uint16_t
28
+#define OP_UU_W uint32_t, uint32_t, uint32_t
29
+#define OP_UU_D uint64_t, uint64_t, uint64_t
30
+
31
/* (TD, T1, T2, TX1, TX2) */
32
#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
33
#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
34
#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
35
#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
36
37
+#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
38
+static void do_##NAME(void *vd, void *vs2, int i) \
39
+{ \
40
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
41
+ *((TD *)vd + HD(i)) = OP(s2); \
42
+}
43
+
44
+#define GEN_VEXT_V(NAME, ESZ) \
45
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
46
+ CPURISCVState *env, uint32_t desc) \
47
+{ \
48
+ uint32_t vm = vext_vm(desc); \
49
+ uint32_t vl = env->vl; \
50
+ uint32_t total_elems = \
51
+ vext_get_total_elems(env, desc, ESZ); \
52
+ uint32_t vta = vext_vta(desc); \
53
+ uint32_t vma = vext_vma(desc); \
54
+ uint32_t i; \
55
+ \
56
+ for (i = env->vstart; i < vl; i++) { \
57
+ if (!vm && !vext_elem_mask(v0, i)) { \
58
+ /* set masked-off elements to 1s */ \
59
+ vext_set_elems_1s(vd, vma, i * ESZ, \
60
+ (i + 1) * ESZ); \
61
+ continue; \
62
+ } \
63
+ do_##NAME(vd, vs2, i); \
64
+ } \
65
+ env->vstart = 0; \
66
+ /* set tail elements to 1s */ \
67
+ vext_set_elems_1s(vd, vta, vl * ESZ, \
68
+ total_elems * ESZ); \
69
+}
70
+
71
/* operation of two vector elements */
72
typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
73
74
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
75
do_##NAME, ESZ); \
76
}
77
78
+/* Three of the widening shortening macros: */
79
+/* (TD, T1, T2, TX1, TX2) */
80
+#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
81
+#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
82
+#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
83
+
84
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
15
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
85
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
16
index XXXXXXX..XXXXXXX 100644
86
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/vector_helper.c
87
--- a/target/riscv/vector_helper.c
18
+++ b/target/riscv/vector_helper.c
88
+++ b/target/riscv/vector_helper.c
19
@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
89
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
90
#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
91
#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
92
#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
93
-#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
94
-#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
95
-#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
96
#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
97
#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
98
#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
99
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4)
100
GEN_VEXT_VF(vfwnmsac_vf_w, 8)
101
102
/* Vector Floating-Point Square-Root Instruction */
103
-/* (TD, T2, TX2) */
104
-#define OP_UU_H uint16_t, uint16_t, uint16_t
105
-#define OP_UU_W uint32_t, uint32_t, uint32_t
106
-#define OP_UU_D uint64_t, uint64_t, uint64_t
107
-
108
#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
109
static void do_##NAME(void *vd, void *vs2, int i, \
110
CPURISCVState *env) \
111
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
112
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
113
114
/* Vector Floating-Point Classify Instruction */
115
-#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
116
-static void do_##NAME(void *vd, void *vs2, int i) \
117
-{ \
118
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
119
- *((TD *)vd + HD(i)) = OP(s2); \
120
-}
121
-
122
-#define GEN_VEXT_V(NAME, ESZ) \
123
-void HELPER(NAME)(void *vd, void *v0, void *vs2, \
124
- CPURISCVState *env, uint32_t desc) \
125
-{ \
126
- uint32_t vm = vext_vm(desc); \
127
- uint32_t vl = env->vl; \
128
- uint32_t total_elems = \
129
- vext_get_total_elems(env, desc, ESZ); \
130
- uint32_t vta = vext_vta(desc); \
131
- uint32_t vma = vext_vma(desc); \
132
- uint32_t i; \
133
- \
134
- for (i = env->vstart; i < vl; i++) { \
135
- if (!vm && !vext_elem_mask(v0, i)) { \
136
- /* set masked-off elements to 1s */ \
137
- vext_set_elems_1s(vd, vma, i * ESZ, \
138
- (i + 1) * ESZ); \
139
- continue; \
140
- } \
141
- do_##NAME(vd, vs2, i); \
142
- } \
143
- env->vstart = 0; \
144
- /* set tail elements to 1s */ \
145
- vext_set_elems_1s(vd, vta, vl * ESZ, \
146
- total_elems * ESZ); \
147
-}
148
-
149
target_ulong fclass_h(uint64_t frs1)
20
{
150
{
21
int8_t res = a - b;
151
float16 f = frs1;
22
if ((res ^ a) & (a ^ b) & INT8_MIN) {
23
- res = a > 0 ? INT8_MAX : INT8_MIN;
24
+ res = a >= 0 ? INT8_MAX : INT8_MIN;
25
env->vxsat = 0x1;
26
}
27
return res;
28
@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
29
{
30
int16_t res = a - b;
31
if ((res ^ a) & (a ^ b) & INT16_MIN) {
32
- res = a > 0 ? INT16_MAX : INT16_MIN;
33
+ res = a >= 0 ? INT16_MAX : INT16_MIN;
34
env->vxsat = 0x1;
35
}
36
return res;
37
@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
38
{
39
int32_t res = a - b;
40
if ((res ^ a) & (a ^ b) & INT32_MIN) {
41
- res = a > 0 ? INT32_MAX : INT32_MIN;
42
+ res = a >= 0 ? INT32_MAX : INT32_MIN;
43
env->vxsat = 0x1;
44
}
45
return res;
46
@@ -XXX,XX +XXX,XX @@ static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
47
{
48
int64_t res = a - b;
49
if ((res ^ a) & (a ^ b) & INT64_MIN) {
50
- res = a > 0 ? INT64_MAX : INT64_MIN;
51
+ res = a >= 0 ? INT64_MAX : INT64_MIN;
52
env->vxsat = 0x1;
53
}
54
return res;
55
--
152
--
56
2.31.1
153
2.41.0
57
58
diff view generated by jsdifflib
[PULL 07/42] hw/char: Add Shakti UART emulation
[PULL v2 15/45] target/riscv: Add Zvbb ISA extension support
1
From: Vijai Kumar K <vijai@behindbytes.com>
1
From: Dickon Hood <dickon.hood@codethink.co.uk>
2
2
3
This is the initial implementation of Shakti UART.
3
This commit adds support for the Zvbb vector-crypto extension, which
4
consists of the following instructions:
4
5
5
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
6
* vrol.[vv,vx]
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
* vror.[vv,vx,vi]
7
Message-id: 20210401181457.73039-4-vijai@behindbytes.com
8
* vbrev8.v
9
* vrev8.v
10
* vandn.[vv,vx]
11
* vbrev.v
12
* vclz.v
13
* vctz.v
14
* vcpop.v
15
* vwsll.[vv,vx,vi]
16
17
Translation functions are defined in
18
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
19
`target/riscv/vcrypto_helper.c`.
20
21
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
22
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
23
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
24
[max.chou@sifive.com: Fix imm mode of vror.vi]
25
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
26
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
27
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
28
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
29
Signed-off-by: Max Chou <max.chou@sifive.com>
30
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
[max.chou@sifive.com: Exposed x-zvbb property]
32
Message-ID: <20230711165917.2629866-9-max.chou@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
34
---
10
include/hw/char/shakti_uart.h | 74 ++++++++++++++
35
target/riscv/cpu_cfg.h | 1 +
11
hw/char/shakti_uart.c | 185 ++++++++++++++++++++++++++++++++++
36
target/riscv/helper.h | 62 +++++++++
12
MAINTAINERS | 2 +
37
target/riscv/insn32.decode | 20 +++
13
hw/char/meson.build | 1 +
38
target/riscv/cpu.c | 12 ++
14
hw/char/trace-events | 4 +
39
target/riscv/vcrypto_helper.c | 138 +++++++++++++++++++
15
5 files changed, 266 insertions(+)
40
target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++
16
create mode 100644 include/hw/char/shakti_uart.h
41
6 files changed, 397 insertions(+)
17
create mode 100644 hw/char/shakti_uart.c
18
42
19
diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
43
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
20
new file mode 100644
44
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX
45
--- a/target/riscv/cpu_cfg.h
22
--- /dev/null
46
+++ b/target/riscv/cpu_cfg.h
23
+++ b/include/hw/char/shakti_uart.h
47
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
48
bool ext_zve32f;
49
bool ext_zve64f;
50
bool ext_zve64d;
51
+ bool ext_zvbb;
52
bool ext_zvbc;
53
bool ext_zmmul;
54
bool ext_zvfbfmin;
55
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/helper.h
58
+++ b/target/riscv/helper.h
59
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
60
DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
61
DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
62
DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
63
+
64
+DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
65
+DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
66
+DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
67
+DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
68
+
69
+DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32)
70
+DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32)
71
+DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32)
72
+DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32)
73
+
74
+DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
75
+DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
76
+DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
77
+DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
78
+
79
+DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32)
80
+DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32)
81
+DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32)
82
+DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32)
83
+
84
+DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32)
85
+DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32)
86
+DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32)
87
+DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32)
88
+DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32)
89
+DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32)
90
+DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32)
91
+DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32)
92
+DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32)
93
+DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32)
94
+DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32)
95
+DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32)
96
+
97
+DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32)
98
+DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32)
99
+DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32)
100
+DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32)
101
+DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32)
102
+DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32)
103
+DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32)
104
+DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32)
105
+DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32)
106
+DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32)
107
+DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32)
108
+DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32)
109
+
110
+DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
111
+DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
112
+DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
113
+DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32)
114
+DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32)
115
+DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32)
116
+
117
+DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
118
+DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
119
+DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
120
+DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
121
+DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
122
+DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
123
+DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
124
+DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
125
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/riscv/insn32.decode
128
+++ b/target/riscv/insn32.decode
24
@@ -XXX,XX +XXX,XX @@
129
@@ -XXX,XX +XXX,XX @@
130
%imm_u 12:s20 !function=ex_shift_12
131
%imm_bs 30:2 !function=ex_shift_3
132
%imm_rnum 20:4
133
+%imm_z6 26:1 15:5
134
135
# Argument sets:
136
&empty
137
@@ -XXX,XX +XXX,XX @@
138
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
139
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
140
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
141
+@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd
142
@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
143
@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
144
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
145
@@ -XXX,XX +XXX,XX @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
146
vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
147
vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
148
vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
149
+
150
+# *** Zvbb vector crypto extension ***
151
+vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm
152
+vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm
153
+vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
154
+vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
155
+vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
156
+vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
157
+vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm
158
+vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm
159
+vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm
160
+vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm
161
+vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm
162
+vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm
163
+vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
164
+vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
165
+vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
166
+vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
167
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
168
index XXXXXXX..XXXXXXX 100644
169
--- a/target/riscv/cpu.c
170
+++ b/target/riscv/cpu.c
171
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
172
ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
173
ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
174
ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
175
+ ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
176
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
177
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
178
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
179
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
180
return;
181
}
182
183
+ /*
184
+ * In principle Zve*x would also suffice here, were they supported
185
+ * in qemu
186
+ */
187
+ if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
188
+ error_setg(errp,
189
+ "Vector crypto extensions require V or Zve* extensions");
190
+ return;
191
+ }
192
+
193
if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
194
error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
195
return;
196
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
197
DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
198
199
/* Vector cryptography extensions */
200
+ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
201
DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
202
203
DEFINE_PROP_END_OF_LIST(),
204
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/riscv/vcrypto_helper.c
207
+++ b/target/riscv/vcrypto_helper.c
208
@@ -XXX,XX +XXX,XX @@
209
#include "qemu/osdep.h"
210
#include "qemu/host-utils.h"
211
#include "qemu/bitops.h"
212
+#include "qemu/bswap.h"
213
#include "cpu.h"
214
#include "exec/memop.h"
215
#include "exec/exec-all.h"
216
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
217
GEN_VEXT_VV(vclmulh_vv, 8)
218
RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
219
GEN_VEXT_VX(vclmulh_vx, 8)
220
+
221
+RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8)
222
+RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16)
223
+RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32)
224
+RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64)
225
+GEN_VEXT_VV(vror_vv_b, 1)
226
+GEN_VEXT_VV(vror_vv_h, 2)
227
+GEN_VEXT_VV(vror_vv_w, 4)
228
+GEN_VEXT_VV(vror_vv_d, 8)
229
+
230
+RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8)
231
+RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16)
232
+RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32)
233
+RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64)
234
+GEN_VEXT_VX(vror_vx_b, 1)
235
+GEN_VEXT_VX(vror_vx_h, 2)
236
+GEN_VEXT_VX(vror_vx_w, 4)
237
+GEN_VEXT_VX(vror_vx_d, 8)
238
+
239
+RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8)
240
+RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16)
241
+RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32)
242
+RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64)
243
+GEN_VEXT_VV(vrol_vv_b, 1)
244
+GEN_VEXT_VV(vrol_vv_h, 2)
245
+GEN_VEXT_VV(vrol_vv_w, 4)
246
+GEN_VEXT_VV(vrol_vv_d, 8)
247
+
248
+RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8)
249
+RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16)
250
+RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32)
251
+RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64)
252
+GEN_VEXT_VX(vrol_vx_b, 1)
253
+GEN_VEXT_VX(vrol_vx_h, 2)
254
+GEN_VEXT_VX(vrol_vx_w, 4)
255
+GEN_VEXT_VX(vrol_vx_d, 8)
256
+
257
+static uint64_t brev8(uint64_t val)
258
+{
259
+ val = ((val & 0x5555555555555555ull) << 1) |
260
+ ((val & 0xAAAAAAAAAAAAAAAAull) >> 1);
261
+ val = ((val & 0x3333333333333333ull) << 2) |
262
+ ((val & 0xCCCCCCCCCCCCCCCCull) >> 2);
263
+ val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4) |
264
+ ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4);
265
+
266
+ return val;
267
+}
268
+
269
+RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8)
270
+RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8)
271
+RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8)
272
+RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8)
273
+GEN_VEXT_V(vbrev8_v_b, 1)
274
+GEN_VEXT_V(vbrev8_v_h, 2)
275
+GEN_VEXT_V(vbrev8_v_w, 4)
276
+GEN_VEXT_V(vbrev8_v_d, 8)
277
+
278
+#define DO_IDENTITY(a) (a)
279
+RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY)
280
+RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16)
281
+RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32)
282
+RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64)
283
+GEN_VEXT_V(vrev8_v_b, 1)
284
+GEN_VEXT_V(vrev8_v_h, 2)
285
+GEN_VEXT_V(vrev8_v_w, 4)
286
+GEN_VEXT_V(vrev8_v_d, 8)
287
+
288
+#define DO_ANDN(a, b) ((a) & ~(b))
289
+RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN)
290
+RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN)
291
+RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN)
292
+RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN)
293
+GEN_VEXT_VV(vandn_vv_b, 1)
294
+GEN_VEXT_VV(vandn_vv_h, 2)
295
+GEN_VEXT_VV(vandn_vv_w, 4)
296
+GEN_VEXT_VV(vandn_vv_d, 8)
297
+
298
+RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN)
299
+RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN)
300
+RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN)
301
+RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN)
302
+GEN_VEXT_VX(vandn_vx_b, 1)
303
+GEN_VEXT_VX(vandn_vx_h, 2)
304
+GEN_VEXT_VX(vandn_vx_w, 4)
305
+GEN_VEXT_VX(vandn_vx_d, 8)
306
+
307
+RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8)
308
+RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16)
309
+RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32)
310
+RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64)
311
+GEN_VEXT_V(vbrev_v_b, 1)
312
+GEN_VEXT_V(vbrev_v_h, 2)
313
+GEN_VEXT_V(vbrev_v_w, 4)
314
+GEN_VEXT_V(vbrev_v_d, 8)
315
+
316
+RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8)
317
+RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16)
318
+RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32)
319
+RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64)
320
+GEN_VEXT_V(vclz_v_b, 1)
321
+GEN_VEXT_V(vclz_v_h, 2)
322
+GEN_VEXT_V(vclz_v_w, 4)
323
+GEN_VEXT_V(vclz_v_d, 8)
324
+
325
+RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8)
326
+RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16)
327
+RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32)
328
+RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64)
329
+GEN_VEXT_V(vctz_v_b, 1)
330
+GEN_VEXT_V(vctz_v_h, 2)
331
+GEN_VEXT_V(vctz_v_w, 4)
332
+GEN_VEXT_V(vctz_v_d, 8)
333
+
334
+RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8)
335
+RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16)
336
+RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32)
337
+RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64)
338
+GEN_VEXT_V(vcpop_v_b, 1)
339
+GEN_VEXT_V(vcpop_v_h, 2)
340
+GEN_VEXT_V(vcpop_v_w, 4)
341
+GEN_VEXT_V(vcpop_v_d, 8)
342
+
343
+#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1)))
344
+RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL)
345
+RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL)
346
+RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL)
347
+GEN_VEXT_VV(vwsll_vv_b, 2)
348
+GEN_VEXT_VV(vwsll_vv_h, 4)
349
+GEN_VEXT_VV(vwsll_vv_w, 8)
350
+
351
+RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL)
352
+RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL)
353
+RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
354
+GEN_VEXT_VX(vwsll_vx_b, 2)
355
+GEN_VEXT_VX(vwsll_vx_h, 4)
356
+GEN_VEXT_VX(vwsll_vx_w, 8)
357
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
358
index XXXXXXX..XXXXXXX 100644
359
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
360
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
361
@@ -XXX,XX +XXX,XX @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
362
363
GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
364
GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
365
+
25
+/*
366
+/*
26
+ * SHAKTI UART
367
+ * Zvbb
27
+ *
28
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
29
+ *
30
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
31
+ * of this software and associated documentation files (the "Software"), to deal
32
+ * in the Software without restriction, including without limitation the rights
33
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34
+ * copies of the Software, and to permit persons to whom the Software is
35
+ * furnished to do so, subject to the following conditions:
36
+ *
37
+ * The above copyright notice and this permission notice shall be included in
38
+ * all copies or substantial portions of the Software.
39
+ *
40
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46
+ * THE SOFTWARE.
47
+ */
368
+ */
48
+
369
+
49
+#ifndef HW_SHAKTI_UART_H
370
+#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \
50
+#define HW_SHAKTI_UART_H
371
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
51
+
372
+ { \
52
+#include "hw/sysbus.h"
373
+ if (CHECK(s, a)) { \
53
+#include "chardev/char-fe.h"
374
+ static gen_helper_opivx *const fns[4] = { \
54
+
375
+ gen_helper_##OPIVX##_b, \
55
+#define SHAKTI_UART_BAUD 0x00
376
+ gen_helper_##OPIVX##_h, \
56
+#define SHAKTI_UART_TX 0x04
377
+ gen_helper_##OPIVX##_w, \
57
+#define SHAKTI_UART_RX 0x08
378
+ gen_helper_##OPIVX##_d, \
58
+#define SHAKTI_UART_STATUS 0x0C
379
+ }; \
59
+#define SHAKTI_UART_DELAY 0x10
380
+ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \
60
+#define SHAKTI_UART_CONTROL 0x14
381
+ IMM_MODE); \
61
+#define SHAKTI_UART_INT_EN 0x18
382
+ } \
62
+#define SHAKTI_UART_IQ_CYCLES 0x1C
383
+ return false; \
63
+#define SHAKTI_UART_RX_THRES 0x20
384
+ }
64
+
385
+
65
+#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
386
+#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
66
+#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
387
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
67
+#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
388
+ { \
68
+#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
389
+ if (CHECK(s, a)) { \
69
+/* 9600 8N1 is the default setting */
390
+ static gen_helper_gvec_4_ptr *const fns[4] = { \
70
+/* Reg value = (50000000 Hz)/(16 * 9600)*/
391
+ gen_helper_##NAME##_b, \
71
+#define SHAKTI_UART_BAUD_DEFAULT 0x0145
392
+ gen_helper_##NAME##_h, \
72
+#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
393
+ gen_helper_##NAME##_w, \
73
+
394
+ gen_helper_##NAME##_d, \
74
+#define TYPE_SHAKTI_UART "shakti-uart"
395
+ }; \
75
+#define SHAKTI_UART(obj) \
396
+ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
76
+ OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
397
+ } \
77
+
398
+ return false; \
78
+typedef struct {
399
+ }
79
+ /* <private> */
400
+
80
+ SysBusDevice parent_obj;
401
+#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \
81
+
402
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
82
+ /* <public> */
403
+ { \
83
+ MemoryRegion mmio;
404
+ if (CHECK(s, a)) { \
84
+
405
+ static gen_helper_opivx *const fns[4] = { \
85
+ uint32_t uart_baud;
406
+ gen_helper_##NAME##_b, \
86
+ uint32_t uart_tx;
407
+ gen_helper_##NAME##_h, \
87
+ uint32_t uart_rx;
408
+ gen_helper_##NAME##_w, \
88
+ uint32_t uart_status;
409
+ gen_helper_##NAME##_d, \
89
+ uint32_t uart_delay;
410
+ }; \
90
+ uint32_t uart_control;
411
+ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \
91
+ uint32_t uart_interrupt;
412
+ fns[s->sew]); \
92
+ uint32_t uart_iq_cycles;
413
+ } \
93
+ uint32_t uart_rx_threshold;
414
+ return false; \
94
+
415
+ }
95
+ CharBackend chr;
416
+
96
+} ShaktiUartState;
417
+static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
97
+
98
+#endif /* HW_SHAKTI_UART_H */
99
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
100
new file mode 100644
101
index XXXXXXX..XXXXXXX
102
--- /dev/null
103
+++ b/hw/char/shakti_uart.c
104
@@ -XXX,XX +XXX,XX @@
105
+/*
106
+ * SHAKTI UART
107
+ *
108
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
109
+ *
110
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
111
+ * of this software and associated documentation files (the "Software"), to deal
112
+ * in the Software without restriction, including without limitation the rights
113
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
114
+ * copies of the Software, and to permit persons to whom the Software is
115
+ * furnished to do so, subject to the following conditions:
116
+ *
117
+ * The above copyright notice and this permission notice shall be included in
118
+ * all copies or substantial portions of the Software.
119
+ *
120
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
121
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
122
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
123
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
124
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
125
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
126
+ * THE SOFTWARE.
127
+ */
128
+
129
+#include "qemu/osdep.h"
130
+#include "hw/char/shakti_uart.h"
131
+#include "hw/qdev-properties.h"
132
+#include "hw/qdev-properties-system.h"
133
+#include "qemu/log.h"
134
+
135
+static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
136
+{
418
+{
137
+ ShaktiUartState *s = opaque;
419
+ return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
138
+
139
+ switch (addr) {
140
+ case SHAKTI_UART_BAUD:
141
+ return s->uart_baud;
142
+ case SHAKTI_UART_RX:
143
+ qemu_chr_fe_accept_input(&s->chr);
144
+ s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
145
+ return s->uart_rx;
146
+ case SHAKTI_UART_STATUS:
147
+ return s->uart_status;
148
+ case SHAKTI_UART_DELAY:
149
+ return s->uart_delay;
150
+ case SHAKTI_UART_CONTROL:
151
+ return s->uart_control;
152
+ case SHAKTI_UART_INT_EN:
153
+ return s->uart_interrupt;
154
+ case SHAKTI_UART_IQ_CYCLES:
155
+ return s->uart_iq_cycles;
156
+ case SHAKTI_UART_RX_THRES:
157
+ return s->uart_rx_threshold;
158
+ default:
159
+ /* Also handles TX REG which is write only */
160
+ qemu_log_mask(LOG_GUEST_ERROR,
161
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
162
+ }
163
+
164
+ return 0;
165
+}
420
+}
166
+
421
+
167
+static void shakti_uart_write(void *opaque, hwaddr addr,
422
+static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
168
+ uint64_t data, unsigned size)
169
+{
423
+{
170
+ ShaktiUartState *s = opaque;
424
+ return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
171
+ uint32_t value = data;
172
+ uint8_t ch;
173
+
174
+ switch (addr) {
175
+ case SHAKTI_UART_BAUD:
176
+ s->uart_baud = value;
177
+ break;
178
+ case SHAKTI_UART_TX:
179
+ ch = value;
180
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
181
+ s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
182
+ break;
183
+ case SHAKTI_UART_STATUS:
184
+ s->uart_status = value;
185
+ break;
186
+ case SHAKTI_UART_DELAY:
187
+ s->uart_delay = value;
188
+ break;
189
+ case SHAKTI_UART_CONTROL:
190
+ s->uart_control = value;
191
+ break;
192
+ case SHAKTI_UART_INT_EN:
193
+ s->uart_interrupt = value;
194
+ break;
195
+ case SHAKTI_UART_IQ_CYCLES:
196
+ s->uart_iq_cycles = value;
197
+ break;
198
+ case SHAKTI_UART_RX_THRES:
199
+ s->uart_rx_threshold = value;
200
+ break;
201
+ default:
202
+ qemu_log_mask(LOG_GUEST_ERROR,
203
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
204
+ }
205
+}
425
+}
206
+
426
+
207
+static const MemoryRegionOps shakti_uart_ops = {
427
+/* vrol.v[vx] */
208
+ .read = shakti_uart_read,
428
+GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
209
+ .write = shakti_uart_write,
429
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
210
+ .endianness = DEVICE_NATIVE_ENDIAN,
430
+
211
+ .impl = {.min_access_size = 1, .max_access_size = 4},
431
+/* vror.v[vxi] */
212
+ .valid = {.min_access_size = 1, .max_access_size = 4},
432
+GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
213
+};
433
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
214
+
434
+GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
215
+static void shakti_uart_reset(DeviceState *dev)
435
+
436
+#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
437
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
438
+ { \
439
+ if (CHECK(s, a)) { \
440
+ static gen_helper_opivx *const fns[4] = { \
441
+ gen_helper_##NAME##_b, \
442
+ gen_helper_##NAME##_h, \
443
+ gen_helper_##NAME##_w, \
444
+ gen_helper_##NAME##_d, \
445
+ }; \
446
+ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
447
+ } \
448
+ return false; \
449
+ }
450
+
451
+/* vandn.v[vx] */
452
+GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
453
+GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
454
+
455
+#define GEN_OPIV_TRANS(NAME, CHECK) \
456
+ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
457
+ { \
458
+ if (CHECK(s, a)) { \
459
+ uint32_t data = 0; \
460
+ static gen_helper_gvec_3_ptr *const fns[4] = { \
461
+ gen_helper_##NAME##_b, \
462
+ gen_helper_##NAME##_h, \
463
+ gen_helper_##NAME##_w, \
464
+ gen_helper_##NAME##_d, \
465
+ }; \
466
+ TCGLabel *over = gen_new_label(); \
467
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
468
+ \
469
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
470
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
471
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
472
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
473
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
474
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
475
+ vreg_ofs(s, a->rs2), cpu_env, \
476
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
477
+ data, fns[s->sew]); \
478
+ mark_vs_dirty(s); \
479
+ gen_set_label(over); \
480
+ return true; \
481
+ } \
482
+ return false; \
483
+ }
484
+
485
+static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
216
+{
486
+{
217
+ ShaktiUartState *s = SHAKTI_UART(dev);
487
+ return s->cfg_ptr->ext_zvbb == true &&
218
+
488
+ require_rvv(s) &&
219
+ s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
489
+ vext_check_isa_ill(s) &&
220
+ s->uart_tx = 0x0;
490
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
221
+ s->uart_rx = 0x0;
222
+ s->uart_status = 0x0000;
223
+ s->uart_delay = 0x0000;
224
+ s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
225
+ s->uart_interrupt = 0x0000;
226
+ s->uart_iq_cycles = 0x00;
227
+ s->uart_rx_threshold = 0x00;
228
+}
491
+}
229
+
492
+
230
+static int shakti_uart_can_receive(void *opaque)
493
+GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
494
+GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
495
+GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
496
+GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
497
+GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
498
+GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check)
499
+
500
+static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a)
231
+{
501
+{
232
+ ShaktiUartState *s = opaque;
502
+ return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a);
233
+
234
+ return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
235
+}
503
+}
236
+
504
+
237
+static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
505
+static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
238
+{
506
+{
239
+ ShaktiUartState *s = opaque;
507
+ return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a);
240
+
241
+ s->uart_rx = *buf;
242
+ s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
243
+}
508
+}
244
+
509
+
245
+static void shakti_uart_realize(DeviceState *dev, Error **errp)
510
+/* OPIVI without GVEC IR */
246
+{
511
+#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \
247
+ ShaktiUartState *sus = SHAKTI_UART(dev);
512
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
248
+ qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
513
+ { \
249
+ shakti_uart_receive, NULL, NULL, sus, NULL, true);
514
+ if (CHECK(s, a)) { \
250
+}
515
+ static gen_helper_opivx *const fns[3] = { \
251
+
516
+ gen_helper_##OPIVX##_b, \
252
+static void shakti_uart_instance_init(Object *obj)
517
+ gen_helper_##OPIVX##_h, \
253
+{
518
+ gen_helper_##OPIVX##_w, \
254
+ ShaktiUartState *sus = SHAKTI_UART(obj);
519
+ }; \
255
+ memory_region_init_io(&sus->mmio,
520
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
256
+ obj,
521
+ IMM_MODE); \
257
+ &shakti_uart_ops,
522
+ } \
258
+ sus,
523
+ return false; \
259
+ TYPE_SHAKTI_UART,
524
+ }
260
+ 0x1000);
525
+
261
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
526
+GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
262
+}
527
+GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
263
+
528
+GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
264
+static Property shakti_uart_properties[] = {
265
+ DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
266
+ DEFINE_PROP_END_OF_LIST(),
267
+};
268
+
269
+static void shakti_uart_class_init(ObjectClass *klass, void *data)
270
+{
271
+ DeviceClass *dc = DEVICE_CLASS(klass);
272
+ dc->reset = shakti_uart_reset;
273
+ dc->realize = shakti_uart_realize;
274
+ device_class_set_props(dc, shakti_uart_properties);
275
+}
276
+
277
+static const TypeInfo shakti_uart_info = {
278
+ .name = TYPE_SHAKTI_UART,
279
+ .parent = TYPE_SYS_BUS_DEVICE,
280
+ .instance_size = sizeof(ShaktiUartState),
281
+ .class_init = shakti_uart_class_init,
282
+ .instance_init = shakti_uart_instance_init,
283
+};
284
+
285
+static void shakti_uart_register_types(void)
286
+{
287
+ type_register_static(&shakti_uart_info);
288
+}
289
+type_init(shakti_uart_register_types)
290
diff --git a/MAINTAINERS b/MAINTAINERS
291
index XXXXXXX..XXXXXXX 100644
292
--- a/MAINTAINERS
293
+++ b/MAINTAINERS
294
@@ -XXX,XX +XXX,XX @@ M: Vijai Kumar K <vijai@behindbytes.com>
295
L: qemu-riscv@nongnu.org
296
S: Supported
297
F: hw/riscv/shakti_c.c
298
+F: hw/char/shakti_uart.c
299
F: include/hw/riscv/shakti_c.h
300
+F: include/hw/char/shakti_uart.h
301
302
SiFive Machines
303
M: Alistair Francis <Alistair.Francis@wdc.com>
304
diff --git a/hw/char/meson.build b/hw/char/meson.build
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/char/meson.build
307
+++ b/hw/char/meson.build
308
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
309
softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
310
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
311
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
312
+softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
313
softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
314
softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
315
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
316
diff --git a/hw/char/trace-events b/hw/char/trace-events
317
index XXXXXXX..XXXXXXX 100644
318
--- a/hw/char/trace-events
319
+++ b/hw/char/trace-events
320
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
321
nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
322
nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
323
324
+# shakti_uart.c
325
+shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
326
+shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
327
+
328
# exynos4210_uart.c
329
exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
330
exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
331
--
529
--
332
2.31.1
530
2.41.0
333
334
diff view generated by jsdifflib
[PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro
[PULL v2 16/45] target/riscv: Add Zvkned ISA extension support
1
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
2
3
This commit adds support for the Zvkned vector-crypto extension, which
4
consists of the following instructions:
5
6
* vaesef.[vv,vs]
7
* vaesdf.[vv,vs]
8
* vaesdm.[vv,vs]
9
* vaesz.vs
10
* vaesem.[vv,vs]
11
* vaeskf1.vi
12
* vaeskf2.vi
13
14
Translation functions are defined in
15
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
16
`target/riscv/vcrypto_helper.c`.
17
18
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
19
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
20
[max.chou@sifive.com: Replaced vstart checking by TCG op]
21
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
22
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
23
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
24
Signed-off-by: Max Chou <max.chou@sifive.com>
25
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
[max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
27
property]
28
[max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
29
egs checking by helper function]
30
[max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
31
Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
5
---
33
---
6
target/riscv/cpu.h | 6 ------
34
target/riscv/cpu_cfg.h | 1 +
7
target/riscv/cpu.c | 6 +++++-
35
target/riscv/helper.h | 14 ++
8
2 files changed, 5 insertions(+), 7 deletions(-)
36
target/riscv/insn32.decode | 14 ++
37
target/riscv/cpu.c | 4 +-
38
target/riscv/vcrypto_helper.c | 202 +++++++++++++++++++++++
39
target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++
40
6 files changed, 381 insertions(+), 1 deletion(-)
9
41
10
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
42
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
11
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.h
44
--- a/target/riscv/cpu_cfg.h
13
+++ b/target/riscv/cpu.h
45
+++ b/target/riscv/cpu_cfg.h
46
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
47
bool ext_zve64d;
48
bool ext_zvbb;
49
bool ext_zvbc;
50
+ bool ext_zvkned;
51
bool ext_zmmul;
52
bool ext_zvfbfmin;
53
bool ext_zvfbfwma;
54
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/riscv/helper.h
57
+++ b/target/riscv/helper.h
58
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
59
DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
60
DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
61
DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
62
+
63
+DEF_HELPER_2(egs_check, void, i32, env)
64
+
65
+DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
66
+DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
67
+DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
68
+DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32)
69
+DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32)
70
+DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32)
71
+DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32)
72
+DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
73
+DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
74
+DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
75
+DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
76
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/riscv/insn32.decode
79
+++ b/target/riscv/insn32.decode
14
@@ -XXX,XX +XXX,XX @@
80
@@ -XXX,XX +XXX,XX @@
15
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
81
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
16
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
82
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
17
83
@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
18
-#if defined(TARGET_RISCV32)
84
+@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
19
-#define RVXLEN RV32
85
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
20
-#elif defined(TARGET_RISCV64)
86
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
21
-#define RVXLEN RV64
87
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
22
-#endif
88
@@ -XXX,XX +XXX,XX @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
23
-
89
vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
24
#define RV(x) ((target_ulong)1 << (x - 'A'))
90
vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
25
91
vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
26
#define RVI RV('I')
92
+
93
+# *** Zvkned vector crypto extension ***
94
+vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
95
+vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
96
+vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
97
+vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
98
+vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
99
+vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
100
+vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
101
+vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
102
+vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
103
+vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
104
+vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
27
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
105
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
28
index XXXXXXX..XXXXXXX 100644
106
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/cpu.c
107
--- a/target/riscv/cpu.c
30
+++ b/target/riscv/cpu.c
108
+++ b/target/riscv/cpu.c
31
@@ -XXX,XX +XXX,XX @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
109
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
32
static void riscv_any_cpu_init(Object *obj)
110
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
33
{
111
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
34
CPURISCVState *env = &RISCV_CPU(obj)->env;
112
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
35
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
113
+ ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
36
+#if defined(TARGET_RISCV32)
114
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
37
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
115
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
38
+#elif defined(TARGET_RISCV64)
116
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
39
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
117
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
40
+#endif
118
* In principle Zve*x would also suffice here, were they supported
41
set_priv_version(env, PRIV_VERSION_1_11_0);
119
* in qemu
42
}
120
*/
43
121
- if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
122
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
123
error_setg(errp,
124
"Vector crypto extensions require V or Zve* extensions");
125
return;
126
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
127
/* Vector cryptography extensions */
128
DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
129
DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
130
+ DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
131
132
DEFINE_PROP_END_OF_LIST(),
133
};
134
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
135
index XXXXXXX..XXXXXXX 100644
136
--- a/target/riscv/vcrypto_helper.c
137
+++ b/target/riscv/vcrypto_helper.c
138
@@ -XXX,XX +XXX,XX @@
139
#include "qemu/bitops.h"
140
#include "qemu/bswap.h"
141
#include "cpu.h"
142
+#include "crypto/aes.h"
143
+#include "crypto/aes-round.h"
144
#include "exec/memop.h"
145
#include "exec/exec-all.h"
146
#include "exec/helper-proto.h"
147
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
148
GEN_VEXT_VX(vwsll_vx_b, 2)
149
GEN_VEXT_VX(vwsll_vx_h, 4)
150
GEN_VEXT_VX(vwsll_vx_w, 8)
151
+
152
+void HELPER(egs_check)(uint32_t egs, CPURISCVState *env)
153
+{
154
+ uint32_t vl = env->vl;
155
+ uint32_t vstart = env->vstart;
156
+
157
+ if (vl % egs != 0 || vstart % egs != 0) {
158
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
159
+ }
160
+}
161
+
162
+static inline void xor_round_key(AESState *round_state, AESState *round_key)
163
+{
164
+ round_state->v = round_state->v ^ round_key->v;
165
+}
166
+
167
+#define GEN_ZVKNED_HELPER_VV(NAME, ...) \
168
+ void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
169
+ uint32_t desc) \
170
+ { \
171
+ uint32_t vl = env->vl; \
172
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
173
+ uint32_t vta = vext_vta(desc); \
174
+ \
175
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
176
+ AESState round_key; \
177
+ round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
178
+ round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
179
+ AESState round_state; \
180
+ round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
181
+ round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
182
+ __VA_ARGS__; \
183
+ *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
184
+ *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
185
+ } \
186
+ env->vstart = 0; \
187
+ /* set tail elements to 1s */ \
188
+ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
189
+ }
190
+
191
+#define GEN_ZVKNED_HELPER_VS(NAME, ...) \
192
+ void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
193
+ uint32_t desc) \
194
+ { \
195
+ uint32_t vl = env->vl; \
196
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
197
+ uint32_t vta = vext_vta(desc); \
198
+ \
199
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
200
+ AESState round_key; \
201
+ round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
202
+ round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
203
+ AESState round_state; \
204
+ round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
205
+ round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
206
+ __VA_ARGS__; \
207
+ *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
208
+ *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
209
+ } \
210
+ env->vstart = 0; \
211
+ /* set tail elements to 1s */ \
212
+ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
213
+ }
214
+
215
+GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state,
216
+ &round_state,
217
+ &round_key,
218
+ false);)
219
+GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state,
220
+ &round_state,
221
+ &round_key,
222
+ false);)
223
+GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state,
224
+ &round_state,
225
+ &round_key,
226
+ false);)
227
+GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state,
228
+ &round_state,
229
+ &round_key,
230
+ false);)
231
+GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state,
232
+ &round_state,
233
+ &round_key,
234
+ false);)
235
+GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state,
236
+ &round_state,
237
+ &round_key,
238
+ false);)
239
+GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state,
240
+ &round_state,
241
+ &round_key,
242
+ false);)
243
+GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state,
244
+ &round_state,
245
+ &round_key,
246
+ false);)
247
+GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);)
248
+
249
+void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
250
+ CPURISCVState *env, uint32_t desc)
251
+{
252
+ uint32_t *vd = vd_vptr;
253
+ uint32_t *vs2 = vs2_vptr;
254
+ uint32_t vl = env->vl;
255
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4);
256
+ uint32_t vta = vext_vta(desc);
257
+
258
+ uimm &= 0b1111;
259
+ if (uimm > 10 || uimm == 0) {
260
+ uimm ^= 0b1000;
261
+ }
262
+
263
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
264
+ uint32_t rk[8], tmp;
265
+ static const uint32_t rcon[] = {
266
+ 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
267
+ 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
268
+ };
269
+
270
+ rk[0] = vs2[i * 4 + H4(0)];
271
+ rk[1] = vs2[i * 4 + H4(1)];
272
+ rk[2] = vs2[i * 4 + H4(2)];
273
+ rk[3] = vs2[i * 4 + H4(3)];
274
+ tmp = ror32(rk[3], 8);
275
+
276
+ rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
277
+ ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
278
+ ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
279
+ ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
280
+ ^ rcon[uimm - 1];
281
+ rk[5] = rk[1] ^ rk[4];
282
+ rk[6] = rk[2] ^ rk[5];
283
+ rk[7] = rk[3] ^ rk[6];
284
+
285
+ vd[i * 4 + H4(0)] = rk[4];
286
+ vd[i * 4 + H4(1)] = rk[5];
287
+ vd[i * 4 + H4(2)] = rk[6];
288
+ vd[i * 4 + H4(3)] = rk[7];
289
+ }
290
+ env->vstart = 0;
291
+ /* set tail elements to 1s */
292
+ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
293
+}
294
+
295
+void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
296
+ CPURISCVState *env, uint32_t desc)
297
+{
298
+ uint32_t *vd = vd_vptr;
299
+ uint32_t *vs2 = vs2_vptr;
300
+ uint32_t vl = env->vl;
301
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4);
302
+ uint32_t vta = vext_vta(desc);
303
+
304
+ uimm &= 0b1111;
305
+ if (uimm > 14 || uimm < 2) {
306
+ uimm ^= 0b1000;
307
+ }
308
+
309
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
310
+ uint32_t rk[12], tmp;
311
+ static const uint32_t rcon[] = {
312
+ 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
313
+ 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
314
+ };
315
+
316
+ rk[0] = vd[i * 4 + H4(0)];
317
+ rk[1] = vd[i * 4 + H4(1)];
318
+ rk[2] = vd[i * 4 + H4(2)];
319
+ rk[3] = vd[i * 4 + H4(3)];
320
+ rk[4] = vs2[i * 4 + H4(0)];
321
+ rk[5] = vs2[i * 4 + H4(1)];
322
+ rk[6] = vs2[i * 4 + H4(2)];
323
+ rk[7] = vs2[i * 4 + H4(3)];
324
+
325
+ if (uimm % 2 == 0) {
326
+ tmp = ror32(rk[7], 8);
327
+ rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
328
+ ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
329
+ ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
330
+ ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
331
+ ^ rcon[(uimm - 1) / 2];
332
+ } else {
333
+ rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) |
334
+ ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) |
335
+ ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) |
336
+ ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0));
337
+ }
338
+ rk[9] = rk[1] ^ rk[8];
339
+ rk[10] = rk[2] ^ rk[9];
340
+ rk[11] = rk[3] ^ rk[10];
341
+
342
+ vd[i * 4 + H4(0)] = rk[8];
343
+ vd[i * 4 + H4(1)] = rk[9];
344
+ vd[i * 4 + H4(2)] = rk[10];
345
+ vd[i * 4 + H4(3)] = rk[11];
346
+ }
347
+ env->vstart = 0;
348
+ /* set tail elements to 1s */
349
+ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
350
+}
351
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
352
index XXXXXXX..XXXXXXX 100644
353
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
354
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
355
@@ -XXX,XX +XXX,XX @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
356
GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
357
GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
358
GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
359
+
360
+/*
361
+ * Zvkned
362
+ */
363
+
364
+#define ZVKNED_EGS 4
365
+
366
+#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) \
367
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
368
+ { \
369
+ if (CHECK(s, a)) { \
370
+ TCGv_ptr rd_v, rs2_v; \
371
+ TCGv_i32 desc, egs; \
372
+ uint32_t data = 0; \
373
+ TCGLabel *over = gen_new_label(); \
374
+ \
375
+ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
376
+ /* save opcode for unwinding in case we throw an exception */ \
377
+ decode_save_opc(s); \
378
+ egs = tcg_constant_i32(EGS); \
379
+ gen_helper_egs_check(egs, cpu_env); \
380
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
381
+ } \
382
+ \
383
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
384
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
385
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
386
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
387
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
388
+ rd_v = tcg_temp_new_ptr(); \
389
+ rs2_v = tcg_temp_new_ptr(); \
390
+ desc = tcg_constant_i32( \
391
+ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
392
+ tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
393
+ tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
394
+ gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \
395
+ mark_vs_dirty(s); \
396
+ gen_set_label(over); \
397
+ return true; \
398
+ } \
399
+ return false; \
400
+ }
401
+
402
+static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
403
+{
404
+ int egw_bytes = ZVKNED_EGS << s->sew;
405
+ return s->cfg_ptr->ext_zvkned == true &&
406
+ require_rvv(s) &&
407
+ vext_check_isa_ill(s) &&
408
+ MAXSZ(s) >= egw_bytes &&
409
+ require_align(a->rd, s->lmul) &&
410
+ require_align(a->rs2, s->lmul) &&
411
+ s->sew == MO_32;
412
+}
413
+
414
+static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
415
+{
416
+ int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
417
+ return !is_overlapped(vd, op_size, vs2, 1);
418
+}
419
+
420
+static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
421
+{
422
+ int egw_bytes = ZVKNED_EGS << s->sew;
423
+ return vaes_check_overlap(s, a->rd, a->rs2) &&
424
+ MAXSZ(s) >= egw_bytes &&
425
+ s->cfg_ptr->ext_zvkned == true &&
426
+ require_rvv(s) &&
427
+ vext_check_isa_ill(s) &&
428
+ require_align(a->rd, s->lmul) &&
429
+ s->sew == MO_32;
430
+}
431
+
432
+GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS)
433
+GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS)
434
+GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS)
435
+GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS)
436
+GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS)
437
+GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS)
438
+GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS)
439
+GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS)
440
+GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
441
+
442
+#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) \
443
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
444
+ { \
445
+ if (CHECK(s, a)) { \
446
+ TCGv_ptr rd_v, rs2_v; \
447
+ TCGv_i32 uimm_v, desc, egs; \
448
+ uint32_t data = 0; \
449
+ TCGLabel *over = gen_new_label(); \
450
+ \
451
+ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
452
+ /* save opcode for unwinding in case we throw an exception */ \
453
+ decode_save_opc(s); \
454
+ egs = tcg_constant_i32(EGS); \
455
+ gen_helper_egs_check(egs, cpu_env); \
456
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
457
+ } \
458
+ \
459
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
460
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
461
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
462
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
463
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
464
+ \
465
+ rd_v = tcg_temp_new_ptr(); \
466
+ rs2_v = tcg_temp_new_ptr(); \
467
+ uimm_v = tcg_constant_i32(a->rs1); \
468
+ desc = tcg_constant_i32( \
469
+ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
470
+ tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
471
+ tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
472
+ gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \
473
+ mark_vs_dirty(s); \
474
+ gen_set_label(over); \
475
+ return true; \
476
+ } \
477
+ return false; \
478
+ }
479
+
480
+static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
481
+{
482
+ int egw_bytes = ZVKNED_EGS << s->sew;
483
+ return s->cfg_ptr->ext_zvkned == true &&
484
+ require_rvv(s) &&
485
+ vext_check_isa_ill(s) &&
486
+ MAXSZ(s) >= egw_bytes &&
487
+ s->sew == MO_32 &&
488
+ require_align(a->rd, s->lmul) &&
489
+ require_align(a->rs2, s->lmul);
490
+}
491
+
492
+static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
493
+{
494
+ int egw_bytes = ZVKNED_EGS << s->sew;
495
+ return s->cfg_ptr->ext_zvkned == true &&
496
+ require_rvv(s) &&
497
+ vext_check_isa_ill(s) &&
498
+ MAXSZ(s) >= egw_bytes &&
499
+ s->sew == MO_32 &&
500
+ require_align(a->rd, s->lmul) &&
501
+ require_align(a->rs2, s->lmul);
502
+}
503
+
504
+GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
505
+GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
44
--
506
--
45
2.31.1
507
2.41.0
46
47
diff view generated by jsdifflib
[PULL 25/42] target/riscv: Add a config option for ePMP
[PULL v2 17/45] target/riscv: Add Zvknh ISA extension support
1
From: Hou Weiying <weiying_hou@outlook.com>
1
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
2
2
3
Add a config option to enable experimental support for ePMP. This
3
This commit adds support for the Zvknh vector-crypto extension, which
4
is disabled by default and can be enabled with 'x-epmp=true'.
4
consists of the following instructions:
5
5
6
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
6
* vsha2ms.vv
7
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
7
* vsha2c[hl].vv
8
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
8
9
Translation functions are defined in
10
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
11
`target/riscv/vcrypto_helper.c`.
12
13
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
14
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
15
[max.chou@sifive.com: Replaced vstart checking by TCG op]
16
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
17
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
18
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
19
Signed-off-by: Max Chou <max.chou@sifive.com>
20
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
[max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
22
[max.chou@sifive.com: Replaced SEW selection to happened during
23
translation]
24
Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
14
---
26
---
15
target/riscv/cpu.h | 1 +
27
target/riscv/cpu_cfg.h | 2 +
16
target/riscv/cpu.c | 10 ++++++++++
28
target/riscv/helper.h | 6 +
17
2 files changed, 11 insertions(+)
29
target/riscv/insn32.decode | 5 +
30
target/riscv/cpu.c | 13 +-
31
target/riscv/vcrypto_helper.c | 238 +++++++++++++++++++++++
32
target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++
33
6 files changed, 390 insertions(+), 3 deletions(-)
18
34
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
35
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
20
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
37
--- a/target/riscv/cpu_cfg.h
22
+++ b/target/riscv/cpu.h
38
+++ b/target/riscv/cpu_cfg.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
39
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
uint16_t elen;
40
bool ext_zvbb;
25
bool mmu;
41
bool ext_zvbc;
26
bool pmp;
42
bool ext_zvkned;
27
+ bool epmp;
43
+ bool ext_zvknha;
28
uint64_t resetvec;
44
+ bool ext_zvknhb;
29
} cfg;
45
bool ext_zmmul;
30
};
46
bool ext_zvfbfmin;
47
bool ext_zvfbfwma;
48
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/helper.h
51
+++ b/target/riscv/helper.h
52
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
53
DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
54
DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
55
DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
56
+
57
+DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32)
58
+DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
59
+DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
60
+DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
61
+DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
62
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/riscv/insn32.decode
65
+++ b/target/riscv/insn32.decode
66
@@ -XXX,XX +XXX,XX @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
67
vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
68
vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
69
vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
70
+
71
+# *** Zvknh vector crypto extension ***
72
+vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
73
+vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
74
+vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
75
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
77
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
78
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
79
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
36
80
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
37
if (cpu->cfg.pmp) {
81
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
38
set_feature(env, RISCV_FEATURE_PMP);
82
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
39
+
83
+ ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
40
+ /*
84
+ ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
41
+ * Enhanced PMP should only be available
85
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
42
+ * on harts with PMP support
86
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
43
+ */
87
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
44
+ if (cpu->cfg.epmp) {
88
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
45
+ set_feature(env, RISCV_FEATURE_EPMP);
89
* In principle Zve*x would also suffice here, were they supported
46
+ }
90
* in qemu
91
*/
92
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
93
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
94
+ !cpu->cfg.ext_zve32f) {
95
error_setg(errp,
96
"Vector crypto extensions require V or Zve* extensions");
97
return;
47
}
98
}
48
99
49
set_resetvec(env, cpu->cfg.resetvec);
100
- if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) {
50
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
101
- error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions");
51
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
102
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
52
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
103
+ error_setg(
53
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
104
+ errp,
54
+ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
105
+ "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
55
+
106
return;
56
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
107
}
108
109
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
110
DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
111
DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
112
DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
113
+ DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
114
+ DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
115
57
DEFINE_PROP_END_OF_LIST(),
116
DEFINE_PROP_END_OF_LIST(),
58
};
117
};
118
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/vcrypto_helper.c
121
+++ b/target/riscv/vcrypto_helper.c
122
@@ -XXX,XX +XXX,XX @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
123
/* set tail elements to 1s */
124
vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
125
}
126
+
127
+static inline uint32_t sig0_sha256(uint32_t x)
128
+{
129
+ return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3);
130
+}
131
+
132
+static inline uint32_t sig1_sha256(uint32_t x)
133
+{
134
+ return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
135
+}
136
+
137
+static inline uint64_t sig0_sha512(uint64_t x)
138
+{
139
+ return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7);
140
+}
141
+
142
+static inline uint64_t sig1_sha512(uint64_t x)
143
+{
144
+ return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
145
+}
146
+
147
+static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2)
148
+{
149
+ uint32_t res[4];
150
+ res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) +
151
+ vd[H4(0)];
152
+ res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) +
153
+ vd[H4(1)];
154
+ res[2] =
155
+ sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(2)];
156
+ res[3] =
157
+ sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)];
158
+ vd[H4(3)] = res[3];
159
+ vd[H4(2)] = res[2];
160
+ vd[H4(1)] = res[1];
161
+ vd[H4(0)] = res[0];
162
+}
163
+
164
+static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2)
165
+{
166
+ uint64_t res[4];
167
+ res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0];
168
+ res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1];
169
+ res[2] = sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2];
170
+ res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3];
171
+ vd[3] = res[3];
172
+ vd[2] = res[2];
173
+ vd[1] = res[1];
174
+ vd[0] = res[0];
175
+}
176
+
177
+void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
178
+ uint32_t desc)
179
+{
180
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
181
+ uint32_t esz = sew == MO_32 ? 4 : 8;
182
+ uint32_t total_elems;
183
+ uint32_t vta = vext_vta(desc);
184
+
185
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
186
+ if (sew == MO_32) {
187
+ vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4,
188
+ ((uint32_t *)vs2) + i * 4);
189
+ } else {
190
+ /* If not 32 then SEW should be 64 */
191
+ vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4,
192
+ ((uint64_t *)vs2) + i * 4);
193
+ }
194
+ }
195
+ /* set tail elements to 1s */
196
+ total_elems = vext_get_total_elems(env, desc, esz);
197
+ vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
198
+ env->vstart = 0;
199
+}
200
+
201
+static inline uint64_t sum0_64(uint64_t x)
202
+{
203
+ return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39);
204
+}
205
+
206
+static inline uint32_t sum0_32(uint32_t x)
207
+{
208
+ return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22);
209
+}
210
+
211
+static inline uint64_t sum1_64(uint64_t x)
212
+{
213
+ return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41);
214
+}
215
+
216
+static inline uint32_t sum1_32(uint32_t x)
217
+{
218
+ return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25);
219
+}
220
+
221
+#define ch(x, y, z) ((x & y) ^ ((~x) & z))
222
+
223
+#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
224
+
225
+static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1)
226
+{
227
+ uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0];
228
+ uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0];
229
+ uint64_t W0 = vs1[0], W1 = vs1[1];
230
+ uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0;
231
+ uint64_t T2 = sum0_64(a) + maj(a, b, c);
232
+
233
+ h = g;
234
+ g = f;
235
+ f = e;
236
+ e = d + T1;
237
+ d = c;
238
+ c = b;
239
+ b = a;
240
+ a = T1 + T2;
241
+
242
+ T1 = h + sum1_64(e) + ch(e, f, g) + W1;
243
+ T2 = sum0_64(a) + maj(a, b, c);
244
+ h = g;
245
+ g = f;
246
+ f = e;
247
+ e = d + T1;
248
+ d = c;
249
+ c = b;
250
+ b = a;
251
+ a = T1 + T2;
252
+
253
+ vd[0] = f;
254
+ vd[1] = e;
255
+ vd[2] = b;
256
+ vd[3] = a;
257
+}
258
+
259
+static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1)
260
+{
261
+ uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)];
262
+ uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)];
263
+ uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)];
264
+ uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0;
265
+ uint32_t T2 = sum0_32(a) + maj(a, b, c);
266
+
267
+ h = g;
268
+ g = f;
269
+ f = e;
270
+ e = d + T1;
271
+ d = c;
272
+ c = b;
273
+ b = a;
274
+ a = T1 + T2;
275
+
276
+ T1 = h + sum1_32(e) + ch(e, f, g) + W1;
277
+ T2 = sum0_32(a) + maj(a, b, c);
278
+ h = g;
279
+ g = f;
280
+ f = e;
281
+ e = d + T1;
282
+ d = c;
283
+ c = b;
284
+ b = a;
285
+ a = T1 + T2;
286
+
287
+ vd[H4(0)] = f;
288
+ vd[H4(1)] = e;
289
+ vd[H4(2)] = b;
290
+ vd[H4(3)] = a;
291
+}
292
+
293
+void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
294
+ uint32_t desc)
295
+{
296
+ const uint32_t esz = 4;
297
+ uint32_t total_elems;
298
+ uint32_t vta = vext_vta(desc);
299
+
300
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
301
+ vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
302
+ ((uint32_t *)vs1) + 4 * i + 2);
303
+ }
304
+
305
+ /* set tail elements to 1s */
306
+ total_elems = vext_get_total_elems(env, desc, esz);
307
+ vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
308
+ env->vstart = 0;
309
+}
310
+
311
+void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
312
+ uint32_t desc)
313
+{
314
+ const uint32_t esz = 8;
315
+ uint32_t total_elems;
316
+ uint32_t vta = vext_vta(desc);
317
+
318
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
319
+ vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
320
+ ((uint64_t *)vs1) + 4 * i + 2);
321
+ }
322
+
323
+ /* set tail elements to 1s */
324
+ total_elems = vext_get_total_elems(env, desc, esz);
325
+ vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
326
+ env->vstart = 0;
327
+}
328
+
329
+void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
330
+ uint32_t desc)
331
+{
332
+ const uint32_t esz = 4;
333
+ uint32_t total_elems;
334
+ uint32_t vta = vext_vta(desc);
335
+
336
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
337
+ vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
338
+ (((uint32_t *)vs1) + 4 * i));
339
+ }
340
+
341
+ /* set tail elements to 1s */
342
+ total_elems = vext_get_total_elems(env, desc, esz);
343
+ vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
344
+ env->vstart = 0;
345
+}
346
+
347
+void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
348
+ uint32_t desc)
349
+{
350
+ uint32_t esz = 8;
351
+ uint32_t total_elems;
352
+ uint32_t vta = vext_vta(desc);
353
+
354
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
355
+ vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
356
+ (((uint64_t *)vs1) + 4 * i));
357
+ }
358
+
359
+ /* set tail elements to 1s */
360
+ total_elems = vext_get_total_elems(env, desc, esz);
361
+ vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
362
+ env->vstart = 0;
363
+}
364
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
365
index XXXXXXX..XXXXXXX 100644
366
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
367
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
368
@@ -XXX,XX +XXX,XX @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
369
370
GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
371
GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
372
+
373
+/*
374
+ * Zvknh
375
+ */
376
+
377
+#define ZVKNH_EGS 4
378
+
379
+#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS) \
380
+ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
381
+ { \
382
+ if (CHECK(s, a)) { \
383
+ uint32_t data = 0; \
384
+ TCGLabel *over = gen_new_label(); \
385
+ TCGv_i32 egs; \
386
+ \
387
+ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
388
+ /* save opcode for unwinding in case we throw an exception */ \
389
+ decode_save_opc(s); \
390
+ egs = tcg_constant_i32(EGS); \
391
+ gen_helper_egs_check(egs, cpu_env); \
392
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
393
+ } \
394
+ \
395
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
396
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
397
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
398
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
399
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
400
+ \
401
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \
402
+ vreg_ofs(s, a->rs2), cpu_env, \
403
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
404
+ data, gen_helper_##NAME); \
405
+ \
406
+ mark_vs_dirty(s); \
407
+ gen_set_label(over); \
408
+ return true; \
409
+ } \
410
+ return false; \
411
+ }
412
+
413
+static bool vsha_check_sew(DisasContext *s)
414
+{
415
+ return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) ||
416
+ (s->cfg_ptr->ext_zvknhb == true &&
417
+ (s->sew == MO_32 || s->sew == MO_64));
418
+}
419
+
420
+static bool vsha_check(DisasContext *s, arg_rmrr *a)
421
+{
422
+ int egw_bytes = ZVKNH_EGS << s->sew;
423
+ int mult = 1 << MAX(s->lmul, 0);
424
+ return opivv_check(s, a) &&
425
+ vsha_check_sew(s) &&
426
+ MAXSZ(s) >= egw_bytes &&
427
+ !is_overlapped(a->rd, mult, a->rs1, mult) &&
428
+ !is_overlapped(a->rd, mult, a->rs2, mult) &&
429
+ s->lmul >= 0;
430
+}
431
+
432
+GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)
433
+
434
+static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
435
+{
436
+ if (vsha_check(s, a)) {
437
+ uint32_t data = 0;
438
+ TCGLabel *over = gen_new_label();
439
+ TCGv_i32 egs;
440
+
441
+ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
442
+ /* save opcode for unwinding in case we throw an exception */
443
+ decode_save_opc(s);
444
+ egs = tcg_constant_i32(ZVKNH_EGS);
445
+ gen_helper_egs_check(egs, cpu_env);
446
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
447
+ }
448
+
449
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
450
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
451
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
452
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
453
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
454
+
455
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
456
+ vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
457
+ s->cfg_ptr->vlen / 8, data,
458
+ s->sew == MO_32 ?
459
+ gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
460
+
461
+ mark_vs_dirty(s);
462
+ gen_set_label(over);
463
+ return true;
464
+ }
465
+ return false;
466
+}
467
+
468
+static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
469
+{
470
+ if (vsha_check(s, a)) {
471
+ uint32_t data = 0;
472
+ TCGLabel *over = gen_new_label();
473
+ TCGv_i32 egs;
474
+
475
+ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
476
+ /* save opcode for unwinding in case we throw an exception */
477
+ decode_save_opc(s);
478
+ egs = tcg_constant_i32(ZVKNH_EGS);
479
+ gen_helper_egs_check(egs, cpu_env);
480
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
481
+ }
482
+
483
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
484
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
485
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
486
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
487
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
488
+
489
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
490
+ vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
491
+ s->cfg_ptr->vlen / 8, data,
492
+ s->sew == MO_32 ?
493
+ gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
494
+
495
+ mark_vs_dirty(s);
496
+ gen_set_label(over);
497
+ return true;
498
+ }
499
+ return false;
500
+}
59
--
501
--
60
2.31.1
502
2.41.0
61
62
diff view generated by jsdifflib
[PULL 42/42] target/riscv: Fix the RV64H decode comment
[PULL v2 18/45] target/riscv: Add Zvksh ISA extension support
1
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
1
From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
2
3
This commit adds support for the Zvksh vector-crypto extension, which
4
consists of the following instructions:
5
6
* vsm3me.vv
7
* vsm3c.vi
8
9
Translation functions are defined in
10
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
11
`target/riscv/vcrypto_helper.c`.
12
13
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
14
[max.chou@sifive.com: Replaced vstart checking by TCG op]
15
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
16
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
17
Signed-off-by: Max Chou <max.chou@sifive.com>
18
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
19
[max.chou@sifive.com: Exposed x-zvksh property]
20
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
2
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
5
---
22
---
6
target/riscv/insn32.decode | 2 +-
23
target/riscv/cpu_cfg.h | 1 +
7
1 file changed, 1 insertion(+), 1 deletion(-)
24
target/riscv/helper.h | 3 +
8
25
target/riscv/insn32.decode | 4 +
26
target/riscv/cpu.c | 6 +-
27
target/riscv/vcrypto_helper.c | 134 +++++++++++++++++++++++
28
target/riscv/insn_trans/trans_rvvk.c.inc | 31 ++++++
29
6 files changed, 177 insertions(+), 2 deletions(-)
30
31
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu_cfg.h
34
+++ b/target/riscv/cpu_cfg.h
35
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
36
bool ext_zvkned;
37
bool ext_zvknha;
38
bool ext_zvknhb;
39
+ bool ext_zvksh;
40
bool ext_zmmul;
41
bool ext_zvfbfmin;
42
bool ext_zvfbfwma;
43
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/helper.h
46
+++ b/target/riscv/helper.h
47
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
48
DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
49
DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
50
DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
51
+
52
+DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
53
+DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
9
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
54
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
10
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
11
--- a/target/riscv/insn32.decode
56
--- a/target/riscv/insn32.decode
12
+++ b/target/riscv/insn32.decode
57
+++ b/target/riscv/insn32.decode
13
@@ -XXX,XX +XXX,XX @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
58
@@ -XXX,XX +XXX,XX @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
14
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
59
vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
15
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
60
vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
16
61
vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
17
-# *** RV32H Base Instruction Set ***
62
+
18
+# *** RV64H Base Instruction Set ***
63
+# *** Zvksh vector crypto extension ***
19
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
64
+vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
20
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
65
+vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
21
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
66
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/cpu.c
69
+++ b/target/riscv/cpu.c
70
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
71
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
72
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
73
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
74
+ ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
75
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
76
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
77
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
78
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
79
* In principle Zve*x would also suffice here, were they supported
80
* in qemu
81
*/
82
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
83
- !cpu->cfg.ext_zve32f) {
84
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
85
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
86
error_setg(errp,
87
"Vector crypto extensions require V or Zve* extensions");
88
return;
89
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
90
DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
91
DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
92
DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
93
+ DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
94
95
DEFINE_PROP_END_OF_LIST(),
96
};
97
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/target/riscv/vcrypto_helper.c
100
+++ b/target/riscv/vcrypto_helper.c
101
@@ -XXX,XX +XXX,XX @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
102
vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
103
env->vstart = 0;
104
}
105
+
106
+static inline uint32_t p1(uint32_t x)
107
+{
108
+ return x ^ rol32(x, 15) ^ rol32(x, 23);
109
+}
110
+
111
+static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3,
112
+ uint32_t m13, uint32_t m6)
113
+{
114
+ return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6;
115
+}
116
+
117
+void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
118
+ CPURISCVState *env, uint32_t desc)
119
+{
120
+ uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
121
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
122
+ uint32_t vta = vext_vta(desc);
123
+ uint32_t *vd = vd_vptr;
124
+ uint32_t *vs1 = vs1_vptr;
125
+ uint32_t *vs2 = vs2_vptr;
126
+
127
+ for (int i = env->vstart / 8; i < env->vl / 8; i++) {
128
+ uint32_t w[24];
129
+ for (int j = 0; j < 8; j++) {
130
+ w[j] = bswap32(vs1[H4((i * 8) + j)]);
131
+ w[j + 8] = bswap32(vs2[H4((i * 8) + j)]);
132
+ }
133
+ for (int j = 0; j < 8; j++) {
134
+ w[j + 16] =
135
+ zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]);
136
+ }
137
+ for (int j = 0; j < 8; j++) {
138
+ vd[(i * 8) + j] = bswap32(w[H4(j + 16)]);
139
+ }
140
+ }
141
+ vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
142
+ env->vstart = 0;
143
+}
144
+
145
+static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z)
146
+{
147
+ return x ^ y ^ z;
148
+}
149
+
150
+static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z)
151
+{
152
+ return (x & y) | (x & z) | (y & z);
153
+}
154
+
155
+static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
156
+{
157
+ return (j <= 15) ? ff1(x, y, z) : ff2(x, y, z);
158
+}
159
+
160
+static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z)
161
+{
162
+ return x ^ y ^ z;
163
+}
164
+
165
+static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z)
166
+{
167
+ return (x & y) | (~x & z);
168
+}
169
+
170
+static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
171
+{
172
+ return (j <= 15) ? gg1(x, y, z) : gg2(x, y, z);
173
+}
174
+
175
+static inline uint32_t t_j(uint32_t j)
176
+{
177
+ return (j <= 15) ? 0x79cc4519 : 0x7a879d8a;
178
+}
179
+
180
+static inline uint32_t p_0(uint32_t x)
181
+{
182
+ return x ^ rol32(x, 9) ^ rol32(x, 17);
183
+}
184
+
185
+static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm)
186
+{
187
+ uint32_t x0, x1;
188
+ uint32_t j;
189
+ uint32_t ss1, ss2, tt1, tt2;
190
+ x0 = vs2[0] ^ vs2[4];
191
+ x1 = vs2[1] ^ vs2[5];
192
+ j = 2 * uimm;
193
+ ss1 = rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7);
194
+ ss2 = ss1 ^ rol32(vs1[0], 12);
195
+ tt1 = ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0;
196
+ tt2 = gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0];
197
+ vs1[3] = vs1[2];
198
+ vd[3] = rol32(vs1[1], 9);
199
+ vs1[1] = vs1[0];
200
+ vd[1] = tt1;
201
+ vs1[7] = vs1[6];
202
+ vd[7] = rol32(vs1[5], 19);
203
+ vs1[5] = vs1[4];
204
+ vd[5] = p_0(tt2);
205
+ j = 2 * uimm + 1;
206
+ ss1 = rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7);
207
+ ss2 = ss1 ^ rol32(vd[1], 12);
208
+ tt1 = ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1;
209
+ tt2 = gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1];
210
+ vd[2] = rol32(vs1[1], 9);
211
+ vd[0] = tt1;
212
+ vd[6] = rol32(vs1[5], 19);
213
+ vd[4] = p_0(tt2);
214
+}
215
+
216
+void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
217
+ CPURISCVState *env, uint32_t desc)
218
+{
219
+ uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
220
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
221
+ uint32_t vta = vext_vta(desc);
222
+ uint32_t *vd = vd_vptr;
223
+ uint32_t *vs2 = vs2_vptr;
224
+ uint32_t v1[8], v2[8], v3[8];
225
+
226
+ for (int i = env->vstart / 8; i < env->vl / 8; i++) {
227
+ for (int k = 0; k < 8; k++) {
228
+ v2[k] = bswap32(vd[H4(i * 8 + k)]);
229
+ v3[k] = bswap32(vs2[H4(i * 8 + k)]);
230
+ }
231
+ sm3c(v1, v2, v3, uimm);
232
+ for (int k = 0; k < 8; k++) {
233
+ vd[i * 8 + k] = bswap32(v1[H4(k)]);
234
+ }
235
+ }
236
+ vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
237
+ env->vstart = 0;
238
+}
239
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
240
index XXXXXXX..XXXXXXX 100644
241
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
242
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
243
@@ -XXX,XX +XXX,XX @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
244
}
245
return false;
246
}
247
+
248
+/*
249
+ * Zvksh
250
+ */
251
+
252
+#define ZVKSH_EGS 8
253
+
254
+static inline bool vsm3_check(DisasContext *s, arg_rmrr *a)
255
+{
256
+ int egw_bytes = ZVKSH_EGS << s->sew;
257
+ int mult = 1 << MAX(s->lmul, 0);
258
+ return s->cfg_ptr->ext_zvksh == true &&
259
+ require_rvv(s) &&
260
+ vext_check_isa_ill(s) &&
261
+ !is_overlapped(a->rd, mult, a->rs2, mult) &&
262
+ MAXSZ(s) >= egw_bytes &&
263
+ s->sew == MO_32;
264
+}
265
+
266
+static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a)
267
+{
268
+ return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
269
+}
270
+
271
+static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
272
+{
273
+ return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm);
274
+}
275
+
276
+GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS)
277
+GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS)
22
--
278
--
23
2.31.1
279
2.41.0
24
25
diff view generated by jsdifflib
[PULL 24/42] target/riscv: Implementation of enhanced PMP (ePMP)
[PULL v2 19/45] target/riscv: Add Zvkg ISA extension support
1
From: Hou Weiying <weiying_hou@outlook.com>
1
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
2
2
3
This commit adds support for ePMP v0.9.1.
3
This commit adds support for the Zvkg vector-crypto extension, which
4
4
consists of the following instructions:
5
The ePMP spec can be found in:
5
6
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
6
* vgmul.vv
7
7
* vghsh.vv
8
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
8
9
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
9
Translation functions are defined in
10
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
10
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
`target/riscv/vcrypto_helper.c`.
12
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
13
Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
13
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
14
[ Changes by AF:
14
[max.chou@sifive.com: Replaced vstart checking by TCG op]
15
- Rebase on master
15
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
16
- Update to latest spec
16
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
17
- Use a switch case to handle ePMP MML permissions
17
Signed-off-by: Max Chou <max.chou@sifive.com>
18
- Fix a few bugs
18
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
19
]
19
[max.chou@sifive.com: Exposed x-zvkg property]
20
[max.chou@sifive.com: Replaced uint by int for cross win32 build]
21
Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
---
23
---
22
target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
24
target/riscv/cpu_cfg.h | 1 +
23
1 file changed, 146 insertions(+), 8 deletions(-)
25
target/riscv/helper.h | 3 +
24
26
target/riscv/insn32.decode | 4 ++
25
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
27
target/riscv/cpu.c | 6 +-
26
index XXXXXXX..XXXXXXX 100644
28
target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++
27
--- a/target/riscv/pmp.c
29
target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++
28
+++ b/target/riscv/pmp.c
30
6 files changed, 114 insertions(+), 2 deletions(-)
29
@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
31
30
static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
32
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
31
{
33
index XXXXXXX..XXXXXXX 100644
32
if (pmp_index < MAX_RISCV_PMPS) {
34
--- a/target/riscv/cpu_cfg.h
33
- if (!pmp_is_locked(env, pmp_index)) {
35
+++ b/target/riscv/cpu_cfg.h
34
- env->pmp_state.pmp[pmp_index].cfg_reg = val;
36
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
35
- pmp_update_rule(env, pmp_index);
37
bool ext_zve64d;
36
+ bool locked = true;
38
bool ext_zvbb;
37
+
39
bool ext_zvbc;
38
+ if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
40
+ bool ext_zvkg;
39
+ /* mseccfg.RLB is set */
41
bool ext_zvkned;
40
+ if (MSECCFG_RLB_ISSET(env)) {
42
bool ext_zvknha;
41
+ locked = false;
43
bool ext_zvknhb;
42
+ }
44
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
43
+
45
index XXXXXXX..XXXXXXX 100644
44
+ /* mseccfg.MML is not set */
46
--- a/target/riscv/helper.h
45
+ if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index)) {
47
+++ b/target/riscv/helper.h
46
+ locked = false;
48
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
47
+ }
49
48
+
50
DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
49
+ /* mseccfg.MML is set */
51
DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
50
+ if (MSECCFG_MML_ISSET(env)) {
52
+
51
+ /* not adding execute bit */
53
+DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32)
52
+ if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) {
54
+DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32)
53
+ locked = false;
55
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
54
+ }
56
index XXXXXXX..XXXXXXX 100644
55
+ /* shared region and not adding X bit */
57
--- a/target/riscv/insn32.decode
56
+ if ((val & PMP_LOCK) != PMP_LOCK &&
58
+++ b/target/riscv/insn32.decode
57
+ (val & 0x7) != (PMP_WRITE | PMP_EXEC)) {
59
@@ -XXX,XX +XXX,XX @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
58
+ locked = false;
60
# *** Zvksh vector crypto extension ***
59
+ }
61
vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
60
+ }
62
vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
61
} else {
63
+
62
+ if (!pmp_is_locked(env, pmp_index)) {
64
+# *** Zvkg vector crypto extension ***
63
+ locked = false;
65
+vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
66
+vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
67
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/riscv/cpu.c
70
+++ b/target/riscv/cpu.c
71
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
72
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
73
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
74
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
75
+ ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
76
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
77
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
78
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
79
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
80
* In principle Zve*x would also suffice here, were they supported
81
* in qemu
82
*/
83
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
84
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
85
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
86
+ cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
87
error_setg(errp,
88
"Vector crypto extensions require V or Zve* extensions");
89
return;
90
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
91
/* Vector cryptography extensions */
92
DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
93
DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
94
+ DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
95
DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
96
DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
97
DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
98
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/riscv/vcrypto_helper.c
101
+++ b/target/riscv/vcrypto_helper.c
102
@@ -XXX,XX +XXX,XX @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
103
vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
104
env->vstart = 0;
105
}
106
+
107
+void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
108
+ CPURISCVState *env, uint32_t desc)
109
+{
110
+ uint64_t *vd = vd_vptr;
111
+ uint64_t *vs1 = vs1_vptr;
112
+ uint64_t *vs2 = vs2_vptr;
113
+ uint32_t vta = vext_vta(desc);
114
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4);
115
+
116
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
117
+ uint64_t Y[2] = {vd[i * 2 + 0], vd[i * 2 + 1]};
118
+ uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])};
119
+ uint64_t X[2] = {vs1[i * 2 + 0], vs1[i * 2 + 1]};
120
+ uint64_t Z[2] = {0, 0};
121
+
122
+ uint64_t S[2] = {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])};
123
+
124
+ for (int j = 0; j < 128; j++) {
125
+ if ((S[j / 64] >> (j % 64)) & 1) {
126
+ Z[0] ^= H[0];
127
+ Z[1] ^= H[1];
128
+ }
129
+ bool reduce = ((H[1] >> 63) & 1);
130
+ H[1] = H[1] << 1 | H[0] >> 63;
131
+ H[0] = H[0] << 1;
132
+ if (reduce) {
133
+ H[0] ^= 0x87;
64
+ }
134
+ }
65
+ }
135
+ }
66
+
136
+
67
+ if (locked) {
137
+ vd[i * 2 + 0] = brev8(Z[0]);
68
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
138
+ vd[i * 2 + 1] = brev8(Z[1]);
69
+ } else {
139
+ }
70
+ env->pmp_state.pmp[pmp_index].cfg_reg = val;
140
+ /* set tail elements to 1s */
71
+ pmp_update_rule(env, pmp_index);
141
+ vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
72
}
142
+ env->vstart = 0;
73
} else {
143
+}
74
qemu_log_mask(LOG_GUEST_ERROR,
144
+
75
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
145
+void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env,
76
{
146
+ uint32_t desc)
77
bool ret;
147
+{
78
148
+ uint64_t *vd = vd_vptr;
79
+ if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
149
+ uint64_t *vs2 = vs2_vptr;
80
+ if (MSECCFG_MMWP_ISSET(env)) {
150
+ uint32_t vta = vext_vta(desc);
81
+ /*
151
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4);
82
+ * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
152
+
83
+ * so we default to deny all, even for M-mode.
153
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
84
+ */
154
+ uint64_t Y[2] = {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])};
85
+ *allowed_privs = 0;
155
+ uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])};
86
+ return false;
156
+ uint64_t Z[2] = {0, 0};
87
+ } else if (MSECCFG_MML_ISSET(env)) {
157
+
88
+ /*
158
+ for (int j = 0; j < 128; j++) {
89
+ * The Machine Mode Lockdown (mseccfg.MML) bit is set
159
+ if ((Y[j / 64] >> (j % 64)) & 1) {
90
+ * so we can only execute code in M-mode with an applicable
160
+ Z[0] ^= H[0];
91
+ * rule. Other modes are disabled.
161
+ Z[1] ^= H[1];
92
+ */
162
+ }
93
+ if (mode == PRV_M && !(privs & PMP_EXEC)) {
163
+ bool reduce = ((H[1] >> 63) & 1);
94
+ ret = true;
164
+ H[1] = H[1] << 1 | H[0] >> 63;
95
+ *allowed_privs = PMP_READ | PMP_WRITE;
165
+ H[0] = H[0] << 1;
96
+ } else {
166
+ if (reduce) {
97
+ ret = false;
167
+ H[0] ^= 0x87;
98
+ *allowed_privs = 0;
168
+ }
99
+ }
100
+
101
+ return ret;
102
+ }
169
+ }
170
+
171
+ vd[i * 2 + 0] = brev8(Z[0]);
172
+ vd[i * 2 + 1] = brev8(Z[1]);
103
+ }
173
+ }
104
+
174
+ /* set tail elements to 1s */
105
if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
175
+ vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
106
/*
176
+ env->vstart = 0;
107
* Privileged spec v1.10 states if HW doesn't implement any PMP entry
177
+}
108
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
178
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
109
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
179
index XXXXXXX..XXXXXXX 100644
110
180
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
111
/*
181
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
112
- * If the PMP entry is not off and the address is in range, do the priv
182
@@ -XXX,XX +XXX,XX @@ static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
113
- * check
183
114
+ * Convert the PMP permissions to match the truth table in the
184
GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS)
115
+ * ePMP spec.
185
GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS)
116
*/
186
+
117
+ const uint8_t epmp_operation =
187
+/*
118
+ ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
188
+ * Zvkg
119
+ ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
189
+ */
120
+ (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
190
+
121
+ ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
191
+#define ZVKG_EGS 4
122
+
192
+
123
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
193
+static bool vgmul_check(DisasContext *s, arg_rmr *a)
124
- *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
194
+{
125
- if ((mode != PRV_M) || pmp_is_locked(env, i)) {
195
+ int egw_bytes = ZVKG_EGS << s->sew;
126
- *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
196
+ return s->cfg_ptr->ext_zvkg == true &&
127
+ /*
197
+ vext_check_isa_ill(s) &&
128
+ * If the PMP entry is not off and the address is in range,
198
+ require_rvv(s) &&
129
+ * do the priv check
199
+ MAXSZ(s) >= egw_bytes &&
130
+ */
200
+ vext_check_ss(s, a->rd, a->rs2, a->vm) &&
131
+ if (!MSECCFG_MML_ISSET(env)) {
201
+ s->sew == MO_32;
132
+ /*
202
+}
133
+ * If mseccfg.MML Bit is not set, do pmp priv check
203
+
134
+ * This will always apply to regular PMP.
204
+GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS)
135
+ */
205
+
136
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
206
+static bool vghsh_check(DisasContext *s, arg_rmrr *a)
137
+ if ((mode != PRV_M) || pmp_is_locked(env, i)) {
207
+{
138
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
208
+ int egw_bytes = ZVKG_EGS << s->sew;
139
+ }
209
+ return s->cfg_ptr->ext_zvkg == true &&
140
+ } else {
210
+ opivv_check(s, a) &&
141
+ /*
211
+ MAXSZ(s) >= egw_bytes &&
142
+ * If mseccfg.MML Bit set, do the enhanced pmp priv check
212
+ s->sew == MO_32;
143
+ */
213
+}
144
+ if (mode == PRV_M) {
214
+
145
+ switch (epmp_operation) {
215
+GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS)
146
+ case 0:
147
+ case 1:
148
+ case 4:
149
+ case 5:
150
+ case 6:
151
+ case 7:
152
+ case 8:
153
+ *allowed_privs = 0;
154
+ break;
155
+ case 2:
156
+ case 3:
157
+ case 14:
158
+ *allowed_privs = PMP_READ | PMP_WRITE;
159
+ break;
160
+ case 9:
161
+ case 10:
162
+ *allowed_privs = PMP_EXEC;
163
+ break;
164
+ case 11:
165
+ case 13:
166
+ *allowed_privs = PMP_READ | PMP_EXEC;
167
+ break;
168
+ case 12:
169
+ case 15:
170
+ *allowed_privs = PMP_READ;
171
+ break;
172
+ }
173
+ } else {
174
+ switch (epmp_operation) {
175
+ case 0:
176
+ case 8:
177
+ case 9:
178
+ case 12:
179
+ case 13:
180
+ case 14:
181
+ *allowed_privs = 0;
182
+ break;
183
+ case 1:
184
+ case 10:
185
+ case 11:
186
+ *allowed_privs = PMP_EXEC;
187
+ break;
188
+ case 2:
189
+ case 4:
190
+ case 15:
191
+ *allowed_privs = PMP_READ;
192
+ break;
193
+ case 3:
194
+ case 6:
195
+ *allowed_privs = PMP_READ | PMP_WRITE;
196
+ break;
197
+ case 5:
198
+ *allowed_privs = PMP_READ | PMP_EXEC;
199
+ break;
200
+ case 7:
201
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
202
+ break;
203
+ }
204
+ }
205
}
206
207
ret = ((privs & *allowed_privs) == privs);
208
--
216
--
209
2.31.1
217
2.41.0
210
211
diff view generated by jsdifflib
[PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions
[PULL v2 20/45] crypto: Create sm4_subword
1
This patch removes the insn16-32.decode and insn16-64.decode decode
1
From: Max Chou <max.chou@sifive.com>
2
files and consolidates the instructions into the general RISC-V
3
insn16.decode decode tree.
4
2
5
This means that all of the instructions are avaliable in both the 32-bit
3
Allows sharing of sm4_subword between different targets.
6
and 64-bit builds. This also means that we run a check to ensure we are
7
running a 64-bit softmmu before we execute the 64-bit only instructions.
8
This allows us to include the 32-bit instructions in the 64-bit build,
9
while also ensuring that 32-bit only software can not execute the
10
instructions.
11
4
5
Signed-off-by: Max Chou <max.chou@sifive.com>
6
Reviewed-by: Frank Chang <frank.chang@sifive.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Max Chou <max.chou@sifive.com>
9
Message-ID: <20230711165917.2629866-14-max.chou@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
15
---
11
---
16
target/riscv/insn16-32.decode | 28 -------------------
12
include/crypto/sm4.h | 8 ++++++++
17
target/riscv/insn16-64.decode | 36 -------------------------
13
target/arm/tcg/crypto_helper.c | 10 ++--------
18
target/riscv/insn16.decode | 30 +++++++++++++++++++++
14
2 files changed, 10 insertions(+), 8 deletions(-)
19
target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++
20
target/riscv/meson.build | 11 +++-----
21
5 files changed, 39 insertions(+), 72 deletions(-)
22
delete mode 100644 target/riscv/insn16-32.decode
23
delete mode 100644 target/riscv/insn16-64.decode
24
15
25
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
16
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
26
deleted file mode 100644
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX
18
--- a/include/crypto/sm4.h
28
--- a/target/riscv/insn16-32.decode
19
+++ b/include/crypto/sm4.h
29
+++ /dev/null
30
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
31
-#
21
32
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
22
extern const uint8_t sm4_sbox[256];
33
-#
23
34
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
24
+static inline uint32_t sm4_subword(uint32_t word)
35
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
36
-#
37
-# This program is free software; you can redistribute it and/or modify it
38
-# under the terms and conditions of the GNU General Public License,
39
-# version 2 or later, as published by the Free Software Foundation.
40
-#
41
-# This program is distributed in the hope it will be useful, but WITHOUT
42
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
43
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
44
-# more details.
45
-#
46
-# You should have received a copy of the GNU General Public License along with
47
-# this program. If not, see <http://www.gnu.org/licenses/>.
48
-
49
-# *** RV32C Standard Extension (Quadrant 0) ***
50
-flw 011 ... ... .. ... 00 @cl_w
51
-fsw 111 ... ... .. ... 00 @cs_w
52
-
53
-# *** RV32C Standard Extension (Quadrant 1) ***
54
-jal 001 ........... 01 @cj rd=1 # C.JAL
55
-
56
-# *** RV32C Standard Extension (Quadrant 2) ***
57
-flw 011 . ..... ..... 10 @c_lwsp
58
-fsw 111 . ..... ..... 10 @c_swsp
59
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
60
deleted file mode 100644
61
index XXXXXXX..XXXXXXX
62
--- a/target/riscv/insn16-64.decode
63
+++ /dev/null
64
@@ -XXX,XX +XXX,XX @@
65
-#
66
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
67
-#
68
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
69
-# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
70
-#
71
-# This program is free software; you can redistribute it and/or modify it
72
-# under the terms and conditions of the GNU General Public License,
73
-# version 2 or later, as published by the Free Software Foundation.
74
-#
75
-# This program is distributed in the hope it will be useful, but WITHOUT
76
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
77
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
78
-# more details.
79
-#
80
-# You should have received a copy of the GNU General Public License along with
81
-# this program. If not, see <http://www.gnu.org/licenses/>.
82
-
83
-# *** RV64C Standard Extension (Quadrant 0) ***
84
-ld 011 ... ... .. ... 00 @cl_d
85
-sd 111 ... ... .. ... 00 @cs_d
86
-
87
-# *** RV64C Standard Extension (Quadrant 1) ***
88
-{
89
- illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
90
- addiw 001 . ..... ..... 01 @ci
91
-}
92
-subw 100 1 11 ... 00 ... 01 @cs_2
93
-addw 100 1 11 ... 01 ... 01 @cs_2
94
-
95
-# *** RV64C Standard Extension (Quadrant 2) ***
96
-{
97
- illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
98
- ld 011 . ..... ..... 10 @c_ldsp
99
-}
100
-sd 111 . ..... ..... 10 @c_sdsp
101
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
102
index XXXXXXX..XXXXXXX 100644
103
--- a/target/riscv/insn16.decode
104
+++ b/target/riscv/insn16.decode
105
@@ -XXX,XX +XXX,XX @@ lw 010 ... ... .. ... 00 @cl_w
106
fsd 101 ... ... .. ... 00 @cs_d
107
sw 110 ... ... .. ... 00 @cs_w
108
109
+# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
110
+{
25
+{
111
+ ld 011 ... ... .. ... 00 @cl_d
26
+ return sm4_sbox[word & 0xff] |
112
+ flw 011 ... ... .. ... 00 @cl_w
27
+ sm4_sbox[(word >> 8) & 0xff] << 8 |
113
+}
28
+ sm4_sbox[(word >> 16) & 0xff] << 16 |
114
+{
29
+ sm4_sbox[(word >> 24) & 0xff] << 24;
115
+ sd 111 ... ... .. ... 00 @cs_d
116
+ fsw 111 ... ... .. ... 00 @cs_w
117
+}
30
+}
118
+
31
+
119
# *** RV32/64C Standard Extension (Quadrant 1) ***
32
#endif
120
addi 000 . ..... ..... 01 @ci
33
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
121
addi 010 . ..... ..... 01 @c_li
122
@@ -XXX,XX +XXX,XX @@ jal 101 ........... 01 @cj rd=0 # C.J
123
beq 110 ... ... ..... 01 @cb_z
124
bne 111 ... ... ..... 01 @cb_z
125
126
+# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
127
+{
128
+ c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
129
+ addiw 001 . ..... ..... 01 @ci
130
+ jal 001 ........... 01 @cj rd=1 # C.JAL
131
+}
132
+subw 100 1 11 ... 00 ... 01 @cs_2
133
+addw 100 1 11 ... 01 ... 01 @cs_2
134
+
135
# *** RV32/64C Standard Extension (Quadrant 2) ***
136
slli 000 . ..... ..... 10 @c_shift2
137
fld 001 . ..... ..... 10 @c_ldsp
138
@@ -XXX,XX +XXX,XX @@ fld 001 . ..... ..... 10 @c_ldsp
139
}
140
fsd 101 ...... ..... 10 @c_sdsp
141
sw 110 . ..... ..... 10 @c_swsp
142
+
143
+# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
144
+{
145
+ c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
146
+ ld 011 . ..... ..... 10 @c_ldsp
147
+ flw 011 . ..... ..... 10 @c_lwsp
148
+}
149
+{
150
+ sd 111 . ..... ..... 10 @c_sdsp
151
+ fsw 111 . ..... ..... 10 @c_swsp
152
+}
153
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
154
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
155
--- a/target/riscv/insn_trans/trans_rvi.c.inc
35
--- a/target/arm/tcg/crypto_helper.c
156
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
36
+++ b/target/arm/tcg/crypto_helper.c
157
@@ -XXX,XX +XXX,XX @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
37
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
158
return true;
38
CR_ST_WORD(d, (i + 3) % 4) ^
159
}
39
CR_ST_WORD(n, i);
160
40
161
+static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
41
- t = sm4_sbox[t & 0xff] |
162
+{
42
- sm4_sbox[(t >> 8) & 0xff] << 8 |
163
+ REQUIRE_64BIT(ctx);
43
- sm4_sbox[(t >> 16) & 0xff] << 16 |
164
+ return trans_illegal(ctx, a);
44
- sm4_sbox[(t >> 24) & 0xff] << 24;
165
+}
45
+ t = sm4_subword(t);
166
+
46
167
static bool trans_lui(DisasContext *ctx, arg_lui *a)
47
CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^
168
{
48
rol32(t, 24);
169
if (a->rd != 0) {
49
@@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
170
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
50
CR_ST_WORD(d, (i + 3) % 4) ^
171
index XXXXXXX..XXXXXXX 100644
51
CR_ST_WORD(m, i);
172
--- a/target/riscv/meson.build
52
173
+++ b/target/riscv/meson.build
53
- t = sm4_sbox[t & 0xff] |
174
@@ -XXX,XX +XXX,XX @@
54
- sm4_sbox[(t >> 8) & 0xff] << 8 |
175
# FIXME extra_args should accept files()
55
- sm4_sbox[(t >> 16) & 0xff] << 16 |
176
dir = meson.current_source_dir()
56
- sm4_sbox[(t >> 24) & 0xff] << 24;
177
-gen32 = [
57
+ t = sm4_subword(t);
178
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
58
179
- decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
59
CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23);
180
-]
60
}
181
182
-gen64 = [
183
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
184
+gen = [
185
+ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
186
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
187
]
188
189
riscv_ss = ss.source_set()
190
-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
191
-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
192
+riscv_ss.add(gen)
193
riscv_ss.add(files(
194
'cpu.c',
195
'cpu_helper.c',
196
--
61
--
197
2.31.1
62
2.41.0
198
199
diff view generated by jsdifflib
[PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
[PULL v2 21/45] crypto: Add SM4 constant parameter CK
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
In IEEE 754-2008 spec:
3
Adds sm4_ck constant for use in sm4 cryptography across different targets.
4
Invalid operation exception is signaled when doing:
5
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
6
unless c is a quiet NaN; if c is a quiet NaN then it is
7
implementation defined whether the invalid operation exception
8
is signaled.
9
4
10
In RISC-V Unprivileged ISA spec:
5
Signed-off-by: Max Chou <max.chou@sifive.com>
11
The fused multiply-add instructions must set the invalid
6
Reviewed-by: Frank Chang <frank.chang@sifive.com>
12
operation exception flag when the multiplicands are Inf and
7
Signed-off-by: Max Chou <max.chou@sifive.com>
13
zero, even when the addend is a quiet NaN.
8
Message-ID: <20230711165917.2629866-15-max.chou@sifive.com>
14
15
This commit set invalid operation execption flag for RISC-V when
16
multiplicands of muladd instructions are Inf and zero.
17
18
Signed-off-by: Frank Chang <frank.chang@sifive.com>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
10
---
23
fpu/softfloat-specialize.c.inc | 6 ++++++
11
include/crypto/sm4.h | 1 +
24
1 file changed, 6 insertions(+)
12
crypto/sm4.c | 10 ++++++++++
13
2 files changed, 11 insertions(+)
25
14
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
15
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
27
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
28
--- a/fpu/softfloat-specialize.c.inc
17
--- a/include/crypto/sm4.h
29
+++ b/fpu/softfloat-specialize.c.inc
18
+++ b/include/crypto/sm4.h
30
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
19
@@ -XXX,XX +XXX,XX @@
31
} else {
20
#define QEMU_SM4_H
32
return 1;
21
33
}
22
extern const uint8_t sm4_sbox[256];
34
+#elif defined(TARGET_RISCV)
23
+extern const uint32_t sm4_ck[32];
35
+ /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
24
36
+ if (infzero) {
25
static inline uint32_t sm4_subword(uint32_t word)
37
+ float_raise(float_flag_invalid, status);
26
{
38
+ }
27
diff --git a/crypto/sm4.c b/crypto/sm4.c
39
+ return 3; /* default NaN */
28
index XXXXXXX..XXXXXXX 100644
40
#elif defined(TARGET_XTENSA)
29
--- a/crypto/sm4.c
41
/*
30
+++ b/crypto/sm4.c
42
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
31
@@ -XXX,XX +XXX,XX @@ uint8_t const sm4_sbox[] = {
32
0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
33
};
34
35
+uint32_t const sm4_ck[] = {
36
+ 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
37
+ 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
38
+ 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
39
+ 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
40
+ 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
41
+ 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
42
+ 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
43
+ 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
44
+};
43
--
45
--
44
2.31.1
46
2.41.0
45
46
diff view generated by jsdifflib
[PULL 30/42] hw/riscv: Fix OT IBEX reset vector
[PULL v2 22/45] target/riscv: Add Zvksed ISA extension support
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
The IBEX documentation [1] specifies the reset vector to be "the most
3
This commit adds support for the Zvksed vector-crypto extension, which
4
significant 3 bytes of the boot address and the reset value (0x80) as
4
consists of the following instructions:
5
the least significant byte".
5
6
6
* vsm4k.vi
7
[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
7
* vsm4r.[vv,vs]
8
8
9
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
9
Translation functions are defined in
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
11
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
11
`target/riscv/vcrypto_helper.c`.
12
13
Signed-off-by: Max Chou <max.chou@sifive.com>
14
Reviewed-by: Frank Chang <frank.chang@sifive.com>
15
[lawrence.hunter@codethink.co.uk: Moved SM4 functions from
16
crypto_helper.c to vcrypto_helper.c]
17
[nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
18
use macros, and minor style changes]
19
Signed-off-by: Max Chou <max.chou@sifive.com>
20
Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
22
---
14
hw/riscv/opentitan.c | 2 +-
23
target/riscv/cpu_cfg.h | 1 +
15
1 file changed, 1 insertion(+), 1 deletion(-)
24
target/riscv/helper.h | 4 +
16
25
target/riscv/insn32.decode | 5 +
17
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
26
target/riscv/cpu.c | 5 +-
18
index XXXXXXX..XXXXXXX 100644
27
target/riscv/vcrypto_helper.c | 127 +++++++++++++++++++++++
19
--- a/hw/riscv/opentitan.c
28
target/riscv/insn_trans/trans_rvvk.c.inc | 43 ++++++++
20
+++ b/hw/riscv/opentitan.c
29
6 files changed, 184 insertions(+), 1 deletion(-)
21
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
30
22
&error_abort);
31
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
23
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
32
index XXXXXXX..XXXXXXX 100644
24
&error_abort);
33
--- a/target/riscv/cpu_cfg.h
25
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
34
+++ b/target/riscv/cpu_cfg.h
26
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
35
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
27
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
36
bool ext_zvkned;
28
37
bool ext_zvknha;
29
/* Boot ROM */
38
bool ext_zvknhb;
39
+ bool ext_zvksed;
40
bool ext_zvksh;
41
bool ext_zmmul;
42
bool ext_zvfbfmin;
43
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/helper.h
46
+++ b/target/riscv/helper.h
47
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
48
49
DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32)
50
DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32)
51
+
52
+DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32)
53
+DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32)
54
+DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)
55
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/insn32.decode
58
+++ b/target/riscv/insn32.decode
59
@@ -XXX,XX +XXX,XX @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
60
# *** Zvkg vector crypto extension ***
61
vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
62
vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
63
+
64
+# *** Zvksed vector crypto extension ***
65
+vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1
66
+vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1
67
+vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1
68
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/riscv/cpu.c
71
+++ b/target/riscv/cpu.c
72
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
73
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
74
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
75
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
76
+ ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
77
ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
78
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
79
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
80
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
81
* in qemu
82
*/
83
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
84
- cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
85
+ cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
86
+ !cpu->cfg.ext_zve32f) {
87
error_setg(errp,
88
"Vector crypto extensions require V or Zve* extensions");
89
return;
90
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
91
DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
92
DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
93
DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
94
+ DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
95
DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
96
97
DEFINE_PROP_END_OF_LIST(),
98
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/riscv/vcrypto_helper.c
101
+++ b/target/riscv/vcrypto_helper.c
102
@@ -XXX,XX +XXX,XX @@
103
#include "cpu.h"
104
#include "crypto/aes.h"
105
#include "crypto/aes-round.h"
106
+#include "crypto/sm4.h"
107
#include "exec/memop.h"
108
#include "exec/exec-all.h"
109
#include "exec/helper-proto.h"
110
@@ -XXX,XX +XXX,XX @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env,
111
vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
112
env->vstart = 0;
113
}
114
+
115
+void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *env,
116
+ uint32_t desc)
117
+{
118
+ const uint32_t egs = 4;
119
+ uint32_t rnd = uimm5 & 0x7;
120
+ uint32_t group_start = env->vstart / egs;
121
+ uint32_t group_end = env->vl / egs;
122
+ uint32_t esz = sizeof(uint32_t);
123
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
124
+
125
+ for (uint32_t i = group_start; i < group_end; ++i) {
126
+ uint32_t vstart = i * egs;
127
+ uint32_t vend = (i + 1) * egs;
128
+ uint32_t rk[4] = {0};
129
+ uint32_t tmp[8] = {0};
130
+
131
+ for (uint32_t j = vstart; j < vend; ++j) {
132
+ rk[j - vstart] = *((uint32_t *)vs2 + H4(j));
133
+ }
134
+
135
+ for (uint32_t j = 0; j < egs; ++j) {
136
+ tmp[j] = rk[j];
137
+ }
138
+
139
+ for (uint32_t j = 0; j < egs; ++j) {
140
+ uint32_t b, s;
141
+ b = tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + j];
142
+
143
+ s = sm4_subword(b);
144
+
145
+ tmp[j + 4] = tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23));
146
+ }
147
+
148
+ for (uint32_t j = vstart; j < vend; ++j) {
149
+ *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
150
+ }
151
+ }
152
+
153
+ env->vstart = 0;
154
+ /* set tail elements to 1s */
155
+ vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
156
+}
157
+
158
+static void do_sm4_round(uint32_t *rk, uint32_t *buf)
159
+{
160
+ const uint32_t egs = 4;
161
+ uint32_t s, b;
162
+
163
+ for (uint32_t j = egs; j < egs * 2; ++j) {
164
+ b = buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4];
165
+
166
+ s = sm4_subword(b);
167
+
168
+ buf[j] = buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s, 18) ^
169
+ rol32(s, 24));
170
+ }
171
+}
172
+
173
+void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
174
+{
175
+ const uint32_t egs = 4;
176
+ uint32_t group_start = env->vstart / egs;
177
+ uint32_t group_end = env->vl / egs;
178
+ uint32_t esz = sizeof(uint32_t);
179
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
180
+
181
+ for (uint32_t i = group_start; i < group_end; ++i) {
182
+ uint32_t vstart = i * egs;
183
+ uint32_t vend = (i + 1) * egs;
184
+ uint32_t rk[4] = {0};
185
+ uint32_t tmp[8] = {0};
186
+
187
+ for (uint32_t j = vstart; j < vend; ++j) {
188
+ rk[j - vstart] = *((uint32_t *)vs2 + H4(j));
189
+ }
190
+
191
+ for (uint32_t j = vstart; j < vend; ++j) {
192
+ tmp[j - vstart] = *((uint32_t *)vd + H4(j));
193
+ }
194
+
195
+ do_sm4_round(rk, tmp);
196
+
197
+ for (uint32_t j = vstart; j < vend; ++j) {
198
+ *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
199
+ }
200
+ }
201
+
202
+ env->vstart = 0;
203
+ /* set tail elements to 1s */
204
+ vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
205
+}
206
+
207
+void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
208
+{
209
+ const uint32_t egs = 4;
210
+ uint32_t group_start = env->vstart / egs;
211
+ uint32_t group_end = env->vl / egs;
212
+ uint32_t esz = sizeof(uint32_t);
213
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
214
+
215
+ for (uint32_t i = group_start; i < group_end; ++i) {
216
+ uint32_t vstart = i * egs;
217
+ uint32_t vend = (i + 1) * egs;
218
+ uint32_t rk[4] = {0};
219
+ uint32_t tmp[8] = {0};
220
+
221
+ for (uint32_t j = 0; j < egs; ++j) {
222
+ rk[j] = *((uint32_t *)vs2 + H4(j));
223
+ }
224
+
225
+ for (uint32_t j = vstart; j < vend; ++j) {
226
+ tmp[j - vstart] = *((uint32_t *)vd + H4(j));
227
+ }
228
+
229
+ do_sm4_round(rk, tmp);
230
+
231
+ for (uint32_t j = vstart; j < vend; ++j) {
232
+ *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)];
233
+ }
234
+ }
235
+
236
+ env->vstart = 0;
237
+ /* set tail elements to 1s */
238
+ vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz);
239
+}
240
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
241
index XXXXXXX..XXXXXXX 100644
242
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
243
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
244
@@ -XXX,XX +XXX,XX @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a)
245
}
246
247
GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS)
248
+
249
+/*
250
+ * Zvksed
251
+ */
252
+
253
+#define ZVKSED_EGS 4
254
+
255
+static bool zvksed_check(DisasContext *s)
256
+{
257
+ int egw_bytes = ZVKSED_EGS << s->sew;
258
+ return s->cfg_ptr->ext_zvksed == true &&
259
+ require_rvv(s) &&
260
+ vext_check_isa_ill(s) &&
261
+ MAXSZ(s) >= egw_bytes &&
262
+ s->sew == MO_32;
263
+}
264
+
265
+static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a)
266
+{
267
+ return zvksed_check(s) &&
268
+ require_align(a->rd, s->lmul) &&
269
+ require_align(a->rs2, s->lmul);
270
+}
271
+
272
+GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS)
273
+
274
+static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a)
275
+{
276
+ return zvksed_check(s) &&
277
+ require_align(a->rd, s->lmul) &&
278
+ require_align(a->rs2, s->lmul);
279
+}
280
+
281
+GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check, ZVKSED_EGS)
282
+
283
+static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a)
284
+{
285
+ return zvksed_check(s) &&
286
+ !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
287
+ require_align(a->rd, s->lmul);
288
+}
289
+
290
+GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check, ZVKSED_EGS)
30
--
291
--
31
2.31.1
292
2.41.0
32
33
diff view generated by jsdifflib
[PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro
[PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
1
From: Rob Bradford <rbradford@rivosinc.com>
2
3
These are WARL fields - zero out the bits for unavailable counters and
4
special case the TM bit in mcountinhibit which is hardwired to zero.
5
This patch achieves this by modifying the value written so that any use
6
of the field will see the correctly masked bits.
7
8
Tested by modifying OpenSBI to write max value to these CSRs and upon
9
subsequent read the appropriate number of bits for number of PMUs is
10
enabled and the TM bit is zero in mcountinhibit.
11
12
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Atish Patra <atishp@rivosinc.com>
15
Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
4
---
17
---
5
target/riscv/cpu_bits.h | 10 ----------
18
target/riscv/csr.c | 11 +++++++++--
6
target/riscv/csr.c | 12 ++++++++++--
19
1 file changed, 9 insertions(+), 2 deletions(-)
7
target/riscv/translate.c | 19 +++++++++++++++++--
8
3 files changed, 27 insertions(+), 14 deletions(-)
9
20
10
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu_bits.h
13
+++ b/target/riscv/cpu_bits.h
14
@@ -XXX,XX +XXX,XX @@
15
#define MXL_RV64 2
16
#define MXL_RV128 3
17
18
-#if defined(TARGET_RISCV32)
19
-#define MSTATUS_SD MSTATUS32_SD
20
-#define MISA_MXL MISA32_MXL
21
-#define MXL_VAL MXL_RV32
22
-#elif defined(TARGET_RISCV64)
23
-#define MSTATUS_SD MSTATUS64_SD
24
-#define MISA_MXL MISA64_MXL
25
-#define MXL_VAL MXL_RV64
26
-#endif
27
-
28
/* sstatus CSR bits */
29
#define SSTATUS_UIE 0x00000001
30
#define SSTATUS_SIE 0x00000002
31
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
21
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
32
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/csr.c
23
--- a/target/riscv/csr.c
34
+++ b/target/riscv/csr.c
24
+++ b/target/riscv/csr.c
35
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
25
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
36
26
{
37
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
27
int cidx;
38
((mstatus & MSTATUS_XS) == MSTATUS_XS);
28
PMUCTRState *counter;
39
- mstatus = set_field(mstatus, MSTATUS_SD, dirty);
29
+ RISCVCPU *cpu = env_archcpu(env);
40
+ if (riscv_cpu_is_32bit(env)) {
30
41
+ mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
31
- env->mcountinhibit = val;
42
+ } else {
32
+ /* WARL register - disable unavailable counters; TM bit is always 0 */
43
+ mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
33
+ env->mcountinhibit =
44
+ }
34
+ val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR);
45
env->mstatus = mstatus;
35
46
36
/* Check if any other counter is also monitoring cycles/instructions */
37
for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
38
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
39
static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
40
target_ulong val)
41
{
42
- env->mcounteren = val;
43
+ RISCVCPU *cpu = env_archcpu(env);
44
+
45
+ /* WARL register - disable unavailable counters */
46
+ env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
47
+ COUNTEREN_IR);
47
return RISCV_EXCP_NONE;
48
return RISCV_EXCP_NONE;
48
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
49
}
50
51
/* misa.MXL writes are not supported by QEMU */
52
- val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
53
+ if (riscv_cpu_is_32bit(env)) {
54
+ val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
55
+ } else {
56
+ val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
57
+ }
58
59
/* flush translation cache */
60
if (val != env->misa) {
61
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/translate.c
64
+++ b/target/riscv/translate.c
65
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
66
return ctx->misa & ext;
67
}
49
}
68
50
69
+#ifdef TARGET_RISCV32
70
+# define is_32bit(ctx) true
71
+#elif defined(CONFIG_USER_ONLY)
72
+# define is_32bit(ctx) false
73
+#else
74
+static inline bool is_32bit(DisasContext *ctx)
75
+{
76
+ return (ctx->misa & RV32) == RV32;
77
+}
78
+#endif
79
+
80
/*
81
* RISC-V requires NaN-boxing of narrower width floating point values.
82
* This applies when a 32-bit value is assigned to a 64-bit FP register.
83
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
84
static void mark_fs_dirty(DisasContext *ctx)
85
{
86
TCGv tmp;
87
+ target_ulong sd;
88
+
89
if (ctx->mstatus_fs == MSTATUS_FS) {
90
return;
91
}
92
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
93
ctx->mstatus_fs = MSTATUS_FS;
94
95
tmp = tcg_temp_new();
96
+ sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
97
+
98
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
99
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
100
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
101
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
102
103
if (ctx->virt_enabled) {
104
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
105
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
106
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
107
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
108
}
109
tcg_temp_free(tmp);
110
--
51
--
111
2.31.1
52
2.41.0
112
113
diff view generated by jsdifflib
[PULL 05/42] target/riscv: Add Shakti C class CPU
[PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS
1
From: Vijai Kumar K <vijai@behindbytes.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
C-Class is a member of the SHAKTI family of processors from IIT-M.
3
RVA23 Profiles states:
4
The RVA23 profiles are intended to be used for 64-bit application
5
processors that will run rich OS stacks from standard binary OS
6
distributions and with a substantial number of third-party binary user
7
applications that will be supported over a considerable length of time
8
in the field.
4
9
5
It is an extremely configurable and commercial-grade 5-stage in-order
10
The chapter 4 of the unprivileged spec introduces the Zihintntl extension
6
core supporting the standard RV64GCSUN ISA extensions.
11
and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose
12
purpose is to enable application and operating system portability across
13
different implementations. Thus the DTS should contain the Zihintntl ISA
14
string in order to pass to software.
7
15
8
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
16
The unprivileged spec states:
17
Like any HINTs, these instructions may be freely ignored. Hence, although
18
they are described in terms of cache-based memory hierarchies, they do not
19
mandate the provision of caches.
20
21
These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2,
22
which QEMU already supports, and QEMU does not emulate cache. Therefore
23
these instructions can be considered as a no-op, and we only need to add
24
a new property for the Zihintntl extension.
25
26
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
28
Signed-off-by: Jason Chien <jason.chien@sifive.com>
29
Message-ID: <20230726074049.19505-2-jason.chien@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
31
---
13
target/riscv/cpu.h | 1 +
32
target/riscv/cpu_cfg.h | 1 +
14
target/riscv/cpu.c | 1 +
33
target/riscv/cpu.c | 2 ++
15
2 files changed, 2 insertions(+)
34
2 files changed, 3 insertions(+)
16
35
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
36
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
18
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.h
38
--- a/target/riscv/cpu_cfg.h
20
+++ b/target/riscv/cpu.h
39
+++ b/target/riscv/cpu_cfg.h
21
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
41
bool ext_icbom;
23
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
42
bool ext_icboz;
24
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
43
bool ext_zicond;
25
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
44
+ bool ext_zihintntl;
26
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
45
bool ext_zihintpause;
27
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
46
bool ext_smstateen;
28
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
47
bool ext_sstc;
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
48
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
30
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu.c
50
--- a/target/riscv/cpu.c
32
+++ b/target/riscv/cpu.c
51
+++ b/target/riscv/cpu.c
33
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
52
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
34
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
53
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
35
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
54
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
36
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
55
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
37
+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
56
+ ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
38
#endif
57
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
39
};
58
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
40
59
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
60
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
61
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
62
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
63
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
64
+ DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
65
DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
66
DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
67
DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
41
--
68
--
42
2.31.1
69
2.41.0
43
44
diff view generated by jsdifflib
[PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro
[PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d
1
This also ensures that the SD bit is not writable.
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
2
2
3
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension.
4
However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s
5
helper function.
6
7
Fixes: a47842d ("riscv: Add support for the Zfa extension")
8
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
3
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
7
---
13
---
8
target/riscv/cpu_bits.h | 6 ------
14
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
9
target/riscv/csr.c | 9 ++++++++-
15
1 file changed, 2 insertions(+), 2 deletions(-)
10
2 files changed, 8 insertions(+), 7 deletions(-)
11
16
12
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
17
diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc
13
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu_bits.h
19
--- a/target/riscv/insn_trans/trans_rvzfa.c.inc
15
+++ b/target/riscv/cpu_bits.h
20
+++ b/target/riscv/insn_trans/trans_rvzfa.c.inc
16
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
17
#define SSTATUS32_SD 0x80000000
22
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
18
#define SSTATUS64_SD 0x8000000000000000ULL
23
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
19
24
20
-#if defined(TARGET_RISCV32)
25
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
21
-#define SSTATUS_SD SSTATUS32_SD
26
+ gen_helper_fleq_d(dest, cpu_env, src1, src2);
22
-#elif defined(TARGET_RISCV64)
27
gen_set_gpr(ctx, a->rd, dest);
23
-#define SSTATUS_SD SSTATUS64_SD
28
return true;
24
-#endif
29
}
25
-
30
@@ -XXX,XX +XXX,XX @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
26
/* hstatus CSR bits */
31
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
27
#define HSTATUS_VSBE 0x00000020
32
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
28
#define HSTATUS_GVA 0x00000040
33
29
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
34
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
30
index XXXXXXX..XXXXXXX 100644
35
+ gen_helper_fltq_d(dest, cpu_env, src1, src2);
31
--- a/target/riscv/csr.c
36
gen_set_gpr(ctx, a->rd, dest);
32
+++ b/target/riscv/csr.c
37
return true;
33
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
34
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
35
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
36
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
37
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
38
+ SSTATUS_SUM | SSTATUS_MXR;
39
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
40
static const target_ulong hip_writable_mask = MIP_VSSIP;
41
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
42
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
43
target_ulong *val)
44
{
45
target_ulong mask = (sstatus_v1_10_mask);
46
+
47
+ if (riscv_cpu_is_32bit(env)) {
48
+ mask |= SSTATUS32_SD;
49
+ } else {
50
+ mask |= SSTATUS64_SD;
51
+ }
52
+
53
*val = env->mstatus & mask;
54
return RISCV_EXCP_NONE;
55
}
38
}
56
--
39
--
57
2.31.1
40
2.41.0
58
59
diff view generated by jsdifflib
[PULL 21/42] target/riscv: Define ePMP mseccfg
[PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation
1
From: Hou Weiying <weiying_hou@outlook.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
Use address 0x390 and 0x391 for the ePMP CSRs.
3
When writing the upper mtime, we should keep the original lower mtime
4
whose value is given by cpu_riscv_read_rtc() instead of
5
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
4
6
5
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
6
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
7
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
12
[ Changes by AF:
13
- Tidy up commit message
14
]
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
17
---
11
---
18
target/riscv/cpu_bits.h | 3 +++
12
hw/intc/riscv_aclint.c | 5 +++--
19
1 file changed, 3 insertions(+)
13
1 file changed, 3 insertions(+), 2 deletions(-)
20
14
21
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
15
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_bits.h
17
--- a/hw/intc/riscv_aclint.c
24
+++ b/target/riscv/cpu_bits.h
18
+++ b/hw/intc/riscv_aclint.c
25
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
26
#define CSR_MTINST 0x34a
20
return;
27
#define CSR_MTVAL2 0x34b
21
} else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
28
22
uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
29
+/* Enhanced Physical Memory Protection (ePMP) */
23
+ uint64_t rtc = cpu_riscv_read_rtc(mtimer);
30
+#define CSR_MSECCFG 0x390
24
31
+#define CSR_MSECCFGH 0x391
25
if (addr == mtimer->time_base) {
32
/* Physical Memory Protection */
26
if (size == 4) {
33
#define CSR_PMPCFG0 0x3a0
27
/* time_lo for RV32/RV64 */
34
#define CSR_PMPCFG1 0x3a1
28
- mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
29
+ mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
30
} else {
31
/* time for RV64 */
32
mtimer->time_delta = value - rtc_r;
33
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
34
} else {
35
if (size == 4) {
36
/* time_hi for RV32/RV64 */
37
- mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
38
+ mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
39
} else {
40
qemu_log_mask(LOG_GUEST_ERROR,
41
"aclint-mtimer: invalid time_hi write: %08x",
35
--
42
--
36
2.31.1
43
2.41.0
37
38
diff view generated by jsdifflib
[PULL 22/42] target/riscv: Add the ePMP feature
[PULL v2 27/45] hw/intc: Make rtc variable names consistent
1
The spec is avaliable at:
1
From: Jason Chien <jason.chien@sifive.com>
2
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
3
2
3
The variables whose values are given by cpu_riscv_read_rtc() should be named
4
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
5
should be named "rtc_r".
6
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20230728082502.26439-2-jason.chien@sifive.com>
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Message-id: 28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
7
---
11
---
8
target/riscv/cpu.h | 1 +
12
hw/intc/riscv_aclint.c | 6 +++---
9
1 file changed, 1 insertion(+)
13
1 file changed, 3 insertions(+), 3 deletions(-)
10
14
11
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
15
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.h
17
--- a/hw/intc/riscv_aclint.c
14
+++ b/target/riscv/cpu.h
18
+++ b/hw/intc/riscv_aclint.c
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
16
enum {
20
uint64_t next;
17
RISCV_FEATURE_MMU,
21
uint64_t diff;
18
RISCV_FEATURE_PMP,
22
19
+ RISCV_FEATURE_EPMP,
23
- uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
20
RISCV_FEATURE_MISA
24
+ uint64_t rtc = cpu_riscv_read_rtc(mtimer);
21
};
25
26
/* Compute the relative hartid w.r.t the socket */
27
hartid = hartid - mtimer->hartid_base;
28
29
mtimer->timecmp[hartid] = value;
30
- if (mtimer->timecmp[hartid] <= rtc_r) {
31
+ if (mtimer->timecmp[hartid] <= rtc) {
32
/*
33
* If we're setting an MTIMECMP value in the "past",
34
* immediately raise the timer interrupt
35
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
36
37
/* otherwise, set up the future timer interrupt */
38
qemu_irq_lower(mtimer->timer_irqs[hartid]);
39
- diff = mtimer->timecmp[hartid] - rtc_r;
40
+ diff = mtimer->timecmp[hartid] - rtc;
41
/* back to ns (note args switched in muldiv64) */
42
uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
22
43
23
--
44
--
24
2.31.1
45
2.41.0
25
26
diff view generated by jsdifflib
[PULL 19/42] docs: Add documentation for shakti_c machine
[PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext
1
From: Vijai Kumar K <vijai@behindbytes.com>
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
2
2
3
Add documentation for Shakti C reference platform.
3
We should not use types dependend on host arch for target_ucontext.
4
This bug is found when run rv32 applications.
4
5
5
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
6
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
12
---
10
docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
13
linux-user/riscv/signal.c | 4 ++--
11
1 file changed, 82 insertions(+)
14
1 file changed, 2 insertions(+), 2 deletions(-)
12
create mode 100644 docs/system/riscv/shakti-c.rst
13
15
14
diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
16
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
15
new file mode 100644
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX
18
--- a/linux-user/riscv/signal.c
17
--- /dev/null
19
+++ b/linux-user/riscv/signal.c
18
+++ b/docs/system/riscv/shakti-c.rst
20
@@ -XXX,XX +XXX,XX @@ struct target_sigcontext {
19
@@ -XXX,XX +XXX,XX @@
21
}; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */
20
+Shakti C Reference Platform (``shakti_c``)
22
21
+==========================================
23
struct target_ucontext {
22
+
24
- unsigned long uc_flags;
23
+Shakti C Reference Platform is a reference platform based on arty a7 100t
25
- struct target_ucontext *uc_link;
24
+for the Shakti SoC.
26
+ abi_ulong uc_flags;
25
+
27
+ abi_ptr uc_link;
26
+Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
28
target_stack_t uc_stack;
27
+is a 64bit RV64GCSUN processor core.
29
target_sigset_t uc_sigmask;
28
+
30
uint8_t __unused[1024 / 8 - sizeof(target_sigset_t)];
29
+For more details on Shakti SoC, please see:
30
+https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
31
+
32
+For more info on the Shakti C-class core, please see:
33
+https://c-class.readthedocs.io/en/latest/
34
+
35
+Supported devices
36
+-----------------
37
+
38
+The ``shakti_c`` machine supports the following devices:
39
+
40
+ * 1 C-class core
41
+ * Core Level Interruptor (CLINT)
42
+ * Platform-Level Interrupt Controller (PLIC)
43
+ * 1 UART
44
+
45
+Boot options
46
+------------
47
+
48
+The ``shakti_c`` machine can start using the standard -bios
49
+functionality for loading the baremetal application or opensbi.
50
+
51
+Boot the machine
52
+----------------
53
+
54
+Shakti SDK
55
+~~~~~~~~~~
56
+Shakti SDK can be used to generate the baremetal example UART applications.
57
+
58
+.. code-block:: bash
59
+
60
+ $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
61
+ $ cd shakti-sdk
62
+ $ make software PROGRAM=loopback TARGET=artix7_100t
63
+
64
+Binary would be generated in:
65
+ software/examples/uart_applns/loopback/output/loopback.shakti
66
+
67
+You could also download the precompiled example applicatons using below
68
+commands.
69
+
70
+.. code-block:: bash
71
+
72
+ $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
73
+ $ unzip shakti_sdk_qemu.zip
74
+
75
+Then we can run the UART example using:
76
+
77
+.. code-block:: bash
78
+
79
+ $ qemu-system-riscv64 -M shakti_c -nographic \
80
+ -bios path/to/shakti_sdk_qemu/loopback.shakti
81
+
82
+OpenSBI
83
+~~~~~~~
84
+We can also run OpenSBI with Test Payload.
85
+
86
+.. code-block:: bash
87
+
88
+ $ git clone https://github.com/riscv/opensbi.git -b v0.9
89
+ $ cd opensbi
90
+ $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
91
+ $ export CROSS_COMPILE=riscv64-unknown-elf-
92
+ $ export FW_FDT_PATH=./shakti.dtb
93
+ $ make PLATFORM=generic
94
+
95
+fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
96
+Boot it using the below qemu command.
97
+
98
+.. code-block:: bash
99
+
100
+ $ qemu-system-riscv64 -M shakti_c -nographic \
101
+ -bios path/to/fw_payload.elf
102
--
31
--
103
2.31.1
32
2.41.0
104
33
105
34
diff view generated by jsdifflib
[PULL 12/42] target/riscv: Use the RISCVException enum for CSR operations
[PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
3
In this patch, we create the APLIC and IMSIC FDT helper functions and
4
remove M mode AIA devices when using KVM acceleration.
5
6
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
7
Reviewed-by: Jim Shu <jim.shu@sifive.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
10
Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
5
---
12
---
6
target/riscv/cpu.h | 14 +-
13
hw/riscv/virt.c | 290 +++++++++++++++++++++++-------------------------
7
target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------
14
1 file changed, 137 insertions(+), 153 deletions(-)
8
2 files changed, 382 insertions(+), 261 deletions(-)
9
15
10
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
11
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.h
18
--- a/hw/riscv/virt.c
13
+++ b/target/riscv/cpu.h
19
+++ b/hw/riscv/virt.c
14
@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
20
@@ -XXX,XX +XXX,XX @@ static uint32_t imsic_num_bits(uint32_t count)
15
16
typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
17
int csrno);
18
-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
19
- target_ulong *ret_value);
20
-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
21
- target_ulong new_value);
22
-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
23
- target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
24
+typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
25
+ target_ulong *ret_value);
26
+typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
27
+ target_ulong new_value);
28
+typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
29
+ target_ulong *ret_value,
30
+ target_ulong new_value,
31
+ target_ulong write_mask);
32
33
typedef struct {
34
const char *name;
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
38
+++ b/target/riscv/csr.c
39
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
40
#endif
41
42
/* User Floating-Point CSRs */
43
-static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
44
+static RISCVException read_fflags(CPURISCVState *env, int csrno,
45
+ target_ulong *val)
46
{
47
#if !defined(CONFIG_USER_ONLY)
48
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
49
- return -RISCV_EXCP_ILLEGAL_INST;
50
+ return RISCV_EXCP_ILLEGAL_INST;
51
}
52
#endif
53
*val = riscv_cpu_get_fflags(env);
54
- return 0;
55
+ return RISCV_EXCP_NONE;
56
}
57
58
-static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
59
+static RISCVException write_fflags(CPURISCVState *env, int csrno,
60
+ target_ulong val)
61
{
62
#if !defined(CONFIG_USER_ONLY)
63
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
64
- return -RISCV_EXCP_ILLEGAL_INST;
65
+ return RISCV_EXCP_ILLEGAL_INST;
66
}
67
env->mstatus |= MSTATUS_FS;
68
#endif
69
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
70
- return 0;
71
+ return RISCV_EXCP_NONE;
72
}
73
74
-static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
75
+static RISCVException read_frm(CPURISCVState *env, int csrno,
76
+ target_ulong *val)
77
{
78
#if !defined(CONFIG_USER_ONLY)
79
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
80
- return -RISCV_EXCP_ILLEGAL_INST;
81
+ return RISCV_EXCP_ILLEGAL_INST;
82
}
83
#endif
84
*val = env->frm;
85
- return 0;
86
+ return RISCV_EXCP_NONE;
87
}
88
89
-static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
90
+static RISCVException write_frm(CPURISCVState *env, int csrno,
91
+ target_ulong val)
92
{
93
#if !defined(CONFIG_USER_ONLY)
94
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
95
- return -RISCV_EXCP_ILLEGAL_INST;
96
+ return RISCV_EXCP_ILLEGAL_INST;
97
}
98
env->mstatus |= MSTATUS_FS;
99
#endif
100
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
101
- return 0;
102
+ return RISCV_EXCP_NONE;
103
}
104
105
-static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
106
+static RISCVException read_fcsr(CPURISCVState *env, int csrno,
107
+ target_ulong *val)
108
{
109
#if !defined(CONFIG_USER_ONLY)
110
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
111
- return -RISCV_EXCP_ILLEGAL_INST;
112
+ return RISCV_EXCP_ILLEGAL_INST;
113
}
114
#endif
115
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
116
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
117
*val |= (env->vxrm << FSR_VXRM_SHIFT)
118
| (env->vxsat << FSR_VXSAT_SHIFT);
119
}
120
- return 0;
121
+ return RISCV_EXCP_NONE;
122
}
123
124
-static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
125
+static RISCVException write_fcsr(CPURISCVState *env, int csrno,
126
+ target_ulong val)
127
{
128
#if !defined(CONFIG_USER_ONLY)
129
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
130
- return -RISCV_EXCP_ILLEGAL_INST;
131
+ return RISCV_EXCP_ILLEGAL_INST;
132
}
133
env->mstatus |= MSTATUS_FS;
134
#endif
135
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
136
env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
137
}
138
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
139
- return 0;
140
+ return RISCV_EXCP_NONE;
141
}
142
143
-static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
144
+static RISCVException read_vtype(CPURISCVState *env, int csrno,
145
+ target_ulong *val)
146
{
147
*val = env->vtype;
148
- return 0;
149
+ return RISCV_EXCP_NONE;
150
}
151
152
-static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
153
+static RISCVException read_vl(CPURISCVState *env, int csrno,
154
+ target_ulong *val)
155
{
156
*val = env->vl;
157
- return 0;
158
+ return RISCV_EXCP_NONE;
159
}
160
161
-static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
162
+static RISCVException read_vxrm(CPURISCVState *env, int csrno,
163
+ target_ulong *val)
164
{
165
*val = env->vxrm;
166
- return 0;
167
+ return RISCV_EXCP_NONE;
168
}
169
170
-static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
171
+static RISCVException write_vxrm(CPURISCVState *env, int csrno,
172
+ target_ulong val)
173
{
174
env->vxrm = val;
175
- return 0;
176
+ return RISCV_EXCP_NONE;
177
}
178
179
-static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
180
+static RISCVException read_vxsat(CPURISCVState *env, int csrno,
181
+ target_ulong *val)
182
{
183
*val = env->vxsat;
184
- return 0;
185
+ return RISCV_EXCP_NONE;
186
}
187
188
-static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
189
+static RISCVException write_vxsat(CPURISCVState *env, int csrno,
190
+ target_ulong val)
191
{
192
env->vxsat = val;
193
- return 0;
194
+ return RISCV_EXCP_NONE;
195
}
196
197
-static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
198
+static RISCVException read_vstart(CPURISCVState *env, int csrno,
199
+ target_ulong *val)
200
{
201
*val = env->vstart;
202
- return 0;
203
+ return RISCV_EXCP_NONE;
204
}
205
206
-static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
207
+static RISCVException write_vstart(CPURISCVState *env, int csrno,
208
+ target_ulong val)
209
{
210
env->vstart = val;
211
- return 0;
212
+ return RISCV_EXCP_NONE;
213
}
214
215
/* User Timers and Counters */
216
-static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
217
+static RISCVException read_instret(CPURISCVState *env, int csrno,
218
+ target_ulong *val)
219
{
220
#if !defined(CONFIG_USER_ONLY)
221
if (icount_enabled()) {
222
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
223
#else
224
*val = cpu_get_host_ticks();
225
#endif
226
- return 0;
227
+ return RISCV_EXCP_NONE;
228
}
229
230
-static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
231
+static RISCVException read_instreth(CPURISCVState *env, int csrno,
232
+ target_ulong *val)
233
{
234
#if !defined(CONFIG_USER_ONLY)
235
if (icount_enabled()) {
236
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
237
#else
238
*val = cpu_get_host_ticks() >> 32;
239
#endif
240
- return 0;
241
+ return RISCV_EXCP_NONE;
242
}
243
244
#if defined(CONFIG_USER_ONLY)
245
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
246
+static RISCVException read_time(CPURISCVState *env, int csrno,
247
+ target_ulong *val)
248
{
249
*val = cpu_get_host_ticks();
250
- return 0;
251
+ return RISCV_EXCP_NONE;
252
}
253
254
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
255
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
256
+ target_ulong *val)
257
{
258
*val = cpu_get_host_ticks() >> 32;
259
- return 0;
260
+ return RISCV_EXCP_NONE;
261
}
262
263
#else /* CONFIG_USER_ONLY */
264
265
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
266
+static RISCVException read_time(CPURISCVState *env, int csrno,
267
+ target_ulong *val)
268
{
269
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
270
271
if (!env->rdtime_fn) {
272
- return -RISCV_EXCP_ILLEGAL_INST;
273
+ return RISCV_EXCP_ILLEGAL_INST;
274
}
275
276
*val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
277
- return 0;
278
+ return RISCV_EXCP_NONE;
279
}
280
281
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
282
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
283
+ target_ulong *val)
284
{
285
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
286
287
if (!env->rdtime_fn) {
288
- return -RISCV_EXCP_ILLEGAL_INST;
289
+ return RISCV_EXCP_ILLEGAL_INST;
290
}
291
292
*val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
293
- return 0;
294
+ return RISCV_EXCP_NONE;
295
}
296
297
/* Machine constants */
298
@@ -XXX,XX +XXX,XX @@ static const char valid_vm_1_10_64[16] = {
299
};
300
301
/* Machine Information Registers */
302
-static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
303
+static RISCVException read_zero(CPURISCVState *env, int csrno,
304
+ target_ulong *val)
305
{
306
- return *val = 0;
307
+ *val = 0;
308
+ return RISCV_EXCP_NONE;
309
}
310
311
-static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
312
+static RISCVException read_mhartid(CPURISCVState *env, int csrno,
313
+ target_ulong *val)
314
{
315
*val = env->mhartid;
316
- return 0;
317
+ return RISCV_EXCP_NONE;
318
}
319
320
/* Machine Trap Setup */
321
-static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
322
+static RISCVException read_mstatus(CPURISCVState *env, int csrno,
323
+ target_ulong *val)
324
{
325
*val = env->mstatus;
326
- return 0;
327
+ return RISCV_EXCP_NONE;
328
}
329
330
static int validate_vm(CPURISCVState *env, target_ulong vm)
331
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
332
}
333
}
334
335
-static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
336
+static RISCVException write_mstatus(CPURISCVState *env, int csrno,
337
+ target_ulong val)
338
{
339
uint64_t mstatus = env->mstatus;
340
uint64_t mask = 0;
341
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
342
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
343
env->mstatus = mstatus;
344
345
- return 0;
346
+ return RISCV_EXCP_NONE;
347
}
348
349
-static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
350
+static RISCVException read_mstatush(CPURISCVState *env, int csrno,
351
+ target_ulong *val)
352
{
353
*val = env->mstatus >> 32;
354
- return 0;
355
+ return RISCV_EXCP_NONE;
356
}
357
358
-static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
359
+static RISCVException write_mstatush(CPURISCVState *env, int csrno,
360
+ target_ulong val)
361
{
362
uint64_t valh = (uint64_t)val << 32;
363
uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
364
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
365
366
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
367
368
- return 0;
369
+ return RISCV_EXCP_NONE;
370
}
371
372
-static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
373
+static RISCVException read_misa(CPURISCVState *env, int csrno,
374
+ target_ulong *val)
375
{
376
*val = env->misa;
377
- return 0;
378
+ return RISCV_EXCP_NONE;
379
}
380
381
-static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
382
+static RISCVException write_misa(CPURISCVState *env, int csrno,
383
+ target_ulong val)
384
{
385
if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
386
/* drop write to misa */
387
- return 0;
388
+ return RISCV_EXCP_NONE;
389
}
390
391
/* 'I' or 'E' must be present */
392
if (!(val & (RVI | RVE))) {
393
/* It is not, drop write to misa */
394
- return 0;
395
+ return RISCV_EXCP_NONE;
396
}
397
398
/* 'E' excludes all other extensions */
399
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
400
/* when we support 'E' we can do "val = RVE;" however
401
* for now we just drop writes if 'E' is present.
402
*/
403
- return 0;
404
+ return RISCV_EXCP_NONE;
405
}
406
407
/* Mask extensions that are not supported by this hart */
408
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
409
410
env->misa = val;
411
412
- return 0;
413
+ return RISCV_EXCP_NONE;
414
}
415
416
-static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
417
+static RISCVException read_medeleg(CPURISCVState *env, int csrno,
418
+ target_ulong *val)
419
{
420
*val = env->medeleg;
421
- return 0;
422
+ return RISCV_EXCP_NONE;
423
}
424
425
-static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
426
+static RISCVException write_medeleg(CPURISCVState *env, int csrno,
427
+ target_ulong val)
428
{
429
env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
430
- return 0;
431
+ return RISCV_EXCP_NONE;
432
}
433
434
-static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
435
+static RISCVException read_mideleg(CPURISCVState *env, int csrno,
436
+ target_ulong *val)
437
{
438
*val = env->mideleg;
439
- return 0;
440
+ return RISCV_EXCP_NONE;
441
}
442
443
-static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
444
+static RISCVException write_mideleg(CPURISCVState *env, int csrno,
445
+ target_ulong val)
446
{
447
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
448
if (riscv_has_ext(env, RVH)) {
449
env->mideleg |= VS_MODE_INTERRUPTS;
450
}
451
- return 0;
452
+ return RISCV_EXCP_NONE;
453
}
454
455
-static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
456
+static RISCVException read_mie(CPURISCVState *env, int csrno,
457
+ target_ulong *val)
458
{
459
*val = env->mie;
460
- return 0;
461
+ return RISCV_EXCP_NONE;
462
}
463
464
-static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
465
+static RISCVException write_mie(CPURISCVState *env, int csrno,
466
+ target_ulong val)
467
{
468
env->mie = (env->mie & ~all_ints) | (val & all_ints);
469
- return 0;
470
+ return RISCV_EXCP_NONE;
471
}
472
473
-static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
474
+static RISCVException read_mtvec(CPURISCVState *env, int csrno,
475
+ target_ulong *val)
476
{
477
*val = env->mtvec;
478
- return 0;
479
+ return RISCV_EXCP_NONE;
480
}
481
482
-static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
483
+static RISCVException write_mtvec(CPURISCVState *env, int csrno,
484
+ target_ulong val)
485
{
486
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
487
if ((val & 3) < 2) {
488
@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
489
} else {
490
qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
491
}
492
- return 0;
493
+ return RISCV_EXCP_NONE;
494
}
495
496
-static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
497
+static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
498
+ target_ulong *val)
499
{
500
*val = env->mcounteren;
501
- return 0;
502
+ return RISCV_EXCP_NONE;
503
}
504
505
-static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
506
+static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
507
+ target_ulong val)
508
{
509
env->mcounteren = val;
510
- return 0;
511
+ return RISCV_EXCP_NONE;
512
}
513
514
/* Machine Trap Handling */
515
-static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
516
+static RISCVException read_mscratch(CPURISCVState *env, int csrno,
517
+ target_ulong *val)
518
{
519
*val = env->mscratch;
520
- return 0;
521
+ return RISCV_EXCP_NONE;
522
}
523
524
-static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
525
+static RISCVException write_mscratch(CPURISCVState *env, int csrno,
526
+ target_ulong val)
527
{
528
env->mscratch = val;
529
- return 0;
530
+ return RISCV_EXCP_NONE;
531
}
532
533
-static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
534
+static RISCVException read_mepc(CPURISCVState *env, int csrno,
535
+ target_ulong *val)
536
{
537
*val = env->mepc;
538
- return 0;
539
+ return RISCV_EXCP_NONE;
540
}
541
542
-static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
543
+static RISCVException write_mepc(CPURISCVState *env, int csrno,
544
+ target_ulong val)
545
{
546
env->mepc = val;
547
- return 0;
548
+ return RISCV_EXCP_NONE;
549
}
550
551
-static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
552
+static RISCVException read_mcause(CPURISCVState *env, int csrno,
553
+ target_ulong *val)
554
{
555
*val = env->mcause;
556
- return 0;
557
+ return RISCV_EXCP_NONE;
558
}
559
560
-static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
561
+static RISCVException write_mcause(CPURISCVState *env, int csrno,
562
+ target_ulong val)
563
{
564
env->mcause = val;
565
- return 0;
566
+ return RISCV_EXCP_NONE;
567
}
568
569
-static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
570
+static RISCVException read_mtval(CPURISCVState *env, int csrno,
571
+ target_ulong *val)
572
{
573
*val = env->mtval;
574
- return 0;
575
+ return RISCV_EXCP_NONE;
576
}
577
578
-static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
579
+static RISCVException write_mtval(CPURISCVState *env, int csrno,
580
+ target_ulong val)
581
{
582
env->mtval = val;
583
- return 0;
584
+ return RISCV_EXCP_NONE;
585
}
586
587
-static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
588
- target_ulong new_value, target_ulong write_mask)
589
+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
590
+ target_ulong *ret_value,
591
+ target_ulong new_value, target_ulong write_mask)
592
{
593
RISCVCPU *cpu = env_archcpu(env);
594
/* Allow software control of delegable interrupts not claimed by hardware */
595
@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
596
*ret_value = old_mip;
597
}
598
599
- return 0;
600
+ return RISCV_EXCP_NONE;
601
}
602
603
/* Supervisor Trap Setup */
604
-static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
605
+static RISCVException read_sstatus(CPURISCVState *env, int csrno,
606
+ target_ulong *val)
607
{
608
target_ulong mask = (sstatus_v1_10_mask);
609
*val = env->mstatus & mask;
610
- return 0;
611
+ return RISCV_EXCP_NONE;
612
}
613
614
-static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
615
+static RISCVException write_sstatus(CPURISCVState *env, int csrno,
616
+ target_ulong val)
617
{
618
target_ulong mask = (sstatus_v1_10_mask);
619
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
620
return write_mstatus(env, CSR_MSTATUS, newval);
621
}
622
623
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
624
+static RISCVException read_vsie(CPURISCVState *env, int csrno,
625
+ target_ulong *val)
626
{
627
/* Shift the VS bits to their S bit location in vsie */
628
*val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
629
- return 0;
630
+ return RISCV_EXCP_NONE;
631
}
632
633
-static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
634
+static RISCVException read_sie(CPURISCVState *env, int csrno,
635
+ target_ulong *val)
636
{
637
if (riscv_cpu_virt_enabled(env)) {
638
read_vsie(env, CSR_VSIE, val);
639
} else {
640
*val = env->mie & env->mideleg;
641
}
642
- return 0;
643
+ return RISCV_EXCP_NONE;
644
}
645
646
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
647
+static RISCVException write_vsie(CPURISCVState *env, int csrno,
648
+ target_ulong val)
649
{
650
/* Shift the S bits to their VS bit location in mie */
651
target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
652
@@ -XXX,XX +XXX,XX @@ static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
653
write_mie(env, CSR_MIE, newval);
654
}
655
656
- return 0;
657
+ return RISCV_EXCP_NONE;
658
}
659
660
-static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
661
+static RISCVException read_stvec(CPURISCVState *env, int csrno,
662
+ target_ulong *val)
663
{
664
*val = env->stvec;
665
- return 0;
666
+ return RISCV_EXCP_NONE;
667
}
668
669
-static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
670
+static RISCVException write_stvec(CPURISCVState *env, int csrno,
671
+ target_ulong val)
672
{
673
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
674
if ((val & 3) < 2) {
675
@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
676
} else {
677
qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
678
}
679
- return 0;
680
+ return RISCV_EXCP_NONE;
681
}
682
683
-static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
684
+static RISCVException read_scounteren(CPURISCVState *env, int csrno,
685
+ target_ulong *val)
686
{
687
*val = env->scounteren;
688
- return 0;
689
+ return RISCV_EXCP_NONE;
690
}
691
692
-static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
693
+static RISCVException write_scounteren(CPURISCVState *env, int csrno,
694
+ target_ulong val)
695
{
696
env->scounteren = val;
697
- return 0;
698
+ return RISCV_EXCP_NONE;
699
}
700
701
/* Supervisor Trap Handling */
702
-static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
703
+static RISCVException read_sscratch(CPURISCVState *env, int csrno,
704
+ target_ulong *val)
705
{
706
*val = env->sscratch;
707
- return 0;
708
+ return RISCV_EXCP_NONE;
709
}
710
711
-static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
712
+static RISCVException write_sscratch(CPURISCVState *env, int csrno,
713
+ target_ulong val)
714
{
715
env->sscratch = val;
716
- return 0;
717
+ return RISCV_EXCP_NONE;
718
}
719
720
-static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
721
+static RISCVException read_sepc(CPURISCVState *env, int csrno,
722
+ target_ulong *val)
723
{
724
*val = env->sepc;
725
- return 0;
726
+ return RISCV_EXCP_NONE;
727
}
728
729
-static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
730
+static RISCVException write_sepc(CPURISCVState *env, int csrno,
731
+ target_ulong val)
732
{
733
env->sepc = val;
734
- return 0;
735
+ return RISCV_EXCP_NONE;
736
}
737
738
-static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
739
+static RISCVException read_scause(CPURISCVState *env, int csrno,
740
+ target_ulong *val)
741
{
742
*val = env->scause;
743
- return 0;
744
+ return RISCV_EXCP_NONE;
745
}
746
747
-static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
748
+static RISCVException write_scause(CPURISCVState *env, int csrno,
749
+ target_ulong val)
750
{
751
env->scause = val;
752
- return 0;
753
+ return RISCV_EXCP_NONE;
754
}
755
756
-static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
757
+static RISCVException read_stval(CPURISCVState *env, int csrno,
758
+ target_ulong *val)
759
{
760
*val = env->stval;
761
- return 0;
762
+ return RISCV_EXCP_NONE;
763
}
764
765
-static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
766
+static RISCVException write_stval(CPURISCVState *env, int csrno,
767
+ target_ulong val)
768
{
769
env->stval = val;
770
- return 0;
771
+ return RISCV_EXCP_NONE;
772
}
773
774
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
775
- target_ulong new_value, target_ulong write_mask)
776
+static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
777
+ target_ulong *ret_value,
778
+ target_ulong new_value, target_ulong write_mask)
779
{
780
/* Shift the S bits to their VS bit location in mip */
781
int ret = rmw_mip(env, 0, ret_value, new_value << 1,
782
@@ -XXX,XX +XXX,XX @@ static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
783
return ret;
21
return ret;
784
}
22
}
785
23
786
-static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
24
-static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
787
- target_ulong new_value, target_ulong write_mask)
25
- uint32_t *phandle, uint32_t *intc_phandles,
788
+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
26
- uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
789
+ target_ulong *ret_value,
27
+static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
790
+ target_ulong new_value, target_ulong write_mask)
28
+ uint32_t *intc_phandles, uint32_t msi_phandle,
29
+ bool m_mode, uint32_t imsic_guest_bits)
791
{
30
{
792
int ret;
31
int cpu, socket;
793
32
char *imsic_name;
794
@@ -XXX,XX +XXX,XX @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
33
MachineState *ms = MACHINE(s);
34
int socket_count = riscv_socket_count(ms);
35
- uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
36
+ uint32_t imsic_max_hart_per_socket;
37
uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
38
39
- *msi_m_phandle = (*phandle)++;
40
- *msi_s_phandle = (*phandle)++;
41
imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
42
imsic_regs = g_new0(uint32_t, socket_count * 4);
43
44
- /* M-level IMSIC node */
45
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
46
imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
47
- imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
48
+ imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
49
}
50
- imsic_max_hart_per_socket = 0;
51
- for (socket = 0; socket < socket_count; socket++) {
52
- imsic_addr = memmap[VIRT_IMSIC_M].base +
53
- socket * VIRT_IMSIC_GROUP_MAX_SIZE;
54
- imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
55
- imsic_regs[socket * 4 + 0] = 0;
56
- imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
57
- imsic_regs[socket * 4 + 2] = 0;
58
- imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
59
- if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
60
- imsic_max_hart_per_socket = s->soc[socket].num_harts;
61
- }
62
- }
63
- imsic_name = g_strdup_printf("/soc/imsics@%lx",
64
- (unsigned long)memmap[VIRT_IMSIC_M].base);
65
- qemu_fdt_add_subnode(ms->fdt, imsic_name);
66
- qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
67
- "riscv,imsics");
68
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
69
- FDT_IMSIC_INT_CELLS);
70
- qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
71
- NULL, 0);
72
- qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
73
- NULL, 0);
74
- qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
75
- imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
76
- qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
77
- socket_count * sizeof(uint32_t) * 4);
78
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
79
- VIRT_IRQCHIP_NUM_MSIS);
80
- if (socket_count > 1) {
81
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
82
- imsic_num_bits(imsic_max_hart_per_socket));
83
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
84
- imsic_num_bits(socket_count));
85
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
86
- IMSIC_MMIO_GROUP_MIN_SHIFT);
87
- }
88
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
89
-
90
- g_free(imsic_name);
91
92
- /* S-level IMSIC node */
93
- for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
94
- imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
95
- imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
96
- }
97
- imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
98
imsic_max_hart_per_socket = 0;
99
for (socket = 0; socket < socket_count; socket++) {
100
- imsic_addr = memmap[VIRT_IMSIC_S].base +
101
- socket * VIRT_IMSIC_GROUP_MAX_SIZE;
102
+ imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
103
imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
104
s->soc[socket].num_harts;
105
imsic_regs[socket * 4 + 0] = 0;
106
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
107
imsic_max_hart_per_socket = s->soc[socket].num_harts;
108
}
109
}
110
- imsic_name = g_strdup_printf("/soc/imsics@%lx",
111
- (unsigned long)memmap[VIRT_IMSIC_S].base);
112
+
113
+ imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr);
114
qemu_fdt_add_subnode(ms->fdt, imsic_name);
115
- qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
116
- "riscv,imsics");
117
+ qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics");
118
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
119
- FDT_IMSIC_INT_CELLS);
120
- qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
121
- NULL, 0);
122
- qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
123
- NULL, 0);
124
+ FDT_IMSIC_INT_CELLS);
125
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
126
+ qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
127
qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
128
- imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
129
+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
130
qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
131
- socket_count * sizeof(uint32_t) * 4);
132
+ socket_count * sizeof(uint32_t) * 4);
133
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
134
- VIRT_IRQCHIP_NUM_MSIS);
135
+ VIRT_IRQCHIP_NUM_MSIS);
136
+
137
if (imsic_guest_bits) {
138
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
139
- imsic_guest_bits);
140
+ imsic_guest_bits);
141
}
142
+
143
if (socket_count > 1) {
144
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
145
- imsic_num_bits(imsic_max_hart_per_socket));
146
+ imsic_num_bits(imsic_max_hart_per_socket));
147
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
148
- imsic_num_bits(socket_count));
149
+ imsic_num_bits(socket_count));
150
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
151
- IMSIC_MMIO_GROUP_MIN_SHIFT);
152
+ IMSIC_MMIO_GROUP_MIN_SHIFT);
153
}
154
- qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
155
- g_free(imsic_name);
156
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
157
158
+ g_free(imsic_name);
159
g_free(imsic_regs);
160
g_free(imsic_cells);
795
}
161
}
796
162
797
/* Supervisor Protection and Translation */
163
-static void create_fdt_socket_aplic(RISCVVirtState *s,
798
-static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
164
- const MemMapEntry *memmap, int socket,
799
+static RISCVException read_satp(CPURISCVState *env, int csrno,
165
- uint32_t msi_m_phandle,
800
+ target_ulong *val)
166
- uint32_t msi_s_phandle,
167
- uint32_t *phandle,
168
- uint32_t *intc_phandles,
169
- uint32_t *aplic_phandles)
170
+static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
171
+ uint32_t *phandle, uint32_t *intc_phandles,
172
+ uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
173
+{
174
+ *msi_m_phandle = (*phandle)++;
175
+ *msi_s_phandle = (*phandle)++;
176
+
177
+ if (!kvm_enabled()) {
178
+ /* M-level IMSIC node */
179
+ create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles,
180
+ *msi_m_phandle, true, 0);
181
+ }
182
+
183
+ /* S-level IMSIC node */
184
+ create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles,
185
+ *msi_s_phandle, false,
186
+ imsic_num_bits(s->aia_guests + 1));
187
+
188
+}
189
+
190
+static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
191
+ unsigned long aplic_addr, uint32_t aplic_size,
192
+ uint32_t msi_phandle,
193
+ uint32_t *intc_phandles,
194
+ uint32_t aplic_phandle,
195
+ uint32_t aplic_child_phandle,
196
+ bool m_mode)
801
{
197
{
802
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
198
int cpu;
803
*val = 0;
199
char *aplic_name;
804
- return 0;
200
uint32_t *aplic_cells;
805
+ return RISCV_EXCP_NONE;
201
- unsigned long aplic_addr;
806
}
202
MachineState *ms = MACHINE(s);
807
203
- uint32_t aplic_m_phandle, aplic_s_phandle;
808
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
204
809
- return -RISCV_EXCP_ILLEGAL_INST;
205
- aplic_m_phandle = (*phandle)++;
810
+ return RISCV_EXCP_ILLEGAL_INST;
206
- aplic_s_phandle = (*phandle)++;
207
aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
208
209
- /* M-level APLIC node */
210
for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
211
aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
212
- aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
213
+ aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
214
}
215
- aplic_addr = memmap[VIRT_APLIC_M].base +
216
- (memmap[VIRT_APLIC_M].size * socket);
217
+
218
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
219
qemu_fdt_add_subnode(ms->fdt, aplic_name);
220
qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
221
qemu_fdt_setprop_cell(ms->fdt, aplic_name,
222
- "#interrupt-cells", FDT_APLIC_INT_CELLS);
223
+ "#interrupt-cells", FDT_APLIC_INT_CELLS);
224
qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
225
+
226
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
227
qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
228
- aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
229
+ aplic_cells,
230
+ s->soc[socket].num_harts * sizeof(uint32_t) * 2);
811
} else {
231
} else {
812
*val = env->satp;
232
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
813
}
233
- msi_m_phandle);
814
234
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
815
- return 0;
235
}
816
+ return RISCV_EXCP_NONE;
236
+
237
qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
238
- 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
239
+ 0x0, aplic_addr, 0x0, aplic_size);
240
qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
241
- VIRT_IRQCHIP_NUM_SOURCES);
242
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
243
- aplic_s_phandle);
244
- qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
245
- aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
246
+ VIRT_IRQCHIP_NUM_SOURCES);
247
+
248
+ if (aplic_child_phandle) {
249
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
250
+ aplic_child_phandle);
251
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
252
+ aplic_child_phandle, 0x1,
253
+ VIRT_IRQCHIP_NUM_SOURCES);
254
+ }
255
+
256
riscv_socket_fdt_write_id(ms, aplic_name, socket);
257
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
258
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
259
+
260
g_free(aplic_name);
261
+ g_free(aplic_cells);
262
+}
263
264
- /* S-level APLIC node */
265
- for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
266
- aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
267
- aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
268
+static void create_fdt_socket_aplic(RISCVVirtState *s,
269
+ const MemMapEntry *memmap, int socket,
270
+ uint32_t msi_m_phandle,
271
+ uint32_t msi_s_phandle,
272
+ uint32_t *phandle,
273
+ uint32_t *intc_phandles,
274
+ uint32_t *aplic_phandles)
275
+{
276
+ char *aplic_name;
277
+ unsigned long aplic_addr;
278
+ MachineState *ms = MACHINE(s);
279
+ uint32_t aplic_m_phandle, aplic_s_phandle;
280
+
281
+ aplic_m_phandle = (*phandle)++;
282
+ aplic_s_phandle = (*phandle)++;
283
+
284
+ if (!kvm_enabled()) {
285
+ /* M-level APLIC node */
286
+ aplic_addr = memmap[VIRT_APLIC_M].base +
287
+ (memmap[VIRT_APLIC_M].size * socket);
288
+ create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
289
+ msi_m_phandle, intc_phandles,
290
+ aplic_m_phandle, aplic_s_phandle,
291
+ true);
292
}
293
+
294
+ /* S-level APLIC node */
295
aplic_addr = memmap[VIRT_APLIC_S].base +
296
(memmap[VIRT_APLIC_S].size * socket);
297
+ create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
298
+ msi_s_phandle, intc_phandles,
299
+ aplic_s_phandle, 0,
300
+ false);
301
+
302
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
303
- qemu_fdt_add_subnode(ms->fdt, aplic_name);
304
- qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
305
- qemu_fdt_setprop_cell(ms->fdt, aplic_name,
306
- "#interrupt-cells", FDT_APLIC_INT_CELLS);
307
- qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
308
- if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
309
- qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
310
- aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
311
- } else {
312
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
313
- msi_s_phandle);
314
- }
315
- qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
316
- 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
317
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
318
- VIRT_IRQCHIP_NUM_SOURCES);
319
- riscv_socket_fdt_write_id(ms, aplic_name, socket);
320
- qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
321
322
if (!socket) {
323
platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
324
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
325
326
g_free(aplic_name);
327
328
- g_free(aplic_cells);
329
aplic_phandles[socket] = aplic_s_phandle;
817
}
330
}
818
331
819
-static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
332
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
820
+static RISCVException write_satp(CPURISCVState *env, int csrno,
333
int i;
821
+ target_ulong val)
334
hwaddr addr;
822
{
335
uint32_t guest_bits;
823
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
336
- DeviceState *aplic_m;
824
- return 0;
337
- bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
825
+ return RISCV_EXCP_NONE;
338
+ DeviceState *aplic_s = NULL;
826
}
339
+ DeviceState *aplic_m = NULL;
827
if (validate_vm(env, get_field(val, SATP_MODE)) &&
340
+ bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
828
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
341
829
{
342
if (msimode) {
830
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
343
- /* Per-socket M-level IMSICs */
831
- return -RISCV_EXCP_ILLEGAL_INST;
344
- addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
832
+ return RISCV_EXCP_ILLEGAL_INST;
345
- for (i = 0; i < hart_count; i++) {
833
} else {
346
- riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
834
if ((val ^ env->satp) & SATP_ASID) {
347
- base_hartid + i, true, 1,
835
tlb_flush(env_cpu(env));
348
- VIRT_IRQCHIP_NUM_MSIS);
836
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
349
+ if (!kvm_enabled()) {
837
env->satp = val;
350
+ /* Per-socket M-level IMSICs */
351
+ addr = memmap[VIRT_IMSIC_M].base +
352
+ socket * VIRT_IMSIC_GROUP_MAX_SIZE;
353
+ for (i = 0; i < hart_count; i++) {
354
+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
355
+ base_hartid + i, true, 1,
356
+ VIRT_IRQCHIP_NUM_MSIS);
357
+ }
838
}
358
}
839
}
359
840
- return 0;
360
/* Per-socket S-level IMSICs */
841
+ return RISCV_EXCP_NONE;
361
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
362
}
363
}
364
365
- /* Per-socket M-level APLIC */
366
- aplic_m = riscv_aplic_create(
367
- memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
368
- memmap[VIRT_APLIC_M].size,
369
- (msimode) ? 0 : base_hartid,
370
- (msimode) ? 0 : hart_count,
371
- VIRT_IRQCHIP_NUM_SOURCES,
372
- VIRT_IRQCHIP_NUM_PRIO_BITS,
373
- msimode, true, NULL);
374
-
375
- if (aplic_m) {
376
- /* Per-socket S-level APLIC */
377
- riscv_aplic_create(
378
- memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
379
- memmap[VIRT_APLIC_S].size,
380
- (msimode) ? 0 : base_hartid,
381
- (msimode) ? 0 : hart_count,
382
- VIRT_IRQCHIP_NUM_SOURCES,
383
- VIRT_IRQCHIP_NUM_PRIO_BITS,
384
- msimode, false, aplic_m);
385
+ if (!kvm_enabled()) {
386
+ /* Per-socket M-level APLIC */
387
+ aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
388
+ socket * memmap[VIRT_APLIC_M].size,
389
+ memmap[VIRT_APLIC_M].size,
390
+ (msimode) ? 0 : base_hartid,
391
+ (msimode) ? 0 : hart_count,
392
+ VIRT_IRQCHIP_NUM_SOURCES,
393
+ VIRT_IRQCHIP_NUM_PRIO_BITS,
394
+ msimode, true, NULL);
395
}
396
397
- return aplic_m;
398
+ /* Per-socket S-level APLIC */
399
+ aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
400
+ socket * memmap[VIRT_APLIC_S].size,
401
+ memmap[VIRT_APLIC_S].size,
402
+ (msimode) ? 0 : base_hartid,
403
+ (msimode) ? 0 : hart_count,
404
+ VIRT_IRQCHIP_NUM_SOURCES,
405
+ VIRT_IRQCHIP_NUM_PRIO_BITS,
406
+ msimode, false, aplic_m);
407
+
408
+ return kvm_enabled() ? aplic_s : aplic_m;
842
}
409
}
843
410
844
/* Hypervisor Extensions */
411
static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
845
-static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
846
+static RISCVException read_hstatus(CPURISCVState *env, int csrno,
847
+ target_ulong *val)
848
{
849
*val = env->hstatus;
850
if (!riscv_cpu_is_32bit(env)) {
851
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
852
}
853
/* We only support little endian */
854
*val = set_field(*val, HSTATUS_VSBE, 0);
855
- return 0;
856
+ return RISCV_EXCP_NONE;
857
}
858
859
-static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
860
+static RISCVException write_hstatus(CPURISCVState *env, int csrno,
861
+ target_ulong val)
862
{
863
env->hstatus = val;
864
if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
865
@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
866
if (get_field(val, HSTATUS_VSBE) != 0) {
867
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
868
}
869
- return 0;
870
+ return RISCV_EXCP_NONE;
871
}
872
873
-static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
874
+static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
875
+ target_ulong *val)
876
{
877
*val = env->hedeleg;
878
- return 0;
879
+ return RISCV_EXCP_NONE;
880
}
881
882
-static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
883
+static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
884
+ target_ulong val)
885
{
886
env->hedeleg = val;
887
- return 0;
888
+ return RISCV_EXCP_NONE;
889
}
890
891
-static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
892
+static RISCVException read_hideleg(CPURISCVState *env, int csrno,
893
+ target_ulong *val)
894
{
895
*val = env->hideleg;
896
- return 0;
897
+ return RISCV_EXCP_NONE;
898
}
899
900
-static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
901
+static RISCVException write_hideleg(CPURISCVState *env, int csrno,
902
+ target_ulong val)
903
{
904
env->hideleg = val;
905
- return 0;
906
+ return RISCV_EXCP_NONE;
907
}
908
909
-static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
910
- target_ulong new_value, target_ulong write_mask)
911
+static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
912
+ target_ulong *ret_value,
913
+ target_ulong new_value, target_ulong write_mask)
914
{
915
int ret = rmw_mip(env, 0, ret_value, new_value,
916
write_mask & hvip_writable_mask);
917
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
918
return ret;
919
}
920
921
-static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
922
- target_ulong new_value, target_ulong write_mask)
923
+static RISCVException rmw_hip(CPURISCVState *env, int csrno,
924
+ target_ulong *ret_value,
925
+ target_ulong new_value, target_ulong write_mask)
926
{
927
int ret = rmw_mip(env, 0, ret_value, new_value,
928
write_mask & hip_writable_mask);
929
@@ -XXX,XX +XXX,XX @@ static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
930
return ret;
931
}
932
933
-static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
934
+static RISCVException read_hie(CPURISCVState *env, int csrno,
935
+ target_ulong *val)
936
{
937
*val = env->mie & VS_MODE_INTERRUPTS;
938
- return 0;
939
+ return RISCV_EXCP_NONE;
940
}
941
942
-static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
943
+static RISCVException write_hie(CPURISCVState *env, int csrno,
944
+ target_ulong val)
945
{
946
target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
947
return write_mie(env, CSR_MIE, newval);
948
}
949
950
-static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
951
+static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
952
+ target_ulong *val)
953
{
954
*val = env->hcounteren;
955
- return 0;
956
+ return RISCV_EXCP_NONE;
957
}
958
959
-static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
960
+static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
961
+ target_ulong val)
962
{
963
env->hcounteren = val;
964
- return 0;
965
+ return RISCV_EXCP_NONE;
966
}
967
968
-static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
969
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
970
+ target_ulong *val)
971
{
972
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
973
- return 0;
974
+ return RISCV_EXCP_NONE;
975
}
976
977
-static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
978
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
979
+ target_ulong val)
980
{
981
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
982
- return 0;
983
+ return RISCV_EXCP_NONE;
984
}
985
986
-static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
987
+static RISCVException read_htval(CPURISCVState *env, int csrno,
988
+ target_ulong *val)
989
{
990
*val = env->htval;
991
- return 0;
992
+ return RISCV_EXCP_NONE;
993
}
994
995
-static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
996
+static RISCVException write_htval(CPURISCVState *env, int csrno,
997
+ target_ulong val)
998
{
999
env->htval = val;
1000
- return 0;
1001
+ return RISCV_EXCP_NONE;
1002
}
1003
1004
-static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1005
+static RISCVException read_htinst(CPURISCVState *env, int csrno,
1006
+ target_ulong *val)
1007
{
1008
*val = env->htinst;
1009
- return 0;
1010
+ return RISCV_EXCP_NONE;
1011
}
1012
1013
-static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1014
+static RISCVException write_htinst(CPURISCVState *env, int csrno,
1015
+ target_ulong val)
1016
{
1017
- return 0;
1018
+ return RISCV_EXCP_NONE;
1019
}
1020
1021
-static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1022
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
1023
+ target_ulong *val)
1024
{
1025
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1026
- return 0;
1027
+ return RISCV_EXCP_NONE;
1028
}
1029
1030
-static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1031
+static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1032
+ target_ulong val)
1033
{
1034
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1035
- return 0;
1036
+ return RISCV_EXCP_NONE;
1037
}
1038
1039
-static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1040
+static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1041
+ target_ulong *val)
1042
{
1043
*val = env->hgatp;
1044
- return 0;
1045
+ return RISCV_EXCP_NONE;
1046
}
1047
1048
-static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1049
+static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1050
+ target_ulong val)
1051
{
1052
env->hgatp = val;
1053
- return 0;
1054
+ return RISCV_EXCP_NONE;
1055
}
1056
1057
-static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1058
+static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1059
+ target_ulong *val)
1060
{
1061
if (!env->rdtime_fn) {
1062
- return -RISCV_EXCP_ILLEGAL_INST;
1063
+ return RISCV_EXCP_ILLEGAL_INST;
1064
}
1065
1066
*val = env->htimedelta;
1067
- return 0;
1068
+ return RISCV_EXCP_NONE;
1069
}
1070
1071
-static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1072
+static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1073
+ target_ulong val)
1074
{
1075
if (!env->rdtime_fn) {
1076
- return -RISCV_EXCP_ILLEGAL_INST;
1077
+ return RISCV_EXCP_ILLEGAL_INST;
1078
}
1079
1080
if (riscv_cpu_is_32bit(env)) {
1081
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1082
} else {
1083
env->htimedelta = val;
1084
}
1085
- return 0;
1086
+ return RISCV_EXCP_NONE;
1087
}
1088
1089
-static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1090
+static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1091
+ target_ulong *val)
1092
{
1093
if (!env->rdtime_fn) {
1094
- return -RISCV_EXCP_ILLEGAL_INST;
1095
+ return RISCV_EXCP_ILLEGAL_INST;
1096
}
1097
1098
*val = env->htimedelta >> 32;
1099
- return 0;
1100
+ return RISCV_EXCP_NONE;
1101
}
1102
1103
-static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1104
+static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1105
+ target_ulong val)
1106
{
1107
if (!env->rdtime_fn) {
1108
- return -RISCV_EXCP_ILLEGAL_INST;
1109
+ return RISCV_EXCP_ILLEGAL_INST;
1110
}
1111
1112
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1113
- return 0;
1114
+ return RISCV_EXCP_NONE;
1115
}
1116
1117
/* Virtual CSR Registers */
1118
-static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1119
+static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1120
+ target_ulong *val)
1121
{
1122
*val = env->vsstatus;
1123
- return 0;
1124
+ return RISCV_EXCP_NONE;
1125
}
1126
1127
-static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1128
+static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1129
+ target_ulong val)
1130
{
1131
uint64_t mask = (target_ulong)-1;
1132
env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1133
- return 0;
1134
+ return RISCV_EXCP_NONE;
1135
}
1136
1137
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1138
{
1139
*val = env->vstvec;
1140
- return 0;
1141
+ return RISCV_EXCP_NONE;
1142
}
1143
1144
-static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1145
+static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1146
+ target_ulong val)
1147
{
1148
env->vstvec = val;
1149
- return 0;
1150
+ return RISCV_EXCP_NONE;
1151
}
1152
1153
-static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1154
+static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1155
+ target_ulong *val)
1156
{
1157
*val = env->vsscratch;
1158
- return 0;
1159
+ return RISCV_EXCP_NONE;
1160
}
1161
1162
-static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1163
+static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1164
+ target_ulong val)
1165
{
1166
env->vsscratch = val;
1167
- return 0;
1168
+ return RISCV_EXCP_NONE;
1169
}
1170
1171
-static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1172
+static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1173
+ target_ulong *val)
1174
{
1175
*val = env->vsepc;
1176
- return 0;
1177
+ return RISCV_EXCP_NONE;
1178
}
1179
1180
-static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1181
+static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1182
+ target_ulong val)
1183
{
1184
env->vsepc = val;
1185
- return 0;
1186
+ return RISCV_EXCP_NONE;
1187
}
1188
1189
-static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1190
+static RISCVException read_vscause(CPURISCVState *env, int csrno,
1191
+ target_ulong *val)
1192
{
1193
*val = env->vscause;
1194
- return 0;
1195
+ return RISCV_EXCP_NONE;
1196
}
1197
1198
-static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1199
+static RISCVException write_vscause(CPURISCVState *env, int csrno,
1200
+ target_ulong val)
1201
{
1202
env->vscause = val;
1203
- return 0;
1204
+ return RISCV_EXCP_NONE;
1205
}
1206
1207
-static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1208
+static RISCVException read_vstval(CPURISCVState *env, int csrno,
1209
+ target_ulong *val)
1210
{
1211
*val = env->vstval;
1212
- return 0;
1213
+ return RISCV_EXCP_NONE;
1214
}
1215
1216
-static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1217
+static RISCVException write_vstval(CPURISCVState *env, int csrno,
1218
+ target_ulong val)
1219
{
1220
env->vstval = val;
1221
- return 0;
1222
+ return RISCV_EXCP_NONE;
1223
}
1224
1225
-static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1226
+static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1227
+ target_ulong *val)
1228
{
1229
*val = env->vsatp;
1230
- return 0;
1231
+ return RISCV_EXCP_NONE;
1232
}
1233
1234
-static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1235
+static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1236
+ target_ulong val)
1237
{
1238
env->vsatp = val;
1239
- return 0;
1240
+ return RISCV_EXCP_NONE;
1241
}
1242
1243
-static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1244
+static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1245
+ target_ulong *val)
1246
{
1247
*val = env->mtval2;
1248
- return 0;
1249
+ return RISCV_EXCP_NONE;
1250
}
1251
1252
-static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1253
+static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1254
+ target_ulong val)
1255
{
1256
env->mtval2 = val;
1257
- return 0;
1258
+ return RISCV_EXCP_NONE;
1259
}
1260
1261
-static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1262
+static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1263
+ target_ulong *val)
1264
{
1265
*val = env->mtinst;
1266
- return 0;
1267
+ return RISCV_EXCP_NONE;
1268
}
1269
1270
-static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1271
+static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1272
+ target_ulong val)
1273
{
1274
env->mtinst = val;
1275
- return 0;
1276
+ return RISCV_EXCP_NONE;
1277
}
1278
1279
/* Physical Memory Protection */
1280
-static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1281
+static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1282
+ target_ulong *val)
1283
{
1284
*val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1285
- return 0;
1286
+ return RISCV_EXCP_NONE;
1287
}
1288
1289
-static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1290
+static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1291
+ target_ulong val)
1292
{
1293
pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1294
- return 0;
1295
+ return RISCV_EXCP_NONE;
1296
}
1297
1298
-static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1299
+static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1300
+ target_ulong *val)
1301
{
1302
*val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1303
- return 0;
1304
+ return RISCV_EXCP_NONE;
1305
}
1306
1307
-static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1308
+static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1309
+ target_ulong val)
1310
{
1311
pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1312
- return 0;
1313
+ return RISCV_EXCP_NONE;
1314
}
1315
1316
#endif
1317
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1318
1319
/* execute combined read/write operation if it exists */
1320
if (csr_ops[csrno].op) {
1321
- return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1322
+ ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1323
+ if (ret != RISCV_EXCP_NONE) {
1324
+ return -ret;
1325
+ }
1326
+ return 0;
1327
}
1328
1329
/* if no accessor exists then return failure */
1330
if (!csr_ops[csrno].read) {
1331
return -RISCV_EXCP_ILLEGAL_INST;
1332
}
1333
-
1334
/* read old value */
1335
ret = csr_ops[csrno].read(env, csrno, &old_value);
1336
- if (ret < 0) {
1337
- return ret;
1338
+ if (ret != RISCV_EXCP_NONE) {
1339
+ return -ret;
1340
}
1341
1342
/* write value if writable and write mask set, otherwise drop writes */
1343
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1344
new_value = (old_value & ~write_mask) | (new_value & write_mask);
1345
if (csr_ops[csrno].write) {
1346
ret = csr_ops[csrno].write(env, csrno, new_value);
1347
- if (ret < 0) {
1348
- return ret;
1349
+ if (ret != RISCV_EXCP_NONE) {
1350
+ return -ret;
1351
}
1352
}
1353
}
1354
--
412
--
1355
2.31.1
413
2.41.0
1356
1357
diff view generated by jsdifflib
[PULL 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers
[PULL v2 30/45] target/riscv: check the in-kernel irqchip support
1
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
been involved recently.
3
2
4
Also add Bin who has been helping with reviews.
3
We check the in-kernel irqchip support when using KVM acceleration.
5
4
5
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
6
Reviewed-by: Jim Shu <jim.shu@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
9
Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Acked-by: Bin Meng <bin.meng@windriver.com>
8
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
11
---
11
---
12
MAINTAINERS | 5 ++---
12
target/riscv/kvm.c | 10 +++++++++-
13
1 file changed, 2 insertions(+), 3 deletions(-)
13
1 file changed, 9 insertions(+), 1 deletion(-)
14
14
15
diff --git a/MAINTAINERS b/MAINTAINERS
15
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/MAINTAINERS
17
--- a/target/riscv/kvm.c
18
+++ b/MAINTAINERS
18
+++ b/target/riscv/kvm.c
19
@@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_ppc.py
19
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
20
20
21
RISC-V TCG CPUs
21
int kvm_arch_irqchip_create(KVMState *s)
22
M: Palmer Dabbelt <palmer@dabbelt.com>
22
{
23
-M: Alistair Francis <Alistair.Francis@wdc.com>
23
- return 0;
24
-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
24
+ if (kvm_kernel_irqchip_split()) {
25
-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
25
+ error_report("-machine kernel_irqchip=split is not supported on RISC-V.");
26
+M: Alistair Francis <alistair.francis@wdc.com>
26
+ exit(1);
27
+M: Bin Meng <bin.meng@windriver.com>
27
+ }
28
L: qemu-riscv@nongnu.org
28
+
29
S: Supported
29
+ /*
30
F: target/riscv/
30
+ * We can create the VAIA using the newer device control API.
31
+ */
32
+ return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
33
}
34
35
int kvm_arch_process_async_events(CPUState *cs)
31
--
36
--
32
2.31.1
37
2.41.0
33
34
diff view generated by jsdifflib
[PULL 23/42] target/riscv: Add ePMP CSR access functions
[PULL v2 31/45] target/riscv: Create an KVM AIA irqchip
1
From: Hou Weiying <weiying_hou@outlook.com>
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
2
3
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
3
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
4
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
4
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
5
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
5
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
6
parameter is passed along with --accel in QEMU command-line.
7
1) "riscv-aia=emul": IMSIC is emulated by hypervisor
8
2) "riscv-aia=hwaccel": use hardware guest IMSIC
9
3) "riscv-aia=auto": use the hardware guest IMSICs whenever available
10
otherwise we fallback to software emulation.
11
12
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
13
Reviewed-by: Jim Shu <jim.shu@sifive.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
16
Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
9
[ Changes by AF:
10
- Rebase on master
11
- Fix build errors
12
- Fix some style issues
13
]
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
16
---
18
---
17
target/riscv/cpu.h | 1 +
19
target/riscv/kvm_riscv.h | 4 +
18
target/riscv/pmp.h | 14 ++++++++++++++
20
target/riscv/kvm.c | 186 +++++++++++++++++++++++++++++++++++++++
19
target/riscv/csr.c | 24 ++++++++++++++++++++++++
21
2 files changed, 190 insertions(+)
20
target/riscv/pmp.c | 34 ++++++++++++++++++++++++++++++++++
21
target/riscv/trace-events | 3 +++
22
5 files changed, 76 insertions(+)
23
22
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
25
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
25
--- a/target/riscv/kvm_riscv.h
27
+++ b/target/riscv/cpu.h
26
+++ b/target/riscv/kvm_riscv.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
27
@@ -XXX,XX +XXX,XX @@
29
28
void kvm_riscv_init_user_properties(Object *cpu_obj);
30
/* physical memory protection */
29
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
31
pmp_table_t pmp_state;
30
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
32
+ target_ulong mseccfg;
31
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
33
32
+ uint64_t aia_irq_num, uint64_t aia_msi_num,
34
/* machine specific rdtime callback */
33
+ uint64_t aplic_base, uint64_t imsic_base,
35
uint64_t (*rdtime_fn)(uint32_t);
34
+ uint64_t guest_num);
36
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
35
36
#endif
37
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
37
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/pmp.h
39
--- a/target/riscv/kvm.c
39
+++ b/target/riscv/pmp.h
40
+++ b/target/riscv/kvm.c
40
@@ -XXX,XX +XXX,XX @@ typedef enum {
41
@@ -XXX,XX +XXX,XX @@
41
PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
42
#include "exec/address-spaces.h"
42
} pmp_am_t;
43
#include "hw/boards.h"
43
44
#include "hw/irq.h"
44
+typedef enum {
45
+#include "hw/intc/riscv_imsic.h"
45
+ MSECCFG_MML = 1 << 0,
46
#include "qemu/log.h"
46
+ MSECCFG_MMWP = 1 << 1,
47
#include "hw/loader.h"
47
+ MSECCFG_RLB = 1 << 2
48
#include "kvm_riscv.h"
48
+} mseccfg_field_t;
49
@@ -XXX,XX +XXX,XX @@
49
+
50
#include "chardev/char-fe.h"
50
typedef struct {
51
#include "migration/migration.h"
51
target_ulong addr_reg;
52
#include "sysemu/runstate.h"
52
uint8_t cfg_reg;
53
+#include "hw/riscv/numa.h"
53
@@ -XXX,XX +XXX,XX @@ typedef struct {
54
54
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
55
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
55
target_ulong val);
56
uint64_t idx)
56
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
57
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_cpu_check_are_resettable(void)
57
+
58
return true;
58
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
59
+target_ulong mseccfg_csr_read(CPURISCVState *env);
60
+
61
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
62
target_ulong val);
63
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
64
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env);
65
uint32_t pmp_get_num_rules(CPURISCVState *env);
66
int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
67
68
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
69
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
70
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
71
+
72
#endif
73
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/csr.c
76
+++ b/target/riscv/csr.c
77
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
78
79
return RISCV_EXCP_ILLEGAL_INST;
80
}
59
}
81
+
60
82
+static RISCVException epmp(CPURISCVState *env, int csrno)
61
+static int aia_mode;
83
+{
62
+
84
+ if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
63
+static const char *kvm_aia_mode_str(uint64_t mode)
85
+ return RISCV_EXCP_NONE;
64
+{
86
+ }
65
+ switch (mode) {
87
+
66
+ case KVM_DEV_RISCV_AIA_MODE_EMUL:
88
+ return RISCV_EXCP_ILLEGAL_INST;
67
+ return "emul";
89
+}
68
+ case KVM_DEV_RISCV_AIA_MODE_HWACCEL:
90
#endif
69
+ return "hwaccel";
91
70
+ case KVM_DEV_RISCV_AIA_MODE_AUTO:
92
/* User Floating-Point CSRs */
71
+ default:
93
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
72
+ return "auto";
94
}
73
+ };
95
74
+}
96
/* Physical Memory Protection */
75
+
97
+static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
76
+static char *riscv_get_kvm_aia(Object *obj, Error **errp)
98
+ target_ulong *val)
77
+{
99
+{
78
+ return g_strdup(kvm_aia_mode_str(aia_mode));
100
+ *val = mseccfg_csr_read(env);
79
+}
101
+ return RISCV_EXCP_NONE;
80
+
102
+}
81
+static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp)
103
+
82
+{
104
+static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
83
+ if (!strcmp(val, "emul")) {
105
+ target_ulong val)
84
+ aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL;
106
+{
85
+ } else if (!strcmp(val, "hwaccel")) {
107
+ mseccfg_csr_write(env, val);
86
+ aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL;
108
+ return RISCV_EXCP_NONE;
87
+ } else if (!strcmp(val, "auto")) {
109
+}
88
+ aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO;
110
+
89
+ } else {
111
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
90
+ error_setg(errp, "Invalid KVM AIA mode");
112
target_ulong *val)
91
+ error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n");
92
+ }
93
+}
94
+
95
void kvm_arch_accel_class_init(ObjectClass *oc)
113
{
96
{
114
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
97
+ object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia,
115
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
98
+ riscv_set_kvm_aia);
116
99
+ object_class_property_set_description(oc, "riscv-aia",
117
/* Physical Memory Protection */
100
+ "Set KVM AIA mode. Valid values are "
118
+ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
101
+ "emul, hwaccel, and auto. Default "
119
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
102
+ "is auto.");
120
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
103
+ object_property_set_default_str(object_class_property_find(oc, "riscv-aia"),
121
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
104
+ "auto");
122
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
105
+}
123
index XXXXXXX..XXXXXXX 100644
106
+
124
--- a/target/riscv/pmp.c
107
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
125
+++ b/target/riscv/pmp.c
108
+ uint64_t aia_irq_num, uint64_t aia_msi_num,
126
@@ -XXX,XX +XXX,XX @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
109
+ uint64_t aplic_base, uint64_t imsic_base,
127
return val;
110
+ uint64_t guest_num)
128
}
111
+{
129
112
+ int ret, i;
130
+/*
113
+ int aia_fd = -1;
131
+ * Handle a write to a mseccfg CSR
114
+ uint64_t default_aia_mode;
132
+ */
115
+ uint64_t socket_count = riscv_socket_count(machine);
133
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
116
+ uint64_t max_hart_per_socket = 0;
134
+{
117
+ uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr;
135
+ int i;
118
+ uint64_t socket_bits, hart_bits, guest_bits;
136
+
119
+
137
+ trace_mseccfg_csr_write(env->mhartid, val);
120
+ aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false);
138
+
121
+
139
+ /* RLB cannot be enabled if it's already 0 and if any regions are locked */
122
+ if (aia_fd < 0) {
140
+ if (!MSECCFG_RLB_ISSET(env)) {
123
+ error_report("Unable to create in-kernel irqchip");
141
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
124
+ exit(1);
142
+ if (pmp_is_locked(env, i)) {
125
+ }
143
+ val &= ~MSECCFG_RLB;
126
+
144
+ break;
127
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
128
+ KVM_DEV_RISCV_AIA_CONFIG_MODE,
129
+ &default_aia_mode, false, NULL);
130
+ if (ret < 0) {
131
+ error_report("KVM AIA: failed to get current KVM AIA mode");
132
+ exit(1);
133
+ }
134
+ qemu_log("KVM AIA: default mode is %s\n",
135
+ kvm_aia_mode_str(default_aia_mode));
136
+
137
+ if (default_aia_mode != aia_mode) {
138
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
139
+ KVM_DEV_RISCV_AIA_CONFIG_MODE,
140
+ &aia_mode, true, NULL);
141
+ if (ret < 0)
142
+ warn_report("KVM AIA: failed to set KVM AIA mode");
143
+ else
144
+ qemu_log("KVM AIA: set current mode to %s\n",
145
+ kvm_aia_mode_str(aia_mode));
146
+ }
147
+
148
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
149
+ KVM_DEV_RISCV_AIA_CONFIG_SRCS,
150
+ &aia_irq_num, true, NULL);
151
+ if (ret < 0) {
152
+ error_report("KVM AIA: failed to set number of input irq lines");
153
+ exit(1);
154
+ }
155
+
156
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
157
+ KVM_DEV_RISCV_AIA_CONFIG_IDS,
158
+ &aia_msi_num, true, NULL);
159
+ if (ret < 0) {
160
+ error_report("KVM AIA: failed to set number of msi");
161
+ exit(1);
162
+ }
163
+
164
+ socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1;
165
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
166
+ KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS,
167
+ &socket_bits, true, NULL);
168
+ if (ret < 0) {
169
+ error_report("KVM AIA: failed to set group_bits");
170
+ exit(1);
171
+ }
172
+
173
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
174
+ KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT,
175
+ &group_shift, true, NULL);
176
+ if (ret < 0) {
177
+ error_report("KVM AIA: failed to set group_shift");
178
+ exit(1);
179
+ }
180
+
181
+ guest_bits = guest_num == 0 ? 0 :
182
+ find_last_bit(&guest_num, BITS_PER_LONG) + 1;
183
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
184
+ KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS,
185
+ &guest_bits, true, NULL);
186
+ if (ret < 0) {
187
+ error_report("KVM AIA: failed to set guest_bits");
188
+ exit(1);
189
+ }
190
+
191
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
192
+ KVM_DEV_RISCV_AIA_ADDR_APLIC,
193
+ &aplic_base, true, NULL);
194
+ if (ret < 0) {
195
+ error_report("KVM AIA: failed to set the base address of APLIC");
196
+ exit(1);
197
+ }
198
+
199
+ for (socket = 0; socket < socket_count; socket++) {
200
+ socket_imsic_base = imsic_base + socket * (1U << group_shift);
201
+ hart_count = riscv_socket_hart_count(machine, socket);
202
+ base_hart = riscv_socket_first_hartid(machine, socket);
203
+
204
+ if (max_hart_per_socket < hart_count) {
205
+ max_hart_per_socket = hart_count;
206
+ }
207
+
208
+ for (i = 0; i < hart_count; i++) {
209
+ imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits);
210
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
211
+ KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart),
212
+ &imsic_addr, true, NULL);
213
+ if (ret < 0) {
214
+ error_report("KVM AIA: failed to set the IMSIC address for hart %d", i);
215
+ exit(1);
145
+ }
216
+ }
146
+ }
217
+ }
147
+ }
218
+ }
148
+
219
+
149
+ /* Sticky bits */
220
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
150
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
221
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
151
+
222
+ KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
152
+ env->mseccfg = val;
223
+ &hart_bits, true, NULL);
153
+}
224
+ if (ret < 0) {
154
+
225
+ error_report("KVM AIA: failed to set hart_bits");
155
+/*
226
+ exit(1);
156
+ * Handle a read from a mseccfg CSR
227
+ }
157
+ */
228
+
158
+target_ulong mseccfg_csr_read(CPURISCVState *env)
229
+ if (kvm_has_gsi_routing()) {
159
+{
230
+ for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) {
160
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
231
+ /* KVM AIA only has one APLIC instance */
161
+ return env->mseccfg;
232
+ kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx);
162
+}
233
+ }
163
+
234
+ kvm_gsi_routing_allowed = true;
164
/*
235
+ kvm_irqchip_commit_routes(kvm_state);
165
* Calculate the TLB size if the start address or the end address of
236
+ }
166
* PMP entry is presented in thie TLB page.
237
+
167
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
238
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL,
168
index XXXXXXX..XXXXXXX 100644
239
+ KVM_DEV_RISCV_AIA_CTRL_INIT,
169
--- a/target/riscv/trace-events
240
+ NULL, true, NULL);
170
+++ b/target/riscv/trace-events
241
+ if (ret < 0) {
171
@@ -XXX,XX +XXX,XX @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
242
+ error_report("KVM AIA: initialized fail");
172
pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
243
+ exit(1);
173
pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
244
+ }
174
pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
245
+
175
+
246
+ kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
176
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
247
}
177
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
178
--
248
--
179
2.31.1
249
2.41.0
180
181
diff view generated by jsdifflib
[PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro
[PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
3
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
4
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
5
mmio operations of APLIC when using KVM AIA and send wired interrupt
6
signal via KVM_IRQ_LINE API.
7
After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
8
when the IMSICs receive mmio write requests.
9
10
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
11
Reviewed-by: Jim Shu <jim.shu@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
14
Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
4
---
16
---
5
target/riscv/cpu_bits.h | 11 -----------
17
hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++-------------
6
target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
18
hw/intc/riscv_imsic.c | 25 +++++++++++++++----
7
target/riscv/csr.c | 19 +++++++++++++++----
19
2 files changed, 61 insertions(+), 20 deletions(-)
8
target/riscv/monitor.c | 22 +++++++++++++++++-----
9
4 files changed, 56 insertions(+), 28 deletions(-)
10
20
11
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
21
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
12
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu_bits.h
23
--- a/hw/intc/riscv_aplic.c
14
+++ b/target/riscv/cpu_bits.h
24
+++ b/hw/intc/riscv_aplic.c
15
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
16
#define SATP64_ASID 0x0FFFF00000000000ULL
26
#include "hw/irq.h"
17
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
27
#include "target/riscv/cpu.h"
18
28
#include "sysemu/sysemu.h"
19
-#if defined(TARGET_RISCV32)
29
+#include "sysemu/kvm.h"
20
-#define SATP_MODE SATP32_MODE
30
#include "migration/vmstate.h"
21
-#define SATP_ASID SATP32_ASID
31
22
-#define SATP_PPN SATP32_PPN
32
#define APLIC_MAX_IDC (1UL << 14)
23
-#endif
33
@@ -XXX,XX +XXX,XX @@
24
-#if defined(TARGET_RISCV64)
34
25
-#define SATP_MODE SATP64_MODE
35
#define APLIC_IDC_CLAIMI 0x1c
26
-#define SATP_ASID SATP64_ASID
36
27
-#define SATP_PPN SATP64_PPN
37
+/*
28
-#endif
38
+ * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
29
-
39
+ * APLIC Wired.
30
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
40
+ */
31
#define VM_1_09_MBARE 0
41
+static bool is_kvm_aia(bool msimode)
32
#define VM_1_09_MBB 1
42
+{
33
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
43
+ return kvm_irqchip_in_kernel() && msimode;
34
index XXXXXXX..XXXXXXX 100644
44
+}
35
--- a/target/riscv/cpu_helper.c
45
+
36
+++ b/target/riscv/cpu_helper.c
46
static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
37
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
47
uint32_t word)
38
48
{
39
if (first_stage == true) {
49
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
40
if (use_background) {
50
return topi;
41
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
51
}
42
- vm = get_field(env->vsatp, SATP_MODE);
52
43
+ if (riscv_cpu_is_32bit(env)) {
53
+static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
44
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
54
+{
45
+ vm = get_field(env->vsatp, SATP32_MODE);
55
+ kvm_set_irq(kvm_state, irq, !!level);
46
+ } else {
56
+}
47
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
57
+
48
+ vm = get_field(env->vsatp, SATP64_MODE);
58
static void riscv_aplic_request(void *opaque, int irq, int level)
49
+ }
59
{
50
} else {
60
bool update = false;
51
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
61
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
52
- vm = get_field(env->satp, SATP_MODE);
62
uint32_t i;
53
+ if (riscv_cpu_is_32bit(env)) {
63
RISCVAPLICState *aplic = RISCV_APLIC(dev);
54
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
64
55
+ vm = get_field(env->satp, SATP32_MODE);
65
- aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
56
+ } else {
66
- aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
57
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
67
- aplic->state = g_new0(uint32_t, aplic->num_irqs);
58
+ vm = get_field(env->satp, SATP64_MODE);
68
- aplic->target = g_new0(uint32_t, aplic->num_irqs);
69
- if (!aplic->msimode) {
70
- for (i = 0; i < aplic->num_irqs; i++) {
71
- aplic->target[i] = 1;
72
+ if (!is_kvm_aia(aplic->msimode)) {
73
+ aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
74
+ aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
75
+ aplic->state = g_new0(uint32_t, aplic->num_irqs);
76
+ aplic->target = g_new0(uint32_t, aplic->num_irqs);
77
+ if (!aplic->msimode) {
78
+ for (i = 0; i < aplic->num_irqs; i++) {
79
+ aplic->target[i] = 1;
59
+ }
80
+ }
60
}
81
}
61
widened = 0;
82
- }
62
} else {
83
- aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
63
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
84
- aplic->iforce = g_new0(uint32_t, aplic->num_harts);
64
{
85
- aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
65
CPUState *cs = env_cpu(env);
86
+ aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
66
int page_fault_exceptions, vm;
87
+ aplic->iforce = g_new0(uint32_t, aplic->num_harts);
67
+ uint64_t stap_mode;
88
+ aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
68
+
89
69
+ if (riscv_cpu_is_32bit(env)) {
90
- memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
70
+ stap_mode = SATP32_MODE;
91
- TYPE_RISCV_APLIC, aplic->aperture_size);
71
+ } else {
92
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
72
+ stap_mode = SATP64_MODE;
93
+ memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
94
+ aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
95
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
73
+ }
96
+ }
74
97
75
if (first_stage) {
98
/*
76
- vm = get_field(env->satp, SATP_MODE);
99
* Only root APLICs have hardware IRQ lines. All non-root APLICs
77
- } else if (riscv_cpu_is_32bit(env)) {
100
* have IRQ lines delegated by their parent APLIC.
78
- vm = get_field(env->hgatp, SATP32_MODE);
101
*/
79
+ vm = get_field(env->satp, stap_mode);
102
if (!aplic->parent) {
80
} else {
103
- qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
81
- vm = get_field(env->hgatp, SATP64_MODE);
104
+ if (is_kvm_aia(aplic->msimode)) {
82
+ vm = get_field(env->hgatp, stap_mode);
105
+ qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
83
}
106
+ } else {
84
+
107
+ qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
85
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
86
87
switch (access_type) {
88
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/riscv/csr.c
91
+++ b/target/riscv/csr.c
92
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
93
static RISCVException write_satp(CPURISCVState *env, int csrno,
94
target_ulong val)
95
{
96
+ int vm, mask, asid;
97
+
98
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
99
return RISCV_EXCP_NONE;
100
}
101
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
102
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
103
- {
104
+
105
+ if (riscv_cpu_is_32bit(env)) {
106
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
107
+ mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
108
+ asid = (val ^ env->satp) & SATP32_ASID;
109
+ } else {
110
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
111
+ mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
112
+ asid = (val ^ env->satp) & SATP64_ASID;
113
+ }
114
+
115
+ if (vm && mask) {
116
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
117
return RISCV_EXCP_ILLEGAL_INST;
118
} else {
119
- if ((val ^ env->satp) & SATP_ASID) {
120
+ if (asid) {
121
tlb_flush(env_cpu(env));
122
}
123
env->satp = val;
124
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/riscv/monitor.c
127
+++ b/target/riscv/monitor.c
128
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
129
target_ulong last_size;
130
int last_attr;
131
132
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
133
+ if (riscv_cpu_is_32bit(env)) {
134
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
135
+ vm = get_field(env->satp, SATP32_MODE);
136
+ } else {
137
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
138
+ vm = get_field(env->satp, SATP64_MODE);
139
+ }
140
141
- vm = get_field(env->satp, SATP_MODE);
142
switch (vm) {
143
case VM_1_10_SV32:
144
levels = 2;
145
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
146
return;
147
}
148
149
- if (!(env->satp & SATP_MODE)) {
150
- monitor_printf(mon, "No translation or protection\n");
151
- return;
152
+ if (riscv_cpu_is_32bit(env)) {
153
+ if (!(env->satp & SATP32_MODE)) {
154
+ monitor_printf(mon, "No translation or protection\n");
155
+ return;
156
+ }
157
+ } else {
158
+ if (!(env->satp & SATP64_MODE)) {
159
+ monitor_printf(mon, "No translation or protection\n");
160
+ return;
161
+ }
108
+ }
162
}
109
}
163
110
164
mem_info_svxx(mon, env);
111
/* Create output IRQ lines for non-MSI mode */
112
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
113
qdev_prop_set_bit(dev, "mmode", mmode);
114
115
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
116
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
117
+
118
+ if (!is_kvm_aia(msimode)) {
119
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
120
+ }
121
122
if (parent) {
123
riscv_aplic_add_child(parent, dev);
124
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/intc/riscv_imsic.c
127
+++ b/hw/intc/riscv_imsic.c
128
@@ -XXX,XX +XXX,XX @@
129
#include "target/riscv/cpu.h"
130
#include "target/riscv/cpu_bits.h"
131
#include "sysemu/sysemu.h"
132
+#include "sysemu/kvm.h"
133
#include "migration/vmstate.h"
134
135
#define IMSIC_MMIO_PAGE_LE 0x00
136
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
137
goto err;
138
}
139
140
+#if defined(CONFIG_KVM)
141
+ if (kvm_irqchip_in_kernel()) {
142
+ struct kvm_msi msi;
143
+
144
+ msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32);
145
+ msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32);
146
+ msi.data = le32_to_cpu(value);
147
+
148
+ kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
149
+
150
+ return;
151
+ }
152
+#endif
153
+
154
/* Writes only supported for MSI little-endian registers */
155
page = addr >> IMSIC_MMIO_PAGE_SHIFT;
156
if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
157
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
158
CPUState *cpu = cpu_by_arch_id(imsic->hartid);
159
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
160
161
- imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
162
- imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
163
- imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
164
- imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
165
+ if (!kvm_irqchip_in_kernel()) {
166
+ imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
167
+ imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
168
+ imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
169
+ imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
170
+ }
171
172
memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
173
imsic, TYPE_RISCV_IMSIC,
165
--
174
--
166
2.31.1
175
2.41.0
167
168
diff view generated by jsdifflib
[PULL 10/42] target/riscv: Use the RISCVException enum for CSR predicates
[PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
3
Select KVM AIA when the host kernel has in-kernel AIA chip support.
4
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
5
devices to KVM APLIC.
6
7
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
8
Reviewed-by: Jim Shu <jim.shu@sifive.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
11
Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
5
---
13
---
6
target/riscv/cpu.h | 3 +-
14
hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++----------------
7
target/riscv/csr.c | 80 +++++++++++++++++++++++++---------------------
15
1 file changed, 63 insertions(+), 31 deletions(-)
8
2 files changed, 46 insertions(+), 37 deletions(-)
9
16
10
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.h
19
--- a/hw/riscv/virt.c
13
+++ b/target/riscv/cpu.h
20
+++ b/hw/riscv/virt.c
14
@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
21
@@ -XXX,XX +XXX,XX @@
15
return val;
22
#include "hw/riscv/virt.h"
16
}
23
#include "hw/riscv/boot.h"
17
24
#include "hw/riscv/numa.h"
18
-typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
25
+#include "kvm_riscv.h"
19
+typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
26
#include "hw/intc/riscv_aclint.h"
20
+ int csrno);
27
#include "hw/intc/riscv_aplic.h"
21
typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
28
#include "hw/intc/riscv_imsic.h"
22
target_ulong *ret_value);
29
@@ -XXX,XX +XXX,XX @@
23
typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
30
#error "Can't accommodate all IMSIC groups in address space"
24
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
31
#endif
25
index XXXXXXX..XXXXXXX 100644
32
26
--- a/target/riscv/csr.c
33
+/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
27
+++ b/target/riscv/csr.c
34
+static bool virt_use_kvm_aia(RISCVVirtState *s)
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
35
+{
29
}
36
+ return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
30
37
+}
31
/* Predicates */
38
+
32
-static int fs(CPURISCVState *env, int csrno)
39
static const MemMapEntry virt_memmap[] = {
33
+static RISCVException fs(CPURISCVState *env, int csrno)
40
[VIRT_DEBUG] = { 0x0, 0x100 },
41
[VIRT_MROM] = { 0x1000, 0xf000 },
42
@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
43
uint32_t *intc_phandles,
44
uint32_t aplic_phandle,
45
uint32_t aplic_child_phandle,
46
- bool m_mode)
47
+ bool m_mode, int num_harts)
34
{
48
{
35
#if !defined(CONFIG_USER_ONLY)
49
int cpu;
36
/* loose check condition for fcsr in vector extension */
50
char *aplic_name;
37
if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
51
uint32_t *aplic_cells;
38
- return 0;
52
MachineState *ms = MACHINE(s);
39
+ return RISCV_EXCP_NONE;
53
54
- aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
55
+ aplic_cells = g_new0(uint32_t, num_harts * 2);
56
57
- for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
58
+ for (cpu = 0; cpu < num_harts; cpu++) {
59
aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
60
aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
40
}
61
}
41
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
62
@@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
42
- return -RISCV_EXCP_ILLEGAL_INST;
63
43
+ return RISCV_EXCP_ILLEGAL_INST;
64
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
65
qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
66
- aplic_cells,
67
- s->soc[socket].num_harts * sizeof(uint32_t) * 2);
68
+ aplic_cells, num_harts * sizeof(uint32_t) * 2);
69
} else {
70
qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
44
}
71
}
45
#endif
72
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
46
- return 0;
73
uint32_t msi_s_phandle,
47
+ return RISCV_EXCP_NONE;
74
uint32_t *phandle,
48
}
75
uint32_t *intc_phandles,
49
76
- uint32_t *aplic_phandles)
50
-static int vs(CPURISCVState *env, int csrno)
77
+ uint32_t *aplic_phandles,
51
+static RISCVException vs(CPURISCVState *env, int csrno)
78
+ int num_harts)
52
{
79
{
53
if (env->misa & RVV) {
80
char *aplic_name;
54
- return 0;
81
unsigned long aplic_addr;
55
+ return RISCV_EXCP_NONE;
82
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
83
create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
84
msi_m_phandle, intc_phandles,
85
aplic_m_phandle, aplic_s_phandle,
86
- true);
87
+ true, num_harts);
56
}
88
}
57
- return -RISCV_EXCP_ILLEGAL_INST;
89
58
+ return RISCV_EXCP_ILLEGAL_INST;
90
/* S-level APLIC node */
59
}
91
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
60
92
create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
61
-static int ctr(CPURISCVState *env, int csrno)
93
msi_s_phandle, intc_phandles,
62
+static RISCVException ctr(CPURISCVState *env, int csrno)
94
aplic_s_phandle, 0,
63
{
95
- false);
64
#if !defined(CONFIG_USER_ONLY)
96
+ false, num_harts);
65
CPUState *cs = env_cpu(env);
97
66
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
98
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
67
99
68
if (!cpu->cfg.ext_counters) {
100
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
69
/* The Counters extensions is not enabled */
101
*msi_pcie_phandle = msi_s_phandle;
70
- return -RISCV_EXCP_ILLEGAL_INST;
71
+ return RISCV_EXCP_ILLEGAL_INST;
72
}
102
}
73
103
74
if (riscv_cpu_virt_enabled(env)) {
104
- phandle_pos = ms->smp.cpus;
75
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
105
- for (socket = (socket_count - 1); socket >= 0; socket--) {
76
case CSR_CYCLE:
106
- phandle_pos -= s->soc[socket].num_harts;
77
if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
107
-
78
get_field(env->mcounteren, HCOUNTEREN_CY)) {
108
- if (s->aia_type == VIRT_AIA_TYPE_NONE) {
79
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109
- create_fdt_socket_plic(s, memmap, socket, phandle,
80
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
110
- &intc_phandles[phandle_pos], xplic_phandles);
81
}
111
- } else {
82
break;
112
- create_fdt_socket_aplic(s, memmap, socket,
83
case CSR_TIME:
113
- msi_m_phandle, msi_s_phandle, phandle,
84
if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
114
- &intc_phandles[phandle_pos], xplic_phandles);
85
get_field(env->mcounteren, HCOUNTEREN_TM)) {
115
+ /* KVM AIA only has one APLIC instance */
86
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
116
+ if (virt_use_kvm_aia(s)) {
87
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
117
+ create_fdt_socket_aplic(s, memmap, 0,
88
}
118
+ msi_m_phandle, msi_s_phandle, phandle,
89
break;
119
+ &intc_phandles[0], xplic_phandles,
90
case CSR_INSTRET:
120
+ ms->smp.cpus);
91
if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
121
+ } else {
92
get_field(env->mcounteren, HCOUNTEREN_IR)) {
122
+ phandle_pos = ms->smp.cpus;
93
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
123
+ for (socket = (socket_count - 1); socket >= 0; socket--) {
94
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
124
+ phandle_pos -= s->soc[socket].num_harts;
95
}
125
+
96
break;
126
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
97
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
127
+ create_fdt_socket_plic(s, memmap, socket, phandle,
98
if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
128
+ &intc_phandles[phandle_pos],
99
get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
129
+ xplic_phandles);
100
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
130
+ } else {
101
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
131
+ create_fdt_socket_aplic(s, memmap, socket,
102
}
132
+ msi_m_phandle, msi_s_phandle, phandle,
103
break;
133
+ &intc_phandles[phandle_pos],
104
}
134
+ xplic_phandles,
105
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
135
+ s->soc[socket].num_harts);
106
case CSR_CYCLEH:
136
+ }
107
if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
108
get_field(env->mcounteren, HCOUNTEREN_CY)) {
109
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
110
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
111
}
112
break;
113
case CSR_TIMEH:
114
if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
115
get_field(env->mcounteren, HCOUNTEREN_TM)) {
116
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
117
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
118
}
119
break;
120
case CSR_INSTRETH:
121
if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
122
get_field(env->mcounteren, HCOUNTEREN_IR)) {
123
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
124
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
125
}
126
break;
127
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
128
if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
129
get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
130
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
131
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
132
}
133
break;
134
}
135
}
137
}
136
}
138
}
137
#endif
139
138
- return 0;
140
g_free(intc_phandles);
139
+ return RISCV_EXCP_NONE;
141
140
}
142
- for (socket = 0; socket < socket_count; socket++) {
141
143
- if (socket == 0) {
142
-static int ctr32(CPURISCVState *env, int csrno)
144
- *irq_mmio_phandle = xplic_phandles[socket];
143
+static RISCVException ctr32(CPURISCVState *env, int csrno)
145
- *irq_virtio_phandle = xplic_phandles[socket];
144
{
146
- *irq_pcie_phandle = xplic_phandles[socket];
145
if (!riscv_cpu_is_32bit(env)) {
147
- }
146
- return -RISCV_EXCP_ILLEGAL_INST;
148
- if (socket == 1) {
147
+ return RISCV_EXCP_ILLEGAL_INST;
149
- *irq_virtio_phandle = xplic_phandles[socket];
150
- *irq_pcie_phandle = xplic_phandles[socket];
151
- }
152
- if (socket == 2) {
153
- *irq_pcie_phandle = xplic_phandles[socket];
154
+ if (virt_use_kvm_aia(s)) {
155
+ *irq_mmio_phandle = xplic_phandles[0];
156
+ *irq_virtio_phandle = xplic_phandles[0];
157
+ *irq_pcie_phandle = xplic_phandles[0];
158
+ } else {
159
+ for (socket = 0; socket < socket_count; socket++) {
160
+ if (socket == 0) {
161
+ *irq_mmio_phandle = xplic_phandles[socket];
162
+ *irq_virtio_phandle = xplic_phandles[socket];
163
+ *irq_pcie_phandle = xplic_phandles[socket];
164
+ }
165
+ if (socket == 1) {
166
+ *irq_virtio_phandle = xplic_phandles[socket];
167
+ *irq_pcie_phandle = xplic_phandles[socket];
168
+ }
169
+ if (socket == 2) {
170
+ *irq_pcie_phandle = xplic_phandles[socket];
171
+ }
172
}
148
}
173
}
149
174
150
return ctr(env, csrno);
175
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
151
}
176
}
152
153
#if !defined(CONFIG_USER_ONLY)
154
-static int any(CPURISCVState *env, int csrno)
155
+static RISCVException any(CPURISCVState *env, int csrno)
156
{
157
- return 0;
158
+ return RISCV_EXCP_NONE;
159
}
160
161
-static int any32(CPURISCVState *env, int csrno)
162
+static RISCVException any32(CPURISCVState *env, int csrno)
163
{
164
if (!riscv_cpu_is_32bit(env)) {
165
- return -RISCV_EXCP_ILLEGAL_INST;
166
+ return RISCV_EXCP_ILLEGAL_INST;
167
}
177
}
168
178
169
return any(env, csrno);
179
+ if (virt_use_kvm_aia(s)) {
170
180
+ kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
171
}
181
+ VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
172
182
+ memmap[VIRT_APLIC_S].base,
173
-static int smode(CPURISCVState *env, int csrno)
183
+ memmap[VIRT_IMSIC_S].base,
174
+static RISCVException smode(CPURISCVState *env, int csrno)
184
+ s->aia_guests);
175
{
176
- return -!riscv_has_ext(env, RVS);
177
+ if (riscv_has_ext(env, RVS)) {
178
+ return RISCV_EXCP_NONE;
179
+ }
185
+ }
180
+
186
+
181
+ return RISCV_EXCP_ILLEGAL_INST;
187
if (riscv_is_32bit(&s->soc[0])) {
182
}
188
#if HOST_LONG_BITS == 64
183
189
/* limit RAM size in a 32-bit system */
184
-static int hmode(CPURISCVState *env, int csrno)
185
+static RISCVException hmode(CPURISCVState *env, int csrno)
186
{
187
if (riscv_has_ext(env, RVS) &&
188
riscv_has_ext(env, RVH)) {
189
/* Hypervisor extension is supported */
190
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
191
env->priv == PRV_M) {
192
- return 0;
193
+ return RISCV_EXCP_NONE;
194
} else {
195
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
196
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
197
}
198
}
199
200
- return -RISCV_EXCP_ILLEGAL_INST;
201
+ return RISCV_EXCP_ILLEGAL_INST;
202
}
203
204
-static int hmode32(CPURISCVState *env, int csrno)
205
+static RISCVException hmode32(CPURISCVState *env, int csrno)
206
{
207
if (!riscv_cpu_is_32bit(env)) {
208
- return 0;
209
+ return RISCV_EXCP_NONE;
210
}
211
212
return hmode(env, csrno);
213
214
}
215
216
-static int pmp(CPURISCVState *env, int csrno)
217
+static RISCVException pmp(CPURISCVState *env, int csrno)
218
{
219
- return -!riscv_feature(env, RISCV_FEATURE_PMP);
220
+ if (riscv_feature(env, RISCV_FEATURE_PMP)) {
221
+ return RISCV_EXCP_NONE;
222
+ }
223
+
224
+ return RISCV_EXCP_ILLEGAL_INST;
225
}
226
#endif
227
228
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
229
return -RISCV_EXCP_ILLEGAL_INST;
230
}
231
ret = csr_ops[csrno].predicate(env, csrno);
232
- if (ret < 0) {
233
- return ret;
234
+ if (ret != RISCV_EXCP_NONE) {
235
+ return -ret;
236
}
237
238
/* execute combined read/write operation if it exists */
239
--
190
--
240
2.31.1
191
2.41.0
241
242
diff view generated by jsdifflib
[PULL 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
[PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path
1
From: Bin Meng <bmeng.cn@gmail.com>
1
From: Conor Dooley <conor.dooley@microchip.com>
2
2
3
This was accidentally dropped before. Add it back.
3
On a dtb dumped from the virt machine, dt-validate complains:
4
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
5
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
6
That's pretty cryptic, but running the dtb back through dtc produces
7
something a lot more reasonable:
8
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
4
9
5
Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
10
Moving the riscv,pmu node out of the soc bus solves the problem.
6
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
11
7
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
12
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
15
Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
17
---
13
hw/riscv/sifive_e.c | 2 +-
18
hw/riscv/virt.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
19
1 file changed, 1 insertion(+), 1 deletion(-)
15
20
16
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
21
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/sifive_e.c
23
--- a/hw/riscv/virt.c
19
+++ b/hw/riscv/sifive_e.c
24
+++ b/hw/riscv/virt.c
20
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s)
21
#include "sysemu/sysemu.h"
26
MachineState *ms = MACHINE(s);
22
#include "exec/address-spaces.h"
27
RISCVCPU hart = s->soc[0].harts[0];
23
28
24
-static MemMapEntry sifive_e_memmap[] = {
29
- pmu_name = g_strdup_printf("/soc/pmu");
25
+static const MemMapEntry sifive_e_memmap[] = {
30
+ pmu_name = g_strdup_printf("/pmu");
26
[SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
31
qemu_fdt_add_subnode(ms->fdt, pmu_name);
27
[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
32
qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
28
[SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
33
riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
29
--
34
--
30
2.31.1
35
2.41.0
31
32
diff view generated by jsdifflib
[PULL 01/42] target/riscv: Remove privilege v1.9 specific CSR related code
[PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
3
The Svadu specification updated the name of the *envcfg bit from
4
remaining v1.9 specific references from the implementation.
4
HADE to ADUE.
5
5
6
Signed-off-by: Atish Patra <atish.patra@wdc.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
[Changes by AF:
9
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
10
- Rebase on latest patches
11
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
11
---
15
target/riscv/cpu.h | 4 +---
12
target/riscv/cpu_bits.h | 8 ++++----
16
target/riscv/cpu_bits.h | 23 ---------------------
13
target/riscv/cpu.c | 4 ++--
17
target/riscv/cpu.c | 2 +-
14
target/riscv/cpu_helper.c | 6 +++---
18
target/riscv/cpu_helper.c | 12 +++++------
15
target/riscv/csr.c | 12 ++++++------
19
target/riscv/csr.c | 42 ++++++++++-----------------------------
16
4 files changed, 15 insertions(+), 15 deletions(-)
20
target/riscv/machine.c | 8 +++-----
21
target/riscv/translate.c | 4 ++--
22
7 files changed, 23 insertions(+), 72 deletions(-)
23
17
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
29
target_ulong mie;
30
target_ulong mideleg;
31
32
- target_ulong sptbr; /* until: priv-1.9.1 */
33
target_ulong satp; /* since: priv-1.10.0 */
34
- target_ulong sbadaddr;
35
- target_ulong mbadaddr;
36
+ target_ulong stval;
37
target_ulong medeleg;
38
39
target_ulong stvec;
40
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
18
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
41
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
42
--- a/target/riscv/cpu_bits.h
20
--- a/target/riscv/cpu_bits.h
43
+++ b/target/riscv/cpu_bits.h
21
+++ b/target/riscv/cpu_bits.h
44
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
45
/* 32-bit only */
23
#define MENVCFG_CBIE (3UL << 4)
46
#define CSR_MSTATUSH 0x310
24
#define MENVCFG_CBCFE BIT(6)
47
25
#define MENVCFG_CBZE BIT(7)
48
-/* Legacy Counter Setup (priv v1.9.1) */
26
-#define MENVCFG_HADE (1ULL << 61)
49
-/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
27
+#define MENVCFG_ADUE (1ULL << 61)
50
-#define CSR_MUCOUNTEREN 0x320
28
#define MENVCFG_PBMTE (1ULL << 62)
51
-#define CSR_MSCOUNTEREN 0x321
29
#define MENVCFG_STCE (1ULL << 63)
52
-#define CSR_MHCOUNTEREN 0x322
30
53
-
31
/* For RV32 */
54
/* Machine Trap Handling */
32
-#define MENVCFGH_HADE BIT(29)
55
#define CSR_MSCRATCH 0x340
33
+#define MENVCFGH_ADUE BIT(29)
56
#define CSR_MEPC 0x341
34
#define MENVCFGH_PBMTE BIT(30)
57
@@ -XXX,XX +XXX,XX @@
35
#define MENVCFGH_STCE BIT(31)
58
#define CSR_MTVAL 0x343
36
59
#define CSR_MIP 0x344
37
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
60
38
#define HENVCFG_CBIE MENVCFG_CBIE
61
-/* Legacy Machine Trap Handling (priv v1.9.1) */
39
#define HENVCFG_CBCFE MENVCFG_CBCFE
62
-#define CSR_MBADADDR 0x343
40
#define HENVCFG_CBZE MENVCFG_CBZE
63
-
41
-#define HENVCFG_HADE MENVCFG_HADE
64
/* Supervisor Trap Setup */
42
+#define HENVCFG_ADUE MENVCFG_ADUE
65
#define CSR_SSTATUS 0x100
43
#define HENVCFG_PBMTE MENVCFG_PBMTE
66
#define CSR_SEDELEG 0x102
44
#define HENVCFG_STCE MENVCFG_STCE
67
@@ -XXX,XX +XXX,XX @@
45
68
#define CSR_STVAL 0x143
46
/* For RV32 */
69
#define CSR_SIP 0x144
47
-#define HENVCFGH_HADE MENVCFGH_HADE
70
48
+#define HENVCFGH_ADUE MENVCFGH_ADUE
71
-/* Legacy Supervisor Trap Handling (priv v1.9.1) */
49
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
72
-#define CSR_SBADADDR 0x143
50
#define HENVCFGH_STCE MENVCFGH_STCE
73
-
74
/* Supervisor Protection and Translation */
75
#define CSR_SPTBR 0x180
76
#define CSR_SATP 0x180
77
@@ -XXX,XX +XXX,XX @@
78
#define CSR_MHPMCOUNTER30H 0xb9e
79
#define CSR_MHPMCOUNTER31H 0xb9f
80
81
-/* Legacy Machine Protection and Translation (priv v1.9.1) */
82
-#define CSR_MBASE 0x380
83
-#define CSR_MBOUND 0x381
84
-#define CSR_MIBASE 0x382
85
-#define CSR_MIBOUND 0x383
86
-#define CSR_MDBASE 0x384
87
-#define CSR_MDBOUND 0x385
88
-
89
/* mstatus CSR bits */
90
#define MSTATUS_UIE 0x00000001
91
#define MSTATUS_SIE 0x00000002
92
@@ -XXX,XX +XXX,XX @@
93
#define MSTATUS_FS 0x00006000
94
#define MSTATUS_XS 0x00018000
95
#define MSTATUS_MPRV 0x00020000
96
-#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
97
#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
98
#define MSTATUS_MXR 0x00080000
99
-#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
100
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
101
#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
102
#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
103
@@ -XXX,XX +XXX,XX @@
104
#define SSTATUS_SPP 0x00000100
105
#define SSTATUS_FS 0x00006000
106
#define SSTATUS_XS 0x00018000
107
-#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
108
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
109
#define SSTATUS_MXR 0x00080000
110
51
111
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
52
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
112
index XXXXXXX..XXXXXXX 100644
53
index XXXXXXX..XXXXXXX 100644
113
--- a/target/riscv/cpu.c
54
--- a/target/riscv/cpu.c
114
+++ b/target/riscv/cpu.c
55
+++ b/target/riscv/cpu.c
115
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
56
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
116
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
57
env->two_stage_lookup = false;
117
}
58
118
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
59
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
119
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
60
- (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
120
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
61
+ (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
121
if (riscv_has_ext(env, RVH)) {
62
env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
122
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
63
- (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
123
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
64
+ (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
65
66
/* Initialized default priorities of local interrupts. */
67
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
124
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
68
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
125
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
126
--- a/target/riscv/cpu_helper.c
70
--- a/target/riscv/cpu_helper.c
127
+++ b/target/riscv/cpu_helper.c
71
+++ b/target/riscv/cpu_helper.c
128
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
72
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
129
env->vscause = env->scause;
73
}
130
env->scause = env->scause_hs;
74
131
75
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
132
- env->vstval = env->sbadaddr;
76
- bool hade = env->menvcfg & MENVCFG_HADE;
133
- env->sbadaddr = env->stval_hs;
77
+ bool adue = env->menvcfg & MENVCFG_ADUE;
134
+ env->vstval = env->stval;
78
135
+ env->stval = env->stval_hs;
79
if (first_stage && two_stage && env->virt_enabled) {
136
80
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
137
env->vsatp = env->satp;
81
- hade = hade && (env->henvcfg & HENVCFG_HADE);
138
env->satp = env->satp_hs;
82
+ adue = adue && (env->henvcfg & HENVCFG_ADUE);
139
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
83
}
140
env->scause_hs = env->scause;
84
141
env->scause = env->vscause;
85
int ptshift = (levels - 1) * ptidxbits;
142
86
@@ -XXX,XX +XXX,XX @@ restart:
143
- env->stval_hs = env->sbadaddr;
87
144
- env->sbadaddr = env->vstval;
88
/* Page table updates need to be atomic with MTTCG enabled */
145
+ env->stval_hs = env->stval;
89
if (updated_pte != pte && !is_debug) {
146
+ env->stval = env->vstval;
90
- if (!hade) {
147
91
+ if (!adue) {
148
env->satp_hs = env->satp;
92
return TRANSLATE_FAIL;
149
env->satp = env->vsatp;
93
}
150
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
94
151
env->mstatus = s;
152
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
153
env->sepc = env->pc;
154
- env->sbadaddr = tval;
155
+ env->stval = tval;
156
env->htval = htval;
157
env->pc = (env->stvec >> 2 << 2) +
158
((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
159
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
160
env->mstatus = s;
161
env->mcause = cause | ~(((target_ulong)-1) >> async);
162
env->mepc = env->pc;
163
- env->mbadaddr = tval;
164
+ env->mtval = tval;
165
env->mtval2 = mtval2;
166
env->pc = (env->mtvec >> 2 << 2) +
167
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
168
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
95
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
169
index XXXXXXX..XXXXXXX 100644
96
index XXXXXXX..XXXXXXX 100644
170
--- a/target/riscv/csr.c
97
--- a/target/riscv/csr.c
171
+++ b/target/riscv/csr.c
98
+++ b/target/riscv/csr.c
172
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
99
@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
173
return 0;
100
if (riscv_cpu_mxl(env) == MXL_RV64) {
101
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
102
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
103
- (cfg->ext_svadu ? MENVCFG_HADE : 0);
104
+ (cfg->ext_svadu ? MENVCFG_ADUE : 0);
105
}
106
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
107
108
@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
109
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
110
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
111
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
112
- (cfg->ext_svadu ? MENVCFG_HADE : 0);
113
+ (cfg->ext_svadu ? MENVCFG_ADUE : 0);
114
uint64_t valh = (uint64_t)val << 32;
115
116
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
117
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
118
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
119
* henvcfg.hade is read_only 0 when menvcfg.hade = 0
120
*/
121
- *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
122
+ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
123
env->menvcfg);
124
return RISCV_EXCP_NONE;
174
}
125
}
175
126
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
176
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
127
}
177
-static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
128
178
-{
129
if (riscv_cpu_mxl(env) == MXL_RV64) {
179
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
130
- mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
180
- return -RISCV_EXCP_ILLEGAL_INST;
131
+ mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
181
- }
132
}
182
- *val = env->mcounteren;
133
183
- return 0;
134
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
184
-}
135
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
185
-
136
return ret;
186
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
137
}
187
-static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
138
188
-{
139
- *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
189
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
140
+ *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
190
- return -RISCV_EXCP_ILLEGAL_INST;
141
env->menvcfg)) >> 32;
191
- }
142
return RISCV_EXCP_NONE;
192
- env->mcounteren = val;
143
}
193
- return 0;
144
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
194
-}
145
target_ulong val)
195
-
196
/* Machine Trap Handling */
197
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
198
{
146
{
199
@@ -XXX,XX +XXX,XX @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
147
uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
200
return 0;
148
- HENVCFG_HADE);
201
}
149
+ HENVCFG_ADUE);
202
150
uint64_t valh = (uint64_t)val << 32;
203
-static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
151
RISCVException ret;
204
+static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
152
205
{
206
- *val = env->mbadaddr;
207
+ *val = env->mtval;
208
return 0;
209
}
210
211
-static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
212
+static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
213
{
214
- env->mbadaddr = val;
215
+ env->mtval = val;
216
return 0;
217
}
218
219
@@ -XXX,XX +XXX,XX @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
220
return 0;
221
}
222
223
-static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
224
+static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
225
{
226
- *val = env->sbadaddr;
227
+ *val = env->stval;
228
return 0;
229
}
230
231
-static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
232
+static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
233
{
234
- env->sbadaddr = val;
235
+ env->stval = val;
236
return 0;
237
}
238
239
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
240
241
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
242
243
- [CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
244
-
245
/* Machine Trap Handling */
246
[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
247
[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
248
[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
249
- [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
250
+ [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
251
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
252
253
/* Supervisor Trap Setup */
254
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
255
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
256
[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
257
[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
258
- [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
259
+ [CSR_STVAL] = { "stval", smode, read_stval, write_stval },
260
[CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
261
262
/* Supervisor Protection and Translation */
263
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
264
index XXXXXXX..XXXXXXX 100644
265
--- a/target/riscv/machine.c
266
+++ b/target/riscv/machine.c
267
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
268
269
const VMStateDescription vmstate_riscv_cpu = {
270
.name = "cpu",
271
- .version_id = 1,
272
- .minimum_version_id = 1,
273
+ .version_id = 2,
274
+ .minimum_version_id = 2,
275
.fields = (VMStateField[]) {
276
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
277
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
278
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
279
VMSTATE_UINT32(env.miclaim, RISCVCPU),
280
VMSTATE_UINTTL(env.mie, RISCVCPU),
281
VMSTATE_UINTTL(env.mideleg, RISCVCPU),
282
- VMSTATE_UINTTL(env.sptbr, RISCVCPU),
283
VMSTATE_UINTTL(env.satp, RISCVCPU),
284
- VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
285
- VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
286
+ VMSTATE_UINTTL(env.stval, RISCVCPU),
287
VMSTATE_UINTTL(env.medeleg, RISCVCPU),
288
VMSTATE_UINTTL(env.stvec, RISCVCPU),
289
VMSTATE_UINTTL(env.sepc, RISCVCPU),
290
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
291
index XXXXXXX..XXXXXXX 100644
292
--- a/target/riscv/translate.c
293
+++ b/target/riscv/translate.c
294
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
295
ctx->base.is_jmp = DISAS_NORETURN;
296
}
297
298
-static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
299
+static void generate_exception_mtval(DisasContext *ctx, int excp)
300
{
301
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
302
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
303
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
304
305
static void gen_exception_inst_addr_mis(DisasContext *ctx)
306
{
307
- generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
308
+ generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
309
}
310
311
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
312
--
153
--
313
2.31.1
154
2.41.0
314
315
diff view generated by jsdifflib
[PULL 32/42] target/riscv: fix a typo with interrupt names
[PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
1
From: Emmanuel Blot <emmanuel.blot@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Interrupt names have been swapped in 205377f8 and do not follow
3
In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
4
IRQ_*_EXT definition order.
4
longer to boot than the 'rv64' KVM CPU.
5
5
6
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
6
The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
when satp_mode.supported = 0, i.e. when cpu_init() does not set
8
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
8
satp_mode_max_supported(). satp_mode_max_from_map(map) does:
9
10
31 - __builtin_clz(map)
11
12
This means that, if satp_mode.supported = 0, satp_mode_supported_max
13
wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly
14
set it to UINT_MAX (4294967295). After that, if the user didn't set a
15
satp_mode, set_satp_mode_default_map(cpu) will make
16
17
cfg.satp_mode.map = cfg.satp_mode.supported
18
19
So satp_mode.map = 0. And then satp_mode_map_max will be set to
20
satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The
21
guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us
22
here since both are UINT_MAX.
23
24
And finally we have 2 loops:
25
26
for (int i = satp_mode_map_max - 1; i >= 0; --i) {
27
28
Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the
29
extra delay when booting the 'host' CPU is coming from.
30
31
Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0
32
in a different manner. We're doing the same here. If supported == 0,
33
interpret as 'the CPU wants the OS to handle satp mode alone' and skip
34
satp_mode_finalize().
35
36
We'll also put a guard in satp_mode_max_from_map() to assert out if map
37
is 0 since the function is not ready to deal with it.
38
39
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
40
Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode")
41
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
42
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
43
Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
44
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
45
---
11
target/riscv/cpu.c | 2 +-
46
target/riscv/cpu.c | 23 ++++++++++++++++++++---
12
1 file changed, 1 insertion(+), 1 deletion(-)
47
1 file changed, 20 insertions(+), 3 deletions(-)
13
48
14
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
49
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
15
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu.c
51
--- a/target/riscv/cpu.c
17
+++ b/target/riscv/cpu.c
52
+++ b/target/riscv/cpu.c
18
@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
53
@@ -XXX,XX +XXX,XX @@ static uint8_t satp_mode_from_str(const char *satp_mode_str)
19
"vs_timer",
54
20
"m_timer",
55
uint8_t satp_mode_max_from_map(uint32_t map)
21
"u_external",
56
{
22
+ "s_external",
57
+ /*
23
"vs_external",
58
+ * 'map = 0' will make us return (31 - 32), which C will
24
- "h_external",
59
+ * happily overflow to UINT_MAX. There's no good result to
25
"m_external",
60
+ * return if 'map = 0' (e.g. returning 0 will be ambiguous
26
"reserved",
61
+ * with the result for 'map = 1').
27
"reserved",
62
+ *
63
+ * Assert out if map = 0. Callers will have to deal with
64
+ * it outside of this function.
65
+ */
66
+ g_assert(map > 0);
67
+
68
/* map here has at least one bit set, so no problem with clz */
69
return 31 - __builtin_clz(map);
70
}
71
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
72
static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
73
{
74
bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
75
- uint8_t satp_mode_map_max;
76
- uint8_t satp_mode_supported_max =
77
- satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
78
+ uint8_t satp_mode_map_max, satp_mode_supported_max;
79
+
80
+ /* The CPU wants the OS to decide which satp mode to use */
81
+ if (cpu->cfg.satp_mode.supported == 0) {
82
+ return;
83
+ }
84
+
85
+ satp_mode_supported_max =
86
+ satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
87
88
if (cpu->cfg.satp_mode.map == 0) {
89
if (cpu->cfg.satp_mode.init == 0) {
28
--
90
--
29
2.31.1
91
2.41.0
30
31
diff view generated by jsdifflib
[PULL 03/42] target/riscv: Align the data type of reset vector address
[PULL v2 37/45] riscv: zicond: make non-experimental
1
From: Dylan Jhong <dylan@andestech.com>
1
From: Vineet Gupta <vineetg@rivosinc.com>
2
2
3
Use target_ulong to instead of uint64_t on reset vector address
3
zicond is now codegen supported in both llvm and gcc.
4
to adapt on both 32/64 machine.
5
4
6
Signed-off-by: Dylan Jhong <dylan@andestech.com>
5
This change allows seamless enabling/testing of zicond in downstream
7
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
6
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
to create a cmdline for qemu but fails short of enabling it because of
8
the "x-" prefix.
9
10
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
11
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210329034801.22667-1-dylan@andestech.com
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
14
---
13
target/riscv/cpu.c | 2 +-
15
target/riscv/cpu.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
16
1 file changed, 1 insertion(+), 1 deletion(-)
15
17
16
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.c
20
--- a/target/riscv/cpu.c
19
+++ b/target/riscv/cpu.c
21
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void set_feature(CPURISCVState *env, int feature)
22
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
21
env->features |= (1ULL << feature);
23
DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
22
}
24
DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
23
25
DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
24
-static void set_resetvec(CPURISCVState *env, int resetvec)
26
+ DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
25
+static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
27
26
{
28
/* Vendor-specific custom extensions */
27
#ifndef CONFIG_USER_ONLY
29
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
28
env->resetvec = resetvec;
30
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
31
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
32
33
/* These are experimental so mark with 'x-' */
34
- DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
35
36
/* ePMP 0.9.3 */
37
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
29
--
38
--
30
2.31.1
39
2.41.0
31
32
diff view generated by jsdifflib
[PULL 17/42] riscv: don't look at SUM when accessing memory from a debugger context
[PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build
1
From: Jade Fink <qemu@jade.fyi>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Previously the qemu monitor and gdbstub looked at SUM and refused to
3
A build with --enable-debug and without KVM will fail as follows:
4
perform accesses to user memory if it is off, which was an impediment to
5
debugging.
6
4
7
Signed-off-by: Jade Fink <qemu@jade.fyi>
5
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `virt_machine_init':
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia_create'
9
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
7
8
This happens because the code block with "if virt_use_kvm_aia(s)" isn't
9
being ignored by the debug build, resulting in an undefined reference to
10
a KVM only function.
11
12
Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will
13
make the compiler crop the kvm_riscv_aia_create() call entirely from a
14
non-KVM build. Note that adding the 'kvm_enabled()' conditional inside
15
virt_use_kvm_aia() won't fix the build because this function would need
16
to be inlined multiple times to make the compiler zero out the entire
17
block.
18
19
While we're at it, use kvm_enabled() in all instances where
20
virt_use_kvm_aia() is checked to allow the compiler to elide these other
21
kvm-only instances as well.
22
23
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
24
Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine")
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
27
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
31
---
12
target/riscv/cpu_helper.c | 20 ++++++++++++--------
32
hw/riscv/virt.c | 6 +++---
13
1 file changed, 12 insertions(+), 8 deletions(-)
33
1 file changed, 3 insertions(+), 3 deletions(-)
14
34
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
35
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
16
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
37
--- a/hw/riscv/virt.c
18
+++ b/target/riscv/cpu_helper.c
38
+++ b/hw/riscv/virt.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
39
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
20
* @first_stage: Are we in first stage translation?
21
* Second stage is used for hypervisor guest translation
22
* @two_stage: Are we going to perform two stage translation
23
+ * @is_debug: Is this access from a debugger or the monitor?
24
*/
25
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
26
int *prot, target_ulong addr,
27
target_ulong *fault_pte_addr,
28
int access_type, int mmu_idx,
29
- bool first_stage, bool two_stage)
30
+ bool first_stage, bool two_stage,
31
+ bool is_debug)
32
{
33
/* NOTE: the env->pc value visible here will not be
34
* correct, but the value visible to the exception handler
35
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
36
widened = 2;
37
}
40
}
38
/* status.SUM will be ignored if execute on background */
41
39
- sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
42
/* KVM AIA only has one APLIC instance */
40
+ sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
43
- if (virt_use_kvm_aia(s)) {
41
switch (vm) {
44
+ if (kvm_enabled() && virt_use_kvm_aia(s)) {
42
case VM_1_10_SV32:
45
create_fdt_socket_aplic(s, memmap, 0,
43
levels = 2; ptidxbits = 10; ptesize = 4; break;
46
msi_m_phandle, msi_s_phandle, phandle,
44
@@ -XXX,XX +XXX,XX @@ restart:
47
&intc_phandles[0], xplic_phandles,
45
/* Do the second stage translation on the base PTE address. */
48
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
46
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
49
47
base, NULL, MMU_DATA_LOAD,
50
g_free(intc_phandles);
48
- mmu_idx, false, true);
51
49
+ mmu_idx, false, true,
52
- if (virt_use_kvm_aia(s)) {
50
+ is_debug);
53
+ if (kvm_enabled() && virt_use_kvm_aia(s)) {
51
54
*irq_mmio_phandle = xplic_phandles[0];
52
if (vbase_ret != TRANSLATE_SUCCESS) {
55
*irq_virtio_phandle = xplic_phandles[0];
53
if (fault_pte_addr) {
56
*irq_pcie_phandle = xplic_phandles[0];
54
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
57
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
55
int mmu_idx = cpu_mmu_index(&cpu->env, false);
56
57
if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
58
- true, riscv_cpu_virt_enabled(env))) {
59
+ true, riscv_cpu_virt_enabled(env), true)) {
60
return -1;
61
}
62
63
if (riscv_cpu_virt_enabled(env)) {
64
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
65
- 0, mmu_idx, false, true)) {
66
+ 0, mmu_idx, false, true, true)) {
67
return -1;
68
}
58
}
69
}
59
}
70
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
60
71
/* Two stage lookup */
61
- if (virt_use_kvm_aia(s)) {
72
ret = get_physical_address(env, &pa, &prot, address,
62
+ if (kvm_enabled() && virt_use_kvm_aia(s)) {
73
&env->guest_phys_fault_addr, access_type,
63
kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
74
- mmu_idx, true, true);
64
VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
75
+ mmu_idx, true, true, false);
65
memmap[VIRT_APLIC_S].base,
76
77
/*
78
* A G-stage exception may be triggered during two state lookup.
79
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
80
im_address = pa;
81
82
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
83
- access_type, mmu_idx, false, true);
84
+ access_type, mmu_idx, false, true,
85
+ false);
86
87
qemu_log_mask(CPU_LOG_MMU,
88
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
89
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
90
} else {
91
/* Single stage lookup */
92
ret = get_physical_address(env, &pa, &prot, address, NULL,
93
- access_type, mmu_idx, true, false);
94
+ access_type, mmu_idx, true, false, false);
95
96
qemu_log_mask(CPU_LOG_MMU,
97
"%s address=%" VADDR_PRIx " ret %d physical "
98
--
66
--
99
2.31.1
67
2.41.0
100
68
101
69
diff view generated by jsdifflib
[PULL 15/42] hw/opentitan: Update the interrupt layout
[PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
1
Update the OpenTitan interrupt layout to match the latest OpenTitan
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
bitstreams. This involves changing the Ibex PLIC memory layout and the
3
UART interrupts.
4
2
3
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
4
environment with the following error:
5
6
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request':
7
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq'
8
collect2: error: ld returned 1 exit status
9
10
This happens because the debug build will poke into the
11
'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to
12
the KVM only function riscv_kvm_aplic_request().
13
14
There are multiple solutions to fix this. We'll go with the same
15
solution from the previous patch, i.e. add a kvm_enabled() conditional
16
to filter out the block. But there's a catch: riscv_kvm_aplic_request()
17
is a local function that would end up being used if the compiler crops
18
the block, and this won't work. Quoting Richard Henderson's explanation
19
in [1]:
20
21
"(...) the compiler won't eliminate entire unused functions with -O0"
22
23
We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its
24
declaration in kvm_riscv.h, where all other KVM specific public
25
functions are already declared. Other archs handles KVM specific code in
26
this manner and we expect to do the same from now on.
27
28
[1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/
29
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com>
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
8
---
36
---
9
include/hw/riscv/opentitan.h | 16 ++++++++--------
37
target/riscv/kvm_riscv.h | 1 +
10
hw/intc/ibex_plic.c | 20 ++++++++++----------
38
hw/intc/riscv_aplic.c | 8 ++------
11
hw/riscv/opentitan.c | 8 ++++----
39
target/riscv/kvm.c | 5 +++++
12
3 files changed, 22 insertions(+), 22 deletions(-)
40
3 files changed, 8 insertions(+), 6 deletions(-)
13
41
14
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
42
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
15
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/riscv/opentitan.h
44
--- a/target/riscv/kvm_riscv.h
17
+++ b/include/hw/riscv/opentitan.h
45
+++ b/target/riscv/kvm_riscv.h
18
@@ -XXX,XX +XXX,XX @@ enum {
46
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
19
};
47
uint64_t aia_irq_num, uint64_t aia_msi_num,
20
48
uint64_t aplic_base, uint64_t imsic_base,
21
enum {
49
uint64_t guest_num);
22
- IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
50
+void riscv_kvm_aplic_request(void *opaque, int irq, int level);
23
- IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
24
- IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
25
- IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
26
- IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
27
- IBEX_UART_TX_EMPTY_IRQ = 0x23,
28
- IBEX_UART_RX_WATERMARK_IRQ = 0x22,
29
- IBEX_UART_TX_WATERMARK_IRQ = 0x21,
30
+ IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
31
+ IBEX_UART0_RX_TIMEOUT_IRQ = 7,
32
+ IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
33
+ IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
34
+ IBEX_UART0_RX_OVERFLOW_IRQ = 4,
35
+ IBEX_UART0_TX_EMPTY_IRQ = 3,
36
+ IBEX_UART0_RX_WATERMARK_IRQ = 2,
37
+ IBEX_UART0_TX_WATERMARK_IRQ = 1,
38
};
39
51
40
#endif
52
#endif
41
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
53
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
42
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/intc/ibex_plic.c
55
--- a/hw/intc/riscv_aplic.c
44
+++ b/hw/intc/ibex_plic.c
56
+++ b/hw/intc/riscv_aplic.c
45
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
57
@@ -XXX,XX +XXX,XX @@
46
58
#include "target/riscv/cpu.h"
47
static Property ibex_plic_properties[] = {
59
#include "sysemu/sysemu.h"
48
DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
60
#include "sysemu/kvm.h"
49
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
61
+#include "kvm_riscv.h"
50
+ DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
62
#include "migration/vmstate.h"
51
63
52
DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
64
#define APLIC_MAX_IDC (1UL << 14)
53
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
65
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
54
+ DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
66
return topi;
55
67
}
56
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
68
57
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
69
-static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
58
+ DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
70
-{
59
+ DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
71
- kvm_set_irq(kvm_state, irq, !!level);
60
72
-}
61
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
73
-
62
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
74
static void riscv_aplic_request(void *opaque, int irq, int level)
63
+ DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
75
{
64
+ DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
76
bool update = false;
65
77
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
66
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
78
* have IRQ lines delegated by their parent APLIC.
67
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
79
*/
68
+ DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
80
if (!aplic->parent) {
69
+ DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
81
- if (is_kvm_aia(aplic->msimode)) {
70
82
+ if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
71
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
83
qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
72
+ DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
84
} else {
73
85
qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
74
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
86
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
75
+ DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
76
DEFINE_PROP_END_OF_LIST(),
77
};
78
79
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
80
index XXXXXXX..XXXXXXX 100644
87
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/riscv/opentitan.c
88
--- a/target/riscv/kvm.c
82
+++ b/hw/riscv/opentitan.c
89
+++ b/target/riscv/kvm.c
83
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
90
@@ -XXX,XX +XXX,XX @@
84
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
91
#include "sysemu/runstate.h"
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
92
#include "hw/riscv/numa.h"
86
0, qdev_get_gpio_in(DEVICE(&s->plic),
93
87
- IBEX_UART_TX_WATERMARK_IRQ));
94
+void riscv_kvm_aplic_request(void *opaque, int irq, int level)
88
+ IBEX_UART0_TX_WATERMARK_IRQ));
95
+{
89
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
96
+ kvm_set_irq(kvm_state, irq, !!level);
90
1, qdev_get_gpio_in(DEVICE(&s->plic),
97
+}
91
- IBEX_UART_RX_WATERMARK_IRQ));
98
+
92
+ IBEX_UART0_RX_WATERMARK_IRQ));
99
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
93
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
100
uint64_t idx)
94
2, qdev_get_gpio_in(DEVICE(&s->plic),
101
{
95
- IBEX_UART_TX_EMPTY_IRQ));
96
+ IBEX_UART0_TX_EMPTY_IRQ));
97
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
98
3, qdev_get_gpio_in(DEVICE(&s->plic),
99
- IBEX_UART_RX_OVERFLOW_IRQ));
100
+ IBEX_UART0_RX_OVERFLOW_IRQ));
101
102
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
103
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
104
--
102
--
105
2.31.1
103
2.41.0
106
104
107
105
diff view generated by jsdifflib
[PULL 02/42] docs/system/generic-loader.rst: Fix style
[PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe
1
From: Axel Heider <axelheider@gmx.de>
1
From: Robbin Ehn <rehn@rivosinc.com>
2
2
3
Fix style to have a proper description of the parameter 'force-raw'.
3
This patch adds the new extensions in
4
linux 6.5 to the hwprobe syscall.
4
5
5
Signed-off-by: Axel Heider <axelheider@gmx.de>
6
And fixes RVC check to OR with correct value.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
The previous variable contains 0 therefore it
7
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
8
did work.
9
10
Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
11
Acked-by: Richard Henderson <richard.henderson@linaro.org>
12
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
15
---
10
docs/system/generic-loader.rst | 9 ++++++---
16
linux-user/syscall.c | 14 +++++++++++++-
11
1 file changed, 6 insertions(+), 3 deletions(-)
17
1 file changed, 13 insertions(+), 1 deletion(-)
12
18
13
diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
19
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/generic-loader.rst
21
--- a/linux-user/syscall.c
16
+++ b/docs/system/generic-loader.rst
22
+++ b/linux-user/syscall.c
17
@@ -XXX,XX +XXX,XX @@ shown below:
23
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
18
specified in the executable format header. This option should only
24
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
19
be used for the boot image. This will also cause the image to be
25
#define RISCV_HWPROBE_IMA_FD (1 << 0)
20
written to the specified CPU's address space. If not specified, the
26
#define RISCV_HWPROBE_IMA_C (1 << 1)
21
- default is CPU 0. <force-raw> - Setting force-raw=on forces the file
27
+#define RISCV_HWPROBE_IMA_V (1 << 2)
22
- to be treated as a raw image. This can be used to load supported
28
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
23
- executable formats as if they were raw.
29
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
24
+ default is CPU 0.
30
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
25
+
31
26
+``<force-raw>``
32
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
27
+ Setting 'force-raw=on' forces the file to be treated as a raw image.
33
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
28
+ This can be used to load supported executable formats as if they
34
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
29
+ were raw.
35
riscv_has_ext(env, RVD) ?
30
36
RISCV_HWPROBE_IMA_FD : 0;
31
All values are parsed using the standard QemuOpts parsing. This allows the user
37
value |= riscv_has_ext(env, RVC) ?
32
to specify any values in any format supported. By default the values
38
- RISCV_HWPROBE_IMA_C : pair->value;
39
+ RISCV_HWPROBE_IMA_C : 0;
40
+ value |= riscv_has_ext(env, RVV) ?
41
+ RISCV_HWPROBE_IMA_V : 0;
42
+ value |= cfg->ext_zba ?
43
+ RISCV_HWPROBE_EXT_ZBA : 0;
44
+ value |= cfg->ext_zbb ?
45
+ RISCV_HWPROBE_EXT_ZBB : 0;
46
+ value |= cfg->ext_zbs ?
47
+ RISCV_HWPROBE_EXT_ZBS : 0;
48
__put_user(value, &pair->value);
49
break;
50
case RISCV_HWPROBE_KEY_CPUPERF_0:
33
--
51
--
34
2.31.1
52
2.41.0
35
36
diff view generated by jsdifflib
[PULL 29/42] target/riscv: fix exception index on instruction access fault
[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I
1
From: Emmanuel Blot <emmanuel.blot@sifive.com>
1
From: Ard Biesheuvel <ardb@kernel.org>
2
2
3
When no MMU is used and the guest code attempts to fetch an instruction
3
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
4
from an invalid memory location, the exception index defaults to a data
4
implement the first half of the key schedule derivation. This does not
5
load access fault, rather an instruction access fault.
5
actually involve shifting rows, so clone the same value into all four
6
columns of the AES vector to counter that operation.
6
7
7
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
8
Cc: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
10
Cc: Palmer Dabbelt <palmer@dabbelt.com>
11
Cc: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
17
---
12
target/riscv/cpu_helper.c | 4 +++-
18
target/riscv/crypto_helper.c | 17 +++++------------
13
1 file changed, 3 insertions(+), 1 deletion(-)
19
1 file changed, 5 insertions(+), 12 deletions(-)
14
20
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
21
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
23
--- a/target/riscv/crypto_helper.c
18
+++ b/target/riscv/cpu_helper.c
24
+++ b/target/riscv/crypto_helper.c
19
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
25
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
20
26
21
if (access_type == MMU_DATA_STORE) {
27
uint8_t enc_rnum = rnum;
22
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
28
uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
23
- } else {
29
- uint8_t rcon_ = 0;
24
+ } else if (access_type == MMU_DATA_LOAD) {
30
- target_ulong result;
25
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
31
+ AESState t, rc = {};
26
+ } else {
32
27
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
33
if (enc_rnum != 0xA) {
34
temp = ror32(temp, 8); /* Rotate right by 8 */
35
- rcon_ = round_consts[enc_rnum];
36
+ rc.w[0] = rc.w[1] = round_consts[enc_rnum];
28
}
37
}
29
38
30
env->badaddr = addr;
39
- temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
40
- ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
41
- ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
42
- ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
43
+ t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp;
44
+ aesenc_SB_SR_AK(&t, &t, &rc, false);
45
46
- temp ^= rcon_;
47
-
48
- result = ((uint64_t)temp << 32) | temp;
49
-
50
- return result;
51
+ return t.d[0];
52
}
53
54
target_ulong HELPER(aes64im)(target_ulong rs1)
31
--
55
--
32
2.31.1
56
2.41.0
33
57
34
58
diff view generated by jsdifflib
[PULL 09/42] target/riscv: Convert the RISC-V exceptions to an enum
[PULL v2 42/45] target/riscv: Allocate itrigger timers only once
1
From: Akihiko Odaki <akihiko.odaki@daynix.com>
2
3
riscv_trigger_init() had been called on reset events that can happen
4
several times for a CPU and it allocated timers for itrigger. If old
5
timers were present, they were simply overwritten by the new timers,
6
resulting in a memory leak.
7
8
Divide riscv_trigger_init() into two functions, namely
9
riscv_trigger_realize() and riscv_trigger_reset() and call them in
10
appropriate timing. The timer allocation will happen only once for a
11
CPU in riscv_trigger_realize().
12
13
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
14
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
5
---
20
---
6
target/riscv/cpu_bits.h | 44 ++++++++++++++++++++-------------------
21
target/riscv/debug.h | 3 ++-
7
target/riscv/cpu.c | 2 +-
22
target/riscv/cpu.c | 8 +++++++-
8
target/riscv/cpu_helper.c | 4 ++--
23
target/riscv/debug.c | 15 ++++++++++++---
9
3 files changed, 26 insertions(+), 24 deletions(-)
24
3 files changed, 21 insertions(+), 5 deletions(-)
10
25
11
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
26
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
12
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu_bits.h
28
--- a/target/riscv/debug.h
14
+++ b/target/riscv/cpu_bits.h
29
+++ b/target/riscv/debug.h
15
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
16
#define DEFAULT_RSTVEC 0x1000
31
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
17
32
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
18
/* Exception causes */
33
19
-#define EXCP_NONE -1 /* sentinel value */
34
-void riscv_trigger_init(CPURISCVState *env);
20
-#define RISCV_EXCP_INST_ADDR_MIS 0x0
35
+void riscv_trigger_realize(CPURISCVState *env);
21
-#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
36
+void riscv_trigger_reset_hold(CPURISCVState *env);
22
-#define RISCV_EXCP_ILLEGAL_INST 0x2
37
23
-#define RISCV_EXCP_BREAKPOINT 0x3
38
bool riscv_itrigger_enabled(CPURISCVState *env);
24
-#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
39
void riscv_itrigger_update_priv(CPURISCVState *env);
25
-#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
26
-#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
27
-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
28
-#define RISCV_EXCP_U_ECALL 0x8
29
-#define RISCV_EXCP_S_ECALL 0x9
30
-#define RISCV_EXCP_VS_ECALL 0xa
31
-#define RISCV_EXCP_M_ECALL 0xb
32
-#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
33
-#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
34
-#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
35
-#define RISCV_EXCP_SEMIHOST 0x10
36
-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
37
-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
38
-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
39
-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
40
+typedef enum RISCVException {
41
+ RISCV_EXCP_NONE = -1, /* sentinel value */
42
+ RISCV_EXCP_INST_ADDR_MIS = 0x0,
43
+ RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
44
+ RISCV_EXCP_ILLEGAL_INST = 0x2,
45
+ RISCV_EXCP_BREAKPOINT = 0x3,
46
+ RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
47
+ RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
48
+ RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
49
+ RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
50
+ RISCV_EXCP_U_ECALL = 0x8,
51
+ RISCV_EXCP_S_ECALL = 0x9,
52
+ RISCV_EXCP_VS_ECALL = 0xa,
53
+ RISCV_EXCP_M_ECALL = 0xb,
54
+ RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
55
+ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
56
+ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
57
+ RISCV_EXCP_SEMIHOST = 0x10,
58
+ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
59
+ RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
60
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
61
+ RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
62
+} RISCVException;
63
64
#define RISCV_EXCP_INT_FLAG 0x80000000
65
#define RISCV_EXCP_INT_MASK 0x7fffffff
66
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
67
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/cpu.c
42
--- a/target/riscv/cpu.c
69
+++ b/target/riscv/cpu.c
43
+++ b/target/riscv/cpu.c
70
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
44
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
71
env->pc = env->resetvec;
45
72
env->two_stage_lookup = false;
46
#ifndef CONFIG_USER_ONLY
73
#endif
47
if (cpu->cfg.debug) {
74
- cs->exception_index = EXCP_NONE;
48
- riscv_trigger_init(env);
75
+ cs->exception_index = RISCV_EXCP_NONE;
49
+ riscv_trigger_reset_hold(env);
76
env->load_res = -1;
50
}
77
set_default_nan_mode(1, &env->fp_status);
51
52
if (kvm_enabled()) {
53
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
54
55
riscv_cpu_register_gdb_regs_for_features(cs);
56
57
+#ifndef CONFIG_USER_ONLY
58
+ if (cpu->cfg.debug) {
59
+ riscv_trigger_realize(&cpu->env);
60
+ }
61
+#endif
62
+
63
qemu_init_vcpu(cs);
64
cpu_reset(cs);
65
66
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/debug.c
69
+++ b/target/riscv/debug.c
70
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
71
return false;
78
}
72
}
79
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
73
80
index XXXXXXX..XXXXXXX 100644
74
-void riscv_trigger_init(CPURISCVState *env)
81
--- a/target/riscv/cpu_helper.c
75
+void riscv_trigger_realize(CPURISCVState *env)
82
+++ b/target/riscv/cpu_helper.c
76
+{
83
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
77
+ int i;
84
if (irqs) {
78
+
85
return ctz64(irqs); /* since non-zero */
79
+ for (i = 0; i < RV_MAX_TRIGGERS; i++) {
86
} else {
80
+ env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
87
- return EXCP_NONE; /* indicates no pending interrupt */
81
+ riscv_itrigger_timer_cb, env);
88
+ return RISCV_EXCP_NONE; /* indicates no pending interrupt */
82
+ }
83
+}
84
+
85
+void riscv_trigger_reset_hold(CPURISCVState *env)
86
{
87
target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
88
int i;
89
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
90
env->tdata3[i] = 0;
91
env->cpu_breakpoint[i] = NULL;
92
env->cpu_watchpoint[i] = NULL;
93
- env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
94
- riscv_itrigger_timer_cb, env);
95
+ timer_del(env->itrigger_timer[i]);
89
}
96
}
90
}
97
}
91
#endif
92
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
93
94
env->two_stage_lookup = false;
95
#endif
96
- cs->exception_index = EXCP_NONE; /* mark handled to qemu */
97
+ cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
98
}
99
--
98
--
100
2.31.1
99
2.41.0
101
100
102
101
diff view generated by jsdifflib
[PULL 26/42] target/riscv/pmp: Remove outdated comment
[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
1
From: Leon Schuermann <leons@opentitan.org>
2
3
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
4
configuration lock bits must not apply. While this behavior is
5
implemented for the pmpcfgX CSRs, this bit is not respected for
6
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
7
writes work even on locked regions when the global rule-lock bypass is
8
enabled.
9
10
Signed-off-by: Leon Schuermann <leons@opentitan.org>
11
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3
Message-id: 10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
4
---
15
---
5
target/riscv/pmp.c | 4 ----
16
target/riscv/pmp.c | 4 ++++
6
1 file changed, 4 deletions(-)
17
1 file changed, 4 insertions(+)
7
18
8
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
19
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
9
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
10
--- a/target/riscv/pmp.c
21
--- a/target/riscv/pmp.c
11
+++ b/target/riscv/pmp.c
22
+++ b/target/riscv/pmp.c
12
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
13
* this program. If not, see <http://www.gnu.org/licenses/>.
14
*/
24
*/
15
25
static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
16
-/*
26
{
17
- * PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
27
+ /* mseccfg.RLB is set */
18
- */
28
+ if (MSECCFG_RLB_ISSET(env)) {
19
-
29
+ return 0;
20
#include "qemu/osdep.h"
30
+ }
21
#include "qemu/log.h"
31
22
#include "qapi/error.h"
32
if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
33
return 1;
23
--
34
--
24
2.31.1
35
2.41.0
25
26
diff view generated by jsdifflib
[PULL 11/42] target/riscv: Fix 32-bit HS mode access permissions
[PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified spec
1
From: Tommy Wu <tommy.wu@sifive.com>
2
3
According to the new spec, when vsiselect has a reserved value, attempts
4
from M-mode or HS-mode to access vsireg, or from VS-mode to access
5
sireg, should preferably raise an illegal instruction exception.
6
7
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
5
---
11
---
6
target/riscv/csr.c | 6 +++++-
12
target/riscv/csr.c | 7 +++++--
7
1 file changed, 5 insertions(+), 1 deletion(-)
13
1 file changed, 5 insertions(+), 2 deletions(-)
8
14
9
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
15
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
10
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
11
--- a/target/riscv/csr.c
17
--- a/target/riscv/csr.c
12
+++ b/target/riscv/csr.c
18
+++ b/target/riscv/csr.c
13
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
19
@@ -XXX,XX +XXX,XX @@ static int rmw_iprio(target_ulong xlen,
14
static RISCVException hmode32(CPURISCVState *env, int csrno)
20
static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
21
target_ulong new_val, target_ulong wr_mask)
15
{
22
{
16
if (!riscv_cpu_is_32bit(env)) {
23
- bool virt;
17
- return RISCV_EXCP_NONE;
24
+ bool virt, isel_reserved;
18
+ if (riscv_cpu_virt_enabled(env)) {
25
uint8_t *iprio;
19
+ return RISCV_EXCP_ILLEGAL_INST;
26
int ret = -EINVAL;
20
+ } else {
27
target_ulong priv, isel, vgein;
21
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
28
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
22
+ }
29
30
/* Decode register details from CSR number */
31
virt = false;
32
+ isel_reserved = false;
33
switch (csrno) {
34
case CSR_MIREG:
35
iprio = env->miprio;
36
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
37
riscv_cpu_mxl_bits(env)),
38
val, new_val, wr_mask);
39
}
40
+ } else {
41
+ isel_reserved = true;
23
}
42
}
24
43
25
return hmode(env, csrno);
44
done:
45
if (ret) {
46
- return (env->virt_enabled && virt) ?
47
+ return (env->virt_enabled && virt && !isel_reserved) ?
48
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
49
}
50
return RISCV_EXCP_NONE;
26
--
51
--
27
2.31.1
52
2.41.0
28
29
diff view generated by jsdifflib
[PULL 13/42] target/riscv: Use RISCVException enum for CSR access
[PULL v2 45/45] target/riscv: don't read CSR in riscv_csrrw_do64
1
From: Nikita Shubin <n.shubin@yadro.com>
2
3
As per ISA:
4
5
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
6
shall not cause any of the side effects that might occur on a CSR read."
7
8
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
9
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.
10
11
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4
Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
5
---
15
---
6
target/riscv/cpu.h | 11 +++++++----
16
target/riscv/csr.c | 24 +++++++++++++++---------
7
target/riscv/csr.c | 37 ++++++++++++++++++-------------------
17
1 file changed, 15 insertions(+), 9 deletions(-)
8
target/riscv/gdbstub.c | 8 ++++----
9
target/riscv/op_helper.c | 18 +++++++++---------
10
4 files changed, 38 insertions(+), 36 deletions(-)
11
18
12
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.h
15
+++ b/target/riscv/cpu.h
16
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
17
*pflags = flags;
18
}
19
20
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
21
- target_ulong new_value, target_ulong write_mask);
22
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
23
- target_ulong new_value, target_ulong write_mask);
24
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
25
+ target_ulong *ret_value,
26
+ target_ulong new_value, target_ulong write_mask);
27
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
28
+ target_ulong *ret_value,
29
+ target_ulong new_value,
30
+ target_ulong write_mask);
31
32
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
33
target_ulong val)
34
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
35
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/csr.c
21
--- a/target/riscv/csr.c
37
+++ b/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
38
@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
23
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
39
* csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
24
target_ulong write_mask)
40
*/
41
42
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
43
- target_ulong new_value, target_ulong write_mask)
44
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
45
+ target_ulong *ret_value,
46
+ target_ulong new_value, target_ulong write_mask)
47
{
25
{
48
- int ret;
26
RISCVException ret;
49
+ RISCVException ret;
27
- target_ulong old_value;
50
target_ulong old_value;
28
+ target_ulong old_value = 0;
51
RISCVCPU *cpu = env_archcpu(env);
52
53
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
54
55
if ((write_mask && read_only) ||
56
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
57
- return -RISCV_EXCP_ILLEGAL_INST;
58
+ return RISCV_EXCP_ILLEGAL_INST;
59
}
60
#endif
61
62
/* ensure the CSR extension is enabled. */
63
if (!cpu->cfg.ext_icsr) {
64
- return -RISCV_EXCP_ILLEGAL_INST;
65
+ return RISCV_EXCP_ILLEGAL_INST;
66
}
67
68
/* check predicate */
69
if (!csr_ops[csrno].predicate) {
70
- return -RISCV_EXCP_ILLEGAL_INST;
71
+ return RISCV_EXCP_ILLEGAL_INST;
72
}
73
ret = csr_ops[csrno].predicate(env, csrno);
74
if (ret != RISCV_EXCP_NONE) {
75
- return -ret;
76
+ return ret;
77
}
78
29
79
/* execute combined read/write operation if it exists */
30
/* execute combined read/write operation if it exists */
80
if (csr_ops[csrno].op) {
31
if (csr_ops[csrno].op) {
81
- ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
32
return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
82
- if (ret != RISCV_EXCP_NONE) {
83
- return -ret;
84
- }
85
- return 0;
86
+ return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
87
}
33
}
88
34
89
/* if no accessor exists then return failure */
35
- /* if no accessor exists then return failure */
90
if (!csr_ops[csrno].read) {
36
- if (!csr_ops[csrno].read) {
91
- return -RISCV_EXCP_ILLEGAL_INST;
37
- return RISCV_EXCP_ILLEGAL_INST;
92
+ return RISCV_EXCP_ILLEGAL_INST;
38
- }
39
- /* read old value */
40
- ret = csr_ops[csrno].read(env, csrno, &old_value);
41
- if (ret != RISCV_EXCP_NONE) {
42
- return ret;
43
+ /*
44
+ * ret_value == NULL means that rd=x0 and we're coming from helper_csrw()
45
+ * and we can't throw side effects caused by CSR reads.
46
+ */
47
+ if (ret_value) {
48
+ /* if no accessor exists then return failure */
49
+ if (!csr_ops[csrno].read) {
50
+ return RISCV_EXCP_ILLEGAL_INST;
51
+ }
52
+ /* read old value */
53
+ ret = csr_ops[csrno].read(env, csrno, &old_value);
54
+ if (ret != RISCV_EXCP_NONE) {
55
+ return ret;
56
+ }
93
}
57
}
94
/* read old value */
95
ret = csr_ops[csrno].read(env, csrno, &old_value);
96
if (ret != RISCV_EXCP_NONE) {
97
- return -ret;
98
+ return ret;
99
}
100
58
101
/* write value if writable and write mask set, otherwise drop writes */
59
/* write value if writable and write mask set, otherwise drop writes */
102
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
103
if (csr_ops[csrno].write) {
104
ret = csr_ops[csrno].write(env, csrno, new_value);
105
if (ret != RISCV_EXCP_NONE) {
106
- return -ret;
107
+ return ret;
108
}
109
}
110
}
111
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
112
*ret_value = old_value;
113
}
114
115
- return 0;
116
+ return RISCV_EXCP_NONE;
117
}
118
119
/*
120
* Debugger support. If not in user mode, set env->debugger before the
121
* riscv_csrrw call and clear it after the call.
122
*/
123
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
124
- target_ulong new_value, target_ulong write_mask)
125
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
126
+ target_ulong *ret_value,
127
+ target_ulong new_value,
128
+ target_ulong write_mask)
129
{
130
- int ret;
131
+ RISCVException ret;
132
#if !defined(CONFIG_USER_ONLY)
133
env->debugger = true;
134
#endif
135
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/target/riscv/gdbstub.c
138
+++ b/target/riscv/gdbstub.c
139
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
140
*/
141
result = riscv_csrrw_debug(env, n - 32, &val,
142
0, 0);
143
- if (result == 0) {
144
+ if (result == RISCV_EXCP_NONE) {
145
return gdb_get_regl(buf, val);
146
}
147
}
148
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
149
*/
150
result = riscv_csrrw_debug(env, n - 32, NULL,
151
val, -1);
152
- if (result == 0) {
153
+ if (result == RISCV_EXCP_NONE) {
154
return sizeof(target_ulong);
155
}
156
}
157
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
158
int result;
159
160
result = riscv_csrrw_debug(env, n, &val, 0, 0);
161
- if (result == 0) {
162
+ if (result == RISCV_EXCP_NONE) {
163
return gdb_get_regl(buf, val);
164
}
165
}
166
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
167
int result;
168
169
result = riscv_csrrw_debug(env, n, NULL, val, -1);
170
- if (result == 0) {
171
+ if (result == RISCV_EXCP_NONE) {
172
return sizeof(target_ulong);
173
}
174
}
175
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/target/riscv/op_helper.c
178
+++ b/target/riscv/op_helper.c
179
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
180
target_ulong csr)
181
{
182
target_ulong val = 0;
183
- int ret = riscv_csrrw(env, csr, &val, src, -1);
184
+ RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
185
186
- if (ret < 0) {
187
- riscv_raise_exception(env, -ret, GETPC());
188
+ if (ret != RISCV_EXCP_NONE) {
189
+ riscv_raise_exception(env, ret, GETPC());
190
}
191
return val;
192
}
193
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
194
target_ulong csr, target_ulong rs1_pass)
195
{
196
target_ulong val = 0;
197
- int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
198
+ RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
199
200
- if (ret < 0) {
201
- riscv_raise_exception(env, -ret, GETPC());
202
+ if (ret != RISCV_EXCP_NONE) {
203
+ riscv_raise_exception(env, ret, GETPC());
204
}
205
return val;
206
}
207
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
208
target_ulong csr, target_ulong rs1_pass)
209
{
210
target_ulong val = 0;
211
- int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
212
+ RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
213
214
- if (ret < 0) {
215
- riscv_raise_exception(env, -ret, GETPC());
216
+ if (ret != RISCV_EXCP_NONE) {
217
+ riscv_raise_exception(env, ret, GETPC());
218
}
219
return val;
220
}
221
--
60
--
222
2.31.1
61
2.41.0
223
224
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