[PULL 0/5] tcg patch queue
[PULL 00/24] tcg patch queue
1
The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
1
The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
2
2
3
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)
3
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
8
8
9
for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:
9
for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
10
10
11
decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)
11
Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Include cleanups.
14
Move gdb singlestep to generic code
15
Decodetree enhancements for power10.
15
Fix cpu_common_props
16
16
17
----------------------------------------------------------------
17
----------------------------------------------------------------
18
Luis Fernando Fujita Pires (1):
18
Richard Henderson (24):
19
decodetree: Add support for 64-bit instructions
19
accel/tcg: Handle gdb singlestep in cpu_tb_exec
20
target/alpha: Drop checks for singlestep_enabled
21
target/avr: Drop checks for singlestep_enabled
22
target/cris: Drop checks for singlestep_enabled
23
target/hexagon: Drop checks for singlestep_enabled
24
target/arm: Drop checks for singlestep_enabled
25
target/hppa: Drop checks for singlestep_enabled
26
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
27
target/i386: Drop check for singlestep_enabled
28
target/m68k: Drop checks for singlestep_enabled
29
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
30
target/microblaze: Drop checks for singlestep_enabled
31
target/mips: Fix single stepping
32
target/mips: Drop exit checks for singlestep_enabled
33
target/openrisc: Drop checks for singlestep_enabled
34
target/ppc: Drop exit checks for singlestep_enabled
35
target/riscv: Remove dead code after exception
36
target/riscv: Remove exit_tb and lookup_and_goto_ptr
37
target/rx: Drop checks for singlestep_enabled
38
target/s390x: Drop check for singlestep_enabled
39
target/sh4: Drop check for singlestep_enabled
40
target/tricore: Drop check for singlestep_enabled
41
target/xtensa: Drop check for singlestep_enabled
42
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
20
43
21
Philippe Mathieu-Daudé (1):
44
include/hw/core/cpu.h | 1 +
22
exec: Remove accel/tcg/ from include paths
45
target/i386/helper.h | 1 -
46
target/rx/helper.h | 1 -
47
target/sh4/helper.h | 1 -
48
target/tricore/helper.h | 1 -
49
accel/tcg/cpu-exec.c | 11 ++++
50
cpu.c | 21 ++++++++
51
hw/core/cpu-common.c | 17 +-----
52
target/alpha/translate.c | 13 ++---
53
target/arm/translate-a64.c | 10 +---
54
target/arm/translate.c | 36 +++----------
55
target/avr/translate.c | 19 ++-----
56
target/cris/translate.c | 16 ------
57
target/hexagon/translate.c | 12 +----
58
target/hppa/translate.c | 17 ++----
59
target/i386/tcg/misc_helper.c | 8 ---
60
target/i386/tcg/translate.c | 9 ++--
61
target/m68k/translate.c | 44 ++++-----------
62
target/microblaze/translate.c | 18 ++-----
63
target/mips/tcg/translate.c | 75 ++++++++++++--------------
64
target/openrisc/translate.c | 18 ++-----
65
target/ppc/translate.c | 38 +++----------
66
target/riscv/translate.c | 27 +---------
67
target/rx/op_helper.c | 8 ---
68
target/rx/translate.c | 12 +----
69
target/s390x/tcg/translate.c | 8 +--
70
target/sh4/op_helper.c | 5 --
71
target/sh4/translate.c | 14 ++---
72
target/tricore/op_helper.c | 7 ---
73
target/tricore/translate.c | 14 +----
74
target/xtensa/translate.c | 25 +++------
75
target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
76
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-
77
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
78
34 files changed, 141 insertions(+), 386 deletions(-)
23
79
24
Richard Henderson (3):
25
decodetree: Introduce whex and whexC helpers
26
decodetree: More use of f-strings
27
decodetree: Extend argument set syntax to allow types
28
29
docs/devel/decodetree.rst | 11 ++-
30
meson.build | 1 -
31
include/exec/helper-gen.h | 4 +-
32
include/exec/helper-proto.h | 4 +-
33
include/exec/helper-tcg.h | 4 +-
34
tests/decode/succ_argset_type1.decode | 1 +
35
scripts/decodetree.py | 172 +++++++++++++++++++---------------
36
7 files changed, 112 insertions(+), 85 deletions(-)
37
create mode 100644 tests/decode/succ_argset_type1.decode
38
diff view generated by jsdifflib
New patch
[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec
1
Currently the change in cpu_tb_exec is masked by the debug exception
2
being raised by the translators. But this allows us to remove that code.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/cpu-exec.c | 11 +++++++++++
7
1 file changed, 11 insertions(+)
8
9
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/accel/tcg/cpu-exec.c
12
+++ b/accel/tcg/cpu-exec.c
13
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
14
cc->set_pc(cpu, last_tb->pc);
15
}
16
}
17
+
18
+ /*
19
+ * If gdb single-step, and we haven't raised another exception,
20
+ * raise a debug exception. Single-step with another exception
21
+ * is handled in cpu_handle_exception.
22
+ */
23
+ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
24
+ cpu->exception_index = EXCP_DEBUG;
25
+ cpu_loop_exit(cpu);
26
+ }
27
+
28
return last_tb;
29
}
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 02/24] target/alpha: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/alpha/translate.c | 13 +++----------
7
1 file changed, 3 insertions(+), 10 deletions(-)
8
9
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/alpha/translate.c
12
+++ b/target/alpha/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
15
/* FALLTHRU */
16
case DISAS_PC_UPDATED:
17
- if (!ctx->base.singlestep_enabled) {
18
- tcg_gen_lookup_and_goto_ptr();
19
- break;
20
- }
21
- /* FALLTHRU */
22
+ tcg_gen_lookup_and_goto_ptr();
23
+ break;
24
case DISAS_PC_UPDATED_NOCHAIN:
25
- if (ctx->base.singlestep_enabled) {
26
- gen_excp_1(EXCP_DEBUG, 0);
27
- } else {
28
- tcg_gen_exit_tb(NULL, 0);
29
- }
30
+ tcg_gen_exit_tb(NULL, 0);
31
break;
32
default:
33
g_assert_not_reached();
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
New patch
[PULL 03/24] target/avr: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Tested-by: Michael Rolnik <mrolnik@gmail.com>
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 19 ++++---------------
9
1 file changed, 4 insertions(+), 15 deletions(-)
10
11
diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tcg_gen_exit_tb(tb, n);
17
} else {
18
tcg_gen_movi_i32(cpu_pc, dest);
19
- if (ctx->base.singlestep_enabled) {
20
- gen_helper_debug(cpu_env);
21
- } else {
22
- tcg_gen_lookup_and_goto_ptr();
23
- }
24
+ tcg_gen_lookup_and_goto_ptr();
25
}
26
ctx->base.is_jmp = DISAS_NORETURN;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
tcg_gen_movi_tl(cpu_pc, ctx->npc);
30
/* fall through */
31
case DISAS_LOOKUP:
32
- if (!ctx->base.singlestep_enabled) {
33
- tcg_gen_lookup_and_goto_ptr();
34
- break;
35
- }
36
- /* fall through */
37
+ tcg_gen_lookup_and_goto_ptr();
38
+ break;
39
case DISAS_EXIT:
40
- if (ctx->base.singlestep_enabled) {
41
- gen_helper_debug(cpu_env);
42
- } else {
43
- tcg_gen_exit_tb(NULL, 0);
44
- }
45
+ tcg_gen_exit_tb(NULL, 0);
46
break;
47
default:
48
g_assert_not_reached();
49
--
50
2.25.1
51
52
diff view generated by jsdifflib
New patch
[PULL 04/24] target/cris: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/cris/translate.c | 16 ----------------
6
1 file changed, 16 deletions(-)
7
8
diff --git a/target/cris/translate.c b/target/cris/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/cris/translate.c
11
+++ b/target/cris/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13
}
14
}
15
16
- if (unlikely(dc->base.singlestep_enabled)) {
17
- switch (is_jmp) {
18
- case DISAS_TOO_MANY:
19
- case DISAS_UPDATE_NEXT:
20
- tcg_gen_movi_tl(env_pc, npc);
21
- /* fall through */
22
- case DISAS_JUMP:
23
- case DISAS_UPDATE:
24
- t_gen_raise_exception(EXCP_DEBUG);
25
- return;
26
- default:
27
- break;
28
- }
29
- g_assert_not_reached();
30
- }
31
-
32
switch (is_jmp) {
33
case DISAS_TOO_MANY:
34
gen_goto_tb(dc, 0, npc);
35
--
36
2.25.1
37
38
diff view generated by jsdifflib
New patch
[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hexagon/translate.c | 12 ++----------
7
1 file changed, 2 insertions(+), 10 deletions(-)
8
9
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hexagon/translate.c
12
+++ b/target/hexagon/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
14
{
15
gen_exec_counters(ctx);
16
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_exception_raw(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_exit_tb(NULL, 0);
21
- }
22
+ tcg_gen_exit_tb(NULL, 0);
23
ctx->base.is_jmp = DISAS_NORETURN;
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
27
case DISAS_TOO_MANY:
28
gen_exec_counters(ctx);
29
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
30
- if (ctx->base.singlestep_enabled) {
31
- gen_exception_raw(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
break;
37
case DISAS_NORETURN:
38
break;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
New patch
[PULL 06/24] target/arm: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/arm/translate-a64.c | 10 ++--------
6
target/arm/translate.c | 36 ++++++------------------------------
7
2 files changed, 8 insertions(+), 38 deletions(-)
8
9
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate-a64.c
12
+++ b/target/arm/translate-a64.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
14
gen_a64_set_pc_im(dest);
15
if (s->ss_active) {
16
gen_step_complete_exception(s);
17
- } else if (s->base.singlestep_enabled) {
18
- gen_exception_internal(EXCP_DEBUG);
19
} else {
20
tcg_gen_lookup_and_goto_ptr();
21
s->base.is_jmp = DISAS_NORETURN;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
23
{
24
DisasContext *dc = container_of(dcbase, DisasContext, base);
25
26
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
27
+ if (unlikely(dc->ss_active)) {
28
/* Note that this means single stepping WFI doesn't halt the CPU.
29
* For conditional branch insns this is harmless unreachable code as
30
* gen_goto_tb() has already handled emitting the debug exception
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
32
/* fall through */
33
case DISAS_EXIT:
34
case DISAS_JUMP:
35
- if (dc->base.singlestep_enabled) {
36
- gen_exception_internal(EXCP_DEBUG);
37
- } else {
38
- gen_step_complete_exception(dc);
39
- }
40
+ gen_step_complete_exception(dc);
41
break;
42
case DISAS_NORETURN:
43
break;
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
49
tcg_temp_free_i32(tcg_excp);
50
}
51
52
-static void gen_step_complete_exception(DisasContext *s)
53
+static void gen_singlestep_exception(DisasContext *s)
54
{
55
/* We just completed step of an insn. Move from Active-not-pending
56
* to Active-pending, and then also take the swstep exception.
57
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
58
s->base.is_jmp = DISAS_NORETURN;
59
}
60
61
-static void gen_singlestep_exception(DisasContext *s)
62
-{
63
- /* Generate the right kind of exception for singlestep, which is
64
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
65
- * gdb singlestepping.
66
- */
67
- if (s->ss_active) {
68
- gen_step_complete_exception(s);
69
- } else {
70
- gen_exception_internal(EXCP_DEBUG);
71
- }
72
-}
73
-
74
-static inline bool is_singlestepping(DisasContext *s)
75
-{
76
- /* Return true if we are singlestepping either because of
77
- * architectural singlestep or QEMU gdbstub singlestep. This does
78
- * not include the command line '-singlestep' mode which is rather
79
- * misnamed as it only means "one instruction per TB" and doesn't
80
- * affect the code we generate.
81
- */
82
- return s->base.singlestep_enabled || s->ss_active;
83
-}
84
-
85
void clear_eci_state(DisasContext *s)
86
{
87
/*
88
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
89
/* Is the new PC value in the magic range indicating exception return? */
90
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
91
/* No: end the TB as we would for a DISAS_JMP */
92
- if (is_singlestepping(s)) {
93
+ if (s->ss_active) {
94
gen_singlestep_exception(s);
95
} else {
96
tcg_gen_exit_tb(NULL, 0);
97
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
98
/* Jump, specifying which TB number to use if we gen_goto_tb() */
99
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
100
{
101
- if (unlikely(is_singlestepping(s))) {
102
+ if (unlikely(s->ss_active)) {
103
/* An indirect jump so that we still trigger the debug exception. */
104
gen_set_pc_im(s, dest);
105
s->base.is_jmp = DISAS_JUMP;
106
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
107
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
108
109
/* If architectural single step active, limit to 1. */
110
- if (is_singlestepping(dc)) {
111
+ if (dc->ss_active) {
112
dc->base.max_insns = 1;
113
}
114
115
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
116
* insn codepath itself.
117
*/
118
gen_bx_excret_final_code(dc);
119
- } else if (unlikely(is_singlestepping(dc))) {
120
+ } else if (unlikely(dc->ss_active)) {
121
/* Unconditional and "condition passed" instruction codepath. */
122
switch (dc->base.is_jmp) {
123
case DISAS_SWI:
124
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
125
/* "Condition failed" instruction codepath for the branch/trap insn */
126
gen_set_label(dc->condlabel);
127
gen_set_condexec(dc);
128
- if (unlikely(is_singlestepping(dc))) {
129
+ if (unlikely(dc->ss_active)) {
130
gen_set_pc_im(dc, dc->base.pc_next);
131
gen_singlestep_exception(dc);
132
} else {
133
--
134
2.25.1
135
136
diff view generated by jsdifflib
New patch
[PULL 07/24] target/hppa: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hppa/translate.c | 17 ++++-------------
7
1 file changed, 4 insertions(+), 13 deletions(-)
8
9
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hppa/translate.c
12
+++ b/target/hppa/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
14
} else {
15
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
16
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_excp_1(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
}
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
27
gen_helper_rfi(cpu_env);
28
}
29
/* Exit the TB to recognize new interrupts. */
30
- if (ctx->base.singlestep_enabled) {
31
- gen_excp_1(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
ctx->base.is_jmp = DISAS_NORETURN;
37
38
return nullify_end(ctx);
39
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
40
nullify_save(ctx);
41
/* FALLTHRU */
42
case DISAS_IAQ_N_UPDATED:
43
- if (ctx->base.singlestep_enabled) {
44
- gen_excp_1(EXCP_DEBUG);
45
- } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
46
+ if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
47
tcg_gen_lookup_and_goto_ptr();
48
+ break;
49
}
50
/* FALLTHRU */
51
case DISAS_EXIT:
52
--
53
2.25.1
54
55
diff view generated by jsdifflib
New patch
[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/i386/tcg/translate.c | 5 +++--
7
1 file changed, 3 insertions(+), 2 deletions(-)
8
9
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/i386/tcg/translate.c
12
+++ b/target/i386/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
14
DisasContext *dc = container_of(dcbase, DisasContext, base);
15
CPUX86State *env = cpu->env_ptr;
16
uint32_t flags = dc->base.tb->flags;
17
+ uint32_t cflags = tb_cflags(dc->base.tb);
18
int cpl = (flags >> HF_CPL_SHIFT) & 3;
19
int iopl = (flags >> IOPL_SHIFT) & 3;
20
21
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
22
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
23
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
24
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
25
- dc->jmp_opt = !(dc->base.singlestep_enabled ||
26
+ dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
27
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
28
/*
29
* If jmp_opt, we want to handle each string instruction individually.
30
* For icount also disable repz optimization so that each iteration
31
* is accounted separately.
32
*/
33
- dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
34
+ dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
35
36
dc->T0 = tcg_temp_new();
37
dc->T1 = tcg_temp_new();
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
New patch
[PULL 09/24] target/i386: Drop check for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/i386/helper.h | 1 -
6
target/i386/tcg/misc_helper.c | 8 --------
7
target/i386/tcg/translate.c | 4 +---
8
3 files changed, 1 insertion(+), 12 deletions(-)
9
10
diff --git a/target/i386/helper.h b/target/i386/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/i386/helper.h
13
+++ b/target/i386/helper.h
14
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
15
DEF_HELPER_2(sysret, void, env, int)
16
#endif
17
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
18
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
19
DEF_HELPER_1(reset_rf, void, env)
20
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
21
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
22
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/i386/tcg/misc_helper.c
25
+++ b/target/i386/tcg/misc_helper.c
26
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
27
do_pause(env);
28
}
29
30
-void QEMU_NORETURN helper_debug(CPUX86State *env)
31
-{
32
- CPUState *cs = env_cpu(env);
33
-
34
- cs->exception_index = EXCP_DEBUG;
35
- cpu_loop_exit(cs);
36
-}
37
-
38
uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
39
{
40
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
41
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/i386/tcg/translate.c
44
+++ b/target/i386/tcg/translate.c
45
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
46
if (s->base.tb->flags & HF_RF_MASK) {
47
gen_helper_reset_rf(cpu_env);
48
}
49
- if (s->base.singlestep_enabled) {
50
- gen_helper_debug(cpu_env);
51
- } else if (recheck_tf) {
52
+ if (recheck_tf) {
53
gen_helper_rechecking_single_step(cpu_env);
54
tcg_gen_exit_tb(NULL, 0);
55
} else if (s->flags & HF_TF_MASK) {
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
New patch
[PULL 10/24] target/m68k: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Acked-by: Laurent Vivier <laurent@vivier.eu>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/m68k/translate.c | 44 +++++++++--------------------------------
7
1 file changed, 9 insertions(+), 35 deletions(-)
8
9
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/m68k/translate.c
12
+++ b/target/m68k/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
14
}
15
}
16
17
-static bool is_singlestepping(DisasContext *s)
18
-{
19
- /*
20
- * Return true if we are singlestepping either because of
21
- * architectural singlestep or QEMU gdbstub singlestep. This does
22
- * not include the command line '-singlestep' mode which is rather
23
- * misnamed as it only means "one instruction per TB" and doesn't
24
- * affect the code we generate.
25
- */
26
- return s->base.singlestep_enabled || s->ss_active;
27
-}
28
-
29
/* is_jmp field values */
30
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
31
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
32
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
33
s->base.is_jmp = DISAS_NORETURN;
34
}
35
36
-static void gen_singlestep_exception(DisasContext *s)
37
-{
38
- /*
39
- * Generate the right kind of exception for singlestep, which is
40
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
41
- * gdb singlestepping.
42
- */
43
- if (s->ss_active) {
44
- gen_raise_exception(EXCP_TRACE);
45
- } else {
46
- gen_raise_exception(EXCP_DEBUG);
47
- }
48
-}
49
-
50
static inline void gen_addr_fault(DisasContext *s)
51
{
52
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
53
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
54
/* Generate a jump to an immediate address. */
55
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
56
{
57
- if (unlikely(is_singlestepping(s))) {
58
+ if (unlikely(s->ss_active)) {
59
update_cc_op(s);
60
tcg_gen_movi_i32(QREG_PC, dest);
61
- gen_singlestep_exception(s);
62
+ gen_raise_exception(EXCP_TRACE);
63
} else if (translator_use_goto_tb(&s->base, dest)) {
64
tcg_gen_goto_tb(n);
65
tcg_gen_movi_i32(QREG_PC, dest);
66
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
67
68
dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
69
/* If architectural single step active, limit to 1 */
70
- if (is_singlestepping(dc)) {
71
+ if (dc->ss_active) {
72
dc->base.max_insns = 1;
73
}
74
}
75
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
76
break;
77
case DISAS_TOO_MANY:
78
update_cc_op(dc);
79
- if (is_singlestepping(dc)) {
80
+ if (dc->ss_active) {
81
tcg_gen_movi_i32(QREG_PC, dc->pc);
82
- gen_singlestep_exception(dc);
83
+ gen_raise_exception(EXCP_TRACE);
84
} else {
85
gen_jmp_tb(dc, 0, dc->pc);
86
}
87
break;
88
case DISAS_JUMP:
89
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
90
- if (is_singlestepping(dc)) {
91
- gen_singlestep_exception(dc);
92
+ if (dc->ss_active) {
93
+ gen_raise_exception(EXCP_TRACE);
94
} else {
95
tcg_gen_lookup_and_goto_ptr();
96
}
97
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
98
* We updated CC_OP and PC in gen_exit_tb, but also modified
99
* other state that may require returning to the main loop.
100
*/
101
- if (is_singlestepping(dc)) {
102
- gen_singlestep_exception(dc);
103
+ if (dc->ss_active) {
104
+ gen_raise_exception(EXCP_TRACE);
105
} else {
106
tcg_gen_exit_tb(NULL, 0);
107
}
108
--
109
2.25.1
110
111
diff view generated by jsdifflib
New patch
[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/microblaze/translate.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/microblaze/translate.c
12
+++ b/target/microblaze/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
14
break;
15
16
case DISAS_JUMP:
17
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
18
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
19
/* Direct jump. */
20
tcg_gen_discard_i32(cpu_btarget);
21
22
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
23
return;
24
}
25
26
- /* Indirect jump (or direct jump w/ singlestep) */
27
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/microblaze/translate.c | 14 ++------------
6
1 file changed, 2 insertions(+), 12 deletions(-)
7
8
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/microblaze/translate.c
11
+++ b/target/microblaze/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
13
14
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
15
{
16
- if (dc->base.singlestep_enabled) {
17
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
18
- tcg_gen_movi_i32(cpu_pc, dest);
19
- gen_helper_raise_exception(cpu_env, tmp);
20
- tcg_temp_free_i32(tmp);
21
- } else if (translator_use_goto_tb(&dc->base, dest)) {
22
+ if (translator_use_goto_tb(&dc->base, dest)) {
23
tcg_gen_goto_tb(n);
24
tcg_gen_movi_i32(cpu_pc, dest);
25
tcg_gen_exit_tb(dc->base.tb, n);
26
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
27
/* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
-
31
- if (unlikely(cs->singlestep_enabled)) {
32
- gen_raise_exception(dc, EXCP_DEBUG);
33
- } else {
34
- tcg_gen_lookup_and_goto_ptr();
35
- }
36
+ tcg_gen_lookup_and_goto_ptr();
37
return;
38
39
default:
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
New patch
[PULL 13/24] target/mips: Fix single stepping
1
As per an ancient comment in mips_tr_translate_insn about the
2
expectations of gdb, when restarting the insn in a delay slot
3
we also re-execute the branch. Which means that we are
4
expected to execute two insns in this case.
1
5
6
This has been broken since 8b86d6d2580, where we forced max_insns
7
to 1 while single-stepping. This resulted in an exit from the
8
translator loop after the branch but before the delay slot is
9
translated.
10
11
Increase the max_insns to 2 for this case. In addition, bypass
12
the end-of-page check, for when the branch itself ends the page.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
target/mips/tcg/translate.c | 25 ++++++++++++++++---------
18
1 file changed, 16 insertions(+), 9 deletions(-)
19
20
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/mips/tcg/translate.c
23
+++ b/target/mips/tcg/translate.c
24
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
25
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
26
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
27
28
+ /*
29
+ * Execute a branch and its delay slot as a single instruction.
30
+ * This is what GDB expects and is consistent with what the
31
+ * hardware does (e.g. if a delay slot instruction faults, the
32
+ * reported PC is the PC of the branch).
33
+ */
34
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
35
+ ctx->base.max_insns = 2;
36
+ }
37
+
38
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
39
ctx->hflags);
40
}
41
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
42
if (ctx->base.is_jmp != DISAS_NEXT) {
43
return;
44
}
45
+
46
/*
47
- * Execute a branch and its delay slot as a single instruction.
48
- * This is what GDB expects and is consistent with what the
49
- * hardware does (e.g. if a delay slot instruction faults, the
50
- * reported PC is the PC of the branch).
51
+ * End the TB on (most) page crossings.
52
+ * See mips_tr_init_disas_context about single-stepping a branch
53
+ * together with its delay slot.
54
*/
55
- if (ctx->base.singlestep_enabled &&
56
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
57
- ctx->base.is_jmp = DISAS_TOO_MANY;
58
- }
59
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
60
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
61
+ && !ctx->base.singlestep_enabled) {
62
ctx->base.is_jmp = DISAS_TOO_MANY;
63
}
64
}
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
New patch
[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/mips/tcg/translate.c | 50 +++++++++++++------------------------
7
1 file changed, 18 insertions(+), 32 deletions(-)
8
9
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/mips/tcg/translate.c
12
+++ b/target/mips/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
14
tcg_gen_exit_tb(ctx->base.tb, n);
15
} else {
16
gen_save_pc(dest);
17
- if (ctx->base.singlestep_enabled) {
18
- save_cpu_state(ctx, 0);
19
- gen_helper_raise_exception_debug(cpu_env);
20
- } else {
21
- tcg_gen_lookup_and_goto_ptr();
22
- }
23
+ tcg_gen_lookup_and_goto_ptr();
24
}
25
}
26
27
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
28
} else {
29
tcg_gen_mov_tl(cpu_PC, btarget);
30
}
31
- if (ctx->base.singlestep_enabled) {
32
- save_cpu_state(ctx, 0);
33
- gen_helper_raise_exception_debug(cpu_env);
34
- }
35
tcg_gen_lookup_and_goto_ptr();
36
break;
37
default:
38
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
39
{
40
DisasContext *ctx = container_of(dcbase, DisasContext, base);
41
42
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
43
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
44
- gen_helper_raise_exception_debug(cpu_env);
45
- } else {
46
- switch (ctx->base.is_jmp) {
47
- case DISAS_STOP:
48
- gen_save_pc(ctx->base.pc_next);
49
- tcg_gen_lookup_and_goto_ptr();
50
- break;
51
- case DISAS_NEXT:
52
- case DISAS_TOO_MANY:
53
- save_cpu_state(ctx, 0);
54
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
55
- break;
56
- case DISAS_EXIT:
57
- tcg_gen_exit_tb(NULL, 0);
58
- break;
59
- case DISAS_NORETURN:
60
- break;
61
- default:
62
- g_assert_not_reached();
63
- }
64
+ switch (ctx->base.is_jmp) {
65
+ case DISAS_STOP:
66
+ gen_save_pc(ctx->base.pc_next);
67
+ tcg_gen_lookup_and_goto_ptr();
68
+ break;
69
+ case DISAS_NEXT:
70
+ case DISAS_TOO_MANY:
71
+ save_cpu_state(ctx, 0);
72
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
73
+ break;
74
+ case DISAS_EXIT:
75
+ tcg_gen_exit_tb(NULL, 0);
76
+ break;
77
+ case DISAS_NORETURN:
78
+ break;
79
+ default:
80
+ g_assert_not_reached();
81
}
82
}
83
84
--
85
2.25.1
86
87
diff view generated by jsdifflib
New patch
[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/openrisc/translate.c | 18 +++---------------
7
1 file changed, 3 insertions(+), 15 deletions(-)
8
9
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/openrisc/translate.c
12
+++ b/target/openrisc/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
14
/* The jump destination is indirect/computed; use jmp_pc. */
15
tcg_gen_mov_tl(cpu_pc, jmp_pc);
16
tcg_gen_discard_tl(jmp_pc);
17
- if (unlikely(dc->base.singlestep_enabled)) {
18
- gen_exception(dc, EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
break;
24
}
25
/* The jump destination is direct; use jmp_pc_imm.
26
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
27
break;
28
}
29
tcg_gen_movi_tl(cpu_pc, jmp_dest);
30
- if (unlikely(dc->base.singlestep_enabled)) {
31
- gen_exception(dc, EXCP_DEBUG);
32
- } else {
33
- tcg_gen_lookup_and_goto_ptr();
34
- }
35
+ tcg_gen_lookup_and_goto_ptr();
36
break;
37
38
case DISAS_EXIT:
39
- if (unlikely(dc->base.singlestep_enabled)) {
40
- gen_exception(dc, EXCP_DEBUG);
41
- } else {
42
- tcg_gen_exit_tb(NULL, 0);
43
- }
44
+ tcg_gen_exit_tb(NULL, 0);
45
break;
46
default:
47
g_assert_not_reached();
48
--
49
2.25.1
50
51
diff view generated by jsdifflib
[PULL 1/5] exec: Remove accel/tcg/ from include paths
[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
GDB single-stepping is now handled generically.
2
Reuse gen_debug_exception to handle architectural debug exceptions.
2
3
3
When TCG is enabled, the accel/tcg/ include path is added to the
4
project global include search list. This accel/tcg/ directory
5
contains a header named "internal.h" which, while intented to
6
be internal to accel/tcg/, is accessible by all files compiled
7
when TCG is enabled. This might lead to problem with other
8
directories using the same "internal.h" header name:
9
10
$ git ls-files | fgrep /internal.h
11
accel/tcg/internal.h
12
include/hw/ide/internal.h
13
target/hexagon/internal.h
14
target/mips/internal.h
15
target/ppc/internal.h
16
target/s390x/internal.h
17
18
As we don't need to expose accel/tcg/ internals to the rest of
19
the code base, simplify by removing it from the include search
20
list, and include the accel/tcg/ public headers relative to the
21
project root search path (which is already in the generic include
22
search path).
23
24
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Claudio Fontana <cfontana@suse.de>
26
Message-Id: <20210413081008.3409459-1-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
5
---
29
meson.build | 1 -
6
target/ppc/translate.c | 38 ++++++++------------------------------
30
include/exec/helper-gen.h | 4 ++--
7
1 file changed, 8 insertions(+), 30 deletions(-)
31
include/exec/helper-proto.h | 4 ++--
32
include/exec/helper-tcg.h | 4 ++--
33
4 files changed, 6 insertions(+), 7 deletions(-)
34
8
35
diff --git a/meson.build b/meson.build
9
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
36
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
37
--- a/meson.build
11
--- a/target/ppc/translate.c
38
+++ b/meson.build
12
+++ b/target/ppc/translate.c
39
@@ -XXX,XX +XXX,XX @@ if not get_option('tcg').disabled()
40
tcg_arch = 'riscv'
41
endif
42
add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch,
43
- '-iquote', meson.current_source_dir() / 'accel/tcg',
44
language: ['c', 'cpp', 'objc'])
45
46
accelerators += 'CONFIG_TCG'
47
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/include/exec/helper-gen.h
50
+++ b/include/exec/helper-gen.h
51
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
52
#include "helper.h"
53
#include "trace/generated-helpers.h"
54
#include "trace/generated-helpers-wrappers.h"
55
-#include "tcg-runtime.h"
56
-#include "plugin-helpers.h"
57
+#include "accel/tcg/tcg-runtime.h"
58
+#include "accel/tcg/plugin-helpers.h"
59
60
#undef DEF_HELPER_FLAGS_0
61
#undef DEF_HELPER_FLAGS_1
62
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/exec/helper-proto.h
65
+++ b/include/exec/helper-proto.h
66
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
68
#include "helper.h"
69
#include "trace/generated-helpers.h"
70
-#include "tcg-runtime.h"
71
-#include "plugin-helpers.h"
72
+#include "accel/tcg/tcg-runtime.h"
73
+#include "accel/tcg/plugin-helpers.h"
74
75
#undef IN_HELPER_PROTO
76
77
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
78
index XXXXXXX..XXXXXXX 100644
79
--- a/include/exec/helper-tcg.h
80
+++ b/include/exec/helper-tcg.h
81
@@ -XXX,XX +XXX,XX @@
13
@@ -XXX,XX +XXX,XX @@
82
14
83
#include "helper.h"
15
#define CPU_SINGLE_STEP 0x1
84
#include "trace/generated-helpers.h"
16
#define CPU_BRANCH_STEP 0x2
85
-#include "tcg-runtime.h"
17
-#define GDBSTUB_SINGLE_STEP 0x4
86
-#include "plugin-helpers.h"
18
87
+#include "accel/tcg/tcg-runtime.h"
19
/* Include definitions for instructions classes and implementations flags */
88
+#include "accel/tcg/plugin-helpers.h"
20
/* #define PPC_DEBUG_DISAS */
89
21
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
90
#undef str
22
91
#undef DEF_HELPER_FLAGS_0
23
static void gen_debug_exception(DisasContext *ctx)
24
{
25
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
26
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
27
ctx->base.is_jmp = DISAS_NORETURN;
28
}
29
30
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
31
32
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
33
{
34
- int sse = ctx->singlestep_enabled;
35
- if (unlikely(sse)) {
36
- if (sse & GDBSTUB_SINGLE_STEP) {
37
- gen_debug_exception(ctx);
38
- } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
39
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
40
- } else {
41
- tcg_gen_exit_tb(NULL, 0);
42
- }
43
+ if (unlikely(ctx->singlestep_enabled)) {
44
+ gen_debug_exception(ctx);
45
} else {
46
tcg_gen_lookup_and_goto_ptr();
47
}
48
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
49
ctx->singlestep_enabled = 0;
50
if ((hflags >> HFLAGS_SE) & 1) {
51
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
52
+ ctx->base.max_insns = 1;
53
}
54
if ((hflags >> HFLAGS_BE) & 1) {
55
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
56
}
57
- if (unlikely(ctx->base.singlestep_enabled)) {
58
- ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
59
- }
60
-
61
- if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
62
- ctx->base.max_insns = 1;
63
- }
64
}
65
66
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
67
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
68
DisasContext *ctx = container_of(dcbase, DisasContext, base);
69
DisasJumpType is_jmp = ctx->base.is_jmp;
70
target_ulong nip = ctx->base.pc_next;
71
- int sse;
72
73
if (is_jmp == DISAS_NORETURN) {
74
/* We have already exited the TB. */
75
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
76
}
77
78
/* Honor single stepping. */
79
- sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
80
- if (unlikely(sse)) {
81
+ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
82
+ && (nip <= 0x100 || nip > 0xf00)) {
83
switch (is_jmp) {
84
case DISAS_TOO_MANY:
85
case DISAS_EXIT_UPDATE:
86
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
87
g_assert_not_reached();
88
}
89
90
- if (sse & GDBSTUB_SINGLE_STEP) {
91
- gen_debug_exception(ctx);
92
- return;
93
- }
94
- /* else CPU_SINGLE_STEP... */
95
- if (nip <= 0x100 || nip > 0xf00) {
96
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
97
- return;
98
- }
99
+ gen_debug_exception(ctx);
100
+ return;
101
}
102
103
switch (is_jmp) {
92
--
104
--
93
2.25.1
105
2.25.1
94
106
95
107
diff view generated by jsdifflib
New patch
[PULL 17/24] target/riscv: Remove dead code after exception
1
We have already set DISAS_NORETURN in generate_exception,
2
which makes the exit_tb unreachable.
1
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
8
1 file changed, 1 insertion(+), 5 deletions(-)
9
10
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/insn_trans/trans_privileged.c.inc
13
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
15
{
16
/* always generates U-level ECALL, fixed in do_interrupt handler */
17
generate_exception(ctx, RISCV_EXCP_U_ECALL);
18
- exit_tb(ctx); /* no chaining */
19
- ctx->base.is_jmp = DISAS_NORETURN;
20
return true;
21
}
22
23
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
24
post = opcode_at(&ctx->base, post_addr);
25
}
26
27
- if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
28
+ if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
29
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
30
} else {
31
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
32
}
33
- exit_tb(ctx); /* no chaining */
34
- ctx->base.is_jmp = DISAS_NORETURN;
35
return true;
36
}
37
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
New patch
[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr
1
GDB single-stepping is now handled generically, which means
2
we don't need to do anything in the wrappers.
1
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/riscv/translate.c | 27 +------------------
8
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
9
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
10
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
11
4 files changed, 7 insertions(+), 34 deletions(-)
12
13
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/translate.c
16
+++ b/target/riscv/translate.c
17
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
18
ctx->base.is_jmp = DISAS_NORETURN;
19
}
20
21
-static void gen_exception_debug(void)
22
-{
23
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
24
-}
25
-
26
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
27
-static void exit_tb(DisasContext *ctx)
28
-{
29
- if (ctx->base.singlestep_enabled) {
30
- gen_exception_debug();
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
-}
35
-
36
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
37
-static void lookup_and_goto_ptr(DisasContext *ctx)
38
-{
39
- if (ctx->base.singlestep_enabled) {
40
- gen_exception_debug();
41
- } else {
42
- tcg_gen_lookup_and_goto_ptr();
43
- }
44
-}
45
-
46
static void gen_exception_illegal(DisasContext *ctx)
47
{
48
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
49
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
50
tcg_gen_exit_tb(ctx->base.tb, n);
51
} else {
52
tcg_gen_movi_tl(cpu_pc, dest);
53
- lookup_and_goto_ptr(ctx);
54
+ tcg_gen_lookup_and_goto_ptr();
55
}
56
}
57
58
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/insn_trans/trans_privileged.c.inc
61
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
63
64
if (has_ext(ctx, RVS)) {
65
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
66
- exit_tb(ctx); /* no chaining */
67
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
68
ctx->base.is_jmp = DISAS_NORETURN;
69
} else {
70
return false;
71
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
72
#ifndef CONFIG_USER_ONLY
73
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
74
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
75
- exit_tb(ctx); /* no chaining */
76
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
77
ctx->base.is_jmp = DISAS_NORETURN;
78
return true;
79
#else
80
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/riscv/insn_trans/trans_rvi.c.inc
83
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
84
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
85
if (a->rd != 0) {
86
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
87
}
88
-
89
- /* No chaining with JALR. */
90
- lookup_and_goto_ptr(ctx);
91
+ tcg_gen_lookup_and_goto_ptr();
92
93
if (misaligned) {
94
gen_set_label(misaligned);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
96
* however we need to end the translation block
97
*/
98
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
99
- exit_tb(ctx);
100
+ tcg_gen_exit_tb(NULL, 0);
101
ctx->base.is_jmp = DISAS_NORETURN;
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
105
{
106
/* We may have changed important cpu state -- exit to main loop. */
107
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
108
- exit_tb(ctx);
109
+ tcg_gen_exit_tb(NULL, 0);
110
ctx->base.is_jmp = DISAS_NORETURN;
111
return true;
112
}
113
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/riscv/insn_trans/trans_rvv.c.inc
116
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
117
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
118
gen_set_gpr(ctx, a->rd, dst);
119
120
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
121
- lookup_and_goto_ptr(ctx);
122
+ tcg_gen_lookup_and_goto_ptr();
123
ctx->base.is_jmp = DISAS_NORETURN;
124
return true;
125
}
126
--
127
2.25.1
128
129
diff view generated by jsdifflib
New patch
[PULL 19/24] target/rx: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/rx/helper.h | 1 -
7
target/rx/op_helper.c | 8 --------
8
target/rx/translate.c | 12 ++----------
9
3 files changed, 2 insertions(+), 19 deletions(-)
10
11
diff --git a/target/rx/helper.h b/target/rx/helper.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/rx/helper.h
14
+++ b/target/rx/helper.h
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
16
DEF_HELPER_1(raise_access_fault, noreturn, env)
17
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
18
DEF_HELPER_1(wait, noreturn, env)
19
-DEF_HELPER_1(debug, noreturn, env)
20
DEF_HELPER_2(rxint, noreturn, env, i32)
21
DEF_HELPER_1(rxbrk, noreturn, env)
22
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
23
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/rx/op_helper.c
26
+++ b/target/rx/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
28
raise_exception(env, EXCP_HLT, 0);
29
}
30
31
-void QEMU_NORETURN helper_debug(CPURXState *env)
32
-{
33
- CPUState *cs = env_cpu(env);
34
-
35
- cs->exception_index = EXCP_DEBUG;
36
- cpu_loop_exit(cs);
37
-}
38
-
39
void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
40
{
41
raise_exception(env, 0x100 + vec, 0);
42
diff --git a/target/rx/translate.c b/target/rx/translate.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/rx/translate.c
45
+++ b/target/rx/translate.c
46
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
47
tcg_gen_exit_tb(dc->base.tb, n);
48
} else {
49
tcg_gen_movi_i32(cpu_pc, dest);
50
- if (dc->base.singlestep_enabled) {
51
- gen_helper_debug(cpu_env);
52
- } else {
53
- tcg_gen_lookup_and_goto_ptr();
54
- }
55
+ tcg_gen_lookup_and_goto_ptr();
56
}
57
dc->base.is_jmp = DISAS_NORETURN;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
60
gen_goto_tb(ctx, 0, dcbase->pc_next);
61
break;
62
case DISAS_JUMP:
63
- if (ctx->base.singlestep_enabled) {
64
- gen_helper_debug(cpu_env);
65
- } else {
66
- tcg_gen_lookup_and_goto_ptr();
67
- }
68
+ tcg_gen_lookup_and_goto_ptr();
69
break;
70
case DISAS_UPDATE:
71
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
72
--
73
2.25.1
74
75
diff view generated by jsdifflib
New patch
[PULL 20/24] target/s390x: Drop check for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/s390x/tcg/translate.c | 8 ++------
6
1 file changed, 2 insertions(+), 6 deletions(-)
7
8
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/s390x/tcg/translate.c
11
+++ b/target/s390x/tcg/translate.c
12
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
13
uint64_t pc_tmp;
14
uint32_t ilen;
15
enum cc_op cc_op;
16
- bool do_debug;
17
};
18
19
/* Information carried about a condition to be evaluated. */
20
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
21
22
dc->cc_op = CC_OP_DYNAMIC;
23
dc->ex_value = dc->base.tb->cs_base;
24
- dc->do_debug = dc->base.singlestep_enabled;
25
}
26
27
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
28
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
/* FALLTHRU */
30
case DISAS_PC_CC_UPDATED:
31
/* Exit the TB, either by raising a debug exception or by return. */
32
- if (dc->do_debug) {
33
- gen_exception(EXCP_DEBUG);
34
- } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
35
- dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
36
+ if ((dc->base.tb->flags & FLAG_MASK_PER) ||
37
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
38
tcg_gen_exit_tb(NULL, 0);
39
} else {
40
tcg_gen_lookup_and_goto_ptr();
41
--
42
2.25.1
43
44
diff view generated by jsdifflib
[PULL 4/5] decodetree: Add support for 64-bit instructions
[PULL 21/24] target/sh4: Drop check for singlestep_enabled
1
From: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>
1
GDB single-stepping is now handled generically.
2
3
Allow '64' to be specified for the instruction width command line params
4
and use the appropriate extract and deposit functions in that case.
5
6
This will be used to implement the new 64-bit Power ISA 3.1 instructions.
7
2
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
10
Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com>
11
[rth: Drop the change to the field type; use bitop_width instead of separate
12
variables for extract/deposit; use "ull" for 64-bit constants.]
13
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
5
---
16
scripts/decodetree.py | 21 ++++++++++++++-------
6
target/sh4/helper.h | 1 -
17
1 file changed, 14 insertions(+), 7 deletions(-)
7
target/sh4/op_helper.c | 5 -----
8
target/sh4/translate.c | 14 +++-----------
9
3 files changed, 3 insertions(+), 17 deletions(-)
18
10
19
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
11
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/scripts/decodetree.py
13
--- a/target/sh4/helper.h
22
+++ b/scripts/decodetree.py
14
+++ b/target/sh4/helper.h
23
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
24
import getopt
16
DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
25
17
DEF_HELPER_1(raise_fpu_disable, noreturn, env)
26
insnwidth = 32
18
DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
27
+bitop_width = 32
19
-DEF_HELPER_1(debug, noreturn, env)
28
insnmask = 0xffffffff
20
DEF_HELPER_1(sleep, noreturn, env)
29
variablewidth = False
21
DEF_HELPER_2(trapa, noreturn, env, i32)
30
fields = {}
22
DEF_HELPER_1(exclusive, noreturn, env)
31
@@ -XXX,XX +XXX,XX @@ def whexC(val):
23
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
32
"""Return a hex string for val padded for insnwidth,
24
index XXXXXXX..XXXXXXX 100644
33
and with the proper suffix for a C constant."""
25
--- a/target/sh4/op_helper.c
34
suffix = ''
26
+++ b/target/sh4/op_helper.c
35
- if val >= 0x80000000:
27
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
36
+ if val >= 0x100000000:
28
raise_exception(env, 0x820, 0);
37
+ suffix = 'ull'
29
}
38
+ elif val >= 0x80000000:
30
39
suffix = 'u'
31
-void helper_debug(CPUSH4State *env)
40
return whex(val) + suffix
32
-{
41
33
- raise_exception(env, EXCP_DEBUG, 0);
42
@@ -XXX,XX +XXX,XX @@ def __str__(self):
34
-}
43
return str(self.pos) + ':' + s + str(self.len)
35
-
44
36
void helper_sleep(CPUSH4State *env)
45
def str_extract(self):
37
{
46
- if self.sign:
38
CPUState *cs = env_cpu(env);
47
- extr = 'sextract32'
39
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
48
- else:
40
index XXXXXXX..XXXXXXX 100644
49
- extr = 'extract32'
41
--- a/target/sh4/translate.c
50
- return f'{extr}(insn, {self.pos}, {self.len})'
42
+++ b/target/sh4/translate.c
51
+ global bitop_width
43
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
52
+ s = 's' if self.sign else ''
44
tcg_gen_exit_tb(ctx->base.tb, n);
53
+ return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
45
} else {
54
46
tcg_gen_movi_i32(cpu_pc, dest);
55
def __eq__(self, other):
47
- if (ctx->base.singlestep_enabled) {
56
return self.sign == other.sign and self.mask == other.mask
48
- gen_helper_debug(cpu_env);
57
@@ -XXX,XX +XXX,XX @@ def __str__(self):
49
- } else if (use_exit_tb(ctx)) {
58
return str(self.subs)
50
+ if (use_exit_tb(ctx)) {
59
51
tcg_gen_exit_tb(NULL, 0);
60
def str_extract(self):
52
} else {
61
+ global bitop_width
53
tcg_gen_lookup_and_goto_ptr();
62
ret = '0'
54
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
63
pos = 0
55
     delayed jump as immediate jump are conditinal jumps */
64
for f in reversed(self.subs):
56
    tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
65
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
57
tcg_gen_discard_i32(cpu_delayed_pc);
66
if pos == 0:
58
- if (ctx->base.singlestep_enabled) {
67
ret = ext
59
- gen_helper_debug(cpu_env);
68
else:
60
- } else if (use_exit_tb(ctx)) {
69
- ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
61
+ if (use_exit_tb(ctx)) {
70
+ ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
62
tcg_gen_exit_tb(NULL, 0);
71
pos += f.len
63
} else {
72
return ret
64
tcg_gen_lookup_and_goto_ptr();
73
65
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
74
@@ -XXX,XX +XXX,XX @@ def main():
66
switch (ctx->base.is_jmp) {
75
global insntype
67
case DISAS_STOP:
76
global insnmask
68
gen_save_cpu_state(ctx, true);
77
global decode_function
69
- if (ctx->base.singlestep_enabled) {
78
+ global bitop_width
70
- gen_helper_debug(cpu_env);
79
global variablewidth
71
- } else {
80
global anyextern
72
- tcg_gen_exit_tb(NULL, 0);
81
73
- }
82
@@ -XXX,XX +XXX,XX @@ def main():
74
+ tcg_gen_exit_tb(NULL, 0);
83
if insnwidth == 16:
75
break;
84
insntype = 'uint16_t'
76
case DISAS_NEXT:
85
insnmask = 0xffff
77
case DISAS_TOO_MANY:
86
+ elif insnwidth == 64:
87
+ insntype = 'uint64_t'
88
+ insnmask = 0xffffffffffffffff
89
+ bitop_width = 64
90
elif insnwidth != 32:
91
error(0, 'cannot handle insns of width', insnwidth)
92
else:
93
--
78
--
94
2.25.1
79
2.25.1
95
80
96
81
diff view generated by jsdifflib
[PULL 5/5] decodetree: Extend argument set syntax to allow types
[PULL 22/24] target/tricore: Drop check for singlestep_enabled
1
Rather than force all structure members to be 'int',
1
GDB single-stepping is now handled generically.
2
allow the type of the member to be specified.
3
2
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
docs/devel/decodetree.rst | 11 ++++---
6
target/tricore/helper.h | 1 -
8
tests/decode/succ_argset_type1.decode | 1 +
7
target/tricore/op_helper.c | 7 -------
9
scripts/decodetree.py | 45 +++++++++++++++++----------
8
target/tricore/translate.c | 14 +-------------
10
3 files changed, 36 insertions(+), 21 deletions(-)
9
3 files changed, 1 insertion(+), 21 deletions(-)
11
create mode 100644 tests/decode/succ_argset_type1.decode
12
10
13
diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
11
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/devel/decodetree.rst
13
--- a/target/tricore/helper.h
16
+++ b/docs/devel/decodetree.rst
14
+++ b/target/tricore/helper.h
17
@@ -XXX,XX +XXX,XX @@ and returns an integral value extracted from there.
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
18
16
DEF_HELPER_1(psw_read, i32, env)
19
A field with no ``unnamed_fields`` and no ``!function`` is in error.
17
/* Exceptions */
20
18
DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
21
-FIXME: the fields of the structure into which this result will be stored
19
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
22
-is restricted to ``int``. Which means that we cannot expand 64-bit items.
20
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/tricore/op_helper.c
23
+++ b/target/tricore/op_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
25
raise_exception_sync_internal(env, class, tin, pc, 0);
26
}
27
28
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
29
-{
30
- CPUState *cs = env_cpu(env);
31
- cs->exception_index = excp;
32
- cpu_loop_exit(cs);
33
-}
23
-
34
-
24
Field examples:
35
/* Addressing mode helper */
25
36
26
+---------------------------+---------------------------------------------+
37
static uint16_t reverse16(uint16_t val)
27
@@ -XXX,XX +XXX,XX @@ Argument Sets
38
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
28
Syntax::
29
30
args_def := '&' identifier ( args_elt )+ ( !extern )?
31
- args_elt := identifier
32
+ args_elt := identifier (':' identifier)?
33
34
Each *args_elt* defines an argument within the argument set.
35
+If the form of the *args_elt* contains a colon, the first
36
+identifier is the argument name and the second identifier is
37
+the argument type. If the colon is missing, the argument
38
+type will be ``int``.
39
+
40
Each argument set will be rendered as a C structure "arg_$name"
41
with each of the fields being one of the member arguments.
42
43
@@ -XXX,XX +XXX,XX @@ Argument set examples::
44
45
&reg3 ra rb rc
46
&loadstore reg base offset
47
+ &longldst reg base offset:int64_t
48
49
50
Formats
51
diff --git a/tests/decode/succ_argset_type1.decode b/tests/decode/succ_argset_type1.decode
52
new file mode 100644
53
index XXXXXXX..XXXXXXX
54
--- /dev/null
55
+++ b/tests/decode/succ_argset_type1.decode
56
@@ -0,0 +1 @@
57
+&asdf b:bool c:uint64_t a
58
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
59
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
60
--- a/scripts/decodetree.py
40
--- a/target/tricore/translate.c
61
+++ b/scripts/decodetree.py
41
+++ b/target/tricore/translate.c
62
@@ -XXX,XX +XXX,XX @@ def is_contiguous(bits):
42
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
63
return -1
43
tcg_gen_movi_tl(cpu_PC, pc);
64
44
}
65
45
66
-def eq_fields_for_args(flds_a, flds_b):
46
-static void generate_qemu_excp(DisasContext *ctx, int excp)
67
- if len(flds_a) != len(flds_b):
47
-{
68
+def eq_fields_for_args(flds_a, arg):
48
- TCGv_i32 tmp = tcg_const_i32(excp);
69
+ if len(flds_a) != len(arg.fields):
49
- gen_helper_qemu_excp(cpu_env, tmp);
70
return False
50
- ctx->base.is_jmp = DISAS_NORETURN;
71
+ # Only allow inference on default types
51
- tcg_temp_free(tmp);
72
+ for t in arg.types:
52
-}
73
+ if t != 'int':
53
-
74
+ return False
54
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
75
for k, a in flds_a.items():
55
{
76
- if k not in flds_b:
56
if (translator_use_goto_tb(&ctx->base, dest)) {
77
+ if k not in arg.fields:
57
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
78
return False
58
tcg_gen_exit_tb(ctx->base.tb, n);
79
return True
59
} else {
80
60
gen_save_pc(dest);
81
@@ -XXX,XX +XXX,XX @@ def __ne__(self, other):
61
- if (ctx->base.singlestep_enabled) {
82
62
- generate_qemu_excp(ctx, EXCP_DEBUG);
83
class Arguments:
63
- } else {
84
"""Class representing the extracted fields of a format"""
64
- tcg_gen_lookup_and_goto_ptr();
85
- def __init__(self, nm, flds, extern):
65
- }
86
+ def __init__(self, nm, flds, types, extern):
66
+ tcg_gen_lookup_and_goto_ptr();
87
self.name = nm
67
}
88
self.extern = extern
68
}
89
- self.fields = sorted(flds)
90
+ self.fields = flds
91
+ self.types = types
92
93
def __str__(self):
94
return self.name + ' ' + str(self.fields)
95
@@ -XXX,XX +XXX,XX @@ def struct_name(self):
96
def output_def(self):
97
if not self.extern:
98
output('typedef struct {\n')
99
- for n in self.fields:
100
- output(' int ', n, ';\n')
101
+ for (n, t) in zip(self.fields, self.types):
102
+ output(f' {t} {n};\n')
103
output('} ', self.struct_name(), ';\n\n')
104
# end Arguments
105
106
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
107
global anyextern
108
109
flds = []
110
+ types = []
111
extern = False
112
- for t in toks:
113
- if re.fullmatch('!extern', t):
114
+ for n in toks:
115
+ if re.fullmatch('!extern', n):
116
extern = True
117
anyextern = True
118
continue
119
- if not re.fullmatch(re_C_ident, t):
120
- error(lineno, f'invalid argument set token "{t}"')
121
- if t in flds:
122
- error(lineno, f'duplicate argument "{t}"')
123
- flds.append(t)
124
+ if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
125
+ (n, t) = n.split(':')
126
+ elif re.fullmatch(re_C_ident, n):
127
+ t = 'int'
128
+ else:
129
+ error(lineno, f'invalid argument set token "{n}"')
130
+ if n in flds:
131
+ error(lineno, f'duplicate argument "{n}"')
132
+ flds.append(n)
133
+ types.append(t)
134
135
if name in arguments:
136
error(lineno, 'duplicate argument set', name)
137
- arguments[name] = Arguments(name, flds, extern)
138
+ arguments[name] = Arguments(name, flds, types, extern)
139
# end parse_arguments
140
141
142
@@ -XXX,XX +XXX,XX @@ def infer_argument_set(flds):
143
global decode_function
144
145
for arg in arguments.values():
146
- if eq_fields_for_args(flds, arg.fields):
147
+ if eq_fields_for_args(flds, arg):
148
return arg
149
150
name = decode_function + str(len(arguments))
151
- arg = Arguments(name, flds.keys(), False)
152
+ arg = Arguments(name, flds.keys(), ['int'] * len(flds), False)
153
arguments[name] = arg
154
return arg
155
69
156
--
70
--
157
2.25.1
71
2.25.1
158
72
159
73
diff view generated by jsdifflib
[PULL 3/5] decodetree: More use of f-strings
[PULL 23/24] target/xtensa: Drop check for singlestep_enabled
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
1
GDB single-stepping is now handled generically.
2
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
---
4
scripts/decodetree.py | 50 ++++++++++++++++++++-----------------------
5
target/xtensa/translate.c | 25 ++++++++-----------------
5
1 file changed, 23 insertions(+), 27 deletions(-)
6
1 file changed, 8 insertions(+), 17 deletions(-)
6
7
7
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
8
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
8
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
9
--- a/scripts/decodetree.py
10
--- a/target/xtensa/translate.c
10
+++ b/scripts/decodetree.py
11
+++ b/target/xtensa/translate.c
11
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
12
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
12
13
if (dc->icount) {
13
prefix = ''
14
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
14
if file:
15
}
15
- prefix += '{0}:'.format(file)
16
- if (dc->base.singlestep_enabled) {
16
+ prefix += f'{file}:'
17
- gen_exception(dc, EXCP_DEBUG);
17
if lineno:
18
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
18
- prefix += '{0}:'.format(lineno)
19
+ slot = gen_postprocess(dc, slot);
19
+ prefix += f'{lineno}:'
20
+ }
20
if prefix:
21
+ if (slot >= 0) {
21
prefix += ' '
22
+ tcg_gen_goto_tb(slot);
22
print(prefix, end='error: ', file=sys.stderr)
23
+ tcg_gen_exit_tb(dc->base.tb, slot);
23
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
24
} else {
24
extr = 'sextract32'
25
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
25
else:
26
- slot = gen_postprocess(dc, slot);
26
extr = 'extract32'
27
- }
27
- return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
28
- if (slot >= 0) {
28
+ return f'{extr}(insn, {self.pos}, {self.len})'
29
- tcg_gen_goto_tb(slot);
29
30
- tcg_gen_exit_tb(dc->base.tb, slot);
30
def __eq__(self, other):
31
- } else {
31
return self.sign == other.sign and self.mask == other.mask
32
- tcg_gen_exit_tb(NULL, 0);
32
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
33
- }
33
ret = '0'
34
+ tcg_gen_exit_tb(NULL, 0);
34
pos = 0
35
}
35
for f in reversed(self.subs):
36
dc->base.is_jmp = DISAS_NORETURN;
36
+ ext = f.str_extract()
37
}
37
if pos == 0:
38
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
38
- ret = f.str_extract()
39
case DISAS_NORETURN:
39
+ ret = ext
40
break;
40
else:
41
case DISAS_TOO_MANY:
41
- ret = 'deposit32({0}, {1}, {2}, {3})' \
42
- if (dc->base.singlestep_enabled) {
42
- .format(ret, pos, 32 - pos, f.str_extract())
43
- tcg_gen_movi_i32(cpu_pc, dc->pc);
43
+ ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
44
- gen_exception(dc, EXCP_DEBUG);
44
pos += f.len
45
- } else {
45
return ret
46
- gen_jumpi(dc, dc->pc, 0);
46
47
- }
47
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
48
+ gen_jumpi(dc, dc->pc, 0);
48
subtoks = t.split(':')
49
break;
49
sign = False
50
default:
50
else:
51
g_assert_not_reached();
51
- error(lineno, 'invalid field token "{0}"'.format(t))
52
+ error(lineno, f'invalid field token "{t}"')
53
po = int(subtoks[0])
54
le = int(subtoks[1])
55
if po + le > insnwidth:
56
- error(lineno, 'field {0} too large'.format(t))
57
+ error(lineno, f'field {t} too large')
58
f = Field(sign, po, le)
59
subs.append(f)
60
width += le
61
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
62
anyextern = True
63
continue
64
if not re.fullmatch(re_C_ident, t):
65
- error(lineno, 'invalid argument set token "{0}"'.format(t))
66
+ error(lineno, f'invalid argument set token "{t}"')
67
if t in flds:
68
- error(lineno, 'duplicate argument "{0}"'.format(t))
69
+ error(lineno, f'duplicate argument "{t}"')
70
flds.append(t)
71
72
if name in arguments:
73
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
74
flen = flen[1:]
75
shift = int(flen, 10)
76
if shift + width > insnwidth:
77
- error(lineno, 'field {0} exceeds insnwidth'.format(fname))
78
+ error(lineno, f'field {fname} exceeds insnwidth')
79
f = Field(sign, insnwidth - width - shift, shift)
80
flds = add_field(lineno, flds, fname, f)
81
fixedbits <<= shift
82
fixedmask <<= shift
83
undefmask <<= shift
84
else:
85
- error(lineno, 'invalid token "{0}"'.format(t))
86
+ error(lineno, f'invalid token "{t}"')
87
width += shift
88
89
if variablewidth and width < insnwidth and width % 8 == 0:
90
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
91
92
# We should have filled in all of the bits of the instruction.
93
elif not (is_format and width == 0) and width != insnwidth:
94
- error(lineno, 'definition has {0} bits'.format(width))
95
+ error(lineno, f'definition has {width} bits')
96
97
# Do not check for fields overlapping fields; one valid usage
98
# is to be able to duplicate fields via import.
99
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
100
if arg:
101
for f in flds.keys():
102
if f not in arg.fields:
103
- error(lineno, 'field {0} not in argument set {1}'
104
- .format(f, arg.name))
105
+ error(lineno, f'field {f} not in argument set {arg.name}')
106
else:
107
arg = infer_argument_set(flds)
108
if name in formats:
109
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
110
arg = fmt.base
111
for f in flds.keys():
112
if f not in arg.fields:
113
- error(lineno, 'field {0} not in argument set {1}'
114
- .format(f, arg.name))
115
+ error(lineno, f'field {f} not in argument set {arg.name}')
116
if f in fmt.fields.keys():
117
- error(lineno, 'field {0} set by format and pattern'.format(f))
118
+ error(lineno, f'field {f} set by format and pattern')
119
for f in arg.fields:
120
if f not in flds.keys() and f not in fmt.fields.keys():
121
- error(lineno, 'field {0} not initialized'.format(f))
122
+ error(lineno, f'field {f} not initialized')
123
pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
124
undefmask, fieldmask, flds, width)
125
parent_pat.pats.append(pat)
126
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
127
elif re.fullmatch(re_pat_ident, name):
128
parse_generic(start_lineno, parent_pat, name, toks)
129
else:
130
- error(lineno, 'invalid token "{0}"'.format(name))
131
+ error(lineno, f'invalid token "{name}"')
132
toks = []
133
134
if nesting != 0:
135
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
136
137
# If we need to load more bytes to test, do so now.
138
if extracted < self.width:
139
- output(ind, 'insn = ', decode_function,
140
- '_load_bytes(ctx, insn, {0}, {1});\n'
141
- .format(extracted // 8, self.width // 8));
142
+ output(ind, f'insn = {decode_function}_load_bytes',
143
+ f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
144
extracted = self.width
145
146
# Attempt to aid the compiler in producing compact switch statements.
147
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
148
149
# If we need to load more bytes, do so now.
150
if extracted < self.width:
151
- output(ind, 'insn = ', decode_function,
152
- '_load_bytes(ctx, insn, {0}, {1});\n'
153
- .format(extracted // 8, self.width // 8));
154
+ output(ind, f'insn = {decode_function}_load_bytes',
155
+ f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
156
extracted = self.width
157
output(ind, 'return insn;\n')
158
# end SizeLeaf
159
@@ -XXX,XX +XXX,XX @@ def build_size_tree(pats, width, outerbits, outermask):
160
for p in pats:
161
pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
162
error_with_file(pats[0].file, pats[0].lineno,
163
- 'overlapping patterns size {0}:'.format(width), pnames)
164
+ f'overlapping patterns size {width}:', pnames)
165
166
bins = {}
167
for i in pats:
168
--
52
--
169
2.25.1
53
2.25.1
170
54
171
55
diff view generated by jsdifflib
[PULL 2/5] decodetree: Introduce whex and whexC helpers
[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
1
Form a hex constant of the appropriate insnwidth.
1
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
2
Begin using f-strings on changed lines.
3
2
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Despite a comment saying why cpu_common_props cannot be placed in
4
a file that is compiled once, it was moved anyway. Revert that.
5
6
Since then, Property is not defined in hw/core/cpu.h, so it is now
7
easier to declare a function to install the properties rather than
8
the Property array itself.
9
10
Cc: Eduardo Habkost <ehabkost@redhat.com>
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
13
---
7
scripts/decodetree.py | 66 +++++++++++++++++++++++++------------------
14
include/hw/core/cpu.h | 1 +
8
1 file changed, 38 insertions(+), 28 deletions(-)
15
cpu.c | 21 +++++++++++++++++++++
16
hw/core/cpu-common.c | 17 +----------------
17
3 files changed, 23 insertions(+), 16 deletions(-)
9
18
10
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
11
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
12
--- a/scripts/decodetree.py
21
--- a/include/hw/core/cpu.h
13
+++ b/scripts/decodetree.py
22
+++ b/include/hw/core/cpu.h
14
@@ -XXX,XX +XXX,XX @@ def str_fields(fields):
23
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
15
return r[1:]
24
GCC_FMT_ATTR(2, 3);
16
25
17
26
/* $(top_srcdir)/cpu.c */
18
+def whex(val):
27
+void cpu_class_init_props(DeviceClass *dc);
19
+ """Return a hex string for val padded for insnwidth"""
28
void cpu_exec_initfn(CPUState *cpu);
20
+ global insnwidth
29
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
21
+ return f'0x{val:0{insnwidth // 4}x}'
30
void cpu_exec_unrealizefn(CPUState *cpu);
31
diff --git a/cpu.c b/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/cpu.c
34
+++ b/cpu.c
35
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
36
cpu_list_remove(cpu);
37
}
38
39
+static Property cpu_common_props[] = {
40
+#ifndef CONFIG_USER_ONLY
41
+ /*
42
+ * Create a memory property for softmmu CPU object,
43
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
44
+ * because that file is compiled only once for both user-mode
45
+ * and system builds.) The default if no link is set up is to use
46
+ * the system address space.
47
+ */
48
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
49
+ MemoryRegion *),
50
+#endif
51
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
52
+ DEFINE_PROP_END_OF_LIST(),
53
+};
22
+
54
+
55
+void cpu_class_init_props(DeviceClass *dc)
56
+{
57
+ device_class_set_props(dc, cpu_common_props);
58
+}
23
+
59
+
24
+def whexC(val):
60
void cpu_exec_initfn(CPUState *cpu)
25
+ """Return a hex string for val padded for insnwidth,
61
{
26
+ and with the proper suffix for a C constant."""
62
cpu->as = NULL;
27
+ suffix = ''
63
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
28
+ if val >= 0x80000000:
64
index XXXXXXX..XXXXXXX 100644
29
+ suffix = 'u'
65
--- a/hw/core/cpu-common.c
30
+ return whex(val) + suffix
66
+++ b/hw/core/cpu-common.c
31
+
67
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
32
+
68
return cpu->cpu_index;
33
def str_match_bits(bits, mask):
69
}
34
"""Return a string pretty-printing BITS/MASK"""
70
35
global insnwidth
71
-static Property cpu_common_props[] = {
36
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
72
-#ifndef CONFIG_USER_ONLY
37
if outermask != p.fixedmask:
73
- /* Create a memory property for softmmu CPU object,
38
innermask = p.fixedmask & ~outermask
74
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
39
innerbits = p.fixedbits & ~outermask
75
- * because that file is compiled only once for both user-mode
40
- output(ind, 'if ((insn & ',
76
- * and system builds.) The default if no link is set up is to use
41
- '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits),
77
- * the system address space.
42
- ') {\n')
78
- */
43
- output(ind, ' /* ',
79
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
44
- str_match_bits(p.fixedbits, p.fixedmask), ' */\n')
80
- MemoryRegion *),
45
+ output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
81
-#endif
46
+ output(ind, f' /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
82
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
47
p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
83
- DEFINE_PROP_END_OF_LIST(),
48
output(ind, '}\n')
84
-};
49
else:
85
-
50
@@ -XXX,XX +XXX,XX @@ def __init__(self, fm, tm):
86
static void cpu_class_init(ObjectClass *klass, void *data)
51
87
{
52
def str1(self, i):
88
DeviceClass *dc = DEVICE_CLASS(klass);
53
ind = str_indent(i)
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
54
- r = '{0}{1:08x}'.format(ind, self.fixedmask)
90
dc->realize = cpu_common_realizefn;
55
+ r = ind + whex(self.fixedmask)
91
dc->unrealize = cpu_common_unrealizefn;
56
if self.format:
92
dc->reset = cpu_common_reset;
57
r += ' ' + self.format.name
93
- device_class_set_props(dc, cpu_common_props);
58
r += ' [\n'
94
+ cpu_class_init_props(dc);
59
for (b, s) in self.subs:
95
/*
60
- r += '{0} {1:08x}:\n'.format(ind, b)
96
* Reason: CPUs still need special care by board code: wiring up
61
+ r += ind + f' {whex(b)}:\n'
97
* IRQs, adding reset handlers, halting non-first CPUs, ...
62
r += s.str1(i + 4) + '\n'
63
r += ind + ']'
64
return r
65
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
66
if sh > 0:
67
# Propagate SH down into the local functions.
68
def str_switch(b, sh=sh):
69
- return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
70
+ return f'(insn >> {sh}) & {b >> sh:#x}'
71
72
def str_case(b, sh=sh):
73
- return '0x{0:x}'.format(b >> sh)
74
+ return hex(b >> sh)
75
else:
76
def str_switch(b):
77
- return 'insn & 0x{0:08x}'.format(b)
78
+ return f'insn & {whexC(b)}'
79
80
def str_case(b):
81
- return '0x{0:08x}'.format(b)
82
+ return whexC(b)
83
84
output(ind, 'switch (', str_switch(self.thismask), ') {\n')
85
for b, s in sorted(self.subs):
86
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
87
88
# Validate the masks that we have assembled.
89
if fieldmask & fixedmask:
90
- error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})'
91
- .format(fieldmask, fixedmask))
92
+ error(lineno, 'fieldmask overlaps fixedmask ',
93
+ f'({whex(fieldmask)} & {whex(fixedmask)})')
94
if fieldmask & undefmask:
95
- error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
96
- .format(fieldmask, undefmask))
97
+ error(lineno, 'fieldmask overlaps undefmask ',
98
+ f'({whex(fieldmask)} & {whex(undefmask)})')
99
if fixedmask & undefmask:
100
- error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
101
- .format(fixedmask, undefmask))
102
+ error(lineno, 'fixedmask overlaps undefmask ',
103
+ f'({whex(fixedmask)} & {whex(undefmask)})')
104
if not is_format:
105
allbits = fieldmask | fixedmask | undefmask
106
if allbits != insnmask:
107
- error(lineno, 'bits left unspecified (0x{0:08x})'
108
- .format(allbits ^ insnmask))
109
+ error(lineno, 'bits left unspecified ',
110
+ f'({whex(allbits ^ insnmask)})')
111
# end parse_general
112
113
114
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
115
116
def str1(self, i):
117
ind = str_indent(i)
118
- r = '{0}{1:08x}'.format(ind, self.mask)
119
- r += ' [\n'
120
+ r = ind + whex(self.mask) + ' [\n'
121
for (b, s) in self.subs:
122
- r += '{0} {1:08x}:\n'.format(ind, b)
123
+ r += ind + f' {whex(b)}:\n'
124
r += s.str1(i + 4) + '\n'
125
r += ind + ']'
126
return r
127
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
128
if sh > 0:
129
# Propagate SH down into the local functions.
130
def str_switch(b, sh=sh):
131
- return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
132
+ return f'(insn >> {sh}) & {b >> sh:#x}'
133
134
def str_case(b, sh=sh):
135
- return '0x{0:x}'.format(b >> sh)
136
+ return hex(b >> sh)
137
else:
138
def str_switch(b):
139
- return 'insn & 0x{0:08x}'.format(b)
140
+ return f'insn & {whexC(b)}'
141
142
def str_case(b):
143
- return '0x{0:08x}'.format(b)
144
+ return whexC(b)
145
146
output(ind, 'switch (', str_switch(self.mask), ') {\n')
147
for b, s in sorted(self.subs):
148
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
149
self.width = w
150
151
def str1(self, i):
152
- ind = str_indent(i)
153
- return '{0}{1:08x}'.format(ind, self.mask)
154
+ return str_indent(i) + whex(self.mask)
155
156
def __str__(self):
157
return self.str1(0)
158
--
98
--
159
2.25.1
99
2.25.1
160
100
161
101
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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