[PULL 0/5] tcg patch queue
[PULL 00/31] tcg patch queue
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The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
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The following changes since commit 0319ad22bd5789e1eaa8a2dd5773db2d2c372f20:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)
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Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging (2021-05-25 17:31:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210526
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for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:
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for you to fetch changes up to 119065574d02deffc28fe5b6a864db9b467c6ffd:
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decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)
11
hw/core: Constify TCGCPUOps (2021-05-26 15:33:59 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Include cleanups.
14
Adjust types for some memory access functions.
15
Decodetree enhancements for power10.
15
Reduce inclusion of tcg headers.
16
Fix watchpoints vs replay.
17
Fix tcg/aarch64 roli expansion.
18
Introduce SysemuCPUOps structure.
16
19
17
----------------------------------------------------------------
20
----------------------------------------------------------------
18
Luis Fernando Fujita Pires (1):
21
Pavel Dovgalyuk (1):
19
decodetree: Add support for 64-bit instructions
22
replay: fix watchpoint processing for reverse debugging
20
23
21
Philippe Mathieu-Daudé (1):
24
Philippe Mathieu-Daudé (27):
22
exec: Remove accel/tcg/ from include paths
25
exec/memory_ldst_cached: Sort declarations
26
exec/memory_ldst_phys: Sort declarations
27
exec/memory_ldst: Use correct type sizes
28
exec/memory_ldst_phys: Use correct type sizes
29
exec/memory_ldst_cached: Use correct type size
30
exec/memory: Use correct type size
31
accel/tcg: Reduce 'exec/tb-context.h' inclusion
32
accel/tcg: Keep TranslationBlock headers local to TCG
33
cpu: Remove duplicated 'sysemu/hw_accel.h' header
34
cpu: Split as cpu-common / cpu-sysemu
35
cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
36
cpu: Introduce cpu_virtio_is_big_endian()
37
cpu: Directly use cpu_write_elf*() fallback handlers in place
38
cpu: Directly use get_paging_enabled() fallback handlers in place
39
cpu: Directly use get_memory_mapping() fallback handlers in place
40
cpu: Assert DeviceClass::vmsd is NULL on user emulation
41
cpu: Rename CPUClass vmsd -> legacy_vmsd
42
cpu: Move AVR target vmsd field from CPUClass to DeviceClass
43
cpu: Introduce SysemuCPUOps structure
44
cpu: Move CPUClass::vmsd to SysemuCPUOps
45
cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
46
cpu: Move CPUClass::get_crash_info to SysemuCPUOps
47
cpu: Move CPUClass::write_elf* to SysemuCPUOps
48
cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
49
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
50
cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
51
cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
23
52
24
Richard Henderson (3):
53
Richard Henderson (2):
25
decodetree: Introduce whex and whexC helpers
54
target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
26
decodetree: More use of f-strings
55
hw/core: Constify TCGCPUOps
27
decodetree: Extend argument set syntax to allow types
28
56
29
docs/devel/decodetree.rst | 11 ++-
57
Yasuo Kuwahara (1):
30
meson.build | 1 -
58
tcg/aarch64: Fix tcg_out_rotl
31
include/exec/helper-gen.h | 4 +-
32
include/exec/helper-proto.h | 4 +-
33
include/exec/helper-tcg.h | 4 +-
34
tests/decode/succ_argset_type1.decode | 1 +
35
scripts/decodetree.py | 172 +++++++++++++++++++---------------
36
7 files changed, 112 insertions(+), 85 deletions(-)
37
create mode 100644 tests/decode/succ_argset_type1.decode
38
59
60
{include/exec => accel/tcg}/tb-context.h | 0
61
{include/exec => accel/tcg}/tb-hash.h | 0
62
{include/exec => accel/tcg}/tb-lookup.h | 2 +-
63
include/exec/exec-all.h | 1 -
64
include/exec/memory.h | 2 +-
65
include/hw/core/cpu.h | 94 +++++---------------
66
include/hw/core/sysemu-cpu-ops.h | 92 ++++++++++++++++++++
67
include/migration/vmstate.h | 2 -
68
include/tcg/tcg.h | 1 -
69
plugins/plugin.h | 1 +
70
target/mips/cpu-qom.h | 3 +
71
include/exec/memory_ldst.h.inc | 16 ++--
72
include/exec/memory_ldst_cached.h.inc | 46 +++++-----
73
include/exec/memory_ldst_phys.h.inc | 72 +++++++--------
74
accel/tcg/cpu-exec.c | 5 +-
75
accel/tcg/cputlb.c | 2 +-
76
accel/tcg/tcg-runtime.c | 2 +-
77
accel/tcg/translate-all.c | 3 +-
78
cpu.c | 18 ++--
79
hw/core/{cpu.c => cpu-common.c} | 116 -------------------------
80
hw/core/cpu-sysemu.c | 145 +++++++++++++++++++++++++++++++
81
hw/mips/jazz.c | 35 +-------
82
hw/virtio/virtio.c | 4 +-
83
softmmu/physmem.c | 10 +++
84
stubs/vmstate.c | 2 -
85
target/alpha/cpu.c | 12 ++-
86
target/arm/cpu.c | 22 +++--
87
target/arm/cpu_tcg.c | 2 +-
88
target/avr/cpu.c | 12 ++-
89
target/avr/machine.c | 4 +-
90
target/cris/cpu.c | 14 ++-
91
target/hexagon/cpu.c | 2 +-
92
target/hppa/cpu.c | 12 ++-
93
target/i386/cpu.c | 30 ++++---
94
target/i386/tcg/tcg-cpu.c | 2 +-
95
target/m68k/cpu.c | 12 ++-
96
target/microblaze/cpu.c | 12 ++-
97
target/mips/cpu.c | 14 ++-
98
target/mips/tcg/op_helper.c | 3 +-
99
target/nios2/cpu.c | 12 ++-
100
target/openrisc/cpu.c | 12 ++-
101
target/ppc/cpu_init.c | 24 ++---
102
target/riscv/cpu.c | 19 ++--
103
target/rx/cpu.c | 14 ++-
104
target/s390x/cpu.c | 18 ++--
105
target/sh4/cpu.c | 15 +++-
106
target/sparc/cpu.c | 14 ++-
107
target/tricore/cpu.c | 10 ++-
108
target/xtensa/cpu.c | 14 ++-
109
memory_ldst.c.inc | 20 ++---
110
tcg/aarch64/tcg-target.c.inc | 5 +-
111
MAINTAINERS | 1 -
112
hw/core/meson.build | 3 +-
113
53 files changed, 602 insertions(+), 406 deletions(-)
114
rename {include/exec => accel/tcg}/tb-context.h (100%)
115
rename {include/exec => accel/tcg}/tb-hash.h (100%)
116
rename {include/exec => accel/tcg}/tb-lookup.h (98%)
117
create mode 100644 include/hw/core/sysemu-cpu-ops.h
118
rename hw/core/{cpu.c => cpu-common.c} (73%)
119
create mode 100644 hw/core/cpu-sysemu.c
120
diff view generated by jsdifflib
New patch
[PULL 01/31] exec/memory_ldst_cached: Sort declarations
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
To ease the file review, sort the declarations by the size of
4
the access (8, 16, 32). Simple code movement, no logical change.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-Id: <20210518183655.1711377-2-philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/exec/memory_ldst_cached.h.inc | 46 +++++++++++++--------------
11
1 file changed, 23 insertions(+), 23 deletions(-)
12
13
diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ldst_cached.h.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory_ldst_cached.h.inc
16
+++ b/include/exec/memory_ldst_cached.h.inc
17
@@ -XXX,XX +XXX,XX @@
18
#define LD_P(size) \
19
glue(glue(ld, size), glue(ENDIANNESS, _p))
20
21
+static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
22
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
23
+{
24
+ assert(addr < cache->len && 2 <= cache->len - addr);
25
+ fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
26
+ if (likely(cache->ptr)) {
27
+ return LD_P(uw)(cache->ptr + addr);
28
+ } else {
29
+ return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
30
+ }
31
+}
32
+
33
static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
34
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
35
{
36
@@ -XXX,XX +XXX,XX @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
37
}
38
}
39
40
-static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
41
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
42
-{
43
- assert(addr < cache->len && 2 <= cache->len - addr);
44
- fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
45
- if (likely(cache->ptr)) {
46
- return LD_P(uw)(cache->ptr + addr);
47
- } else {
48
- return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
49
- }
50
-}
51
-
52
#undef ADDRESS_SPACE_LD_CACHED
53
#undef ADDRESS_SPACE_LD_CACHED_SLOW
54
#undef LD_P
55
@@ -XXX,XX +XXX,XX @@ static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
56
#define ST_P(size) \
57
glue(glue(st, size), glue(ENDIANNESS, _p))
58
59
-static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
60
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
61
-{
62
- assert(addr < cache->len && 4 <= cache->len - addr);
63
- if (likely(cache->ptr)) {
64
- ST_P(l)(cache->ptr + addr, val);
65
- } else {
66
- ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
67
- }
68
-}
69
-
70
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
71
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
72
{
73
@@ -XXX,XX +XXX,XX @@ static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
74
}
75
}
76
77
+static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
78
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
79
+{
80
+ assert(addr < cache->len && 4 <= cache->len - addr);
81
+ if (likely(cache->ptr)) {
82
+ ST_P(l)(cache->ptr + addr, val);
83
+ } else {
84
+ ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
85
+ }
86
+}
87
+
88
static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache,
89
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
90
{
91
--
92
2.25.1
93
94
diff view generated by jsdifflib
New patch
[PULL 02/31] exec/memory_ldst_phys: Sort declarations
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
To ease the file review, sort the declarations by the size of
4
the access (8, 16, 32). Simple code movement, no logical change.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-Id: <20210518183655.1711377-3-philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/exec/memory_ldst_phys.h.inc | 78 ++++++++++++++---------------
11
1 file changed, 39 insertions(+), 39 deletions(-)
12
13
diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory_ldst_phys.h.inc
16
+++ b/include/exec/memory_ldst_phys.h.inc
17
@@ -XXX,XX +XXX,XX @@
18
*/
19
20
#ifdef TARGET_ENDIANNESS
21
+static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
22
+{
23
+ return glue(address_space_lduw, SUFFIX)(ARG1, addr,
24
+ MEMTXATTRS_UNSPECIFIED, NULL);
25
+}
26
+
27
static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
28
{
29
return glue(address_space_ldl, SUFFIX)(ARG1, addr,
30
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
31
MEMTXATTRS_UNSPECIFIED, NULL);
32
}
33
34
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
35
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
36
{
37
- return glue(address_space_lduw, SUFFIX)(ARG1, addr,
38
- MEMTXATTRS_UNSPECIFIED, NULL);
39
+ glue(address_space_stw, SUFFIX)(ARG1, addr, val,
40
+ MEMTXATTRS_UNSPECIFIED, NULL);
41
}
42
43
static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
44
@@ -XXX,XX +XXX,XX @@ static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
45
MEMTXATTRS_UNSPECIFIED, NULL);
46
}
47
48
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
49
-{
50
- glue(address_space_stw, SUFFIX)(ARG1, addr, val,
51
- MEMTXATTRS_UNSPECIFIED, NULL);
52
-}
53
-
54
static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
55
{
56
glue(address_space_stq, SUFFIX)(ARG1, addr, val,
57
MEMTXATTRS_UNSPECIFIED, NULL);
58
}
59
#else
60
+static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
61
+{
62
+ return glue(address_space_ldub, SUFFIX)(ARG1, addr,
63
+ MEMTXATTRS_UNSPECIFIED, NULL);
64
+}
65
+
66
+static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
67
+{
68
+ return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
69
+ MEMTXATTRS_UNSPECIFIED, NULL);
70
+}
71
+
72
+static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
73
+{
74
+ return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
75
+ MEMTXATTRS_UNSPECIFIED, NULL);
76
+}
77
+
78
static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
79
{
80
return glue(address_space_ldl_le, SUFFIX)(ARG1, addr,
81
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
82
MEMTXATTRS_UNSPECIFIED, NULL);
83
}
84
85
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
86
-{
87
- return glue(address_space_ldub, SUFFIX)(ARG1, addr,
88
- MEMTXATTRS_UNSPECIFIED, NULL);
89
-}
90
-
91
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
92
-{
93
- return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
94
- MEMTXATTRS_UNSPECIFIED, NULL);
95
-}
96
-
97
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
98
-{
99
- return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
100
- MEMTXATTRS_UNSPECIFIED, NULL);
101
-}
102
-
103
-static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
104
-{
105
- glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
106
- MEMTXATTRS_UNSPECIFIED, NULL);
107
-}
108
-
109
-static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
110
-{
111
- glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
112
- MEMTXATTRS_UNSPECIFIED, NULL);
113
-}
114
-
115
static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
116
{
117
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
118
@@ -XXX,XX +XXX,XX @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t va
119
MEMTXATTRS_UNSPECIFIED, NULL);
120
}
121
122
+static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
123
+{
124
+ glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
125
+ MEMTXATTRS_UNSPECIFIED, NULL);
126
+}
127
+
128
+static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
129
+{
130
+ glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
131
+ MEMTXATTRS_UNSPECIFIED, NULL);
132
+}
133
+
134
static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
135
{
136
glue(address_space_stq_le, SUFFIX)(ARG1, addr, val,
137
--
138
2.25.1
139
140
diff view generated by jsdifflib
New patch
[PULL 03/31] exec/memory_ldst: Use correct type sizes
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
4
16-bit word.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-Id: <20210518183655.1711377-4-philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/exec/memory_ldst.h.inc | 16 ++++++++--------
11
memory_ldst.c.inc | 20 ++++++++++----------
12
2 files changed, 18 insertions(+), 18 deletions(-)
13
14
diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory_ldst.h.inc
17
+++ b/include/exec/memory_ldst.h.inc
18
@@ -XXX,XX +XXX,XX @@
19
*/
20
21
#ifdef TARGET_ENDIANNESS
22
-extern uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
23
+extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
24
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
25
extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
26
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
27
@@ -XXX,XX +XXX,XX @@ extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
28
extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
29
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
30
extern void glue(address_space_stw, SUFFIX)(ARG1_DECL,
31
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
32
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
33
extern void glue(address_space_stl, SUFFIX)(ARG1_DECL,
34
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
35
extern void glue(address_space_stq, SUFFIX)(ARG1_DECL,
36
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
37
#else
38
-extern uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
39
+extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
40
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
41
-extern uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
42
+extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
43
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
44
-extern uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
45
+extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
46
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
47
extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
48
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
49
@@ -XXX,XX +XXX,XX @@ extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
50
extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
51
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
52
extern void glue(address_space_stb, SUFFIX)(ARG1_DECL,
53
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
54
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result);
55
extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
56
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
57
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
58
extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
59
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
60
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
61
extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
62
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
63
extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
64
diff --git a/memory_ldst.c.inc b/memory_ldst.c.inc
65
index XXXXXXX..XXXXXXX 100644
66
--- a/memory_ldst.c.inc
67
+++ b/memory_ldst.c.inc
68
@@ -XXX,XX +XXX,XX @@ uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
69
DEVICE_BIG_ENDIAN);
70
}
71
72
-uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
73
+uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
74
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
75
{
76
uint8_t *ptr;
77
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
78
}
79
80
/* warning: addr must be aligned */
81
-static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
82
+static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
83
hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
84
enum device_endian endian)
85
{
86
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
87
return val;
88
}
89
90
-uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
91
+uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
92
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
93
{
94
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
95
DEVICE_NATIVE_ENDIAN);
96
}
97
98
-uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
99
+uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
100
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
101
{
102
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
103
DEVICE_LITTLE_ENDIAN);
104
}
105
106
-uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
107
+uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
108
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
109
{
110
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
111
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
112
}
113
114
void glue(address_space_stb, SUFFIX)(ARG1_DECL,
115
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
116
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)
117
{
118
uint8_t *ptr;
119
MemoryRegion *mr;
120
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
121
122
/* warning: addr must be aligned */
123
static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
124
- hwaddr addr, uint32_t val, MemTxAttrs attrs,
125
+ hwaddr addr, uint16_t val, MemTxAttrs attrs,
126
MemTxResult *result, enum device_endian endian)
127
{
128
uint8_t *ptr;
129
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
130
}
131
132
void glue(address_space_stw, SUFFIX)(ARG1_DECL,
133
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
134
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
135
{
136
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
137
DEVICE_NATIVE_ENDIAN);
138
}
139
140
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
141
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
142
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
143
{
144
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
145
DEVICE_LITTLE_ENDIAN);
146
}
147
148
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
149
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
150
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
151
{
152
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
153
DEVICE_BIG_ENDIAN);
154
--
155
2.25.1
156
157
diff view generated by jsdifflib
New patch
[PULL 04/31] exec/memory_ldst_phys: Use correct type sizes
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
4
16-bit word.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-Id: <20210518183655.1711377-5-philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/exec/memory_ldst_phys.h.inc | 16 ++++++++--------
11
1 file changed, 8 insertions(+), 8 deletions(-)
12
13
diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory_ldst_phys.h.inc
16
+++ b/include/exec/memory_ldst_phys.h.inc
17
@@ -XXX,XX +XXX,XX @@
18
*/
19
20
#ifdef TARGET_ENDIANNESS
21
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
22
+static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
23
{
24
return glue(address_space_lduw, SUFFIX)(ARG1, addr,
25
MEMTXATTRS_UNSPECIFIED, NULL);
26
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
27
MEMTXATTRS_UNSPECIFIED, NULL);
28
}
29
30
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
31
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
32
{
33
glue(address_space_stw, SUFFIX)(ARG1, addr, val,
34
MEMTXATTRS_UNSPECIFIED, NULL);
35
@@ -XXX,XX +XXX,XX @@ static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
36
MEMTXATTRS_UNSPECIFIED, NULL);
37
}
38
#else
39
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
40
+static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
41
{
42
return glue(address_space_ldub, SUFFIX)(ARG1, addr,
43
MEMTXATTRS_UNSPECIFIED, NULL);
44
}
45
46
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
47
+static inline uint16_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
48
{
49
return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
50
MEMTXATTRS_UNSPECIFIED, NULL);
51
}
52
53
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
54
+static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
55
{
56
return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
57
MEMTXATTRS_UNSPECIFIED, NULL);
58
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
59
MEMTXATTRS_UNSPECIFIED, NULL);
60
}
61
62
-static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
63
+static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val)
64
{
65
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
66
MEMTXATTRS_UNSPECIFIED, NULL);
67
}
68
69
-static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
70
+static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
71
{
72
glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
73
MEMTXATTRS_UNSPECIFIED, NULL);
74
}
75
76
-static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
77
+static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
78
{
79
glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
80
MEMTXATTRS_UNSPECIFIED, NULL);
81
--
82
2.25.1
83
84
diff view generated by jsdifflib
New patch
[PULL 05/31] exec/memory_ldst_cached: Use correct type size
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use uint16_t for (unsigned) 16-bit word.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-Id: <20210518183655.1711377-6-philmd@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/exec/memory_ldst_cached.h.inc | 4 ++--
10
1 file changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ldst_cached.h.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/exec/memory_ldst_cached.h.inc
15
+++ b/include/exec/memory_ldst_cached.h.inc
16
@@ -XXX,XX +XXX,XX @@
17
#define LD_P(size) \
18
glue(glue(ld, size), glue(ENDIANNESS, _p))
19
20
-static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
21
+static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
22
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
23
{
24
assert(addr < cache->len && 2 <= cache->len - addr);
25
@@ -XXX,XX +XXX,XX @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
26
glue(glue(st, size), glue(ENDIANNESS, _p))
27
28
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
29
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
30
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
31
{
32
assert(addr < cache->len && 2 <= cache->len - addr);
33
if (likely(cache->ptr)) {
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
New patch
[PULL 06/31] exec/memory: Use correct type size
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use uint8_t for (unsigned) byte.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-Id: <20210518183655.1711377-7-philmd@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/exec/memory.h | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/include/exec/memory.h b/include/exec/memory.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/exec/memory.h
15
+++ b/include/exec/memory.h
16
@@ -XXX,XX +XXX,XX @@ static inline uint8_t address_space_ldub_cached(MemoryRegionCache *cache,
17
}
18
19
static inline void address_space_stb_cached(MemoryRegionCache *cache,
20
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
21
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)
22
{
23
assert(addr < cache->len);
24
if (likely(cache->ptr)) {
25
--
26
2.25.1
27
28
diff view generated by jsdifflib
New patch
[PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Only 2 headers require "exec/tb-context.h". Instead of having
4
all files including "exec/exec-all.h" also including it, directly
5
include it where it is required:
6
- accel/tcg/cpu-exec.c
7
- accel/tcg/translate-all.c
8
9
For plugins/plugin.h, we were implicitly relying on
10
exec/exec-all.h -> exec/tb-context.h -> qemu/qht.h
11
which is now included directly.
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-Id: <20210524170453.3791436-2-f4bug@amsat.org>
15
[rth: Fix plugins/plugin.h compilation]
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
---
18
include/exec/exec-all.h | 1 -
19
include/tcg/tcg.h | 1 -
20
plugins/plugin.h | 1 +
21
accel/tcg/cpu-exec.c | 1 +
22
accel/tcg/translate-all.c | 1 +
23
5 files changed, 3 insertions(+), 2 deletions(-)
24
25
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/exec/exec-all.h
28
+++ b/include/exec/exec-all.h
29
@@ -XXX,XX +XXX,XX @@
30
#define EXEC_ALL_H
31
32
#include "cpu.h"
33
-#include "exec/tb-context.h"
34
#ifdef CONFIG_TCG
35
#include "exec/cpu_ldst.h"
36
#endif
37
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/tcg/tcg.h
40
+++ b/include/tcg/tcg.h
41
@@ -XXX,XX +XXX,XX @@
42
43
#include "cpu.h"
44
#include "exec/memop.h"
45
-#include "exec/tb-context.h"
46
#include "qemu/bitops.h"
47
#include "qemu/plugin.h"
48
#include "qemu/queue.h"
49
diff --git a/plugins/plugin.h b/plugins/plugin.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/plugins/plugin.h
52
+++ b/plugins/plugin.h
53
@@ -XXX,XX +XXX,XX @@
54
#define _PLUGIN_INTERNAL_H_
55
56
#include <gmodule.h>
57
+#include "qemu/qht.h"
58
59
#define QEMU_PLUGIN_MIN_VERSION 0
60
61
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/accel/tcg/cpu-exec.c
64
+++ b/accel/tcg/cpu-exec.c
65
@@ -XXX,XX +XXX,XX @@
66
#include "qemu/rcu.h"
67
#include "exec/tb-hash.h"
68
#include "exec/tb-lookup.h"
69
+#include "exec/tb-context.h"
70
#include "exec/log.h"
71
#include "qemu/main-loop.h"
72
#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
73
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/accel/tcg/translate-all.c
76
+++ b/accel/tcg/translate-all.c
77
@@ -XXX,XX +XXX,XX @@
78
79
#include "exec/cputlb.h"
80
#include "exec/tb-hash.h"
81
+#include "exec/tb-context.h"
82
#include "exec/translate-all.h"
83
#include "qemu/bitmap.h"
84
#include "qemu/error-report.h"
85
--
86
2.25.1
87
88
diff view generated by jsdifflib
New patch
[PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Only the TCG accelerator uses the TranslationBlock API.
4
Move the tb-context.h / tb-hash.h / tb-lookup.h from the
5
global namespace to the TCG one (in accel/tcg).
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210524170453.3791436-3-f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
{include/exec => accel/tcg}/tb-context.h | 0
12
{include/exec => accel/tcg}/tb-hash.h | 0
13
{include/exec => accel/tcg}/tb-lookup.h | 2 +-
14
accel/tcg/cpu-exec.c | 6 +++---
15
accel/tcg/cputlb.c | 2 +-
16
accel/tcg/tcg-runtime.c | 2 +-
17
accel/tcg/translate-all.c | 4 ++--
18
MAINTAINERS | 1 -
19
8 files changed, 8 insertions(+), 9 deletions(-)
20
rename {include/exec => accel/tcg}/tb-context.h (100%)
21
rename {include/exec => accel/tcg}/tb-hash.h (100%)
22
rename {include/exec => accel/tcg}/tb-lookup.h (98%)
23
24
diff --git a/include/exec/tb-context.h b/accel/tcg/tb-context.h
25
similarity index 100%
26
rename from include/exec/tb-context.h
27
rename to accel/tcg/tb-context.h
28
diff --git a/include/exec/tb-hash.h b/accel/tcg/tb-hash.h
29
similarity index 100%
30
rename from include/exec/tb-hash.h
31
rename to accel/tcg/tb-hash.h
32
diff --git a/include/exec/tb-lookup.h b/accel/tcg/tb-lookup.h
33
similarity index 98%
34
rename from include/exec/tb-lookup.h
35
rename to accel/tcg/tb-lookup.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/exec/tb-lookup.h
38
+++ b/accel/tcg/tb-lookup.h
39
@@ -XXX,XX +XXX,XX @@
40
#endif
41
42
#include "exec/exec-all.h"
43
-#include "exec/tb-hash.h"
44
+#include "tb-hash.h"
45
46
/* Might cause an exception, so have a longjmp destination ready */
47
static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
48
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/accel/tcg/cpu-exec.c
51
+++ b/accel/tcg/cpu-exec.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "qemu/compiler.h"
54
#include "qemu/timer.h"
55
#include "qemu/rcu.h"
56
-#include "exec/tb-hash.h"
57
-#include "exec/tb-lookup.h"
58
-#include "exec/tb-context.h"
59
#include "exec/log.h"
60
#include "qemu/main-loop.h"
61
#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
62
@@ -XXX,XX +XXX,XX @@
63
#include "exec/cpu-all.h"
64
#include "sysemu/cpu-timers.h"
65
#include "sysemu/replay.h"
66
+#include "tb-hash.h"
67
+#include "tb-lookup.h"
68
+#include "tb-context.h"
69
#include "internal.h"
70
71
/* -icount align implementation. */
72
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/accel/tcg/cputlb.c
75
+++ b/accel/tcg/cputlb.c
76
@@ -XXX,XX +XXX,XX @@
77
#include "exec/memory.h"
78
#include "exec/cpu_ldst.h"
79
#include "exec/cputlb.h"
80
-#include "exec/tb-hash.h"
81
#include "exec/memory-internal.h"
82
#include "exec/ram_addr.h"
83
#include "tcg/tcg.h"
84
@@ -XXX,XX +XXX,XX @@
85
#include "exec/translate-all.h"
86
#include "trace/trace-root.h"
87
#include "trace/mem.h"
88
+#include "tb-hash.h"
89
#include "internal.h"
90
#ifdef CONFIG_PLUGIN
91
#include "qemu/plugin-memory.h"
92
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/accel/tcg/tcg-runtime.c
95
+++ b/accel/tcg/tcg-runtime.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "disas/disas.h"
98
#include "exec/log.h"
99
#include "tcg/tcg.h"
100
-#include "exec/tb-lookup.h"
101
+#include "tb-lookup.h"
102
103
/* 32-bit helpers */
104
105
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/accel/tcg/translate-all.c
108
+++ b/accel/tcg/translate-all.c
109
@@ -XXX,XX +XXX,XX @@
110
#endif
111
112
#include "exec/cputlb.h"
113
-#include "exec/tb-hash.h"
114
-#include "exec/tb-context.h"
115
#include "exec/translate-all.h"
116
#include "qemu/bitmap.h"
117
#include "qemu/error-report.h"
118
@@ -XXX,XX +XXX,XX @@
119
#include "sysemu/tcg.h"
120
#include "qapi/error.h"
121
#include "hw/core/tcg-cpu-ops.h"
122
+#include "tb-hash.h"
123
+#include "tb-context.h"
124
#include "internal.h"
125
126
/* #define DEBUG_TB_INVALIDATE */
127
diff --git a/MAINTAINERS b/MAINTAINERS
128
index XXXXXXX..XXXXXXX 100644
129
--- a/MAINTAINERS
130
+++ b/MAINTAINERS
131
@@ -XXX,XX +XXX,XX @@ F: docs/devel/decodetree.rst
132
F: include/exec/cpu*.h
133
F: include/exec/exec-all.h
134
F: include/exec/helper*.h
135
-F: include/exec/tb-hash.h
136
F: include/sysemu/cpus.h
137
F: include/sysemu/tcg.h
138
F: include/hw/core/tcg-cpu-ops.h
139
--
140
2.25.1
141
142
diff view generated by jsdifflib
New patch
[PULL 09/31] replay: fix watchpoint processing for reverse debugging
1
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
1
2
3
This patch enables reverse debugging with watchpoints.
4
Reverse continue scans the execution to find the breakpoints
5
and watchpoints that should fire. It uses helper function
6
replay_breakpoint() for that. But this function needs to access
7
icount, which can't be correct in the middle of TB.
8
Therefore, in case of watchpoint, we have to retranslate the block
9
to allow this access.
10
11
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
12
Message-Id: <162072430303.827403.7379783546934958566.stgit@pasha-ThinkPad-X280>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
15
softmmu/physmem.c | 10 ++++++++++
16
1 file changed, 10 insertions(+)
17
18
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/softmmu/physmem.c
21
+++ b/softmmu/physmem.c
22
@@ -XXX,XX +XXX,XX @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
23
if (watchpoint_address_matches(wp, addr, len)
24
&& (wp->flags & flags)) {
25
if (replay_running_debug()) {
26
+ /*
27
+ * replay_breakpoint reads icount.
28
+ * Force recompile to succeed, because icount may
29
+ * be read only at the end of the block.
30
+ */
31
+ if (!cpu->can_do_io) {
32
+ /* Force execution of one insn next time. */
33
+ cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu);
34
+ cpu_loop_exit_restore(cpu, ra);
35
+ }
36
/*
37
* Don't process the watchpoints when we are
38
* in a reverse debugging operation.
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
New patch
[PULL 10/31] tcg/aarch64: Fix tcg_out_rotl
1
From: Yasuo Kuwahara <kwhr00@gmail.com>
1
2
3
The last argument of tcg_out_extr() must be in the range 0-31 if ext==0.
4
Before the fix, when m==0 it becomes 32 and it crashes with an Illegal
5
instruction on Apple Silicon. After the fix, it will be 0. If m is in
6
the range 1-31, it is the same as before.
7
8
Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com>
9
Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
tcg/aarch64/tcg-target.c.inc | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/aarch64/tcg-target.c.inc
18
+++ b/tcg/aarch64/tcg-target.c.inc
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
20
static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
21
TCGReg rd, TCGReg rn, unsigned int m)
22
{
23
- int bits = ext ? 64 : 32;
24
- int max = bits - 1;
25
- tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
26
+ int max = ext ? 63 : 31;
27
+ tcg_out_extr(s, ext, rd, rn, rn, -m & max);
28
}
29
30
static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <20210517105140.1062037-5-f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
hw/core/cpu.c | 1 -
9
1 file changed, 1 deletion(-)
10
11
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/core/cpu.c
14
+++ b/hw/core/cpu.c
15
@@ -XXX,XX +XXX,XX @@
16
#include "hw/qdev-properties.h"
17
#include "trace/trace-root.h"
18
#include "qemu/plugin.h"
19
-#include "sysemu/hw_accel.h"
20
21
CPUState *cpu_by_arch_id(int64_t id)
22
{
23
--
24
2.25.1
25
26
diff view generated by jsdifflib
New patch
[PULL 12/31] cpu: Split as cpu-common / cpu-sysemu
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The current cpu.c contains sysemu-specific methods.
4
To avoid building them in user-mode builds, split the
5
current cpu.c as cpu-common.c / cpu-sysemu.c.
6
7
Start by moving cpu_get_crash_info().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20210517105140.1062037-6-f4bug@amsat.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
hw/core/{cpu.c => cpu-common.c} | 17 -----------------
15
hw/core/cpu-sysemu.c | 34 +++++++++++++++++++++++++++++++++
16
hw/core/meson.build | 3 ++-
17
3 files changed, 36 insertions(+), 18 deletions(-)
18
rename hw/core/{cpu.c => cpu-common.c} (96%)
19
create mode 100644 hw/core/cpu-sysemu.c
20
21
diff --git a/hw/core/cpu.c b/hw/core/cpu-common.c
22
similarity index 96%
23
rename from hw/core/cpu.c
24
rename to hw/core/cpu-common.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/core/cpu.c
27
+++ b/hw/core/cpu-common.c
28
@@ -XXX,XX +XXX,XX @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
29
return target_words_bigendian();
30
}
31
32
-/*
33
- * XXX the following #if is always true because this is a common_ss
34
- * module, so target CONFIG_* is never defined.
35
- */
36
-#if !defined(CONFIG_USER_ONLY)
37
-GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
38
-{
39
- CPUClass *cc = CPU_GET_CLASS(cpu);
40
- GuestPanicInformation *res = NULL;
41
-
42
- if (cc->get_crash_info) {
43
- res = cc->get_crash_info(cpu);
44
- }
45
- return res;
46
-}
47
-#endif
48
-
49
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
50
{
51
CPUClass *cc = CPU_GET_CLASS(cpu);
52
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
53
new file mode 100644
54
index XXXXXXX..XXXXXXX
55
--- /dev/null
56
+++ b/hw/core/cpu-sysemu.c
57
@@ -XXX,XX +XXX,XX @@
58
+/*
59
+ * QEMU CPU model (system emulation specific)
60
+ *
61
+ * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
62
+ *
63
+ * This program is free software; you can redistribute it and/or
64
+ * modify it under the terms of the GNU General Public License
65
+ * as published by the Free Software Foundation; either version 2
66
+ * of the License, or (at your option) any later version.
67
+ *
68
+ * This program is distributed in the hope that it will be useful,
69
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
70
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
71
+ * GNU General Public License for more details.
72
+ *
73
+ * You should have received a copy of the GNU General Public License
74
+ * along with this program; if not, see
75
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
76
+ */
77
+
78
+#include "qemu/osdep.h"
79
+#include "qapi/error.h"
80
+#include "hw/core/cpu.h"
81
+
82
+GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
83
+{
84
+ CPUClass *cc = CPU_GET_CLASS(cpu);
85
+ GuestPanicInformation *res = NULL;
86
+
87
+ if (cc->get_crash_info) {
88
+ res = cc->get_crash_info(cpu);
89
+ }
90
+ return res;
91
+}
92
diff --git a/hw/core/meson.build b/hw/core/meson.build
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/core/meson.build
95
+++ b/hw/core/meson.build
96
@@ -XXX,XX +XXX,XX @@ hwcore_files = files(
97
'qdev-clock.c',
98
)
99
100
-common_ss.add(files('cpu.c'))
101
+common_ss.add(files('cpu-common.c'))
102
common_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c'))
103
common_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c'))
104
common_ss.add(when: ['CONFIG_GUEST_LOADER', fdt], if_true: files('guest-loader.c'))
105
@@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
106
common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
107
108
softmmu_ss.add(files(
109
+ 'cpu-sysemu.c',
110
'fw-path-provider.c',
111
'loader.c',
112
'machine-hmp-cmds.c',
113
--
114
2.25.1
115
116
diff view generated by jsdifflib
New patch
[PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
To be able to later extract the cpu_get_phys_page_debug() and
4
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
5
from "hw/core/cpu.h".
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20210517105140.1062037-7-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/hw/core/cpu.h | 33 ++++-----------------------------
13
hw/core/cpu-sysemu.c | 32 ++++++++++++++++++++++++++++++++
14
2 files changed, 36 insertions(+), 29 deletions(-)
15
16
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/core/cpu.h
19
+++ b/include/hw/core/cpu.h
20
@@ -XXX,XX +XXX,XX @@ void cpu_dump_statistics(CPUState *cpu, int flags);
21
*
22
* Returns: Corresponding physical page address or -1 if no page found.
23
*/
24
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
25
- MemTxAttrs *attrs)
26
-{
27
- CPUClass *cc = CPU_GET_CLASS(cpu);
28
-
29
- if (cc->get_phys_page_attrs_debug) {
30
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
31
- }
32
- /* Fallback for CPUs which don't implement the _attrs_ hook */
33
- *attrs = MEMTXATTRS_UNSPECIFIED;
34
- return cc->get_phys_page_debug(cpu, addr);
35
-}
36
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
37
+ MemTxAttrs *attrs);
38
39
/**
40
* cpu_get_phys_page_debug:
41
@@ -XXX,XX +XXX,XX @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
42
*
43
* Returns: Corresponding physical page address or -1 if no page found.
44
*/
45
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
46
-{
47
- MemTxAttrs attrs = {};
48
-
49
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
50
-}
51
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
52
53
/** cpu_asidx_from_attrs:
54
* @cpu: CPU
55
@@ -XXX,XX +XXX,XX @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
56
* Returns the address space index specifying the CPU AddressSpace
57
* to use for a memory access with the given transaction attributes.
58
*/
59
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
60
-{
61
- CPUClass *cc = CPU_GET_CLASS(cpu);
62
- int ret = 0;
63
-
64
- if (cc->asidx_from_attrs) {
65
- ret = cc->asidx_from_attrs(cpu, attrs);
66
- assert(ret < cpu->num_ases && ret >= 0);
67
- }
68
- return ret;
69
-}
70
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
71
72
#endif /* CONFIG_USER_ONLY */
73
74
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/core/cpu-sysemu.c
77
+++ b/hw/core/cpu-sysemu.c
78
@@ -XXX,XX +XXX,XX @@
79
#include "qapi/error.h"
80
#include "hw/core/cpu.h"
81
82
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
83
+ MemTxAttrs *attrs)
84
+{
85
+ CPUClass *cc = CPU_GET_CLASS(cpu);
86
+
87
+ if (cc->get_phys_page_attrs_debug) {
88
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
89
+ }
90
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
91
+ *attrs = MEMTXATTRS_UNSPECIFIED;
92
+ return cc->get_phys_page_debug(cpu, addr);
93
+}
94
+
95
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
96
+{
97
+ MemTxAttrs attrs = {};
98
+
99
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
100
+}
101
+
102
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
103
+{
104
+ CPUClass *cc = CPU_GET_CLASS(cpu);
105
+ int ret = 0;
106
+
107
+ if (cc->asidx_from_attrs) {
108
+ ret = cc->asidx_from_attrs(cpu, attrs);
109
+ assert(ret < cpu->num_ases && ret >= 0);
110
+ }
111
+ return ret;
112
+}
113
+
114
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
115
{
116
CPUClass *cc = CPU_GET_CLASS(cpu);
117
--
118
2.25.1
119
120
diff view generated by jsdifflib
New patch
[PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian()
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
4
calling CPUClass internal virtio_is_big_endian() one.
5
6
Similarly to commit bf7663c4bd8 ("cpu: introduce
7
CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method
8
name to hint this handler shouldn't be called anywhere but from the
9
virtio code.
10
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-Id: <20210517105140.1062037-8-f4bug@amsat.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
include/hw/core/cpu.h | 9 +++++++++
17
hw/core/cpu-common.c | 6 ------
18
hw/core/cpu-sysemu.c | 10 ++++++++++
19
hw/virtio/virtio.c | 4 +---
20
4 files changed, 20 insertions(+), 9 deletions(-)
21
22
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/core/cpu.h
25
+++ b/include/hw/core/cpu.h
26
@@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
27
*/
28
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
29
30
+/**
31
+ * cpu_virtio_is_big_endian:
32
+ * @cpu: CPU
33
+
34
+ * Returns %true if a CPU which supports runtime configurable endianness
35
+ * is currently big-endian.
36
+ */
37
+bool cpu_virtio_is_big_endian(CPUState *cpu);
38
+
39
#endif /* CONFIG_USER_ONLY */
40
41
/**
42
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/core/cpu-common.c
45
+++ b/hw/core/cpu-common.c
46
@@ -XXX,XX +XXX,XX @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
47
return 0;
48
}
49
50
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
51
-{
52
- return target_words_bigendian();
53
-}
54
-
55
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
56
{
57
CPUClass *cc = CPU_GET_CLASS(cpu);
58
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
59
k->write_elf64_note = cpu_common_write_elf64_note;
60
k->gdb_read_register = cpu_common_gdb_read_register;
61
k->gdb_write_register = cpu_common_gdb_write_register;
62
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
63
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
64
dc->realize = cpu_common_realizefn;
65
dc->unrealize = cpu_common_unrealizefn;
66
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/core/cpu-sysemu.c
69
+++ b/hw/core/cpu-sysemu.c
70
@@ -XXX,XX +XXX,XX @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
71
return ret;
72
}
73
74
+bool cpu_virtio_is_big_endian(CPUState *cpu)
75
+{
76
+ CPUClass *cc = CPU_GET_CLASS(cpu);
77
+
78
+ if (cc->virtio_is_big_endian) {
79
+ return cc->virtio_is_big_endian(cpu);
80
+ }
81
+ return target_words_bigendian();
82
+}
83
+
84
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
85
{
86
CPUClass *cc = CPU_GET_CLASS(cpu);
87
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/virtio/virtio.c
90
+++ b/hw/virtio/virtio.c
91
@@ -XXX,XX +XXX,XX @@ static enum virtio_device_endian virtio_default_endian(void)
92
93
static enum virtio_device_endian virtio_current_cpu_endian(void)
94
{
95
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
96
-
97
- if (cc->virtio_is_big_endian(current_cpu)) {
98
+ if (cpu_virtio_is_big_endian(current_cpu)) {
99
return VIRTIO_DEVICE_ENDIAN_BIG;
100
} else {
101
return VIRTIO_DEVICE_ENDIAN_LITTLE;
102
--
103
2.25.1
104
105
diff view generated by jsdifflib
New patch
[PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
No code directly accesses CPUClass::write_elf*() handlers out
4
of hw/core/cpu.c (the rest are assignation in target/ code):
5
6
$ git grep -F -- '->write_elf'
7
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
8
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
9
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
10
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
11
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
12
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
13
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
14
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
15
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
16
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
17
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
18
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
19
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
20
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
21
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
22
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
23
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
24
25
Check the handler presence in place and remove the common fallback code.
26
27
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Message-Id: <20210517105140.1062037-9-f4bug@amsat.org>
30
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
31
---
32
hw/core/cpu-common.c | 63 --------------------------------------------
33
hw/core/cpu-sysemu.c | 44 +++++++++++++++++++++++++++++++
34
2 files changed, 44 insertions(+), 63 deletions(-)
35
36
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/core/cpu-common.c
39
+++ b/hw/core/cpu-common.c
40
@@ -XXX,XX +XXX,XX @@ void cpu_exit(CPUState *cpu)
41
qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
42
}
43
44
-int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
45
- void *opaque)
46
-{
47
- CPUClass *cc = CPU_GET_CLASS(cpu);
48
-
49
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
50
-}
51
-
52
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
53
- CPUState *cpu, void *opaque)
54
-{
55
- return 0;
56
-}
57
-
58
-int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
59
- int cpuid, void *opaque)
60
-{
61
- CPUClass *cc = CPU_GET_CLASS(cpu);
62
-
63
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
64
-}
65
-
66
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
67
- CPUState *cpu, int cpuid,
68
- void *opaque)
69
-{
70
- return -1;
71
-}
72
-
73
-int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
74
- void *opaque)
75
-{
76
- CPUClass *cc = CPU_GET_CLASS(cpu);
77
-
78
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
79
-}
80
-
81
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
82
- CPUState *cpu, void *opaque)
83
-{
84
- return 0;
85
-}
86
-
87
-int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
88
- int cpuid, void *opaque)
89
-{
90
- CPUClass *cc = CPU_GET_CLASS(cpu);
91
-
92
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
93
-}
94
-
95
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
96
- CPUState *cpu, int cpuid,
97
- void *opaque)
98
-{
99
- return -1;
100
-}
101
-
102
-
103
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
104
{
105
return 0;
106
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
107
k->has_work = cpu_common_has_work;
108
k->get_paging_enabled = cpu_common_get_paging_enabled;
109
k->get_memory_mapping = cpu_common_get_memory_mapping;
110
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
111
- k->write_elf32_note = cpu_common_write_elf32_note;
112
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
113
- k->write_elf64_note = cpu_common_write_elf64_note;
114
k->gdb_read_register = cpu_common_gdb_read_register;
115
k->gdb_write_register = cpu_common_gdb_write_register;
116
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
117
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/core/cpu-sysemu.c
120
+++ b/hw/core/cpu-sysemu.c
121
@@ -XXX,XX +XXX,XX @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
122
return ret;
123
}
124
125
+int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
126
+ void *opaque)
127
+{
128
+ CPUClass *cc = CPU_GET_CLASS(cpu);
129
+
130
+ if (!cc->write_elf32_qemunote) {
131
+ return 0;
132
+ }
133
+ return (*cc->write_elf32_qemunote)(f, cpu, opaque);
134
+}
135
+
136
+int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
137
+ int cpuid, void *opaque)
138
+{
139
+ CPUClass *cc = CPU_GET_CLASS(cpu);
140
+
141
+ if (!cc->write_elf32_note) {
142
+ return -1;
143
+ }
144
+ return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
145
+}
146
+
147
+int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
148
+ void *opaque)
149
+{
150
+ CPUClass *cc = CPU_GET_CLASS(cpu);
151
+
152
+ if (!cc->write_elf64_qemunote) {
153
+ return 0;
154
+ }
155
+ return (*cc->write_elf64_qemunote)(f, cpu, opaque);
156
+}
157
+
158
+int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
159
+ int cpuid, void *opaque)
160
+{
161
+ CPUClass *cc = CPU_GET_CLASS(cpu);
162
+
163
+ if (!cc->write_elf64_note) {
164
+ return -1;
165
+ }
166
+ return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
167
+}
168
+
169
bool cpu_virtio_is_big_endian(CPUState *cpu)
170
{
171
CPUClass *cc = CPU_GET_CLASS(cpu);
172
--
173
2.25.1
174
175
diff view generated by jsdifflib
New patch
[PULL 16/31] cpu: Directly use get_paging_enabled() fallback handlers in place
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
4
5
$ git grep -F -- '->get_paging_enabled'
6
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
7
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
8
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
9
10
Check the handler presence in place and remove the common fallback code.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-Id: <20210517105140.1062037-10-f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
hw/core/cpu-common.c | 13 -------------
18
hw/core/cpu-sysemu.c | 11 +++++++++++
19
2 files changed, 11 insertions(+), 13 deletions(-)
20
21
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/core/cpu-common.c
24
+++ b/hw/core/cpu-common.c
25
@@ -XXX,XX +XXX,XX @@ CPUState *cpu_create(const char *typename)
26
return cpu;
27
}
28
29
-bool cpu_paging_enabled(const CPUState *cpu)
30
-{
31
- CPUClass *cc = CPU_GET_CLASS(cpu);
32
-
33
- return cc->get_paging_enabled(cpu);
34
-}
35
-
36
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
37
-{
38
- return false;
39
-}
40
-
41
void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
42
Error **errp)
43
{
44
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
45
k->parse_features = cpu_common_parse_features;
46
k->get_arch_id = cpu_common_get_arch_id;
47
k->has_work = cpu_common_has_work;
48
- k->get_paging_enabled = cpu_common_get_paging_enabled;
49
k->get_memory_mapping = cpu_common_get_memory_mapping;
50
k->gdb_read_register = cpu_common_gdb_read_register;
51
k->gdb_write_register = cpu_common_gdb_write_register;
52
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/core/cpu-sysemu.c
55
+++ b/hw/core/cpu-sysemu.c
56
@@ -XXX,XX +XXX,XX @@
57
#include "qapi/error.h"
58
#include "hw/core/cpu.h"
59
60
+bool cpu_paging_enabled(const CPUState *cpu)
61
+{
62
+ CPUClass *cc = CPU_GET_CLASS(cpu);
63
+
64
+ if (cc->get_paging_enabled) {
65
+ return cc->get_paging_enabled(cpu);
66
+ }
67
+
68
+ return false;
69
+}
70
+
71
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
72
MemTxAttrs *attrs)
73
{
74
--
75
2.25.1
76
77
diff view generated by jsdifflib
New patch
[PULL 17/31] cpu: Directly use get_memory_mapping() fallback handlers in place
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
4
5
$ git grep -F -- '->get_memory_mapping'
6
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
7
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
8
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
9
10
Check the handler presence in place and remove the common fallback code.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-Id: <20210517105140.1062037-11-f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
hw/core/cpu-common.c | 16 ----------------
18
hw/core/cpu-sysemu.c | 13 +++++++++++++
19
2 files changed, 13 insertions(+), 16 deletions(-)
20
21
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/core/cpu-common.c
24
+++ b/hw/core/cpu-common.c
25
@@ -XXX,XX +XXX,XX @@ CPUState *cpu_create(const char *typename)
26
return cpu;
27
}
28
29
-void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
30
- Error **errp)
31
-{
32
- CPUClass *cc = CPU_GET_CLASS(cpu);
33
-
34
- cc->get_memory_mapping(cpu, list, errp);
35
-}
36
-
37
-static void cpu_common_get_memory_mapping(CPUState *cpu,
38
- MemoryMappingList *list,
39
- Error **errp)
40
-{
41
- error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
42
-}
43
-
44
/* Resetting the IRQ comes from across the code base so we take the
45
* BQL here if we need to. cpu_interrupt assumes it is held.*/
46
void cpu_reset_interrupt(CPUState *cpu, int mask)
47
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
48
k->parse_features = cpu_common_parse_features;
49
k->get_arch_id = cpu_common_get_arch_id;
50
k->has_work = cpu_common_has_work;
51
- k->get_memory_mapping = cpu_common_get_memory_mapping;
52
k->gdb_read_register = cpu_common_gdb_read_register;
53
k->gdb_write_register = cpu_common_gdb_write_register;
54
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
55
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/core/cpu-sysemu.c
58
+++ b/hw/core/cpu-sysemu.c
59
@@ -XXX,XX +XXX,XX @@ bool cpu_paging_enabled(const CPUState *cpu)
60
return false;
61
}
62
63
+void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
64
+ Error **errp)
65
+{
66
+ CPUClass *cc = CPU_GET_CLASS(cpu);
67
+
68
+ if (cc->get_memory_mapping) {
69
+ cc->get_memory_mapping(cpu, list, errp);
70
+ return;
71
+ }
72
+
73
+ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
74
+}
75
+
76
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
77
MemTxAttrs *attrs)
78
{
79
--
80
2.25.1
81
82
diff view generated by jsdifflib
New patch
[PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Migration is specific to system emulation.
4
5
Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
6
and assert in cpu_exec_realizefn() that dc->vmsd not set under
7
user emulation.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20210517105140.1062037-12-f4bug@amsat.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
cpu.c | 2 ++
15
target/sh4/cpu.c | 5 +++--
16
target/xtensa/cpu.c | 4 +++-
17
3 files changed, 8 insertions(+), 3 deletions(-)
18
19
diff --git a/cpu.c b/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/cpu.c
22
+++ b/cpu.c
23
@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
24
#endif /* CONFIG_TCG */
25
26
#ifdef CONFIG_USER_ONLY
27
+ assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
28
+ qdev_get_vmsd(DEVICE(cpu))->unmigratable);
29
assert(cc->vmsd == NULL);
30
#else
31
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
32
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/sh4/cpu.c
35
+++ b/target/sh4/cpu.c
36
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_initfn(Object *obj)
37
env->movcal_backup_tail = &(env->movcal_backup);
38
}
39
40
+#ifndef CONFIG_USER_ONLY
41
static const VMStateDescription vmstate_sh_cpu = {
42
.name = "cpu",
43
.unmigratable = 1,
44
};
45
+#endif
46
47
#include "hw/core/tcg-cpu-ops.h"
48
49
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
50
cc->gdb_write_register = superh_cpu_gdb_write_register;
51
#ifndef CONFIG_USER_ONLY
52
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
53
+ dc->vmsd = &vmstate_sh_cpu;
54
#endif
55
cc->disas_set_info = superh_cpu_disas_set_info;
56
57
cc->gdb_num_core_regs = 59;
58
-
59
- dc->vmsd = &vmstate_sh_cpu;
60
cc->tcg_ops = &superh_tcg_ops;
61
}
62
63
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/xtensa/cpu.c
66
+++ b/target/xtensa/cpu.c
67
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_initfn(Object *obj)
68
#endif
69
}
70
71
+#ifndef CONFIG_USER_ONLY
72
static const VMStateDescription vmstate_xtensa_cpu = {
73
.name = "cpu",
74
.unmigratable = 1,
75
};
76
+#endif
77
78
#include "hw/core/tcg-cpu-ops.h"
79
80
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
81
cc->gdb_stop_before_watchpoint = true;
82
#ifndef CONFIG_USER_ONLY
83
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
84
+ dc->vmsd = &vmstate_xtensa_cpu;
85
#endif
86
cc->disas_set_info = xtensa_cpu_disas_set_info;
87
- dc->vmsd = &vmstate_xtensa_cpu;
88
cc->tcg_ops = &xtensa_tcg_ops;
89
}
90
91
--
92
2.25.1
93
94
diff view generated by jsdifflib
New patch
[PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd
1
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
3
Quoting Peter Maydell [*]:
4
5
There are two ways to handle migration for
6
a CPU object:
7
8
(1) like any other device, so it has a dc->vmsd that covers
9
migration for the whole object. As usual for objects that are a
10
subclass of a parent that has state, the first entry in the
11
VMStateDescription field list is VMSTATE_CPU(), which migrates
12
the cpu_common fields, followed by whatever the CPU's own migration
13
fields are.
14
15
(2) a backwards-compatible mechanism for CPUs that were
16
originally migrated using manual "write fields to the migration
17
stream structures". The on-the-wire migration format
18
for those is based on the 'env' pointer (which isn't a QOM object),
19
and the cpu_common part of the migration data is elsewhere.
20
21
cpu_exec_realizefn() handles both possibilities:
22
23
* for type 1, dc->vmsd is set and cc->vmsd is not,
24
so cpu_exec_realizefn() does nothing, and the standard
25
"register dc->vmsd for a device" code does everything needed
26
27
* for type 2, dc->vmsd is NULL and so we register the
28
vmstate_cpu_common directly to handle the cpu-common fields,
29
and the cc->vmsd to handle the per-CPU stuff
30
31
You can't change a CPU from one type to the other without breaking
32
migration compatibility, which is why some guest architectures
33
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
34
35
To avoid new targets to start using type (2), rename cc->vmsd as
36
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
37
DeviceClass one).
38
39
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
40
through CPUState") for historic background.
41
42
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
43
44
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
46
Cc: Peter Maydell <peter.maydell@linaro.org>
47
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
48
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
49
---
50
include/hw/core/cpu.h | 5 +++--
51
cpu.c | 12 ++++++------
52
target/arm/cpu.c | 2 +-
53
target/avr/cpu.c | 2 +-
54
target/i386/cpu.c | 2 +-
55
target/mips/cpu.c | 2 +-
56
target/ppc/cpu_init.c | 2 +-
57
target/riscv/cpu.c | 3 +--
58
target/s390x/cpu.c | 2 +-
59
target/sparc/cpu.c | 2 +-
60
10 files changed, 17 insertions(+), 17 deletions(-)
61
62
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/hw/core/cpu.h
65
+++ b/include/hw/core/cpu.h
66
@@ -XXX,XX +XXX,XX @@ struct AccelCPUClass;
67
* 32-bit VM coredump.
68
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
69
* note to a 32-bit VM coredump.
70
- * @vmsd: State description for migration.
71
+ * @legacy_vmsd: Legacy state description for migration.
72
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
73
* @gdb_num_core_regs: Number of core registers accessible to GDB.
74
* @gdb_core_xml_file: File name for core registers GDB XML description.
75
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
76
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
77
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
78
void *opaque);
79
80
- const VMStateDescription *vmsd;
81
+ const VMStateDescription *legacy_vmsd;
82
const char *gdb_core_xml_file;
83
gchar * (*gdb_arch_name)(CPUState *cpu);
84
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
85
diff --git a/cpu.c b/cpu.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/cpu.c
88
+++ b/cpu.c
89
@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
90
#ifdef CONFIG_USER_ONLY
91
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
92
qdev_get_vmsd(DEVICE(cpu))->unmigratable);
93
- assert(cc->vmsd == NULL);
94
+ assert(cc->legacy_vmsd == NULL);
95
#else
96
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
97
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
98
}
99
- if (cc->vmsd != NULL) {
100
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
101
+ if (cc->legacy_vmsd != NULL) {
102
+ vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
103
}
104
#endif /* CONFIG_USER_ONLY */
105
}
106
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
107
CPUClass *cc = CPU_GET_CLASS(cpu);
108
109
#ifdef CONFIG_USER_ONLY
110
- assert(cc->vmsd == NULL);
111
+ assert(cc->legacy_vmsd == NULL);
112
#else
113
- if (cc->vmsd != NULL) {
114
- vmstate_unregister(NULL, cc->vmsd, cpu);
115
+ if (cc->legacy_vmsd != NULL) {
116
+ vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
117
}
118
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
119
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
120
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/target/arm/cpu.c
123
+++ b/target/arm/cpu.c
124
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
125
#ifndef CONFIG_USER_ONLY
126
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
127
cc->asidx_from_attrs = arm_asidx_from_attrs;
128
- cc->vmsd = &vmstate_arm_cpu;
129
+ cc->legacy_vmsd = &vmstate_arm_cpu;
130
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
131
cc->write_elf64_note = arm_cpu_write_elf64_note;
132
cc->write_elf32_note = arm_cpu_write_elf32_note;
133
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/avr/cpu.c
136
+++ b/target/avr/cpu.c
137
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
138
cc->set_pc = avr_cpu_set_pc;
139
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
140
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
141
- cc->vmsd = &vms_avr_cpu;
142
+ cc->legacy_vmsd = &vms_avr_cpu;
143
cc->disas_set_info = avr_cpu_disas_set_info;
144
cc->gdb_read_register = avr_cpu_gdb_read_register;
145
cc->gdb_write_register = avr_cpu_gdb_write_register;
146
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/i386/cpu.c
149
+++ b/target/i386/cpu.c
150
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
151
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
152
cc->write_elf32_note = x86_cpu_write_elf32_note;
153
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
154
- cc->vmsd = &vmstate_x86_cpu;
155
+ cc->legacy_vmsd = &vmstate_x86_cpu;
156
#endif /* !CONFIG_USER_ONLY */
157
158
cc->gdb_arch_name = x86_gdb_arch_name;
159
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/target/mips/cpu.c
162
+++ b/target/mips/cpu.c
163
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
164
cc->gdb_write_register = mips_cpu_gdb_write_register;
165
#ifndef CONFIG_USER_ONLY
166
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
167
- cc->vmsd = &vmstate_mips_cpu;
168
+ cc->legacy_vmsd = &vmstate_mips_cpu;
169
#endif
170
cc->disas_set_info = mips_cpu_disas_set_info;
171
cc->gdb_num_core_regs = 73;
172
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/ppc/cpu_init.c
175
+++ b/target/ppc/cpu_init.c
176
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
177
cc->gdb_write_register = ppc_cpu_gdb_write_register;
178
#ifndef CONFIG_USER_ONLY
179
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
180
- cc->vmsd = &vmstate_ppc_cpu;
181
+ cc->legacy_vmsd = &vmstate_ppc_cpu;
182
#endif
183
#if defined(CONFIG_SOFTMMU)
184
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
185
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/target/riscv/cpu.c
188
+++ b/target/riscv/cpu.c
189
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
190
cc->disas_set_info = riscv_cpu_disas_set_info;
191
#ifndef CONFIG_USER_ONLY
192
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
193
- /* For now, mark unmigratable: */
194
- cc->vmsd = &vmstate_riscv_cpu;
195
+ cc->legacy_vmsd = &vmstate_riscv_cpu;
196
cc->write_elf64_note = riscv_cpu_write_elf64_note;
197
cc->write_elf32_note = riscv_cpu_write_elf32_note;
198
#endif
199
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/target/s390x/cpu.c
202
+++ b/target/s390x/cpu.c
203
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
204
cc->gdb_write_register = s390_cpu_gdb_write_register;
205
#ifndef CONFIG_USER_ONLY
206
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
207
- cc->vmsd = &vmstate_s390_cpu;
208
+ cc->legacy_vmsd = &vmstate_s390_cpu;
209
cc->get_crash_info = s390_cpu_get_crash_info;
210
cc->write_elf64_note = s390_cpu_write_elf64_note;
211
#endif
212
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
213
index XXXXXXX..XXXXXXX 100644
214
--- a/target/sparc/cpu.c
215
+++ b/target/sparc/cpu.c
216
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
217
cc->gdb_write_register = sparc_cpu_gdb_write_register;
218
#ifndef CONFIG_USER_ONLY
219
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
220
- cc->vmsd = &vmstate_sparc_cpu;
221
+ cc->legacy_vmsd = &vmstate_sparc_cpu;
222
#endif
223
cc->disas_set_info = cpu_sparc_disas_set_info;
224
225
--
226
2.25.1
227
228
diff view generated by jsdifflib
New patch
[PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
See rationale in previous commit. Targets should use the vmsd field
4
of DeviceClass, not CPUClass. As migration is not important on the
5
AVR target, break the migration compatibility and set the DeviceClass
6
vmsd field. To feel safer, increment the vmstate version.
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210517105140.1062037-14-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
target/avr/cpu.c | 2 +-
13
target/avr/machine.c | 4 ++--
14
2 files changed, 3 insertions(+), 3 deletions(-)
15
16
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/avr/cpu.c
19
+++ b/target/avr/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
21
cc->set_pc = avr_cpu_set_pc;
22
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
23
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
24
- cc->legacy_vmsd = &vms_avr_cpu;
25
+ dc->vmsd = &vms_avr_cpu;
26
cc->disas_set_info = avr_cpu_disas_set_info;
27
cc->gdb_read_register = avr_cpu_gdb_read_register;
28
cc->gdb_write_register = avr_cpu_gdb_write_register;
29
diff --git a/target/avr/machine.c b/target/avr/machine.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/avr/machine.c
32
+++ b/target/avr/machine.c
33
@@ -XXX,XX +XXX,XX @@ static const VMStateInfo vms_eind = {
34
35
const VMStateDescription vms_avr_cpu = {
36
.name = "cpu",
37
- .version_id = 0,
38
- .minimum_version_id = 0,
39
+ .version_id = 1,
40
+ .minimum_version_id = 1,
41
.fields = (VMStateField[]) {
42
VMSTATE_UINT32(env.pc_w, AVRCPU),
43
VMSTATE_UINT32(env.sp, AVRCPU),
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
[PULL 5/5] decodetree: Extend argument set syntax to allow types
[PULL 21/31] cpu: Introduce SysemuCPUOps structure
1
Rather than force all structure members to be 'int',
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
allow the type of the member to be specified.
3
2
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Introduce a structure to hold handler specific to sysemu.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org>
8
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
10
---
7
docs/devel/decodetree.rst | 11 ++++---
11
include/hw/core/cpu.h | 6 ++++++
8
tests/decode/succ_argset_type1.decode | 1 +
12
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
9
scripts/decodetree.py | 45 +++++++++++++++++----------
13
cpu.c | 1 +
10
3 files changed, 36 insertions(+), 21 deletions(-)
14
target/alpha/cpu.c | 8 ++++++++
11
create mode 100644 tests/decode/succ_argset_type1.decode
15
target/arm/cpu.c | 8 ++++++++
16
target/avr/cpu.c | 6 ++++++
17
target/cris/cpu.c | 8 ++++++++
18
target/hppa/cpu.c | 8 ++++++++
19
target/i386/cpu.c | 8 ++++++++
20
target/m68k/cpu.c | 8 ++++++++
21
target/microblaze/cpu.c | 8 ++++++++
22
target/mips/cpu.c | 8 ++++++++
23
target/nios2/cpu.c | 8 ++++++++
24
target/openrisc/cpu.c | 8 ++++++++
25
target/ppc/cpu_init.c | 8 ++++++++
26
target/riscv/cpu.c | 8 ++++++++
27
target/rx/cpu.c | 10 ++++++++++
28
target/s390x/cpu.c | 8 ++++++++
29
target/sh4/cpu.c | 6 ++++++
30
target/sparc/cpu.c | 8 ++++++++
31
target/tricore/cpu.c | 6 ++++++
32
target/xtensa/cpu.c | 6 ++++++
33
22 files changed, 174 insertions(+)
34
create mode 100644 include/hw/core/sysemu-cpu-ops.h
12
35
13
diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
36
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
14
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/devel/decodetree.rst
38
--- a/include/hw/core/cpu.h
16
+++ b/docs/devel/decodetree.rst
39
+++ b/include/hw/core/cpu.h
17
@@ -XXX,XX +XXX,XX @@ and returns an integral value extracted from there.
40
@@ -XXX,XX +XXX,XX @@ struct TCGCPUOps;
18
41
/* see accel-cpu.h */
19
A field with no ``unnamed_fields`` and no ``!function`` is in error.
42
struct AccelCPUClass;
20
43
21
-FIXME: the fields of the structure into which this result will be stored
44
+/* see sysemu-cpu-ops.h */
22
-is restricted to ``int``. Which means that we cannot expand 64-bit items.
45
+struct SysemuCPUOps;
23
-
46
+
24
Field examples:
47
/**
25
48
* CPUClass:
26
+---------------------------+---------------------------------------------+
49
* @class_by_name: Callback to map -cpu command line model name to an
27
@@ -XXX,XX +XXX,XX @@ Argument Sets
50
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
28
Syntax::
51
bool gdb_stop_before_watchpoint;
29
52
struct AccelCPUClass *accel_cpu;
30
args_def := '&' identifier ( args_elt )+ ( !extern )?
53
31
- args_elt := identifier
54
+ /* when system emulation is not available, this pointer is NULL */
32
+ args_elt := identifier (':' identifier)?
55
+ const struct SysemuCPUOps *sysemu_ops;
33
56
+
34
Each *args_elt* defines an argument within the argument set.
57
/* when TCG is not available, this pointer is NULL */
35
+If the form of the *args_elt* contains a colon, the first
58
struct TCGCPUOps *tcg_ops;
36
+identifier is the argument name and the second identifier is
59
37
+the argument type. If the colon is missing, the argument
60
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
38
+type will be ``int``.
39
+
40
Each argument set will be rendered as a C structure "arg_$name"
41
with each of the fields being one of the member arguments.
42
43
@@ -XXX,XX +XXX,XX @@ Argument set examples::
44
45
&reg3 ra rb rc
46
&loadstore reg base offset
47
+ &longldst reg base offset:int64_t
48
49
50
Formats
51
diff --git a/tests/decode/succ_argset_type1.decode b/tests/decode/succ_argset_type1.decode
52
new file mode 100644
61
new file mode 100644
53
index XXXXXXX..XXXXXXX
62
index XXXXXXX..XXXXXXX
54
--- /dev/null
63
--- /dev/null
55
+++ b/tests/decode/succ_argset_type1.decode
64
+++ b/include/hw/core/sysemu-cpu-ops.h
56
@@ -0,0 +1 @@
65
@@ -XXX,XX +XXX,XX @@
57
+&asdf b:bool c:uint64_t a
66
+/*
58
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
67
+ * CPU operations specific to system emulation
59
index XXXXXXX..XXXXXXX 100644
68
+ *
60
--- a/scripts/decodetree.py
69
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
61
+++ b/scripts/decodetree.py
70
+ *
62
@@ -XXX,XX +XXX,XX @@ def is_contiguous(bits):
71
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
63
return -1
72
+ * See the COPYING file in the top-level directory.
64
73
+ */
65
74
+
66
-def eq_fields_for_args(flds_a, flds_b):
75
+#ifndef SYSEMU_CPU_OPS_H
67
- if len(flds_a) != len(flds_b):
76
+#define SYSEMU_CPU_OPS_H
68
+def eq_fields_for_args(flds_a, arg):
77
+
69
+ if len(flds_a) != len(arg.fields):
78
+#include "hw/core/cpu.h"
70
return False
79
+
71
+ # Only allow inference on default types
80
+/*
72
+ for t in arg.types:
81
+ * struct SysemuCPUOps: System operations specific to a CPU class
73
+ if t != 'int':
82
+ */
74
+ return False
83
+typedef struct SysemuCPUOps {
75
for k, a in flds_a.items():
84
+} SysemuCPUOps;
76
- if k not in flds_b:
85
+
77
+ if k not in arg.fields:
86
+#endif /* SYSEMU_CPU_OPS_H */
78
return False
87
diff --git a/cpu.c b/cpu.c
79
return True
88
index XXXXXXX..XXXXXXX 100644
80
89
--- a/cpu.c
81
@@ -XXX,XX +XXX,XX @@ def __ne__(self, other):
90
+++ b/cpu.c
82
91
@@ -XXX,XX +XXX,XX @@
83
class Arguments:
92
#ifdef CONFIG_USER_ONLY
84
"""Class representing the extracted fields of a format"""
93
#include "qemu.h"
85
- def __init__(self, nm, flds, extern):
94
#else
86
+ def __init__(self, nm, flds, types, extern):
95
+#include "hw/core/sysemu-cpu-ops.h"
87
self.name = nm
96
#include "exec/address-spaces.h"
88
self.extern = extern
97
#endif
89
- self.fields = sorted(flds)
98
#include "sysemu/tcg.h"
90
+ self.fields = flds
99
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
91
+ self.types = types
100
index XXXXXXX..XXXXXXX 100644
92
101
--- a/target/alpha/cpu.c
93
def __str__(self):
102
+++ b/target/alpha/cpu.c
94
return self.name + ' ' + str(self.fields)
103
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
95
@@ -XXX,XX +XXX,XX @@ def struct_name(self):
104
#endif
96
def output_def(self):
105
}
97
if not self.extern:
106
98
output('typedef struct {\n')
107
+#ifndef CONFIG_USER_ONLY
99
- for n in self.fields:
108
+#include "hw/core/sysemu-cpu-ops.h"
100
- output(' int ', n, ';\n')
109
+
101
+ for (n, t) in zip(self.fields, self.types):
110
+static const struct SysemuCPUOps alpha_sysemu_ops = {
102
+ output(f' {t} {n};\n')
111
+};
103
output('} ', self.struct_name(), ';\n\n')
112
+#endif
104
# end Arguments
113
+
105
114
#include "hw/core/tcg-cpu-ops.h"
106
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
115
107
global anyextern
116
static struct TCGCPUOps alpha_tcg_ops = {
108
117
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
109
flds = []
118
#ifndef CONFIG_USER_ONLY
110
+ types = []
119
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
111
extern = False
120
dc->vmsd = &vmstate_alpha_cpu;
112
- for t in toks:
121
+ cc->sysemu_ops = &alpha_sysemu_ops;
113
- if re.fullmatch('!extern', t):
122
#endif
114
+ for n in toks:
123
cc->disas_set_info = alpha_cpu_disas_set_info;
115
+ if re.fullmatch('!extern', n):
124
116
extern = True
125
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
117
anyextern = True
126
index XXXXXXX..XXXXXXX 100644
118
continue
127
--- a/target/arm/cpu.c
119
- if not re.fullmatch(re_C_ident, t):
128
+++ b/target/arm/cpu.c
120
- error(lineno, f'invalid argument set token "{t}"')
129
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
121
- if t in flds:
130
return g_strdup("arm");
122
- error(lineno, f'duplicate argument "{t}"')
131
}
123
- flds.append(t)
132
124
+ if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
133
+#ifndef CONFIG_USER_ONLY
125
+ (n, t) = n.split(':')
134
+#include "hw/core/sysemu-cpu-ops.h"
126
+ elif re.fullmatch(re_C_ident, n):
135
+
127
+ t = 'int'
136
+static const struct SysemuCPUOps arm_sysemu_ops = {
128
+ else:
137
+};
129
+ error(lineno, f'invalid argument set token "{n}"')
138
+#endif
130
+ if n in flds:
139
+
131
+ error(lineno, f'duplicate argument "{n}"')
140
#ifdef CONFIG_TCG
132
+ flds.append(n)
141
static struct TCGCPUOps arm_tcg_ops = {
133
+ types.append(t)
142
.initialize = arm_translate_init,
134
143
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
135
if name in arguments:
144
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
136
error(lineno, 'duplicate argument set', name)
145
cc->write_elf64_note = arm_cpu_write_elf64_note;
137
- arguments[name] = Arguments(name, flds, extern)
146
cc->write_elf32_note = arm_cpu_write_elf32_note;
138
+ arguments[name] = Arguments(name, flds, types, extern)
147
+ cc->sysemu_ops = &arm_sysemu_ops;
139
# end parse_arguments
148
#endif
140
149
cc->gdb_num_core_regs = 26;
141
150
cc->gdb_core_xml_file = "arm-core.xml";
142
@@ -XXX,XX +XXX,XX @@ def infer_argument_set(flds):
151
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
143
global decode_function
152
index XXXXXXX..XXXXXXX 100644
144
153
--- a/target/avr/cpu.c
145
for arg in arguments.values():
154
+++ b/target/avr/cpu.c
146
- if eq_fields_for_args(flds, arg.fields):
155
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
147
+ if eq_fields_for_args(flds, arg):
156
qemu_fprintf(f, "\n");
148
return arg
157
}
149
158
150
name = decode_function + str(len(arguments))
159
+#include "hw/core/sysemu-cpu-ops.h"
151
- arg = Arguments(name, flds.keys(), False)
160
+
152
+ arg = Arguments(name, flds.keys(), ['int'] * len(flds), False)
161
+static const struct SysemuCPUOps avr_sysemu_ops = {
153
arguments[name] = arg
162
+};
154
return arg
163
+
155
164
#include "hw/core/tcg-cpu-ops.h"
165
166
static struct TCGCPUOps avr_tcg_ops = {
167
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
168
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
169
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
170
dc->vmsd = &vms_avr_cpu;
171
+ cc->sysemu_ops = &avr_sysemu_ops;
172
cc->disas_set_info = avr_cpu_disas_set_info;
173
cc->gdb_read_register = avr_cpu_gdb_read_register;
174
cc->gdb_write_register = avr_cpu_gdb_write_register;
175
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/target/cris/cpu.c
178
+++ b/target/cris/cpu.c
179
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_initfn(Object *obj)
180
#endif
181
}
182
183
+#ifndef CONFIG_USER_ONLY
184
+#include "hw/core/sysemu-cpu-ops.h"
185
+
186
+static const struct SysemuCPUOps cris_sysemu_ops = {
187
+};
188
+#endif
189
+
190
#include "hw/core/tcg-cpu-ops.h"
191
192
static struct TCGCPUOps crisv10_tcg_ops = {
193
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
194
#ifndef CONFIG_USER_ONLY
195
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
196
dc->vmsd = &vmstate_cris_cpu;
197
+ cc->sysemu_ops = &cris_sysemu_ops;
198
#endif
199
200
cc->gdb_num_core_regs = 49;
201
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/target/hppa/cpu.c
204
+++ b/target/hppa/cpu.c
205
@@ -XXX,XX +XXX,XX @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
206
return object_class_by_name(TYPE_HPPA_CPU);
207
}
208
209
+#ifndef CONFIG_USER_ONLY
210
+#include "hw/core/sysemu-cpu-ops.h"
211
+
212
+static const struct SysemuCPUOps hppa_sysemu_ops = {
213
+};
214
+#endif
215
+
216
#include "hw/core/tcg-cpu-ops.h"
217
218
static struct TCGCPUOps hppa_tcg_ops = {
219
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
220
#ifndef CONFIG_USER_ONLY
221
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
222
dc->vmsd = &vmstate_hppa_cpu;
223
+ cc->sysemu_ops = &hppa_sysemu_ops;
224
#endif
225
cc->disas_set_info = hppa_cpu_disas_set_info;
226
cc->gdb_num_core_regs = 128;
227
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/target/i386/cpu.c
230
+++ b/target/i386/cpu.c
231
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
232
DEFINE_PROP_END_OF_LIST()
233
};
234
235
+#ifndef CONFIG_USER_ONLY
236
+#include "hw/core/sysemu-cpu-ops.h"
237
+
238
+static const struct SysemuCPUOps i386_sysemu_ops = {
239
+};
240
+#endif
241
+
242
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
243
{
244
X86CPUClass *xcc = X86_CPU_CLASS(oc);
245
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
246
cc->write_elf32_note = x86_cpu_write_elf32_note;
247
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
248
cc->legacy_vmsd = &vmstate_x86_cpu;
249
+ cc->sysemu_ops = &i386_sysemu_ops;
250
#endif /* !CONFIG_USER_ONLY */
251
252
cc->gdb_arch_name = x86_gdb_arch_name;
253
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
254
index XXXXXXX..XXXXXXX 100644
255
--- a/target/m68k/cpu.c
256
+++ b/target/m68k/cpu.c
257
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m68k_cpu = {
258
};
259
#endif
260
261
+#ifndef CONFIG_USER_ONLY
262
+#include "hw/core/sysemu-cpu-ops.h"
263
+
264
+static const struct SysemuCPUOps m68k_sysemu_ops = {
265
+};
266
+#endif
267
+
268
#include "hw/core/tcg-cpu-ops.h"
269
270
static struct TCGCPUOps m68k_tcg_ops = {
271
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
272
#if defined(CONFIG_SOFTMMU)
273
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
274
dc->vmsd = &vmstate_m68k_cpu;
275
+ cc->sysemu_ops = &m68k_sysemu_ops;
276
#endif
277
cc->disas_set_info = m68k_cpu_disas_set_info;
278
279
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
280
index XXXXXXX..XXXXXXX 100644
281
--- a/target/microblaze/cpu.c
282
+++ b/target/microblaze/cpu.c
283
@@ -XXX,XX +XXX,XX @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
284
return object_class_by_name(TYPE_MICROBLAZE_CPU);
285
}
286
287
+#ifndef CONFIG_USER_ONLY
288
+#include "hw/core/sysemu-cpu-ops.h"
289
+
290
+static const struct SysemuCPUOps mb_sysemu_ops = {
291
+};
292
+#endif
293
+
294
#include "hw/core/tcg-cpu-ops.h"
295
296
static struct TCGCPUOps mb_tcg_ops = {
297
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
298
#ifndef CONFIG_USER_ONLY
299
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
300
dc->vmsd = &vmstate_mb_cpu;
301
+ cc->sysemu_ops = &mb_sysemu_ops;
302
#endif
303
device_class_set_props(dc, mb_properties);
304
cc->gdb_num_core_regs = 32 + 27;
305
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
306
index XXXXXXX..XXXXXXX 100644
307
--- a/target/mips/cpu.c
308
+++ b/target/mips/cpu.c
309
@@ -XXX,XX +XXX,XX @@ static Property mips_cpu_properties[] = {
310
DEFINE_PROP_END_OF_LIST()
311
};
312
313
+#ifndef CONFIG_USER_ONLY
314
+#include "hw/core/sysemu-cpu-ops.h"
315
+
316
+static const struct SysemuCPUOps mips_sysemu_ops = {
317
+};
318
+#endif
319
+
320
#ifdef CONFIG_TCG
321
#include "hw/core/tcg-cpu-ops.h"
322
/*
323
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
324
#ifndef CONFIG_USER_ONLY
325
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
326
cc->legacy_vmsd = &vmstate_mips_cpu;
327
+ cc->sysemu_ops = &mips_sysemu_ops;
328
#endif
329
cc->disas_set_info = mips_cpu_disas_set_info;
330
cc->gdb_num_core_regs = 73;
331
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
332
index XXXXXXX..XXXXXXX 100644
333
--- a/target/nios2/cpu.c
334
+++ b/target/nios2/cpu.c
335
@@ -XXX,XX +XXX,XX @@ static Property nios2_properties[] = {
336
DEFINE_PROP_END_OF_LIST(),
337
};
338
339
+#ifndef CONFIG_USER_ONLY
340
+#include "hw/core/sysemu-cpu-ops.h"
341
+
342
+static const struct SysemuCPUOps nios2_sysemu_ops = {
343
+};
344
+#endif
345
+
346
#include "hw/core/tcg-cpu-ops.h"
347
348
static struct TCGCPUOps nios2_tcg_ops = {
349
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
350
cc->disas_set_info = nios2_cpu_disas_set_info;
351
#ifndef CONFIG_USER_ONLY
352
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
353
+ cc->sysemu_ops = &nios2_sysemu_ops;
354
#endif
355
cc->gdb_read_register = nios2_cpu_gdb_read_register;
356
cc->gdb_write_register = nios2_cpu_gdb_write_register;
357
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
358
index XXXXXXX..XXXXXXX 100644
359
--- a/target/openrisc/cpu.c
360
+++ b/target/openrisc/cpu.c
361
@@ -XXX,XX +XXX,XX @@ static void openrisc_any_initfn(Object *obj)
362
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
363
}
364
365
+#ifndef CONFIG_USER_ONLY
366
+#include "hw/core/sysemu-cpu-ops.h"
367
+
368
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
369
+};
370
+#endif
371
+
372
#include "hw/core/tcg-cpu-ops.h"
373
374
static struct TCGCPUOps openrisc_tcg_ops = {
375
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
376
#ifndef CONFIG_USER_ONLY
377
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
378
dc->vmsd = &vmstate_openrisc_cpu;
379
+ cc->sysemu_ops = &openrisc_sysemu_ops;
380
#endif
381
cc->gdb_num_core_regs = 32 + 3;
382
cc->disas_set_info = openrisc_disas_set_info;
383
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
384
index XXXXXXX..XXXXXXX 100644
385
--- a/target/ppc/cpu_init.c
386
+++ b/target/ppc/cpu_init.c
387
@@ -XXX,XX +XXX,XX @@ static Property ppc_cpu_properties[] = {
388
DEFINE_PROP_END_OF_LIST(),
389
};
390
391
+#ifndef CONFIG_USER_ONLY
392
+#include "hw/core/sysemu-cpu-ops.h"
393
+
394
+static const struct SysemuCPUOps ppc_sysemu_ops = {
395
+};
396
+#endif
397
+
398
#ifdef CONFIG_TCG
399
#include "hw/core/tcg-cpu-ops.h"
400
401
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
402
#ifndef CONFIG_USER_ONLY
403
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
404
cc->legacy_vmsd = &vmstate_ppc_cpu;
405
+ cc->sysemu_ops = &ppc_sysemu_ops;
406
#endif
407
#if defined(CONFIG_SOFTMMU)
408
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
409
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
410
index XXXXXXX..XXXXXXX 100644
411
--- a/target/riscv/cpu.c
412
+++ b/target/riscv/cpu.c
413
@@ -XXX,XX +XXX,XX @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
414
return NULL;
415
}
416
417
+#ifndef CONFIG_USER_ONLY
418
+#include "hw/core/sysemu-cpu-ops.h"
419
+
420
+static const struct SysemuCPUOps riscv_sysemu_ops = {
421
+};
422
+#endif
423
+
424
#include "hw/core/tcg-cpu-ops.h"
425
426
static struct TCGCPUOps riscv_tcg_ops = {
427
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
428
#ifndef CONFIG_USER_ONLY
429
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
430
cc->legacy_vmsd = &vmstate_riscv_cpu;
431
+ cc->sysemu_ops = &riscv_sysemu_ops;
432
cc->write_elf64_note = riscv_cpu_write_elf64_note;
433
cc->write_elf32_note = riscv_cpu_write_elf32_note;
434
#endif
435
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/target/rx/cpu.c
438
+++ b/target/rx/cpu.c
439
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_init(Object *obj)
440
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
441
}
442
443
+#ifndef CONFIG_USER_ONLY
444
+#include "hw/core/sysemu-cpu-ops.h"
445
+
446
+static const struct SysemuCPUOps rx_sysemu_ops = {
447
+};
448
+#endif
449
+
450
#include "hw/core/tcg-cpu-ops.h"
451
452
static struct TCGCPUOps rx_tcg_ops = {
453
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
454
cc->dump_state = rx_cpu_dump_state;
455
cc->set_pc = rx_cpu_set_pc;
456
457
+#ifndef CONFIG_USER_ONLY
458
+ cc->sysemu_ops = &rx_sysemu_ops;
459
+#endif
460
cc->gdb_read_register = rx_cpu_gdb_read_register;
461
cc->gdb_write_register = rx_cpu_gdb_write_register;
462
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
463
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
464
index XXXXXXX..XXXXXXX 100644
465
--- a/target/s390x/cpu.c
466
+++ b/target/s390x/cpu.c
467
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_full(DeviceState *dev)
468
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
469
}
470
471
+#ifndef CONFIG_USER_ONLY
472
+#include "hw/core/sysemu-cpu-ops.h"
473
+
474
+static const struct SysemuCPUOps s390_sysemu_ops = {
475
+};
476
+#endif
477
+
478
#ifdef CONFIG_TCG
479
#include "hw/core/tcg-cpu-ops.h"
480
481
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
482
cc->legacy_vmsd = &vmstate_s390_cpu;
483
cc->get_crash_info = s390_cpu_get_crash_info;
484
cc->write_elf64_note = s390_cpu_write_elf64_note;
485
+ cc->sysemu_ops = &s390_sysemu_ops;
486
#endif
487
cc->disas_set_info = s390_cpu_disas_set_info;
488
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
489
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
490
index XXXXXXX..XXXXXXX 100644
491
--- a/target/sh4/cpu.c
492
+++ b/target/sh4/cpu.c
493
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sh_cpu = {
494
.name = "cpu",
495
.unmigratable = 1,
496
};
497
+
498
+#include "hw/core/sysemu-cpu-ops.h"
499
+
500
+static const struct SysemuCPUOps sh4_sysemu_ops = {
501
+};
502
#endif
503
504
#include "hw/core/tcg-cpu-ops.h"
505
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
506
cc->gdb_write_register = superh_cpu_gdb_write_register;
507
#ifndef CONFIG_USER_ONLY
508
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
509
+ cc->sysemu_ops = &sh4_sysemu_ops;
510
dc->vmsd = &vmstate_sh_cpu;
511
#endif
512
cc->disas_set_info = superh_cpu_disas_set_info;
513
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/target/sparc/cpu.c
516
+++ b/target/sparc/cpu.c
517
@@ -XXX,XX +XXX,XX @@ static Property sparc_cpu_properties[] = {
518
DEFINE_PROP_END_OF_LIST()
519
};
520
521
+#ifndef CONFIG_USER_ONLY
522
+#include "hw/core/sysemu-cpu-ops.h"
523
+
524
+static const struct SysemuCPUOps sparc_sysemu_ops = {
525
+};
526
+#endif
527
+
528
#ifdef CONFIG_TCG
529
#include "hw/core/tcg-cpu-ops.h"
530
531
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
532
#ifndef CONFIG_USER_ONLY
533
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
534
cc->legacy_vmsd = &vmstate_sparc_cpu;
535
+ cc->sysemu_ops = &sparc_sysemu_ops;
536
#endif
537
cc->disas_set_info = cpu_sparc_disas_set_info;
538
539
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/target/tricore/cpu.c
542
+++ b/target/tricore/cpu.c
543
@@ -XXX,XX +XXX,XX @@ static void tc27x_initfn(Object *obj)
544
set_feature(&cpu->env, TRICORE_FEATURE_161);
545
}
546
547
+#include "hw/core/sysemu-cpu-ops.h"
548
+
549
+static const struct SysemuCPUOps tricore_sysemu_ops = {
550
+};
551
+
552
#include "hw/core/tcg-cpu-ops.h"
553
554
static struct TCGCPUOps tricore_tcg_ops = {
555
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
556
cc->dump_state = tricore_cpu_dump_state;
557
cc->set_pc = tricore_cpu_set_pc;
558
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
559
+ cc->sysemu_ops = &tricore_sysemu_ops;
560
cc->tcg_ops = &tricore_tcg_ops;
561
}
562
563
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
564
index XXXXXXX..XXXXXXX 100644
565
--- a/target/xtensa/cpu.c
566
+++ b/target/xtensa/cpu.c
567
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_xtensa_cpu = {
568
.name = "cpu",
569
.unmigratable = 1,
570
};
571
+
572
+#include "hw/core/sysemu-cpu-ops.h"
573
+
574
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
575
+};
576
#endif
577
578
#include "hw/core/tcg-cpu-ops.h"
579
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
580
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
581
cc->gdb_stop_before_watchpoint = true;
582
#ifndef CONFIG_USER_ONLY
583
+ cc->sysemu_ops = &xtensa_sysemu_ops;
584
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
585
dc->vmsd = &vmstate_xtensa_cpu;
586
#endif
156
--
587
--
157
2.25.1
588
2.25.1
158
589
159
590
diff view generated by jsdifflib
New patch
[PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps
1
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
3
Migration is specific to system emulation.
4
5
- Move the CPUClass::vmsd field to SysemuCPUOps,
6
- restrict VMSTATE_CPU() macro to sysemu,
7
- vmstate_dummy is now unused, remove it.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20210517105140.1062037-16-f4bug@amsat.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
include/hw/core/cpu.h | 8 ++------
15
include/hw/core/sysemu-cpu-ops.h | 6 ++++++
16
include/migration/vmstate.h | 2 --
17
cpu.c | 15 +++++++--------
18
stubs/vmstate.c | 2 --
19
target/arm/cpu.c | 2 +-
20
target/i386/cpu.c | 2 +-
21
target/mips/cpu.c | 2 +-
22
target/ppc/cpu_init.c | 2 +-
23
target/riscv/cpu.c | 2 +-
24
target/s390x/cpu.c | 2 +-
25
target/sparc/cpu.c | 2 +-
26
12 files changed, 22 insertions(+), 25 deletions(-)
27
28
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/core/cpu.h
31
+++ b/include/hw/core/cpu.h
32
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
33
* 32-bit VM coredump.
34
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
35
* note to a 32-bit VM coredump.
36
- * @legacy_vmsd: Legacy state description for migration.
37
- * Do not use in new targets, use #DeviceClass::vmsd instead.
38
* @gdb_num_core_regs: Number of core registers accessible to GDB.
39
* @gdb_core_xml_file: File name for core registers GDB XML description.
40
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
41
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
42
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
43
void *opaque);
44
45
- const VMStateDescription *legacy_vmsd;
46
const char *gdb_core_xml_file;
47
gchar * (*gdb_arch_name)(CPUState *cpu);
48
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
49
@@ -XXX,XX +XXX,XX @@ bool target_words_bigendian(void);
50
#ifdef NEED_CPU_H
51
52
#ifdef CONFIG_SOFTMMU
53
+
54
extern const VMStateDescription vmstate_cpu_common;
55
-#else
56
-#define vmstate_cpu_common vmstate_dummy
57
-#endif
58
59
#define VMSTATE_CPU() { \
60
.name = "parent_obj", \
61
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_cpu_common;
62
.flags = VMS_STRUCT, \
63
.offset = 0, \
64
}
65
+#endif /* CONFIG_SOFTMMU */
66
67
#endif /* NEED_CPU_H */
68
69
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/core/sysemu-cpu-ops.h
72
+++ b/include/hw/core/sysemu-cpu-ops.h
73
@@ -XXX,XX +XXX,XX @@
74
* struct SysemuCPUOps: System operations specific to a CPU class
75
*/
76
typedef struct SysemuCPUOps {
77
+ /**
78
+ * @legacy_vmsd: Legacy state for migration.
79
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
80
+ */
81
+ const VMStateDescription *legacy_vmsd;
82
+
83
} SysemuCPUOps;
84
85
#endif /* SYSEMU_CPU_OPS_H */
86
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
87
index XXXXXXX..XXXXXXX 100644
88
--- a/include/migration/vmstate.h
89
+++ b/include/migration/vmstate.h
90
@@ -XXX,XX +XXX,XX @@ struct VMStateDescription {
91
const VMStateDescription **subsections;
92
};
93
94
-extern const VMStateDescription vmstate_dummy;
95
-
96
extern const VMStateInfo vmstate_info_bool;
97
98
extern const VMStateInfo vmstate_info_int8;
99
diff --git a/cpu.c b/cpu.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/cpu.c
102
+++ b/cpu.c
103
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_cpu_common = {
104
105
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
106
{
107
+#ifndef CONFIG_USER_ONLY
108
CPUClass *cc = CPU_GET_CLASS(cpu);
109
+#endif
110
111
cpu_list_add(cpu);
112
if (!accel_cpu_realizefn(cpu, errp)) {
113
@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
114
#ifdef CONFIG_USER_ONLY
115
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
116
qdev_get_vmsd(DEVICE(cpu))->unmigratable);
117
- assert(cc->legacy_vmsd == NULL);
118
#else
119
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
120
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
121
}
122
- if (cc->legacy_vmsd != NULL) {
123
- vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
124
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
125
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
126
}
127
#endif /* CONFIG_USER_ONLY */
128
}
129
130
void cpu_exec_unrealizefn(CPUState *cpu)
131
{
132
+#ifndef CONFIG_USER_ONLY
133
CPUClass *cc = CPU_GET_CLASS(cpu);
134
135
-#ifdef CONFIG_USER_ONLY
136
- assert(cc->legacy_vmsd == NULL);
137
-#else
138
- if (cc->legacy_vmsd != NULL) {
139
- vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
140
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
141
+ vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
142
}
143
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
144
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
145
diff --git a/stubs/vmstate.c b/stubs/vmstate.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/stubs/vmstate.c
148
+++ b/stubs/vmstate.c
149
@@ -XXX,XX +XXX,XX @@
150
#include "qemu/osdep.h"
151
#include "migration/vmstate.h"
152
153
-const VMStateDescription vmstate_dummy = {};
154
-
155
int vmstate_register_with_alias_id(VMStateIf *obj,
156
uint32_t instance_id,
157
const VMStateDescription *vmsd,
158
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/cpu.c
161
+++ b/target/arm/cpu.c
162
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
163
#include "hw/core/sysemu-cpu-ops.h"
164
165
static const struct SysemuCPUOps arm_sysemu_ops = {
166
+ .legacy_vmsd = &vmstate_arm_cpu,
167
};
168
#endif
169
170
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
171
#ifndef CONFIG_USER_ONLY
172
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
173
cc->asidx_from_attrs = arm_asidx_from_attrs;
174
- cc->legacy_vmsd = &vmstate_arm_cpu;
175
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
176
cc->write_elf64_note = arm_cpu_write_elf64_note;
177
cc->write_elf32_note = arm_cpu_write_elf32_note;
178
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
179
index XXXXXXX..XXXXXXX 100644
180
--- a/target/i386/cpu.c
181
+++ b/target/i386/cpu.c
182
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
183
#include "hw/core/sysemu-cpu-ops.h"
184
185
static const struct SysemuCPUOps i386_sysemu_ops = {
186
+ .legacy_vmsd = &vmstate_x86_cpu,
187
};
188
#endif
189
190
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
191
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
192
cc->write_elf32_note = x86_cpu_write_elf32_note;
193
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
194
- cc->legacy_vmsd = &vmstate_x86_cpu;
195
cc->sysemu_ops = &i386_sysemu_ops;
196
#endif /* !CONFIG_USER_ONLY */
197
198
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/target/mips/cpu.c
201
+++ b/target/mips/cpu.c
202
@@ -XXX,XX +XXX,XX @@ static Property mips_cpu_properties[] = {
203
#include "hw/core/sysemu-cpu-ops.h"
204
205
static const struct SysemuCPUOps mips_sysemu_ops = {
206
+ .legacy_vmsd = &vmstate_mips_cpu,
207
};
208
#endif
209
210
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
211
cc->gdb_write_register = mips_cpu_gdb_write_register;
212
#ifndef CONFIG_USER_ONLY
213
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
214
- cc->legacy_vmsd = &vmstate_mips_cpu;
215
cc->sysemu_ops = &mips_sysemu_ops;
216
#endif
217
cc->disas_set_info = mips_cpu_disas_set_info;
218
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
219
index XXXXXXX..XXXXXXX 100644
220
--- a/target/ppc/cpu_init.c
221
+++ b/target/ppc/cpu_init.c
222
@@ -XXX,XX +XXX,XX @@ static Property ppc_cpu_properties[] = {
223
#include "hw/core/sysemu-cpu-ops.h"
224
225
static const struct SysemuCPUOps ppc_sysemu_ops = {
226
+ .legacy_vmsd = &vmstate_ppc_cpu,
227
};
228
#endif
229
230
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
231
cc->gdb_write_register = ppc_cpu_gdb_write_register;
232
#ifndef CONFIG_USER_ONLY
233
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
234
- cc->legacy_vmsd = &vmstate_ppc_cpu;
235
cc->sysemu_ops = &ppc_sysemu_ops;
236
#endif
237
#if defined(CONFIG_SOFTMMU)
238
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
239
index XXXXXXX..XXXXXXX 100644
240
--- a/target/riscv/cpu.c
241
+++ b/target/riscv/cpu.c
242
@@ -XXX,XX +XXX,XX @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
243
#include "hw/core/sysemu-cpu-ops.h"
244
245
static const struct SysemuCPUOps riscv_sysemu_ops = {
246
+ .legacy_vmsd = &vmstate_riscv_cpu,
247
};
248
#endif
249
250
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
251
cc->disas_set_info = riscv_cpu_disas_set_info;
252
#ifndef CONFIG_USER_ONLY
253
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
254
- cc->legacy_vmsd = &vmstate_riscv_cpu;
255
cc->sysemu_ops = &riscv_sysemu_ops;
256
cc->write_elf64_note = riscv_cpu_write_elf64_note;
257
cc->write_elf32_note = riscv_cpu_write_elf32_note;
258
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
259
index XXXXXXX..XXXXXXX 100644
260
--- a/target/s390x/cpu.c
261
+++ b/target/s390x/cpu.c
262
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_full(DeviceState *dev)
263
#include "hw/core/sysemu-cpu-ops.h"
264
265
static const struct SysemuCPUOps s390_sysemu_ops = {
266
+ .legacy_vmsd = &vmstate_s390_cpu,
267
};
268
#endif
269
270
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
271
cc->gdb_write_register = s390_cpu_gdb_write_register;
272
#ifndef CONFIG_USER_ONLY
273
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
274
- cc->legacy_vmsd = &vmstate_s390_cpu;
275
cc->get_crash_info = s390_cpu_get_crash_info;
276
cc->write_elf64_note = s390_cpu_write_elf64_note;
277
cc->sysemu_ops = &s390_sysemu_ops;
278
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
279
index XXXXXXX..XXXXXXX 100644
280
--- a/target/sparc/cpu.c
281
+++ b/target/sparc/cpu.c
282
@@ -XXX,XX +XXX,XX @@ static Property sparc_cpu_properties[] = {
283
#include "hw/core/sysemu-cpu-ops.h"
284
285
static const struct SysemuCPUOps sparc_sysemu_ops = {
286
+ .legacy_vmsd = &vmstate_sparc_cpu,
287
};
288
#endif
289
290
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
291
cc->gdb_write_register = sparc_cpu_gdb_write_register;
292
#ifndef CONFIG_USER_ONLY
293
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
294
- cc->legacy_vmsd = &vmstate_sparc_cpu;
295
cc->sysemu_ops = &sparc_sysemu_ops;
296
#endif
297
cc->disas_set_info = cpu_sparc_disas_set_info;
298
--
299
2.25.1
300
301
diff view generated by jsdifflib
New patch
[PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
VirtIO devices are only meaningful with system emulation.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-Id: <20210517105140.1062037-17-f4bug@amsat.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/hw/core/cpu.h | 5 -----
11
include/hw/core/sysemu-cpu-ops.h | 9 +++++++++
12
hw/core/cpu-sysemu.c | 5 +++--
13
target/arm/cpu.c | 2 +-
14
target/ppc/cpu_init.c | 4 +---
15
5 files changed, 14 insertions(+), 11 deletions(-)
16
17
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/core/cpu.h
20
+++ b/include/hw/core/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
22
* @parse_features: Callback to parse command line arguments.
23
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
24
* @has_work: Callback for checking if there is work to do.
25
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
26
- * runtime configurable endianness is currently big-endian. Non-configurable
27
- * CPUs can use the default implementation of this method. This method should
28
- * not be used by any callers other than the pre-1.0 virtio devices.
29
* @memory_rw_debug: Callback for GDB memory access.
30
* @dump_state: Callback for dumping state.
31
* @dump_statistics: Callback for dumping statistics.
32
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
33
34
int reset_dump_flags;
35
bool (*has_work)(CPUState *cpu);
36
- bool (*virtio_is_big_endian)(CPUState *cpu);
37
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
38
uint8_t *buf, int len, bool is_write);
39
void (*dump_state)(CPUState *cpu, FILE *, int flags);
40
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/core/sysemu-cpu-ops.h
43
+++ b/include/hw/core/sysemu-cpu-ops.h
44
@@ -XXX,XX +XXX,XX @@
45
* struct SysemuCPUOps: System operations specific to a CPU class
46
*/
47
typedef struct SysemuCPUOps {
48
+ /**
49
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
50
+ * runtime configurable endianness is currently big-endian.
51
+ * Non-configurable CPUs can use the default implementation of this method.
52
+ * This method should not be used by any callers other than the pre-1.0
53
+ * virtio devices.
54
+ */
55
+ bool (*virtio_is_big_endian)(CPUState *cpu);
56
+
57
/**
58
* @legacy_vmsd: Legacy state for migration.
59
* Do not use in new targets, use #DeviceClass::vmsd instead.
60
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/core/cpu-sysemu.c
63
+++ b/hw/core/cpu-sysemu.c
64
@@ -XXX,XX +XXX,XX @@
65
#include "qemu/osdep.h"
66
#include "qapi/error.h"
67
#include "hw/core/cpu.h"
68
+#include "hw/core/sysemu-cpu-ops.h"
69
70
bool cpu_paging_enabled(const CPUState *cpu)
71
{
72
@@ -XXX,XX +XXX,XX @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
73
{
74
CPUClass *cc = CPU_GET_CLASS(cpu);
75
76
- if (cc->virtio_is_big_endian) {
77
- return cc->virtio_is_big_endian(cpu);
78
+ if (cc->sysemu_ops->virtio_is_big_endian) {
79
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
80
}
81
return target_words_bigendian();
82
}
83
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/cpu.c
86
+++ b/target/arm/cpu.c
87
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
88
#include "hw/core/sysemu-cpu-ops.h"
89
90
static const struct SysemuCPUOps arm_sysemu_ops = {
91
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
92
.legacy_vmsd = &vmstate_arm_cpu,
93
};
94
#endif
95
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
96
#ifndef CONFIG_USER_ONLY
97
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
98
cc->asidx_from_attrs = arm_asidx_from_attrs;
99
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
100
cc->write_elf64_note = arm_cpu_write_elf64_note;
101
cc->write_elf32_note = arm_cpu_write_elf32_note;
102
cc->sysemu_ops = &arm_sysemu_ops;
103
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/ppc/cpu_init.c
106
+++ b/target/ppc/cpu_init.c
107
@@ -XXX,XX +XXX,XX @@ static Property ppc_cpu_properties[] = {
108
#include "hw/core/sysemu-cpu-ops.h"
109
110
static const struct SysemuCPUOps ppc_sysemu_ops = {
111
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
112
.legacy_vmsd = &vmstate_ppc_cpu,
113
};
114
#endif
115
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
116
cc->gdb_core_xml_file = "power64-core.xml";
117
#else
118
cc->gdb_core_xml_file = "power-core.xml";
119
-#endif
120
-#ifndef CONFIG_USER_ONLY
121
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
122
#endif
123
cc->disas_set_info = ppc_disas_set_info;
124
125
--
126
2.25.1
127
128
diff view generated by jsdifflib
New patch
[PULL 24/31] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
cpu_get_crash_info() is called on GUEST_PANICKED events,
4
which only occur in system emulation.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20210517105140.1062037-18-f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/hw/core/cpu.h | 1 -
12
include/hw/core/sysemu-cpu-ops.h | 5 +++++
13
hw/core/cpu-sysemu.c | 4 ++--
14
target/i386/cpu.c | 2 +-
15
target/s390x/cpu.c | 2 +-
16
5 files changed, 9 insertions(+), 5 deletions(-)
17
18
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/core/cpu.h
21
+++ b/include/hw/core/cpu.h
22
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
23
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
24
uint8_t *buf, int len, bool is_write);
25
void (*dump_state)(CPUState *cpu, FILE *, int flags);
26
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
27
void (*dump_statistics)(CPUState *cpu, int flags);
28
int64_t (*get_arch_id)(CPUState *cpu);
29
bool (*get_paging_enabled)(const CPUState *cpu);
30
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/core/sysemu-cpu-ops.h
33
+++ b/include/hw/core/sysemu-cpu-ops.h
34
@@ -XXX,XX +XXX,XX @@
35
* struct SysemuCPUOps: System operations specific to a CPU class
36
*/
37
typedef struct SysemuCPUOps {
38
+ /**
39
+ * @get_crash_info: Callback for reporting guest crash information in
40
+ * GUEST_PANICKED events.
41
+ */
42
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
43
/**
44
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
45
* runtime configurable endianness is currently big-endian.
46
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/core/cpu-sysemu.c
49
+++ b/hw/core/cpu-sysemu.c
50
@@ -XXX,XX +XXX,XX @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
51
CPUClass *cc = CPU_GET_CLASS(cpu);
52
GuestPanicInformation *res = NULL;
53
54
- if (cc->get_crash_info) {
55
- res = cc->get_crash_info(cpu);
56
+ if (cc->sysemu_ops->get_crash_info) {
57
+ res = cc->sysemu_ops->get_crash_info(cpu);
58
}
59
return res;
60
}
61
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/i386/cpu.c
64
+++ b/target/i386/cpu.c
65
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
66
#include "hw/core/sysemu-cpu-ops.h"
67
68
static const struct SysemuCPUOps i386_sysemu_ops = {
69
+ .get_crash_info = x86_cpu_get_crash_info,
70
.legacy_vmsd = &vmstate_x86_cpu,
71
};
72
#endif
73
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
74
cc->asidx_from_attrs = x86_asidx_from_attrs;
75
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
76
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
77
- cc->get_crash_info = x86_cpu_get_crash_info;
78
cc->write_elf64_note = x86_cpu_write_elf64_note;
79
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
80
cc->write_elf32_note = x86_cpu_write_elf32_note;
81
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/s390x/cpu.c
84
+++ b/target/s390x/cpu.c
85
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_full(DeviceState *dev)
86
#include "hw/core/sysemu-cpu-ops.h"
87
88
static const struct SysemuCPUOps s390_sysemu_ops = {
89
+ .get_crash_info = s390_cpu_get_crash_info,
90
.legacy_vmsd = &vmstate_s390_cpu,
91
};
92
#endif
93
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
94
cc->gdb_write_register = s390_cpu_gdb_write_register;
95
#ifndef CONFIG_USER_ONLY
96
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
97
- cc->get_crash_info = s390_cpu_get_crash_info;
98
cc->write_elf64_note = s390_cpu_write_elf64_note;
99
cc->sysemu_ops = &s390_sysemu_ops;
100
#endif
101
--
102
2.25.1
103
104
diff view generated by jsdifflib
[PULL 1/5] exec: Remove accel/tcg/ from include paths
[PULL 25/31] cpu: Move CPUClass::write_elf* to SysemuCPUOps
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
When TCG is enabled, the accel/tcg/ include path is added to the
3
The write_elf*() handlers are used to dump vmcore images.
4
project global include search list. This accel/tcg/ directory
4
This feature is only meaningful for system emulation.
5
contains a header named "internal.h" which, while intented to
6
be internal to accel/tcg/, is accessible by all files compiled
7
when TCG is enabled. This might lead to problem with other
8
directories using the same "internal.h" header name:
9
10
$ git ls-files | fgrep /internal.h
11
accel/tcg/internal.h
12
include/hw/ide/internal.h
13
target/hexagon/internal.h
14
target/mips/internal.h
15
target/ppc/internal.h
16
target/s390x/internal.h
17
18
As we don't need to expose accel/tcg/ internals to the rest of
19
the code base, simplify by removing it from the include search
20
list, and include the accel/tcg/ public headers relative to the
21
project root search path (which is already in the generic include
22
search path).
23
5
24
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Claudio Fontana <cfontana@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-Id: <20210413081008.3409459-1-f4bug@amsat.org>
8
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org>
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
10
---
29
meson.build | 1 -
11
include/hw/core/cpu.h | 17 -----------------
30
include/exec/helper-gen.h | 4 ++--
12
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
31
include/exec/helper-proto.h | 4 ++--
13
hw/core/cpu-sysemu.c | 16 ++++++++--------
32
include/exec/helper-tcg.h | 4 ++--
14
target/arm/cpu.c | 4 ++--
33
4 files changed, 6 insertions(+), 7 deletions(-)
15
target/i386/cpu.c | 8 ++++----
34
16
target/ppc/cpu_init.c | 6 ++----
35
diff --git a/meson.build b/meson.build
17
target/riscv/cpu.c | 4 ++--
36
index XXXXXXX..XXXXXXX 100644
18
target/s390x/cpu.c | 2 +-
37
--- a/meson.build
19
8 files changed, 43 insertions(+), 38 deletions(-)
38
+++ b/meson.build
20
39
@@ -XXX,XX +XXX,XX @@ if not get_option('tcg').disabled()
21
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
40
tcg_arch = 'riscv'
22
index XXXXXXX..XXXXXXX 100644
41
endif
23
--- a/include/hw/core/cpu.h
42
add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch,
24
+++ b/include/hw/core/cpu.h
43
- '-iquote', meson.current_source_dir() / 'accel/tcg',
25
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
44
language: ['c', 'cpp', 'objc'])
26
* a memory access with the specified memory transaction attributes.
45
27
* @gdb_read_register: Callback for letting GDB read a register.
46
accelerators += 'CONFIG_TCG'
28
* @gdb_write_register: Callback for letting GDB write a register.
47
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
29
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
48
index XXXXXXX..XXXXXXX 100644
30
- * 64-bit VM coredump.
49
--- a/include/exec/helper-gen.h
31
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
50
+++ b/include/exec/helper-gen.h
32
- * note to a 32-bit VM coredump.
51
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
33
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
52
#include "helper.h"
34
- * 32-bit VM coredump.
53
#include "trace/generated-helpers.h"
35
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
54
#include "trace/generated-helpers-wrappers.h"
36
- * note to a 32-bit VM coredump.
55
-#include "tcg-runtime.h"
37
* @gdb_num_core_regs: Number of core registers accessible to GDB.
56
-#include "plugin-helpers.h"
38
* @gdb_core_xml_file: File name for core registers GDB XML description.
57
+#include "accel/tcg/tcg-runtime.h"
39
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
58
+#include "accel/tcg/plugin-helpers.h"
40
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
59
41
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
60
#undef DEF_HELPER_FLAGS_0
42
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
61
#undef DEF_HELPER_FLAGS_1
43
62
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
44
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
63
index XXXXXXX..XXXXXXX 100644
45
- int cpuid, void *opaque);
64
--- a/include/exec/helper-proto.h
46
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
65
+++ b/include/exec/helper-proto.h
47
- void *opaque);
66
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
48
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
67
49
- int cpuid, void *opaque);
68
#include "helper.h"
50
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
69
#include "trace/generated-helpers.h"
51
- void *opaque);
70
-#include "tcg-runtime.h"
52
-
71
-#include "plugin-helpers.h"
53
const char *gdb_core_xml_file;
72
+#include "accel/tcg/tcg-runtime.h"
54
gchar * (*gdb_arch_name)(CPUState *cpu);
73
+#include "accel/tcg/plugin-helpers.h"
55
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
74
56
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
75
#undef IN_HELPER_PROTO
57
index XXXXXXX..XXXXXXX 100644
76
58
--- a/include/hw/core/sysemu-cpu-ops.h
77
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
59
+++ b/include/hw/core/sysemu-cpu-ops.h
78
index XXXXXXX..XXXXXXX 100644
60
@@ -XXX,XX +XXX,XX @@ typedef struct SysemuCPUOps {
79
--- a/include/exec/helper-tcg.h
61
* GUEST_PANICKED events.
80
+++ b/include/exec/helper-tcg.h
62
*/
81
@@ -XXX,XX +XXX,XX @@
63
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
82
64
+ /**
83
#include "helper.h"
65
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
84
#include "trace/generated-helpers.h"
66
+ * 32-bit VM coredump.
85
-#include "tcg-runtime.h"
67
+ */
86
-#include "plugin-helpers.h"
68
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
87
+#include "accel/tcg/tcg-runtime.h"
69
+ int cpuid, void *opaque);
88
+#include "accel/tcg/plugin-helpers.h"
70
+ /**
89
71
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
90
#undef str
72
+ * 64-bit VM coredump.
91
#undef DEF_HELPER_FLAGS_0
73
+ */
74
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
75
+ int cpuid, void *opaque);
76
+ /**
77
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
78
+ * note to a 32-bit VM coredump.
79
+ */
80
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
81
+ void *opaque);
82
+ /**
83
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
84
+ * note to a 64-bit VM coredump.
85
+ */
86
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
87
+ void *opaque);
88
/**
89
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
90
* runtime configurable endianness is currently big-endian.
91
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/core/cpu-sysemu.c
94
+++ b/hw/core/cpu-sysemu.c
95
@@ -XXX,XX +XXX,XX @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
96
{
97
CPUClass *cc = CPU_GET_CLASS(cpu);
98
99
- if (!cc->write_elf32_qemunote) {
100
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
101
return 0;
102
}
103
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
104
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
105
}
106
107
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
108
@@ -XXX,XX +XXX,XX @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
109
{
110
CPUClass *cc = CPU_GET_CLASS(cpu);
111
112
- if (!cc->write_elf32_note) {
113
+ if (!cc->sysemu_ops->write_elf32_note) {
114
return -1;
115
}
116
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
117
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
118
}
119
120
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
121
@@ -XXX,XX +XXX,XX @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
122
{
123
CPUClass *cc = CPU_GET_CLASS(cpu);
124
125
- if (!cc->write_elf64_qemunote) {
126
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
127
return 0;
128
}
129
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
130
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
131
}
132
133
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
134
@@ -XXX,XX +XXX,XX @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
135
{
136
CPUClass *cc = CPU_GET_CLASS(cpu);
137
138
- if (!cc->write_elf64_note) {
139
+ if (!cc->sysemu_ops->write_elf64_note) {
140
return -1;
141
}
142
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
143
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
144
}
145
146
bool cpu_virtio_is_big_endian(CPUState *cpu)
147
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/target/arm/cpu.c
150
+++ b/target/arm/cpu.c
151
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
152
#include "hw/core/sysemu-cpu-ops.h"
153
154
static const struct SysemuCPUOps arm_sysemu_ops = {
155
+ .write_elf32_note = arm_cpu_write_elf32_note,
156
+ .write_elf64_note = arm_cpu_write_elf64_note,
157
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
158
.legacy_vmsd = &vmstate_arm_cpu,
159
};
160
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
161
#ifndef CONFIG_USER_ONLY
162
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
163
cc->asidx_from_attrs = arm_asidx_from_attrs;
164
- cc->write_elf64_note = arm_cpu_write_elf64_note;
165
- cc->write_elf32_note = arm_cpu_write_elf32_note;
166
cc->sysemu_ops = &arm_sysemu_ops;
167
#endif
168
cc->gdb_num_core_regs = 26;
169
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/target/i386/cpu.c
172
+++ b/target/i386/cpu.c
173
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
174
175
static const struct SysemuCPUOps i386_sysemu_ops = {
176
.get_crash_info = x86_cpu_get_crash_info,
177
+ .write_elf32_note = x86_cpu_write_elf32_note,
178
+ .write_elf64_note = x86_cpu_write_elf64_note,
179
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
180
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
181
.legacy_vmsd = &vmstate_x86_cpu,
182
};
183
#endif
184
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
185
cc->asidx_from_attrs = x86_asidx_from_attrs;
186
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
187
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
188
- cc->write_elf64_note = x86_cpu_write_elf64_note;
189
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
190
- cc->write_elf32_note = x86_cpu_write_elf32_note;
191
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
192
cc->sysemu_ops = &i386_sysemu_ops;
193
#endif /* !CONFIG_USER_ONLY */
194
195
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/target/ppc/cpu_init.c
198
+++ b/target/ppc/cpu_init.c
199
@@ -XXX,XX +XXX,XX @@ static Property ppc_cpu_properties[] = {
200
#include "hw/core/sysemu-cpu-ops.h"
201
202
static const struct SysemuCPUOps ppc_sysemu_ops = {
203
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
204
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
205
.virtio_is_big_endian = ppc_cpu_is_big_endian,
206
.legacy_vmsd = &vmstate_ppc_cpu,
207
};
208
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
209
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
210
cc->sysemu_ops = &ppc_sysemu_ops;
211
#endif
212
-#if defined(CONFIG_SOFTMMU)
213
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
214
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
215
-#endif
216
217
cc->gdb_num_core_regs = 71;
218
#ifndef CONFIG_USER_ONLY
219
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/target/riscv/cpu.c
222
+++ b/target/riscv/cpu.c
223
@@ -XXX,XX +XXX,XX @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
224
#include "hw/core/sysemu-cpu-ops.h"
225
226
static const struct SysemuCPUOps riscv_sysemu_ops = {
227
+ .write_elf64_note = riscv_cpu_write_elf64_note,
228
+ .write_elf32_note = riscv_cpu_write_elf32_note,
229
.legacy_vmsd = &vmstate_riscv_cpu,
230
};
231
#endif
232
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
233
#ifndef CONFIG_USER_ONLY
234
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
235
cc->sysemu_ops = &riscv_sysemu_ops;
236
- cc->write_elf64_note = riscv_cpu_write_elf64_note;
237
- cc->write_elf32_note = riscv_cpu_write_elf32_note;
238
#endif
239
cc->gdb_arch_name = riscv_gdb_arch_name;
240
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
241
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/target/s390x/cpu.c
244
+++ b/target/s390x/cpu.c
245
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_full(DeviceState *dev)
246
247
static const struct SysemuCPUOps s390_sysemu_ops = {
248
.get_crash_info = s390_cpu_get_crash_info,
249
+ .write_elf64_note = s390_cpu_write_elf64_note,
250
.legacy_vmsd = &vmstate_s390_cpu,
251
};
252
#endif
253
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
254
cc->gdb_write_register = s390_cpu_gdb_write_register;
255
#ifndef CONFIG_USER_ONLY
256
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
257
- cc->write_elf64_note = s390_cpu_write_elf64_note;
258
cc->sysemu_ops = &s390_sysemu_ops;
259
#endif
260
cc->disas_set_info = s390_cpu_disas_set_info;
92
--
261
--
93
2.25.1
262
2.25.1
94
263
95
264
diff view generated by jsdifflib
New patch
[PULL 26/31] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <20210517105140.1062037-20-f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
include/hw/core/cpu.h | 3 ---
9
include/hw/core/sysemu-cpu-ops.h | 5 +++++
10
hw/core/cpu-sysemu.c | 4 ++--
11
target/arm/cpu.c | 2 +-
12
target/i386/cpu.c | 2 +-
13
5 files changed, 9 insertions(+), 7 deletions(-)
14
15
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/core/cpu.h
18
+++ b/include/hw/core/cpu.h
19
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
20
* associated memory transaction attributes to use for the access.
21
* CPUs which use memory transaction attributes should implement this
22
* instead of get_phys_page_debug.
23
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
24
- * a memory access with the specified memory transaction attributes.
25
* @gdb_read_register: Callback for letting GDB read a register.
26
* @gdb_write_register: Callback for letting GDB write a register.
27
* @gdb_num_core_regs: Number of core registers accessible to GDB.
28
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
29
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
30
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
31
MemTxAttrs *attrs);
32
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
33
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
34
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
35
36
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/core/sysemu-cpu-ops.h
39
+++ b/include/hw/core/sysemu-cpu-ops.h
40
@@ -XXX,XX +XXX,XX @@
41
* struct SysemuCPUOps: System operations specific to a CPU class
42
*/
43
typedef struct SysemuCPUOps {
44
+ /**
45
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
46
+ * a memory access with the specified memory transaction attributes.
47
+ */
48
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
49
/**
50
* @get_crash_info: Callback for reporting guest crash information in
51
* GUEST_PANICKED events.
52
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/core/cpu-sysemu.c
55
+++ b/hw/core/cpu-sysemu.c
56
@@ -XXX,XX +XXX,XX @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
57
CPUClass *cc = CPU_GET_CLASS(cpu);
58
int ret = 0;
59
60
- if (cc->asidx_from_attrs) {
61
- ret = cc->asidx_from_attrs(cpu, attrs);
62
+ if (cc->sysemu_ops->asidx_from_attrs) {
63
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
64
assert(ret < cpu->num_ases && ret >= 0);
65
}
66
return ret;
67
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/cpu.c
70
+++ b/target/arm/cpu.c
71
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
72
#include "hw/core/sysemu-cpu-ops.h"
73
74
static const struct SysemuCPUOps arm_sysemu_ops = {
75
+ .asidx_from_attrs = arm_asidx_from_attrs,
76
.write_elf32_note = arm_cpu_write_elf32_note,
77
.write_elf64_note = arm_cpu_write_elf64_note,
78
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
79
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
80
cc->gdb_write_register = arm_cpu_gdb_write_register;
81
#ifndef CONFIG_USER_ONLY
82
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
83
- cc->asidx_from_attrs = arm_asidx_from_attrs;
84
cc->sysemu_ops = &arm_sysemu_ops;
85
#endif
86
cc->gdb_num_core_regs = 26;
87
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/i386/cpu.c
90
+++ b/target/i386/cpu.c
91
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
92
#include "hw/core/sysemu-cpu-ops.h"
93
94
static const struct SysemuCPUOps i386_sysemu_ops = {
95
+ .asidx_from_attrs = x86_asidx_from_attrs,
96
.get_crash_info = x86_cpu_get_crash_info,
97
.write_elf32_note = x86_cpu_write_elf32_note,
98
.write_elf64_note = x86_cpu_write_elf64_note,
99
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
100
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
101
102
#ifndef CONFIG_USER_ONLY
103
- cc->asidx_from_attrs = x86_asidx_from_attrs;
104
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
105
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
106
cc->sysemu_ops = &i386_sysemu_ops;
107
--
108
2.25.1
109
110
diff view generated by jsdifflib
[PULL 4/5] decodetree: Add support for 64-bit instructions
[PULL 27/31] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
1
From: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Allow '64' to be specified for the instruction width command line params
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
and use the appropriate extract and deposit functions in that case.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
5
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org>
6
This will be used to implement the new 64-bit Power ISA 3.1 instructions.
6
[rth: Drop declaration movement from target/*/cpu.h]
7
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
10
Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com>
11
[rth: Drop the change to the field type; use bitop_width instead of separate
12
variables for extract/deposit; use "ull" for 64-bit constants.]
13
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
8
---
16
scripts/decodetree.py | 21 ++++++++++++++-------
9
include/hw/core/cpu.h | 8 --------
17
1 file changed, 14 insertions(+), 7 deletions(-)
10
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
11
hw/core/cpu-sysemu.c | 6 +++---
12
target/alpha/cpu.c | 2 +-
13
target/arm/cpu.c | 2 +-
14
target/avr/cpu.c | 2 +-
15
target/cris/cpu.c | 2 +-
16
target/hppa/cpu.c | 2 +-
17
target/i386/cpu.c | 2 +-
18
target/m68k/cpu.c | 2 +-
19
target/microblaze/cpu.c | 2 +-
20
target/mips/cpu.c | 2 +-
21
target/nios2/cpu.c | 2 +-
22
target/openrisc/cpu.c | 2 +-
23
target/ppc/cpu_init.c | 2 +-
24
target/riscv/cpu.c | 2 +-
25
target/rx/cpu.c | 2 +-
26
target/s390x/cpu.c | 2 +-
27
target/sh4/cpu.c | 2 +-
28
target/sparc/cpu.c | 2 +-
29
target/tricore/cpu.c | 2 +-
30
target/xtensa/cpu.c | 2 +-
31
22 files changed, 35 insertions(+), 30 deletions(-)
18
32
19
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
33
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
20
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
21
--- a/scripts/decodetree.py
35
--- a/include/hw/core/cpu.h
22
+++ b/scripts/decodetree.py
36
+++ b/include/hw/core/cpu.h
37
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
38
* If the target behaviour here is anything other than "set
39
* the PC register to the value passed in" then the target must
40
* also implement the synchronize_from_tb hook.
41
- * @get_phys_page_debug: Callback for obtaining a physical address.
42
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
43
- * associated memory transaction attributes to use for the access.
44
- * CPUs which use memory transaction attributes should implement this
45
- * instead of get_phys_page_debug.
46
* @gdb_read_register: Callback for letting GDB read a register.
47
* @gdb_write_register: Callback for letting GDB write a register.
48
* @gdb_num_core_regs: Number of core registers accessible to GDB.
49
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
50
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
51
Error **errp);
52
void (*set_pc)(CPUState *cpu, vaddr value);
53
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
54
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
55
- MemTxAttrs *attrs);
56
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
57
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
58
59
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
60
index XXXXXXX..XXXXXXX 100644
61
--- a/include/hw/core/sysemu-cpu-ops.h
62
+++ b/include/hw/core/sysemu-cpu-ops.h
23
@@ -XXX,XX +XXX,XX @@
63
@@ -XXX,XX +XXX,XX @@
24
import getopt
64
* struct SysemuCPUOps: System operations specific to a CPU class
25
65
*/
26
insnwidth = 32
66
typedef struct SysemuCPUOps {
27
+bitop_width = 32
67
+ /**
28
insnmask = 0xffffffff
68
+ * @get_phys_page_debug: Callback for obtaining a physical address.
29
variablewidth = False
69
+ */
30
fields = {}
70
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
31
@@ -XXX,XX +XXX,XX @@ def whexC(val):
71
+ /**
32
"""Return a hex string for val padded for insnwidth,
72
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
33
and with the proper suffix for a C constant."""
73
+ * and the associated memory transaction attributes to use for the
34
suffix = ''
74
+ * access.
35
- if val >= 0x80000000:
75
+ * CPUs which use memory transaction attributes should implement this
36
+ if val >= 0x100000000:
76
+ * instead of get_phys_page_debug.
37
+ suffix = 'ull'
77
+ */
38
+ elif val >= 0x80000000:
78
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
39
suffix = 'u'
79
+ MemTxAttrs *attrs);
40
return whex(val) + suffix
80
/**
41
81
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
42
@@ -XXX,XX +XXX,XX @@ def __str__(self):
82
* a memory access with the specified memory transaction attributes.
43
return str(self.pos) + ':' + s + str(self.len)
83
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
44
84
index XXXXXXX..XXXXXXX 100644
45
def str_extract(self):
85
--- a/hw/core/cpu-sysemu.c
46
- if self.sign:
86
+++ b/hw/core/cpu-sysemu.c
47
- extr = 'sextract32'
87
@@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
48
- else:
88
{
49
- extr = 'extract32'
89
CPUClass *cc = CPU_GET_CLASS(cpu);
50
- return f'{extr}(insn, {self.pos}, {self.len})'
90
51
+ global bitop_width
91
- if (cc->get_phys_page_attrs_debug) {
52
+ s = 's' if self.sign else ''
92
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
53
+ return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
93
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
54
94
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
55
def __eq__(self, other):
95
}
56
return self.sign == other.sign and self.mask == other.mask
96
/* Fallback for CPUs which don't implement the _attrs_ hook */
57
@@ -XXX,XX +XXX,XX @@ def __str__(self):
97
*attrs = MEMTXATTRS_UNSPECIFIED;
58
return str(self.subs)
98
- return cc->get_phys_page_debug(cpu, addr);
59
99
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
60
def str_extract(self):
100
}
61
+ global bitop_width
101
62
ret = '0'
102
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
63
pos = 0
103
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
64
for f in reversed(self.subs):
104
index XXXXXXX..XXXXXXX 100644
65
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
105
--- a/target/alpha/cpu.c
66
if pos == 0:
106
+++ b/target/alpha/cpu.c
67
ret = ext
107
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
68
else:
108
#include "hw/core/sysemu-cpu-ops.h"
69
- ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
109
70
+ ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
110
static const struct SysemuCPUOps alpha_sysemu_ops = {
71
pos += f.len
111
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
72
return ret
112
};
73
113
#endif
74
@@ -XXX,XX +XXX,XX @@ def main():
114
75
global insntype
115
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
76
global insnmask
116
cc->gdb_read_register = alpha_cpu_gdb_read_register;
77
global decode_function
117
cc->gdb_write_register = alpha_cpu_gdb_write_register;
78
+ global bitop_width
118
#ifndef CONFIG_USER_ONLY
79
global variablewidth
119
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
80
global anyextern
120
dc->vmsd = &vmstate_alpha_cpu;
81
121
cc->sysemu_ops = &alpha_sysemu_ops;
82
@@ -XXX,XX +XXX,XX @@ def main():
122
#endif
83
if insnwidth == 16:
123
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
84
insntype = 'uint16_t'
124
index XXXXXXX..XXXXXXX 100644
85
insnmask = 0xffff
125
--- a/target/arm/cpu.c
86
+ elif insnwidth == 64:
126
+++ b/target/arm/cpu.c
87
+ insntype = 'uint64_t'
127
@@ -XXX,XX +XXX,XX @@ static gchar *arm_gdb_arch_name(CPUState *cs)
88
+ insnmask = 0xffffffffffffffff
128
#include "hw/core/sysemu-cpu-ops.h"
89
+ bitop_width = 64
129
90
elif insnwidth != 32:
130
static const struct SysemuCPUOps arm_sysemu_ops = {
91
error(0, 'cannot handle insns of width', insnwidth)
131
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
92
else:
132
.asidx_from_attrs = arm_asidx_from_attrs,
133
.write_elf32_note = arm_cpu_write_elf32_note,
134
.write_elf64_note = arm_cpu_write_elf64_note,
135
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
136
cc->gdb_read_register = arm_cpu_gdb_read_register;
137
cc->gdb_write_register = arm_cpu_gdb_write_register;
138
#ifndef CONFIG_USER_ONLY
139
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
140
cc->sysemu_ops = &arm_sysemu_ops;
141
#endif
142
cc->gdb_num_core_regs = 26;
143
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/target/avr/cpu.c
146
+++ b/target/avr/cpu.c
147
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
148
#include "hw/core/sysemu-cpu-ops.h"
149
150
static const struct SysemuCPUOps avr_sysemu_ops = {
151
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
152
};
153
154
#include "hw/core/tcg-cpu-ops.h"
155
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
156
cc->dump_state = avr_cpu_dump_state;
157
cc->set_pc = avr_cpu_set_pc;
158
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
159
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
160
dc->vmsd = &vms_avr_cpu;
161
cc->sysemu_ops = &avr_sysemu_ops;
162
cc->disas_set_info = avr_cpu_disas_set_info;
163
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/cris/cpu.c
166
+++ b/target/cris/cpu.c
167
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_initfn(Object *obj)
168
#include "hw/core/sysemu-cpu-ops.h"
169
170
static const struct SysemuCPUOps cris_sysemu_ops = {
171
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
172
};
173
#endif
174
175
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
176
cc->gdb_read_register = cris_cpu_gdb_read_register;
177
cc->gdb_write_register = cris_cpu_gdb_write_register;
178
#ifndef CONFIG_USER_ONLY
179
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
180
dc->vmsd = &vmstate_cris_cpu;
181
cc->sysemu_ops = &cris_sysemu_ops;
182
#endif
183
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
184
index XXXXXXX..XXXXXXX 100644
185
--- a/target/hppa/cpu.c
186
+++ b/target/hppa/cpu.c
187
@@ -XXX,XX +XXX,XX @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
188
#include "hw/core/sysemu-cpu-ops.h"
189
190
static const struct SysemuCPUOps hppa_sysemu_ops = {
191
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
192
};
193
#endif
194
195
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
196
cc->gdb_read_register = hppa_cpu_gdb_read_register;
197
cc->gdb_write_register = hppa_cpu_gdb_write_register;
198
#ifndef CONFIG_USER_ONLY
199
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
200
dc->vmsd = &vmstate_hppa_cpu;
201
cc->sysemu_ops = &hppa_sysemu_ops;
202
#endif
203
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/target/i386/cpu.c
206
+++ b/target/i386/cpu.c
207
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
208
#include "hw/core/sysemu-cpu-ops.h"
209
210
static const struct SysemuCPUOps i386_sysemu_ops = {
211
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
212
.asidx_from_attrs = x86_asidx_from_attrs,
213
.get_crash_info = x86_cpu_get_crash_info,
214
.write_elf32_note = x86_cpu_write_elf32_note,
215
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
216
217
#ifndef CONFIG_USER_ONLY
218
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
219
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
220
cc->sysemu_ops = &i386_sysemu_ops;
221
#endif /* !CONFIG_USER_ONLY */
222
223
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
224
index XXXXXXX..XXXXXXX 100644
225
--- a/target/m68k/cpu.c
226
+++ b/target/m68k/cpu.c
227
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m68k_cpu = {
228
#include "hw/core/sysemu-cpu-ops.h"
229
230
static const struct SysemuCPUOps m68k_sysemu_ops = {
231
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
232
};
233
#endif
234
235
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
236
cc->gdb_read_register = m68k_cpu_gdb_read_register;
237
cc->gdb_write_register = m68k_cpu_gdb_write_register;
238
#if defined(CONFIG_SOFTMMU)
239
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
240
dc->vmsd = &vmstate_m68k_cpu;
241
cc->sysemu_ops = &m68k_sysemu_ops;
242
#endif
243
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
244
index XXXXXXX..XXXXXXX 100644
245
--- a/target/microblaze/cpu.c
246
+++ b/target/microblaze/cpu.c
247
@@ -XXX,XX +XXX,XX @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
248
#include "hw/core/sysemu-cpu-ops.h"
249
250
static const struct SysemuCPUOps mb_sysemu_ops = {
251
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
252
};
253
#endif
254
255
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
256
cc->gdb_write_register = mb_cpu_gdb_write_register;
257
258
#ifndef CONFIG_USER_ONLY
259
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
260
dc->vmsd = &vmstate_mb_cpu;
261
cc->sysemu_ops = &mb_sysemu_ops;
262
#endif
263
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
264
index XXXXXXX..XXXXXXX 100644
265
--- a/target/mips/cpu.c
266
+++ b/target/mips/cpu.c
267
@@ -XXX,XX +XXX,XX @@ static Property mips_cpu_properties[] = {
268
#include "hw/core/sysemu-cpu-ops.h"
269
270
static const struct SysemuCPUOps mips_sysemu_ops = {
271
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
272
.legacy_vmsd = &vmstate_mips_cpu,
273
};
274
#endif
275
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
276
cc->gdb_read_register = mips_cpu_gdb_read_register;
277
cc->gdb_write_register = mips_cpu_gdb_write_register;
278
#ifndef CONFIG_USER_ONLY
279
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
280
cc->sysemu_ops = &mips_sysemu_ops;
281
#endif
282
cc->disas_set_info = mips_cpu_disas_set_info;
283
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
284
index XXXXXXX..XXXXXXX 100644
285
--- a/target/nios2/cpu.c
286
+++ b/target/nios2/cpu.c
287
@@ -XXX,XX +XXX,XX @@ static Property nios2_properties[] = {
288
#include "hw/core/sysemu-cpu-ops.h"
289
290
static const struct SysemuCPUOps nios2_sysemu_ops = {
291
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
292
};
293
#endif
294
295
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
296
cc->set_pc = nios2_cpu_set_pc;
297
cc->disas_set_info = nios2_cpu_disas_set_info;
298
#ifndef CONFIG_USER_ONLY
299
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
300
cc->sysemu_ops = &nios2_sysemu_ops;
301
#endif
302
cc->gdb_read_register = nios2_cpu_gdb_read_register;
303
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
304
index XXXXXXX..XXXXXXX 100644
305
--- a/target/openrisc/cpu.c
306
+++ b/target/openrisc/cpu.c
307
@@ -XXX,XX +XXX,XX @@ static void openrisc_any_initfn(Object *obj)
308
#include "hw/core/sysemu-cpu-ops.h"
309
310
static const struct SysemuCPUOps openrisc_sysemu_ops = {
311
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
312
};
313
#endif
314
315
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
316
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
317
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
318
#ifndef CONFIG_USER_ONLY
319
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
320
dc->vmsd = &vmstate_openrisc_cpu;
321
cc->sysemu_ops = &openrisc_sysemu_ops;
322
#endif
323
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
324
index XXXXXXX..XXXXXXX 100644
325
--- a/target/ppc/cpu_init.c
326
+++ b/target/ppc/cpu_init.c
327
@@ -XXX,XX +XXX,XX @@ static Property ppc_cpu_properties[] = {
328
#include "hw/core/sysemu-cpu-ops.h"
329
330
static const struct SysemuCPUOps ppc_sysemu_ops = {
331
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
332
.write_elf32_note = ppc32_cpu_write_elf32_note,
333
.write_elf64_note = ppc64_cpu_write_elf64_note,
334
.virtio_is_big_endian = ppc_cpu_is_big_endian,
335
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
336
cc->gdb_read_register = ppc_cpu_gdb_read_register;
337
cc->gdb_write_register = ppc_cpu_gdb_write_register;
338
#ifndef CONFIG_USER_ONLY
339
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
340
cc->sysemu_ops = &ppc_sysemu_ops;
341
#endif
342
343
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
344
index XXXXXXX..XXXXXXX 100644
345
--- a/target/riscv/cpu.c
346
+++ b/target/riscv/cpu.c
347
@@ -XXX,XX +XXX,XX @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
348
#include "hw/core/sysemu-cpu-ops.h"
349
350
static const struct SysemuCPUOps riscv_sysemu_ops = {
351
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
352
.write_elf64_note = riscv_cpu_write_elf64_note,
353
.write_elf32_note = riscv_cpu_write_elf32_note,
354
.legacy_vmsd = &vmstate_riscv_cpu,
355
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
356
cc->gdb_stop_before_watchpoint = true;
357
cc->disas_set_info = riscv_cpu_disas_set_info;
358
#ifndef CONFIG_USER_ONLY
359
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
360
cc->sysemu_ops = &riscv_sysemu_ops;
361
#endif
362
cc->gdb_arch_name = riscv_gdb_arch_name;
363
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
364
index XXXXXXX..XXXXXXX 100644
365
--- a/target/rx/cpu.c
366
+++ b/target/rx/cpu.c
367
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_init(Object *obj)
368
#include "hw/core/sysemu-cpu-ops.h"
369
370
static const struct SysemuCPUOps rx_sysemu_ops = {
371
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
372
};
373
#endif
374
375
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
376
#endif
377
cc->gdb_read_register = rx_cpu_gdb_read_register;
378
cc->gdb_write_register = rx_cpu_gdb_write_register;
379
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
380
cc->disas_set_info = rx_cpu_disas_set_info;
381
382
cc->gdb_num_core_regs = 26;
383
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
384
index XXXXXXX..XXXXXXX 100644
385
--- a/target/s390x/cpu.c
386
+++ b/target/s390x/cpu.c
387
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_full(DeviceState *dev)
388
#include "hw/core/sysemu-cpu-ops.h"
389
390
static const struct SysemuCPUOps s390_sysemu_ops = {
391
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
392
.get_crash_info = s390_cpu_get_crash_info,
393
.write_elf64_note = s390_cpu_write_elf64_note,
394
.legacy_vmsd = &vmstate_s390_cpu,
395
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
396
cc->gdb_read_register = s390_cpu_gdb_read_register;
397
cc->gdb_write_register = s390_cpu_gdb_write_register;
398
#ifndef CONFIG_USER_ONLY
399
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
400
cc->sysemu_ops = &s390_sysemu_ops;
401
#endif
402
cc->disas_set_info = s390_cpu_disas_set_info;
403
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
404
index XXXXXXX..XXXXXXX 100644
405
--- a/target/sh4/cpu.c
406
+++ b/target/sh4/cpu.c
407
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sh_cpu = {
408
#include "hw/core/sysemu-cpu-ops.h"
409
410
static const struct SysemuCPUOps sh4_sysemu_ops = {
411
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
412
};
413
#endif
414
415
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
416
cc->gdb_read_register = superh_cpu_gdb_read_register;
417
cc->gdb_write_register = superh_cpu_gdb_write_register;
418
#ifndef CONFIG_USER_ONLY
419
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
420
cc->sysemu_ops = &sh4_sysemu_ops;
421
dc->vmsd = &vmstate_sh_cpu;
422
#endif
423
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
424
index XXXXXXX..XXXXXXX 100644
425
--- a/target/sparc/cpu.c
426
+++ b/target/sparc/cpu.c
427
@@ -XXX,XX +XXX,XX @@ static Property sparc_cpu_properties[] = {
428
#include "hw/core/sysemu-cpu-ops.h"
429
430
static const struct SysemuCPUOps sparc_sysemu_ops = {
431
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
432
.legacy_vmsd = &vmstate_sparc_cpu,
433
};
434
#endif
435
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
436
cc->gdb_read_register = sparc_cpu_gdb_read_register;
437
cc->gdb_write_register = sparc_cpu_gdb_write_register;
438
#ifndef CONFIG_USER_ONLY
439
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
440
cc->sysemu_ops = &sparc_sysemu_ops;
441
#endif
442
cc->disas_set_info = cpu_sparc_disas_set_info;
443
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
444
index XXXXXXX..XXXXXXX 100644
445
--- a/target/tricore/cpu.c
446
+++ b/target/tricore/cpu.c
447
@@ -XXX,XX +XXX,XX @@ static void tc27x_initfn(Object *obj)
448
#include "hw/core/sysemu-cpu-ops.h"
449
450
static const struct SysemuCPUOps tricore_sysemu_ops = {
451
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
452
};
453
454
#include "hw/core/tcg-cpu-ops.h"
455
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
456
457
cc->dump_state = tricore_cpu_dump_state;
458
cc->set_pc = tricore_cpu_set_pc;
459
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
460
cc->sysemu_ops = &tricore_sysemu_ops;
461
cc->tcg_ops = &tricore_tcg_ops;
462
}
463
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
464
index XXXXXXX..XXXXXXX 100644
465
--- a/target/xtensa/cpu.c
466
+++ b/target/xtensa/cpu.c
467
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_xtensa_cpu = {
468
#include "hw/core/sysemu-cpu-ops.h"
469
470
static const struct SysemuCPUOps xtensa_sysemu_ops = {
471
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
472
};
473
#endif
474
475
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
476
cc->gdb_stop_before_watchpoint = true;
477
#ifndef CONFIG_USER_ONLY
478
cc->sysemu_ops = &xtensa_sysemu_ops;
479
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
480
dc->vmsd = &vmstate_xtensa_cpu;
481
#endif
482
cc->disas_set_info = xtensa_cpu_disas_set_info;
93
--
483
--
94
2.25.1
484
2.25.1
95
485
96
486
diff view generated by jsdifflib
[PULL 3/5] decodetree: More use of f-strings
[PULL 28/31] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <20210517105140.1062037-22-f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
scripts/decodetree.py | 50 ++++++++++++++++++++-----------------------
8
include/hw/core/cpu.h | 3 ---
5
1 file changed, 23 insertions(+), 27 deletions(-)
9
include/hw/core/sysemu-cpu-ops.h | 5 +++++
10
hw/core/cpu-sysemu.c | 4 ++--
11
target/i386/cpu.c | 2 +-
12
4 files changed, 8 insertions(+), 6 deletions(-)
6
13
7
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
14
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
8
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
9
--- a/scripts/decodetree.py
16
--- a/include/hw/core/cpu.h
10
+++ b/scripts/decodetree.py
17
+++ b/include/hw/core/cpu.h
11
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
18
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
12
19
* @dump_statistics: Callback for dumping statistics.
13
prefix = ''
20
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
14
if file:
21
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
15
- prefix += '{0}:'.format(file)
22
- * @get_memory_mapping: Callback for obtaining the memory mappings.
16
+ prefix += f'{file}:'
23
* @set_pc: Callback for setting the Program Counter register. This
17
if lineno:
24
* should have the semantics used by the target architecture when
18
- prefix += '{0}:'.format(lineno)
25
* setting the PC from a source such as an ELF file entry point;
19
+ prefix += f'{lineno}:'
26
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
20
if prefix:
27
void (*dump_statistics)(CPUState *cpu, int flags);
21
prefix += ' '
28
int64_t (*get_arch_id)(CPUState *cpu);
22
print(prefix, end='error: ', file=sys.stderr)
29
bool (*get_paging_enabled)(const CPUState *cpu);
23
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
30
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
24
extr = 'sextract32'
31
- Error **errp);
25
else:
32
void (*set_pc)(CPUState *cpu, vaddr value);
26
extr = 'extract32'
33
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
27
- return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
34
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
28
+ return f'{extr}(insn, {self.pos}, {self.len})'
35
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
29
36
index XXXXXXX..XXXXXXX 100644
30
def __eq__(self, other):
37
--- a/include/hw/core/sysemu-cpu-ops.h
31
return self.sign == other.sign and self.mask == other.mask
38
+++ b/include/hw/core/sysemu-cpu-ops.h
32
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
39
@@ -XXX,XX +XXX,XX @@
33
ret = '0'
40
* struct SysemuCPUOps: System operations specific to a CPU class
34
pos = 0
41
*/
35
for f in reversed(self.subs):
42
typedef struct SysemuCPUOps {
36
+ ext = f.str_extract()
43
+ /**
37
if pos == 0:
44
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
38
- ret = f.str_extract()
45
+ */
39
+ ret = ext
46
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
40
else:
47
+ Error **errp);
41
- ret = 'deposit32({0}, {1}, {2}, {3})' \
48
/**
42
- .format(ret, pos, 32 - pos, f.str_extract())
49
* @get_phys_page_debug: Callback for obtaining a physical address.
43
+ ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
50
*/
44
pos += f.len
51
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
45
return ret
52
index XXXXXXX..XXXXXXX 100644
46
53
--- a/hw/core/cpu-sysemu.c
47
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
54
+++ b/hw/core/cpu-sysemu.c
48
subtoks = t.split(':')
55
@@ -XXX,XX +XXX,XX @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
49
sign = False
56
{
50
else:
57
CPUClass *cc = CPU_GET_CLASS(cpu);
51
- error(lineno, 'invalid field token "{0}"'.format(t))
58
52
+ error(lineno, f'invalid field token "{t}"')
59
- if (cc->get_memory_mapping) {
53
po = int(subtoks[0])
60
- cc->get_memory_mapping(cpu, list, errp);
54
le = int(subtoks[1])
61
+ if (cc->sysemu_ops->get_memory_mapping) {
55
if po + le > insnwidth:
62
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
56
- error(lineno, 'field {0} too large'.format(t))
63
return;
57
+ error(lineno, f'field {t} too large')
64
}
58
f = Field(sign, po, le)
65
59
subs.append(f)
66
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
60
width += le
67
index XXXXXXX..XXXXXXX 100644
61
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
68
--- a/target/i386/cpu.c
62
anyextern = True
69
+++ b/target/i386/cpu.c
63
continue
70
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
64
if not re.fullmatch(re_C_ident, t):
71
#include "hw/core/sysemu-cpu-ops.h"
65
- error(lineno, 'invalid argument set token "{0}"'.format(t))
72
66
+ error(lineno, f'invalid argument set token "{t}"')
73
static const struct SysemuCPUOps i386_sysemu_ops = {
67
if t in flds:
74
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
68
- error(lineno, 'duplicate argument "{0}"'.format(t))
75
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
69
+ error(lineno, f'duplicate argument "{t}"')
76
.asidx_from_attrs = x86_asidx_from_attrs,
70
flds.append(t)
77
.get_crash_info = x86_cpu_get_crash_info,
71
78
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
72
if name in arguments:
79
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
73
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
80
74
flen = flen[1:]
81
#ifndef CONFIG_USER_ONLY
75
shift = int(flen, 10)
82
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
76
if shift + width > insnwidth:
83
cc->sysemu_ops = &i386_sysemu_ops;
77
- error(lineno, 'field {0} exceeds insnwidth'.format(fname))
84
#endif /* !CONFIG_USER_ONLY */
78
+ error(lineno, f'field {fname} exceeds insnwidth')
85
79
f = Field(sign, insnwidth - width - shift, shift)
80
flds = add_field(lineno, flds, fname, f)
81
fixedbits <<= shift
82
fixedmask <<= shift
83
undefmask <<= shift
84
else:
85
- error(lineno, 'invalid token "{0}"'.format(t))
86
+ error(lineno, f'invalid token "{t}"')
87
width += shift
88
89
if variablewidth and width < insnwidth and width % 8 == 0:
90
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
91
92
# We should have filled in all of the bits of the instruction.
93
elif not (is_format and width == 0) and width != insnwidth:
94
- error(lineno, 'definition has {0} bits'.format(width))
95
+ error(lineno, f'definition has {width} bits')
96
97
# Do not check for fields overlapping fields; one valid usage
98
# is to be able to duplicate fields via import.
99
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
100
if arg:
101
for f in flds.keys():
102
if f not in arg.fields:
103
- error(lineno, 'field {0} not in argument set {1}'
104
- .format(f, arg.name))
105
+ error(lineno, f'field {f} not in argument set {arg.name}')
106
else:
107
arg = infer_argument_set(flds)
108
if name in formats:
109
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
110
arg = fmt.base
111
for f in flds.keys():
112
if f not in arg.fields:
113
- error(lineno, 'field {0} not in argument set {1}'
114
- .format(f, arg.name))
115
+ error(lineno, f'field {f} not in argument set {arg.name}')
116
if f in fmt.fields.keys():
117
- error(lineno, 'field {0} set by format and pattern'.format(f))
118
+ error(lineno, f'field {f} set by format and pattern')
119
for f in arg.fields:
120
if f not in flds.keys() and f not in fmt.fields.keys():
121
- error(lineno, 'field {0} not initialized'.format(f))
122
+ error(lineno, f'field {f} not initialized')
123
pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
124
undefmask, fieldmask, flds, width)
125
parent_pat.pats.append(pat)
126
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
127
elif re.fullmatch(re_pat_ident, name):
128
parse_generic(start_lineno, parent_pat, name, toks)
129
else:
130
- error(lineno, 'invalid token "{0}"'.format(name))
131
+ error(lineno, f'invalid token "{name}"')
132
toks = []
133
134
if nesting != 0:
135
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
136
137
# If we need to load more bytes to test, do so now.
138
if extracted < self.width:
139
- output(ind, 'insn = ', decode_function,
140
- '_load_bytes(ctx, insn, {0}, {1});\n'
141
- .format(extracted // 8, self.width // 8));
142
+ output(ind, f'insn = {decode_function}_load_bytes',
143
+ f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
144
extracted = self.width
145
146
# Attempt to aid the compiler in producing compact switch statements.
147
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
148
149
# If we need to load more bytes, do so now.
150
if extracted < self.width:
151
- output(ind, 'insn = ', decode_function,
152
- '_load_bytes(ctx, insn, {0}, {1});\n'
153
- .format(extracted // 8, self.width // 8));
154
+ output(ind, f'insn = {decode_function}_load_bytes',
155
+ f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
156
extracted = self.width
157
output(ind, 'return insn;\n')
158
# end SizeLeaf
159
@@ -XXX,XX +XXX,XX @@ def build_size_tree(pats, width, outerbits, outermask):
160
for p in pats:
161
pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
162
error_with_file(pats[0].file, pats[0].lineno,
163
- 'overlapping patterns size {0}:'.format(width), pnames)
164
+ f'overlapping patterns size {width}:', pnames)
165
166
bins = {}
167
for i in pats:
168
--
86
--
169
2.25.1
87
2.25.1
170
88
171
89
diff view generated by jsdifflib
[PULL 2/5] decodetree: Introduce whex and whexC helpers
[PULL 29/31] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
1
Form a hex constant of the appropriate insnwidth.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Begin using f-strings on changed lines.
3
2
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <20210517105140.1062037-23-f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
---
7
scripts/decodetree.py | 66 +++++++++++++++++++++++++------------------
8
include/hw/core/cpu.h | 2 --
8
1 file changed, 38 insertions(+), 28 deletions(-)
9
include/hw/core/sysemu-cpu-ops.h | 4 ++++
10
hw/core/cpu-sysemu.c | 4 ++--
11
target/i386/cpu.c | 4 +++-
12
4 files changed, 9 insertions(+), 5 deletions(-)
9
13
10
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
14
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/scripts/decodetree.py
16
--- a/include/hw/core/cpu.h
13
+++ b/scripts/decodetree.py
17
+++ b/include/hw/core/cpu.h
14
@@ -XXX,XX +XXX,XX @@ def str_fields(fields):
18
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
15
return r[1:]
19
* @dump_state: Callback for dumping state.
16
20
* @dump_statistics: Callback for dumping statistics.
17
21
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
18
+def whex(val):
22
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
19
+ """Return a hex string for val padded for insnwidth"""
23
* @set_pc: Callback for setting the Program Counter register. This
20
+ global insnwidth
24
* should have the semantics used by the target architecture when
21
+ return f'0x{val:0{insnwidth // 4}x}'
25
* setting the PC from a source such as an ELF file entry point;
22
+
26
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
23
+
27
void (*dump_state)(CPUState *cpu, FILE *, int flags);
24
+def whexC(val):
28
void (*dump_statistics)(CPUState *cpu, int flags);
25
+ """Return a hex string for val padded for insnwidth,
29
int64_t (*get_arch_id)(CPUState *cpu);
26
+ and with the proper suffix for a C constant."""
30
- bool (*get_paging_enabled)(const CPUState *cpu);
27
+ suffix = ''
31
void (*set_pc)(CPUState *cpu, vaddr value);
28
+ if val >= 0x80000000:
32
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
29
+ suffix = 'u'
33
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
30
+ return whex(val) + suffix
34
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
31
+
35
index XXXXXXX..XXXXXXX 100644
32
+
36
--- a/include/hw/core/sysemu-cpu-ops.h
33
def str_match_bits(bits, mask):
37
+++ b/include/hw/core/sysemu-cpu-ops.h
34
"""Return a string pretty-printing BITS/MASK"""
38
@@ -XXX,XX +XXX,XX @@ typedef struct SysemuCPUOps {
35
global insnwidth
39
*/
36
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
40
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
37
if outermask != p.fixedmask:
41
Error **errp);
38
innermask = p.fixedmask & ~outermask
42
+ /**
39
innerbits = p.fixedbits & ~outermask
43
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
40
- output(ind, 'if ((insn & ',
44
+ */
41
- '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits),
45
+ bool (*get_paging_enabled)(const CPUState *cpu);
42
- ') {\n')
46
/**
43
- output(ind, ' /* ',
47
* @get_phys_page_debug: Callback for obtaining a physical address.
44
- str_match_bits(p.fixedbits, p.fixedmask), ' */\n')
48
*/
45
+ output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
49
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
46
+ output(ind, f' /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
50
index XXXXXXX..XXXXXXX 100644
47
p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
51
--- a/hw/core/cpu-sysemu.c
48
output(ind, '}\n')
52
+++ b/hw/core/cpu-sysemu.c
49
else:
53
@@ -XXX,XX +XXX,XX @@ bool cpu_paging_enabled(const CPUState *cpu)
50
@@ -XXX,XX +XXX,XX @@ def __init__(self, fm, tm):
54
{
51
55
CPUClass *cc = CPU_GET_CLASS(cpu);
52
def str1(self, i):
56
53
ind = str_indent(i)
57
- if (cc->get_paging_enabled) {
54
- r = '{0}{1:08x}'.format(ind, self.fixedmask)
58
- return cc->get_paging_enabled(cpu);
55
+ r = ind + whex(self.fixedmask)
59
+ if (cc->sysemu_ops->get_paging_enabled) {
56
if self.format:
60
+ return cc->sysemu_ops->get_paging_enabled(cpu);
57
r += ' ' + self.format.name
61
}
58
r += ' [\n'
62
59
for (b, s) in self.subs:
63
return false;
60
- r += '{0} {1:08x}:\n'.format(ind, b)
64
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
61
+ r += ind + f' {whex(b)}:\n'
65
index XXXXXXX..XXXXXXX 100644
62
r += s.str1(i + 4) + '\n'
66
--- a/target/i386/cpu.c
63
r += ind + ']'
67
+++ b/target/i386/cpu.c
64
return r
68
@@ -XXX,XX +XXX,XX @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
65
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
69
return cpu->apic_id;
66
if sh > 0:
70
}
67
# Propagate SH down into the local functions.
71
68
def str_switch(b, sh=sh):
72
+#if !defined(CONFIG_USER_ONLY)
69
- return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
73
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
70
+ return f'(insn >> {sh}) & {b >> sh:#x}'
74
{
71
75
X86CPU *cpu = X86_CPU(cs);
72
def str_case(b, sh=sh):
76
73
- return '0x{0:x}'.format(b >> sh)
77
return cpu->env.cr[0] & CR0_PG_MASK;
74
+ return hex(b >> sh)
78
}
75
else:
79
+#endif /* !CONFIG_USER_ONLY */
76
def str_switch(b):
80
77
- return 'insn & 0x{0:08x}'.format(b)
81
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
78
+ return f'insn & {whexC(b)}'
82
{
79
83
@@ -XXX,XX +XXX,XX @@ static Property x86_cpu_properties[] = {
80
def str_case(b):
84
81
- return '0x{0:08x}'.format(b)
85
static const struct SysemuCPUOps i386_sysemu_ops = {
82
+ return whexC(b)
86
.get_memory_mapping = x86_cpu_get_memory_mapping,
83
87
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
84
output(ind, 'switch (', str_switch(self.thismask), ') {\n')
88
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
85
for b, s in sorted(self.subs):
89
.asidx_from_attrs = x86_asidx_from_attrs,
86
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
90
.get_crash_info = x86_cpu_get_crash_info,
87
91
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
88
# Validate the masks that we have assembled.
92
cc->gdb_read_register = x86_cpu_gdb_read_register;
89
if fieldmask & fixedmask:
93
cc->gdb_write_register = x86_cpu_gdb_write_register;
90
- error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})'
94
cc->get_arch_id = x86_cpu_get_arch_id;
91
- .format(fieldmask, fixedmask))
95
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
92
+ error(lineno, 'fieldmask overlaps fixedmask ',
96
93
+ f'({whex(fieldmask)} & {whex(fixedmask)})')
97
#ifndef CONFIG_USER_ONLY
94
if fieldmask & undefmask:
98
cc->sysemu_ops = &i386_sysemu_ops;
95
- error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
96
- .format(fieldmask, undefmask))
97
+ error(lineno, 'fieldmask overlaps undefmask ',
98
+ f'({whex(fieldmask)} & {whex(undefmask)})')
99
if fixedmask & undefmask:
100
- error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
101
- .format(fixedmask, undefmask))
102
+ error(lineno, 'fixedmask overlaps undefmask ',
103
+ f'({whex(fixedmask)} & {whex(undefmask)})')
104
if not is_format:
105
allbits = fieldmask | fixedmask | undefmask
106
if allbits != insnmask:
107
- error(lineno, 'bits left unspecified (0x{0:08x})'
108
- .format(allbits ^ insnmask))
109
+ error(lineno, 'bits left unspecified ',
110
+ f'({whex(allbits ^ insnmask)})')
111
# end parse_general
112
113
114
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
115
116
def str1(self, i):
117
ind = str_indent(i)
118
- r = '{0}{1:08x}'.format(ind, self.mask)
119
- r += ' [\n'
120
+ r = ind + whex(self.mask) + ' [\n'
121
for (b, s) in self.subs:
122
- r += '{0} {1:08x}:\n'.format(ind, b)
123
+ r += ind + f' {whex(b)}:\n'
124
r += s.str1(i + 4) + '\n'
125
r += ind + ']'
126
return r
127
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
128
if sh > 0:
129
# Propagate SH down into the local functions.
130
def str_switch(b, sh=sh):
131
- return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
132
+ return f'(insn >> {sh}) & {b >> sh:#x}'
133
134
def str_case(b, sh=sh):
135
- return '0x{0:x}'.format(b >> sh)
136
+ return hex(b >> sh)
137
else:
138
def str_switch(b):
139
- return 'insn & 0x{0:08x}'.format(b)
140
+ return f'insn & {whexC(b)}'
141
142
def str_case(b):
143
- return '0x{0:08x}'.format(b)
144
+ return whexC(b)
145
146
output(ind, 'switch (', str_switch(self.mask), ') {\n')
147
for b, s in sorted(self.subs):
148
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
149
self.width = w
150
151
def str1(self, i):
152
- ind = str_indent(i)
153
- return '{0}{1:08x}'.format(ind, self.mask)
154
+ return str_indent(i) + whex(self.mask)
155
156
def __str__(self):
157
return self.str1(0)
158
--
99
--
159
2.25.1
100
2.25.1
160
101
161
102
diff view generated by jsdifflib
New patch
[PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
1
Add a flag to MIPSCPUClass in order to avoid needing to
2
replace mips_tcg_ops.do_transaction_failed.
1
3
4
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
8
---
9
target/mips/cpu-qom.h | 3 +++
10
hw/mips/jazz.c | 35 +++--------------------------------
11
target/mips/tcg/op_helper.c | 3 ++-
12
3 files changed, 8 insertions(+), 33 deletions(-)
13
14
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/cpu-qom.h
17
+++ b/target/mips/cpu-qom.h
18
@@ -XXX,XX +XXX,XX @@ struct MIPSCPUClass {
19
DeviceRealize parent_realize;
20
DeviceReset parent_reset;
21
const struct mips_def_t *cpu_def;
22
+
23
+ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
24
+ bool no_data_aborts;
25
};
26
27
28
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/mips/jazz.c
31
+++ b/hw/mips/jazz.c
32
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps dma_dummy_ops = {
33
#define MAGNUM_BIOS_SIZE \
34
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
35
36
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
37
-static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
38
- vaddr addr, unsigned size,
39
- MMUAccessType access_type,
40
- int mmu_idx, MemTxAttrs attrs,
41
- MemTxResult response,
42
- uintptr_t retaddr);
43
-
44
-static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
45
- vaddr addr, unsigned size,
46
- MMUAccessType access_type,
47
- int mmu_idx, MemTxAttrs attrs,
48
- MemTxResult response,
49
- uintptr_t retaddr)
50
-{
51
- if (access_type != MMU_INST_FETCH) {
52
- /* ignore invalid access (ie do not raise exception) */
53
- return;
54
- }
55
- (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
56
- mmu_idx, attrs, response, retaddr);
57
-}
58
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
59
-
60
static void mips_jazz_init(MachineState *machine,
61
enum jazz_model_e jazz_model)
62
{
63
@@ -XXX,XX +XXX,XX @@ static void mips_jazz_init(MachineState *machine,
64
int bios_size, n;
65
Clock *cpuclk;
66
MIPSCPU *cpu;
67
- CPUClass *cc;
68
+ MIPSCPUClass *mcc;
69
CPUMIPSState *env;
70
qemu_irq *i8259;
71
rc4030_dma *dmas;
72
@@ -XXX,XX +XXX,XX @@ static void mips_jazz_init(MachineState *machine,
73
* However, we can't simply add a global memory region to catch
74
* everything, as this would make all accesses including instruction
75
* accesses be ignored and not raise exceptions.
76
- * So instead we hijack the do_transaction_failed method on the CPU, and
77
- * do not raise exceptions for data access.
78
*
79
* NOTE: this behaviour of raising exceptions for bad instruction
80
* fetches but not bad data accesses was added in commit 54e755588cf1e9
81
@@ -XXX,XX +XXX,XX @@ static void mips_jazz_init(MachineState *machine,
82
* we could replace this hijacking of CPU methods with a simple global
83
* memory region that catches all memory accesses, as we do on Malta.
84
*/
85
- cc = CPU_GET_CLASS(cpu);
86
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
87
- real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
88
- cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
89
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
90
+ mcc = MIPS_CPU_GET_CLASS(cpu);
91
+ mcc->no_data_aborts = true;
92
93
/* allocate RAM */
94
memory_region_add_subregion(address_space, 0, machine->ram);
95
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/mips/tcg/op_helper.c
98
+++ b/target/mips/tcg/op_helper.c
99
@@ -XXX,XX +XXX,XX @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
100
MemTxResult response, uintptr_t retaddr)
101
{
102
MIPSCPU *cpu = MIPS_CPU(cs);
103
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
104
CPUMIPSState *env = &cpu->env;
105
106
if (access_type == MMU_INST_FETCH) {
107
do_raise_exception(env, EXCP_IBE, retaddr);
108
- } else {
109
+ } else if (!mcc->no_data_aborts) {
110
do_raise_exception(env, EXCP_DBE, retaddr);
111
}
112
}
113
--
114
2.25.1
115
116
diff view generated by jsdifflib
New patch
[PULL 31/31] hw/core: Constify TCGCPUOps
1
We no longer have any runtime modifications to this struct,
2
so declare them all const.
1
3
4
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
8
---
9
include/hw/core/cpu.h | 2 +-
10
target/alpha/cpu.c | 2 +-
11
target/arm/cpu.c | 2 +-
12
target/arm/cpu_tcg.c | 2 +-
13
target/avr/cpu.c | 2 +-
14
target/cris/cpu.c | 4 ++--
15
target/hexagon/cpu.c | 2 +-
16
target/hppa/cpu.c | 2 +-
17
target/i386/tcg/tcg-cpu.c | 2 +-
18
target/m68k/cpu.c | 2 +-
19
target/microblaze/cpu.c | 2 +-
20
target/mips/cpu.c | 2 +-
21
target/nios2/cpu.c | 2 +-
22
target/openrisc/cpu.c | 2 +-
23
target/ppc/cpu_init.c | 2 +-
24
target/riscv/cpu.c | 2 +-
25
target/rx/cpu.c | 2 +-
26
target/s390x/cpu.c | 2 +-
27
target/sh4/cpu.c | 2 +-
28
target/sparc/cpu.c | 2 +-
29
target/tricore/cpu.c | 2 +-
30
target/xtensa/cpu.c | 2 +-
31
22 files changed, 23 insertions(+), 23 deletions(-)
32
33
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/core/cpu.h
36
+++ b/include/hw/core/cpu.h
37
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
38
const struct SysemuCPUOps *sysemu_ops;
39
40
/* when TCG is not available, this pointer is NULL */
41
- struct TCGCPUOps *tcg_ops;
42
+ const struct TCGCPUOps *tcg_ops;
43
44
/*
45
* if not NULL, this is called in order for the CPUClass to initialize
46
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/alpha/cpu.c
49
+++ b/target/alpha/cpu.c
50
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
51
52
#include "hw/core/tcg-cpu-ops.h"
53
54
-static struct TCGCPUOps alpha_tcg_ops = {
55
+static const struct TCGCPUOps alpha_tcg_ops = {
56
.initialize = alpha_translate_init,
57
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
58
.tlb_fill = alpha_cpu_tlb_fill,
59
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu.c
62
+++ b/target/arm/cpu.c
63
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps arm_sysemu_ops = {
64
#endif
65
66
#ifdef CONFIG_TCG
67
-static struct TCGCPUOps arm_tcg_ops = {
68
+static const struct TCGCPUOps arm_tcg_ops = {
69
.initialize = arm_translate_init,
70
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
71
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
72
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/cpu_tcg.c
75
+++ b/target/arm/cpu_tcg.c
76
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
77
}
78
79
#ifdef CONFIG_TCG
80
-static struct TCGCPUOps arm_v7m_tcg_ops = {
81
+static const struct TCGCPUOps arm_v7m_tcg_ops = {
82
.initialize = arm_translate_init,
83
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
84
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
85
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/target/avr/cpu.c
88
+++ b/target/avr/cpu.c
89
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps avr_sysemu_ops = {
90
91
#include "hw/core/tcg-cpu-ops.h"
92
93
-static struct TCGCPUOps avr_tcg_ops = {
94
+static const struct TCGCPUOps avr_tcg_ops = {
95
.initialize = avr_cpu_tcg_init,
96
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
97
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
98
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/cris/cpu.c
101
+++ b/target/cris/cpu.c
102
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps cris_sysemu_ops = {
103
104
#include "hw/core/tcg-cpu-ops.h"
105
106
-static struct TCGCPUOps crisv10_tcg_ops = {
107
+static const struct TCGCPUOps crisv10_tcg_ops = {
108
.initialize = cris_initialize_crisv10_tcg,
109
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
110
.tlb_fill = cris_cpu_tlb_fill,
111
@@ -XXX,XX +XXX,XX @@ static struct TCGCPUOps crisv10_tcg_ops = {
112
#endif /* !CONFIG_USER_ONLY */
113
};
114
115
-static struct TCGCPUOps crisv32_tcg_ops = {
116
+static const struct TCGCPUOps crisv32_tcg_ops = {
117
.initialize = cris_initialize_tcg,
118
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
119
.tlb_fill = cris_cpu_tlb_fill,
120
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/target/hexagon/cpu.c
123
+++ b/target/hexagon/cpu.c
124
@@ -XXX,XX +XXX,XX @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
#include "hw/core/tcg-cpu-ops.h"
127
128
-static struct TCGCPUOps hexagon_tcg_ops = {
129
+static const struct TCGCPUOps hexagon_tcg_ops = {
130
.initialize = hexagon_translate_init,
131
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
132
.tlb_fill = hexagon_tlb_fill,
133
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/hppa/cpu.c
136
+++ b/target/hppa/cpu.c
137
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
138
139
#include "hw/core/tcg-cpu-ops.h"
140
141
-static struct TCGCPUOps hppa_tcg_ops = {
142
+static const struct TCGCPUOps hppa_tcg_ops = {
143
.initialize = hppa_translate_init,
144
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
145
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
146
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/i386/tcg/tcg-cpu.c
149
+++ b/target/i386/tcg/tcg-cpu.c
150
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
151
152
#include "hw/core/tcg-cpu-ops.h"
153
154
-static struct TCGCPUOps x86_tcg_ops = {
155
+static const struct TCGCPUOps x86_tcg_ops = {
156
.initialize = tcg_x86_init,
157
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
158
.cpu_exec_enter = x86_cpu_exec_enter,
159
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/target/m68k/cpu.c
162
+++ b/target/m68k/cpu.c
163
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
164
165
#include "hw/core/tcg-cpu-ops.h"
166
167
-static struct TCGCPUOps m68k_tcg_ops = {
168
+static const struct TCGCPUOps m68k_tcg_ops = {
169
.initialize = m68k_tcg_init,
170
.cpu_exec_interrupt = m68k_cpu_exec_interrupt,
171
.tlb_fill = m68k_cpu_tlb_fill,
172
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/microblaze/cpu.c
175
+++ b/target/microblaze/cpu.c
176
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps mb_sysemu_ops = {
177
178
#include "hw/core/tcg-cpu-ops.h"
179
180
-static struct TCGCPUOps mb_tcg_ops = {
181
+static const struct TCGCPUOps mb_tcg_ops = {
182
.initialize = mb_tcg_init,
183
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
184
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
185
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/target/mips/cpu.c
188
+++ b/target/mips/cpu.c
189
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps mips_sysemu_ops = {
190
* NB: cannot be const, as some elements are changed for specific
191
* mips hardware (see hw/mips/jazz.c).
192
*/
193
-static struct TCGCPUOps mips_tcg_ops = {
194
+static const struct TCGCPUOps mips_tcg_ops = {
195
.initialize = mips_tcg_init,
196
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
197
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
198
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/target/nios2/cpu.c
201
+++ b/target/nios2/cpu.c
202
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
203
204
#include "hw/core/tcg-cpu-ops.h"
205
206
-static struct TCGCPUOps nios2_tcg_ops = {
207
+static const struct TCGCPUOps nios2_tcg_ops = {
208
.initialize = nios2_tcg_init,
209
.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
210
.tlb_fill = nios2_cpu_tlb_fill,
211
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/openrisc/cpu.c
214
+++ b/target/openrisc/cpu.c
215
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
216
217
#include "hw/core/tcg-cpu-ops.h"
218
219
-static struct TCGCPUOps openrisc_tcg_ops = {
220
+static const struct TCGCPUOps openrisc_tcg_ops = {
221
.initialize = openrisc_translate_init,
222
.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
223
.tlb_fill = openrisc_cpu_tlb_fill,
224
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
225
index XXXXXXX..XXXXXXX 100644
226
--- a/target/ppc/cpu_init.c
227
+++ b/target/ppc/cpu_init.c
228
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
229
#ifdef CONFIG_TCG
230
#include "hw/core/tcg-cpu-ops.h"
231
232
-static struct TCGCPUOps ppc_tcg_ops = {
233
+static const struct TCGCPUOps ppc_tcg_ops = {
234
.initialize = ppc_translate_init,
235
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
236
.tlb_fill = ppc_cpu_tlb_fill,
237
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
238
index XXXXXXX..XXXXXXX 100644
239
--- a/target/riscv/cpu.c
240
+++ b/target/riscv/cpu.c
241
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
242
243
#include "hw/core/tcg-cpu-ops.h"
244
245
-static struct TCGCPUOps riscv_tcg_ops = {
246
+static const struct TCGCPUOps riscv_tcg_ops = {
247
.initialize = riscv_translate_init,
248
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
249
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
250
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/target/rx/cpu.c
253
+++ b/target/rx/cpu.c
254
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps rx_sysemu_ops = {
255
256
#include "hw/core/tcg-cpu-ops.h"
257
258
-static struct TCGCPUOps rx_tcg_ops = {
259
+static const struct TCGCPUOps rx_tcg_ops = {
260
.initialize = rx_translate_init,
261
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
262
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
263
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
264
index XXXXXXX..XXXXXXX 100644
265
--- a/target/s390x/cpu.c
266
+++ b/target/s390x/cpu.c
267
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps s390_sysemu_ops = {
268
#ifdef CONFIG_TCG
269
#include "hw/core/tcg-cpu-ops.h"
270
271
-static struct TCGCPUOps s390_tcg_ops = {
272
+static const struct TCGCPUOps s390_tcg_ops = {
273
.initialize = s390x_translate_init,
274
.tlb_fill = s390_cpu_tlb_fill,
275
276
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
277
index XXXXXXX..XXXXXXX 100644
278
--- a/target/sh4/cpu.c
279
+++ b/target/sh4/cpu.c
280
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
281
282
#include "hw/core/tcg-cpu-ops.h"
283
284
-static struct TCGCPUOps superh_tcg_ops = {
285
+static const struct TCGCPUOps superh_tcg_ops = {
286
.initialize = sh4_translate_init,
287
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
288
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
289
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
290
index XXXXXXX..XXXXXXX 100644
291
--- a/target/sparc/cpu.c
292
+++ b/target/sparc/cpu.c
293
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
294
#ifdef CONFIG_TCG
295
#include "hw/core/tcg-cpu-ops.h"
296
297
-static struct TCGCPUOps sparc_tcg_ops = {
298
+static const struct TCGCPUOps sparc_tcg_ops = {
299
.initialize = sparc_tcg_init,
300
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
301
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
302
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
303
index XXXXXXX..XXXXXXX 100644
304
--- a/target/tricore/cpu.c
305
+++ b/target/tricore/cpu.c
306
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
307
308
#include "hw/core/tcg-cpu-ops.h"
309
310
-static struct TCGCPUOps tricore_tcg_ops = {
311
+static const struct TCGCPUOps tricore_tcg_ops = {
312
.initialize = tricore_tcg_init,
313
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
314
.tlb_fill = tricore_cpu_tlb_fill,
315
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
316
index XXXXXXX..XXXXXXX 100644
317
--- a/target/xtensa/cpu.c
318
+++ b/target/xtensa/cpu.c
319
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
320
321
#include "hw/core/tcg-cpu-ops.h"
322
323
-static struct TCGCPUOps xtensa_tcg_ops = {
324
+static const struct TCGCPUOps xtensa_tcg_ops = {
325
.initialize = xtensa_translate_init,
326
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
327
.tlb_fill = xtensa_cpu_tlb_fill,
328
--
329
2.25.1
330
331
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