v8:
Hi folks,

Finally we were able to assign v0.1 draft for Pointer Masking extension for RISC-V: https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc
This is supposed to be the first series of patches with initial support for PM. It obviously misses support for hypervisor mode, vector load/stores and some other features, while using temporary csr numbers(they're to be assigned by the committee a bit later).
With this patch series we were able to run a bunch of tests with HWASAN checks enabled.

I hope I've managed to addressed @Alistair's previous comments in this version.

Thanks!

v7:
Hi folks,

Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
This series contains fixed @Alistair suggestion on enabling J-ext.

As for @Richard comments:
- Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
- These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.

If this patch series would be accepted, I think my further attention would be to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned previously

Thanks!

Alexey Baturo (5):
  [RISCV_PM] Add J-extension into RISC-V
  [RISCV_PM] Support CSRs required for RISC-V PM extension except for
    the h-mode
  [RISCV_PM] Print new PM CSRs in QEMU logs
  [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
    instructions
  [RISCV_PM] Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  [RISCV_PM] Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  32 ++++
 target/riscv/cpu.h                      |  34 ++++
 target/riscv/cpu_bits.h                 |  66 +++++++
 target/riscv/csr.c                      | 236 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/translate.c                |  42 +++++
 9 files changed, 419 insertions(+)

-- 
2.20.1

Patchew URL: https://patchew.org/QEMU/20210427220615.12763-1-space.monkey.delivers@gmail.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210427220615.12763-1-space.monkey.delivers@gmail.com
Subject: [PATCH v8 0/6] RISC-V Pointer Masking implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210427220615.12763-1-space.monkey.delivers@gmail.com -> patchew/20210427220615.12763-1-space.monkey.delivers@gmail.com
Switched to a new branch 'test'
0d3c038 Allow experimental J-ext to be turned on
2e8b023 Implement address masking functions required for RISC-V Pointer Masking extension
9cf6cf0 Support pointer masking for RISC-V for i/c/f/d/a types of instructions
583ea8a Print new PM CSRs in QEMU logs
d674a6d Support CSRs required for RISC-V PM extension except for the h-mode
8f777b4 Add J-extension into RISC-V

=== OUTPUT BEGIN ===
1/6 Checking commit 8f777b425749 (Add J-extension into RISC-V)
2/6 Checking commit d674a6dc8388 (Support CSRs required for RISC-V PM extension except for the h-mode)
ERROR: open brace '{' following function declarations go on the next line
#151: FILE: target/riscv/csr.c:193:
+static int pointer_masking(CPURISCVState *env, int csrno) {

WARNING: line over 80 characters
#386: FILE: target/riscv/csr.c:1724:
+    [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },

WARNING: line over 80 characters
#387: FILE: target/riscv/csr.c:1725:
+    [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },

WARNING: line over 80 characters
#388: FILE: target/riscv/csr.c:1726:
+    [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },

WARNING: line over 80 characters
#390: FILE: target/riscv/csr.c:1728:
+    [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },

WARNING: line over 80 characters
#391: FILE: target/riscv/csr.c:1729:
+    [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },

WARNING: line over 80 characters
#392: FILE: target/riscv/csr.c:1730:
+    [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },

WARNING: line over 80 characters
#394: FILE: target/riscv/csr.c:1732:
+    [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },

WARNING: line over 80 characters
#395: FILE: target/riscv/csr.c:1733:
+    [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },

WARNING: line over 80 characters
#396: FILE: target/riscv/csr.c:1734:
+    [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },

total: 1 errors, 9 warnings, 362 lines checked

Patch 2/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/6 Checking commit 583ea8a026a6 (Print new PM CSRs in QEMU logs)
4/6 Checking commit 9cf6cf0a67f9 (Support pointer masking for RISC-V for i/c/f/d/a types of instructions)
5/6 Checking commit 2e8b02377249 (Implement address masking functions required for RISC-V Pointer Masking extension)
6/6 Checking commit 0d3c0387b1bb (Allow experimental J-ext to be turned on)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210427220615.12763-1-space.monkey.delivers@gmail.com/testing.checkpatch/?type=message.
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