hw/arm/armsse.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
The SSE-300 has a Cortex-M55 (which was the whole reason for us
modelling it), but we forgot to actually update the code to let it
have a different CPU type from the IoTKit and SSE-200. Add CPU type
as a field for ARMSSEInfo instead of hardcoding it to always use a
Cortex-M33.
Buglink: https://bugs.launchpad.net/qemu/+bug/1923861
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
This is a rather embarrassing bug. None of the test code I ran
on the a547 model actually cared about the CPU specifically being
an M55... Another one for the "maybe in rc4" bucket.
hw/arm/armsse.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 170dea8632d..2e5d0679e7b 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -56,6 +56,7 @@ typedef struct ARMSSEDeviceInfo {
struct ARMSSEInfo {
const char *name;
+ const char *cpu_type;
uint32_t sse_version;
int sram_banks;
int num_cpus;
@@ -501,6 +502,7 @@ static const ARMSSEInfo armsse_variants[] = {
{
.name = TYPE_IOTKIT,
.sse_version = ARMSSE_IOTKIT,
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
.sram_banks = 1,
.num_cpus = 1,
.sys_version = 0x41743,
@@ -519,6 +521,7 @@ static const ARMSSEInfo armsse_variants[] = {
{
.name = TYPE_SSE200,
.sse_version = ARMSSE_SSE200,
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
.sram_banks = 4,
.num_cpus = 2,
.sys_version = 0x22041743,
@@ -537,6 +540,7 @@ static const ARMSSEInfo armsse_variants[] = {
{
.name = TYPE_SSE300,
.sse_version = ARMSSE_SSE300,
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"),
.sram_banks = 2,
.num_cpus = 1,
.sys_version = 0x7e00043b,
@@ -719,8 +723,7 @@ static void armsse_init(Object *obj)
name = g_strdup_printf("armv7m%d", i);
object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
TYPE_ARMV7M);
- qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type",
- ARM_CPU_TYPE_NAME("cortex-m33"));
+ qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type);
g_free(name);
name = g_strdup_printf("arm-sse-cpu-container%d", i);
memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX);
--
2.20.1
On 4/16/21 12:40 PM, Peter Maydell wrote: > The SSE-300 has a Cortex-M55 (which was the whole reason for us > modelling it), but we forgot to actually update the code to let it > have a different CPU type from the IoTKit and SSE-200. Add CPU type > as a field for ARMSSEInfo instead of hardcoding it to always use a > Cortex-M33. > > Buglink: https://bugs.launchpad.net/qemu/+bug/1923861 > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > This is a rather embarrassing bug. None of the test code I ran > on the a547 model actually cared about the CPU specifically being > an M55... Another one for the "maybe in rc4" bucket. Yes please. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > hw/arm/armsse.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-)
On 4/16/21 3:40 AM, Peter Maydell wrote: > The SSE-300 has a Cortex-M55 (which was the whole reason for us > modelling it), but we forgot to actually update the code to let it > have a different CPU type from the IoTKit and SSE-200. Add CPU type > as a field for ARMSSEInfo instead of hardcoding it to always use a > Cortex-M33. > > Buglink:https://bugs.launchpad.net/qemu/+bug/1923861 > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > This is a rather embarrassing bug. None of the test code I ran > on the a547 model actually cared about the CPU specifically being > an M55... Another one for the "maybe in rc4" bucket. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
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