This series provides the basic infrastructure for adding the new
32/64-bit instructions in Power ISA 3.1 to target/ppc.

It starts by changing decodetree.py to support 64-bit instructions
as well as custom variable-width instruction load functions.

Then it changes the target/ppc code to allow 32- and 64-bit instructions
to be decoded using decodetree, and finishes by adding the implementation
for 2 simple instructions to demonstrate the new approach:
- addi (replacing the legacy implementation)
- paddi (new)

Luis Pires (5):
  decodetree: Add support for 64-bit instructions
  decodetree: Fix empty input files for varinsnwidth
  decodetree: Allow custom var width load functions
  target/ppc: Base changes to allow 32/64-bit insns
  target/ppc: Implement paddi and replace addi insns

 docs/devel/decodetree.rst                  |   5 +-
 scripts/decodetree.py                      |  55 ++++--
 target/ppc/cpu.h                           |   1 +
 target/ppc/meson.build                     |   5 +
 target/ppc/ppc.decode                      |  26 +++
 target/ppc/translate.c                     | 206 +++++++++++++++------
 target/ppc/translate/fixedpoint-impl.c.inc |  26 +++
 7 files changed, 250 insertions(+), 74 deletions(-)
 create mode 100644 target/ppc/ppc.decode
 create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc

-- 
2.25.1