1
A few last patches to go in for rc3...
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
2
we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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4
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The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620:
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thanks
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-- PMM
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 12:12:09 +0100)
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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11
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are available in the Git repository at:
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are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210413
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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15
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for you to fetch changes up to 2d18b4ca023ca1a3aee18064251d6e6e1084f3eb:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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sphinx: qapidoc: Wrap "If" section body in a paragraph node (2021-04-13 10:14:58 +0100)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* Fix MPC setting for AN524 SRAM block
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guarded bit state when combining S1/S2 attrs
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* sphinx: qapidoc: Wrap "If" section body in a paragraph node
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23
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----------------------------------------------------------------
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----------------------------------------------------------------
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John Snow (1):
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Richard Henderson (2):
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sphinx: qapidoc: Wrap "If" section body in a paragraph node
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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28
24
Peter Maydell (2):
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target/arm/ptw.c | 11 ++++++-----
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hw/arm/mps2-tz: Fix MPC setting for AN524 SRAM block
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/arm/mps2-tz: Assert if more than one RAM is attached to an MPC
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docs/sphinx/qapidoc.py | 4 +++-
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hw/arm/mps2-tz.c | 10 +++++++---
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2 files changed, 10 insertions(+), 4 deletions(-)
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diff view generated by jsdifflib
Deleted patch
1
The AN524 has three MPCs: one for the BRAM, one for the QSPI flash,
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and one for the DDR. We incorrectly set the .mpc field in the
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RAMInfo struct for the SRAM block to 1, giving it the same MPC we are
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using for the QSPI. The effect of this was that the QSPI didn't get
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mapped into the system address space at all, via an MPC or otherwise,
6
and guest programs which tried to read from the QSPI would get a bus
7
error. Correct the SRAM RAMInfo to indicate that it does not have an
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associated MPC.
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1
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Fixes: 25ff112a8cc ("hw/arm/mps2-tz: Add new mps3-an524 board")
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Message-id: 20210409150527.15053-2-peter.maydell@linaro.org
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---
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hw/arm/mps2-tz.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/arm/mps2-tz.c
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+++ b/hw/arm/mps2-tz.c
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@@ -XXX,XX +XXX,XX @@ static const RAMInfo an524_raminfo[] = { {
24
.name = "sram",
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.base = 0x20000000,
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.size = 32 * 4 * KiB,
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- .mpc = 1,
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+ .mpc = -1,
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.mrindex = 1,
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}, {
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/* We don't model QSPI flash yet; for now expose it as simple ROM */
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--
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2.20.1
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diff view generated by jsdifflib
1
Each board in mps2-tz.c specifies a RAMInfo[] array providing
1
From: Richard Henderson <richard.henderson@linaro.org>
2
information about each RAM in the board. The .mpc field of the
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RAMInfo struct specifies which MPC, if any, the RAM is attached to.
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We already assert if the array doesn't have any entry for an MPC, but
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we don't diagnose the error of using the same MPC number twice (which
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is quite easy to do by accident if copy-and-pasting structure
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entries).
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2
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Enhance find_raminfo_for_mpc() so that it detects multiple entries
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Only perform the extract of GP during the stage1 walk.
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for the MPC as well as missing entries.
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4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Message-id: 20210409150527.15053-3-peter.maydell@linaro.org
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---
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---
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hw/arm/mps2-tz.c | 8 ++++++--
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 6 insertions(+), 2 deletions(-)
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1 file changed, 5 insertions(+), 5 deletions(-)
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13
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diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/mps2-tz.c
16
--- a/target/arm/ptw.c
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+++ b/hw/arm/mps2-tz.c
17
+++ b/target/arm/ptw.c
24
@@ -XXX,XX +XXX,XX @@ static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
25
{
19
result->f.attrs.secure = false;
26
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
27
const RAMInfo *p;
28
+ const RAMInfo *found = NULL;
29
30
for (p = mmc->raminfo; p->name; p++) {
31
if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {
32
- return p;
33
+ /* There should only be one entry in the array for this MPC */
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+ g_assert(!found);
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+ found = p;
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}
37
}
20
}
38
/* if raminfo array doesn't have an entry for each MPC this is a bug */
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39
- g_assert_not_reached();
22
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
40
+ assert(found);
23
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
41
+ return found;
24
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
42
}
25
- }
43
26
-
44
static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
27
if (regime_is_stage2(mmu_idx)) {
28
result->cacheattrs.is_s2_format = true;
29
result->cacheattrs.attrs = extract32(attrs, 2, 4);
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
31
assert(attrindx <= 7);
32
result->cacheattrs.is_s2_format = false;
33
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
34
+
35
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
36
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
37
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
38
+ }
39
}
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41
/*
45
--
42
--
46
2.20.1
43
2.34.1
47
48
diff view generated by jsdifflib
1
From: John Snow <jsnow@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
These sections need to be wrapped in a block-level element, such as
3
The guarded bit comes from the stage1 walk.
4
Paragraph in order for them to be rendered into Texinfo correctly.
5
4
6
Before (e.g.):
5
Fixes: Coverity CID 1507929
7
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
<section ids="qapidoc-713">
9
<title>If</title>
10
<literal>defined(CONFIG_REPLICATION)</literal>
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</section>
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became:
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15
.SS If
16
\fBdefined(CONFIG_REPLICATION)\fP.SS \fBBlockdevOptionsReplication\fP (Object)
17
...
18
19
After:
20
21
<section ids="qapidoc-713">
22
<title>If</title>
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<paragraph>
24
<literal>defined(CONFIG_REPLICATION)</literal>
25
</paragraph>
26
</section>
27
28
becomes:
29
30
.SS If
31
.sp
32
\fBdefined(CONFIG_REPLICATION)\fP
33
.SS \fBBlockdevOptionsReplication\fP (Object)
34
...
35
36
Reported-by: Markus Armbruster <armbru@redhat.com>
37
Tested-by: Markus Armbruster <armbru@redhat.com>
38
Signed-off-by: John Snow <jsnow@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20210406141909.1992225-2-jsnow@redhat.com
8
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
10
---
43
docs/sphinx/qapidoc.py | 4 +++-
11
target/arm/ptw.c | 1 +
44
1 file changed, 3 insertions(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
45
13
46
diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
47
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
48
--- a/docs/sphinx/qapidoc.py
16
--- a/target/arm/ptw.c
49
+++ b/docs/sphinx/qapidoc.py
17
+++ b/target/arm/ptw.c
50
@@ -XXX,XX +XXX,XX @@ def _nodes_for_if_section(self, ifcond):
18
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
51
nodelist = []
19
52
if ifcond:
20
assert(!s1.is_s2_format);
53
snode = self._make_section('If')
21
ret.is_s2_format = false;
54
- snode += self._nodes_for_ifcond(ifcond, with_if=False)
22
+ ret.guarded = s1.guarded;
55
+ snode += nodes.paragraph(
23
56
+ '', '', *self._nodes_for_ifcond(ifcond, with_if=False)
24
if (s1.attrs == 0xf0) {
57
+ )
25
tagged = true;
58
nodelist.append(snode)
59
return nodelist
60
61
--
26
--
62
2.20.1
27
2.34.1
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diff view generated by jsdifflib