1 | A few last patches to go in for rc3... | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
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2 | 2 | ||
3 | The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620: | 3 | -- PMM |
4 | 4 | ||
5 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 12:12:09 +0100) | 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: |
6 | |||
7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
6 | 8 | ||
7 | are available in the Git repository at: | 9 | are available in the Git repository at: |
8 | 10 | ||
9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210413 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
10 | 12 | ||
11 | for you to fetch changes up to 2d18b4ca023ca1a3aee18064251d6e6e1084f3eb: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
12 | 14 | ||
13 | sphinx: qapidoc: Wrap "If" section body in a paragraph node (2021-04-13 10:14:58 +0100) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
14 | 16 | ||
15 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
16 | target-arm queue: | 18 | target-arm queue: |
17 | * Fix MPC setting for AN524 SRAM block | 19 | * Fix KVM SVE ID register probe code |
18 | * sphinx: qapidoc: Wrap "If" section body in a paragraph node | ||
19 | 20 | ||
20 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
21 | John Snow (1): | 22 | Richard Henderson (3): |
22 | sphinx: qapidoc: Wrap "If" section body in a paragraph node | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
23 | 26 | ||
24 | Peter Maydell (2): | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
25 | hw/arm/mps2-tz: Fix MPC setting for AN524 SRAM block | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
26 | hw/arm/mps2-tz: Assert if more than one RAM is attached to an MPC | ||
27 | |||
28 | docs/sphinx/qapidoc.py | 4 +++- | ||
29 | hw/arm/mps2-tz.c | 10 +++++++--- | ||
30 | 2 files changed, 10 insertions(+), 4 deletions(-) | ||
31 | diff view generated by jsdifflib |
1 | The AN524 has three MPCs: one for the BRAM, one for the QSPI flash, | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | and one for the DDR. We incorrectly set the .mpc field in the | ||
3 | RAMInfo struct for the SRAM block to 1, giving it the same MPC we are | ||
4 | using for the QSPI. The effect of this was that the QSPI didn't get | ||
5 | mapped into the system address space at all, via an MPC or otherwise, | ||
6 | and guest programs which tried to read from the QSPI would get a bus | ||
7 | error. Correct the SRAM RAMInfo to indicate that it does not have an | ||
8 | associated MPC. | ||
9 | 2 | ||
10 | Fixes: 25ff112a8cc ("hw/arm/mps2-tz: Add new mps3-an524 board") | 3 | Indication for support for SVE will not depend on whether we |
4 | perform the query on the main kvm_state or the temp vcpu. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20210409150527.15053-2-peter.maydell@linaro.org | ||
15 | --- | 10 | --- |
16 | hw/arm/mps2-tz.c | 2 +- | 11 | target/arm/kvm64.c | 2 +- |
17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
18 | 13 | ||
19 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/mps2-tz.c | 16 | --- a/target/arm/kvm64.c |
22 | +++ b/hw/arm/mps2-tz.c | 17 | +++ b/target/arm/kvm64.c |
23 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an524_raminfo[] = { { | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
24 | .name = "sram", | 19 | } |
25 | .base = 0x20000000, | 20 | } |
26 | .size = 32 * 4 * KiB, | 21 | |
27 | - .mpc = 1, | 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; |
28 | + .mpc = -1, | 23 | + sve_supported = kvm_arm_sve_supported(); |
29 | .mrindex = 1, | 24 | |
30 | }, { | 25 | /* Add feature bits that can't appear until after VCPU init. */ |
31 | /* We don't model QSPI flash yet; for now expose it as simple ROM */ | 26 | if (sve_supported) { |
32 | -- | 27 | -- |
33 | 2.20.1 | 28 | 2.25.1 |
34 | |||
35 | diff view generated by jsdifflib |
1 | Each board in mps2-tz.c specifies a RAMInfo[] array providing | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | information about each RAM in the board. The .mpc field of the | ||
3 | RAMInfo struct specifies which MPC, if any, the RAM is attached to. | ||
4 | We already assert if the array doesn't have any entry for an MPC, but | ||
5 | we don't diagnose the error of using the same MPC number twice (which | ||
6 | is quite easy to do by accident if copy-and-pasting structure | ||
7 | entries). | ||
8 | 2 | ||
9 | Enhance find_raminfo_for_mpc() so that it detects multiple entries | 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 |
10 | for the MPC as well as missing entries. | 4 | was always returning zero. This also obviates the adjustment |
5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
11 | 6 | ||
7 | The effects of the bug are not visible, because the only thing that | ||
8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
10 | |||
11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Message-id: 20210409150527.15053-3-peter.maydell@linaro.org | ||
16 | --- | 16 | --- |
17 | hw/arm/mps2-tz.c | 8 ++++++-- | 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- |
18 | 1 file changed, 6 insertions(+), 2 deletions(-) | 18 | 1 file changed, 13 insertions(+), 14 deletions(-) |
19 | 19 | ||
20 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
21 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/arm/mps2-tz.c | 22 | --- a/target/arm/kvm64.c |
23 | +++ b/hw/arm/mps2-tz.c | 23 | +++ b/target/arm/kvm64.c |
24 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) | 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
25 | { | 25 | bool sve_supported; |
26 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | 26 | bool pmu_supported = false; |
27 | const RAMInfo *p; | 27 | uint64_t features = 0; |
28 | + const RAMInfo *found = NULL; | 28 | - uint64_t t; |
29 | 29 | int err; | |
30 | for (p = mmc->raminfo; p->name; p++) { | 30 | |
31 | if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { | 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however |
32 | - return p; | 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
33 | + /* There should only be one entry in the array for this MPC */ | 33 | struct kvm_vcpu_init init = { .target = -1, }; |
34 | + g_assert(!found); | 34 | |
35 | + found = p; | 35 | /* |
36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
39 | - * we have to use the actual ID regs. | ||
40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
41 | + * which is otherwise RAZ. | ||
42 | + */ | ||
43 | + sve_supported = kvm_arm_sve_supported(); | ||
44 | + if (sve_supported) { | ||
45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
46 | + } | ||
47 | + | ||
48 | + /* | ||
49 | + * Ask for Pointer Authentication if supported, so that we get | ||
50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
51 | */ | ||
52 | if (kvm_arm_pauth_supported()) { | ||
53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
36 | } | 55 | } |
37 | } | 56 | } |
38 | /* if raminfo array doesn't have an entry for each MPC this is a bug */ | 57 | |
39 | - g_assert_not_reached(); | 58 | - sve_supported = kvm_arm_sve_supported(); |
40 | + assert(found); | 59 | - |
41 | + return found; | 60 | - /* Add feature bits that can't appear until after VCPU init. */ |
42 | } | 61 | if (sve_supported) { |
43 | 62 | - t = ahcf->isar.id_aa64pfr0; | |
44 | static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, | 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
64 | - ahcf->isar.id_aa64pfr0 = t; | ||
65 | - | ||
66 | /* | ||
67 | * There is a range of kernels between kernel commit 73433762fcae | ||
68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
70 | - * SVE support, so we only read it here, rather than together with all | ||
71 | - * the other ID registers earlier. | ||
72 | + * SVE support, which resulted in an error rather than RAZ. | ||
73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
74 | */ | ||
75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
45 | -- | 77 | -- |
46 | 2.20.1 | 78 | 2.25.1 |
47 | |||
48 | diff view generated by jsdifflib |
1 | From: John Snow <jsnow@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These sections need to be wrapped in a block-level element, such as | 3 | The test for the IF block indicates no ID registers are exposed, much |
4 | Paragraph in order for them to be rendered into Texinfo correctly. | 4 | less host support for SVE. Move the SVE probe into the ELSE block. |
5 | 5 | ||
6 | Before (e.g.): | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | |
8 | <section ids="qapidoc-713"> | ||
9 | <title>If</title> | ||
10 | <literal>defined(CONFIG_REPLICATION)</literal> | ||
11 | </section> | ||
12 | |||
13 | became: | ||
14 | |||
15 | .SS If | ||
16 | \fBdefined(CONFIG_REPLICATION)\fP.SS \fBBlockdevOptionsReplication\fP (Object) | ||
17 | ... | ||
18 | |||
19 | After: | ||
20 | |||
21 | <section ids="qapidoc-713"> | ||
22 | <title>If</title> | ||
23 | <paragraph> | ||
24 | <literal>defined(CONFIG_REPLICATION)</literal> | ||
25 | </paragraph> | ||
26 | </section> | ||
27 | |||
28 | becomes: | ||
29 | |||
30 | .SS If | ||
31 | .sp | ||
32 | \fBdefined(CONFIG_REPLICATION)\fP | ||
33 | .SS \fBBlockdevOptionsReplication\fP (Object) | ||
34 | ... | ||
35 | |||
36 | Reported-by: Markus Armbruster <armbru@redhat.com> | ||
37 | Tested-by: Markus Armbruster <armbru@redhat.com> | ||
38 | Signed-off-by: John Snow <jsnow@redhat.com> | ||
39 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
40 | Message-id: 20210406141909.1992225-2-jsnow@redhat.com | ||
41 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
42 | --- | 10 | --- |
43 | docs/sphinx/qapidoc.py | 4 +++- | 11 | target/arm/kvm64.c | 22 +++++++++++----------- |
44 | 1 file changed, 3 insertions(+), 1 deletion(-) | 12 | 1 file changed, 11 insertions(+), 11 deletions(-) |
45 | 13 | ||
46 | diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
47 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/docs/sphinx/qapidoc.py | 16 | --- a/target/arm/kvm64.c |
49 | +++ b/docs/sphinx/qapidoc.py | 17 | +++ b/target/arm/kvm64.c |
50 | @@ -XXX,XX +XXX,XX @@ def _nodes_for_if_section(self, ifcond): | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
51 | nodelist = [] | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, |
52 | if ifcond: | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
53 | snode = self._make_section('If') | 21 | } |
54 | - snode += self._nodes_for_ifcond(ifcond, with_if=False) | 22 | - } |
55 | + snode += nodes.paragraph( | 23 | |
56 | + '', '', *self._nodes_for_ifcond(ifcond, with_if=False) | 24 | - if (sve_supported) { |
57 | + ) | 25 | - /* |
58 | nodelist.append(snode) | 26 | - * There is a range of kernels between kernel commit 73433762fcae |
59 | return nodelist | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
60 | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | |
29 | - * SVE support, which resulted in an error rather than RAZ. | ||
30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
31 | - */ | ||
32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
34 | + if (sve_supported) { | ||
35 | + /* | ||
36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
41 | + */ | ||
42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
44 | + } | ||
45 | } | ||
46 | |||
47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
61 | -- | 48 | -- |
62 | 2.20.1 | 49 | 2.25.1 |
63 | |||
64 | diff view generated by jsdifflib |