[PULL 0/5] target-arm queue
[PULL v2 00/25] target-arm queue
1
Handful of arm fixes for the rc.
1
v2: drop npcm7xx sdhci tests: new tests assert on some platforms.
2
2
3
The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
3
-- PMM
4
4
5
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)
5
The following changes since commit e670f6d825d4dee248b311197fd4048469d6772b:
6
7
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into staging (2022-02-20 15:05:41 +0000)
6
8
7
are available in the Git repository at:
9
are available in the Git repository at:
8
10
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220221-1
10
12
11
for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
13
for you to fetch changes up to ca511604925eef8572e22ecbf0d3c758d7277924:
12
14
13
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
15
ui/cocoa: Fix the leak of qemu_console_get_label (2022-02-21 13:30:21 +0000)
14
16
15
----------------------------------------------------------------
17
----------------------------------------------------------------
16
target-arm queue:
18
arm, cocoa and misc:
17
* hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
19
* MAINTAINERS file updates
18
* hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
20
* Mark remaining global TypeInfo instances as const
19
* accel/tcg: Preserve PAGE_ANON when changing page permissions
21
* checkpatch: Ensure that TypeInfos are const
20
* target/arm: Check PAGE_WRITE_ORG for MTE writeability
22
* arm hvf: Handle unknown ID registers as RES0
21
* exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
23
* Make KVM -cpu max exactly like -cpu host
24
* Fix '-cpu max' for HVF
25
* Support PAuth extension for hvf
26
* Kconfig: Add I2C_DEVICES device group
27
* Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
28
* hw/arm/armv7m: Handle disconnected clock inputs
29
* osdep.h: pull out various things into new header files
30
* hw/timer: fix a9gtimer vmstate
31
* hw/arm: add initial mori-bmc board
32
* ui/cocoa: Remove allowedFileTypes restriction in SavePanel
33
* ui/cocoa: Do not alert even without block devices
34
* ui/cocoa: Fix the leak of qemu_console_get_label
22
35
23
----------------------------------------------------------------
36
----------------------------------------------------------------
24
Richard Henderson (3):
37
Akihiko Odaki (3):
25
accel/tcg: Preserve PAGE_ANON when changing page permissions
38
MAINTAINERS: Add Akihiko Odaki to macOS-relateds
26
target/arm: Check PAGE_WRITE_ORG for MTE writeability
39
ui/cocoa: Do not alert even without block devices
27
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
40
ui/cocoa: Fix the leak of qemu_console_get_label
28
41
29
Zenghui Yu (2):
42
Alexander Graf (2):
30
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
43
hvf: arm: Use macros for sysreg shift/masking
31
hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
44
hvf: arm: Handle unknown ID registers as RES0
32
45
33
include/exec/cpu-all.h | 4 ++--
46
Ani Sinha (1):
34
tests/tcg/aarch64/mte.h | 3 ++-
47
MAINTAINERS: Adding myself as a reviewer of some components
35
accel/tcg/translate-all.c | 9 ++++++--
36
hw/arm/smmuv3.c | 12 +++++++----
37
hw/arm/virt-acpi-build.c | 4 ++--
38
target/arm/mte_helper.c | 2 +-
39
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++++++++++
40
tests/tcg/aarch64/Makefile.target | 2 +-
41
8 files changed, 66 insertions(+), 13 deletions(-)
42
create mode 100644 tests/tcg/aarch64/mte-6.c
43
48
49
Bernhard Beschow (2):
50
Mark remaining global TypeInfo instances as const
51
checkpatch: Ensure that TypeInfos are const
52
53
Patrick Venture (1):
54
hw/arm: add initial mori-bmc board
55
56
Pavel Dovgalyuk (1):
57
hw/timer: fix a9gtimer vmstate
58
59
Peter Maydell (14):
60
target/arm: Move '-cpu host' code to cpu64.c
61
target/arm: Use aarch64_cpu_register() for 'host' CPU type
62
target/arm: Make KVM -cpu max exactly like -cpu host
63
target/arm: Unindent unnecessary else-clause
64
target/arm: Fix '-cpu max' for HVF
65
target/arm: Support PAuth extension for hvf
66
Kconfig: Add I2C_DEVICES device group
67
Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus
68
hw/arm/armv7m: Handle disconnected clock inputs
69
include: Move qemu_madvise() and related #defines to new qemu/madvise.h
70
include: Move qemu_mprotect_*() to new qemu/mprotect.h
71
include: Move QEMU_MAP_* constants to mmap-alloc.h
72
include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h
73
include: Move hardware version declarations to new qemu/hw-version.h
74
75
Philippe Mathieu-Daudé (1):
76
ui/cocoa: Remove allowedFileTypes restriction in SavePanel
77
78
docs/devel/kconfig.rst | 8 +-
79
docs/system/arm/nuvoton.rst | 1 +
80
include/qemu/cacheinfo.h | 21 +++
81
include/qemu/hw-version.h | 27 ++++
82
include/qemu/madvise.h | 95 +++++++++++++
83
include/qemu/mmap-alloc.h | 23 +++
84
include/qemu/mprotect.h | 14 ++
85
include/qemu/osdep.h | 132 ------------------
86
accel/tcg/translate-all.c | 1 +
87
backends/hostmem-file.c | 1 +
88
backends/hostmem.c | 1 +
89
hw/arm/armv7m.c | 26 +++-
90
hw/arm/npcm7xx_boards.c | 32 +++++
91
hw/arm/nseries.c | 1 +
92
hw/core/generic-loader.c | 2 +-
93
hw/core/guest-loader.c | 2 +-
94
hw/display/bcm2835_fb.c | 2 +-
95
hw/display/i2c-ddc.c | 2 +-
96
hw/display/macfb.c | 4 +-
97
hw/display/virtio-vga.c | 2 +-
98
hw/dma/bcm2835_dma.c | 2 +-
99
hw/i386/pc_piix.c | 2 +-
100
hw/i386/sgx-epc.c | 2 +-
101
hw/ide/core.c | 1 +
102
hw/intc/bcm2835_ic.c | 2 +-
103
hw/intc/bcm2836_control.c | 2 +-
104
hw/ipmi/ipmi.c | 4 +-
105
hw/mem/nvdimm.c | 2 +-
106
hw/mem/pc-dimm.c | 2 +-
107
hw/misc/bcm2835_mbox.c | 2 +-
108
hw/misc/bcm2835_powermgt.c | 2 +-
109
hw/misc/bcm2835_property.c | 2 +-
110
hw/misc/bcm2835_rng.c | 2 +-
111
hw/misc/pvpanic-isa.c | 2 +-
112
hw/misc/pvpanic-pci.c | 2 +-
113
hw/net/fsl_etsec/etsec.c | 2 +-
114
hw/ppc/prep_systemio.c | 2 +-
115
hw/ppc/spapr_iommu.c | 2 +-
116
hw/s390x/s390-pci-bus.c | 2 +-
117
hw/s390x/sclp.c | 2 +-
118
hw/s390x/tod-kvm.c | 2 +-
119
hw/s390x/tod-tcg.c | 2 +-
120
hw/s390x/tod.c | 2 +-
121
hw/scsi/lsi53c895a.c | 2 +-
122
hw/scsi/megasas.c | 1 +
123
hw/scsi/scsi-bus.c | 1 +
124
hw/scsi/scsi-disk.c | 1 +
125
hw/sd/allwinner-sdhost.c | 2 +-
126
hw/sd/aspeed_sdhci.c | 2 +-
127
hw/sd/bcm2835_sdhost.c | 2 +-
128
hw/sd/cadence_sdhci.c | 2 +-
129
hw/sd/npcm7xx_sdhci.c | 2 +-
130
hw/timer/a9gtimer.c | 21 +++
131
hw/usb/dev-mtp.c | 2 +-
132
hw/usb/host-libusb.c | 2 +-
133
hw/vfio/igd.c | 2 +-
134
hw/virtio/virtio-balloon.c | 1 +
135
hw/virtio/virtio-pmem.c | 2 +-
136
migration/postcopy-ram.c | 1 +
137
migration/qemu-file.c | 1 +
138
migration/ram.c | 1 +
139
plugins/loader.c | 1 +
140
qom/object.c | 4 +-
141
softmmu/physmem.c | 1 +
142
softmmu/vl.c | 1 +
143
target/arm/cpu.c | 30 ----
144
target/arm/cpu64.c | 331 ++++++++++++++++++++++++--------------------
145
target/arm/hvf/hvf.c | 83 ++++++++---
146
target/i386/cpu.c | 1 +
147
target/s390x/cpu_models.c | 1 +
148
tcg/region.c | 3 +
149
tcg/tcg.c | 1 +
150
util/atomic64.c | 1 +
151
util/cacheflush.c | 1 +
152
util/cacheinfo.c | 1 +
153
util/osdep.c | 3 +
154
util/oslib-posix.c | 1 +
155
MAINTAINERS | 5 +
156
hw/arm/Kconfig | 10 ++
157
hw/i2c/Kconfig | 5 +
158
hw/rtc/Kconfig | 2 +
159
hw/sensor/Kconfig | 5 +
160
scripts/checkpatch.pl | 1 +
161
ui/cocoa.m | 15 +-
162
84 files changed, 606 insertions(+), 393 deletions(-)
163
create mode 100644 include/qemu/cacheinfo.h
164
create mode 100644 include/qemu/hw-version.h
165
create mode 100644 include/qemu/madvise.h
166
create mode 100644 include/qemu/mprotect.h
167
diff view generated by jsdifflib
[PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
Deleted patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
1
3
The GSIV values in SMMUv3 IORT node are not correct as they don't match
4
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
5
our emulated vSMMU.
6
7
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
8
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
9
Acked-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt-acpi-build.c | 4 ++--
14
1 file changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
21
smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
22
smmu->event_gsiv = cpu_to_le32(irq);
23
smmu->pri_gsiv = cpu_to_le32(irq + 1);
24
- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
25
- smmu->sync_gsiv = cpu_to_le32(irq + 3);
26
+ smmu->sync_gsiv = cpu_to_le32(irq + 2);
27
+ smmu->gerr_gsiv = cpu_to_le32(irq + 3);
28
29
/* Identity RID mapping covering the whole input RID range */
30
idmap = &smmu->id_mapping_array[0];
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
Deleted patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
1
3
In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
4
start of the invalidation range, regardless of whatever the Range is,
5
whilst the spec clearly states that
6
7
- "Invalidation is performed for an *aligned* range of 2^(Range+1)
8
StreamIDs."
9
10
- "The bottom Range+1 bits of the StreamID parameter are IGNORED,
11
aligning the range to its size."
12
13
Take CFGI_ALL (where Range == 31) as an example, if there are some random
14
bits in the StreamID field, we'll fail to perform the full invalidation but
15
get a strange range (e.g., SMMUSIDRange={.start=1, .end=0}) instead. Rework
16
the emulation a bit to get rid of the discrepancy with the spec.
17
18
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
19
Acked-by: Eric Auger <eric.auger@redhat.com>
20
Message-id: 20210402100449.528-1-yuzenghui@huawei.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/arm/smmuv3.c | 12 ++++++++----
24
1 file changed, 8 insertions(+), 4 deletions(-)
25
26
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/smmuv3.c
29
+++ b/hw/arm/smmuv3.c
30
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
31
}
32
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
33
{
34
- uint32_t start = CMD_SID(&cmd);
35
+ uint32_t sid = CMD_SID(&cmd), mask;
36
uint8_t range = CMD_STE_RANGE(&cmd);
37
- uint64_t end = start + (1ULL << (range + 1)) - 1;
38
- SMMUSIDRange sid_range = {start, end};
39
+ SMMUSIDRange sid_range;
40
41
if (CMD_SSEC(&cmd)) {
42
cmd_error = SMMU_CERROR_ILL;
43
break;
44
}
45
- trace_smmuv3_cmdq_cfgi_ste_range(start, end);
46
+
47
+ mask = (1ULL << (range + 1)) - 1;
48
+ sid_range.start = sid & ~mask;
49
+ sid_range.end = sid_range.start + mask;
50
+
51
+ trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
52
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
53
&sid_range);
54
break;
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
[PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Using mprotect() to change PROT_* does not change the MAP_ANON
4
previously set with mmap(). Our linux-user version of MTE only
5
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
6
stop working.
7
8
Reported-by: Stephen Long <steplong@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
tests/tcg/aarch64/mte.h | 3 ++-
15
accel/tcg/translate-all.c | 9 +++++--
16
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++
17
tests/tcg/aarch64/Makefile.target | 2 +-
18
4 files changed, 53 insertions(+), 4 deletions(-)
19
create mode 100644 tests/tcg/aarch64/mte-6.c
20
21
diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tests/tcg/aarch64/mte.h
24
+++ b/tests/tcg/aarch64/mte.h
25
@@ -XXX,XX +XXX,XX @@ static void enable_mte(int tcf)
26
}
27
}
28
29
-static void *alloc_mte_mem(size_t size)
30
+static void * alloc_mte_mem(size_t size) __attribute__((unused));
31
+static void * alloc_mte_mem(size_t size)
32
{
33
void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE,
34
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
35
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/accel/tcg/translate-all.c
38
+++ b/accel/tcg/translate-all.c
39
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
40
a missing call to h2g_valid. */
41
assert(end - 1 <= GUEST_ADDR_MAX);
42
assert(start < end);
43
+ /* Only set PAGE_ANON with new mappings. */
44
+ assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET));
45
assert_memory_lock();
46
47
start = start & TARGET_PAGE_MASK;
48
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
49
p->first_tb) {
50
tb_invalidate_phys_page(addr, 0);
51
}
52
- if (reset_target_data && p->target_data) {
53
+ if (reset_target_data) {
54
g_free(p->target_data);
55
p->target_data = NULL;
56
+ p->flags = flags;
57
+ } else {
58
+ /* Using mprotect on a page does not change MAP_ANON. */
59
+ p->flags = (p->flags & PAGE_ANON) | flags;
60
}
61
- p->flags = flags;
62
}
63
}
64
65
diff --git a/tests/tcg/aarch64/mte-6.c b/tests/tcg/aarch64/mte-6.c
66
new file mode 100644
67
index XXXXXXX..XXXXXXX
68
--- /dev/null
69
+++ b/tests/tcg/aarch64/mte-6.c
70
@@ -XXX,XX +XXX,XX @@
71
+#include "mte.h"
72
+
73
+void pass(int sig, siginfo_t *info, void *uc)
74
+{
75
+ assert(info->si_code == SEGV_MTESERR);
76
+ exit(0);
77
+}
78
+
79
+int main(void)
80
+{
81
+ enable_mte(PR_MTE_TCF_SYNC);
82
+
83
+ void *brk = sbrk(16);
84
+ if (brk == (void *)-1) {
85
+ perror("sbrk");
86
+ return 2;
87
+ }
88
+
89
+ if (mprotect(brk, 16, PROT_READ | PROT_WRITE | PROT_MTE)) {
90
+ perror("mprotect");
91
+ return 2;
92
+ }
93
+
94
+ int *p1, *p2;
95
+ long excl = 1;
96
+
97
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(brk), "r"(excl));
98
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r"(p1));
99
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(brk), "r"(excl));
100
+ asm("stg %0,[%0]" : : "r"(p1));
101
+
102
+ *p1 = 0;
103
+
104
+ struct sigaction sa;
105
+ memset(&sa, 0, sizeof(sa));
106
+ sa.sa_sigaction = pass;
107
+ sa.sa_flags = SA_SIGINFO;
108
+ sigaction(SIGSEGV, &sa, NULL);
109
+
110
+ *p2 = 0;
111
+
112
+ abort();
113
+}
114
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
115
index XXXXXXX..XXXXXXX 100644
116
--- a/tests/tcg/aarch64/Makefile.target
117
+++ b/tests/tcg/aarch64/Makefile.target
118
@@ -XXX,XX +XXX,XX @@ AARCH64_TESTS += bti-2
119
120
# MTE Tests
121
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
122
-AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4
123
+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6
124
mte-%: CFLAGS += -march=armv8.5-a+memtag
125
endif
126
127
--
128
2.20.1
129
130
diff view generated by jsdifflib
[PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We can remove PAGE_WRITE when (internally) marking a page
4
read-only because it contains translated code.
5
6
This can be triggered by tests/tcg/aarch64/bti-2, after
7
having serviced SIGILL trampolines on the stack.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/mte_helper.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/mte_helper.c
19
+++ b/target/arm/mte_helper.c
20
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
21
uint8_t *tags;
22
uintptr_t index;
23
24
- if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
25
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
26
/* SIGSEGV */
27
arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
28
ptr_mmu_idx, false, ra);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Unfortuately, the elements of PAGE_* were not in numerical
4
order and so PAGE_ANON was added to an "unused" bit.
5
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
6
7
Cc: Laurent Vivier <laurent@vivier.eu>
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Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
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Buglink: https://bugs.launchpad.net/bugs/1922617
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Reviewed-by: Laurent Vivier <laurent@vivier.eu>
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Tested-by: Laurent Vivier <laurent@vivier.eu>
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Tested-by: Nathan Chancellor <nathan@kernel.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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include/exec/cpu-all.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/cpu-all.h
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+++ b/include/exec/cpu-all.h
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@@ -XXX,XX +XXX,XX @@ extern intptr_t qemu_host_page_mask;
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#define PAGE_RESERVED 0x0100
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#endif
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/* Target-specific bits that will be used via page_get_flags(). */
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-#define PAGE_TARGET_1 0x0080
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-#define PAGE_TARGET_2 0x0200
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+#define PAGE_TARGET_1 0x0200
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+#define PAGE_TARGET_2 0x0400
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#if defined(CONFIG_USER_ONLY)
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void page_dump(FILE *f);
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--
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2.20.1
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Patchew 2.1-devel-b67e4c2

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