1 | A few patches for the rc today... | 1 | A last small test of bug fixes before rc1. |
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2 | 2 | ||
3 | The following changes since commit 109918d24a3bb9ed3d05beb34ea4ac6be443c138: | 3 | thanks |
4 | -- PMM | ||
4 | 5 | ||
5 | Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-04-05 22:15:38 +0100) | 6 | The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637: |
7 | |||
8 | Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100) | ||
6 | 9 | ||
7 | are available in the Git repository at: | 10 | are available in the Git repository at: |
8 | 11 | ||
9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210406 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717 |
10 | 13 | ||
11 | for you to fetch changes up to 49bc76550c37f4a2b92a05cb3e6989a739d56ac9: | 14 | for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4: |
12 | 15 | ||
13 | Remove myself as i.mx31 maintainer (2021-04-06 11:49:15 +0100) | 16 | hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100) |
14 | 17 | ||
15 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
16 | target-arm queue: | 19 | target-arm queue: |
17 | * ppc/e500 and arm/virt: only add valid dynamic sysbus devices to the | 20 | * hw/arm/sbsa-ref: set 'slots' property of xhci |
18 | platform bus | 21 | * linux-user: Remove pointless NULL check in clock_adjtime handling |
19 | * update i.mx31 maintainer list | 22 | * ptw: Fix S1_ptw_translate() debug path |
20 | * Revert "target/arm: Make number of counters in PMCR follow the CPU" | 23 | * ptw: Account for FEAT_RME when applying {N}SW, SA bits |
24 | * accel/tcg: Zero-pad PC in TCG CPU exec trace lines | ||
25 | * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write | ||
21 | 26 | ||
22 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
23 | Chubb, Peter (Data61, Eveleigh) (1): | 28 | Peter Maydell (5): |
24 | Remove myself as i.mx31 maintainer | 29 | linux-user: Remove pointless NULL check in clock_adjtime handling |
30 | target/arm/ptw.c: Add comments to S1Translate struct fields | ||
31 | target/arm: Fix S1_ptw_translate() debug path | ||
32 | target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits | ||
33 | accel/tcg: Zero-pad PC in TCG CPU exec trace lines | ||
25 | 34 | ||
26 | Peter Maydell (5): | 35 | Tong Ho (1): |
27 | include/hw/boards.h: Document machine_class_allow_dynamic_sysbus_dev() | 36 | hw/nvram: Avoid unnecessary Xilinx eFuse backstore write |
28 | machine: Provide a function to check the dynamic sysbus allowlist | ||
29 | hw/arm/virt: Only try to add valid dynamic sysbus devices to platform bus | ||
30 | hw/ppc/e500plat: Only try to add valid dynamic sysbus devices to platform bus | ||
31 | Revert "target/arm: Make number of counters in PMCR follow the CPU" | ||
32 | 37 | ||
33 | include/hw/boards.h | 39 +++++++++++++++++++++++++++++++++++++++ | 38 | Yuquan Wang (1): |
34 | target/arm/cpu.h | 1 - | 39 | hw/arm/sbsa-ref: set 'slots' property of xhci |
35 | hw/arm/virt.c | 8 ++++++-- | ||
36 | hw/core/machine.c | 21 ++++++++++++++++----- | ||
37 | hw/ppc/e500plat.c | 8 ++++++-- | ||
38 | target/arm/cpu64.c | 3 --- | ||
39 | target/arm/cpu_tcg.c | 5 ----- | ||
40 | target/arm/helper.c | 29 ++++++++++++----------------- | ||
41 | target/arm/kvm64.c | 2 -- | ||
42 | MAINTAINERS | 1 - | ||
43 | 10 files changed, 79 insertions(+), 38 deletions(-) | ||
44 | 40 | ||
41 | accel/tcg/cpu-exec.c | 4 +-- | ||
42 | accel/tcg/translate-all.c | 2 +- | ||
43 | hw/arm/sbsa-ref.c | 1 + | ||
44 | hw/nvram/xlnx-efuse.c | 11 ++++-- | ||
45 | linux-user/syscall.c | 12 +++---- | ||
46 | target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------ | ||
47 | 6 files changed, 98 insertions(+), 22 deletions(-) | diff view generated by jsdifflib |
New patch | |||
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1 | From: Yuquan Wang <wangyuquan1236@phytium.com.cn> | ||
1 | 2 | ||
3 | This extends the slots of xhci to 64, since the default xhci_sysbus | ||
4 | just supports one slot. | ||
5 | |||
6 | Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn> | ||
7 | Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
10 | Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
11 | Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/sbsa-ref.c | 1 + | ||
15 | 1 file changed, 1 insertion(+) | ||
16 | |||
17 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/sbsa-ref.c | ||
20 | +++ b/hw/arm/sbsa-ref.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms) | ||
22 | hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; | ||
23 | int irq = sbsa_ref_irqmap[SBSA_XHCI]; | ||
24 | DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); | ||
25 | + qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); | ||
26 | |||
27 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
28 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
1 | The e500plat machine device plug callback currently calls | 1 | In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to |
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2 | platform_bus_link_device() for any sysbus device. This is overly | 2 | the address of the local variable htx. This means it can never be |
3 | broad, because platform_bus_link_device() will unconditionally grab | 3 | NULL, but later in the code we check it for NULL anyway. Coverity |
4 | the IRQs and MMIOs of the device it is passed, whether it was | 4 | complains about this (CID 1507683) because the NULL check comes after |
5 | intended for the platform bus or not. Restrict hotpluggability of | 5 | a call to clock_adjtime() that assumes it is non-NULL. |
6 | sysbus devices to only those devices on the dynamic sysbus allowlist. | ||
7 | 6 | ||
8 | We were mostly getting away with this because the board creates the | 7 | Since phtx is always &htx, and is used only in three places, it's not |
9 | platform bus as the last device it creates, and so the hotplug | 8 | really necessary. Remove it, bringing the code structure in to line |
10 | callback did not do anything for all the sysbus devices created by | 9 | with that for TARGET_NR_clock_adjtime64, which already uses a simple |
11 | the board itself. However if the user plugged in a device which | 10 | '&htx' when it wants a pointer to 'htx'. |
12 | itself uses a sysbus device internally we would have mishandled this | ||
13 | and probably asserted. An example of this is: | ||
14 | qemu-system-ppc64 -M ppce500 -device macio-oldworld | ||
15 | |||
16 | This isn't a sensible command because the macio-oldworld device | ||
17 | is really specific to the 'g3beige' machine, but we now fail | ||
18 | with a reasonable error message rather than asserting: | ||
19 | qemu-system-ppc64: Device heathrow is not supported by this machine yet. | ||
20 | 11 | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
23 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 15 | Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org |
24 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
25 | Acked-by: David Gibson <david@gibson.dropbear.id.au> | ||
26 | Message-id: 20210325153310.9131-5-peter.maydell@linaro.org | ||
27 | --- | 16 | --- |
28 | hw/ppc/e500plat.c | 8 ++++++-- | 17 | linux-user/syscall.c | 12 +++++------- |
29 | 1 file changed, 6 insertions(+), 2 deletions(-) | 18 | 1 file changed, 5 insertions(+), 7 deletions(-) |
30 | 19 | ||
31 | diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c | 20 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c |
32 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/ppc/e500plat.c | 22 | --- a/linux-user/syscall.c |
34 | +++ b/hw/ppc/e500plat.c | 23 | +++ b/linux-user/syscall.c |
35 | @@ -XXX,XX +XXX,XX @@ static void e500plat_machine_device_plug_cb(HotplugHandler *hotplug_dev, | 24 | @@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, |
36 | PPCE500MachineState *pms = PPCE500_MACHINE(hotplug_dev); | 25 | #if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME) |
37 | 26 | case TARGET_NR_clock_adjtime: | |
38 | if (pms->pbus_dev) { | 27 | { |
39 | - if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { | 28 | - struct timex htx, *phtx = &htx; |
40 | + MachineClass *mc = MACHINE_GET_CLASS(pms); | 29 | + struct timex htx; |
41 | + | 30 | |
42 | + if (device_is_dynamic_sysbus(mc, dev)) { | 31 | - if (target_to_host_timex(phtx, arg2) != 0) { |
43 | platform_bus_link_device(pms->pbus_dev, SYS_BUS_DEVICE(dev)); | 32 | + if (target_to_host_timex(&htx, arg2) != 0) { |
33 | return -TARGET_EFAULT; | ||
34 | } | ||
35 | - ret = get_errno(clock_adjtime(arg1, phtx)); | ||
36 | - if (!is_error(ret) && phtx) { | ||
37 | - if (host_to_target_timex(arg2, phtx) != 0) { | ||
38 | - return -TARGET_EFAULT; | ||
39 | - } | ||
40 | + ret = get_errno(clock_adjtime(arg1, &htx)); | ||
41 | + if (!is_error(ret) && host_to_target_timex(arg2, &htx)) { | ||
42 | + return -TARGET_EFAULT; | ||
43 | } | ||
44 | } | 44 | } |
45 | } | 45 | return ret; |
46 | @@ -XXX,XX +XXX,XX @@ static | ||
47 | HotplugHandler *e500plat_machine_get_hotpug_handler(MachineState *machine, | ||
48 | DeviceState *dev) | ||
49 | { | ||
50 | - if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { | ||
51 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
52 | + | ||
53 | + if (device_is_dynamic_sysbus(mc, dev)) { | ||
54 | return HOTPLUG_HANDLER(machine); | ||
55 | } | ||
56 | |||
57 | -- | 46 | -- |
58 | 2.20.1 | 47 | 2.34.1 |
59 | 48 | ||
60 | 49 | diff view generated by jsdifflib |
1 | This reverts commit f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f. | 1 | Add comments to the in_* fields in the S1Translate struct |
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2 | that explain what they're doing. | ||
2 | 3 | ||
3 | This change turned out to be a bit half-baked, and doesn't | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | work with KVM, which fails with the error: | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | "qemu-system-aarch64: Failed to retrieve host CPU features" | 6 | Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org |
7 | --- | ||
8 | target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 40 insertions(+) | ||
6 | 10 | ||
7 | because KVM does not allow accessing of the PMCR_EL0 value in | 11 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
8 | the scratch "query CPU ID registers" VM unless we have first | ||
9 | set the KVM_ARM_VCPU_PMU_V3 feature on the VM. | ||
10 | |||
11 | Revert the change for 6.0. | ||
12 | |||
13 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Tested-by: Zenghui Yu <yuzenghui@huawei.com> | ||
16 | Message-id: 20210331154822.23332-1-peter.maydell@linaro.org | ||
17 | --- | ||
18 | target/arm/cpu.h | 1 - | ||
19 | target/arm/cpu64.c | 3 --- | ||
20 | target/arm/cpu_tcg.c | 5 ----- | ||
21 | target/arm/helper.c | 29 ++++++++++++----------------- | ||
22 | target/arm/kvm64.c | 2 -- | ||
23 | 5 files changed, 12 insertions(+), 28 deletions(-) | ||
24 | |||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/cpu.h | 13 | --- a/target/arm/ptw.c |
28 | +++ b/target/arm/cpu.h | 14 | +++ b/target/arm/ptw.c |
29 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
30 | uint64_t id_aa64mmfr2; | ||
31 | uint64_t id_aa64dfr0; | ||
32 | uint64_t id_aa64dfr1; | ||
33 | - uint64_t reset_pmcr_el0; | ||
34 | } isar; | ||
35 | uint64_t midr; | ||
36 | uint32_t revidr; | ||
37 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/cpu64.c | ||
40 | +++ b/target/arm/cpu64.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
42 | cpu->gic_num_lrs = 4; | ||
43 | cpu->gic_vpribits = 5; | ||
44 | cpu->gic_vprebits = 5; | ||
45 | - cpu->isar.reset_pmcr_el0 = 0x41013000; | ||
46 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
47 | } | ||
48 | |||
49 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
50 | cpu->gic_num_lrs = 4; | ||
51 | cpu->gic_vpribits = 5; | ||
52 | cpu->gic_vprebits = 5; | ||
53 | - cpu->isar.reset_pmcr_el0 = 0x41033000; | ||
54 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
55 | } | ||
56 | |||
57 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
58 | cpu->gic_num_lrs = 4; | ||
59 | cpu->gic_vpribits = 5; | ||
60 | cpu->gic_vprebits = 5; | ||
61 | - cpu->isar.reset_pmcr_el0 = 0x41023000; | ||
62 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
63 | } | ||
64 | |||
65 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/cpu_tcg.c | ||
68 | +++ b/target/arm/cpu_tcg.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj) | ||
70 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | ||
71 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | ||
72 | cpu->reset_auxcr = 2; | ||
73 | - cpu->isar.reset_pmcr_el0 = 0x41002000; | ||
74 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); | ||
75 | } | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj) | ||
78 | cpu->clidr = (1 << 27) | (1 << 24) | 3; | ||
79 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ | ||
80 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | ||
81 | - cpu->isar.reset_pmcr_el0 = 0x41093000; | ||
82 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); | ||
83 | } | ||
84 | |||
85 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
86 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | ||
87 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | ||
88 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | ||
89 | - cpu->isar.reset_pmcr_el0 = 0x41072000; | ||
90 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | ||
91 | } | ||
92 | |||
93 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
94 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | ||
95 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | ||
96 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | ||
97 | - cpu->isar.reset_pmcr_el0 = 0x410F3000; | ||
98 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); | ||
99 | } | ||
100 | |||
101 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj) | ||
102 | cpu->isar.id_isar6 = 0x0; | ||
103 | cpu->mp_is_up = true; | ||
104 | cpu->pmsav7_dregion = 16; | ||
105 | - cpu->isar.reset_pmcr_el0 = 0x41151800; | ||
106 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); | ||
107 | } | ||
108 | |||
109 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/target/arm/helper.c | ||
112 | +++ b/target/arm/helper.c | ||
113 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
114 | #endif | 16 | #endif |
115 | 17 | ||
116 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ | 18 | typedef struct S1Translate { |
117 | +#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ | 19 | + /* |
118 | 20 | + * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk. | |
119 | #ifndef CONFIG_USER_ONLY | 21 | + * Together with in_space, specifies the architectural translation regime. |
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { | ||
122 | |||
123 | static inline uint32_t pmu_num_counters(CPUARMState *env) | ||
124 | { | ||
125 | - ARMCPU *cpu = env_archcpu(env); | ||
126 | - | ||
127 | - return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; | ||
128 | + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | ||
129 | } | ||
130 | |||
131 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | ||
132 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
133 | .resetvalue = 0, | ||
134 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | ||
135 | #endif | ||
136 | + /* The only field of MDCR_EL2 that has a defined architectural reset value | ||
137 | + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | ||
138 | + */ | 22 | + */ |
139 | + { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | 23 | ARMMMUIdx in_mmu_idx; |
140 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | 24 | + /* |
141 | + .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS, | 25 | + * in_ptw_idx: specifies which mmuidx to use for the actual |
142 | + .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | 26 | + * page table descriptor load operations. This will be one of the |
143 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, | 27 | + * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes. |
144 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | 28 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, |
145 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | 29 | + * this field is updated accordingly. |
146 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | 30 | + */ |
147 | * field as main ID register, and we implement four counters in | 31 | ARMMMUIdx in_ptw_idx; |
148 | * addition to the cycle count register. | 32 | + /* |
149 | */ | 33 | + * in_space: the security space for this walk. This plus |
150 | - unsigned int i, pmcrn = pmu_num_counters(&cpu->env); | 34 | + * the in_mmu_idx specify the architectural translation regime. |
151 | + unsigned int i, pmcrn = PMCR_NUM_COUNTERS; | 35 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, |
152 | ARMCPRegInfo pmcr = { | 36 | + * this field is updated accordingly. |
153 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | 37 | + * |
154 | .access = PL0_RW, | 38 | + * Note that the security space for the in_ptw_idx may be different |
155 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | 39 | + * from that for the in_mmu_idx. We do not need to explicitly track |
156 | .access = PL0_RW, .accessfn = pmreg_access, | 40 | + * the in_ptw_idx security space because: |
157 | .type = ARM_CP_IO, | 41 | + * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx |
158 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | 42 | + * itself specifies the security space |
159 | - .resetvalue = cpu->isar.reset_pmcr_el0, | 43 | + * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security |
160 | + .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | | 44 | + * space used for ptw reads is the same as that of the security |
161 | + PMCRLC, | 45 | + * space of the stage 1 translation for all cases except where |
162 | .writefn = pmcr_write, .raw_writefn = raw_write, | 46 | + * stage 1 is Secure; in that case the only possibilities for |
163 | }; | 47 | + * the ptw read are Secure and NonSecure, and the in_ptw_idx |
164 | - | 48 | + * value being Stage2 vs Stage2_S distinguishes those. |
165 | define_one_arm_cp_reg(cpu, &pmcr); | 49 | + */ |
166 | define_one_arm_cp_reg(cpu, &pmcr64); | 50 | ARMSecuritySpace in_space; |
167 | for (i = 0; i < pmcrn; i++) { | 51 | + /* |
168 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 52 | + * in_secure: whether the translation regime is a Secure one. |
169 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | 53 | + * This is always equal to arm_space_is_secure(in_space). |
170 | REGINFO_SENTINEL | 54 | + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, |
171 | }; | 55 | + * this field is updated accordingly. |
172 | - /* | 56 | + */ |
173 | - * The only field of MDCR_EL2 that has a defined architectural reset | 57 | bool in_secure; |
174 | - * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | 58 | + /* |
175 | - */ | 59 | + * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug |
176 | - ARMCPRegInfo mdcr_el2 = { | 60 | + * accesses will not update the guest page table access flags |
177 | - .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | 61 | + * and will not change the state of the softmmu TLBs. |
178 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | 62 | + */ |
179 | - .access = PL2_RW, .resetvalue = pmu_num_counters(env), | 63 | bool in_debug; |
180 | - .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), | 64 | /* |
181 | - }; | 65 | * If this is stage 2 of a stage 1+2 page table walk, then this must |
182 | - define_one_arm_cp_reg(cpu, &mdcr_el2); | ||
183 | define_arm_cp_regs(cpu, vpidr_regs); | ||
184 | define_arm_cp_regs(cpu, el2_cp_reginfo); | ||
185 | if (arm_feature(env, ARM_FEATURE_V8)) { | ||
186 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
187 | index XXXXXXX..XXXXXXX 100644 | ||
188 | --- a/target/arm/kvm64.c | ||
189 | +++ b/target/arm/kvm64.c | ||
190 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
191 | ARM64_SYS_REG(3, 0, 0, 7, 1)); | ||
192 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, | ||
193 | ARM64_SYS_REG(3, 0, 0, 7, 2)); | ||
194 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
195 | - ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
196 | |||
197 | /* | ||
198 | * Note that if AArch32 support is not present in the host, | ||
199 | -- | 66 | -- |
200 | 2.20.1 | 67 | 2.34.1 |
201 | |||
202 | diff view generated by jsdifflib |
1 | Provide a new function dynamic_sysbus_dev_allowed() which checks the | 1 | In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate() |
---|---|---|---|
2 | per-machine list of permitted dynamic sysbus devices and returns a | 2 | so that the debug-access "call get_phys_addr_*" codepath is used both |
3 | boolean result indicating whether the device is allowed. We can use | 3 | when S1 is doing ptw reads from stage 2 and when it is doing ptw |
4 | this in the implementation of validate_sysbus_device(), but we will | 4 | reads from physical memory. However, we didn't update the |
5 | also need it so that machine hotplug callbacks can validate devices | 5 | calculation of s2ptw->in_space and s2ptw->in_secure to account for |
6 | rather than assuming that any sysbus device might be hotpluggable | 6 | the "ptw reads from physical memory" case. This meant that debug |
7 | into the platform bus. | 7 | accesses when in Secure state broke. |
8 | 8 | ||
9 | Create a new function S2_security_space() which returns the | ||
10 | correct security space to use for the ptw load, and use it to | ||
11 | determine the correct .in_secure and .in_space fields for the | ||
12 | stage 2 lookup for the ptw load. | ||
13 | |||
14 | Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 18 | Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org |
12 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 19 | Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate") |
13 | Message-id: 20210325153310.9131-3-peter.maydell@linaro.org | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 21 | --- |
15 | include/hw/boards.h | 24 ++++++++++++++++++++++++ | 22 | target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++----- |
16 | hw/core/machine.c | 21 ++++++++++++++++----- | 23 | 1 file changed, 32 insertions(+), 5 deletions(-) |
17 | 2 files changed, 40 insertions(+), 5 deletions(-) | ||
18 | 24 | ||
19 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 25 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
20 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/boards.h | 27 | --- a/target/arm/ptw.c |
22 | +++ b/include/hw/boards.h | 28 | +++ b/target/arm/ptw.c |
23 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | 29 | @@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) |
24 | */ | 30 | } |
25 | void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type); | ||
26 | |||
27 | +/** | ||
28 | + * device_is_dynamic_sysbus: test whether device is a dynamic sysbus device | ||
29 | + * @mc: Machine class | ||
30 | + * @dev: device to check | ||
31 | + * | ||
32 | + * Returns: true if @dev is a sysbus device on the machine's list | ||
33 | + * of dynamically pluggable sysbus devices; otherwise false. | ||
34 | + * | ||
35 | + * This function checks whether @dev is a valid dynamic sysbus device, | ||
36 | + * by first confirming that it is a sysbus device and then checking it | ||
37 | + * against the list of permitted dynamic sysbus devices which has been | ||
38 | + * set up by the machine using machine_class_allow_dynamic_sysbus_dev(). | ||
39 | + * | ||
40 | + * It is valid to call this with something that is not a subclass of | ||
41 | + * TYPE_SYS_BUS_DEVICE; the function will return false in this case. | ||
42 | + * This allows hotplug callback functions to be written as: | ||
43 | + * if (device_is_dynamic_sysbus(mc, dev)) { | ||
44 | + * handle dynamic sysbus case; | ||
45 | + * } else if (some other kind of hotplug) { | ||
46 | + * handle that; | ||
47 | + * } | ||
48 | + */ | ||
49 | +bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev); | ||
50 | + | ||
51 | /* | ||
52 | * Checks that backend isn't used, preps it for exclusive usage and | ||
53 | * returns migratable MemoryRegion provided by backend. | ||
54 | diff --git a/hw/core/machine.c b/hw/core/machine.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/core/machine.c | ||
57 | +++ b/hw/core/machine.c | ||
58 | @@ -XXX,XX +XXX,XX @@ void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) | ||
59 | QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); | ||
60 | } | 31 | } |
61 | 32 | ||
62 | -static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) | 33 | +static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, |
63 | +bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) | 34 | + ARMMMUIdx s2_mmu_idx) |
64 | { | 35 | +{ |
65 | - MachineState *machine = opaque; | 36 | + /* |
66 | - MachineClass *mc = MACHINE_GET_CLASS(machine); | 37 | + * Return the security space to use for stage 2 when doing |
67 | bool allowed = false; | 38 | + * the S1 page table descriptor load. |
68 | strList *wl; | 39 | + */ |
69 | + Object *obj = OBJECT(dev); | 40 | + if (regime_is_stage2(s2_mmu_idx)) { |
70 | + | 41 | + /* |
71 | + if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { | 42 | + * The security space for ptw reads is almost always the same |
72 | + return false; | 43 | + * as that of the security space of the stage 1 translation. |
44 | + * The only exception is when stage 1 is Secure; in that case | ||
45 | + * the ptw read might be to the Secure or the NonSecure space | ||
46 | + * (but never Realm or Root), and the s2_mmu_idx tells us which. | ||
47 | + * Root translations are always single-stage. | ||
48 | + */ | ||
49 | + if (s1_space == ARMSS_Secure) { | ||
50 | + return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S); | ||
51 | + } else { | ||
52 | + assert(s2_mmu_idx != ARMMMUIdx_Stage2_S); | ||
53 | + assert(s1_space != ARMSS_Root); | ||
54 | + return s1_space; | ||
55 | + } | ||
56 | + } else { | ||
57 | + /* ptw loads are from phys: the mmu idx itself says which space */ | ||
58 | + return arm_phys_to_space(s2_mmu_idx); | ||
73 | + } | 59 | + } |
74 | |||
75 | for (wl = mc->allowed_dynamic_sysbus_devices; | ||
76 | !allowed && wl; | ||
77 | wl = wl->next) { | ||
78 | - allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value); | ||
79 | + allowed |= !!object_dynamic_cast(obj, wl->value); | ||
80 | } | ||
81 | |||
82 | - if (!allowed) { | ||
83 | + return allowed; | ||
84 | +} | 60 | +} |
85 | + | 61 | + |
86 | +static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) | 62 | /* Translate a S1 pagetable walk through S2 if needed. */ |
87 | +{ | 63 | static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
88 | + MachineState *machine = opaque; | 64 | hwaddr addr, ARMMMUFaultInfo *fi) |
89 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | 65 | { |
90 | + | 66 | - ARMSecuritySpace space = ptw->in_space; |
91 | + if (!device_is_dynamic_sysbus(mc, DEVICE(sbdev))) { | 67 | bool is_secure = ptw->in_secure; |
92 | error_report("Option '-device %s' cannot be handled by this machine", | 68 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
93 | object_class_get_name(object_get_class(OBJECT(sbdev)))); | 69 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; |
94 | exit(1); | 70 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
71 | * From gdbstub, do not use softmmu so that we don't modify the | ||
72 | * state of the cpu at all, including softmmu tlb contents. | ||
73 | */ | ||
74 | + ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx); | ||
75 | S1Translate s2ptw = { | ||
76 | .in_mmu_idx = s2_mmu_idx, | ||
77 | .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), | ||
78 | - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | ||
79 | - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure | ||
80 | - : space == ARMSS_Realm ? ARMSS_Realm | ||
81 | - : ARMSS_NonSecure), | ||
82 | + .in_secure = arm_space_is_secure(s2_space), | ||
83 | + .in_space = s2_space, | ||
84 | .in_debug = true, | ||
85 | }; | ||
86 | GetPhysAddrResult s2 = { }; | ||
95 | -- | 87 | -- |
96 | 2.20.1 | 88 | 2.34.1 |
97 | |||
98 | diff view generated by jsdifflib |
1 | The function machine_class_allow_dynamic_sysbus_dev() is currently | 1 | In get_phys_addr_twostage() the code that applies the effects of |
---|---|---|---|
2 | undocumented; add a doc comment. | 2 | VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure. |
3 | Now we also have f.attrs.space for FEAT_RME, we need to keep the two | ||
4 | in sync. | ||
5 | |||
6 | These bits only have an effect for Secure space translations, not | ||
7 | for Root, so use the input in_space field to determine whether to | ||
8 | apply them rather than the input is_secure. This doesn't actually | ||
9 | make a difference because Root translations are never two-stage, | ||
10 | but it's a little clearer. | ||
3 | 11 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 14 | Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org |
7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
8 | Message-id: 20210325153310.9131-2-peter.maydell@linaro.org | ||
9 | --- | 15 | --- |
10 | include/hw/boards.h | 15 +++++++++++++++ | 16 | target/arm/ptw.c | 13 ++++++++----- |
11 | 1 file changed, 15 insertions(+) | 17 | 1 file changed, 8 insertions(+), 5 deletions(-) |
12 | 18 | ||
13 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 19 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/boards.h | 21 | --- a/target/arm/ptw.c |
16 | +++ b/include/hw/boards.h | 22 | +++ b/target/arm/ptw.c |
17 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | 23 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, |
18 | const CpuInstanceProperties *props, | 24 | hwaddr ipa; |
19 | Error **errp); | 25 | int s1_prot, s1_lgpgsz; |
20 | 26 | bool is_secure = ptw->in_secure; | |
21 | +/** | 27 | + ARMSecuritySpace in_space = ptw->in_space; |
22 | + * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices | 28 | bool ret, ipa_secure; |
23 | + * @mc: Machine class | 29 | ARMCacheAttrs cacheattrs1; |
24 | + * @type: type to allow (should be a subtype of TYPE_SYS_BUS_DEVICE) | 30 | ARMSecuritySpace ipa_space; |
25 | + * | 31 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, |
26 | + * Add the QOM type @type to the list of devices of which are subtypes | 32 | * Check if IPA translates to secure or non-secure PA space. |
27 | + * of TYPE_SYS_BUS_DEVICE but which are still permitted to be dynamically | 33 | * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. |
28 | + * created (eg by the user on the command line with -device). | 34 | */ |
29 | + * By default if the user tries to create any devices on the command line | 35 | - result->f.attrs.secure = |
30 | + * that are subtypes of TYPE_SYS_BUS_DEVICE they will get an error message; | 36 | - (is_secure |
31 | + * for the special cases which are permitted for this machine model, the | 37 | - && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) |
32 | + * machine model class init code must call this function to add them | 38 | - && (ipa_secure |
33 | + * to the list of specifically permitted devices. | 39 | - || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); |
34 | + */ | 40 | + if (in_space == ARMSS_Secure) { |
35 | void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type); | 41 | + result->f.attrs.secure = |
36 | + | 42 | + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) |
37 | /* | 43 | + && (ipa_secure |
38 | * Checks that backend isn't used, preps it for exclusive usage and | 44 | + || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))); |
39 | * returns migratable MemoryRegion provided by backend. | 45 | + result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure); |
46 | + } | ||
47 | |||
48 | return false; | ||
49 | } | ||
40 | -- | 50 | -- |
41 | 2.20.1 | 51 | 2.34.1 |
42 | |||
43 | diff view generated by jsdifflib |
1 | The virt machine device plug callback currently calls | 1 | In commit f0a08b0913befbd we changed the type of the PC from |
---|---|---|---|
2 | platform_bus_link_device() for any sysbus device. This is overly | 2 | target_ulong to vaddr. In doing so we inadvertently dropped the |
3 | broad, because platform_bus_link_device() will unconditionally grab | 3 | zero-padding on the PC in trace lines (the second item inside the [] |
4 | the IRQs and MMIOs of the device it is passed, whether it was | 4 | in these lines). They used to look like this on AArch64, for |
5 | intended for the platform bus or not. Restrict hotpluggability of | 5 | instance: |
6 | sysbus devices to only those devices on the dynamic sysbus | ||
7 | allowlist. | ||
8 | 6 | ||
9 | We were mostly getting away with this because the board creates the | 7 | Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000] |
10 | platform bus as the last device it creates, and so the hotplug | ||
11 | callback did not do anything for all the sysbus devices created by | ||
12 | the board itself. However if the user plugged in a device which | ||
13 | itself uses a sysbus device internally we would have mishandled this | ||
14 | and probably asserted. | ||
15 | 8 | ||
9 | and now they look like this: | ||
10 | Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000] | ||
11 | |||
12 | and if the PC happens to be somewhere low like 0x5000 | ||
13 | then the field is shown as /5000/. | ||
14 | |||
15 | This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier, | ||
16 | depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64 | ||
17 | with no width specifier. | ||
18 | |||
19 | Restore the zero-padding by adding an 016 width specifier to | ||
20 | this tracing and a couple of others that were similarly recently | ||
21 | changed to use VADDR_PRIx without a width specifier. | ||
22 | |||
23 | We can't unfortunately restore the "32-bit guests are padded to | ||
24 | 8 hex digits and 64-bit guests to 16 hex digits" behaviour so | ||
25 | easily. | ||
26 | |||
27 | Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr") | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 29 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
18 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 30 | Reviewed-by: Anton Johansson <anjo@rev.ng> |
19 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 31 | Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org |
20 | Message-id: 20210325153310.9131-4-peter.maydell@linaro.org | ||
21 | --- | 32 | --- |
22 | hw/arm/virt.c | 8 ++++++-- | 33 | accel/tcg/cpu-exec.c | 4 ++-- |
23 | 1 file changed, 6 insertions(+), 2 deletions(-) | 34 | accel/tcg/translate-all.c | 2 +- |
35 | 2 files changed, 3 insertions(+), 3 deletions(-) | ||
24 | 36 | ||
25 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 37 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c |
26 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/arm/virt.c | 39 | --- a/accel/tcg/cpu-exec.c |
28 | +++ b/hw/arm/virt.c | 40 | +++ b/accel/tcg/cpu-exec.c |
29 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, | 41 | @@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, |
30 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | 42 | if (qemu_log_in_addr_range(pc)) { |
31 | 43 | qemu_log_mask(CPU_LOG_EXEC, | |
32 | if (vms->platform_bus_dev) { | 44 | "Trace %d: %p [%08" PRIx64 |
33 | - if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { | 45 | - "/%" VADDR_PRIx "/%08x/%08x] %s\n", |
34 | + MachineClass *mc = MACHINE_GET_CLASS(vms); | 46 | + "/%016" VADDR_PRIx "/%08x/%08x] %s\n", |
35 | + | 47 | cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, |
36 | + if (device_is_dynamic_sysbus(mc, dev)) { | 48 | tb->flags, tb->cflags, lookup_symbol(pc)); |
37 | platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), | 49 | |
38 | SYS_BUS_DEVICE(dev)); | 50 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) |
51 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
52 | vaddr pc = log_pc(cpu, last_tb); | ||
53 | if (qemu_log_in_addr_range(pc)) { | ||
54 | - qemu_log("Stopped execution of TB chain before %p [%" | ||
55 | + qemu_log("Stopped execution of TB chain before %p [%016" | ||
56 | VADDR_PRIx "] %s\n", | ||
57 | last_tb->tc.ptr, pc, lookup_symbol(pc)); | ||
58 | } | ||
59 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/accel/tcg/translate-all.c | ||
62 | +++ b/accel/tcg/translate-all.c | ||
63 | @@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) | ||
64 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { | ||
65 | vaddr pc = log_pc(cpu, tb); | ||
66 | if (qemu_log_in_addr_range(pc)) { | ||
67 | - qemu_log("cpu_io_recompile: rewound execution of TB to %" | ||
68 | + qemu_log("cpu_io_recompile: rewound execution of TB to %016" | ||
69 | VADDR_PRIx "\n", pc); | ||
39 | } | 70 | } |
40 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
41 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | ||
42 | DeviceState *dev) | ||
43 | { | ||
44 | - if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || | ||
45 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
46 | + | ||
47 | + if (device_is_dynamic_sysbus(mc, dev) || | ||
48 | (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { | ||
49 | return HOTPLUG_HANDLER(machine); | ||
50 | } | 71 | } |
51 | -- | 72 | -- |
52 | 2.20.1 | 73 | 2.34.1 |
53 | 74 | ||
54 | 75 | diff view generated by jsdifflib |
1 | From: "Chubb, Peter (Data61, Eveleigh)" <Peter.Chubb@data61.csiro.au> | 1 | From: Tong Ho <tong.ho@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | Remove Peter Chubb as i/MX31 maintainer. | 3 | Add a check in the bit-set operation to write the backstore |
4 | only if the affected bit is 0 before. | ||
4 | 5 | ||
5 | I'm leaving my current job and will no longer have access to the | 6 | With this in place, there will be no need for callers to |
6 | hardware to test or maintain this port. | 7 | do the checking in order to avoid unnecessary writes. |
7 | 8 | ||
8 | Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> | 9 | Signed-off-by: Tong Ho <tong.ho@amd.com> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
11 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 14 | --- |
12 | MAINTAINERS | 1 - | 15 | hw/nvram/xlnx-efuse.c | 11 +++++++++-- |
13 | 1 file changed, 1 deletion(-) | 16 | 1 file changed, 9 insertions(+), 2 deletions(-) |
14 | 17 | ||
15 | diff --git a/MAINTAINERS b/MAINTAINERS | 18 | diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c |
16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/MAINTAINERS | 20 | --- a/hw/nvram/xlnx-efuse.c |
18 | +++ b/MAINTAINERS | 21 | +++ b/hw/nvram/xlnx-efuse.c |
19 | @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx25_ccm.h | 22 | @@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) |
20 | F: include/hw/watchdog/wdt_imx2.h | 23 | |
21 | 24 | bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) | |
22 | i.MX31 (kzm) | 25 | { |
23 | -M: Peter Chubb <peter.chubb@nicta.com.au> | 26 | + uint32_t set, *row; |
24 | M: Peter Maydell <peter.maydell@linaro.org> | 27 | + |
25 | L: qemu-arm@nongnu.org | 28 | if (efuse_ro_bits_find(s, bit)) { |
26 | S: Odd Fixes | 29 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); |
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) | ||
32 | return false; | ||
33 | } | ||
34 | |||
35 | - s->fuse32[bit / 32] |= 1 << (bit % 32); | ||
36 | - efuse_bdrv_sync(s, bit); | ||
37 | + /* Avoid back-end write unless there is a real update */ | ||
38 | + row = &s->fuse32[bit / 32]; | ||
39 | + set = 1 << (bit % 32); | ||
40 | + if (!(set & *row)) { | ||
41 | + *row |= set; | ||
42 | + efuse_bdrv_sync(s, bit); | ||
43 | + } | ||
44 | return true; | ||
45 | } | ||
46 | |||
27 | -- | 47 | -- |
28 | 2.20.1 | 48 | 2.34.1 |
29 | 49 | ||
30 | 50 | diff view generated by jsdifflib |