1
The following changes since commit 7993b0f83fe5c3f8555e79781d5d098f99751a94:
1
The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
2
2
3
Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-03-29 18:45:12 +0100)
3
Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
8
8
9
for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:
9
for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
10
10
11
hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() (2021-03-30 14:05:34 +0100)
11
target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
* net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
14
target-arm queue:
15
* hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
15
* fix part of the "TCG-disabled builds are broken" issue
16
* hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
17
* target/arm: Make number of counters in PMCR follow the CPU
18
* hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
19
16
20
----------------------------------------------------------------
17
----------------------------------------------------------------
21
Doug Evans (1):
18
Philippe Mathieu-Daudé (1):
22
net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
19
target/arm/gdbstub: Only advertise M-profile features if TCG available
23
20
24
Peter Maydell (2):
21
target/arm/gdbstub.c | 5 +++--
25
target/arm: Make number of counters in PMCR follow the CPU
22
1 file changed, 3 insertions(+), 2 deletions(-)
26
hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
27
23
28
Philippe Mathieu-Daudé (1):
29
hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
30
31
Zenghui Yu (1):
32
hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
33
34
hw/arm/smmuv3-internal.h | 7 -------
35
target/arm/cpu.h | 1 +
36
hw/display/xlnx_dp.c | 9 +++++++++
37
hw/net/npcm7xx_emc.c | 4 +++-
38
hw/timer/renesas_tmr.c | 4 ++++
39
target/arm/cpu64.c | 3 +++
40
target/arm/cpu_tcg.c | 5 +++++
41
target/arm/helper.c | 29 +++++++++++++++++------------
42
target/arm/kvm64.c | 2 ++
43
tests/qtest/npcm7xx_emc-test.c | 30 +++++++++++++++++++++---------
44
10 files changed, 65 insertions(+), 29 deletions(-)
45
diff view generated by jsdifflib
1
From: Doug Evans <dje@google.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Turning REG_MCMDR_RXON is enough to start receiving packets.
3
Cortex-M profile is only emulable from TCG accelerator. Restrict
4
the GDBstub features to its availability in order to avoid a link
5
error when TCG is not enabled:
4
6
5
Signed-off-by: Doug Evans <dje@google.com>
7
Undefined symbols for architecture arm64:
6
Message-id: 20210319195044.741821-1-dje@google.com
8
"_arm_v7m_get_sp_ptr", referenced from:
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
_m_sysreg_get in target_arm_gdbstub.c.o
10
"_arm_v7m_mrs_control", referenced from:
11
_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
12
ld: symbol(s) not found for architecture arm64
13
clang: error: linker command failed with exit code 1 (use -v to see invocation)
14
15
Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
19
Message-id: 20230322142902.69511-3-philmd@linaro.org
20
[PMM: add #include since I cherry-picked this patch from the series]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
22
---
10
hw/net/npcm7xx_emc.c | 4 +++-
23
target/arm/gdbstub.c | 5 +++--
11
tests/qtest/npcm7xx_emc-test.c | 30 +++++++++++++++++++++---------
24
1 file changed, 3 insertions(+), 2 deletions(-)
12
2 files changed, 24 insertions(+), 10 deletions(-)
13
25
14
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
26
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
15
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/npcm7xx_emc.c
28
--- a/target/arm/gdbstub.c
17
+++ b/hw/net/npcm7xx_emc.c
29
+++ b/target/arm/gdbstub.c
18
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
30
@@ -XXX,XX +XXX,XX @@
19
!(value & REG_MCMDR_RXON)) {
31
#include "cpu.h"
20
emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
32
#include "exec/gdbstub.h"
33
#include "gdbstub/helpers.h"
34
+#include "sysemu/tcg.h"
35
#include "internals.h"
36
#include "cpregs.h"
37
38
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
39
2, "arm-vfp-sysregs.xml", 0);
21
}
40
}
22
- if (!(value & REG_MCMDR_RXON)) {
23
+ if (value & REG_MCMDR_RXON) {
24
+ emc->rx_active = true;
25
+ } else {
26
emc_halt_rx(emc, 0);
27
}
28
break;
29
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/tests/qtest/npcm7xx_emc-test.c
32
+++ b/tests/qtest/npcm7xx_emc-test.c
33
@@ -XXX,XX +XXX,XX @@ static void enable_tx(QTestState *qts, const EMCModule *mod,
34
mcmdr |= REG_MCMDR_TXON;
35
emc_write(qts, mod, REG_MCMDR, mcmdr);
36
}
41
}
37
-
42
- if (cpu_isar_feature(aa32_mve, cpu)) {
38
- /* Prod the device to send the packet. */
43
+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
39
- emc_write(qts, mod, REG_TSDR, 1);
44
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
40
}
45
1, "arm-m-profile-mve.xml", 0);
41
42
static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
43
@@ -XXX,XX +XXX,XX @@ static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
44
enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
45
with_irq ? REG_MIEN_ENTXINTR : 0);
46
47
+ /* Prod the device to send the packet. */
48
+ emc_write(qts, mod, REG_TSDR, 1);
49
+
50
/*
51
* It's problematic to observe the interrupt for each packet.
52
* Instead just wait until all the packets go out.
53
@@ -XXX,XX +XXX,XX @@ static void enable_rx(QTestState *qts, const EMCModule *mod,
54
mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
55
emc_write(qts, mod, REG_MCMDR, mcmdr);
56
}
46
}
57
-
47
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
58
- /* Prod the device to accept a packet. */
48
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
59
- emc_write(qts, mod, REG_RSDR, 1);
49
"system-registers.xml", 0);
60
}
50
61
51
- if (arm_feature(env, ARM_FEATURE_M)) {
62
static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
52
+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
63
- bool with_irq)
53
gdb_register_coprocessor(cs,
64
+ bool with_irq, bool pump_rsdr)
54
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
65
{
55
arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
66
NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
67
uint32_t desc_addr = DESC_ADDR;
68
@@ -XXX,XX +XXX,XX @@ static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
69
enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
70
with_irq ? REG_MIEN_ENRXINTR : 0, 0);
71
72
+ /*
73
+ * If requested, prod the device to accept a packet.
74
+ * This isn't necessary, the linux driver doesn't do this.
75
+ * Test doing/not-doing this for robustness.
76
+ */
77
+ if (pump_rsdr) {
78
+ emc_write(qts, mod, REG_RSDR, 1);
79
+ }
80
+
81
/* Send test packet to device's socket. */
82
ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
83
g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
84
@@ -XXX,XX +XXX,XX @@ static void test_rx(gconstpointer test_data)
85
86
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
87
88
- emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
89
- emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
90
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
91
+ /*pump_rsdr=*/false);
92
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
93
+ /*pump_rsdr=*/true);
94
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
95
+ /*pump_rsdr=*/false);
96
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
97
+ /*pump_rsdr=*/true);
98
emc_test_ptle(qts, td->module, test_sockets[0]);
99
100
qtest_quit(qts);
101
--
56
--
102
2.20.1
57
2.34.1
103
58
104
59
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
When building with --enable-sanitizers we get:
4
5
Direct leak of 16 byte(s) in 1 object(s) allocated from:
6
#0 0x5618479ec7cf in malloc (qemu-system-aarch64+0x233b7cf)
7
#1 0x7f675745f958 in g_malloc (/lib64/libglib-2.0.so.0+0x58958)
8
#2 0x561847c2dcc9 in xlnx_dp_init hw/display/xlnx_dp.c:1259:5
9
#3 0x56184a5bdab8 in object_init_with_type qom/object.c:375:9
10
#4 0x56184a5a2bda in object_initialize_with_type qom/object.c:517:5
11
#5 0x56184a5a24d5 in object_initialize qom/object.c:536:5
12
#6 0x56184a5a2f6c in object_initialize_child_with_propsv qom/object.c:566:5
13
#7 0x56184a5a2e60 in object_initialize_child_with_props qom/object.c:549:10
14
#8 0x56184a5a3a1e in object_initialize_child_internal qom/object.c:603:5
15
#9 0x5618495aa431 in xlnx_zynqmp_init hw/arm/xlnx-zynqmp.c:273:5
16
17
The RX/TX FIFOs are created in xlnx_dp_init(), add xlnx_dp_finalize()
18
to destroy them.
19
20
Fixes: 58ac482a66d ("introduce xlnx-dp")
21
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Message-id: 20210323182958.277654-1-f4bug@amsat.org
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/display/xlnx_dp.c | 9 +++++++++
27
1 file changed, 9 insertions(+)
28
29
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/display/xlnx_dp.c
32
+++ b/hw/display/xlnx_dp.c
33
@@ -XXX,XX +XXX,XX @@ static void xlnx_dp_init(Object *obj)
34
fifo8_create(&s->tx_fifo, 16);
35
}
36
37
+static void xlnx_dp_finalize(Object *obj)
38
+{
39
+ XlnxDPState *s = XLNX_DP(obj);
40
+
41
+ fifo8_destroy(&s->tx_fifo);
42
+ fifo8_destroy(&s->rx_fifo);
43
+}
44
+
45
static void xlnx_dp_realize(DeviceState *dev, Error **errp)
46
{
47
XlnxDPState *s = XLNX_DP(dev);
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo xlnx_dp_info = {
49
.parent = TYPE_SYS_BUS_DEVICE,
50
.instance_size = sizeof(XlnxDPState),
51
.instance_init = xlnx_dp_init,
52
+ .instance_finalize = xlnx_dp_finalize,
53
.class_init = xlnx_dp_class_init,
54
};
55
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
Deleted patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
1
3
They were introduced in commit 9bde7f0674fe ("hw/arm/smmuv3: Implement
4
translate callback") but never actually used. Drop them.
5
6
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
7
Acked-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20210325142702.790-1-yuzenghui@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/smmuv3-internal.h | 7 -------
13
1 file changed, 7 deletions(-)
14
15
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/smmuv3-internal.h
18
+++ b/hw/arm/smmuv3-internal.h
19
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
20
#define CD_A(x) extract32((x)->word[1], 14, 1)
21
#define CD_AARCH64(x) extract32((x)->word[1], 9 , 1)
22
23
-#define CDM_VALID(x) ((x)->word[0] & 0x1)
24
-
25
-static inline int is_cd_valid(SMMUv3State *s, STE *ste, CD *cd)
26
-{
27
- return CD_VALID(cd);
28
-}
29
-
30
/**
31
* tg2granule - Decodes the CD translation granule size field according
32
* to the ttbr in use
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
Deleted patch
1
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
2
means that we don't provide the 6 counters that are required by the
3
Arm BSA (Base System Architecture) specification if the CPU supports
4
the Virtualization extensions.
5
1
6
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
7
specify the PMCR reset value (obtained from the appropriate TRM), and
8
use the 'N' field of that value to define the number of counters
9
provided.
10
11
This means that we now supply 6 counters for Cortex-A53, A57, A72,
12
A15 and A9 as well as '-cpu max'; Cortex-A7 and A8 stay at 4; and
13
Cortex-R5 goes down to 3.
14
15
Note that because we now use the PMCR reset value of the specific
16
implementation, we no longer set the LC bit out of reset. This has
17
an UNKNOWN value out of reset for all cores with any AArch32 support,
18
so guest software should be setting it anyway if it wants it.
19
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
22
Message-id: 20210311165947.27470-1-peter.maydell@linaro.org
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
---
25
target/arm/cpu.h | 1 +
26
target/arm/cpu64.c | 3 +++
27
target/arm/cpu_tcg.c | 5 +++++
28
target/arm/helper.c | 29 +++++++++++++++++------------
29
target/arm/kvm64.c | 2 ++
30
5 files changed, 28 insertions(+), 12 deletions(-)
31
32
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/cpu.h
35
+++ b/target/arm/cpu.h
36
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
37
uint64_t id_aa64mmfr2;
38
uint64_t id_aa64dfr0;
39
uint64_t id_aa64dfr1;
40
+ uint64_t reset_pmcr_el0;
41
} isar;
42
uint64_t midr;
43
uint32_t revidr;
44
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu64.c
47
+++ b/target/arm/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
49
cpu->gic_num_lrs = 4;
50
cpu->gic_vpribits = 5;
51
cpu->gic_vprebits = 5;
52
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
53
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
54
}
55
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
57
cpu->gic_num_lrs = 4;
58
cpu->gic_vpribits = 5;
59
cpu->gic_vprebits = 5;
60
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
61
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
62
}
63
64
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
65
cpu->gic_num_lrs = 4;
66
cpu->gic_vpribits = 5;
67
cpu->gic_vprebits = 5;
68
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
69
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
70
}
71
72
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/cpu_tcg.c
75
+++ b/target/arm/cpu_tcg.c
76
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
77
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
78
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
79
cpu->reset_auxcr = 2;
80
+ cpu->isar.reset_pmcr_el0 = 0x41002000;
81
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
82
}
83
84
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
85
cpu->clidr = (1 << 27) | (1 << 24) | 3;
86
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
87
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
88
+ cpu->isar.reset_pmcr_el0 = 0x41093000;
89
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
90
}
91
92
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
93
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
94
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
95
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
96
+ cpu->isar.reset_pmcr_el0 = 0x41072000;
97
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
98
}
99
100
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
101
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
102
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
103
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
104
+ cpu->isar.reset_pmcr_el0 = 0x410F3000;
105
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
106
}
107
108
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
109
cpu->isar.id_isar6 = 0x0;
110
cpu->mp_is_up = true;
111
cpu->pmsav7_dregion = 16;
112
+ cpu->isar.reset_pmcr_el0 = 0x41151800;
113
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
114
}
115
116
diff --git a/target/arm/helper.c b/target/arm/helper.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/helper.c
119
+++ b/target/arm/helper.c
120
@@ -XXX,XX +XXX,XX @@
121
#endif
122
123
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
124
-#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
125
126
#ifndef CONFIG_USER_ONLY
127
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
129
130
static inline uint32_t pmu_num_counters(CPUARMState *env)
131
{
132
- return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
133
+ ARMCPU *cpu = env_archcpu(env);
134
+
135
+ return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
136
}
137
138
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
139
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
140
.resetvalue = 0,
141
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
142
#endif
143
- /* The only field of MDCR_EL2 that has a defined architectural reset value
144
- * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
145
- */
146
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
147
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
148
- .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
149
- .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
150
{ .name = "HPFAR", .state = ARM_CP_STATE_AA32,
151
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
152
.access = PL2_RW, .accessfn = access_el3_aa32ns,
153
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
154
* field as main ID register, and we implement four counters in
155
* addition to the cycle count register.
156
*/
157
- unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
158
+ unsigned int i, pmcrn = pmu_num_counters(&cpu->env);
159
ARMCPRegInfo pmcr = {
160
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
161
.access = PL0_RW,
162
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
163
.access = PL0_RW, .accessfn = pmreg_access,
164
.type = ARM_CP_IO,
165
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
166
- .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
167
- PMCRLC,
168
+ .resetvalue = cpu->isar.reset_pmcr_el0,
169
.writefn = pmcr_write, .raw_writefn = raw_write,
170
};
171
+
172
define_one_arm_cp_reg(cpu, &pmcr);
173
define_one_arm_cp_reg(cpu, &pmcr64);
174
for (i = 0; i < pmcrn; i++) {
175
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
176
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
177
REGINFO_SENTINEL
178
};
179
+ /*
180
+ * The only field of MDCR_EL2 that has a defined architectural reset
181
+ * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
182
+ */
183
+ ARMCPRegInfo mdcr_el2 = {
184
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
185
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
186
+ .access = PL2_RW, .resetvalue = pmu_num_counters(env),
187
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
188
+ };
189
+ define_one_arm_cp_reg(cpu, &mdcr_el2);
190
define_arm_cp_regs(cpu, vpidr_regs);
191
define_arm_cp_regs(cpu, el2_cp_reginfo);
192
if (arm_feature(env, ARM_FEATURE_V8)) {
193
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
194
index XXXXXXX..XXXXXXX 100644
195
--- a/target/arm/kvm64.c
196
+++ b/target/arm/kvm64.c
197
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
198
ARM64_SYS_REG(3, 0, 0, 7, 1));
199
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
200
ARM64_SYS_REG(3, 0, 0, 7, 2));
201
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
202
+ ARM64_SYS_REG(3, 3, 9, 12, 0));
203
204
/*
205
* Note that if AArch32 support is not present in the host,
206
--
207
2.20.1
208
209
diff view generated by jsdifflib
Deleted patch
1
In commit 81b3ddaf8772ec we fixed a use of uninitialized data
2
in read_tcnt(). However this change wasn't enough to placate
3
Coverity, which is not smart enough to see that if we read a
4
2 bit field and then handle cases 0, 1, 2 and 3 then there cannot
5
be a flow of execution through the switch default. Add explicit
6
default cases which assert that they can't be reached, which
7
should help silence Coverity.
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20210319162458.13760-1-peter.maydell@linaro.org
12
---
13
hw/timer/renesas_tmr.c | 4 ++++
14
1 file changed, 4 insertions(+)
15
16
diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/renesas_tmr.c
19
+++ b/hw/timer/renesas_tmr.c
20
@@ -XXX,XX +XXX,XX @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size, int ch)
21
case CSS_CASCADING:
22
tcnt[1] = tmr->tcnt[1];
23
break;
24
+ default:
25
+ g_assert_not_reached();
26
}
27
switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) {
28
case CSS_INTERNAL:
29
@@ -XXX,XX +XXX,XX @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size, int ch)
30
case CSS_EXTERNAL: /* QEMU doesn't implement this */
31
tcnt[0] = tmr->tcnt[0];
32
break;
33
+ default:
34
+ g_assert_not_reached();
35
}
36
} else {
37
tcnt[0] = tmr->tcnt[0];
38
--
39
2.20.1
40
41
diff view generated by jsdifflib