target-arm queue: two bug fixes, plus the KVM/SVE patchset,

which is a new feature but one which was in my pre-softfreeze

pullreq (it just had to be dropped due to an unexpected test failure.)

The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:

Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1

for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:

target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)

* Support SVE in KVM guests

* Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'

* Update hflags after boot.c modifies CPU state

Andrew Jones (9):

target/arm/monitor: Introduce qmp_query_cpu_model_expansion

tests: arm: Introduce cpu feature tests

target/arm: Allow SVE to be disabled via a CPU property

target/arm/cpu64: max cpu: Introduce sve<N> properties

target/arm/kvm64: Add kvm_arch_get/put_sve

target/arm/kvm64: max cpu: Enable SVE when available

target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features

target/arm/cpu64: max cpu: Support sve properties with KVM

target/arm/kvm: host cpu: Add support for sve<N> properties

Christophe Lyon (1):

target/arm: Allow reading flags from FPSCR for M-profile

Edgar E. Iglesias (1):

hw/arm/boot: Rebuild hflags when modifying CPUState at boot

tests/Makefile.include | 5 +-

qapi/machine-target.json | 6 +-

include/qemu/bitops.h | 1 +

target/arm/cpu.h | 21 ++

target/arm/kvm_arm.h | 39 +++

hw/arm/boot.c | 1 +

target/arm/cpu.c | 25 +-

target/arm/cpu64.c | 364 +++++++++++++++++++++++++--

target/arm/helper.c | 10 +-

target/arm/kvm.c | 25 +-

target/arm/kvm32.c | 6 +-

target/arm/kvm64.c | 325 +++++++++++++++++++++---

target/arm/monitor.c | 158 ++++++++++++

target/arm/translate-vfp.inc.c | 5 +-

tests/arm-cpu-features.c | 551 +++++++++++++++++++++++++++++++++++++++++

docs/arm-cpu-features.rst | 317 ++++++++++++++++++++++++

16 files changed, 1795 insertions(+), 64 deletions(-)

create mode 100644 tests/arm-cpu-features.c

create mode 100644 docs/arm-cpu-features.rst

From: Andrew Jones <drjones@redhat.com>

Add support for the query-cpu-model-expansion QMP command to Arm. We

do this selectively, only exposing CPU properties which represent

optional CPU features which the user may want to enable/disable.

Additionally we restrict the list of queryable cpu models to 'max',

'host', or the current type when KVM is in use. And, finally, we only

implement expansion type 'full', as Arm does not yet have a "base"

CPU type. More details and example queries are described in a new

document (docs/arm-cpu-features.rst).

Note, certainly more features may be added to the list of advertised

features, e.g. 'vfp' and 'neon'. The only requirement is that we can

detect invalid configurations and emit failures at QMP query time.

For 'vfp' and 'neon' this will require some refactoring to share a

validation function between the QMP query and the CPU realize

functions.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Beata Michalska <beata.michalska@linaro.org>

Message-id: 20191031142734.8590-2-drjones@redhat.com

qapi/machine-target.json | 6 +-

target/arm/monitor.c | 146 ++++++++++++++++++++++++++++++++++++++

docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++

3 files changed, 286 insertions(+), 3 deletions(-)

create mode 100644 docs/arm-cpu-features.rst

diff --git a/qapi/machine-target.json b/qapi/machine-target.json

--- a/qapi/machine-target.json

+++ b/qapi/machine-target.json

@@ -XXX,XX +XXX,XX @@

##

{ 'struct': 'CpuModelExpansionInfo',

'data': { 'model': 'CpuModelInfo' },

- 'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }

+ 'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }

##

# @query-cpu-model-expansion:

@@ -XXX,XX +XXX,XX @@

# query-cpu-model-expansion while using these is not advised.

#

# Some architectures may not support all expansion types. s390x supports

-# "full" and "static".

+# "full" and "static". Arm only supports "full".

#

# Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is

# not supported, if the model cannot be expanded, if the model contains

@@ -XXX,XX +XXX,XX @@

'data': { 'type': 'CpuModelExpansionType',

'model': 'CpuModelInfo' },

'returns': 'CpuModelExpansionInfo',

- 'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }

+ 'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }

##

# @CpuDefinitionInfo:

diff --git a/target/arm/monitor.c b/target/arm/monitor.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/monitor.c

+++ b/target/arm/monitor.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

+#include "hw/boards.h"

#include "kvm_arm.h"

+#include "qapi/error.h"

+#include "qapi/visitor.h"

+#include "qapi/qobject-input-visitor.h"

+#include "qapi/qapi-commands-machine-target.h"

#include "qapi/qapi-commands-misc-target.h"

+#include "qapi/qmp/qerror.h"

+#include "qapi/qmp/qdict.h"

+#include "qom/qom-qobject.h"

static GICCapability *gic_cap_new(int version)

{

@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)

return head;

}

+

+/*

+ * These are cpu model features we want to advertise. The order here

+ * matters as this is the order in which qmp_query_cpu_model_expansion

+ * will attempt to set them. If there are dependencies between features,

+ * then the order that considers those dependencies must be used.

+ */

+static const char *cpu_model_advertised_features[] = {

+ "aarch64", "pmu",

+ NULL

+};

+

+CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,

+ CpuModelInfo *model,

+ Error **errp)

+{

+ CpuModelExpansionInfo *expansion_info;

+ const QDict *qdict_in = NULL;

+ QDict *qdict_out;

+ ObjectClass *oc;

+ Object *obj;

+ const char *name;

+ int i;

+

+ if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {

+ error_setg(errp, "The requested expansion type is not supported");

+ return NULL;

+ }

+

+ if (!kvm_enabled() && !strcmp(model->name, "host")) {

+ error_setg(errp, "The CPU type '%s' requires KVM", model->name);

+ return NULL;

+ }

+

+ oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);

+ if (!oc) {

+ error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",

+ model->name);

+ return NULL;

+ }

+

+ if (kvm_enabled()) {

+ const char *cpu_type = current_machine->cpu_type;

+ int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);

+ bool supported = false;

+

+ if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {

+ /* These are kvmarm's recommended cpu types */

+ supported = true;

+ } else if (strlen(model->name) == len &&

+ !strncmp(model->name, cpu_type, len)) {

+ /* KVM is enabled and we're using this type, so it works. */

+ supported = true;

+ }

+ if (!supported) {

+ error_setg(errp, "We cannot guarantee the CPU type '%s' works "

+ "with KVM on this host", model->name);

+ return NULL;

+ }

+ }

+

+ if (model->props) {

+ qdict_in = qobject_to(QDict, model->props);

+ if (!qdict_in) {

+ error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");

+ return NULL;

+ }

+ }

+

+ obj = object_new(object_class_get_name(oc));

+

+ if (qdict_in) {

+ Visitor *visitor;

+ Error *err = NULL;

+

+ visitor = qobject_input_visitor_new(model->props);

+ visit_start_struct(visitor, NULL, NULL, 0, &err);

+ if (err) {

+ visit_free(visitor);

+ object_unref(obj);

+ error_propagate(errp, err);

+ return NULL;

+ }

+

+ i = 0;

+ while ((name = cpu_model_advertised_features[i++]) != NULL) {

+ if (qdict_get(qdict_in, name)) {

+ object_property_set(obj, visitor, name, &err);

+ if (err) {

+ break;

+ }

+ }

+ }

+

+ if (!err) {

+ visit_check_struct(visitor, &err);

+ }

+ visit_end_struct(visitor, NULL);

+ visit_free(visitor);

+ if (err) {

+ object_unref(obj);

+ error_propagate(errp, err);

+ return NULL;

+ }

+ }

+

+ expansion_info = g_new0(CpuModelExpansionInfo, 1);

+ expansion_info->model = g_malloc0(sizeof(*expansion_info->model));

+ expansion_info->model->name = g_strdup(model->name);

+

+ qdict_out = qdict_new();

+

+ i = 0;

+ while ((name = cpu_model_advertised_features[i++]) != NULL) {

+ ObjectProperty *prop = object_property_find(obj, name, NULL);

+ if (prop) {

+ Error *err = NULL;

+ QObject *value;

+

+ assert(prop->get);

+ value = object_property_get_qobject(obj, name, &err);

+ assert(!err);

+

+ qdict_put_obj(qdict_out, name, value);

+ }

+ }

+

+ if (!qdict_size(qdict_out)) {

+ qobject_unref(qdict_out);

+ } else {

+ expansion_info->model->props = QOBJECT(qdict_out);

+ expansion_info->model->has_props = true;

+ }

+

+ object_unref(obj);

+

+ return expansion_info;

+}

diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/arm-cpu-features.rst

@@ -XXX,XX +XXX,XX @@

+================

+ARM CPU Features

+================

+

+Examples of probing and using ARM CPU features

+

+Introduction

+============

+

+CPU features are optional features that a CPU of supporting type may

+choose to implement or not. In QEMU, optional CPU features have

+corresponding boolean CPU proprieties that, when enabled, indicate

+that the feature is implemented, and, conversely, when disabled,

+indicate that it is not implemented. An example of an ARM CPU feature

+is the Performance Monitoring Unit (PMU). CPU types such as the

+Cortex-A15 and the Cortex-A57, which respectively implement ARM

+architecture reference manuals ARMv7-A and ARMv8-A, may both optionally

+implement PMUs. For example, if a user wants to use a Cortex-A15 without

+a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU

+command line, i.e. `-cpu cortex-a15,pmu=off`.

+

+As not all CPU types support all optional CPU features, then whether or

+not a CPU property exists depends on the CPU type. For example, CPUs

+that implement the ARMv8-A architecture reference manual may optionally

+support the AArch32 CPU feature, which may be enabled by disabling the

+`aarch64` CPU property. A CPU type such as the Cortex-A15, which does

+not implement ARMv8-A, will not have the `aarch64` CPU property.

+

+QEMU's support may be limited for some CPU features, only partially

+supporting the feature or only supporting the feature under certain

+configurations. For example, the `aarch64` CPU feature, which, when

+disabled, enables the optional AArch32 CPU feature, is only supported

+when using the KVM accelerator and when running on a host CPU type that

+supports the feature.

+

+CPU Feature Probing

+===================

+

+Determining which CPU features are available and functional for a given

+CPU type is possible with the `query-cpu-model-expansion` QMP command.

+Below are some examples where `scripts/qmp/qmp-shell` (see the top comment

+block in the script for usage) is used to issue the QMP commands.

+

+(1) Determine which CPU features are available for the `max` CPU type

+ (Note, we started QEMU with qemu-system-aarch64, so `max` is

+ implementing the ARMv8-A reference manual in this case)::

+

+ (QEMU) query-cpu-model-expansion type=full model={"name":"max"}

+ { "return": {

+ "model": { "name": "max", "props": {

+ "pmu": true, "aarch64": true

+ }}}}

+

+We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.

+We also see that the CPU features are enabled, as they are all `true`.

+

+(2) Let's try to disable the PMU::

+

+ (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}

+ { "return": {

+ "model": { "name": "max", "props": {

+ "pmu": false, "aarch64": true

+ }}}}

+

+We see it worked, as `pmu` is now `false`.

+

+(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::

+

+ (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}

+ {"error": {

+ "class": "GenericError", "desc":

+ "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"

+ }}

+

+It looks like this feature is limited to a configuration we do not

+currently have.

+

+(4) Let's try probing CPU features for the Cortex-A15 CPU type::

+

+ (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}

+ {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}

+

+Only the `pmu` CPU feature is available.

+

+A note about CPU feature dependencies

+-------------------------------------

+

+It's possible for features to have dependencies on other features. I.e.

+it may be possible to change one feature at a time without error, but

+when attempting to change all features at once an error could occur

+depending on the order they are processed. It's also possible changing

+all at once doesn't generate an error, because a feature's dependencies

+are satisfied with other features, but the same feature cannot be changed

+independently without error. For these reasons callers should always

+attempt to make their desired changes all at once in order to ensure the

+collection is valid.

+

+A note about CPU models and KVM

+-------------------------------

+

+Named CPU models generally do not work with KVM. There are a few cases

+that do work, e.g. using the named CPU model `cortex-a57` with KVM on a

+seattle host, but mostly if KVM is enabled the `host` CPU type must be

+used. This means the guest is provided all the same CPU features as the

+host CPU type has. And, for this reason, the `host` CPU type should

+enable all CPU features that the host has by default. Indeed it's even

+a bit strange to allow disabling CPU features that the host has when using

+the `host` CPU type, but in the absence of CPU models it's the best we can

+do if we want to launch guests without all the host's CPU features enabled.

+

+Enabling KVM also affects the `query-cpu-model-expansion` QMP command. The

+affect is not only limited to specific features, as pointed out in example

+(3) of "CPU Feature Probing", but also to which CPU types may be expanded.

+When KVM is enabled, only the `max`, `host`, and current CPU type may be

+expanded. This restriction is necessary as it's not possible to know all

+CPU types that may work with KVM, but it does impose a small risk of users

+experiencing unexpected errors. For example on a seattle, as mentioned

+above, the `cortex-a57` CPU type is also valid when KVM is enabled.

+Therefore a user could use the `host` CPU type for the current type, but

+then attempt to query `cortex-a57`, however that query will fail with our

+restrictions. This shouldn't be an issue though as management layers and

+users have been preferring the `host` CPU type for use with KVM for quite

+some time. Additionally, if the KVM-enabled QEMU instance running on a

+seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`

+will work.

+

+Using CPU Features

+==================

+

+After determining which CPU features are available and supported for a

+given CPU type, then they may be selectively enabled or disabled on the

+QEMU command line with that CPU type::

+

+ $ qemu-system-aarch64 -M virt -cpu max,pmu=off

+

+The example above disables the PMU for the `max` CPU type.

+

From: Andrew Jones <drjones@redhat.com>

Now that Arm CPUs have advertised features lets add tests to ensure

we maintain their expected availability with and without KVM.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Message-id: 20191031142734.8590-3-drjones@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

tests/Makefile.include | 5 +-

tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++

2 files changed, 257 insertions(+), 1 deletion(-)

create mode 100644 tests/arm-cpu-features.c

diff --git a/tests/Makefile.include b/tests/Makefile.include

index XXXXXXX..XXXXXXX 100644

--- a/tests/Makefile.include

+++ b/tests/Makefile.include

@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)

check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)

check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)

+check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)

check-qtest-arm-y += tests/microbit-test$(EXESUF)

check-qtest-arm-y += tests/m25p80-test$(EXESUF)

check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)

@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)

check-qtest-arm-y += tests/hexloader-test$(EXESUF)

check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)

-check-qtest-aarch64-y = tests/numa-test$(EXESUF)

+check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)

+check-qtest-aarch64-y += tests/numa-test$(EXESUF)

check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)

check-qtest-aarch64-y += tests/migration-test$(EXESUF)

# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional

@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)

tests/numa-test$(EXESUF): tests/numa-test.o

tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o

tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)

+tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o

tests/migration/stress$(EXESUF): tests/migration/stress.o

    $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")

diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/tests/arm-cpu-features.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Arm CPU feature test cases

+ *

+ * Copyright (c) 2019 Red Hat Inc.

+ * Authors:

+ * Andrew Jones <drjones@redhat.com>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+#include "qemu/osdep.h"

+#include "libqtest.h"

+#include "qapi/qmp/qdict.h"

+#include "qapi/qmp/qjson.h"

+

+#define MACHINE "-machine virt,gic-version=max,accel=tcg "

+#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "

+#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \

+ " 'arguments': { 'type': 'full', "

+#define QUERY_TAIL "}}"

+

+static bool kvm_enabled(QTestState *qts)

+{

+ QDict *resp, *qdict;

+ bool enabled;

+

+ resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");

+ g_assert(qdict_haskey(resp, "return"));

+ qdict = qdict_get_qdict(resp, "return");

+ g_assert(qdict_haskey(qdict, "enabled"));

+ enabled = qdict_get_bool(qdict, "enabled");

+ qobject_unref(resp);

+

+ return enabled;

+}

+

+static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)

+{

+ return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"

+ QUERY_TAIL, cpu_type);

+}

+

+static QDict *do_query(QTestState *qts, const char *cpu_type,

+ const char *fmt, ...)

+{

+ QDict *resp;

+

+ if (fmt) {

+ QDict *args;

+ va_list ap;

+

+ va_start(ap, fmt);

+ args = qdict_from_vjsonf_nofail(fmt, ap);

+ va_end(ap);

+

+ resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "

+ "'props': %p }"

+ QUERY_TAIL, cpu_type, args);

+ } else {

+ resp = do_query_no_props(qts, cpu_type);

+ }

+

+ return resp;

+}

+

+static const char *resp_get_error(QDict *resp)

+{

+ QDict *qdict;

+

+ g_assert(resp);

+

+ qdict = qdict_get_qdict(resp, "error");

+ if (qdict) {

+ return qdict_get_str(qdict, "desc");

+ }

+

+ return NULL;

+}

+

+#define assert_error(qts, cpu_type, expected_error, fmt, ...) \

+({ \

+ QDict *_resp; \

+ const char *_error; \

+ \

+ _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__); \

+ g_assert(_resp); \

+ _error = resp_get_error(_resp); \

+ g_assert(_error); \

+ g_assert(g_str_equal(_error, expected_error)); \

+ qobject_unref(_resp); \

+})

+

+static bool resp_has_props(QDict *resp)

+{

+ QDict *qdict;

+

+ g_assert(resp);

+

+ if (!qdict_haskey(resp, "return")) {

+ return false;

+ }

+ qdict = qdict_get_qdict(resp, "return");

+

+ if (!qdict_haskey(qdict, "model")) {

+ return false;

+ }

+ qdict = qdict_get_qdict(qdict, "model");

+

+ return qdict_haskey(qdict, "props");

+}

+

+static QDict *resp_get_props(QDict *resp)

+{

+ QDict *qdict;

+

+ g_assert(resp);

+ g_assert(resp_has_props(resp));

+

+ qdict = qdict_get_qdict(resp, "return");

+ qdict = qdict_get_qdict(qdict, "model");

+ qdict = qdict_get_qdict(qdict, "props");

+

+ return qdict;

+}

+

+#define assert_has_feature(qts, cpu_type, feature) \

+({ \

+ QDict *_resp = do_query_no_props(qts, cpu_type); \

+ g_assert(_resp); \

+ g_assert(resp_has_props(_resp)); \

+ g_assert(qdict_get(resp_get_props(_resp), feature)); \

+ qobject_unref(_resp); \

+})

+

+#define assert_has_not_feature(qts, cpu_type, feature) \

+({ \

+ QDict *_resp = do_query_no_props(qts, cpu_type); \

+ g_assert(_resp); \

+ g_assert(!resp_has_props(_resp) || \

+ !qdict_get(resp_get_props(_resp), feature)); \

+ qobject_unref(_resp); \

+})

+

+static void assert_type_full(QTestState *qts)

+{

+ const char *error;

+ QDict *resp;

+

+ resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "

+ "'arguments': { 'type': 'static', "

+ "'model': { 'name': 'foo' }}}");

+ g_assert(resp);

+ error = resp_get_error(resp);

+ g_assert(error);

+ g_assert(g_str_equal(error,

+ "The requested expansion type is not supported"));

+ qobject_unref(resp);

+}

+

+static void assert_bad_props(QTestState *qts, const char *cpu_type)

+{

+ const char *error;

+ QDict *resp;

+

+ resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "

+ "'arguments': { 'type': 'full', "

+ "'model': { 'name': %s, "

+ "'props': false }}}",

+ cpu_type);

+ g_assert(resp);

+ error = resp_get_error(resp);

+ g_assert(error);

+ g_assert(g_str_equal(error,

+ "Invalid parameter type for 'props', expected: dict"));

+ qobject_unref(resp);

+}

+

+static void test_query_cpu_model_expansion(const void *data)

+{

+ QTestState *qts;

+

+ qts = qtest_init(MACHINE "-cpu max");

+

+ /* Test common query-cpu-model-expansion input validation */

+ assert_type_full(qts);

+ assert_bad_props(qts, "max");

+ assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "

+ "ARM CPU type", NULL);

+ assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",

+ "{ 'not-a-prop': false }");

+ assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);

+

+ /* Test expected feature presence/absence for some cpu types */

+ assert_has_feature(qts, "max", "pmu");

+ assert_has_feature(qts, "cortex-a15", "pmu");

+ assert_has_not_feature(qts, "cortex-a15", "aarch64");

+

+ if (g_str_equal(qtest_get_arch(), "aarch64")) {

+ assert_has_feature(qts, "max", "aarch64");

+ assert_has_feature(qts, "cortex-a57", "pmu");

+ assert_has_feature(qts, "cortex-a57", "aarch64");

+

+ /* Test that features that depend on KVM generate errors without. */

+ assert_error(qts, "max",

+ "'aarch64' feature cannot be disabled "

+ "unless KVM is enabled and 32-bit EL1 "

+ "is supported",

+ "{ 'aarch64': false }");

+ }

+

+ qtest_quit(qts);

+}

+

+static void test_query_cpu_model_expansion_kvm(const void *data)

+{

+ QTestState *qts;

+

+ qts = qtest_init(MACHINE_KVM "-cpu max");

+

+ /*

+ * These tests target the 'host' CPU type, so KVM must be enabled.

+ */

+ if (!kvm_enabled(qts)) {

+ qtest_quit(qts);

+ return;

+ }

+

+ if (g_str_equal(qtest_get_arch(), "aarch64")) {

+ assert_has_feature(qts, "host", "aarch64");

+ assert_has_feature(qts, "host", "pmu");

+

+ assert_error(qts, "cortex-a15",

+ "We cannot guarantee the CPU type 'cortex-a15' works "

+ "with KVM on this host", NULL);

+ } else {

+ assert_has_not_feature(qts, "host", "aarch64");

+ assert_has_not_feature(qts, "host", "pmu");

+ }

+

+ qtest_quit(qts);

+}

+

+int main(int argc, char **argv)

+{

+ g_test_init(&argc, &argv, NULL);

+

+ qtest_add_data_func("/arm/query-cpu-model-expansion",

+ NULL, test_query_cpu_model_expansion);

+ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",

+ NULL, test_query_cpu_model_expansion_kvm);

+

+ return g_test_run();

+}

--

2.20.1

From: Andrew Jones <drjones@redhat.com>

Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via

a CPU property") we can disable the 'max' cpu model's VFP and neon

features, but there's no way to disable SVE. Add the 'sve=on|off'

property to give it that flexibility. We also rename

cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them

to follow the typical *_get/set_<property-name> pattern.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Reviewed-by: Beata Michalska <beata.michalska@linaro.org>

Message-id: 20191031142734.8590-4-drjones@redhat.com

target/arm/cpu.c | 3 ++-

target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++------

target/arm/monitor.c | 2 +-

tests/arm-cpu-features.c | 1 +

4 files changed, 49 insertions(+), 9 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);

env->cp15.cptr_el[3] |= CPTR_EZ;

/* with maximum vector length */

- env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;

+ env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?

+ cpu->sve_max_vq - 1 : 0;

env->vfp.zcr_el[2] = env->vfp.zcr_el[1];

env->vfp.zcr_el[3] = env->vfp.zcr_el[1];

/*

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)

define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);

}

-static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,

- void *opaque, Error **errp)

+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

{

ARMCPU *cpu = ARM_CPU(obj);

- visit_type_uint32(v, name, &cpu->sve_max_vq, errp);

+ uint32_t value;

+

+ /* All vector lengths are disabled when SVE is off. */

+ if (!cpu_isar_feature(aa64_sve, cpu)) {

+ value = 0;

+ } else {

+ value = cpu->sve_max_vq;

+ }

+ visit_type_uint32(v, name, &value, errp);

}

-static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,

- void *opaque, Error **errp)

+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

{

ARMCPU *cpu = ARM_CPU(obj);

Error *err = NULL;

@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,

error_propagate(errp, err);

}

+static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ bool value = cpu_isar_feature(aa64_sve, cpu);

+

+ visit_type_bool(v, name, &value, errp);

+}

+

+static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ Error *err = NULL;

+ bool value;

+ uint64_t t;

+

+ visit_type_bool(v, name, &value, &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+

+ t = cpu->isar.id_aa64pfr0;

+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);

+ cpu->isar.id_aa64pfr0 = t;

+}

+

/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);

* otherwise, a CPU with as many features enabled as our emulation supports.

* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

#endif

cpu->sve_max_vq = ARM_MAX_VQ;

- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,

- cpu_max_set_sve_vq, NULL, NULL, &error_fatal);

+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,

+ cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);

+ object_property_add(obj, "sve", "bool", cpu_arm_get_sve,

+ cpu_arm_set_sve, NULL, NULL, &error_fatal);

}

}

diff --git a/target/arm/monitor.c b/target/arm/monitor.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/monitor.c

+++ b/target/arm/monitor.c

@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)

* then the order that considers those dependencies must be used.

*/

static const char *cpu_model_advertised_features[] = {

- "aarch64", "pmu",

+ "aarch64", "pmu", "sve",

NULL

};

diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c

index XXXXXXX..XXXXXXX 100644

--- a/tests/arm-cpu-features.c

+++ b/tests/arm-cpu-features.c

@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)

if (g_str_equal(qtest_get_arch(), "aarch64")) {

assert_has_feature(qts, "max", "aarch64");

+ assert_has_feature(qts, "max", "sve");

assert_has_feature(qts, "cortex-a57", "pmu");

assert_has_feature(qts, "cortex-a57", "aarch64");

From: Andrew Jones <drjones@redhat.com>

Introduce cpu properties to give fine control over SVE vector lengths.

We introduce a property for each valid length up to the current

maximum supported, which is 2048-bits. The properties are named, e.g.

sve128, sve256, sve384, sve512, ..., where the number is the number of

bits. See the updates to docs/arm-cpu-features.rst for a description

of the semantics and for example uses.

Note, as sve-max-vq is still present and we'd like to be able to

support qmp_query_cpu_model_expansion with guests launched with e.g.

-cpu max,sve-max-vq=8 on their command lines, then we do allow

sve-max-vq and sve<N> properties to be provided at the same time, but

this is not recommended, and is why sve-max-vq is not mentioned in the

document. If sve-max-vq is provided then it enables all lengths smaller

than and including the max and disables all lengths larger. It also has

the side-effect that no larger lengths may be enabled and that the max

itself cannot be disabled. Smaller non-power-of-two lengths may,

however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a

guest the vector lengths 128, 256, and 512 bits.

This patch has been co-authored with Richard Henderson, who reworked

the target/arm/cpu64.c changes in order to push all the validation and

auto-enabling/disabling steps into the finalizer, resulting in a nice

LOC reduction.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Reviewed-by: Beata Michalska <beata.michalska@linaro.org>

Message-id: 20191031142734.8590-5-drjones@redhat.com

include/qemu/bitops.h | 1 +

target/arm/cpu.h | 19 ++++

target/arm/cpu.c | 19 ++++

target/arm/cpu64.c | 192 ++++++++++++++++++++++++++++++++++++-

target/arm/helper.c | 10 +-

target/arm/monitor.c | 12 +++

tests/arm-cpu-features.c | 194 ++++++++++++++++++++++++++++++++++++++

docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--

8 files changed, 606 insertions(+), 9 deletions(-)

diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h

--- a/include/qemu/bitops.h

+++ b/include/qemu/bitops.h

@@ -XXX,XX +XXX,XX @@

#define BITS_PER_LONG (sizeof (unsigned long) * BITS_PER_BYTE)

#define BIT(nr) (1UL << (nr))

+#define BIT_ULL(nr) (1ULL << (nr))

#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))

#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)

#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct {

#ifdef TARGET_AARCH64

# define ARM_MAX_VQ 16

+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);

+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);

#else

# define ARM_MAX_VQ 1

+static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }

+static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)

+{ return 0; }

#endif

typedef struct ARMVectorReg {

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

/* Used to set the maximum vector length the cpu will support. */

uint32_t sve_max_vq;

+

+ /*

+ * In sve_vq_map each set bit is a supported vector length of

+ * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector

+ * length in quadwords.

+ *

+ * While processing properties during initialization, corresponding

+ * sve_vq_init bits are set for bits in sve_vq_map that have been

+ * set by properties.

+ */

+ DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);

+ DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);

void arm_cpu_post_init(Object *obj);

@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)

return (env->features & (1ULL << feature)) != 0;

}

+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);

+

#if !defined(CONFIG_USER_ONLY)

/* Return true if exception levels below EL3 are in secure state,

* or would be following an exception return to that level.

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)

#endif

}

+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)

+{

+ Error *local_err = NULL;

+

+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

+ arm_cpu_sve_finalize(cpu, &local_err);

+ if (local_err != NULL) {

+ error_propagate(errp, local_err);

+ return;

+ }

+ }

+}

+

static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

{

CPUState *cs = CPU(dev);

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

return;

}

+ arm_cpu_finalize_features(cpu, &local_err);

+ if (local_err != NULL) {

+ error_propagate(errp, local_err);

+ return;

+ }

+

if (arm_feature(env, ARM_FEATURE_AARCH64) &&

cpu->has_vfp != cpu->has_neon) {

/*

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)

define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);

}

+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)

+{

+ /*

+ * If any vector lengths are explicitly enabled with sve<N> properties,

+ * then all other lengths are implicitly disabled. If sve-max-vq is

+ * specified then it is the same as explicitly enabling all lengths

+ * up to and including the specified maximum, which means all larger

+ * lengths will be implicitly disabled. If no sve<N> properties

+ * are enabled and sve-max-vq is not specified, then all lengths not

+ * explicitly disabled will be enabled. Additionally, all power-of-two

+ * vector lengths less than the maximum enabled length will be

+ * automatically enabled and all vector lengths larger than the largest

+ * disabled power-of-two vector length will be automatically disabled.

+ * Errors are generated if the user provided input that interferes with

+ * any of the above. Finally, if SVE is not disabled, then at least one

+ * vector length must be enabled.

+ */

+ DECLARE_BITMAP(tmp, ARM_MAX_VQ);

+ uint32_t vq, max_vq = 0;

+

+ /*

+ * Process explicit sve<N> properties.

+ * From the properties, sve_vq_map<N> implies sve_vq_init<N>.

+ * Check first for any sve<N> enabled.

+ */

+ if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {

+ max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;

+

+ if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {

+ error_setg(errp, "cannot enable sve%d", max_vq * 128);

+ error_append_hint(errp, "sve%d is larger than the maximum vector "

+ "length, sve-max-vq=%d (%d bits)\n",

+ max_vq * 128, cpu->sve_max_vq,

+ cpu->sve_max_vq * 128);

+ return;

+ }

+

+ /* Propagate enabled bits down through required powers-of-two. */

+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {

+ if (!test_bit(vq - 1, cpu->sve_vq_init)) {

+ set_bit(vq - 1, cpu->sve_vq_map);

+ }

+ }

+ } else if (cpu->sve_max_vq == 0) {

+ /*

+ * No explicit bits enabled, and no implicit bits from sve-max-vq.

+ */

+ if (!cpu_isar_feature(aa64_sve, cpu)) {

+ /* SVE is disabled and so are all vector lengths. Good. */

+ return;

+ }

+

+ /* Disabling a power-of-two disables all larger lengths. */

+ if (test_bit(0, cpu->sve_vq_init)) {

+ error_setg(errp, "cannot disable sve128");

+ error_append_hint(errp, "Disabling sve128 results in all vector "

+ "lengths being disabled.\n");

+ error_append_hint(errp, "With SVE enabled, at least one vector "

+ "length must be enabled.\n");

+ return;

+ }

+ for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {

+ if (test_bit(vq - 1, cpu->sve_vq_init)) {

+ break;

+ }

+ }

+ max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;

+

+ bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);

+ max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;

+ }

+

+ /*

+ * Process the sve-max-vq property.

+ * Note that we know from the above that no bit above

+ * sve-max-vq is currently set.

+ */

+ if (cpu->sve_max_vq != 0) {

+ max_vq = cpu->sve_max_vq;

+

+ if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&

+ test_bit(max_vq - 1, cpu->sve_vq_init)) {

+ error_setg(errp, "cannot disable sve%d", max_vq * 128);

+ error_append_hint(errp, "The maximum vector length must be "

+ "enabled, sve-max-vq=%d (%d bits)\n",

+ max_vq, max_vq * 128);

+ return;

+ }

+

+ /* Set all bits not explicitly set within sve-max-vq. */

+ bitmap_complement(tmp, cpu->sve_vq_init, max_vq);

+ bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);

+ }

+

+ /*

+ * We should know what max-vq is now. Also, as we're done

+ * manipulating sve-vq-map, we ensure any bits above max-vq

+ * are clear, just in case anybody looks.

+ */

+ assert(max_vq != 0);

+ bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);

+

+ /* Ensure all required powers-of-two are enabled. */

+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {

+ if (!test_bit(vq - 1, cpu->sve_vq_map)) {

+ error_setg(errp, "cannot disable sve%d", vq * 128);

+ error_append_hint(errp, "sve%d is required as it "

+ "is a power-of-two length smaller than "

+ "the maximum, sve%d\n",

+ vq * 128, max_vq * 128);

+ return;

+ }

+ }

+

+ /*

+ * Now that we validated all our vector lengths, the only question

+ * left to answer is if we even want SVE at all.

+ */

+ if (!cpu_isar_feature(aa64_sve, cpu)) {

+ error_setg(errp, "cannot enable sve%d", max_vq * 128);

+ error_append_hint(errp, "SVE must be enabled to enable vector "

+ "lengths.\n");

+ error_append_hint(errp, "Add sve=on to the CPU property list.\n");

+ return;

+ }

+

+ /* From now on sve_max_vq is the actual maximum supported length. */

+ cpu->sve_max_vq = max_vq;

+}

+

+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)

+{

+ uint32_t bitnum;

+

+ /*

+ * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want

+ * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this

+ * function always returns the next smaller than the input.

+ */

+ assert(vq && vq <= ARM_MAX_VQ + 1);

+

+ bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);

+ return bitnum == vq - 1 ? 0 : bitnum + 1;

+}

+

static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,

void *opaque, Error **errp)

{

@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,

error_propagate(errp, err);

}

+static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ uint32_t vq = atoi(&name[3]) / 128;

+ bool value;

+

+ /* All vector lengths are disabled when SVE is off. */

+ if (!cpu_isar_feature(aa64_sve, cpu)) {

+ value = false;

+ } else {

+ value = test_bit(vq - 1, cpu->sve_vq_map);

+ }

+ visit_type_bool(v, name, &value, errp);

+}

+

+static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ uint32_t vq = atoi(&name[3]) / 128;

+ Error *err = NULL;

+ bool value;

+

+ visit_type_bool(v, name, &value, &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+

+ if (value) {

+ set_bit(vq - 1, cpu->sve_vq_map);

+ } else {

+ clear_bit(vq - 1, cpu->sve_vq_map);

+ }

+ set_bit(vq - 1, cpu->sve_vq_init);

+}

+

static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,

void *opaque, Error **errp)

{

@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,

static void aarch64_max_initfn(Object *obj)

{

ARMCPU *cpu = ARM_CPU(obj);

+ uint32_t vq;

if (kvm_enabled()) {

kvm_arm_set_cpu_features_from_host(cpu);

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

cpu->dcz_blocksize = 7; /* 512 bytes */

#endif

- cpu->sve_max_vq = ARM_MAX_VQ;

object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,

cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);

object_property_add(obj, "sve", "bool", cpu_arm_get_sve,

cpu_arm_set_sve, NULL, NULL, &error_fatal);

+

+ for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {

+ char name[8];

+ sprintf(name, "sve%d", vq * 128);

+ object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,

+ cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);

+ }

}

}

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)

return 0;

}

+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)

+{

+ uint32_t start_vq = (start_len & 0xf) + 1;

+

+ return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;

+}

+

/*

* Given that SVE is enabled, return the vector length for EL.

*/

@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)

if (arm_feature(env, ARM_FEATURE_EL3)) {

zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);

}