[PULL 00/16] riscv-to-apply queue
[PULL 00/59] riscv-to-apply queue
1
The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
1
The following changes since commit 661c2e1ab29cd9c4d268ae3f44712e8d421c0e56:
2
2
3
Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
3
scripts/checkpatch: Fix a typo (2025-03-04 09:30:26 +0800)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
7
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250305-1
8
8
9
for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
9
for you to fetch changes up to 4db19d5b21e058e6eb3474b6be470d1184afaa9e:
10
10
11
target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
11
target/riscv/kvm: add missing KVM CSRs (2025-03-04 15:42:54 +1000)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
RISC-V PR for 6.0
14
Third RISC-V PR for 10.0
15
15
16
This PR includes:
16
* CSR coverity fixes
17
- Fix for vector CSR access
17
* Fix unexpected behavior of vector reduction instructions when vl is 0
18
- Improvements to the Ibex UART device
18
* Fix incorrect vlen comparison in prop_vlen_set
19
- PMP improvements and bug fixes
19
* Throw debug exception before page fault
20
- Hypervisor extension bug fixes
20
* Remove redundant "hart_idx" masking from APLIC
21
- ramfb support for the virt machine
21
* Add support for Control Transfer Records Ext
22
- Fast read support for SST flash
22
* Remove redundant struct members from the IOMMU
23
- Improvements to the microchip_pfsoc machine
23
* Remove duplicate definitions from the IOMMU
24
* Fix tick_offset migration for Goldfish RTC
25
* Add serial alias in virt machine DTB
26
* Remove Bin Meng from RISC-V maintainers
27
* Add support for Control Transfer Records Ext
28
* Log guest errors when reserved bits are set in PTEs
29
* Add missing Sdtrig disas CSRs
30
* Correct the hpmevent sscofpmf mask
31
* Mask upper sscofpmf bits during validation
32
* Remove warnings about Smdbltrp/Smrnmi being disabled
33
* Respect mseccfg.RLB bit for TOR mode PMP entry
34
* Update KVM support to Linux 6.14-rc3
35
* IOMMU HPM support
36
* Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM
37
* Add --ignore-family option to binfmt
38
* Refinement for AIA with KVM acceleration
39
* Reset time changes for KVM
24
40
25
----------------------------------------------------------------
41
----------------------------------------------------------------
26
Alexander Wagner (1):
42
Alistair Francis (1):
27
hw/char: disable ibex uart receive if the buffer is full
43
MAINTAINERS: Remove Bin Meng from RISC-V maintainers
28
44
29
Asherah Connor (2):
45
Andrea Bolognani (3):
30
hw/riscv: Add fw_cfg support to virt
46
binfmt: Shuffle things around
31
hw/riscv: allow ramfb on virt
47
binfmt: Normalize host CPU architecture
48
binfmt: Add --ignore-family option
32
49
33
Bin Meng (3):
50
Atish Patra (2):
34
hw/block: m25p80: Support fast read for SST flashes
51
target/riscv: Fix the hpmevent mask
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
52
target/riscv: Mask out upper sscofpmf bits during validation
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
37
53
38
Frank Chang (1):
54
Clément Léger (1):
39
target/riscv: fix vs() to return proper error code
55
target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled
40
56
41
Georg Kotheimer (6):
57
Daniel Henrique Barboza (22):
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
58
target/riscv/csr.c: fix deadcode in rmw_xireg()
43
target/riscv: Make VSTIP and VSEIP read-only in hip
59
target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg()
44
target/riscv: Use background registers also for MSTATUS_MPV
60
target/riscv/csr.c: fix deadcode in rmw_xiregi()
45
target/riscv: Fix read and write accesses to vsip and vsie
61
target/riscv/csr.c: fix deadcode in aia_smode32()
46
target/riscv: Add proper two-stage lookup exception detection
62
target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt()
47
target/riscv: Prevent lost illegal instruction exceptions
63
target/riscv/debug.c: use wp size = 4 for 32-bit CPUs
64
target/riscv: throw debug exception before page fault
65
target/riscv: add ssu64xl
66
target/riscv: use RVB in RVA22U64
67
target/riscv: add profile u_parent and s_parent
68
target/riscv: change priv_ver check in validate_profile()
69
target/riscv: add RVA23U64 profile
70
target/riscv: add RVA23S64 profile
71
linux-headers: Update to Linux v6.14-rc3
72
target/riscv/cpu.c: create flag for ziccrse
73
target/riscv/kvm: add extensions after 6.14-rc3 update
74
hw/riscv/riscv-iommu.h: add missing headers
75
hw/riscv: add IOMMU HPM trace events
76
docs/specs/riscv-iommu.rst: add HPM support info
77
target/riscv/cpu: remove unneeded !kvm_enabled() check
78
target/riscv/kvm: add kvm_riscv_reset_regs_csr()
79
target/riscv/kvm: add missing KVM CSRs
48
80
49
Jim Shu (3):
81
Huang Borong (1):
50
target/riscv: propagate PMP permission to TLB page
82
hw/intc/riscv_aplic: Remove redundant "hart_idx" masking
51
target/riscv: add log of PMP permission checking
52
target/riscv: flush TLB pages if PMP permission has been changed
53
83
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
84
Jason Chien (2):
55
docs/system/target-riscv.rst | 1 +
85
hw/riscv/riscv-iommu: Remove redundant struct members
56
include/hw/char/ibex_uart.h | 4 +
86
hw/riscv/riscv-iommu-bits: Remove duplicate definitions
57
include/hw/riscv/microchip_pfsoc.h | 1 +
58
include/hw/riscv/virt.h | 2 +
59
target/riscv/cpu.h | 4 +
60
target/riscv/pmp.h | 4 +-
61
hw/block/m25p80.c | 3 +
62
hw/char/ibex_uart.c | 23 +++-
63
hw/riscv/microchip_pfsoc.c | 6 +
64
hw/riscv/virt.c | 33 ++++++
65
target/riscv/cpu.c | 1 +
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
67
target/riscv/csr.c | 77 +++++++------
68
target/riscv/pmp.c | 84 ++++++++++----
69
target/riscv/translate.c | 179 +----------------------------
70
hw/riscv/Kconfig | 1 +
71
17 files changed, 367 insertions(+), 289 deletions(-)
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
73
87
88
Max Chou (2):
89
target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0
90
target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set
91
92
Quan Zhou (1):
93
target/riscv/kvm: Add some exts support
94
95
Rajnesh Kanwal (7):
96
target/riscv: Remove obsolete sfence.vm instruction
97
target/riscv: Add Control Transfer Records CSR definitions.
98
target/riscv: Add support for Control Transfer Records extension CSRs.
99
target/riscv: Add support to record CTR entries.
100
target/riscv: Add CTR sctrclr instruction.
101
target/riscv: machine: Add Control Transfer Record state description
102
target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
103
104
Rob Bradford (3):
105
disas/riscv: Fix minor whitespace issues
106
disas/riscv: Add missing Sdtrig CSRs
107
target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry
108
109
Rodrigo Dias Correa (1):
110
goldfish_rtc: Fix tick_offset migration
111
112
Tomasz Jeznach (8):
113
hw/riscv/riscv-iommu-bits.h: HPM bits
114
hw/riscv/riscv-iommu: add riscv-iommu-hpm file
115
hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()
116
hw/riscv/riscv-iommu: instantiate hpm_timer
117
hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes
118
hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write
119
hw/riscv/riscv-iommu: add hpm events mmio write
120
hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap
121
122
Vasilis Liaskovitis (1):
123
hw/riscv/virt: Add serial alias in DTB
124
125
Yong-Xuan Wang (3):
126
hw/intc/imsic: refine the IMSIC realize
127
hw/intc/aplic: refine the APLIC realize
128
hw/intc/aplic: refine kvm_msicfgaddr
129
130
julia (1):
131
target/riscv: log guest errors when reserved bits are set in PTEs
132
133
MAINTAINERS | 5 +-
134
docs/specs/riscv-iommu.rst | 2 +
135
hw/riscv/riscv-iommu-bits.h | 69 +++-
136
hw/riscv/riscv-iommu-hpm.h | 33 ++
137
hw/riscv/riscv-iommu.h | 32 +-
138
include/standard-headers/linux/ethtool.h | 4 +
139
include/standard-headers/linux/fuse.h | 76 +++-
140
include/standard-headers/linux/input-event-codes.h | 1 +
141
include/standard-headers/linux/pci_regs.h | 16 +-
142
include/standard-headers/linux/virtio_pci.h | 14 +
143
linux-headers/asm-arm64/kvm.h | 3 -
144
linux-headers/asm-loongarch/kvm_para.h | 1 +
145
linux-headers/asm-riscv/kvm.h | 7 +-
146
linux-headers/asm-x86/kvm.h | 1 +
147
linux-headers/linux/iommufd.h | 35 +-
148
linux-headers/linux/kvm.h | 8 +-
149
linux-headers/linux/stddef.h | 13 +-
150
linux-headers/linux/vduse.h | 2 +-
151
target/riscv/cpu-qom.h | 2 +
152
target/riscv/cpu.h | 16 +-
153
target/riscv/cpu_bits.h | 150 +++++++-
154
target/riscv/cpu_cfg.h | 5 +
155
target/riscv/helper.h | 2 +
156
target/riscv/insn32.decode | 2 +-
157
disas/riscv.c | 16 +-
158
hw/intc/riscv_aplic.c | 74 ++--
159
hw/intc/riscv_imsic.c | 47 +--
160
hw/riscv/riscv-iommu-hpm.c | 381 +++++++++++++++++++++
161
hw/riscv/riscv-iommu.c | 131 ++++++-
162
hw/riscv/virt.c | 3 +
163
hw/rtc/goldfish_rtc.c | 43 +--
164
target/riscv/cpu.c | 115 ++++++-
165
target/riscv/cpu_helper.c | 315 ++++++++++++++++-
166
target/riscv/csr.c | 318 +++++++++++++++--
167
target/riscv/debug.c | 6 +-
168
target/riscv/kvm/kvm-cpu.c | 40 ++-
169
target/riscv/machine.c | 25 ++
170
target/riscv/op_helper.c | 48 +++
171
target/riscv/pmp.c | 2 +-
172
target/riscv/pmu.c | 2 +-
173
target/riscv/tcg/tcg-cpu.c | 58 +++-
174
target/riscv/translate.c | 46 +++
175
target/riscv/vector_helper.c | 8 +-
176
target/riscv/insn_trans/trans_privileged.c.inc | 18 +-
177
target/riscv/insn_trans/trans_rvi.c.inc | 75 ++++
178
target/riscv/insn_trans/trans_rvzce.c.inc | 21 ++
179
hw/riscv/meson.build | 3 +-
180
hw/riscv/trace-events | 5 +
181
scripts/qemu-binfmt-conf.sh | 78 +++--
182
tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 400 bytes
183
50 files changed, 2106 insertions(+), 271 deletions(-)
184
create mode 100644 hw/riscv/riscv-iommu-hpm.h
185
create mode 100644 hw/riscv/riscv-iommu-hpm.c
186
diff view generated by jsdifflib
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
[PULL 01/59] target/riscv/csr.c: fix deadcode in rmw_xireg()
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
3
Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
4
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
5
6
done:
7
if (ret) {
8
return (env->virt_enabled && virt) ?
9
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
10
}
11
return RISCV_EXCP_NONE;
12
13
This happens because the 'virt' flag, which is only used by 'done', is
14
set to 'false' and it will always remain 'false' in any condition where
15
we'll jump to 'done':
16
17
switch (csrno) {
18
(...)
19
case CSR_VSIREG:
20
isel = env->vsiselect;
21
virt = true;
22
break;
23
default:
24
goto done;
25
};
26
27
'virt = true' will never reach 'done' because we have a if/else-if/else
28
block right before the label that will always return:
29
30
if (xiselect_aia_range(isel)) {
31
return ...
32
} else if (...) {
33
return ...
34
} else {
35
return RISCV_EXCP_ILLEGAL_INST;
36
}
37
38
All this means that we can preserve the current logic by reducing the
39
'done' label to:
40
41
done:
42
if (ret) {
43
return RISCV_EXCP_ILLEGAL_INST;
44
}
45
return RISCV_EXCP_NONE;
46
47
The flag 'virt' is now unused. Remove it.
48
49
Fix the 'goto done' identation while we're at it.
50
51
Resolves: Coverity CID 1590359
52
Fixes: dc0280723d ("target/riscv: Decouple AIA processing from xiselect and xireg")
53
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
54
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
55
Message-ID: <20250121184847.2109128-2-dbarboza@ventanamicro.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
56
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
57
---
8
target/riscv/csr.c | 7 ++++---
58
target/riscv/csr.c | 7 ++-----
9
1 file changed, 4 insertions(+), 3 deletions(-)
59
1 file changed, 2 insertions(+), 5 deletions(-)
10
60
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
61
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
12
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/csr.c
63
--- a/target/riscv/csr.c
14
+++ b/target/riscv/csr.c
64
+++ b/target/riscv/csr.c
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
65
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
66
target_ulong *val, target_ulong new_val,
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
67
target_ulong wr_mask)
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
23
24
static const char valid_vm_1_10_32[16] = {
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
26
target_ulong new_value, target_ulong write_mask)
27
{
68
{
28
int ret = rmw_mip(env, 0, ret_value, new_value,
69
- bool virt = false;
29
- write_mask & hip_writable_mask);
70
int ret = -EINVAL;
30
+ write_mask & hvip_writable_mask);
71
target_ulong isel;
31
72
32
- *ret_value &= hip_writable_mask;
73
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
33
+ *ret_value &= hvip_writable_mask;
74
break;
34
75
case CSR_VSIREG:
35
return ret;
76
isel = env->vsiselect;
77
- virt = true;
78
break;
79
default:
80
- goto done;
81
+ goto done;
82
};
83
84
/*
85
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
86
87
done:
88
if (ret) {
89
- return (env->virt_enabled && virt) ?
90
- RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
91
+ return RISCV_EXCP_ILLEGAL_INST;
92
}
93
return RISCV_EXCP_NONE;
36
}
94
}
37
--
95
--
38
2.30.1
96
2.48.1
39
40
diff view generated by jsdifflib
New patch
[PULL 02/59] target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Coverity found a second DEADCODE issue in rmw_xireg() claiming that we can't
4
reach 'RISCV_EXCP_NONE' at the 'done' label:
5
6
> 2706 done:
7
> 2707 if (ret) {
8
> 2708 return (env->virt_enabled && virt) ?
9
> 2709 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
10
> 2710 }
11
>>>> CID 1590356: Control flow issues (DEADCODE)
12
>>>> Execution cannot reach this statement: "return RISCV_EXCP_NONE;".
13
> 2711 return RISCV_EXCP_NONE;
14
15
Our label is now reduced after fixing another deadcode in the previous
16
patch but the problem reported here still remains:
17
18
done:
19
if (ret) {
20
return RISCV_EXCP_ILLEGAL_INST;
21
}
22
return RISCV_EXCP_NONE;
23
24
This happens because 'ret' changes only once at the start of the
25
function:
26
27
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
28
if (ret != RISCV_EXCP_NONE) {
29
return ret;
30
}
31
32
So it's a guarantee that ret will be RISCV_EXCP_NONE (-1) if we ever
33
reach the label, i.e. "if (ret)" will always be true, and the label can
34
be even further reduced to:
35
36
done:
37
return RISCV_EXCP_ILLEGAL_INST;
38
39
To make a better use of the label, remove the 'else' from the
40
xiselect_aia_range() chain and let it fall-through to the 'done' label
41
since they are now both returning RISCV_EXCP_ILLEGAL_INST.
42
43
Resolves: Coverity CID 1590356
44
Fixes: dc0280723d ("target/riscv: Decouple AIA processing from xiselect and xireg")
45
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Message-ID: <20250121184847.2109128-3-dbarboza@ventanamicro.com>
48
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
49
---
50
target/riscv/csr.c | 7 +------
51
1 file changed, 1 insertion(+), 6 deletions(-)
52
53
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/csr.c
56
+++ b/target/riscv/csr.c
57
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
58
} else if (riscv_cpu_cfg(env)->ext_smcsrind ||
59
riscv_cpu_cfg(env)->ext_sscsrind) {
60
return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
61
- } else {
62
- return RISCV_EXCP_ILLEGAL_INST;
63
}
64
65
done:
66
- if (ret) {
67
- return RISCV_EXCP_ILLEGAL_INST;
68
- }
69
- return RISCV_EXCP_NONE;
70
+ return RISCV_EXCP_ILLEGAL_INST;
71
}
72
73
static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
74
--
75
2.48.1
diff view generated by jsdifflib
New patch
[PULL 03/59] target/riscv/csr.c: fix deadcode in rmw_xiregi()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Coverity found a DEADCODE issue in rmw_xiregi() claiming that we can't
4
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
5
6
> 2652 done:
7
>>>> CID 1590357: Control flow issues (DEADCODE)
8
>>>> Execution cannot reach the expression "RISCV_EXCP_VIRT_INSTRUCTION_FAULT"
9
inside this statement: "return (env->virt_enabled &...".
10
> 2653 return (env->virt_enabled && virt) ?
11
> 2654 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
12
13
This happens because 'virt' is being set to 'false' and it will remain
14
as 'false' in any code path where 'done' will be called. The label can
15
be safely reduced to:
16
17
done:
18
return RISCV_EXCP_ILLEGAL_INST;
19
20
And that will leave us with the following usage of a 'goto' skipping a
21
single 'return' to do another single 'return':
22
23
} else {
24
goto done;
25
}
26
27
return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
28
29
done:
30
return RISCV_EXCP_ILLEGAL_INST;
31
32
Which we will eliminate it and just do 'return RISCV_EXCP_ILLEGAL_INST'
33
instead.
34
35
Resolves: Coverity CID 1590357
36
Fixes: 5e33a20827 ("target/riscv: Support generic CSR indirect access")
37
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
38
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
39
Message-ID: <20250121184847.2109128-4-dbarboza@ventanamicro.com>
40
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
41
---
42
target/riscv/csr.c | 8 +-------
43
1 file changed, 1 insertion(+), 7 deletions(-)
44
45
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/riscv/csr.c
48
+++ b/target/riscv/csr.c
49
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
50
static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
51
target_ulong new_val, target_ulong wr_mask)
52
{
53
- bool virt = false;
54
int ret = -EINVAL;
55
target_ulong isel;
56
57
@@ -XXX,XX +XXX,XX @@ static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
58
} else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 &&
59
csrno != CSR_VSIREG4 - 1) {
60
isel = env->vsiselect;
61
- virt = true;
62
} else {
63
- goto done;
64
+ return RISCV_EXCP_ILLEGAL_INST;
65
}
66
67
return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
68
-
69
-done:
70
- return (env->virt_enabled && virt) ?
71
- RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
72
}
73
74
static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
75
--
76
2.48.1
diff view generated by jsdifflib
[PULL 01/16] target/riscv: fix vs() to return proper error code
[PULL 04/59] target/riscv/csr.c: fix deadcode in aia_smode32()
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
3
Coverity reported a DEADCODE ticket in this function, as follows:
4
is not enabled.
5
4
6
If -1 is returned, exception will be raised and cs->exception_index will
5
>>>> CID 1590358: Control flow issues (DEADCODE)
7
be set to the negative return value. The exception will then be treated
6
>>>> Execution cannot reach this statement: "return ret;".
8
as an instruction access fault instead of illegal instruction fault.
7
> 380 return ret;
8
> 381 }
9
9
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
10
The cause is that the 'if (ret != RISCV_EXCP_NONE)' conditional is
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
duplicated:
12
13
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
14
if (ret != RISCV_EXCP_NONE) {
15
return ret;
16
}
17
18
if (ret != RISCV_EXCP_NONE) {
19
return ret;
20
}
21
22
Remove the duplication to fix the deadcode.
23
24
Resolves: Coverity CID 1590358
25
Fixes: dbcb6e1ccf ("target/riscv: Enable S*stateen bits for AIA")
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
28
Message-ID: <20250121184847.2109128-5-dbarboza@ventanamicro.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
30
---
16
target/riscv/csr.c | 2 +-
31
target/riscv/csr.c | 4 ----
17
1 file changed, 1 insertion(+), 1 deletion(-)
32
1 file changed, 4 deletions(-)
18
33
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
34
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
36
--- a/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
37
+++ b/target/riscv/csr.c
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
38
@@ -XXX,XX +XXX,XX @@ static RISCVException aia_smode32(CPURISCVState *env, int csrno)
24
if (env->misa & RVV) {
39
return ret;
25
return 0;
26
}
40
}
27
- return -1;
41
28
+ return -RISCV_EXCP_ILLEGAL_INST;
42
- if (ret != RISCV_EXCP_NONE) {
43
- return ret;
44
- }
45
-
46
return smode32(env, csrno);
29
}
47
}
30
48
31
static int ctr(CPURISCVState *env, int csrno)
32
--
49
--
33
2.30.1
50
2.48.1
34
35
diff view generated by jsdifflib
New patch
[PULL 05/59] target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Coverity reported a BAD_SHIFT issue in the following code:
4
5
> 2097
6
>>>> CID 1590355: Integer handling issues (BAD_SHIFT)
7
>>>> In expression "hdeleg >> cause", right shifting by more than 63
8
bits has undefined behavior. The shift amount, "cause", is at least 64.
9
> 2098 vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected);
10
> 2099 /*
11
12
It is not clear to me how the tool guarantees that '"cause" is at least
13
64', but indeed there's no guarantees that it would be < 64 in the
14
'async = true' code path.
15
16
A simple fix to avoid a potential UB is to add a 'cause < 64' guard like
17
'mode' is already doing right before 'vsmode_exc'.
18
19
Resolves: Coverity CID 1590355
20
Fixes: 967760f62c ("target/riscv: Implement Ssdbltrp exception handling")
21
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
22
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Message-ID: <20250121184847.2109128-6-dbarboza@ventanamicro.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
26
target/riscv/cpu_helper.c | 4 +++-
27
1 file changed, 3 insertions(+), 1 deletion(-)
28
29
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu_helper.c
32
+++ b/target/riscv/cpu_helper.c
33
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
34
mode = env->priv <= PRV_S && cause < 64 &&
35
(((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M;
36
37
- vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected);
38
+ vsmode_exc = env->virt_enabled && cause < 64 &&
39
+ (((hdeleg >> cause) & 1) || vs_injected);
40
+
41
/*
42
* Check double trap condition only if already in S-mode and targeting
43
* S-mode
44
--
45
2.48.1
diff view generated by jsdifflib
New patch
[PULL 06/59] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0
1
From: Max Chou <max.chou@sifive.com>
1
2
3
According to the Vector Reduction Operations section in the RISC-V "V"
4
Vector Extension spec,
5
"If vl=0, no operation is performed and the destination register is not
6
updated."
7
8
The vd should be updated when vl is larger than 0.
9
10
Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction instructions")
11
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
12
Signed-off-by: Max Chou <max.chou@sifive.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-ID: <20250124101452.2519171-1-max.chou@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/vector_helper.c | 8 ++++++--
18
1 file changed, 6 insertions(+), 2 deletions(-)
19
20
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/vector_helper.c
23
+++ b/target/riscv/vector_helper.c
24
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
25
} \
26
s1 = OP(s1, (TD)s2); \
27
} \
28
- *((TD *)vd + HD(0)) = s1; \
29
+ if (vl > 0) { \
30
+ *((TD *)vd + HD(0)) = s1; \
31
+ } \
32
env->vstart = 0; \
33
/* set tail elements to 1s */ \
34
vext_set_elems_1s(vd, vta, esz, vlenb); \
35
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
36
} \
37
s1 = OP(s1, (TD)s2, &env->fp_status); \
38
} \
39
- *((TD *)vd + HD(0)) = s1; \
40
+ if (vl > 0) { \
41
+ *((TD *)vd + HD(0)) = s1; \
42
+ } \
43
env->vstart = 0; \
44
/* set tail elements to 1s */ \
45
vext_set_elems_1s(vd, vta, esz, vlenb); \
46
--
47
2.48.1
diff view generated by jsdifflib
New patch
[PULL 07/59] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set
1
From: Max Chou <max.chou@sifive.com>
1
2
3
In prop_vlen_set function, there is an incorrect comparison between
4
vlen(bit) and vlenb(byte).
5
This will cause unexpected error when user applies the `vlen=1024` cpu
6
option with a vendor predefined cpu type that the default vlen is
7
1024(vlenb=128).
8
9
Fixes: 4f6d036ccc ("target/riscv/cpu.c: remove cpu->cfg.vlen")
10
Signed-off-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-ID: <20250124090539.2506448-1-max.chou@sifive.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.c | 5 +++--
16
1 file changed, 3 insertions(+), 2 deletions(-)
17
18
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu.c
21
+++ b/target/riscv/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
23
void *opaque, Error **errp)
24
{
25
RISCVCPU *cpu = RISCV_CPU(obj);
26
+ uint16_t cpu_vlen = cpu->cfg.vlenb << 3;
27
uint16_t value;
28
29
if (!visit_type_uint16(v, name, &value, errp)) {
30
@@ -XXX,XX +XXX,XX @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
31
return;
32
}
33
34
- if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) {
35
+ if (value != cpu_vlen && riscv_cpu_is_vendor(obj)) {
36
cpu_set_prop_err(cpu, name, errp);
37
error_append_hint(errp, "Current '%s' val: %u\n",
38
- name, cpu->cfg.vlenb << 3);
39
+ name, cpu_vlen);
40
return;
41
}
42
43
--
44
2.48.1
diff view generated by jsdifflib
[PULL 04/16] target/riscv: add log of PMP permission checking
[PULL 08/59] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs
1
From: Jim Shu <cwshu@andestech.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Like MMU translation, add qemu log of PMP permission checking for
3
The mcontrol select bit (19) is always zero, meaning our triggers will
4
debugging.
4
always match virtual addresses. In this condition, if the user does not
5
specify a size for the trigger, the access size defaults to XLEN.
5
6
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
7
At this moment we're using def_size = 8 regardless of CPU XLEN. Use
8
def_size = 4 in case we're running 32 bits.
9
10
Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig extension")
11
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-ID: <20250121170626.1992570-2-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
17
target/riscv/debug.c | 6 ++++--
12
1 file changed, 12 insertions(+)
18
1 file changed, 4 insertions(+), 2 deletions(-)
13
19
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
20
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
22
--- a/target/riscv/debug.c
17
+++ b/target/riscv/cpu_helper.c
23
+++ b/target/riscv/debug.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
24
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
19
if (ret == TRANSLATE_SUCCESS) {
25
bool enabled = type2_breakpoint_enabled(ctrl);
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
26
CPUState *cs = env_cpu(env);
21
size, access_type, mode);
27
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
28
- uint32_t size;
29
+ uint32_t size, def_size;
30
31
if (!enabled) {
32
return;
33
@@ -XXX,XX +XXX,XX @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
34
cpu_watchpoint_insert(cs, addr, size, flags,
35
&env->cpu_watchpoint[index]);
36
} else {
37
- cpu_watchpoint_insert(cs, addr, 8, flags,
38
+ def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4;
22
+
39
+
23
+ qemu_log_mask(CPU_LOG_MMU,
40
+ cpu_watchpoint_insert(cs, addr, def_size, flags,
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
41
&env->cpu_watchpoint[index]);
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
26
+ __func__, pa, ret, prot_pmp, tlb_size);
27
+
28
prot &= prot_pmp;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
32
if (ret == TRANSLATE_SUCCESS) {
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
34
size, access_type, mode);
35
+
36
+ qemu_log_mask(CPU_LOG_MMU,
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
39
+ __func__, pa, ret, prot_pmp, tlb_size);
40
+
41
prot &= prot_pmp;
42
}
42
}
43
}
43
}
44
--
44
--
45
2.30.1
45
2.48.1
46
46
47
47
diff view generated by jsdifflib
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
[PULL 09/59] target/riscv: throw debug exception before page fault
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
According to the specification the "field SPVP of hstatus controls the
3
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
4
privilege level of the access" for the hypervisor virtual-machine load
4
that a debug exception that is triggered from a load/store has a higher
5
and store instructions HLV, HLVX and HSV.
5
priority than a possible fault that this access might trigger.
6
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
This is not the case ATM as shown in [1]. Adding a breakpoint in an
8
address that deliberately will fault is causing a load page fault
9
instead of a debug exception. The reason is that we're throwing in the
10
page fault as soon as the fault occurs (end of riscv_cpu_tlb_fill(),
11
raise_mmu_exception()), not allowing the installed watchpoints to
12
trigger.
13
14
Call cpu_check_watchpoint() in the page fault path to search and execute
15
any watchpoints that might exist for the address, never returning back
16
to the fault path. If no watchpoints are found cpu_check_watchpoint()
17
will return and we'll fall-through the regular path to
18
raise_mmu_exception().
19
20
[1] https://gitlab.com/qemu-project/qemu/-/issues/2627
21
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2627
23
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20250121170626.1992570-3-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
28
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
29
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
13
1 file changed, 14 insertions(+), 11 deletions(-)
30
1 file changed, 18 insertions(+)
14
31
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
32
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
34
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
35
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
36
@@ -XXX,XX +XXX,XX @@
20
use_background = true;
37
#include "exec/page-protection.h"
21
}
38
#include "instmap.h"
22
39
#include "tcg/tcg-op.h"
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
40
+#include "hw/core/tcg-cpu-ops.h"
24
+ /* MPRV does not affect the virtual-machine load/store
41
#include "trace.h"
25
+ instructions, HLV, HLVX, and HSV. */
42
#include "semihosting/common-semi.h"
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
43
#include "system/cpu-timers.h"
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
30
mode = get_field(env->mstatus, MSTATUS_MPP);
31
}
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
44
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
45
} else if (probe) {
34
__func__, address, access_type, mmu_idx);
46
return false;
35
47
} else {
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
48
+ int wp_access = 0;
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
49
+
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
50
+ if (access_type == MMU_DATA_LOAD) {
39
+ /* MPRV does not affect the virtual-machine load/store
51
+ wp_access |= BP_MEM_READ;
40
+ instructions, HLV, HLVX, and HSV. */
52
+ } else if (access_type == MMU_DATA_STORE) {
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
53
+ wp_access |= BP_MEM_WRITE;
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
54
+ }
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
55
+
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
56
+ /*
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
57
+ * If a watchpoint isn't found for 'addr' this will
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
58
+ * be a no-op and we'll resume the mmu_exception path.
47
+ two_stage_lookup = true;
59
+ * Otherwise we'll throw a debug exception and execution
48
}
60
+ * will continue elsewhere.
49
}
61
+ */
50
62
+ cpu_check_watchpoint(cs, address, size, MEMTXATTRS_UNSPECIFIED,
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
63
+ wp_access, retaddr);
52
- access_type != MMU_INST_FETCH &&
64
+
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
65
raise_mmu_exception(env, address, access_type, pmp_violation,
54
- get_field(env->mstatus, MSTATUS_MPV)) {
66
first_stage_error, two_stage_lookup,
55
- two_stage_lookup = true;
67
two_stage_indirect_error);
56
- }
57
-
58
if (riscv_cpu_virt_enabled(env) ||
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
60
access_type != MMU_INST_FETCH)) {
61
--
68
--
62
2.30.1
69
2.48.1
63
64
diff view generated by jsdifflib
New patch
[PULL 10/59] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking
1
From: Huang Borong <huangborong@bosc.ac.cn>
1
2
3
Remove the redundant masking of "hart_idx", as the same operation is
4
performed later during address calculation.
5
6
This change impacts the "hart_idx" value in the final qemu_log_mask()
7
call. The original "hart_idx" parameter should be used for logging to
8
ensure accuracy, rather than the masked value.
9
10
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
13
Message-ID: <20250115035105.19600-1-huangborong@bosc.ac.cn>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
hw/intc/riscv_aplic.c | 1 -
17
1 file changed, 1 deletion(-)
18
19
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/riscv_aplic.c
22
+++ b/hw/intc/riscv_aplic.c
23
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
24
APLIC_xMSICFGADDRH_HHXW_MASK;
25
26
group_idx = hart_idx >> lhxw;
27
- hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
28
29
addr = msicfgaddr;
30
addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
31
--
32
2.48.1
diff view generated by jsdifflib
New patch
[PULL 11/59] target/riscv: add ssu64xl
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
ssu64xl is defined in RVA22 as:
4
5
"sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must
6
be supported)."
7
8
This is always true in TCG and it's mandatory for RVA23, so claim
9
support for it.
10
11
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20250115184316.2344583-2-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.c | 1 +
18
tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
19
2 files changed, 1 insertion(+)
20
21
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.c
24
+++ b/target/riscv/cpu.c
25
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
26
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
27
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
28
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
29
+ ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
30
ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
31
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
32
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
33
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
34
index XXXXXXX..XXXXXXX 100644
35
Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ
36
--
37
2.48.1
diff view generated by jsdifflib
New patch
[PULL 12/59] target/riscv: use RVB in RVA22U64
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
From the time we added RVA22U64 until now the spec didn't declare 'RVB'
4
as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
5
[1] added the following in the 'RVA22U64 Mandatory Extensions' section:
6
7
"B Bit-manipulation instructions
8
9
Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
10
time of RVA22U64's ratification, the B extension had not yet been
11
defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
12
Mandating B is equivalent."
13
14
It is also equivalent to QEMU (see riscv_cpu_validate_b() in
15
target/riscv/tcg/tcg-cpu.c).
16
17
Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
18
not citing zba/zbb/zbs.
19
20
To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
21
parent of RVA23), use RVB in RVA22U64 as well.
22
23
(bios-tables-test change: RVB added to riscv,isa)
24
25
[1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
26
[2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
27
28
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20250115184316.2344583-3-dbarboza@ventanamicro.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
---
34
target/riscv/cpu.c | 2 +-
35
tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
36
2 files changed, 1 insertion(+), 1 deletion(-)
37
38
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu.c
41
+++ b/target/riscv/cpu.c
42
@@ -XXX,XX +XXX,XX @@ static const PropertyInfo prop_marchid = {
43
static RISCVCPUProfile RVA22U64 = {
44
.parent = NULL,
45
.name = "rva22u64",
46
- .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
47
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
48
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
49
.satp_mode = RISCV_PROFILE_ATTR_UNUSED,
50
.ext_offsets = {
51
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
52
index XXXXXXX..XXXXXXX 100644
53
Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ
54
--
55
2.48.1
diff view generated by jsdifflib
New patch
[PULL 13/59] target/riscv: add profile u_parent and s_parent
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The current 'parent' mechanic for profiles allows for one profile to be
4
a child of a previous/older profile, enabling all its extensions (and
5
the parent profile itself) and sparing us from tediously listing all
6
extensions for every profile.
7
8
This works fine for u-mode profiles. For s-mode profiles this is not
9
enough: a s-mode profile extends not only his equivalent u-mode profile
10
but also the previous s-mode profile. This means, for example, that
11
RVA23S64 extends both RVA23U64 and RVA22S64.
12
13
To fit this usage, rename the existing 'parent' to 'u_parent' and add a
14
new 's_parent' attribute for profiles. Handle both like we were doing
15
with the previous 'parent' attribute, i.e. if set, enable it. This
16
change does nothing for the existing profiles but will make RVA23S64
17
simpler.
18
19
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Message-ID: <20250115184316.2344583-4-dbarboza@ventanamicro.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
26
target/riscv/cpu.h | 3 ++-
27
target/riscv/cpu.c | 6 ++++--
28
target/riscv/tcg/tcg-cpu.c | 35 ++++++++++++++++++++++++++---------
29
3 files changed, 32 insertions(+), 12 deletions(-)
30
31
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.h
34
+++ b/target/riscv/cpu.h
35
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit);
36
#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
37
38
typedef struct riscv_cpu_profile {
39
- struct riscv_cpu_profile *parent;
40
+ struct riscv_cpu_profile *u_parent;
41
+ struct riscv_cpu_profile *s_parent;
42
const char *name;
43
uint32_t misa_ext;
44
bool enabled;
45
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/riscv/cpu.c
48
+++ b/target/riscv/cpu.c
49
@@ -XXX,XX +XXX,XX @@ static const PropertyInfo prop_marchid = {
50
* doesn't need to be manually enabled by the profile.
51
*/
52
static RISCVCPUProfile RVA22U64 = {
53
- .parent = NULL,
54
+ .u_parent = NULL,
55
+ .s_parent = NULL,
56
.name = "rva22u64",
57
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
58
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
59
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22U64 = {
60
* The remaining features/extensions comes from RVA22U64.
61
*/
62
static RISCVCPUProfile RVA22S64 = {
63
- .parent = &RVA22U64,
64
+ .u_parent = &RVA22U64,
65
+ .s_parent = NULL,
66
.name = "rva22s64",
67
.misa_ext = RVS,
68
.priv_spec = PRIV_VERSION_1_12_0,
69
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/riscv/tcg/tcg-cpu.c
72
+++ b/target/riscv/tcg/tcg-cpu.c
73
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
74
}
75
#endif
76
77
+static void riscv_cpu_check_parent_profile(RISCVCPU *cpu,
78
+ RISCVCPUProfile *profile,
79
+ RISCVCPUProfile *parent)
80
+{
81
+ const char *parent_name;
82
+ bool parent_enabled;
83
+
84
+ if (!profile->enabled || !parent) {
85
+ return;
86
+ }
87
+
88
+ parent_name = parent->name;
89
+ parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL);
90
+ profile->enabled = parent_enabled;
91
+}
92
+
93
static void riscv_cpu_validate_profile(RISCVCPU *cpu,
94
RISCVCPUProfile *profile)
95
{
96
CPURISCVState *env = &cpu->env;
97
const char *warn_msg = "Profile %s mandates disabled extension %s";
98
bool send_warn = profile->user_set && profile->enabled;
99
- bool parent_enabled, profile_impl = true;
100
+ bool profile_impl = true;
101
int i;
102
103
#ifndef CONFIG_USER_ONLY
104
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
105
106
profile->enabled = profile_impl;
107
108
- if (profile->parent != NULL) {
109
- parent_enabled = object_property_get_bool(OBJECT(cpu),
110
- profile->parent->name,
111
- NULL);
112
- profile->enabled = profile->enabled && parent_enabled;
113
- }
114
+ riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
115
+ riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
116
}
117
118
static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
119
@@ -XXX,XX +XXX,XX @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
120
profile->user_set = true;
121
profile->enabled = value;
122
123
- if (profile->parent != NULL) {
124
- object_property_set_bool(obj, profile->parent->name,
125
+ if (profile->u_parent != NULL) {
126
+ object_property_set_bool(obj, profile->u_parent->name,
127
+ profile->enabled, NULL);
128
+ }
129
+
130
+ if (profile->s_parent != NULL) {
131
+ object_property_set_bool(obj, profile->s_parent->name,
132
profile->enabled, NULL);
133
}
134
135
--
136
2.48.1
diff view generated by jsdifflib
New patch
[PULL 14/59] target/riscv: change priv_ver check in validate_profile()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The S profiles do a priv_ver check during validation to see if the
4
running priv_ver is compatible with it. This check is done by comparing
5
if the running priv_ver is equal to the priv_ver the profile specifies.
6
7
There is an universe where we added RVA23S64 support based on both
8
RVA23U64 and RVA22S64 and this error is being thrown:
9
10
qemu-system-riscv64: warning: Profile rva22s64 requires
11
priv spec v1.12.0, but priv ver v1.13.0 was set
12
13
We're enabling RVA22S64 (priv_ver 1.12) as a dependency of RVA23S64
14
(priv_ver 1.13) and complaining to users about what we did ourselves.
15
16
There's no drawback in allowing a profile to run in an env that has a
17
priv_ver newer than it's required by it. So, like Hiro Nakamura saves
18
the future by changing the past, change the priv_ver check now to allow
19
profiles to run in a newer priv_ver. This universe will have one less
20
warning to deal with.
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Message-ID: <20250115184316.2344583-5-dbarboza@ventanamicro.com>
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
---
28
target/riscv/tcg/tcg-cpu.c | 2 +-
29
1 file changed, 1 insertion(+), 1 deletion(-)
30
31
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/tcg/tcg-cpu.c
34
+++ b/target/riscv/tcg/tcg-cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
36
#endif
37
38
if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
39
- profile->priv_spec != env->priv_ver) {
40
+ profile->priv_spec > env->priv_ver) {
41
profile_impl = false;
42
43
if (send_warn) {
44
--
45
2.48.1
diff view generated by jsdifflib
New patch
[PULL 15/59] target/riscv: add RVA23U64 profile
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since
4
all RVA22U64 mandatory extensions are also present in RVA23U64. What's
5
left then is to list the mandatory extensions that are RVA23 only.
6
7
A new "rva23u64" CPU is also added.
8
9
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
10
11
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20250115184316.2344583-6-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu-qom.h | 1 +
18
target/riscv/cpu.c | 33 +++++++++++++++++++++++++++++++++
19
2 files changed, 34 insertions(+)
20
21
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu-qom.h
24
+++ b/target/riscv/cpu-qom.h
25
@@ -XXX,XX +XXX,XX @@
26
#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
27
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
28
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
29
+#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
30
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
31
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
32
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22S64 = {
38
}
39
};
40
41
+/*
42
+ * All mandatory extensions from RVA22U64 are present
43
+ * in RVA23U64 so set RVA22 as a parent. We need to
44
+ * declare just the newly added mandatory extensions.
45
+ */
46
+static RISCVCPUProfile RVA23U64 = {
47
+ .u_parent = &RVA22U64,
48
+ .s_parent = NULL,
49
+ .name = "rva23u64",
50
+ .misa_ext = RVV,
51
+ .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
52
+ .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
53
+ .ext_offsets = {
54
+ CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb),
55
+ CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl),
56
+ CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop),
57
+ CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb),
58
+ CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs),
59
+ CPU_CFG_OFFSET(ext_supm),
60
+
61
+ RISCV_PROFILE_EXT_LIST_END
62
+ }
63
+};
64
+
65
RISCVCPUProfile *riscv_profiles[] = {
66
&RVA22U64,
67
&RVA22S64,
68
+ &RVA23U64,
69
NULL,
70
};
71
72
@@ -XXX,XX +XXX,XX @@ static void rva22s64_profile_cpu_init(Object *obj)
73
74
RVA22S64.enabled = true;
75
}
76
+
77
+static void rva23u64_profile_cpu_init(Object *obj)
78
+{
79
+ rv64i_bare_cpu_init(obj);
80
+
81
+ RVA23U64.enabled = true;
82
+}
83
#endif
84
85
static const gchar *riscv_gdb_arch_name(CPUState *cs)
86
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
87
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
88
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
89
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
90
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
91
#endif /* TARGET_RISCV64 */
92
};
93
94
--
95
2.48.1
diff view generated by jsdifflib
New patch
[PULL 16/59] target/riscv: add RVA23S64 profile
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Add RVA23S64 as described in [1]. This profile inherits all mandatory
4
extensions of RVA23U64 and RVA22S64, making it a child of both profiles.
5
6
A new "rva23s64" profile CPU is also added. This is the generated
7
riscv,isa for it (taken via -M dumpdtb):
8
9
rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_
10
ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_
11
zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_
12
zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_shcounterenw_
13
sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smnpm_smstateen_ssccptr_
14
sscofpmf_sscounterenw_ssnpm_ssstateen_sstc_sstvala_sstvecd_ssu64xl_
15
supm_svade_svinval_svnapot_svpbmt
16
17
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
18
19
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
20
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-ID: <20250115184316.2344583-7-dbarboza@ventanamicro.com>
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
25
target/riscv/cpu-qom.h | 1 +
26
target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++
27
2 files changed, 40 insertions(+)
28
29
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu-qom.h
32
+++ b/target/riscv/cpu-qom.h
33
@@ -XXX,XX +XXX,XX @@
34
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
35
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
36
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
37
+#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
38
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
39
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
40
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
41
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/riscv/cpu.c
44
+++ b/target/riscv/cpu.c
45
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA23U64 = {
46
}
47
};
48
49
+/*
50
+ * As with RVA23U64, RVA23S64 also defines 'named features'.
51
+ *
52
+ * Cache related features that we consider enabled since we don't
53
+ * implement cache: Ssccptr
54
+ *
55
+ * Other named features that we already implement: Sstvecd, Sstvala,
56
+ * Sscounterenw, Ssu64xl
57
+ *
58
+ * The remaining features/extensions comes from RVA23S64.
59
+ */
60
+static RISCVCPUProfile RVA23S64 = {
61
+ .u_parent = &RVA23U64,
62
+ .s_parent = &RVA22S64,
63
+ .name = "rva23s64",
64
+ .misa_ext = RVS,
65
+ .priv_spec = PRIV_VERSION_1_13_0,
66
+ .satp_mode = VM_1_10_SV39,
67
+ .ext_offsets = {
68
+ /* New in RVA23S64 */
69
+ CPU_CFG_OFFSET(ext_svnapot), CPU_CFG_OFFSET(ext_sstc),
70
+ CPU_CFG_OFFSET(ext_sscofpmf), CPU_CFG_OFFSET(ext_ssnpm),
71
+
72
+ /* Named features: Sha */
73
+ CPU_CFG_OFFSET(ext_sha),
74
+
75
+ RISCV_PROFILE_EXT_LIST_END
76
+ }
77
+};
78
+
79
RISCVCPUProfile *riscv_profiles[] = {
80
&RVA22U64,
81
&RVA22S64,
82
&RVA23U64,
83
+ &RVA23S64,
84
NULL,
85
};
86
87
@@ -XXX,XX +XXX,XX @@ static void rva23u64_profile_cpu_init(Object *obj)
88
89
RVA23U64.enabled = true;
90
}
91
+
92
+static void rva23s64_profile_cpu_init(Object *obj)
93
+{
94
+ rv64i_bare_cpu_init(obj);
95
+
96
+ RVA23S64.enabled = true;
97
+}
98
#endif
99
100
static const gchar *riscv_gdb_arch_name(CPUState *cs)
101
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
102
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
103
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
104
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
105
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profile_cpu_init),
106
#endif /* TARGET_RISCV64 */
107
};
108
109
--
110
2.48.1
diff view generated by jsdifflib
New patch
[PULL 17/59] hw/riscv/riscv-iommu: Remove redundant struct members
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
Initially, the IOMMU would create a thread, but this thread was removed in
4
the merged version. The struct members for thread control should have been
5
removed as well, but they were not removed in commit 0c54acb8243
6
("hw/riscv: add RISC-V IOMMU base emulation").
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-ID: <20250115141730.30858-1-jason.chien@sifive.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
hw/riscv/riscv-iommu.h | 5 -----
16
1 file changed, 5 deletions(-)
17
18
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/riscv/riscv-iommu.h
21
+++ b/hw/riscv/riscv-iommu.h
22
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
23
/* interrupt notifier */
24
void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
25
26
- /* IOMMU State Machine */
27
- QemuThread core_proc; /* Background processing thread */
28
- QemuCond core_cond; /* Background processing wake up signal */
29
- unsigned core_exec; /* Processing thread execution actions */
30
-
31
/* IOMMU target address space */
32
AddressSpace *target_as;
33
MemoryRegion *target_mr;
34
--
35
2.48.1
diff view generated by jsdifflib
New patch
[PULL 18/59] hw/riscv/riscv-iommu-bits: Remove duplicate definitions
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
The header contains duplicate macro definitions.
4
This commit eliminates the duplicate part.
5
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20250115141730.30858-2-jason.chien@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/riscv-iommu-bits.h | 22 ++++++----------------
14
1 file changed, 6 insertions(+), 16 deletions(-)
15
16
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/riscv-iommu-bits.h
19
+++ b/hw/riscv/riscv-iommu-bits.h
20
@@ -XXX,XX +XXX,XX @@ struct riscv_iommu_pq_record {
21
#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
22
#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
23
#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
24
+
25
/* Payload fields */
26
+#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
27
+#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
28
+#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
29
#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
30
+#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
31
+#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
32
33
/* Common field positions */
34
#define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
35
@@ -XXX,XX +XXX,XX @@ enum riscv_iommu_fq_ttypes {
36
RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9,
37
};
38
39
-/* Header fields */
40
-#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
41
-#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
42
-#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
43
-#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
44
-#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
45
-
46
-/* Payload fields */
47
-#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
48
-#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
49
-#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
50
-#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
51
-#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
52
-#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
53
-
54
-
55
/*
56
* struct riscv_iommu_msi_pte - MSI Page Table Entry
57
*/
58
--
59
2.48.1
diff view generated by jsdifflib
New patch
[PULL 19/59] goldfish_rtc: Fix tick_offset migration
1
From: Rodrigo Dias Correa <r@drigo.nl>
1
2
3
Instead of migrating the raw tick_offset, goldfish_rtc migrates a
4
recalculated value based on QEMU_CLOCK_VIRTUAL. As QEMU_CLOCK_VIRTUAL
5
stands still across a save-and-restore cycle, the guest RTC becomes out
6
of sync with the host RTC when the VM is restored.
7
8
As described in the bug description, it looks like this calculation was
9
copied from pl031 RTC, which had its tick_offset migration fixed by
10
Commit 032cfe6a79c8 ("pl031: Correctly migrate state when using -rtc
11
clock=host").
12
13
Migrate the tick_offset directly, adding it as a version-dependent field
14
to VMState. Keep the old behavior when migrating from previous versions.
15
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2033
17
Signed-off-by: Rodrigo Dias Correa <r@drigo.nl>
18
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
19
Message-ID: <20250114212150.228241-1-r@drigo.nl>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
---
22
hw/rtc/goldfish_rtc.c | 43 +++++++++++++------------------------------
23
1 file changed, 13 insertions(+), 30 deletions(-)
24
25
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/rtc/goldfish_rtc.c
28
+++ b/hw/rtc/goldfish_rtc.c
29
@@ -XXX,XX +XXX,XX @@ static void goldfish_rtc_write(void *opaque, hwaddr offset,
30
trace_goldfish_rtc_write(offset, value);
31
}
32
33
-static int goldfish_rtc_pre_save(void *opaque)
34
-{
35
- uint64_t delta;
36
- GoldfishRTCState *s = opaque;
37
-
38
- /*
39
- * We want to migrate this offset, which sounds straightforward.
40
- * Unfortunately, we cannot directly pass tick_offset because
41
- * rtc_clock on destination Host might not be same source Host.
42
- *
43
- * To tackle, this we pass tick_offset relative to vm_clock from
44
- * source Host and make it relative to rtc_clock at destination Host.
45
- */
46
- delta = qemu_clock_get_ns(rtc_clock) -
47
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
48
- s->tick_offset_vmstate = s->tick_offset + delta;
49
-
50
- return 0;
51
-}
52
-
53
static int goldfish_rtc_post_load(void *opaque, int version_id)
54
{
55
- uint64_t delta;
56
GoldfishRTCState *s = opaque;
57
58
- /*
59
- * We extract tick_offset from tick_offset_vmstate by doing
60
- * reverse math compared to pre_save() function.
61
- */
62
- delta = qemu_clock_get_ns(rtc_clock) -
63
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
64
- s->tick_offset = s->tick_offset_vmstate - delta;
65
+ if (version_id < 3) {
66
+ /*
67
+ * Previous versions didn't migrate tick_offset directly. Instead, they
68
+ * migrated tick_offset_vmstate, which is a recalculation based on
69
+ * QEMU_CLOCK_VIRTUAL. We use tick_offset_vmstate when migrating from
70
+ * older versions.
71
+ */
72
+ uint64_t delta = qemu_clock_get_ns(rtc_clock) -
73
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
74
+ s->tick_offset = s->tick_offset_vmstate - delta;
75
+ }
76
77
goldfish_rtc_set_alarm(s);
78
79
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps goldfish_rtc_ops[2] = {
80
81
static const VMStateDescription goldfish_rtc_vmstate = {
82
.name = TYPE_GOLDFISH_RTC,
83
- .version_id = 2,
84
- .pre_save = goldfish_rtc_pre_save,
85
+ .version_id = 3,
86
.post_load = goldfish_rtc_post_load,
87
.fields = (const VMStateField[]) {
88
VMSTATE_UINT64(tick_offset_vmstate, GoldfishRTCState),
89
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription goldfish_rtc_vmstate = {
90
VMSTATE_UINT32(irq_pending, GoldfishRTCState),
91
VMSTATE_UINT32(irq_enabled, GoldfishRTCState),
92
VMSTATE_UINT32(time_high, GoldfishRTCState),
93
+ VMSTATE_UINT64_V(tick_offset, GoldfishRTCState, 3),
94
VMSTATE_END_OF_LIST()
95
}
96
};
97
--
98
2.48.1
diff view generated by jsdifflib
[PULL 10/16] hw/riscv: allow ramfb on virt
[PULL 20/59] hw/riscv/virt: Add serial alias in DTB
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Vasilis Liaskovitis <vliaskovitis@suse.com>
2
2
3
Allow ramfb on virt. This lets `-device ramfb' work.
3
Add an "aliases" node with a "serial0" entry for the single UART
4
in the riscv virt machine.
4
5
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2774
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
10
Message-ID: <20250116161007.39710-1-vliaskovitis@suse.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
12
---
11
hw/riscv/virt.c | 3 +++
13
hw/riscv/virt.c | 3 +++
12
1 file changed, 3 insertions(+)
14
1 file changed, 3 insertions(+)
13
15
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
16
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
18
--- a/hw/riscv/virt.c
17
+++ b/hw/riscv/virt.c
19
+++ b/hw/riscv/virt.c
18
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
19
#include "sysemu/sysemu.h"
21
}
20
#include "hw/pci/pci.h"
22
21
#include "hw/pci-host/gpex.h"
23
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
22
+#include "hw/display/ramfb.h"
24
+ qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name);
23
25
}
24
static const MemMapEntry virt_memmap[] = {
26
25
[VIRT_DEBUG] = { 0x0, 0x100 },
27
static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
29
qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
30
rng_seed, sizeof(rng_seed));
29
mc->numa_mem_supported = true;
31
32
+ qemu_fdt_add_subnode(ms->fdt, "/aliases");
30
+
33
+
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
34
create_fdt_flash(s, memmap);
32
}
35
create_fdt_fw_cfg(s, memmap);
33
36
create_fdt_pmu(s);
34
static const TypeInfo virt_machine_typeinfo = {
35
--
37
--
36
2.30.1
38
2.48.1
37
38
diff view generated by jsdifflib
New patch
[PULL 21/59] MAINTAINERS: Remove Bin Meng from RISC-V maintainers
1
From: Alistair Francis <alistair23@gmail.com>
1
2
3
Bin Meng has been a long time contributor and maintainer for QEMU RISC-V
4
and has been very beneficial to the RISC-V ecosystem.
5
6
Unfortunately his email has started to bounce so this patch is removing
7
them from MAINTAINERS. If in the future Bin Meng wants to return we will
8
happily re-add them.
9
10
Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer.
11
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-ID: <20250128060546.1374394-1-alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
MAINTAINERS | 5 +----
18
1 file changed, 1 insertion(+), 4 deletions(-)
19
20
diff --git a/MAINTAINERS b/MAINTAINERS
21
index XXXXXXX..XXXXXXX 100644
22
--- a/MAINTAINERS
23
+++ b/MAINTAINERS
24
@@ -XXX,XX +XXX,XX @@ F: tests/functional/test_ppc_74xx.py
25
RISC-V TCG CPUs
26
M: Palmer Dabbelt <palmer@dabbelt.com>
27
M: Alistair Francis <alistair.francis@wdc.com>
28
-M: Bin Meng <bmeng.cn@gmail.com>
29
R: Weiwei Li <liwei1518@gmail.com>
30
R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
33
F: include/hw/*/ibex_*.h
34
35
Microchip PolarFire SoC Icicle Kit
36
-M: Bin Meng <bmeng.cn@gmail.com>
37
L: qemu-riscv@nongnu.org
38
S: Supported
39
F: docs/system/riscv/microchip-icicle-kit.rst
40
@@ -XXX,XX +XXX,XX @@ F: include/hw/char/shakti_uart.h
41
42
SiFive Machines
43
M: Alistair Francis <Alistair.Francis@wdc.com>
44
-M: Bin Meng <bmeng.cn@gmail.com>
45
M: Palmer Dabbelt <palmer@dabbelt.com>
46
L: qemu-riscv@nongnu.org
47
S: Supported
48
@@ -XXX,XX +XXX,XX @@ S: Orphan
49
F: hw/i386/amd_iommu.?
50
51
OpenSBI Firmware
52
-M: Bin Meng <bmeng.cn@gmail.com>
53
+L: qemu-riscv@nongnu.org
54
S: Supported
55
F: pc-bios/opensbi-*
56
F: .gitlab-ci.d/opensbi.yml
57
--
58
2.48.1
diff view generated by jsdifflib
New patch
[PULL 22/59] target/riscv: Remove obsolete sfence.vm instruction
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
1
2
3
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Jason Chien <jason.chien@sifive.com>
6
Message-ID: <20250205-b4-ctr_upstream_v6-v6-1-439d8e06c8ef@rivosinc.com>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
target/riscv/insn32.decode | 1 -
10
target/riscv/insn_trans/trans_privileged.c.inc | 5 -----
11
2 files changed, 6 deletions(-)
12
13
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/insn32.decode
16
+++ b/target/riscv/insn32.decode
17
@@ -XXX,XX +XXX,XX @@ sret 0001000 00010 00000 000 00000 1110011
18
mret 0011000 00010 00000 000 00000 1110011
19
wfi 0001000 00101 00000 000 00000 1110011
20
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
21
-sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
22
23
# *** NMI ***
24
mnret 0111000 00010 00000 000 00000 1110011
25
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/insn_trans/trans_privileged.c.inc
28
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
29
@@ -XXX,XX +XXX,XX @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
30
#endif
31
return false;
32
}
33
-
34
-static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
35
-{
36
- return false;
37
-}
38
--
39
2.48.1
diff view generated by jsdifflib
New patch
[PULL 23/59] target/riscv: Add Control Transfer Records CSR definitions.
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
1
2
3
The Control Transfer Records (CTR) extension provides a method to
4
record a limited branch history in register-accessible internal chip
5
storage.
6
7
This extension is similar to Arch LBR in x86 and BRBE in ARM.
8
The Extension has been stable and the latest release can be found here
9
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5
10
11
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
12
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <20250205-b4-ctr_upstream_v6-v6-2-439d8e06c8ef@rivosinc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu_bits.h | 145 ++++++++++++++++++++++++++++++++++++++++
17
1 file changed, 145 insertions(+)
18
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu_bits.h
22
+++ b/target/riscv/cpu_bits.h
23
@@ -XXX,XX +XXX,XX @@
24
#define CSR_SIEH 0x114
25
#define CSR_SIPH 0x154
26
27
+/* Machine-Level Control transfer records CSRs */
28
+#define CSR_MCTRCTL 0x34e
29
+
30
+/* Supervisor-Level Control transfer records CSRs */
31
+#define CSR_SCTRCTL 0x14e
32
+#define CSR_SCTRSTATUS 0x14f
33
+#define CSR_SCTRDEPTH 0x15f
34
+
35
+/* VS-Level Control transfer records CSRs */
36
+#define CSR_VSCTRCTL 0x24e
37
+
38
/* Hpervisor CSRs */
39
#define CSR_HSTATUS 0x600
40
#define CSR_HEDELEG 0x602
41
@@ -XXX,XX +XXX,XX @@
42
#define SMSTATEEN0_CS (1ULL << 0)
43
#define SMSTATEEN0_FCSR (1ULL << 1)
44
#define SMSTATEEN0_JVT (1ULL << 2)
45
+#define SMSTATEEN0_CTR (1ULL << 54)
46
#define SMSTATEEN0_P1P13 (1ULL << 56)
47
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
48
#define SMSTATEEN0_IMSIC (1ULL << 58)
49
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
50
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
51
#define HENVCFGH_STCE MENVCFGH_STCE
52
53
+/* Offsets for every pair of control bits per each priv level */
54
+#define XS_OFFSET 0ULL
55
+#define U_OFFSET 2ULL
56
+#define S_OFFSET 5ULL
57
+#define M_OFFSET 8ULL
58
+
59
+#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
60
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
61
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
62
+#define U_PM_INSN (PM_INSN << U_OFFSET)
63
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
64
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
65
+#define S_PM_INSN (PM_INSN << S_OFFSET)
66
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
67
+#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
68
+#define M_PM_INSN (PM_INSN << M_OFFSET)
69
+
70
+/* mmte CSR bits */
71
+#define MMTE_PM_XS_BITS PM_XS_BITS
72
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
73
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
74
+#define MMTE_U_PM_INSN U_PM_INSN
75
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
76
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
77
+#define MMTE_S_PM_INSN S_PM_INSN
78
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
79
+#define MMTE_M_PM_CURRENT M_PM_CURRENT
80
+#define MMTE_M_PM_INSN M_PM_INSN
81
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
82
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
83
+ MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
84
+ MMTE_PM_XS_BITS)
85
+
86
+/* (v)smte CSR bits */
87
+#define SMTE_PM_XS_BITS PM_XS_BITS
88
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
89
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
90
+#define SMTE_U_PM_INSN U_PM_INSN
91
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
92
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
93
+#define SMTE_S_PM_INSN S_PM_INSN
94
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
95
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
96
+ SMTE_PM_XS_BITS)
97
+
98
+/* umte CSR bits */
99
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
100
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
101
+#define UMTE_U_PM_INSN U_PM_INSN
102
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
103
+
104
+/* CTR control register commom fields */
105
+#define XCTRCTL_U BIT_ULL(0)
106
+#define XCTRCTL_S BIT_ULL(1)
107
+#define XCTRCTL_RASEMU BIT_ULL(7)
108
+#define XCTRCTL_STE BIT_ULL(8)
109
+#define XCTRCTL_BPFRZ BIT_ULL(11)
110
+#define XCTRCTL_LCOFIFRZ BIT_ULL(12)
111
+#define XCTRCTL_EXCINH BIT_ULL(33)
112
+#define XCTRCTL_INTRINH BIT_ULL(34)
113
+#define XCTRCTL_TRETINH BIT_ULL(35)
114
+#define XCTRCTL_NTBREN BIT_ULL(36)
115
+#define XCTRCTL_TKBRINH BIT_ULL(37)
116
+#define XCTRCTL_INDCALLINH BIT_ULL(40)
117
+#define XCTRCTL_DIRCALLINH BIT_ULL(41)
118
+#define XCTRCTL_INDJMPINH BIT_ULL(42)
119
+#define XCTRCTL_DIRJMPINH BIT_ULL(43)
120
+#define XCTRCTL_CORSWAPINH BIT_ULL(44)
121
+#define XCTRCTL_RETINH BIT_ULL(45)
122
+#define XCTRCTL_INDLJMPINH BIT_ULL(46)
123
+#define XCTRCTL_DIRLJMPINH BIT_ULL(47)
124
+
125
+#define XCTRCTL_MASK (XCTRCTL_U | XCTRCTL_S | XCTRCTL_RASEMU | \
126
+ XCTRCTL_STE | XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ | \
127
+ XCTRCTL_EXCINH | XCTRCTL_INTRINH | XCTRCTL_TRETINH | \
128
+ XCTRCTL_NTBREN | XCTRCTL_TKBRINH | XCTRCTL_INDCALLINH | \
129
+ XCTRCTL_DIRCALLINH | XCTRCTL_INDJMPINH | \
130
+ XCTRCTL_DIRJMPINH | XCTRCTL_CORSWAPINH | \
131
+ XCTRCTL_RETINH | XCTRCTL_INDLJMPINH | XCTRCTL_DIRLJMPINH)
132
+
133
+#define XCTRCTL_INH_START 32U
134
+
135
+/* CTR mctrctl bits */
136
+#define MCTRCTL_M BIT_ULL(2)
137
+#define MCTRCTL_MTE BIT_ULL(9)
138
+
139
+#define MCTRCTL_MASK (XCTRCTL_MASK | MCTRCTL_M | MCTRCTL_MTE)
140
+#define SCTRCTL_MASK XCTRCTL_MASK
141
+#define VSCTRCTL_MASK XCTRCTL_MASK
142
+
143
+/* sctrstatus CSR bits. */
144
+#define SCTRSTATUS_WRPTR_MASK 0xFF
145
+#define SCTRSTATUS_FROZEN BIT(31)
146
+#define SCTRSTATUS_MASK (SCTRSTATUS_WRPTR_MASK | SCTRSTATUS_FROZEN)
147
+
148
+/* sctrdepth CSR bits. */
149
+#define SCTRDEPTH_MASK 0x7
150
+#define SCTRDEPTH_MIN 0U /* 16 Entries. */
151
+#define SCTRDEPTH_MAX 4U /* 256 Entries. */
152
+
153
+#define CTR_ENTRIES_FIRST 0x200
154
+#define CTR_ENTRIES_LAST 0x2ff
155
+
156
+#define CTRSOURCE_VALID BIT(0)
157
+#define CTRTARGET_MISP BIT(0)
158
+
159
+#define CTRDATA_TYPE_MASK 0xF
160
+#define CTRDATA_CCV BIT(15)
161
+#define CTRDATA_CCM_MASK 0xFFF0000
162
+#define CTRDATA_CCE_MASK 0xF0000000
163
+
164
+#define CTRDATA_MASK (CTRDATA_TYPE_MASK | CTRDATA_CCV | \
165
+ CTRDATA_CCM_MASK | CTRDATA_CCE_MASK)
166
+
167
+typedef enum CTRType {
168
+ CTRDATA_TYPE_NONE = 0,
169
+ CTRDATA_TYPE_EXCEPTION = 1,
170
+ CTRDATA_TYPE_INTERRUPT = 2,
171
+ CTRDATA_TYPE_EXCEP_INT_RET = 3,
172
+ CTRDATA_TYPE_NONTAKEN_BRANCH = 4,
173
+ CTRDATA_TYPE_TAKEN_BRANCH = 5,
174
+ CTRDATA_TYPE_RESERVED_0 = 6,
175
+ CTRDATA_TYPE_RESERVED_1 = 7,
176
+ CTRDATA_TYPE_INDIRECT_CALL = 8,
177
+ CTRDATA_TYPE_DIRECT_CALL = 9,
178
+ CTRDATA_TYPE_INDIRECT_JUMP = 10,
179
+ CTRDATA_TYPE_DIRECT_JUMP = 11,
180
+ CTRDATA_TYPE_CO_ROUTINE_SWAP = 12,
181
+ CTRDATA_TYPE_RETURN = 13,
182
+ CTRDATA_TYPE_OTHER_INDIRECT_JUMP = 14,
183
+ CTRDATA_TYPE_OTHER_DIRECT_JUMP = 15,
184
+} CTRType;
185
+
186
/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
187
#define ISELECT_IPRIO0 0x30
188
#define ISELECT_IPRIO15 0x3f
189
--
190
2.48.1
diff view generated by jsdifflib
New patch
[PULL 24/59] target/riscv: Add support for Control Transfer Records extension CSRs.
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
1
2
3
This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
4
sctrdepth CSRs handling.
5
6
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-ID: <20250205-b4-ctr_upstream_v6-v6-3-439d8e06c8ef@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/cpu.h | 5 ++
12
target/riscv/cpu_cfg.h | 2 +
13
target/riscv/csr.c | 144 +++++++++++++++++++++++++++++++++++++++++
14
3 files changed, 151 insertions(+)
15
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
19
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
21
target_ulong mcause;
22
target_ulong mtval; /* since: priv-1.10.0 */
23
24
+ uint64_t mctrctl;
25
+ uint32_t sctrdepth;
26
+ uint32_t sctrstatus;
27
+ uint64_t vsctrctl;
28
+
29
/* Machine and Supervisor interrupt priorities */
30
uint8_t miprio[64];
31
uint8_t siprio[64];
32
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/cpu_cfg.h
35
+++ b/target/riscv/cpu_cfg.h
36
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
37
bool ext_zvfhmin;
38
bool ext_smaia;
39
bool ext_ssaia;
40
+ bool ext_smctr;
41
+ bool ext_ssctr;
42
bool ext_sscofpmf;
43
bool ext_smepmp;
44
bool ext_smrnmi;
45
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/riscv/csr.c
48
+++ b/target/riscv/csr.c
49
@@ -XXX,XX +XXX,XX @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
50
return hmode(env, csrno);
51
}
52
53
+/*
54
+ * M-mode:
55
+ * Without ext_smctr raise illegal inst excep.
56
+ * Otherwise everything is accessible to m-mode.
57
+ *
58
+ * S-mode:
59
+ * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
60
+ * Otherwise everything other than mctrctl is accessible.
61
+ *
62
+ * VS-mode:
63
+ * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
64
+ * Without hstateen.ctr raise virtual illegal inst excep.
65
+ * Otherwise allow sctrctl (vsctrctl), sctrstatus, 0x200-0x2ff entry range.
66
+ * Always raise illegal instruction exception for sctrdepth.
67
+ */
68
+static RISCVException ctr_mmode(CPURISCVState *env, int csrno)
69
+{
70
+ /* Check if smctr-ext is present */
71
+ if (riscv_cpu_cfg(env)->ext_smctr) {
72
+ return RISCV_EXCP_NONE;
73
+ }
74
+
75
+ return RISCV_EXCP_ILLEGAL_INST;
76
+}
77
+
78
+static RISCVException ctr_smode(CPURISCVState *env, int csrno)
79
+{
80
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
81
+
82
+ if (!cfg->ext_smctr && !cfg->ext_ssctr) {
83
+ return RISCV_EXCP_ILLEGAL_INST;
84
+ }
85
+
86
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
87
+ if (ret == RISCV_EXCP_NONE && csrno == CSR_SCTRDEPTH &&
88
+ env->virt_enabled) {
89
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
90
+ }
91
+
92
+ return ret;
93
+}
94
+
95
static RISCVException aia_hmode(CPURISCVState *env, int csrno)
96
{
97
int ret;
98
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
99
wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
100
}
101
102
+ if (riscv_cpu_cfg(env)->ext_ssctr) {
103
+ wr_mask |= SMSTATEEN0_CTR;
104
+ }
105
+
106
return write_mstateen(env, csrno, wr_mask, new_val);
107
}
108
109
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
110
wr_mask |= SMSTATEEN0_P1P13;
111
}
112
113
+ if (riscv_cpu_cfg(env)->ext_ssctr) {
114
+ wr_mask |= SMSTATEEN0_CTR;
115
+ }
116
+
117
return write_mstateenh(env, csrno, wr_mask, new_val);
118
}
119
120
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
121
wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
122
}
123
124
+ if (riscv_cpu_cfg(env)->ext_ssctr) {
125
+ wr_mask |= SMSTATEEN0_CTR;
126
+ }
127
+
128
return write_hstateen(env, csrno, wr_mask, new_val);
129
}
130
131
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
132
{
133
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
134
135
+ if (riscv_cpu_cfg(env)->ext_ssctr) {
136
+ wr_mask |= SMSTATEEN0_CTR;
137
+ }
138
+
139
return write_hstateenh(env, csrno, wr_mask, new_val);
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
143
return RISCV_EXCP_NONE;
144
}
145
146
+static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno,
147
+ target_ulong *ret_val,
148
+ target_ulong new_val, target_ulong wr_mask)
149
+{
150
+ uint64_t mask = wr_mask & SCTRDEPTH_MASK;
151
+
152
+ if (ret_val) {
153
+ *ret_val = env->sctrdepth;
154
+ }
155
+
156
+ env->sctrdepth = (env->sctrdepth & ~mask) | (new_val & mask);
157
+
158
+ /* Correct depth. */
159
+ if (mask) {
160
+ uint64_t depth = get_field(env->sctrdepth, SCTRDEPTH_MASK);
161
+
162
+ if (depth > SCTRDEPTH_MAX) {
163
+ depth = SCTRDEPTH_MAX;
164
+ env->sctrdepth = set_field(env->sctrdepth, SCTRDEPTH_MASK, depth);
165
+ }
166
+
167
+ /* Update sctrstatus.WRPTR with a legal value */
168
+ depth = 16 << depth;
169
+ env->sctrstatus =
170
+ env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
171
+ }
172
+
173
+ return RISCV_EXCP_NONE;
174
+}
175
+
176
+static RISCVException rmw_sctrstatus(CPURISCVState *env, int csrno,
177
+ target_ulong *ret_val,
178
+ target_ulong new_val, target_ulong wr_mask)
179
+{
180
+ uint32_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
181
+ uint32_t mask = wr_mask & SCTRSTATUS_MASK;
182
+
183
+ if (ret_val) {
184
+ *ret_val = env->sctrstatus;
185
+ }
186
+
187
+ env->sctrstatus = (env->sctrstatus & ~mask) | (new_val & mask);
188
+
189
+ /* Update sctrstatus.WRPTR with a legal value */
190
+ env->sctrstatus = env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
191
+
192
+ return RISCV_EXCP_NONE;
193
+}
194
+
195
+static RISCVException rmw_xctrctl(CPURISCVState *env, int csrno,
196
+ target_ulong *ret_val,
197
+ target_ulong new_val, target_ulong wr_mask)
198
+{
199
+ uint64_t csr_mask, mask = wr_mask;
200
+ uint64_t *ctl_ptr = &env->mctrctl;
201
+
202
+ if (csrno == CSR_MCTRCTL) {
203
+ csr_mask = MCTRCTL_MASK;
204
+ } else if (csrno == CSR_SCTRCTL && !env->virt_enabled) {
205
+ csr_mask = SCTRCTL_MASK;
206
+ } else {
207
+ /*
208
+ * This is for csrno == CSR_SCTRCTL and env->virt_enabled == true
209
+ * or csrno == CSR_VSCTRCTL.
210
+ */
211
+ csr_mask = VSCTRCTL_MASK;
212
+ ctl_ptr = &env->vsctrctl;
213
+ }
214
+
215
+ mask &= csr_mask;
216
+
217
+ if (ret_val) {
218
+ *ret_val = *ctl_ptr & csr_mask;
219
+ }
220
+
221
+ *ctl_ptr = (*ctl_ptr & ~mask) | (new_val & mask);
222
+
223
+ return RISCV_EXCP_NONE;
224
+}
225
+
226
static RISCVException read_vstopi(CPURISCVState *env, int csrno,
227
target_ulong *val)
228
{
229
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
230
[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
231
[CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext },
232
233
+ [CSR_MCTRCTL] = { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrctl },
234
+ [CSR_SCTRCTL] = { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrctl },
235
+ [CSR_VSCTRCTL] = { "vsctrctl", ctr_smode, NULL, NULL, rmw_xctrctl },
236
+ [CSR_SCTRDEPTH] = { "sctrdepth", ctr_smode, NULL, NULL, rmw_sctrdepth },
237
+ [CSR_SCTRSTATUS] = { "sctrstatus", ctr_smode, NULL, NULL, rmw_sctrstatus },
238
+
239
/* Performance Counters */
240
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
241
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
242
--
243
2.48.1
diff view generated by jsdifflib
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
[PULL 25/59] target/riscv: Add support to record CTR entries.
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
2
2
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
3
This commit adds logic to records CTR entries of different types
4
short of its purpose, as all it checks is whether two-stage address
4
and adds required hooks in TCG and interrupt/Exception logic to
5
translation either via the hypervisor-load store instructions or the
5
record events.
6
MPRV feature would be allowed.
7
6
8
What we really need instead is whether two-stage address translation was
7
This commit also adds support to invoke freeze CTR logic for breakpoint
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
8
exceptions and counter overflow interrupts.
10
we do not have the information to reliably detect this. Therefore, when
11
we raise a memory fault exception we have to record whether two-stage
12
address translation is active.
13
9
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
10
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
12
Message-ID: <20250205-b4-ctr_upstream_v6-v6-4-439d8e06c8ef@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
14
---
19
target/riscv/cpu.h | 4 ++++
15
target/riscv/cpu.h | 7 +
20
target/riscv/cpu.c | 1 +
16
target/riscv/helper.h | 1 +
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
17
target/riscv/cpu_helper.c | 259 ++++++++++++++++++
22
3 files changed, 13 insertions(+), 13 deletions(-)
18
target/riscv/op_helper.c | 19 ++
19
target/riscv/translate.c | 46 ++++
20
.../riscv/insn_trans/trans_privileged.c.inc | 2 +
21
target/riscv/insn_trans/trans_rvi.c.inc | 75 +++++
22
target/riscv/insn_trans/trans_rvzce.c.inc | 21 ++
23
8 files changed, 430 insertions(+)
23
24
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
29
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
29
target_ulong satp_hs;
30
uint32_t sctrstatus;
30
uint64_t mstatus_hs;
31
uint64_t vsctrctl;
31
32
32
+ /* Signals whether the current exception occurred with two-stage address
33
+ uint64_t ctr_src[16 << SCTRDEPTH_MAX];
33
+ translation active. */
34
+ uint64_t ctr_dst[16 << SCTRDEPTH_MAX];
34
+ bool two_stage_lookup;
35
+ uint64_t ctr_data[16 << SCTRDEPTH_MAX];
35
+
36
+
36
target_ulong scounteren;
37
/* Machine and Supervisor interrupt priorities */
37
target_ulong mcounteren;
38
uint8_t miprio[64];
38
39
uint8_t siprio[64];
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
@@ -XXX,XX +XXX,XX @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
40
index XXXXXXX..XXXXXXX 100644
41
41
--- a/target/riscv/cpu.c
42
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
42
+++ b/target/riscv/cpu.c
43
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
44
+void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
45
+ enum CTRType type, target_ulong prev_priv, bool prev_virt);
45
env->mcause = 0;
46
+
46
env->pc = env->resetvec;
47
void riscv_translate_init(void);
47
+ env->two_stage_lookup = false;
48
void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
49
int *max_insns, vaddr pc, void *host_pc);
50
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/riscv/helper.h
53
+++ b/target/riscv/helper.h
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfi, void, env)
55
DEF_HELPER_1(wrs_nto, void, env)
56
DEF_HELPER_1(tlb_flush, void, env)
57
DEF_HELPER_1(tlb_flush_all, void, env)
58
+DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl)
59
/* Native Debug */
60
DEF_HELPER_1(itrigger_match, void, env)
48
#endif
61
#endif
49
cs->exception_index = EXCP_NONE;
50
env->load_res = -1;
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
62
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
52
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
64
--- a/target/riscv/cpu_helper.c
54
+++ b/target/riscv/cpu_helper.c
65
+++ b/target/riscv/cpu_helper.c
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
66
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
56
g_assert_not_reached();
67
}
57
}
58
env->badaddr = address;
59
+ env->two_stage_lookup = two_stage;
60
}
68
}
61
69
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
70
+static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
71
+ bool virt)
64
}
72
+{
65
73
+ uint64_t ctl = virt ? env->vsctrctl : env->mctrctl;
66
env->badaddr = addr;
74
+
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
75
+ assert((freeze_mask & (~(XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ))) == 0);
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
76
+
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
77
+ if (ctl & freeze_mask) {
78
+ env->sctrstatus |= SCTRSTATUS_FROZEN;
79
+ }
80
+}
81
+
82
+static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
83
+{
84
+ switch (priv) {
85
+ case PRV_M:
86
+ return MCTRCTL_M;
87
+ case PRV_S:
88
+ if (virt) {
89
+ return XCTRCTL_S;
90
+ }
91
+ return XCTRCTL_S;
92
+ case PRV_U:
93
+ if (virt) {
94
+ return XCTRCTL_U;
95
+ }
96
+ return XCTRCTL_U;
97
+ }
98
+
99
+ g_assert_not_reached();
100
+}
101
+
102
+static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv,
103
+ bool virt)
104
+{
105
+ switch (priv) {
106
+ case PRV_M:
107
+ return env->mctrctl;
108
+ case PRV_S:
109
+ case PRV_U:
110
+ if (virt) {
111
+ return env->vsctrctl;
112
+ }
113
+ return env->mctrctl;
114
+ }
115
+
116
+ g_assert_not_reached();
117
+}
118
+
119
+/*
120
+ * This function assumes that src privilege and target privilege are not same
121
+ * and src privilege is less than target privilege. This includes the virtual
122
+ * state as well.
123
+ */
124
+static bool riscv_ctr_check_xte(CPURISCVState *env, target_long src_prv,
125
+ bool src_virt)
126
+{
127
+ target_long tgt_prv = env->priv;
128
+ bool res = true;
129
+
130
+ /*
131
+ * VS and U mode are same in terms of xTE bits required to record an
132
+ * external trap. See 6.1.2. External Traps, table 8 External Trap Enable
133
+ * Requirements. This changes VS to U to simplify the logic a bit.
134
+ */
135
+ if (src_virt && src_prv == PRV_S) {
136
+ src_prv = PRV_U;
137
+ } else if (env->virt_enabled && tgt_prv == PRV_S) {
138
+ tgt_prv = PRV_U;
139
+ }
140
+
141
+ /* VU mode is an outlier here. */
142
+ if (src_virt && src_prv == PRV_U) {
143
+ res &= !!(env->vsctrctl & XCTRCTL_STE);
144
+ }
145
+
146
+ switch (src_prv) {
147
+ case PRV_U:
148
+ if (tgt_prv == PRV_U) {
149
+ break;
150
+ }
151
+ res &= !!(env->mctrctl & XCTRCTL_STE);
152
+ /* fall-through */
153
+ case PRV_S:
154
+ if (tgt_prv == PRV_S) {
155
+ break;
156
+ }
157
+ res &= !!(env->mctrctl & MCTRCTL_MTE);
158
+ /* fall-through */
159
+ case PRV_M:
160
+ break;
161
+ }
162
+
163
+ return res;
164
+}
165
+
166
+/*
167
+ * Special cases for traps and trap returns:
168
+ *
169
+ * 1- Traps, and trap returns, between enabled modes are recorded as normal.
170
+ * 2- Traps from an inhibited mode to an enabled mode, and trap returns from an
171
+ * enabled mode back to an inhibited mode, are partially recorded. In such
172
+ * cases, the PC from the inhibited mode (source PC for traps, and target PC
173
+ * for trap returns) is 0.
174
+ *
175
+ * 3- Trap returns from an inhibited mode to an enabled mode are not recorded.
176
+ * Traps from an enabled mode to an inhibited mode, known as external traps,
177
+ * receive special handling.
178
+ * By default external traps are not recorded, but a handshake mechanism exists
179
+ * to allow partial recording. Software running in the target mode of the trap
180
+ * can opt-in to allowing CTR to record traps into that mode even when the mode
181
+ * is inhibited. The MTE, STE, and VSTE bits allow M-mode, S-mode, and VS-mode,
182
+ * respectively, to opt-in. When an External Trap occurs, and xTE=1, such that
183
+ * x is the target privilege mode of the trap, will CTR record the trap. In such
184
+ * cases, the target PC is 0.
185
+ */
186
+/*
187
+ * CTR arrays are implemented as circular buffers and new entry is stored at
188
+ * sctrstatus.WRPTR, but they are presented to software as moving circular
189
+ * buffers. Which means, software get's the illusion that whenever a new entry
190
+ * is added the whole buffer is moved by one place and the new entry is added at
191
+ * the start keeping new entry at idx 0 and older ones follow.
192
+ *
193
+ * Depth = 16.
194
+ *
195
+ * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
196
+ * WRPTR W
197
+ * entry 7 6 5 4 3 2 1 0 F E D C B A 9 8
198
+ *
199
+ * When a new entry is added:
200
+ * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
201
+ * WRPTR W
202
+ * entry 8 7 6 5 4 3 2 1 0 F E D C B A 9
203
+ *
204
+ * entry here denotes the logical entry number that software can access
205
+ * using ctrsource, ctrtarget and ctrdata registers. So xiselect 0x200
206
+ * will return entry 0 i-e buffer[8] and 0x201 will return entry 1 i-e
207
+ * buffer[7]. Here is how we convert entry to buffer idx.
208
+ *
209
+ * entry = isel - CTR_ENTRIES_FIRST;
210
+ * idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1);
211
+ */
212
+void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
213
+ enum CTRType type, target_ulong src_priv, bool src_virt)
214
+{
215
+ bool tgt_virt = env->virt_enabled;
216
+ uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt);
217
+ uint64_t tgt_mask = riscv_ctr_priv_to_mask(env->priv, tgt_virt);
218
+ uint64_t src_ctrl = riscv_ctr_get_control(env, src_priv, src_virt);
219
+ uint64_t tgt_ctrl = riscv_ctr_get_control(env, env->priv, tgt_virt);
220
+ uint64_t depth, head;
221
+ bool ext_trap = false;
222
+
223
+ /*
224
+ * Return immediately if both target and src recording is disabled or if
225
+ * CTR is in frozen state.
226
+ */
227
+ if ((!(src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) ||
228
+ env->sctrstatus & SCTRSTATUS_FROZEN) {
229
+ return;
230
+ }
231
+
232
+ /*
233
+ * With RAS Emul enabled, only allow Indirect, direct calls, Function
234
+ * returns and Co-routine swap types.
235
+ */
236
+ if (tgt_ctrl & XCTRCTL_RASEMU &&
237
+ type != CTRDATA_TYPE_INDIRECT_CALL &&
238
+ type != CTRDATA_TYPE_DIRECT_CALL &&
239
+ type != CTRDATA_TYPE_RETURN &&
240
+ type != CTRDATA_TYPE_CO_ROUTINE_SWAP) {
241
+ return;
242
+ }
243
+
244
+ if (type == CTRDATA_TYPE_EXCEPTION || type == CTRDATA_TYPE_INTERRUPT) {
245
+ /* Case 2 for traps. */
246
+ if (!(src_ctrl & src_mask)) {
247
+ src = 0;
248
+ } else if (!(tgt_ctrl & tgt_mask)) {
249
+ /* Check if target priv-mode has allowed external trap recording. */
250
+ if (!riscv_ctr_check_xte(env, src_priv, src_virt)) {
251
+ return;
252
+ }
253
+
254
+ ext_trap = true;
255
+ dst = 0;
256
+ }
257
+ } else if (type == CTRDATA_TYPE_EXCEP_INT_RET) {
258
+ /*
259
+ * Case 3 for trap returns. Trap returns from inhibited mode are not
260
+ * recorded.
261
+ */
262
+ if (!(src_ctrl & src_mask)) {
263
+ return;
264
+ }
265
+
266
+ /* Case 2 for trap returns. */
267
+ if (!(tgt_ctrl & tgt_mask)) {
268
+ dst = 0;
269
+ }
270
+ }
271
+
272
+ /* Ignore filters in case of RASEMU mode or External trap. */
273
+ if (!(tgt_ctrl & XCTRCTL_RASEMU) && !ext_trap) {
274
+ /*
275
+ * Check if the specific type is inhibited. Not taken branch filter is
276
+ * an enable bit and needs to be checked separatly.
277
+ */
278
+ bool check = tgt_ctrl & BIT_ULL(type + XCTRCTL_INH_START);
279
+ if ((type == CTRDATA_TYPE_NONTAKEN_BRANCH && !check) ||
280
+ (type != CTRDATA_TYPE_NONTAKEN_BRANCH && check)) {
281
+ return;
282
+ }
283
+ }
284
+
285
+ head = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
286
+
287
+ depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
288
+ if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_RETURN) {
289
+ head = (head - 1) & (depth - 1);
290
+
291
+ env->ctr_src[head] &= ~CTRSOURCE_VALID;
292
+ env->sctrstatus =
293
+ set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
294
+ return;
295
+ }
296
+
297
+ /* In case of Co-routine SWAP we overwrite latest entry. */
298
+ if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_CO_ROUTINE_SWAP) {
299
+ head = (head - 1) & (depth - 1);
300
+ }
301
+
302
+ env->ctr_src[head] = src | CTRSOURCE_VALID;
303
+ env->ctr_dst[head] = dst & ~CTRTARGET_MISP;
304
+ env->ctr_data[head] = set_field(0, CTRDATA_TYPE_MASK, type);
305
+
306
+ head = (head + 1) & (depth - 1);
307
+
308
+ env->sctrstatus = set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
309
+}
310
+
311
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en)
312
{
313
g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
314
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
315
!(env->mip & (1ULL << cause));
316
bool smode_double_trap = false;
317
uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
318
+ const bool prev_virt = env->virt_enabled;
319
+ const target_ulong prev_priv = env->priv;
320
target_ulong tval = 0;
321
target_ulong tinst = 0;
322
target_ulong htval = 0;
323
target_ulong mtval2 = 0;
324
+ target_ulong src;
325
int sxlen = 0;
326
int mxlen = 16 << riscv_cpu_mxl(env);
327
bool nnmi_excep = false;
328
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
329
env->pc = (env->stvec >> 2 << 2) +
330
((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
331
riscv_cpu_set_mode(env, PRV_S, virt);
332
+
333
+ src = env->sepc;
334
} else {
335
/*
336
* If the hart encounters an exception while executing in M-mode
337
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
338
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
339
}
340
riscv_cpu_set_mode(env, PRV_M, virt);
341
+ src = env->mepc;
342
+ }
343
+
344
+ if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
345
+ if (async && cause == IRQ_PMU_OVF) {
346
+ riscv_ctr_freeze(env, XCTRCTL_LCOFIFRZ, virt);
347
+ } else if (!async && cause == RISCV_EXCP_BREAKPOINT) {
348
+ riscv_ctr_freeze(env, XCTRCTL_BPFRZ, virt);
349
+ }
350
+
351
+ riscv_ctr_add_entry(env, src, env->pc,
352
+ async ? CTRDATA_TYPE_INTERRUPT : CTRDATA_TYPE_EXCEPTION,
353
+ prev_priv, prev_virt);
354
}
355
356
/*
357
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
358
index XXXXXXX..XXXXXXX 100644
359
--- a/target/riscv/op_helper.c
360
+++ b/target/riscv/op_helper.c
361
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
362
{
363
uint64_t mstatus;
364
target_ulong prev_priv, prev_virt = env->virt_enabled;
365
+ const target_ulong src_priv = env->priv;
366
+ const bool src_virt = env->virt_enabled;
367
368
if (!(env->priv >= PRV_S)) {
369
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
370
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
371
}
372
env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, 0);
373
374
+ if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
375
+ riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET,
376
+ src_priv, src_virt);
377
+ }
378
+
379
return retpc;
70
}
380
}
71
381
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
382
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env)
73
g_assert_not_reached();
383
}
74
}
384
env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, 0);
75
env->badaddr = addr;
385
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
386
+ if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
387
+ riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET,
78
riscv_raise_exception(env, cs->exception_index, retaddr);
388
+ PRV_M, false);
389
+ }
390
+
391
return retpc;
79
}
392
}
80
#endif /* !CONFIG_USER_ONLY */
393
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
394
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mnret(CPURISCVState *env)
82
/* handle the trap in S-mode */
395
return retpc;
83
if (riscv_has_ext(env, RVH)) {
396
}
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
397
85
- bool two_stage_lookup = false;
398
+void helper_ctr_add_entry(CPURISCVState *env, target_ulong src,
86
399
+ target_ulong dest, target_ulong type)
87
- if (env->priv == PRV_M ||
400
+{
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
401
+ riscv_ctr_add_entry(env, src, dest, (enum CTRType)type,
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
402
+ env->priv, env->virt_enabled);
90
- get_field(env->hstatus, HSTATUS_HU))) {
403
+}
91
- two_stage_lookup = true;
404
+
92
- }
405
void helper_wfi(CPURISCVState *env)
93
-
406
{
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
407
CPUState *cs = env_cpu(env);
95
+ if (env->two_stage_lookup && write_tval) {
408
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
96
/*
409
index XXXXXXX..XXXXXXX 100644
97
* If we are writing a guest virtual address to stval, set
410
--- a/target/riscv/translate.c
98
* this to 1. If we are trapping to VS we will set this to 0
411
+++ b/target/riscv/translate.c
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
412
@@ -XXX,XX +XXX,XX @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
100
riscv_cpu_set_force_hs_excep(env, 0);
413
}
101
} else {
414
}
102
/* Trap into HS mode */
415
103
- if (!two_stage_lookup) {
416
+#ifndef CONFIG_USER_ONLY
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
417
+/*
105
- riscv_cpu_virt_enabled(env));
418
+ * Direct calls
106
- }
419
+ * - jal x1;
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
420
+ * - jal x5;
108
htval = env->guest_phys_fault_addr;
421
+ * - c.jal.
109
}
422
+ * - cm.jalt.
423
+ *
424
+ * Direct jumps
425
+ * - jal x0;
426
+ * - c.j;
427
+ * - cm.jt.
428
+ *
429
+ * Other direct jumps
430
+ * - jal rd where rd != x1 and rd != x5 and rd != x0;
431
+ */
432
+static void gen_ctr_jal(DisasContext *ctx, int rd, target_ulong imm)
433
+{
434
+ TCGv dest = tcg_temp_new();
435
+ TCGv src = tcg_temp_new();
436
+ TCGv type;
437
+
438
+ /*
439
+ * If rd is x1 or x5 link registers, treat this as direct call otherwise
440
+ * its a direct jump.
441
+ */
442
+ if (rd == 1 || rd == 5) {
443
+ type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL);
444
+ } else if (rd == 0) {
445
+ type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP);
446
+ } else {
447
+ type = tcg_constant_tl(CTRDATA_TYPE_OTHER_DIRECT_JUMP);
448
+ }
449
+
450
+ gen_pc_plus_diff(dest, ctx, imm);
451
+ gen_pc_plus_diff(src, ctx, 0);
452
+ gen_helper_ctr_add_entry(tcg_env, src, dest, type);
453
+}
454
+#endif
455
+
456
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
457
{
458
TCGv succ_pc = dest_gpr(ctx, rd);
459
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
110
}
460
}
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
461
}
112
* RISC-V ISA Specification.
462
113
*/
463
+#ifndef CONFIG_USER_ONLY
114
464
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
115
+ env->two_stage_lookup = false;
465
+ gen_ctr_jal(ctx, rd, imm);
116
#endif
466
+ }
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
467
+#endif
468
+
469
gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
470
gen_set_gpr(ctx, rd, succ_pc);
471
472
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
473
index XXXXXXX..XXXXXXX 100644
474
--- a/target/riscv/insn_trans/trans_privileged.c.inc
475
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
476
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
477
if (has_ext(ctx, RVS)) {
478
decode_save_opc(ctx, 0);
479
translator_io_start(&ctx->base);
480
+ gen_update_pc(ctx, 0);
481
gen_helper_sret(cpu_pc, tcg_env);
482
exit_tb(ctx); /* no chaining */
483
ctx->base.is_jmp = DISAS_NORETURN;
484
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
485
#ifndef CONFIG_USER_ONLY
486
decode_save_opc(ctx, 0);
487
translator_io_start(&ctx->base);
488
+ gen_update_pc(ctx, 0);
489
gen_helper_mret(cpu_pc, tcg_env);
490
exit_tb(ctx); /* no chaining */
491
ctx->base.is_jmp = DISAS_NORETURN;
492
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
493
index XXXXXXX..XXXXXXX 100644
494
--- a/target/riscv/insn_trans/trans_rvi.c.inc
495
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
496
@@ -XXX,XX +XXX,XX @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
497
return true;
118
}
498
}
499
500
+#ifndef CONFIG_USER_ONLY
501
+/*
502
+ * Indirect calls
503
+ * - jalr x1, rs where rs != x5;
504
+ * - jalr x5, rs where rs != x1;
505
+ * - c.jalr rs1 where rs1 != x5;
506
+ *
507
+ * Indirect jumps
508
+ * - jalr x0, rs where rs != x1 and rs != x5;
509
+ * - c.jr rs1 where rs1 != x1 and rs1 != x5.
510
+ *
511
+ * Returns
512
+ * - jalr rd, rs where (rs == x1 or rs == x5) and rd != x1 and rd != x5;
513
+ * - c.jr rs1 where rs1 == x1 or rs1 == x5.
514
+ *
515
+ * Co-routine swap
516
+ * - jalr x1, x5;
517
+ * - jalr x5, x1;
518
+ * - c.jalr x5.
519
+ *
520
+ * Other indirect jumps
521
+ * - jalr rd, rs where rs != x1, rs != x5, rd != x0, rd != x1 and rd != x5.
522
+ */
523
+static void gen_ctr_jalr(DisasContext *ctx, arg_jalr *a, TCGv dest)
524
+{
525
+ TCGv src = tcg_temp_new();
526
+ TCGv type;
527
+
528
+ if ((a->rd == 1 && a->rs1 != 5) || (a->rd == 5 && a->rs1 != 1)) {
529
+ type = tcg_constant_tl(CTRDATA_TYPE_INDIRECT_CALL);
530
+ } else if (a->rd == 0 && a->rs1 != 1 && a->rs1 != 5) {
531
+ type = tcg_constant_tl(CTRDATA_TYPE_INDIRECT_JUMP);
532
+ } else if ((a->rs1 == 1 || a->rs1 == 5) && (a->rd != 1 && a->rd != 5)) {
533
+ type = tcg_constant_tl(CTRDATA_TYPE_RETURN);
534
+ } else if ((a->rs1 == 1 && a->rd == 5) || (a->rs1 == 5 && a->rd == 1)) {
535
+ type = tcg_constant_tl(CTRDATA_TYPE_CO_ROUTINE_SWAP);
536
+ } else {
537
+ type = tcg_constant_tl(CTRDATA_TYPE_OTHER_INDIRECT_JUMP);
538
+ }
539
+
540
+ gen_pc_plus_diff(src, ctx, 0);
541
+ gen_helper_ctr_add_entry(tcg_env, src, dest, type);
542
+}
543
+#endif
544
+
545
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
546
{
547
TCGLabel *misaligned = NULL;
548
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
549
gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
550
gen_set_gpr(ctx, a->rd, succ_pc);
551
552
+#ifndef CONFIG_USER_ONLY
553
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
554
+ gen_ctr_jalr(ctx, a, target_pc);
555
+ }
556
+#endif
557
+
558
tcg_gen_mov_tl(cpu_pc, target_pc);
559
if (ctx->fcfi_enabled) {
560
/*
561
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
562
} else {
563
tcg_gen_brcond_tl(cond, src1, src2, l);
564
}
565
+
566
+#ifndef CONFIG_USER_ONLY
567
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
568
+ TCGv type = tcg_constant_tl(CTRDATA_TYPE_NONTAKEN_BRANCH);
569
+ TCGv dest = tcg_temp_new();
570
+ TCGv src = tcg_temp_new();
571
+
572
+ gen_pc_plus_diff(src, ctx, 0);
573
+ gen_pc_plus_diff(dest, ctx, ctx->cur_insn_len);
574
+ gen_helper_ctr_add_entry(tcg_env, src, dest, type);
575
+ }
576
+#endif
577
+
578
gen_goto_tb(ctx, 1, ctx->cur_insn_len);
579
ctx->pc_save = orig_pc_save;
580
581
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
582
gen_pc_plus_diff(target_pc, ctx, a->imm);
583
gen_exception_inst_addr_mis(ctx, target_pc);
584
} else {
585
+#ifndef CONFIG_USER_ONLY
586
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
587
+ TCGv type = tcg_constant_tl(CTRDATA_TYPE_TAKEN_BRANCH);
588
+ TCGv dest = tcg_temp_new();
589
+ TCGv src = tcg_temp_new();
590
+
591
+ gen_pc_plus_diff(src, ctx, 0);
592
+ gen_pc_plus_diff(dest, ctx, a->imm);
593
+ gen_helper_ctr_add_entry(tcg_env, src, dest, type);
594
+ }
595
+#endif
596
gen_goto_tb(ctx, 0, a->imm);
597
}
598
ctx->pc_save = -1;
599
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
600
index XXXXXXX..XXXXXXX 100644
601
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
602
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
603
@@ -XXX,XX +XXX,XX @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
604
605
if (ret) {
606
TCGv ret_addr = get_gpr(ctx, xRA, EXT_SIGN);
607
+#ifndef CONFIG_USER_ONLY
608
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
609
+ TCGv type = tcg_constant_tl(CTRDATA_TYPE_RETURN);
610
+ TCGv src = tcg_temp_new();
611
+ gen_pc_plus_diff(src, ctx, 0);
612
+ gen_helper_ctr_add_entry(tcg_env, src, ret_addr, type);
613
+ }
614
+#endif
615
tcg_gen_mov_tl(cpu_pc, ret_addr);
616
tcg_gen_lookup_and_goto_ptr();
617
ctx->base.is_jmp = DISAS_NORETURN;
618
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
619
gen_set_gpr(ctx, xRA, succ_pc);
620
}
621
622
+#ifndef CONFIG_USER_ONLY
623
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
624
+ if (a->index >= 32) {
625
+ TCGv type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL);
626
+ gen_helper_ctr_add_entry(tcg_env, cpu_pc, addr, type);
627
+ } else {
628
+ TCGv type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP);
629
+ gen_helper_ctr_add_entry(tcg_env, cpu_pc, addr, type);
630
+ }
631
+ }
632
+#endif
633
+
634
+
635
tcg_gen_mov_tl(cpu_pc, addr);
636
637
tcg_gen_lookup_and_goto_ptr();
119
--
638
--
120
2.30.1
639
2.48.1
121
122
diff view generated by jsdifflib
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
[PULL 26/59] target/riscv: Add CTR sctrclr instruction.
1
From: Jim Shu <cwshu@andestech.com>
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
2
2
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
3
CTR extension adds a new instruction sctrclr to quickly
4
Fix it by propagating PMP permission to TLB page permission.
4
clear the recorded entries buffer.
5
5
6
PMP permission checking also use MMU-style API to change TLB permission
6
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
7
and size.
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
8
Message-ID: <20250205-b4-ctr_upstream_v6-v6-5-439d8e06c8ef@rivosinc.com>
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
10
---
14
target/riscv/pmp.h | 4 +-
11
target/riscv/cpu.h | 1 +
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
12
target/riscv/helper.h | 1 +
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
13
target/riscv/insn32.decode | 1 +
17
3 files changed, 125 insertions(+), 43 deletions(-)
14
target/riscv/cpu_helper.c | 7 +++++
15
target/riscv/op_helper.c | 29 +++++++++++++++++++
16
.../riscv/insn_trans/trans_privileged.c.inc | 11 +++++++
17
6 files changed, 50 insertions(+)
18
18
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/pmp.h
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/pmp.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
23
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
24
target_ulong val);
24
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
25
void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
26
enum CTRType type, target_ulong prev_priv, bool prev_virt);
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
27
+void riscv_ctr_clear(CPURISCVState *env);
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
28
29
+ target_ulong mode);
29
void riscv_translate_init(void);
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
30
void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
31
target_ulong *tlb_size);
31
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
32
index XXXXXXX..XXXXXXX 100644
33
void pmp_update_rule_nums(CPURISCVState *env);
33
--- a/target/riscv/helper.h
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
34
+++ b/target/riscv/helper.h
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
35
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
36
36
DEF_HELPER_1(sret, tl, env)
37
#endif
37
DEF_HELPER_1(mret, tl, env)
38
DEF_HELPER_1(mnret, tl, env)
39
+DEF_HELPER_1(ctr_clear, void, env)
40
DEF_HELPER_1(wfi, void, env)
41
DEF_HELPER_1(wrs_nto, void, env)
42
DEF_HELPER_1(tlb_flush, void, env)
43
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/insn32.decode
46
+++ b/target/riscv/insn32.decode
47
@@ -XXX,XX +XXX,XX @@
48
# *** Privileged Instructions ***
49
ecall 000000000000 00000 000 00000 1110011
50
ebreak 000000000001 00000 000 00000 1110011
51
+sctrclr 000100000100 00000 000 00000 1110011
52
uret 0000000 00010 00000 000 00000 1110011
53
sret 0001000 00010 00000 000 00000 1110011
54
mret 0011000 00010 00000 000 00000 1110011
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
55
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
57
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
58
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
59
@@ -XXX,XX +XXX,XX @@ static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
43
env->load_res = -1;
60
}
44
}
61
}
45
62
46
+/*
63
+void riscv_ctr_clear(CPURISCVState *env)
47
+ * get_physical_address_pmp - check PMP permission for this physical address
48
+ *
49
+ * Match the PMP region and check permission for this physical address and it's
50
+ * TLB page. Returns 0 if the permission checking was successful
51
+ *
52
+ * @env: CPURISCVState
53
+ * @prot: The returned protection attributes
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
55
+ * permission checking. NULL if not set TLB page for addr.
56
+ * @addr: The physical address to be checked permission
57
+ * @access_type: The type of MMU access
58
+ * @mode: Indicates current privilege level.
59
+ */
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
61
+ target_ulong *tlb_size, hwaddr addr,
62
+ int size, MMUAccessType access_type,
63
+ int mode)
64
+{
64
+{
65
+ pmp_priv_t pmp_priv;
65
+ memset(env->ctr_src, 0x0, sizeof(env->ctr_src));
66
+ target_ulong tlb_size_pmp = 0;
66
+ memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst));
67
+ memset(env->ctr_data, 0x0, sizeof(env->ctr_data));
68
+}
67
+
69
+
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
70
static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
71
{
70
+ return TRANSLATE_SUCCESS;
72
switch (priv) {
73
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/op_helper.c
76
+++ b/target/riscv/op_helper.c
77
@@ -XXX,XX +XXX,XX @@ void helper_ctr_add_entry(CPURISCVState *env, target_ulong src,
78
env->priv, env->virt_enabled);
79
}
80
81
+void helper_ctr_clear(CPURISCVState *env)
82
+{
83
+ /*
84
+ * It's safe to call smstateen_acc_ok() for umode access regardless of the
85
+ * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the bit
86
+ * is zero, smstateen_acc_ok() will return the correct exception code and
87
+ * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that
88
+ * scenario the U-mode check below will handle that case.
89
+ */
90
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
91
+ if (ret != RISCV_EXCP_NONE) {
92
+ riscv_raise_exception(env, ret, GETPC());
71
+ }
93
+ }
72
+
94
+
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
95
+ if (env->priv == PRV_U) {
74
+ mode)) {
96
+ /*
75
+ *prot = 0;
97
+ * One corner case is when sctrclr is executed from VU-mode and
76
+ return TRANSLATE_PMP_FAIL;
98
+ * mstateen.CTR = 0, in which case we are supposed to raise
99
+ * RISCV_EXCP_ILLEGAL_INST. This case is already handled in
100
+ * smstateen_acc_ok().
101
+ */
102
+ uint32_t excep = env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
103
+ RISCV_EXCP_ILLEGAL_INST;
104
+ riscv_raise_exception(env, excep, GETPC());
77
+ }
105
+ }
78
+
106
+
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
107
+ riscv_ctr_clear(env);
80
+ if (tlb_size != NULL) {
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
82
+ *tlb_size = tlb_size_pmp;
83
+ }
84
+ }
85
+
86
+ return TRANSLATE_SUCCESS;
87
+}
108
+}
88
+
109
+
89
/* get_physical_address - get the physical address for this virtual address
110
void helper_wfi(CPURISCVState *env)
90
*
111
{
91
* Do a page table walk to obtain the physical address corresponding to a
112
CPUState *cs = env_cpu(env);
92
@@ -XXX,XX +XXX,XX @@ restart:
113
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
93
pte_addr = base + idx * ptesize;
94
}
95
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
99
+ int pmp_prot;
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
101
+ sizeof(target_ulong),
102
+ MMU_DATA_LOAD, PRV_S);
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
104
return TRANSLATE_PMP_FAIL;
105
}
106
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
#ifndef CONFIG_USER_ONLY
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
154
}
155
+
156
if (ret == TRANSLATE_PMP_FAIL) {
157
pmp_violation = true;
158
}
159
160
if (ret == TRANSLATE_SUCCESS) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
163
- prot, mmu_idx, tlb_size);
164
- } else {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
174
index XXXXXXX..XXXXXXX 100644
114
index XXXXXXX..XXXXXXX 100644
175
--- a/target/riscv/pmp.c
115
--- a/target/riscv/insn_trans/trans_privileged.c.inc
176
+++ b/target/riscv/pmp.c
116
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
117
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
178
return result;
118
return true;
179
}
119
}
180
120
181
+/*
121
+static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a)
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
183
+ */
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
186
+ target_ulong mode)
187
+{
122
+{
188
+ bool ret;
123
+#ifndef CONFIG_USER_ONLY
189
+
124
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
125
+ gen_helper_ctr_clear(tcg_env);
191
+ /*
126
+ return true;
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
194
+ */
195
+ ret = true;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
197
+ } else {
198
+ /*
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
200
+ * but there are rules. We've checked for no rule earlier in this
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
127
+ }
206
+
128
+#endif
207
+ return ret;
129
+ return false;
208
+}
130
+}
209
+
131
+
210
132
static bool trans_uret(DisasContext *ctx, arg_uret *a)
211
/*
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
215
*/
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
219
+ target_ulong mode)
220
{
133
{
221
int i = 0;
222
int ret = -1;
223
int pmp_size = 0;
224
target_ulong s = 0;
225
target_ulong e = 0;
226
- pmp_priv_t allowed_privs = 0;
227
228
/* Short cut if no rules */
229
if (0 == pmp_get_num_rules(env)) {
230
- return (env->priv == PRV_M) ? true : false;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
232
+ allowed_privs, mode);
233
}
234
235
if (size == 0) {
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
237
* check
238
*/
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
245
}
246
247
- if ((privs & allowed_privs) == privs) {
248
- ret = 1;
249
- break;
250
- } else {
251
- ret = 0;
252
- break;
253
- }
254
+ ret = ((privs & *allowed_privs) == privs);
255
+ break;
256
}
257
}
258
259
/* No rule matched */
260
if (ret == -1) {
261
- if (mode == PRV_M) {
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
263
- * M-Mode access, the access succeeds */
264
- } else {
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
266
- * match a rule, but there are rules. We've checked for
267
- * no rule earlier in this function. */
268
- }
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
270
+ allowed_privs, mode);
271
}
272
273
return ret == 1 ? true : false;
274
}
275
276
-
277
/*
278
* Handle a write to a pmpcfg CSP
279
*/
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
281
282
return false;
134
return false;
283
}
284
+
285
+/*
286
+ * Convert PMP privilege to TLB page privilege.
287
+ */
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
289
+{
290
+ int prot = 0;
291
+
292
+ if (pmp_priv & PMP_READ) {
293
+ prot |= PAGE_READ;
294
+ }
295
+ if (pmp_priv & PMP_WRITE) {
296
+ prot |= PAGE_WRITE;
297
+ }
298
+ if (pmp_priv & PMP_EXEC) {
299
+ prot |= PAGE_EXEC;
300
+ }
301
+
302
+ return prot;
303
+}
304
--
135
--
305
2.30.1
136
2.48.1
306
307
diff view generated by jsdifflib
New patch
[PULL 27/59] target/riscv: machine: Add Control Transfer Record state description
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
1
2
3
Add a subsection to machine.c to migrate CTR CSR state
4
5
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-ID: <20250205-b4-ctr_upstream_v6-v6-6-439d8e06c8ef@rivosinc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
target/riscv/machine.c | 25 +++++++++++++++++++++++++
11
1 file changed, 25 insertions(+)
12
13
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/machine.c
16
+++ b/target/riscv/machine.c
17
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_envcfg = {
18
}
19
};
20
21
+static bool ctr_needed(void *opaque)
22
+{
23
+ RISCVCPU *cpu = opaque;
24
+
25
+ return cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr;
26
+}
27
+
28
+static const VMStateDescription vmstate_ctr = {
29
+ .name = "cpu/ctr",
30
+ .version_id = 1,
31
+ .minimum_version_id = 1,
32
+ .needed = ctr_needed,
33
+ .fields = (const VMStateField[]) {
34
+ VMSTATE_UINT64(env.mctrctl, RISCVCPU),
35
+ VMSTATE_UINT32(env.sctrdepth, RISCVCPU),
36
+ VMSTATE_UINT32(env.sctrstatus, RISCVCPU),
37
+ VMSTATE_UINT64(env.vsctrctl, RISCVCPU),
38
+ VMSTATE_UINT64_ARRAY(env.ctr_src, RISCVCPU, 16 << SCTRDEPTH_MAX),
39
+ VMSTATE_UINT64_ARRAY(env.ctr_dst, RISCVCPU, 16 << SCTRDEPTH_MAX),
40
+ VMSTATE_UINT64_ARRAY(env.ctr_data, RISCVCPU, 16 << SCTRDEPTH_MAX),
41
+ VMSTATE_END_OF_LIST()
42
+ }
43
+};
44
+
45
static bool pmu_needed(void *opaque)
46
{
47
RISCVCPU *cpu = opaque;
48
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
49
&vmstate_jvt,
50
&vmstate_elp,
51
&vmstate_ssp,
52
+ &vmstate_ctr,
53
NULL
54
}
55
};
56
--
57
2.48.1
diff view generated by jsdifflib
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
[PULL 28/59] target/riscv: log guest errors when reserved bits are set in PTEs
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: julia <midnight@trainwit.ch>
2
2
3
The current condition for the use of background registers only
3
For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
4
considers the hypervisor load and store instructions,
4
would silently treat this akin to an unmapped page (as required by the
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
5
RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
6
CVA6) which leads to an apparent QEMU bug.
6
7
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
Instead, log a guest error so that in future, incorrectly set up page
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
tables can be debugged without bisecting QEMU.
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
10
11
Signed-off-by: julia <midnight@trainwit.ch>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-ID: <20250203061852.2931556-1-midnight@trainwit.ch>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
target/riscv/cpu_helper.c | 2 +-
16
target/riscv/cpu_helper.c | 27 ++++++++++++++++++++++++++-
13
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 26 insertions(+), 1 deletion(-)
14
18
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
21
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
22
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
23
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
20
* was called. Background registers will be used if the guest has
24
ppn = pte >> PTE_PPN_SHIFT;
21
* forced a two stage translation to be on (in HS or M mode).
25
} else {
22
*/
26
if (pte & PTE_RESERVED) {
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
27
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits set in PTE: "
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
28
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
25
use_background = true;
29
+ __func__, pte_addr, pte);
30
return TRANSLATE_FAIL;
31
}
32
33
if (!pbmte && (pte & PTE_PBMT)) {
34
+ /* Reserved without Svpbmt. */
35
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, "
36
+ "and Svpbmt extension is disabled: "
37
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
38
+ __func__, pte_addr, pte);
39
return TRANSLATE_FAIL;
40
}
41
42
if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
43
+ /* Reserved without Svnapot extension */
44
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: N bit set in PTE, "
45
+ "and Svnapot extension is disabled: "
46
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
47
+ __func__, pte_addr, pte);
48
return TRANSLATE_FAIL;
49
}
50
51
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
52
/* Invalid PTE */
53
return TRANSLATE_FAIL;
54
}
55
+
56
if (pte & (PTE_R | PTE_W | PTE_X)) {
57
goto leaf;
58
}
59
60
- /* Inner PTE, continue walking */
61
if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
62
+ /* D, A, and U bits are reserved in non-leaf/inner PTEs */
63
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: D, A, or U bits set in non-leaf PTE: "
64
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
65
+ __func__, pte_addr, pte);
66
return TRANSLATE_FAIL;
67
}
68
+ /* Inner PTE, continue walking */
69
base = ppn << PGSHIFT;
26
}
70
}
27
71
72
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
73
leaf:
74
if (ppn & ((1ULL << ptshift) - 1)) {
75
/* Misaligned PPN */
76
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: PPN bits in PTE is misaligned: "
77
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
78
+ __func__, pte_addr, pte);
79
return TRANSLATE_FAIL;
80
}
81
if (!pbmte && (pte & PTE_PBMT)) {
82
/* Reserved without Svpbmt. */
83
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, "
84
+ "and Svpbmt extension is disabled: "
85
+ "addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
86
+ __func__, pte_addr, pte);
87
return TRANSLATE_FAIL;
88
}
89
28
--
90
--
29
2.30.1
91
2.48.1
30
31
diff view generated by jsdifflib
New patch
[PULL 29/59] disas/riscv: Fix minor whitespace issues
1
From: Rob Bradford <rbradford@rivosinc.com>
1
2
3
Some extra spaces made into into the RISC-V opcode data table.
4
5
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-ID: <20250206153410.236636-2-rbradford@rivosinc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
disas/riscv.c | 12 ++++++------
11
1 file changed, 6 insertions(+), 6 deletions(-)
12
13
diff --git a/disas/riscv.c b/disas/riscv.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/disas/riscv.c
16
+++ b/disas/riscv.c
17
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data rvi_opcode_data[] = {
18
{ "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
19
{ "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
20
{ "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
21
- { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
22
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
23
{ "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
24
{ "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
25
{ "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
26
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data rvi_opcode_data[] = {
27
{ "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
28
{ "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
29
{ "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
30
- { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
31
- { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
32
- { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
33
- { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
34
- { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
35
+ { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
36
+ { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
37
+ { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
38
+ { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
39
+ { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
40
{ "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
41
{ "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
42
{ "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
43
--
44
2.48.1
diff view generated by jsdifflib
New patch
[PULL 30/59] disas/riscv: Add missing Sdtrig CSRs
1
From: Rob Bradford <rbradford@rivosinc.com>
1
2
3
This reflects the latest frozen version of the RISC-V Debug
4
specification (1.0.0-rc4) which includes the Sdtrig extension.
5
6
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-ID: <20250206153410.236636-3-rbradford@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
disas/riscv.c | 4 +++-
12
1 file changed, 3 insertions(+), 1 deletion(-)
13
14
diff --git a/disas/riscv.c b/disas/riscv.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/disas/riscv.c
17
+++ b/disas/riscv.c
18
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
19
case 0x07a1: return "tdata1";
20
case 0x07a2: return "tdata2";
21
case 0x07a3: return "tdata3";
22
+ case 0x07a4: return "tinfo";
23
case 0x07b0: return "dcsr";
24
case 0x07b1: return "dpc";
25
- case 0x07b2: return "dscratch";
26
+ case 0x07b2: return "dscratch0";
27
+ case 0x07b3: return "dscratch1";
28
case 0x0b00: return "mcycle";
29
case 0x0b01: return "mtime";
30
case 0x0b02: return "minstret";
31
--
32
2.48.1
diff view generated by jsdifflib
New patch
[PULL 31/59] target/riscv: Fix the hpmevent mask
1
From: Atish Patra <atishp@rivosinc.com>
1
2
3
As per the latest privilege specification v1.13[1], the sscofpmf
4
only reserves first 8 bits of hpmeventX. Update the corresponding
5
masks accordingly.
6
7
[1]https://github.com/riscv/riscv-isa-manual/issues/1578
8
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Acked-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-ID: <20250206-pmu_minor_fixes-v2-1-1bb0f4aeb8b4@rivosinc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu_bits.h | 5 ++---
16
1 file changed, 2 insertions(+), 3 deletions(-)
17
18
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu_bits.h
21
+++ b/target/riscv/cpu_bits.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum CTRType {
23
MHPMEVENTH_BIT_VSINH | \
24
MHPMEVENTH_BIT_VUINH)
25
26
-#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
27
-#define MHPMEVENT_IDX_MASK 0xFFFFF
28
-#define MHPMEVENT_SSCOF_RESVD 16
29
+#define MHPMEVENT_SSCOF_MASK MAKE_64BIT_MASK(63, 56)
30
+#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK)
31
32
/* RISC-V-specific interrupt pending bits. */
33
#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
34
--
35
2.48.1
diff view generated by jsdifflib
New patch
[PULL 32/59] target/riscv: Mask out upper sscofpmf bits during validation
1
From: Atish Patra <atishp@rivosinc.com>
1
2
3
As per the ISA definition, the upper 8 bits in hpmevent are defined
4
by Sscofpmf for privilege mode filtering and overflow bits while the
5
lower 56 bits are desginated for platform specific hpmevent values.
6
For the reset case, mhpmevent value should have zero in lower 56 bits.
7
Software may set the OF bit to indicate disable interrupt.
8
9
Ensure that correct value is checked after masking while clearing the
10
event encodings.
11
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Atish Patra <atishp@rivosinc.com>
15
Message-ID: <20250206-pmu_minor_fixes-v2-2-1bb0f4aeb8b4@rivosinc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/pmu.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/pmu.c
24
+++ b/target/riscv/pmu.c
25
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
26
* Expected mhpmevent value is zero for reset case. Remove the current
27
* mapping.
28
*/
29
- if (!value) {
30
+ if (!(value & MHPMEVENT_IDX_MASK)) {
31
g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
32
pmu_remove_event_map,
33
GUINT_TO_POINTER(ctr_idx));
34
--
35
2.48.1
diff view generated by jsdifflib
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
[PULL 33/59] target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
3
As raised by Richard Henderson, these warnings are displayed in user
4
further compressed instruction decoding. However, prior to this change,
4
only as well. Since they aren't really useful for the end-user, remove
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
5
them and add a "TODO" note in the leading comments.
6
fails to decode the instruction. This means that we skipped illegal
7
compressed instructions instead of raising an illegal instruction
8
exception.
9
6
10
Instead of patching decode_RV32_64C(), we can just remove it,
7
Signed-off-by: Clément Léger <cleger@rivosinc.com>
11
as it is dead code since f330433b363 anyway.
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
9
Message-ID: <20250213145640.117275-1-cleger@rivosinc.com>
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
11
---
19
target/riscv/translate.c | 179 +--------------------------------------
12
target/riscv/tcg/tcg-cpu.c | 8 +++-----
20
1 file changed, 1 insertion(+), 178 deletions(-)
13
1 file changed, 3 insertions(+), 5 deletions(-)
21
14
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
15
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
17
--- a/target/riscv/tcg/tcg-cpu.c
25
+++ b/target/riscv/translate.c
18
+++ b/target/riscv/tcg/tcg-cpu.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
19
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
27
CPUState *cs;
20
}
28
} DisasContext;
21
29
22
/*
30
-#ifdef TARGET_RISCV64
23
- * ext_smrnmi requires OpenSBI changes that our current
31
-/* convert riscv funct3 to qemu memop for load/store */
24
+ * TODO: ext_smrnmi requires OpenSBI changes that our current
32
-static const int tcg_memop_lookup[8] = {
25
* image does not have. Disable it for now.
33
- [0 ... 7] = -1,
26
*/
34
- [0] = MO_SB,
27
if (cpu->cfg.ext_smrnmi) {
35
- [1] = MO_TESW,
28
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false);
36
- [2] = MO_TESL,
29
- qemu_log("Smrnmi is disabled in the 'max' type CPU\n");
37
- [3] = MO_TEQ,
30
}
38
- [4] = MO_UB,
31
39
- [5] = MO_TEUW,
32
/*
40
- [6] = MO_TEUL,
33
- * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to
41
-};
34
- * avoid generating a double trap. OpenSBI does not currently support it,
42
-#endif
35
+ * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup
43
-
36
+ * to avoid generating a double trap. OpenSBI does not currently support it,
44
#ifdef TARGET_RISCV64
37
* disable it for now.
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
38
*/
46
#else
39
if (cpu->cfg.ext_smdbltrp) {
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
40
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false);
48
ctx->base.is_jmp = DISAS_NORETURN;
41
- qemu_log("Smdbltrp is disabled in the 'max' type CPU\n");
42
}
49
}
43
}
50
44
51
-#ifdef TARGET_RISCV64
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
53
- target_long imm)
54
-{
55
- TCGv t0 = tcg_temp_new();
56
- TCGv t1 = tcg_temp_new();
57
- gen_get_gpr(t0, rs1);
58
- tcg_gen_addi_tl(t0, t0, imm);
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
60
-
61
- if (memop < 0) {
62
- gen_exception_illegal(ctx);
63
- return;
64
- }
65
-
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
67
- gen_set_gpr(rd, t1);
68
- tcg_temp_free(t0);
69
- tcg_temp_free(t1);
70
-}
71
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
73
- target_long imm)
74
-{
75
- TCGv t0 = tcg_temp_new();
76
- TCGv dat = tcg_temp_new();
77
- gen_get_gpr(t0, rs1);
78
- tcg_gen_addi_tl(t0, t0, imm);
79
- gen_get_gpr(dat, rs2);
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
81
-
82
- if (memop < 0) {
83
- gen_exception_illegal(ctx);
84
- return;
85
- }
86
-
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
88
- tcg_temp_free(t0);
89
- tcg_temp_free(dat);
90
-}
91
-#endif
92
-
93
#ifndef CONFIG_USER_ONLY
94
/* The states of mstatus_fs are:
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
98
#endif
99
100
-#if !defined(TARGET_RISCV64)
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
102
- int rs1, target_long imm)
103
-{
104
- TCGv t0;
105
-
106
- if (ctx->mstatus_fs == 0) {
107
- gen_exception_illegal(ctx);
108
- return;
109
- }
110
-
111
- t0 = tcg_temp_new();
112
- gen_get_gpr(t0, rs1);
113
- tcg_gen_addi_tl(t0, t0, imm);
114
-
115
- switch (opc) {
116
- case OPC_RISC_FLW:
117
- if (!has_ext(ctx, RVF)) {
118
- goto do_illegal;
119
- }
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
123
- break;
124
- case OPC_RISC_FLD:
125
- if (!has_ext(ctx, RVD)) {
126
- goto do_illegal;
127
- }
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
129
- break;
130
- do_illegal:
131
- default:
132
- gen_exception_illegal(ctx);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
139
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
141
- int rs2, target_long imm)
142
-{
143
- TCGv t0;
144
-
145
- if (ctx->mstatus_fs == 0) {
146
- gen_exception_illegal(ctx);
147
- return;
148
- }
149
-
150
- t0 = tcg_temp_new();
151
- gen_get_gpr(t0, rs1);
152
- tcg_gen_addi_tl(t0, t0, imm);
153
-
154
- switch (opc) {
155
- case OPC_RISC_FSW:
156
- if (!has_ext(ctx, RVF)) {
157
- goto do_illegal;
158
- }
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
179
TCGv_i32 t0;
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
181
tcg_temp_free_i32(t0);
182
}
183
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
185
-{
186
- uint8_t funct3 = extract16(opcode, 13, 3);
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
188
- uint8_t rs1s = GET_C_RS1S(opcode);
189
-
190
- switch (funct3) {
191
- case 3:
192
-#if defined(TARGET_RISCV64)
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
195
- GET_C_LD_IMM(opcode));
196
-#else
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
199
- GET_C_LW_IMM(opcode));
200
-#endif
201
- break;
202
- case 7:
203
-#if defined(TARGET_RISCV64)
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
206
- GET_C_LD_IMM(opcode));
207
-#else
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
210
- GET_C_LW_IMM(opcode));
211
-#endif
212
- break;
213
- }
214
-}
215
-
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
229
return nf + 1;
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
231
} else {
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
233
if (!decode_insn16(ctx, opcode)) {
234
- /* fall back to old decoder */
235
- decode_RV32_64C(ctx, opcode);
236
+ gen_exception_illegal(ctx);
237
}
238
}
239
} else {
240
--
45
--
241
2.30.1
46
2.48.1
242
47
243
48
diff view generated by jsdifflib
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
[PULL 34/59] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
2
2
3
The previous implementation was broken in many ways:
3
CTR entries are accessed using ctrsource, ctrtarget and ctrdata
4
- Used mideleg instead of hideleg to mask accesses
4
registers using smcsrind/sscsrind extension. This commits extends
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
5
the csrind extension to support CTR registers.
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
6
7
7
ctrsource is accessible through xireg CSR, ctrtarget is accessible
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
through xireg1 and ctrdata is accessible through xireg2 CSR.
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
10
CTR supports maximum depth of 256 entries which are accessed using
11
xiselect range 0x200 to 0x2ff.
12
13
This commits also adds properties to enable CTR extension. CTR can be
14
enabled using smctr=true and ssctr=true now.
15
16
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
17
Acked-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20250212-b4-ctr_upstream_v6-v7-1-4e8159ea33bf@rivosinc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
20
---
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
21
target/riscv/cpu.c | 26 ++++++-
14
1 file changed, 34 insertions(+), 34 deletions(-)
22
target/riscv/csr.c | 150 ++++++++++++++++++++++++++++++++++++-
15
23
target/riscv/tcg/tcg-cpu.c | 11 +++
24
3 files changed, 185 insertions(+), 2 deletions(-)
25
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.c
29
+++ b/target/riscv/cpu.c
30
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
31
ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
32
ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
33
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
34
+ ISA_EXT_DATA_ENTRY(smctr, PRIV_VERSION_1_12_0, ext_smctr),
35
+ ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr),
36
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
37
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
38
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
39
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
40
MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false),
41
MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false),
42
MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false),
43
+ MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false),
44
+ MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false),
45
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
46
MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
47
MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
48
@@ -XXX,XX +XXX,XX @@ static RISCVCPUImpliedExtsRule SSPM_IMPLIED = {
49
},
50
};
51
52
+static RISCVCPUImpliedExtsRule SMCTR_IMPLIED = {
53
+ .ext = CPU_CFG_OFFSET(ext_smctr),
54
+ .implied_misa_exts = RVS,
55
+ .implied_multi_exts = {
56
+ CPU_CFG_OFFSET(ext_sscsrind),
57
+
58
+ RISCV_IMPLIED_EXTS_RULE_END
59
+ },
60
+};
61
+
62
+static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
63
+ .ext = CPU_CFG_OFFSET(ext_ssctr),
64
+ .implied_misa_exts = RVS,
65
+ .implied_multi_exts = {
66
+ CPU_CFG_OFFSET(ext_sscsrind),
67
+
68
+ RISCV_IMPLIED_EXTS_RULE_END
69
+ },
70
+};
71
+
72
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
73
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
74
&RVM_IMPLIED, &RVV_IMPLIED, NULL
75
@@ -XXX,XX +XXX,XX @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
76
&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
77
&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
78
&ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
79
- &SUPM_IMPLIED, &SSPM_IMPLIED,
80
+ &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED,
81
NULL
82
};
83
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
84
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
86
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
87
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
88
@@ -XXX,XX +XXX,XX @@ static bool xiselect_cd_range(target_ulong isel)
21
return write_mstatus(env, CSR_MSTATUS, newval);
89
return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
22
}
90
}
23
91
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
92
+static bool xiselect_ctr_range(int csrno, target_ulong isel)
25
+{
93
+{
26
+ /* Shift the VS bits to their S bit location in vsie */
94
+ /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
95
+ return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST &&
28
+ return 0;
96
+ csrno < CSR_MIREG;
29
+}
97
+}
30
+
98
+
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
99
static int rmw_iprio(target_ulong xlen,
32
{
100
target_ulong iselect, uint8_t *iprio,
33
if (riscv_cpu_virt_enabled(env)) {
101
target_ulong *val, target_ulong new_val,
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
102
@@ -XXX,XX +XXX,XX @@ static int rmw_iprio(target_ulong xlen,
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
36
+ read_vsie(env, CSR_VSIE, val);
37
} else {
38
*val = env->mie & env->mideleg;
39
}
40
return 0;
103
return 0;
41
}
104
}
42
105
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
106
+static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
107
+ target_ulong new_val, target_ulong wr_mask)
108
+{
109
+ /*
110
+ * CTR arrays are treated as circular buffers and TOS always points to next
111
+ * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
112
+ * 0 is always the latest one, traversal is a bit different here. See the
113
+ * below example.
114
+ *
115
+ * Depth = 16.
116
+ *
117
+ * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
118
+ * TOS H
119
+ * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
120
+ */
121
+ const uint64_t entry = isel - CTR_ENTRIES_FIRST;
122
+ const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
123
+ uint64_t idx;
124
+
125
+ /* Entry greater than depth-1 is read-only zero */
126
+ if (entry >= depth) {
127
+ if (val) {
128
+ *val = 0;
129
+ }
130
+ return 0;
131
+ }
132
+
133
+ idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
134
+ idx = (idx - entry - 1) & (depth - 1);
135
+
136
+ if (val) {
137
+ *val = env->ctr_src[idx];
138
+ }
139
+
140
+ env->ctr_src[idx] = (env->ctr_src[idx] & ~wr_mask) | (new_val & wr_mask);
141
+
142
+ return 0;
143
+}
144
+
145
+static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
146
+ target_ulong new_val, target_ulong wr_mask)
147
+{
148
+ /*
149
+ * CTR arrays are treated as circular buffers and TOS always points to next
150
+ * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
151
+ * 0 is always the latest one, traversal is a bit different here. See the
152
+ * below example.
153
+ *
154
+ * Depth = 16.
155
+ *
156
+ * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
157
+ * head H
158
+ * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
159
+ */
160
+ const uint64_t entry = isel - CTR_ENTRIES_FIRST;
161
+ const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
162
+ uint64_t idx;
163
+
164
+ /* Entry greater than depth-1 is read-only zero */
165
+ if (entry >= depth) {
166
+ if (val) {
167
+ *val = 0;
168
+ }
169
+ return 0;
170
+ }
171
+
172
+ idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
173
+ idx = (idx - entry - 1) & (depth - 1);
174
+
175
+ if (val) {
176
+ *val = env->ctr_dst[idx];
177
+ }
178
+
179
+ env->ctr_dst[idx] = (env->ctr_dst[idx] & ~wr_mask) | (new_val & wr_mask);
180
+
181
+ return 0;
182
+}
183
+
184
+static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
185
+ target_ulong new_val, target_ulong wr_mask)
186
+{
187
+ /*
188
+ * CTR arrays are treated as circular buffers and TOS always points to next
189
+ * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
190
+ * 0 is always the latest one, traversal is a bit different here. See the
191
+ * below example.
192
+ *
193
+ * Depth = 16.
194
+ *
195
+ * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
196
+ * head H
197
+ * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
198
+ */
199
+ const uint64_t entry = isel - CTR_ENTRIES_FIRST;
200
+ const uint64_t mask = wr_mask & CTRDATA_MASK;
201
+ const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
202
+ uint64_t idx;
203
+
204
+ /* Entry greater than depth-1 is read-only zero */
205
+ if (entry >= depth) {
206
+ if (val) {
207
+ *val = 0;
208
+ }
209
+ return 0;
210
+ }
211
+
212
+ idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
213
+ idx = (idx - entry - 1) & (depth - 1);
214
+
215
+ if (val) {
216
+ *val = env->ctr_data[idx];
217
+ }
218
+
219
+ env->ctr_data[idx] = (env->ctr_data[idx] & ~mask) | (new_val & mask);
220
+
221
+ return 0;
222
+}
223
+
224
static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
225
target_ulong isel, target_ulong *val,
226
target_ulong new_val, target_ulong wr_mask)
227
@@ -XXX,XX +XXX,XX @@ done:
228
return ret;
229
}
230
231
+static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
232
+ target_ulong isel, target_ulong *val,
233
+ target_ulong new_val, target_ulong wr_mask)
234
+{
235
+ if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) {
236
+ return -EINVAL;
237
+ }
238
+
239
+ if (csrno == CSR_SIREG || csrno == CSR_VSIREG) {
240
+ return rmw_ctrsource(env, isel, val, new_val, wr_mask);
241
+ } else if (csrno == CSR_SIREG2 || csrno == CSR_VSIREG2) {
242
+ return rmw_ctrtarget(env, isel, val, new_val, wr_mask);
243
+ } else if (csrno == CSR_SIREG3 || csrno == CSR_VSIREG3) {
244
+ return rmw_ctrdata(env, isel, val, new_val, wr_mask);
245
+ } else if (val) {
246
+ *val = 0;
247
+ }
248
+
249
+ return 0;
250
+}
251
+
252
/*
253
* rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
254
*
255
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
256
target_ulong isel, target_ulong *val,
257
target_ulong new_val, target_ulong wr_mask)
45
{
258
{
46
- target_ulong newval;
259
- int ret = -EINVAL;
47
+ /* Shift the S bits to their VS bit location in mie */
260
bool virt = csrno == CSR_VSIREG ? true : false;
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
261
+ int ret = -EINVAL;
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
262
50
+ return write_mie(env, CSR_MIE, newval);
263
if (xiselect_cd_range(isel)) {
51
+}
264
ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
52
265
+ } else if (xiselect_ctr_range(csrno, isel)) {
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
266
+ ret = rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask);
54
+{
55
if (riscv_cpu_virt_enabled(env)) {
56
- /* Shift the guests S bits to VS */
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
58
- ((val << 1) & VS_MODE_INTERRUPTS);
59
+ write_vsie(env, CSR_VSIE, val);
60
} else {
267
} else {
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
268
/*
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
269
* As per the specification, access to unimplented region is undefined
63
+ (val & S_MODE_INTERRUPTS);
270
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
64
+ write_mie(env, CSR_MIE, newval);
271
index XXXXXXX..XXXXXXX 100644
272
--- a/target/riscv/tcg/tcg-cpu.c
273
+++ b/target/riscv/tcg/tcg-cpu.c
274
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
275
return;
65
}
276
}
66
277
67
- return write_mie(env, CSR_MIE, newval);
278
+ if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) &&
68
+ return 0;
279
+ (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) {
69
}
280
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) ||
70
281
+ cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) {
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
282
+ error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind");
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
283
+ return;
73
return 0;
284
+ }
74
}
285
+ cpu->cfg.ext_smctr = false;
75
286
+ cpu->cfg.ext_ssctr = false;
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
287
+ }
77
+ target_ulong new_value, target_ulong write_mask)
288
+
78
+{
289
/*
79
+ /* Shift the S bits to their VS bit location in mip */
290
* Disable isa extensions based on priv spec after we
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
291
* validated and set everything we need.
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
86
+}
87
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
89
target_ulong new_value, target_ulong write_mask)
90
{
91
int ret;
92
93
if (riscv_cpu_virt_enabled(env)) {
94
- /* Shift the new values to line up with the VS bits */
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
97
- ret &= vsip_writable_mask;
98
- ret >>= 1;
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
100
} else {
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
102
write_mask & env->mideleg & sip_writable_mask);
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
104
return 0;
105
}
106
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
108
- target_ulong new_value, target_ulong write_mask)
109
-{
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
111
- write_mask & env->mideleg & vsip_writable_mask);
112
- return ret;
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
129
*val = env->vstvec;
130
--
292
--
131
2.30.1
293
2.48.1
132
133
diff view generated by jsdifflib
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
[PULL 35/59] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry
1
From: Jim Shu <cwshu@andestech.com>
1
From: Rob Bradford <rbradford@rivosinc.com>
2
2
3
If PMP permission of any address has been changed by updating PMP entry,
3
When running in TOR mode (Top of Range) the next PMP entry controls
4
flush all TLB pages to prevent from getting old permission.
4
whether the entry is locked. However simply checking if the PMP_LOCK bit
5
is set is not sufficient with the Smepmp extension which now provides a
6
bit (mseccfg.RLB (Rule Lock Bypass)) to disregard the lock bits. In
7
order to respect this bit use the convenience pmp_is_locked() function
8
rather than directly checking PMP_LOCK since this function checks
9
mseccfg.RLB.
5
10
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
11
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-ID: <20250210153713.343626-1-rbradford@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/pmp.c | 4 ++++
17
target/riscv/pmp.c | 2 +-
12
1 file changed, 4 insertions(+)
18
1 file changed, 1 insertion(+), 1 deletion(-)
13
19
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
20
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/pmp.c
22
--- a/target/riscv/pmp.c
17
+++ b/target/riscv/pmp.c
23
+++ b/target/riscv/pmp.c
18
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
19
#include "qapi/error.h"
25
uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
20
#include "cpu.h"
26
is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg);
21
#include "trace.h"
27
22
+#include "exec/exec-all.h"
28
- if (pmp_cfg & PMP_LOCK && is_next_cfg_tor) {
23
29
+ if (pmp_is_locked(env, addr_index + 1) && is_next_cfg_tor) {
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
30
qemu_log_mask(LOG_GUEST_ERROR,
25
uint8_t val);
31
"ignoring pmpaddr write - pmpcfg + 1 locked\n");
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
32
return;
27
cfg_val = (val >> 8 * i) & 0xff;
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
29
}
30
+
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
32
+ tlb_flush(env_cpu(env));
33
}
34
35
36
--
33
--
37
2.30.1
34
2.48.1
38
39
diff view generated by jsdifflib
New patch
[PULL 36/59] linux-headers: Update to Linux v6.14-rc3
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Update headers to retrieve the latest KVM caps for RISC-V.
4
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Message-ID: <20250221153758.652078-2-dbarboza@ventanamicro.com>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
include/standard-headers/linux/ethtool.h | 4 +
10
include/standard-headers/linux/fuse.h | 76 ++++++++++++++++++-
11
.../linux/input-event-codes.h | 1 +
12
include/standard-headers/linux/pci_regs.h | 16 ++--
13
include/standard-headers/linux/virtio_pci.h | 14 ++++
14
linux-headers/asm-arm64/kvm.h | 3 -
15
linux-headers/asm-loongarch/kvm_para.h | 1 +
16
linux-headers/asm-riscv/kvm.h | 7 +-
17
linux-headers/asm-x86/kvm.h | 1 +
18
linux-headers/linux/iommufd.h | 35 ++++++---
19
linux-headers/linux/kvm.h | 8 +-
20
linux-headers/linux/stddef.h | 13 +++-
21
linux-headers/linux/vduse.h | 2 +-
22
13 files changed, 146 insertions(+), 35 deletions(-)
23
24
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/standard-headers/linux/ethtool.h
27
+++ b/include/standard-headers/linux/ethtool.h
28
@@ -XXX,XX +XXX,XX @@ enum ethtool_link_ext_substate_module {
29
* @ETH_SS_STATS_ETH_MAC: names of IEEE 802.3 MAC statistics
30
* @ETH_SS_STATS_ETH_CTRL: names of IEEE 802.3 MAC Control statistics
31
* @ETH_SS_STATS_RMON: names of RMON statistics
32
+ * @ETH_SS_STATS_PHY: names of PHY(dev) statistics
33
+ * @ETH_SS_TS_FLAGS: hardware timestamping flags
34
*
35
* @ETH_SS_COUNT: number of defined string sets
36
*/
37
@@ -XXX,XX +XXX,XX @@ enum ethtool_stringset {
38
    ETH_SS_STATS_ETH_MAC,
39
    ETH_SS_STATS_ETH_CTRL,
40
    ETH_SS_STATS_RMON,
41
+    ETH_SS_STATS_PHY,
42
+    ETH_SS_TS_FLAGS,
43
44
    /* add new constants above here */
45
    ETH_SS_COUNT
46
diff --git a/include/standard-headers/linux/fuse.h b/include/standard-headers/linux/fuse.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/standard-headers/linux/fuse.h
49
+++ b/include/standard-headers/linux/fuse.h
50
@@ -XXX,XX +XXX,XX @@
51
*
52
* 7.41
53
* - add FUSE_ALLOW_IDMAP
54
+ * 7.42
55
+ * - Add FUSE_OVER_IO_URING and all other io-uring related flags and data
56
+ * structures:
57
+ * - struct fuse_uring_ent_in_out
58
+ * - struct fuse_uring_req_header
59
+ * - struct fuse_uring_cmd_req
60
+ * - FUSE_URING_IN_OUT_HEADER_SZ
61
+ * - FUSE_URING_OP_IN_OUT_SZ
62
+ * - enum fuse_uring_cmd
63
*/
64
65
#ifndef _LINUX_FUSE_H
66
@@ -XXX,XX +XXX,XX @@
67
#define FUSE_KERNEL_VERSION 7
68
69
/** Minor version number of this interface */
70
-#define FUSE_KERNEL_MINOR_VERSION 41
71
+#define FUSE_KERNEL_MINOR_VERSION 42
72
73
/** The node ID of the root inode */
74
#define FUSE_ROOT_ID 1
75
@@ -XXX,XX +XXX,XX @@ struct fuse_file_lock {
76
* FUSE_HAS_RESEND: kernel supports resending pending requests, and the high bit
77
*         of the request ID indicates resend requests
78
* FUSE_ALLOW_IDMAP: allow creation of idmapped mounts
79
+ * FUSE_OVER_IO_URING: Indicate that client supports io-uring
80
*/
81
#define FUSE_ASYNC_READ        (1 << 0)
82
#define FUSE_POSIX_LOCKS    (1 << 1)
83
@@ -XXX,XX +XXX,XX @@ struct fuse_file_lock {
84
/* Obsolete alias for FUSE_DIRECT_IO_ALLOW_MMAP */
85
#define FUSE_DIRECT_IO_RELAX    FUSE_DIRECT_IO_ALLOW_MMAP
86
#define FUSE_ALLOW_IDMAP    (1ULL << 40)
87
+#define FUSE_OVER_IO_URING    (1ULL << 41)
88
89
/**
90
* CUSE INIT request/reply flags
91
@@ -XXX,XX +XXX,XX @@ struct fuse_supp_groups {
92
    uint32_t    groups[];
93
};
94
95
+/**
96
+ * Size of the ring buffer header
97
+ */
98
+#define FUSE_URING_IN_OUT_HEADER_SZ 128
99
+#define FUSE_URING_OP_IN_OUT_SZ 128
100
+
101
+/* Used as part of the fuse_uring_req_header */
102
+struct fuse_uring_ent_in_out {
103
+    uint64_t flags;
104
+
105
+    /*
106
+     * commit ID to be used in a reply to a ring request (see also
107
+     * struct fuse_uring_cmd_req)
108
+     */
109
+    uint64_t commit_id;
110
+
111
+    /* size of user payload buffer */
112
+    uint32_t payload_sz;
113
+    uint32_t padding;
114
+
115
+    uint64_t reserved;
116
+};
117
+
118
+/**
119
+ * Header for all fuse-io-uring requests
120
+ */
121
+struct fuse_uring_req_header {
122
+    /* struct fuse_in_header / struct fuse_out_header */
123
+    char in_out[FUSE_URING_IN_OUT_HEADER_SZ];
124
+
125
+    /* per op code header */
126
+    char op_in[FUSE_URING_OP_IN_OUT_SZ];
127
+
128
+    struct fuse_uring_ent_in_out ring_ent_in_out;
129
+};
130
+
131
+/**
132
+ * sqe commands to the kernel
133
+ */
134
+enum fuse_uring_cmd {
135
+    FUSE_IO_URING_CMD_INVALID = 0,
136
+
137
+    /* register the request buffer and fetch a fuse request */
138
+    FUSE_IO_URING_CMD_REGISTER = 1,
139
+
140
+    /* commit fuse request result and fetch next request */
141
+    FUSE_IO_URING_CMD_COMMIT_AND_FETCH = 2,
142
+};
143
+
144
+/**
145
+ * In the 80B command area of the SQE.
146
+ */
147
+struct fuse_uring_cmd_req {
148
+    uint64_t flags;
149
+
150
+    /* entry identifier for commits */
151
+    uint64_t commit_id;
152
+
153
+    /* queue the command is for (queue index) */
154
+    uint16_t qid;
155
+    uint8_t padding[6];
156
+};
157
+
158
#endif /* _LINUX_FUSE_H */
159
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
160
index XXXXXXX..XXXXXXX 100644
161
--- a/include/standard-headers/linux/input-event-codes.h
162
+++ b/include/standard-headers/linux/input-event-codes.h
163
@@ -XXX,XX +XXX,XX @@
164
#define KEY_NOTIFICATION_CENTER    0x1bc    /* Show/hide the notification center */
165
#define KEY_PICKUP_PHONE    0x1bd    /* Answer incoming call */
166
#define KEY_HANGUP_PHONE    0x1be    /* Decline incoming call */
167
+#define KEY_LINK_PHONE        0x1bf /* AL Phone Syncing */
168
169
#define KEY_DEL_EOL        0x1c0
170
#define KEY_DEL_EOS        0x1c1
171
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/include/standard-headers/linux/pci_regs.h
174
+++ b/include/standard-headers/linux/pci_regs.h
175
@@ -XXX,XX +XXX,XX @@
176
#define PCI_EXP_DEVSTA_TRPND    0x0020    /* Transactions Pending */
177
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1    12    /* v1 endpoints without link end here */
178
#define PCI_EXP_LNKCAP        0x0c    /* Link Capabilities */
179
-#define PCI_EXP_LNKCAP_SLS    0x0000000f /* Supported Link Speeds */
180
+#define PCI_EXP_LNKCAP_SLS    0x0000000f /* Max Link Speed (prior to PCIe r3.0: Supported Link Speeds) */
181
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
182
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
183
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
184
@@ -XXX,XX +XXX,XX @@
185
#define PCI_EXP_DEVCAP2_OBFF_MSG    0x00040000 /* New message signaling */
186
#define PCI_EXP_DEVCAP2_OBFF_WAKE    0x00080000 /* Re-use WAKE# for OBFF */
187
#define PCI_EXP_DEVCAP2_EE_PREFIX    0x00200000 /* End-End TLP Prefix */
188
+#define PCI_EXP_DEVCAP2_EE_PREFIX_MAX    0x00c00000 /* Max End-End TLP Prefixes */
189
#define PCI_EXP_DEVCTL2        0x28    /* Device Control 2 */
190
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT    0x000f    /* Completion Timeout Value */
191
#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS    0x0010    /* Completion Timeout Disable */
192
@@ -XXX,XX +XXX,XX @@
193
    /* Same bits as above */
194
#define PCI_ERR_CAP        0x18    /* Advanced Error Capabilities & Ctrl*/
195
#define PCI_ERR_CAP_FEP(x)    ((x) & 0x1f)    /* First Error Pointer */
196
-#define PCI_ERR_CAP_ECRC_GENC    0x00000020    /* ECRC Generation Capable */
197
-#define PCI_ERR_CAP_ECRC_GENE    0x00000040    /* ECRC Generation Enable */
198
-#define PCI_ERR_CAP_ECRC_CHKC    0x00000080    /* ECRC Check Capable */
199
-#define PCI_ERR_CAP_ECRC_CHKE    0x00000100    /* ECRC Check Enable */
200
+#define PCI_ERR_CAP_ECRC_GENC        0x00000020 /* ECRC Generation Capable */
201
+#define PCI_ERR_CAP_ECRC_GENE        0x00000040 /* ECRC Generation Enable */
202
+#define PCI_ERR_CAP_ECRC_CHKC        0x00000080 /* ECRC Check Capable */
203
+#define PCI_ERR_CAP_ECRC_CHKE        0x00000100 /* ECRC Check Enable */
204
+#define PCI_ERR_CAP_PREFIX_LOG_PRESENT    0x00000800 /* TLP Prefix Log Present */
205
#define PCI_ERR_HEADER_LOG    0x1c    /* Header Log Register (16 bytes) */
206
#define PCI_ERR_ROOT_COMMAND    0x2c    /* Root Error Command */
207
#define PCI_ERR_ROOT_CMD_COR_EN    0x00000001 /* Correctable Err Reporting Enable */
208
@@ -XXX,XX +XXX,XX @@
209
#define PCI_ERR_ROOT_FATAL_RCV        0x00000040 /* Fatal Received */
210
#define PCI_ERR_ROOT_AER_IRQ        0xf8000000 /* Advanced Error Interrupt Message Number */
211
#define PCI_ERR_ROOT_ERR_SRC    0x34    /* Error Source Identification */
212
+#define PCI_ERR_PREFIX_LOG    0x38    /* TLP Prefix LOG Register (up to 16 bytes) */
213
214
/* Virtual Channel */
215
#define PCI_VC_PORT_CAP1    0x04
216
@@ -XXX,XX +XXX,XX @@
217
#define PCI_ACS_CTRL        0x06    /* ACS Control Register */
218
#define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
219
220
-#define PCI_VSEC_HDR        4    /* extended cap - vendor-specific */
221
-#define PCI_VSEC_HDR_LEN_SHIFT    20    /* shift for length field */
222
-
223
/* SATA capability */
224
#define PCI_SATA_REGS        4    /* SATA REGs specifier */
225
#define PCI_SATA_REGS_MASK    0xF    /* location - BAR#/inline */
226
diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h
227
index XXXXXXX..XXXXXXX 100644
228
--- a/include/standard-headers/linux/virtio_pci.h
229
+++ b/include/standard-headers/linux/virtio_pci.h
230
@@ -XXX,XX +XXX,XX @@
231
#define VIRTIO_PCI_CAP_PCI_CFG        5
232
/* Additional shared memory capability */
233
#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
234
+/* PCI vendor data configuration */
235
+#define VIRTIO_PCI_CAP_VENDOR_CFG    9
236
237
/* This is the PCI capability header: */
238
struct virtio_pci_cap {
239
@@ -XXX,XX +XXX,XX @@ struct virtio_pci_cap {
240
    uint32_t length;        /* Length of the structure, in bytes. */
241
};
242
243
+/* This is the PCI vendor data capability header: */
244
+struct virtio_pci_vndr_data {
245
+    uint8_t cap_vndr;        /* Generic PCI field: PCI_CAP_ID_VNDR */
246
+    uint8_t cap_next;        /* Generic PCI field: next ptr. */
247
+    uint8_t cap_len;        /* Generic PCI field: capability length */
248
+    uint8_t cfg_type;        /* Identifies the structure. */
249
+    uint16_t vendor_id;    /* Identifies the vendor-specific format. */
250
+    /* For Vendor Definition */
251
+    /* Pads structure to a multiple of 4 bytes */
252
+    /* Reads must not have side effects */
253
+};
254
+
255
struct virtio_pci_cap64 {
256
    struct virtio_pci_cap cap;
257
    uint32_t offset_hi; /* Most sig 32 bits of offset */
258
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
259
index XXXXXXX..XXXXXXX 100644
260
--- a/linux-headers/asm-arm64/kvm.h
261
+++ b/linux-headers/asm-arm64/kvm.h
262
@@ -XXX,XX +XXX,XX @@
263
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
264
#define KVM_DIRTY_LOG_PAGE_OFFSET 64
265
266
-#define KVM_REG_SIZE(id)                        \
267
-    (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
268
-
269
struct kvm_regs {
270
    struct user_pt_regs regs;    /* sp = sp_el0 */
271
272
diff --git a/linux-headers/asm-loongarch/kvm_para.h b/linux-headers/asm-loongarch/kvm_para.h
273
index XXXXXXX..XXXXXXX 100644
274
--- a/linux-headers/asm-loongarch/kvm_para.h
275
+++ b/linux-headers/asm-loongarch/kvm_para.h
276
@@ -XXX,XX +XXX,XX @@
277
#define KVM_FEATURE_STEAL_TIME        2
278
/* BIT 24 - 31 are features configurable by user space vmm */
279
#define KVM_FEATURE_VIRT_EXTIOI    24
280
+#define KVM_FEATURE_USER_HCALL        25
281
282
#endif /* _ASM_KVM_PARA_H */
283
diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
284
index XXXXXXX..XXXXXXX 100644
285
--- a/linux-headers/asm-riscv/kvm.h
286
+++ b/linux-headers/asm-riscv/kvm.h
287
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_ISA_EXT_ID {
288
    KVM_RISCV_ISA_EXT_SSNPM,
289
    KVM_RISCV_ISA_EXT_SVADE,
290
    KVM_RISCV_ISA_EXT_SVADU,
291
+    KVM_RISCV_ISA_EXT_SVVPTC,
292
+    KVM_RISCV_ISA_EXT_ZABHA,
293
+    KVM_RISCV_ISA_EXT_ZICCRSE,
294
    KVM_RISCV_ISA_EXT_MAX,
295
};
296
297
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_SBI_EXT_ID {
298
    KVM_RISCV_SBI_EXT_VENDOR,
299
    KVM_RISCV_SBI_EXT_DBCN,
300
    KVM_RISCV_SBI_EXT_STA,
301
+    KVM_RISCV_SBI_EXT_SUSP,
302
    KVM_RISCV_SBI_EXT_MAX,
303
};
304
305
@@ -XXX,XX +XXX,XX @@ struct kvm_riscv_sbi_sta {
306
#define KVM_RISCV_TIMER_STATE_OFF    0
307
#define KVM_RISCV_TIMER_STATE_ON    1
308
309
-#define KVM_REG_SIZE(id)        \
310
-    (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
311
-
312
/* If you need to interpret the index values, here is the key: */
313
#define KVM_REG_RISCV_TYPE_MASK        0x00000000FF000000
314
#define KVM_REG_RISCV_TYPE_SHIFT    24
315
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
316
index XXXXXXX..XXXXXXX 100644
317
--- a/linux-headers/asm-x86/kvm.h
318
+++ b/linux-headers/asm-x86/kvm.h
319
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_eventfd {
320
#define KVM_X86_SEV_VM        2
321
#define KVM_X86_SEV_ES_VM    3
322
#define KVM_X86_SNP_VM        4
323
+#define KVM_X86_TDX_VM        5
324
325
#endif /* _ASM_X86_KVM_H */
326
diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
327
index XXXXXXX..XXXXXXX 100644
328
--- a/linux-headers/linux/iommufd.h
329
+++ b/linux-headers/linux/iommufd.h
330
@@ -XXX,XX +XXX,XX @@ struct iommu_ioas_unmap {
331
* ioctl(IOMMU_OPTION_HUGE_PAGES)
332
* @IOMMU_OPTION_RLIMIT_MODE:
333
* Change how RLIMIT_MEMLOCK accounting works. The caller must have privilege
334
- * to invoke this. Value 0 (default) is user based accouting, 1 uses process
335
+ * to invoke this. Value 0 (default) is user based accounting, 1 uses process
336
* based accounting. Global option, object_id must be 0
337
* @IOMMU_OPTION_HUGE_PAGES:
338
* Value 1 (default) allows contiguous pages to be combined when generating
339
@@ -XXX,XX +XXX,XX @@ struct iommu_vfio_ioas {
340
* @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The
341
* domain can be attached to any PASID on the device.
342
* Any domain attached to the non-PASID part of the
343
- * device must also be flaged, otherwise attaching a
344
+ * device must also be flagged, otherwise attaching a
345
* PASID will blocked.
346
* If IOMMU does not support PASID it will return
347
* error (-EOPNOTSUPP).
348
@@ -XXX,XX +XXX,XX @@ struct iommu_hw_info_vtd {
349
* For the details of @idr, @iidr and @aidr, please refer to the chapters
350
* from 6.3.1 to 6.3.6 in the SMMUv3 Spec.
351
*
352
- * User space should read the underlying ARM SMMUv3 hardware information for
353
- * the list of supported features.
354
+ * This reports the raw HW capability, and not all bits are meaningful to be
355
+ * read by userspace. Only the following fields should be used:
356
*
357
- * Note that these values reflect the raw HW capability, without any insight if
358
- * any required kernel driver support is present. Bits may be set indicating the
359
- * HW has functionality that is lacking kernel software support, such as BTM. If
360
- * a VMM is using this information to construct emulated copies of these
361
- * registers it should only forward bits that it knows it can support.
362
+ * idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF
363
+ * idr[1]: SIDSIZE, SSIDSIZE
364
+ * idr[3]: BBML, RIL
365
+ * idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K
366
*
367
- * In future, presence of required kernel support will be indicated in flags.
368
+ * - S1P should be assumed to be true if a NESTED HWPT can be created
369
+ * - VFIO/iommufd only support platforms with COHACC, it should be assumed to be
370
+ * true.
371
+ * - ATS is a per-device property. If the VMM describes any devices as ATS
372
+ * capable in ACPI/DT it should set the corresponding idr.
373
+ *
374
+ * This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is
375
+ * important that VMMs do not read bits outside the list to allow for
376
+ * compatibility with future kernels. Several features in the SMMUv3
377
+ * architecture are not currently supported by the kernel for nesting: HTTU,
378
+ * BTM, MPAM and others.
379
*/
380
struct iommu_hw_info_arm_smmuv3 {
381
    __u32 flags;
382
@@ -XXX,XX +XXX,XX @@ struct iommu_hwpt_vtd_s1_invalidate {
383
};
384
385
/**
386
- * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cahce invalidation
387
+ * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
388
* (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3)
389
* @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
390
* Must be little-endian.
391
@@ -XXX,XX +XXX,XX @@ enum iommu_hwpt_pgfault_perm {
392
* @pasid: Process Address Space ID
393
* @grpid: Page Request Group Index
394
* @perm: Combination of enum iommu_hwpt_pgfault_perm
395
+ * @__reserved: Must be 0.
396
* @addr: Fault address
397
* @length: a hint of how much data the requestor is expecting to fetch. For
398
* example, if the PRI initiator knows it is going to do a 10MB
399
@@ -XXX,XX +XXX,XX @@ struct iommu_hwpt_pgfault {
400
    __u32 pasid;
401
    __u32 grpid;
402
    __u32 perm;
403
-    __u64 addr;
404
+    __u32 __reserved;
405
+    __aligned_u64 addr;
406
    __u32 length;
407
    __u32 cookie;
408
};
409
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
410
index XXXXXXX..XXXXXXX 100644
411
--- a/linux-headers/linux/kvm.h
412
+++ b/linux-headers/linux/kvm.h
413
@@ -XXX,XX +XXX,XX @@ struct kvm_ioeventfd {
414
#define KVM_X86_DISABLE_EXITS_HLT (1 << 1)
415
#define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2)
416
#define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3)
417
-#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \
418
- KVM_X86_DISABLE_EXITS_HLT | \
419
- KVM_X86_DISABLE_EXITS_PAUSE | \
420
- KVM_X86_DISABLE_EXITS_CSTATE)
421
422
/* for KVM_ENABLE_CAP */
423
struct kvm_enable_cap {
424
@@ -XXX,XX +XXX,XX @@ struct kvm_dirty_tlb {
425
426
#define KVM_REG_SIZE_SHIFT    52
427
#define KVM_REG_SIZE_MASK    0x00f0000000000000ULL
428
+
429
+#define KVM_REG_SIZE(id)        \
430
+    (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
431
+
432
#define KVM_REG_SIZE_U8        0x0000000000000000ULL
433
#define KVM_REG_SIZE_U16    0x0010000000000000ULL
434
#define KVM_REG_SIZE_U32    0x0020000000000000ULL
435
diff --git a/linux-headers/linux/stddef.h b/linux-headers/linux/stddef.h
436
index XXXXXXX..XXXXXXX 100644
437
--- a/linux-headers/linux/stddef.h
438
+++ b/linux-headers/linux/stddef.h
439
@@ -XXX,XX +XXX,XX @@
440
#define __always_inline __inline__
441
#endif
442
443
+/* Not all C++ standards support type declarations inside an anonymous union */
444
+#ifndef __cplusplus
445
+#define __struct_group_tag(TAG)        TAG
446
+#else
447
+#define __struct_group_tag(TAG)
448
+#endif
449
+
450
/**
451
* __struct_group() - Create a mirrored named and anonyomous struct
452
*
453
@@ -XXX,XX +XXX,XX @@
454
* and size: one anonymous and one named. The former's members can be used
455
* normally without sub-struct naming, and the latter can be used to
456
* reason about the start, end, and size of the group of struct members.
457
- * The named struct can also be explicitly tagged for layer reuse, as well
458
- * as both having struct attributes appended.
459
+ * The named struct can also be explicitly tagged for layer reuse (C only),
460
+ * as well as both having struct attributes appended.
461
*/
462
#define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \
463
    union { \
464
        struct { MEMBERS } ATTRS; \
465
-        struct TAG { MEMBERS } ATTRS NAME; \
466
+        struct __struct_group_tag(TAG) { MEMBERS } ATTRS NAME; \
467
    } ATTRS
468
469
#ifdef __cplusplus
470
diff --git a/linux-headers/linux/vduse.h b/linux-headers/linux/vduse.h
471
index XXXXXXX..XXXXXXX 100644
472
--- a/linux-headers/linux/vduse.h
473
+++ b/linux-headers/linux/vduse.h
474
@@ -XXX,XX +XXX,XX @@
475
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
476
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
477
#ifndef _VDUSE_H_
478
#define _VDUSE_H_
479
480
--
481
2.48.1
diff view generated by jsdifflib
New patch
[PULL 37/59] target/riscv/cpu.c: create flag for ziccrse
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
At this moment ziccrse is a TCG always enabled named feature for
4
priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
5
the KVM driver turn ziccrse off if the extension isn't available in the
6
host, and we'll need an ext_ziccrse flag in the CPU state for that.
7
8
Create an exclusive flag for it like we do with other named features.
9
As with any named features we already have, it won't be exposed to
10
users.
11
12
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
14
Message-ID: <20250221153758.652078-3-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu_cfg.h | 3 +++
18
target/riscv/cpu.c | 3 ++-
19
target/riscv/tcg/tcg-cpu.c | 2 ++
20
3 files changed, 7 insertions(+), 1 deletion(-)
21
22
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu_cfg.h
25
+++ b/target/riscv/cpu_cfg.h
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
27
bool has_priv_1_12;
28
bool has_priv_1_11;
29
30
+ /* Always enabled for TCG if has_priv_1_11 */
31
+ bool ext_ziccrse;
32
+
33
/* Vendor-specific custom extensions */
34
bool ext_xtheadba;
35
bool ext_xtheadbb;
36
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu.c
39
+++ b/target/riscv/cpu.c
40
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
41
ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11),
42
ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11),
43
ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11),
44
- ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11),
45
+ ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_ziccrse),
46
ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp),
47
ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss),
48
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
49
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
50
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
51
MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
52
MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
53
+ MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
54
55
{ },
56
};
57
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/tcg/tcg-cpu.c
60
+++ b/target/riscv/tcg/tcg-cpu.c
61
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
62
63
cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) &&
64
cpu->cfg.ext_ssstateen;
65
+
66
+ cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;
67
}
68
69
static void riscv_cpu_validate_g(RISCVCPU *cpu)
70
--
71
2.48.1
diff view generated by jsdifflib
New patch
[PULL 38/59] target/riscv/kvm: add extensions after 6.14-rc3 update
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Expose ziccrse, zabha and svvptc.
4
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
7
Message-ID: <20250221153758.652078-4-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
target/riscv/kvm/kvm-cpu.c | 3 +++
11
1 file changed, 3 insertions(+)
12
13
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/kvm/kvm-cpu.c
16
+++ b/target/riscv/kvm/kvm-cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
18
static KVMCPUConfig kvm_multi_ext_cfgs[] = {
19
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
20
KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
21
+ KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE),
22
KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR),
23
KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND),
24
KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR),
25
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
26
KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
27
KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP),
28
KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP),
29
+ KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA),
30
KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS),
31
KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS),
32
KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA),
33
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
34
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
35
KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT),
36
KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
37
+ KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC),
38
};
39
40
static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg)
41
--
42
2.48.1
diff view generated by jsdifflib
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
[PULL 39/59] hw/riscv/riscv-iommu.h: add missing headers
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
3
This header is incomplete, i.e. it is using definitions that are being
4
been updated to use a register mapped at 0x4f000000 instead of a
4
supplied by the .c files that are including it.
5
GPIO to control whether eMMC or SD card is to be used. With this
6
support the same HSS image can be used for both eMMC and SD card
7
boot flow, while previously two different board configurations were
8
used. This is undocumented but one can take a look at the HSS code
9
HSS_MMCInit() in services/mmc/mmc_api.c.
10
5
11
With this commit, HSS image built from 2020.12 release boots again.
6
Adding this header into a fresh .c file will result in errors:
12
7
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:30:17: error: field ‘parent_obj’ has incomplete type
9
30 | DeviceState parent_obj;
10
| ^~~~~~~~~~
11
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:50:5: error: unknown type name ‘dma_addr_t’; did you mean ‘in_addr_t’?
12
50 | dma_addr_t cq_addr; /* Command queue base physical address */
13
| ^~~~~~~~~~
14
| in_addr_t
15
(...)
16
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:62:5: error: unknown type name ‘QemuThread’; did you mean ‘GThread’?
17
62 | QemuThread core_proc; /* Background processing thread */
18
| ^~~~~~~~~~
19
| GThread
20
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:63:5: error: unknown type name ‘QemuCond’
21
63 | QemuCond core_cond; /* Background processing wake up signal */
22
| ^~~~~~~~
23
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:71:18: error: field ‘trap_as’ has incomplete type
24
71 | AddressSpace trap_as;
25
| ^~~~~~~
26
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:72:18: error: field ‘trap_mr’ has incomplete type
27
72 | MemoryRegion trap_mr;
28
| ^~~~~~~
29
/home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:80:18: error: field ‘regs_mr’ has incomplete type
30
80 | MemoryRegion regs_mr;
31
| ^~~~~~~
32
33
Fix it by adding the missing headers for these definitions.
34
35
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
37
Message-ID: <20250224190826.1858473-2-dbarboza@ventanamicro.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
38
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
39
---
18
include/hw/riscv/microchip_pfsoc.h | 1 +
40
hw/riscv/riscv-iommu.h | 2 ++
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
41
1 file changed, 2 insertions(+)
20
2 files changed, 7 insertions(+)
21
42
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
43
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
23
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/riscv/microchip_pfsoc.h
45
--- a/hw/riscv/riscv-iommu.h
25
+++ b/include/hw/riscv/microchip_pfsoc.h
46
+++ b/hw/riscv/riscv-iommu.h
26
@@ -XXX,XX +XXX,XX @@ enum {
47
@@ -XXX,XX +XXX,XX @@
27
MICROCHIP_PFSOC_ENVM_DATA,
48
#define HW_RISCV_IOMMU_STATE_H
28
MICROCHIP_PFSOC_QSPI_XIP,
49
29
MICROCHIP_PFSOC_IOSCB,
50
#include "qom/object.h"
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
51
+#include "hw/qdev-properties.h"
31
MICROCHIP_PFSOC_DRAM_LO,
52
+#include "system/dma.h"
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
53
#include "hw/riscv/iommu.h"
33
MICROCHIP_PFSOC_DRAM_HI,
54
#include "hw/riscv/riscv-iommu-bits.h"
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
55
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/riscv/microchip_pfsoc.c
37
+++ b/hw/riscv/microchip_pfsoc.c
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
49
50
+ /* eMMC/SD mux */
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
54
+
55
/* QSPI Flash */
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
57
"microchip.pfsoc.qspi_xip",
58
--
56
--
59
2.30.1
57
2.48.1
60
58
61
59
diff view generated by jsdifflib
New patch
[PULL 40/59] hw/riscv/riscv-iommu-bits.h: HPM bits
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
Add the relevant HPM (High Performance Monitor) bits that we'll be using
4
in the next patches.
5
6
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
7
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20250224190826.1858473-3-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/riscv/riscv-iommu-bits.h | 47 +++++++++++++++++++++++++++++++++++++
13
1 file changed, 47 insertions(+)
14
15
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/riscv-iommu-bits.h
18
+++ b/hw/riscv/riscv-iommu-bits.h
19
@@ -XXX,XX +XXX,XX @@ struct riscv_iommu_pq_record {
20
#define RISCV_IOMMU_CAP_ATS BIT_ULL(25)
21
#define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26)
22
#define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28)
23
+#define RISCV_IOMMU_CAP_HPM BIT_ULL(30)
24
#define RISCV_IOMMU_CAP_DBG BIT_ULL(31)
25
#define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32)
26
#define RISCV_IOMMU_CAP_PD8 BIT_ULL(38)
27
@@ -XXX,XX +XXX,XX @@ enum {
28
RISCV_IOMMU_INTR_COUNT
29
};
30
31
+#define RISCV_IOMMU_IOCOUNT_NUM 31
32
+
33
+/* 5.19 Performance monitoring counter overflow status (32bits) */
34
+#define RISCV_IOMMU_REG_IOCOUNTOVF 0x0058
35
+#define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0)
36
+
37
+/* 5.20 Performance monitoring counter inhibits (32bits) */
38
+#define RISCV_IOMMU_REG_IOCOUNTINH 0x005C
39
+#define RISCV_IOMMU_IOCOUNTINH_CY BIT(0)
40
+
41
+/* 5.21 Performance monitoring cycles counter (64bits) */
42
+#define RISCV_IOMMU_REG_IOHPMCYCLES 0x0060
43
+#define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0)
44
+#define RISCV_IOMMU_IOHPMCYCLES_OVF BIT_ULL(63)
45
+
46
+/* 5.22 Performance monitoring event counters (31 * 64bits) */
47
+#define RISCV_IOMMU_REG_IOHPMCTR_BASE 0x0068
48
+#define RISCV_IOMMU_REG_IOHPMCTR(_n) \
49
+ (RISCV_IOMMU_REG_IOHPMCTR_BASE + (_n * 0x8))
50
+
51
+/* 5.23 Performance monitoring event selectors (31 * 64bits) */
52
+#define RISCV_IOMMU_REG_IOHPMEVT_BASE 0x0160
53
+#define RISCV_IOMMU_REG_IOHPMEVT(_n) \
54
+ (RISCV_IOMMU_REG_IOHPMEVT_BASE + (_n * 0x8))
55
+#define RISCV_IOMMU_IOHPMEVT_EVENT_ID GENMASK_ULL(14, 0)
56
+#define RISCV_IOMMU_IOHPMEVT_DMASK BIT_ULL(15)
57
+#define RISCV_IOMMU_IOHPMEVT_PID_PSCID GENMASK_ULL(35, 16)
58
+#define RISCV_IOMMU_IOHPMEVT_DID_GSCID GENMASK_ULL(59, 36)
59
+#define RISCV_IOMMU_IOHPMEVT_PV_PSCV BIT_ULL(60)
60
+#define RISCV_IOMMU_IOHPMEVT_DV_GSCV BIT_ULL(61)
61
+#define RISCV_IOMMU_IOHPMEVT_IDT BIT_ULL(62)
62
+#define RISCV_IOMMU_IOHPMEVT_OF BIT_ULL(63)
63
+
64
+enum RISCV_IOMMU_HPMEVENT_id {
65
+ RISCV_IOMMU_HPMEVENT_INVALID = 0,
66
+ RISCV_IOMMU_HPMEVENT_URQ = 1,
67
+ RISCV_IOMMU_HPMEVENT_TRQ = 2,
68
+ RISCV_IOMMU_HPMEVENT_ATS_RQ = 3,
69
+ RISCV_IOMMU_HPMEVENT_TLB_MISS = 4,
70
+ RISCV_IOMMU_HPMEVENT_DD_WALK = 5,
71
+ RISCV_IOMMU_HPMEVENT_PD_WALK = 6,
72
+ RISCV_IOMMU_HPMEVENT_S_VS_WALKS = 7,
73
+ RISCV_IOMMU_HPMEVENT_G_WALKS = 8,
74
+ RISCV_IOMMU_HPMEVENT_MAX = 9
75
+};
76
+
77
/* 5.24 Translation request IOVA (64bits) */
78
#define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258
79
80
--
81
2.48.1
diff view generated by jsdifflib
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PULL 41/59] hw/riscv/riscv-iommu: add riscv-iommu-hpm file
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
2
2
3
This adds the documentation to describe what is supported for the
3
The HPM (Hardware Performance Monitor) support consists of almost 7
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
4
hundred lines that would be put on top of the base riscv-iommu
5
emulation.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
that will contain HPM specific code.
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
9
10
We'll start by adding riscv_iommu_hpmcycle_read(), a helper that will be
11
called during the riscv_iommu_mmio_read() callback.
12
13
This change will have no effect on the existing emulation since we're
14
not declaring HPM feature support.
15
16
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
17
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
18
Acked-by: Alistair Francis <alistair.francis@wdc.com>
19
Message-ID: <20250224190826.1858473-4-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
21
---
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
22
hw/riscv/riscv-iommu-hpm.h | 27 +++++++++++++++++++
12
docs/system/target-riscv.rst | 1 +
23
hw/riscv/riscv-iommu.h | 4 +++
13
2 files changed, 90 insertions(+)
24
hw/riscv/riscv-iommu-hpm.c | 54 ++++++++++++++++++++++++++++++++++++++
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
25
hw/riscv/riscv-iommu.c | 24 ++++++++++++++++-
26
hw/riscv/meson.build | 3 ++-
27
5 files changed, 110 insertions(+), 2 deletions(-)
28
create mode 100644 hw/riscv/riscv-iommu-hpm.h
29
create mode 100644 hw/riscv/riscv-iommu-hpm.c
15
30
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
31
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
17
new file mode 100644
32
new file mode 100644
18
index XXXXXXX..XXXXXXX
33
index XXXXXXX..XXXXXXX
19
--- /dev/null
34
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
35
+++ b/hw/riscv/riscv-iommu-hpm.h
21
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
37
+/*
23
+=============================================================
38
+ * RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
39
+ *
40
+ * Copyright (C) 2022-2023 Rivos Inc.
41
+ *
42
+ * This program is free software; you can redistribute it and/or modify it
43
+ * under the terms and conditions of the GNU General Public License,
44
+ * version 2 or later, as published by the Free Software Foundation.
45
+ *
46
+ * This program is distributed in the hope that it will be useful,
47
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
48
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49
+ * GNU General Public License for more details.
50
+ *
51
+ * You should have received a copy of the GNU General Public License along
52
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
53
+ */
24
+
54
+
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
55
+#ifndef HW_RISCV_IOMMU_HPM_H
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
56
+#define HW_RISCV_IOMMU_HPM_H
27
+
57
+
28
+For more details about Microchip PolarFire SoC, please see:
58
+#include "qom/object.h"
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
59
+#include "hw/riscv/riscv-iommu.h"
30
+
60
+
31
+The Icicle Kit board information can be found here:
61
+uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
32
+https://www.microsemi.com/existing-parts/parts/152514
33
+
62
+
34
+Supported devices
63
+#endif
35
+-----------------
64
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/riscv/riscv-iommu.h
67
+++ b/hw/riscv/riscv-iommu.h
68
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
69
70
QLIST_ENTRY(RISCVIOMMUState) iommus;
71
QLIST_HEAD(, RISCVIOMMUSpace) spaces;
36
+
72
+
37
+The ``microchip-icicle-kit`` machine supports the following devices:
73
+ /* HPM cycle counter */
74
+ uint64_t hpmcycle_val; /* Current value of cycle register */
75
+ uint64_t hpmcycle_prev; /* Saved value of QEMU_CLOCK_VIRTUAL clock */
76
};
77
78
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
79
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
80
new file mode 100644
81
index XXXXXXX..XXXXXXX
82
--- /dev/null
83
+++ b/hw/riscv/riscv-iommu-hpm.c
84
@@ -XXX,XX +XXX,XX @@
85
+/*
86
+ * RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
87
+ *
88
+ * Copyright (C) 2022-2023 Rivos Inc.
89
+ *
90
+ * This program is free software; you can redistribute it and/or modify it
91
+ * under the terms and conditions of the GNU General Public License,
92
+ * version 2 or later, as published by the Free Software Foundation.
93
+ *
94
+ * This program is distributed in the hope that it will be useful,
95
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
96
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
97
+ * GNU General Public License for more details.
98
+ *
99
+ * You should have received a copy of the GNU General Public License along
100
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
101
+ */
38
+
102
+
39
+ * 1 E51 core
103
+#include "qemu/osdep.h"
40
+ * 4 U54 cores
104
+#include "qemu/timer.h"
41
+ * Core Level Interruptor (CLINT)
105
+#include "cpu_bits.h"
42
+ * Platform-Level Interrupt Controller (PLIC)
106
+#include "riscv-iommu-hpm.h"
43
+ * L2 Loosely Integrated Memory (L2-LIM)
107
+#include "riscv-iommu.h"
44
+ * DDR memory controller
108
+#include "riscv-iommu-bits.h"
45
+ * 5 MMUARTs
109
+#include "trace.h"
46
+ * 1 DMA controller
47
+ * 2 GEM Ethernet controllers
48
+ * 1 SDHC storage controller
49
+
110
+
50
+Boot options
111
+/* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
51
+------------
112
+static inline uint64_t get_cycles(void)
113
+{
114
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
115
+}
52
+
116
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
117
+uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
118
+{
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
119
+ const uint64_t cycle = riscv_iommu_reg_get64(
56
+support direct kernel loading via the -kernel option. One has to load kernel
120
+ s, RISCV_IOMMU_REG_IOHPMCYCLES);
57
+from U-Boot.
121
+ const uint32_t inhibit = riscv_iommu_reg_get32(
122
+ s, RISCV_IOMMU_REG_IOCOUNTINH);
123
+ const uint64_t ctr_prev = s->hpmcycle_prev;
124
+ const uint64_t ctr_val = s->hpmcycle_val;
58
+
125
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
126
+ if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
60
+memory size by HSS. A sanity check on ram size is performed in the machine
127
+ /*
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
128
+ * Counter should not increment if inhibit bit is set. We can't really
62
+than 1537 MiB ram is detected.
129
+ * stop the QEMU_CLOCK_VIRTUAL, so we just return the last updated
130
+ * counter value to indicate that counter was not incremented.
131
+ */
132
+ return (ctr_val & RISCV_IOMMU_IOHPMCYCLES_COUNTER) |
133
+ (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);
134
+ }
63
+
135
+
64
+Boot the machine
136
+ return (ctr_val + get_cycles() - ctr_prev) |
65
+----------------
137
+ (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);
138
+}
139
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
140
index XXXXXXX..XXXXXXX 100644
141
--- a/hw/riscv/riscv-iommu.c
142
+++ b/hw/riscv/riscv-iommu.c
143
@@ -XXX,XX +XXX,XX @@
144
#include "cpu_bits.h"
145
#include "riscv-iommu.h"
146
#include "riscv-iommu-bits.h"
147
+#include "riscv-iommu-hpm.h"
148
#include "trace.h"
149
150
#define LIMIT_CACHE_CTX (1U << 7)
151
@@ -XXX,XX +XXX,XX @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
152
return MEMTX_ACCESS_ERROR;
153
}
154
155
- ptr = &s->regs_rw[addr];
156
+ /* Compute cycle register value. */
157
+ if ((addr & ~7) == RISCV_IOMMU_REG_IOHPMCYCLES) {
158
+ val = riscv_iommu_hpmcycle_read(s);
159
+ ptr = (uint8_t *)&val + (addr & 7);
160
+ } else if ((addr & ~3) == RISCV_IOMMU_REG_IOCOUNTOVF) {
161
+ /*
162
+ * Software can read RISCV_IOMMU_REG_IOCOUNTOVF before timer
163
+ * callback completes. In which case CY_OF bit in
164
+ * RISCV_IOMMU_IOHPMCYCLES_OVF would be 0. Here we take the
165
+ * CY_OF bit state from RISCV_IOMMU_REG_IOHPMCYCLES register as
166
+ * it's not dependent over the timer callback and is computed
167
+ * from cycle overflow.
168
+ */
169
+ val = ldq_le_p(&s->regs_rw[addr]);
170
+ val |= (riscv_iommu_hpmcycle_read(s) & RISCV_IOMMU_IOHPMCYCLES_OVF)
171
+ ? RISCV_IOMMU_IOCOUNTOVF_CY
172
+ : 0;
173
+ ptr = (uint8_t *)&val + (addr & 3);
174
+ } else {
175
+ ptr = &s->regs_rw[addr];
176
+ }
66
+
177
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
178
val = ldn_le_p(ptr, size);
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
179
69
+in the HSS source tree:
180
*data = val;
70
+
181
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
71
+.. code-block:: bash
72
+
73
+ $ export CROSS_COMPILE=riscv64-linux-
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
75
+ $ make BOARD=mpfs-icicle-kit-es
76
+
77
+Download the official SD card image released by Microchip and prepare it for
78
+QEMU usage:
79
+
80
+.. code-block:: bash
81
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
86
+Then we can boot the machine by:
87
+
88
+.. code-block:: bash
89
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
92
+ -nic user,model=cadence_gem \
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
94
+ -display none -serial stdio \
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
96
+ -serial chardev:serial1
97
+
98
+With above command line, current terminal session will be used for the first
99
+serial port. Open another terminal window, and use `minicom` to connect the
100
+second serial port.
101
+
102
+.. code-block:: bash
103
+
104
+ $ minicom -D unix\#serial1.sock
105
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
107
+second serial port. U-Boot will automatically load the Linux kernel from
108
+the SD card image.
109
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
112
index XXXXXXX..XXXXXXX 100644
182
index XXXXXXX..XXXXXXX 100644
113
--- a/docs/system/target-riscv.rst
183
--- a/hw/riscv/meson.build
114
+++ b/docs/system/target-riscv.rst
184
+++ b/hw/riscv/meson.build
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
185
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
116
.. toctree::
186
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
117
:maxdepth: 1
187
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
118
188
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
119
+ riscv/microchip-icicle-kit
189
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
120
riscv/sifive_u
190
+riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
121
191
+    'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
122
RISC-V CPU features
192
riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
193
194
hw_arch += {'riscv': riscv_ss}
123
--
195
--
124
2.30.1
196
2.48.1
125
126
diff view generated by jsdifflib
New patch
[PULL 42/59] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()
1
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
2
3
This function will increment a specific counter, generating an interrupt
4
when an overflow occurs.
5
6
Some extra changes in riscv-iommu.c were required to add this new
7
helper in riscv-iommu-hpm.c:
8
9
- RISCVIOMMUContext was moved to riscv-iommu.h, making it visible in
10
riscv-iommu-hpm.c;
11
12
- riscv_iommu_notify() is now public.
13
14
No behavior change is made since HPM support is not being advertised
15
yet.
16
17
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
18
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
19
Acked-by: Alistair Francis <alistair.francis@wdc.com>
20
Message-ID: <20250224190826.1858473-5-dbarboza@ventanamicro.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
23
hw/riscv/riscv-iommu-hpm.h | 2 +
24
hw/riscv/riscv-iommu.h | 18 ++++++
25
hw/riscv/riscv-iommu-hpm.c | 114 +++++++++++++++++++++++++++++++++++++
26
hw/riscv/riscv-iommu.c | 43 +++++++++-----
27
4 files changed, 162 insertions(+), 15 deletions(-)
28
29
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/riscv/riscv-iommu-hpm.h
32
+++ b/hw/riscv/riscv-iommu-hpm.h
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/riscv/riscv-iommu.h"
35
36
uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
37
+void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
38
+ unsigned event_id);
39
40
#endif
41
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/riscv/riscv-iommu.h
44
+++ b/hw/riscv/riscv-iommu.h
45
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
46
/* HPM cycle counter */
47
uint64_t hpmcycle_val; /* Current value of cycle register */
48
uint64_t hpmcycle_prev; /* Saved value of QEMU_CLOCK_VIRTUAL clock */
49
+
50
+ /* HPM event counters */
51
+ GHashTable *hpm_event_ctr_map; /* Mapping of events to counters */
52
};
53
54
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
55
Error **errp);
56
void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
57
void riscv_iommu_reset(RISCVIOMMUState *s);
58
+void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type);
59
+
60
+typedef struct RISCVIOMMUContext RISCVIOMMUContext;
61
+/* Device translation context state. */
62
+struct RISCVIOMMUContext {
63
+ uint64_t devid:24; /* Requester Id, AKA device_id */
64
+ uint64_t process_id:20; /* Process ID. PASID for PCIe */
65
+ uint64_t tc; /* Translation Control */
66
+ uint64_t ta; /* Translation Attributes */
67
+ uint64_t satp; /* S-Stage address translation and protection */
68
+ uint64_t gatp; /* G-Stage address translation and protection */
69
+ uint64_t msi_addr_mask; /* MSI filtering - address mask */
70
+ uint64_t msi_addr_pattern; /* MSI filtering - address pattern */
71
+ uint64_t msiptp; /* MSI redirection page table pointer */
72
+};
73
74
/* private helpers */
75
76
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/hw/riscv/riscv-iommu-hpm.c
79
+++ b/hw/riscv/riscv-iommu-hpm.c
80
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
81
return (ctr_val + get_cycles() - ctr_prev) |
82
(cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);
83
}
84
+
85
+static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)
86
+{
87
+ const uint32_t off = ctr_idx << 3;
88
+ uint64_t cntr_val;
89
+
90
+ cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
91
+ stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
92
+
93
+ /* Handle the overflow scenario. */
94
+ if (cntr_val == UINT64_MAX) {
95
+ /*
96
+ * Generate interrupt only if OF bit is clear. +1 to offset the cycle
97
+ * register OF bit.
98
+ */
99
+ const uint32_t ovf =
100
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF,
101
+ BIT(ctr_idx + 1), 0);
102
+ if (!get_field(ovf, BIT(ctr_idx + 1))) {
103
+ riscv_iommu_reg_mod64(s,
104
+ RISCV_IOMMU_REG_IOHPMEVT_BASE + off,
105
+ RISCV_IOMMU_IOHPMEVT_OF,
106
+ 0);
107
+ riscv_iommu_notify(s, RISCV_IOMMU_INTR_PM);
108
+ }
109
+ }
110
+}
111
+
112
+void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
113
+ unsigned event_id)
114
+{
115
+ const uint32_t inhibit = riscv_iommu_reg_get32(
116
+ s, RISCV_IOMMU_REG_IOCOUNTINH);
117
+ uint32_t did_gscid;
118
+ uint32_t pid_pscid;
119
+ uint32_t ctr_idx;
120
+ gpointer value;
121
+ uint32_t ctrs;
122
+ uint64_t evt;
123
+
124
+ if (!(s->cap & RISCV_IOMMU_CAP_HPM)) {
125
+ return;
126
+ }
127
+
128
+ value = g_hash_table_lookup(s->hpm_event_ctr_map,
129
+ GUINT_TO_POINTER(event_id));
130
+ if (value == NULL) {
131
+ return;
132
+ }
133
+
134
+ for (ctrs = GPOINTER_TO_UINT(value); ctrs != 0; ctrs &= ctrs - 1) {
135
+ ctr_idx = ctz32(ctrs);
136
+ if (get_field(inhibit, BIT(ctr_idx + 1))) {
137
+ continue;
138
+ }
139
+
140
+ evt = riscv_iommu_reg_get64(s,
141
+ RISCV_IOMMU_REG_IOHPMEVT_BASE + (ctr_idx << 3));
142
+
143
+ /*
144
+ * It's quite possible that event ID has been changed in counter
145
+ * but hashtable hasn't been updated yet. We don't want to increment
146
+ * counter for the old event ID.
147
+ */
148
+ if (event_id != get_field(evt, RISCV_IOMMU_IOHPMEVT_EVENT_ID)) {
149
+ continue;
150
+ }
151
+
152
+ if (get_field(evt, RISCV_IOMMU_IOHPMEVT_IDT)) {
153
+ did_gscid = get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID);
154
+ pid_pscid = get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID);
155
+ } else {
156
+ did_gscid = ctx->devid;
157
+ pid_pscid = ctx->process_id;
158
+ }
159
+
160
+ if (get_field(evt, RISCV_IOMMU_IOHPMEVT_PV_PSCV)) {
161
+ /*
162
+ * If the transaction does not have a valid process_id, counter
163
+ * increments if device_id matches DID_GSCID. If the transaction
164
+ * has a valid process_id, counter increments if device_id
165
+ * matches DID_GSCID and process_id matches PID_PSCID. See
166
+ * IOMMU Specification, Chapter 5.23. Performance-monitoring
167
+ * event selector.
168
+ */
169
+ if (ctx->process_id &&
170
+ get_field(evt, RISCV_IOMMU_IOHPMEVT_PID_PSCID) != pid_pscid) {
171
+ continue;
172
+ }
173
+ }
174
+
175
+ if (get_field(evt, RISCV_IOMMU_IOHPMEVT_DV_GSCV)) {
176
+ uint32_t mask = ~0;
177
+
178
+ if (get_field(evt, RISCV_IOMMU_IOHPMEVT_DMASK)) {
179
+ /*
180
+ * 1001 1011 mask = GSCID
181
+ * 0000 0111 mask = mask ^ (mask + 1)
182
+ * 1111 1000 mask = ~mask;
183
+ */
184
+ mask = get_field(evt, RISCV_IOMMU_IOHPMEVT_DID_GSCID);
185
+ mask = mask ^ (mask + 1);
186
+ mask = ~mask;
187
+ }
188
+
189
+ if ((get_field(evt, RISCV_IOMMU_IOHPMEVT_DID_GSCID) & mask) !=
190
+ (did_gscid & mask)) {
191
+ continue;
192
+ }
193
+ }
194
+
195
+ hpm_incr_ctr(s, ctr_idx);
196
+ }
197
+}
198
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/hw/riscv/riscv-iommu.c
201
+++ b/hw/riscv/riscv-iommu.c
202
@@ -XXX,XX +XXX,XX @@
203
#define PPN_PHYS(ppn) ((ppn) << TARGET_PAGE_BITS)
204
#define PPN_DOWN(phy) ((phy) >> TARGET_PAGE_BITS)
205
206
-typedef struct RISCVIOMMUContext RISCVIOMMUContext;
207
typedef struct RISCVIOMMUEntry RISCVIOMMUEntry;
208
209
/* Device assigned I/O address space */
210
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUSpace {
211
QLIST_ENTRY(RISCVIOMMUSpace) list;
212
};
213
214
-/* Device translation context state. */
215
-struct RISCVIOMMUContext {
216
- uint64_t devid:24; /* Requester Id, AKA device_id */
217
- uint64_t process_id:20; /* Process ID. PASID for PCIe */
218
- uint64_t tc; /* Translation Control */
219
- uint64_t ta; /* Translation Attributes */
220
- uint64_t satp; /* S-Stage address translation and protection */
221
- uint64_t gatp; /* G-Stage address translation and protection */
222
- uint64_t msi_addr_mask; /* MSI filtering - address mask */
223
- uint64_t msi_addr_pattern; /* MSI filtering - address pattern */
224
- uint64_t msiptp; /* MSI redirection page table pointer */
225
-};
226
-
227
typedef enum RISCVIOMMUTransTag {
228
RISCV_IOMMU_TRANS_TAG_BY, /* Bypass */
229
RISCV_IOMMU_TRANS_TAG_SS, /* Single Stage */
230
@@ -XXX,XX +XXX,XX @@ static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type)
231
}
232
}
233
234
-static void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type)
235
+void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type)
236
{
237
uint32_t ipsr, icvec, vector;
238
239
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
240
}
241
}
242
243
+
244
+ if (pass == S_STAGE) {
245
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_S_VS_WALKS);
246
+ } else {
247
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_G_WALKS);
248
+ }
249
+
250
/* Read page table entry */
251
if (sc[pass].ptesize == 4) {
252
uint32_t pte32 = 0;
253
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx)
254
255
/* Device directory tree walk */
256
for (; depth-- > 0; ) {
257
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_DD_WALK);
258
/*
259
* Select device id index bits based on device directory tree level
260
* and device context format.
261
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx)
262
addr = PPN_PHYS(get_field(de, RISCV_IOMMU_DDTE_PPN));
263
}
264
265
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_DD_WALK);
266
+
267
/* index into device context entry page */
268
addr |= (ctx->devid * dc_len) & ~TARGET_PAGE_MASK;
269
270
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx)
271
}
272
273
for (depth = mode - RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8; depth-- > 0; ) {
274
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK);
275
+
276
/*
277
* Select process id index bits based on process directory tree
278
* level. See IOMMU Specification, 2.2. Process-Directory-Table.
279
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx)
280
addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PC_FSC_PPN));
281
}
282
283
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK);
284
+
285
/* Leaf entry in PDT */
286
addr |= (ctx->process_id << 4) & ~TARGET_PAGE_MASK;
287
if (dma_memory_read(s->target_as, addr, &dc.ta, sizeof(uint64_t) * 2,
288
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
289
GHashTable *iot_cache;
290
int fault;
291
292
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);
293
+
294
iot_cache = g_hash_table_ref(s->iot_cache);
295
/*
296
* TC[32] is reserved for custom extensions, used here to temporarily
297
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
298
299
/* Check for ATS request. */
300
if (iotlb->perm == IOMMU_NONE) {
301
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_ATS_RQ);
302
/* Check if ATS is disabled. */
303
if (!(ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS)) {
304
enable_pri = false;
305
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
306
goto done;
307
}
308
309
+ riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_TLB_MISS);
310
+
311
/* Translate using device directory / page table information. */
312
fault = riscv_iommu_spa_fetch(s, ctx, iotlb);
313
314
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
315
memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s,
316
"riscv-iommu-trap", ~0ULL);
317
address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
318
+
319
+ if (s->cap & RISCV_IOMMU_CAP_HPM) {
320
+ s->hpm_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
321
+ }
322
}
323
324
static void riscv_iommu_unrealize(DeviceState *dev)
325
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_unrealize(DeviceState *dev)
326
327
g_hash_table_unref(s->iot_cache);
328
g_hash_table_unref(s->ctx_cache);
329
+
330
+ if (s->cap & RISCV_IOMMU_CAP_HPM) {
331
+ g_hash_table_unref(s->hpm_event_ctr_map);
332
+ }
333
}
334
335
void riscv_iommu_reset(RISCVIOMMUState *s)
336
--
337
2.48.1
diff view generated by jsdifflib
New patch
[PULL 43/59] hw/riscv/riscv-iommu: instantiate hpm_timer
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
The next HPM related changes requires the HPM overflow timer to be
4
initialized by the riscv-iommu base emulation.
5
6
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
7
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20250224190826.1858473-6-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/riscv/riscv-iommu-hpm.h | 1 +
13
hw/riscv/riscv-iommu.h | 2 ++
14
hw/riscv/riscv-iommu-hpm.c | 36 ++++++++++++++++++++++++++++++++++++
15
hw/riscv/riscv-iommu.c | 3 +++
16
4 files changed, 42 insertions(+)
17
18
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/riscv/riscv-iommu-hpm.h
21
+++ b/hw/riscv/riscv-iommu-hpm.h
22
@@ -XXX,XX +XXX,XX @@
23
uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
24
void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
25
unsigned event_id);
26
+void riscv_iommu_hpm_timer_cb(void *priv);
27
28
#endif
29
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/riscv/riscv-iommu.h
32
+++ b/hw/riscv/riscv-iommu.h
33
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
34
QLIST_HEAD(, RISCVIOMMUSpace) spaces;
35
36
/* HPM cycle counter */
37
+ QEMUTimer *hpm_timer;
38
uint64_t hpmcycle_val; /* Current value of cycle register */
39
uint64_t hpmcycle_prev; /* Saved value of QEMU_CLOCK_VIRTUAL clock */
40
+ uint64_t irq_overflow_left; /* Value beyond INT64_MAX after overflow */
41
42
/* HPM event counters */
43
GHashTable *hpm_event_ctr_map; /* Mapping of events to counters */
44
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/riscv-iommu-hpm.c
47
+++ b/hw/riscv/riscv-iommu-hpm.c
48
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
49
hpm_incr_ctr(s, ctr_idx);
50
}
51
}
52
+
53
+/* Timer callback for cycle counter overflow. */
54
+void riscv_iommu_hpm_timer_cb(void *priv)
55
+{
56
+ RISCVIOMMUState *s = priv;
57
+ const uint32_t inhibit = riscv_iommu_reg_get32(
58
+ s, RISCV_IOMMU_REG_IOCOUNTINH);
59
+ uint32_t ovf;
60
+
61
+ if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
62
+ return;
63
+ }
64
+
65
+ if (s->irq_overflow_left > 0) {
66
+ uint64_t irq_trigger_at =
67
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->irq_overflow_left;
68
+ timer_mod_anticipate_ns(s->hpm_timer, irq_trigger_at);
69
+ s->irq_overflow_left = 0;
70
+ return;
71
+ }
72
+
73
+ ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
74
+ if (!get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY)) {
75
+ /*
76
+ * We don't need to set hpmcycle_val to zero and update hpmcycle_prev to
77
+ * current clock value. The way we calculate iohpmcycs will overflow
78
+ * and return the correct value. This avoids the need to synchronize
79
+ * timer callback and write callback.
80
+ */
81
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF,
82
+ RISCV_IOMMU_IOCOUNTOVF_CY, 0);
83
+ riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_IOHPMCYCLES,
84
+ RISCV_IOMMU_IOHPMCYCLES_OVF, 0);
85
+ riscv_iommu_notify(s, RISCV_IOMMU_INTR_PM);
86
+ }
87
+}
88
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/riscv/riscv-iommu.c
91
+++ b/hw/riscv/riscv-iommu.c
92
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
93
address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
94
95
if (s->cap & RISCV_IOMMU_CAP_HPM) {
96
+ s->hpm_timer =
97
+ timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_iommu_hpm_timer_cb, s);
98
s->hpm_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
99
}
100
}
101
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_unrealize(DeviceState *dev)
102
103
if (s->cap & RISCV_IOMMU_CAP_HPM) {
104
g_hash_table_unref(s->hpm_event_ctr_map);
105
+ timer_free(s->hpm_timer);
106
}
107
}
108
109
--
110
2.48.1
diff view generated by jsdifflib
New patch
[PULL 44/59] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(),
4
which is called during riscv_iommu_mmio_write() callback via a new
5
riscv_iommu_pricess_hpm_writes() helper.
6
7
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
8
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20250224190826.1858473-7-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/riscv-iommu-hpm.h | 1 +
14
hw/riscv/riscv-iommu-hpm.c | 60 ++++++++++++++++++++++++++++++++++++++
15
hw/riscv/riscv-iommu.c | 38 ++++++++++++++++++++++++
16
3 files changed, 99 insertions(+)
17
18
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/riscv/riscv-iommu-hpm.h
21
+++ b/hw/riscv/riscv-iommu-hpm.h
22
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
23
void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
24
unsigned event_id);
25
void riscv_iommu_hpm_timer_cb(void *priv);
26
+void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
27
28
#endif
29
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/riscv/riscv-iommu-hpm.c
32
+++ b/hw/riscv/riscv-iommu-hpm.c
33
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_hpm_timer_cb(void *priv)
34
riscv_iommu_notify(s, RISCV_IOMMU_INTR_PM);
35
}
36
}
37
+
38
+static void hpm_setup_timer(RISCVIOMMUState *s, uint64_t value)
39
+{
40
+ const uint32_t inhibit = riscv_iommu_reg_get32(
41
+ s, RISCV_IOMMU_REG_IOCOUNTINH);
42
+ uint64_t overflow_at, overflow_ns;
43
+
44
+ if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
45
+ return;
46
+ }
47
+
48
+ /*
49
+ * We are using INT64_MAX here instead to UINT64_MAX because cycle counter
50
+ * has 63-bit precision and INT64_MAX is the maximum it can store.
51
+ */
52
+ if (value) {
53
+ overflow_ns = INT64_MAX - value + 1;
54
+ } else {
55
+ overflow_ns = INT64_MAX;
56
+ }
57
+
58
+ overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
59
+
60
+ if (overflow_at > INT64_MAX) {
61
+ s->irq_overflow_left = overflow_at - INT64_MAX;
62
+ overflow_at = INT64_MAX;
63
+ }
64
+
65
+ timer_mod_anticipate_ns(s->hpm_timer, overflow_at);
66
+}
67
+
68
+/* Updates the internal cycle counter state when iocntinh:CY is changed. */
69
+void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh)
70
+{
71
+ const uint32_t inhibit = riscv_iommu_reg_get32(
72
+ s, RISCV_IOMMU_REG_IOCOUNTINH);
73
+
74
+ /* We only need to process CY bit toggle. */
75
+ if (!(inhibit ^ prev_cy_inh)) {
76
+ return;
77
+ }
78
+
79
+ if (!(inhibit & RISCV_IOMMU_IOCOUNTINH_CY)) {
80
+ /*
81
+ * Cycle counter is enabled. Just start the timer again and update
82
+ * the clock snapshot value to point to the current time to make
83
+ * sure iohpmcycles read is correct.
84
+ */
85
+ s->hpmcycle_prev = get_cycles();
86
+ hpm_setup_timer(s, s->hpmcycle_val);
87
+ } else {
88
+ /*
89
+ * Cycle counter is disabled. Stop the timer and update the cycle
90
+ * counter to record the current value which is last programmed
91
+ * value + the cycles passed so far.
92
+ */
93
+ s->hpmcycle_val = s->hpmcycle_val + (get_cycles() - s->hpmcycle_prev);
94
+ timer_del(s->hpm_timer);
95
+ }
96
+}
97
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/riscv/riscv-iommu.c
100
+++ b/hw/riscv/riscv-iommu.c
101
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_update_ipsr(RISCVIOMMUState *s, uint64_t data)
102
riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IPSR, ipsr_set, ipsr_clr);
103
}
104
105
+static void riscv_iommu_process_hpm_writes(RISCVIOMMUState *s,
106
+ uint32_t regb,
107
+ bool prev_cy_inh)
108
+{
109
+ switch (regb) {
110
+ case RISCV_IOMMU_REG_IOCOUNTINH:
111
+ riscv_iommu_process_iocntinh_cy(s, prev_cy_inh);
112
+ break;
113
+
114
+ case RISCV_IOMMU_REG_IOHPMCYCLES:
115
+ case RISCV_IOMMU_REG_IOHPMCYCLES + 4:
116
+ /* not yet implemented */
117
+ break;
118
+
119
+ case RISCV_IOMMU_REG_IOHPMEVT_BASE ...
120
+ RISCV_IOMMU_REG_IOHPMEVT(RISCV_IOMMU_IOCOUNT_NUM) + 4:
121
+ /* not yet implemented */
122
+ break;
123
+ }
124
+}
125
+
126
/*
127
* Write the resulting value of 'data' for the reg specified
128
* by 'reg_addr', after considering read-only/read-write/write-clear
129
@@ -XXX,XX +XXX,XX @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
130
uint32_t regb = addr & ~3;
131
uint32_t busy = 0;
132
uint64_t val = 0;
133
+ bool cy_inh = false;
134
135
if ((addr & (size - 1)) != 0) {
136
/* Unsupported MMIO alignment or access size */
137
@@ -XXX,XX +XXX,XX @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
138
busy = RISCV_IOMMU_TR_REQ_CTL_GO_BUSY;
139
break;
140
141
+ case RISCV_IOMMU_REG_IOCOUNTINH:
142
+ if (addr != RISCV_IOMMU_REG_IOCOUNTINH) {
143
+ break;
144
+ }
145
+ /* Store previous value of CY bit. */
146
+ cy_inh = !!(riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTINH) &
147
+ RISCV_IOMMU_IOCOUNTINH_CY);
148
+ break;
149
+
150
+
151
default:
152
break;
153
}
154
@@ -XXX,XX +XXX,XX @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
155
stl_le_p(&s->regs_rw[regb], rw | busy);
156
}
157
158
+ /* Process HPM writes and update any internal state if needed. */
159
+ if (regb >= RISCV_IOMMU_REG_IOCOUNTOVF &&
160
+ regb <= (RISCV_IOMMU_REG_IOHPMEVT(RISCV_IOMMU_IOCOUNT_NUM) + 4)) {
161
+ riscv_iommu_process_hpm_writes(s, regb, cy_inh);
162
+ }
163
+
164
if (process_fn) {
165
process_fn(s);
166
}
167
--
168
2.48.1
diff view generated by jsdifflib
New patch
[PULL 45/59] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
RISCV_IOMMU_REG_IOHPMCYCLES writes are done by
4
riscv_iommu_process_hpmcycle_write(), called by the mmio write callback
5
via riscv_iommu_process_hpm_writes().
6
7
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
8
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20250224190826.1858473-8-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/riscv-iommu-hpm.h | 1 +
14
hw/riscv/riscv-iommu-hpm.c | 19 +++++++++++++++++++
15
hw/riscv/riscv-iommu.c | 2 +-
16
3 files changed, 21 insertions(+), 1 deletion(-)
17
18
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/riscv/riscv-iommu-hpm.h
21
+++ b/hw/riscv/riscv-iommu-hpm.h
22
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
23
unsigned event_id);
24
void riscv_iommu_hpm_timer_cb(void *priv);
25
void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
26
+void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s);
27
28
#endif
29
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/riscv/riscv-iommu-hpm.c
32
+++ b/hw/riscv/riscv-iommu-hpm.c
33
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh)
34
timer_del(s->hpm_timer);
35
}
36
}
37
+
38
+void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s)
39
+{
40
+ const uint64_t val = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHPMCYCLES);
41
+ const uint32_t ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
42
+
43
+ /*
44
+ * Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES register.
45
+ */
46
+ if (get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY) &&
47
+ !get_field(val, RISCV_IOMMU_IOHPMCYCLES_OVF)) {
48
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, 0,
49
+ RISCV_IOMMU_IOCOUNTOVF_CY);
50
+ }
51
+
52
+ s->hpmcycle_val = val & ~RISCV_IOMMU_IOHPMCYCLES_OVF;
53
+ s->hpmcycle_prev = get_cycles();
54
+ hpm_setup_timer(s, s->hpmcycle_val);
55
+}
56
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/riscv/riscv-iommu.c
59
+++ b/hw/riscv/riscv-iommu.c
60
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_process_hpm_writes(RISCVIOMMUState *s,
61
62
case RISCV_IOMMU_REG_IOHPMCYCLES:
63
case RISCV_IOMMU_REG_IOHPMCYCLES + 4:
64
- /* not yet implemented */
65
+ riscv_iommu_process_hpmcycle_write(s);
66
break;
67
68
case RISCV_IOMMU_REG_IOHPMEVT_BASE ...
69
--
70
2.48.1
diff view generated by jsdifflib
New patch
[PULL 46/59] hw/riscv/riscv-iommu: add hpm events mmio write
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
To support hpm events mmio writes, done via
4
riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters'
5
IOMMU property that are used to determine the amount of counters
6
available in the IOMMU.
7
8
Note that everything we did so far didn't change any IOMMU behavior
9
because we're still not advertising HPM capability to software. This
10
will be done in the next patch.
11
12
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
13
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Acked-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-ID: <20250224190826.1858473-9-dbarboza@ventanamicro.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
hw/riscv/riscv-iommu-hpm.h | 1 +
19
hw/riscv/riscv-iommu.h | 1 +
20
hw/riscv/riscv-iommu-hpm.c | 88 ++++++++++++++++++++++++++++++++++++++
21
hw/riscv/riscv-iommu.c | 4 +-
22
4 files changed, 93 insertions(+), 1 deletion(-)
23
24
diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/riscv/riscv-iommu-hpm.h
27
+++ b/hw/riscv/riscv-iommu-hpm.h
28
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
29
void riscv_iommu_hpm_timer_cb(void *priv);
30
void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
31
void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s);
32
+void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg);
33
34
#endif
35
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/riscv/riscv-iommu.h
38
+++ b/hw/riscv/riscv-iommu.h
39
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
40
41
/* HPM event counters */
42
GHashTable *hpm_event_ctr_map; /* Mapping of events to counters */
43
+ uint8_t hpm_cntrs;
44
};
45
46
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
47
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/riscv/riscv-iommu-hpm.c
50
+++ b/hw/riscv/riscv-iommu-hpm.c
51
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s)
52
s->hpmcycle_prev = get_cycles();
53
hpm_setup_timer(s, s->hpmcycle_val);
54
}
55
+
56
+static inline bool check_valid_event_id(unsigned event_id)
57
+{
58
+ return event_id > RISCV_IOMMU_HPMEVENT_INVALID &&
59
+ event_id < RISCV_IOMMU_HPMEVENT_MAX;
60
+}
61
+
62
+static gboolean hpm_event_equal(gpointer key, gpointer value, gpointer udata)
63
+{
64
+ uint32_t *pair = udata;
65
+
66
+ if (GPOINTER_TO_UINT(value) & (1 << pair[0])) {
67
+ pair[1] = GPOINTER_TO_UINT(key);
68
+ return true;
69
+ }
70
+
71
+ return false;
72
+}
73
+
74
+/* Caller must check ctr_idx against hpm_ctrs to see if its supported or not. */
75
+static void update_event_map(RISCVIOMMUState *s, uint64_t value,
76
+ uint32_t ctr_idx)
77
+{
78
+ unsigned event_id = get_field(value, RISCV_IOMMU_IOHPMEVT_EVENT_ID);
79
+ uint32_t pair[2] = { ctr_idx, RISCV_IOMMU_HPMEVENT_INVALID };
80
+ uint32_t new_value = 1 << ctr_idx;
81
+ gpointer data;
82
+
83
+ /*
84
+ * If EventID field is RISCV_IOMMU_HPMEVENT_INVALID
85
+ * remove the current mapping.
86
+ */
87
+ if (event_id == RISCV_IOMMU_HPMEVENT_INVALID) {
88
+ data = g_hash_table_find(s->hpm_event_ctr_map, hpm_event_equal, pair);
89
+
90
+ new_value = GPOINTER_TO_UINT(data) & ~(new_value);
91
+ if (new_value != 0) {
92
+ g_hash_table_replace(s->hpm_event_ctr_map,
93
+ GUINT_TO_POINTER(pair[1]),
94
+ GUINT_TO_POINTER(new_value));
95
+ } else {
96
+ g_hash_table_remove(s->hpm_event_ctr_map,
97
+ GUINT_TO_POINTER(pair[1]));
98
+ }
99
+
100
+ return;
101
+ }
102
+
103
+ /* Update the counter mask if the event is already enabled. */
104
+ if (g_hash_table_lookup_extended(s->hpm_event_ctr_map,
105
+ GUINT_TO_POINTER(event_id),
106
+ NULL,
107
+ &data)) {
108
+ new_value |= GPOINTER_TO_UINT(data);
109
+ }
110
+
111
+ g_hash_table_insert(s->hpm_event_ctr_map,
112
+ GUINT_TO_POINTER(event_id),
113
+ GUINT_TO_POINTER(new_value));
114
+}
115
+
116
+void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg)
117
+{
118
+ const uint32_t ctr_idx = (evt_reg - RISCV_IOMMU_REG_IOHPMEVT_BASE) >> 3;
119
+ const uint32_t ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
120
+ uint64_t val = riscv_iommu_reg_get64(s, evt_reg);
121
+
122
+ if (ctr_idx >= s->hpm_cntrs) {
123
+ return;
124
+ }
125
+
126
+ /* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMEVT register. */
127
+ if (get_field(ovf, BIT(ctr_idx + 1)) &&
128
+ !get_field(val, RISCV_IOMMU_IOHPMEVT_OF)) {
129
+ /* +1 to offset CYCLE register OF bit. */
130
+ riscv_iommu_reg_mod32(
131
+ s, RISCV_IOMMU_REG_IOCOUNTOVF, 0, BIT(ctr_idx + 1));
132
+ }
133
+
134
+ if (!check_valid_event_id(get_field(val, RISCV_IOMMU_IOHPMEVT_EVENT_ID))) {
135
+ /* Reset EventID (WARL) field to invalid. */
136
+ val = set_field(val, RISCV_IOMMU_IOHPMEVT_EVENT_ID,
137
+ RISCV_IOMMU_HPMEVENT_INVALID);
138
+ riscv_iommu_reg_set64(s, evt_reg, val);
139
+ }
140
+
141
+ update_event_map(s, val, ctr_idx);
142
+}
143
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/riscv/riscv-iommu.c
146
+++ b/hw/riscv/riscv-iommu.c
147
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_process_hpm_writes(RISCVIOMMUState *s,
148
149
case RISCV_IOMMU_REG_IOHPMEVT_BASE ...
150
RISCV_IOMMU_REG_IOHPMEVT(RISCV_IOMMU_IOCOUNT_NUM) + 4:
151
- /* not yet implemented */
152
+ riscv_iommu_process_hpmevt_write(s, regb & ~7);
153
break;
154
}
155
}
156
@@ -XXX,XX +XXX,XX @@ static const Property riscv_iommu_properties[] = {
157
DEFINE_PROP_BOOL("g-stage", RISCVIOMMUState, enable_g_stage, TRUE),
158
DEFINE_PROP_LINK("downstream-mr", RISCVIOMMUState, target_mr,
159
TYPE_MEMORY_REGION, MemoryRegion *),
160
+ DEFINE_PROP_UINT8("hpm-counters", RISCVIOMMUState, hpm_cntrs,
161
+ RISCV_IOMMU_IOCOUNT_NUM),
162
};
163
164
static void riscv_iommu_class_init(ObjectClass *klass, void* data)
165
--
166
2.48.1
diff view generated by jsdifflib
New patch
[PULL 47/59] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap
1
From: Tomasz Jeznach <tjeznach@rivosinc.com>
1
2
3
Now that we have every piece in place we can advertise CAP_HTM to
4
software, allowing any HPM aware driver to make use of the counters.
5
6
HPM is enabled/disabled via the 'hpm-counters' attribute. Default value
7
is 31, max value is also 31. Setting it to zero will disable HPM
8
support.
9
10
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
11
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-ID: <20250224190826.1858473-10-dbarboza@ventanamicro.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
hw/riscv/riscv-iommu.c | 21 +++++++++++++++++++++
17
1 file changed, 21 insertions(+)
18
19
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/riscv/riscv-iommu.c
22
+++ b/hw/riscv/riscv-iommu.c
23
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
24
RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
25
}
26
27
+ if (s->hpm_cntrs > 0) {
28
+ /* Clip number of HPM counters to maximum supported (31). */
29
+ if (s->hpm_cntrs > RISCV_IOMMU_IOCOUNT_NUM) {
30
+ s->hpm_cntrs = RISCV_IOMMU_IOCOUNT_NUM;
31
+ }
32
+ /* Enable hardware performance monitor interface */
33
+ s->cap |= RISCV_IOMMU_CAP_HPM;
34
+ }
35
+
36
/* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */
37
s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
38
RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE);
39
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
40
RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
41
}
42
43
+ /* If HPM registers are enabled. */
44
+ if (s->cap & RISCV_IOMMU_CAP_HPM) {
45
+ /* +1 for cycle counter bit. */
46
+ stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOCOUNTINH],
47
+ ~((2 << s->hpm_cntrs) - 1));
48
+ stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCYCLES], 0);
49
+ memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCTR_BASE],
50
+ 0x00, s->hpm_cntrs * 8);
51
+ memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMEVT_BASE],
52
+ 0x00, s->hpm_cntrs * 8);
53
+ }
54
+
55
/* Memory region for downstream access, if specified. */
56
if (s->target_mr) {
57
s->target_as = g_new0(AddressSpace, 1);
58
--
59
2.48.1
diff view generated by jsdifflib
New patch
[PULL 48/59] hw/riscv: add IOMMU HPM trace events
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Add a handful of trace events to allow for an easier time debugging the
4
HPM feature.
5
6
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-ID: <20250224190826.1858473-11-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/riscv/riscv-iommu-hpm.c | 10 ++++++++++
12
hw/riscv/trace-events | 5 +++++
13
2 files changed, 15 insertions(+)
14
15
diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/riscv-iommu-hpm.c
18
+++ b/hw/riscv/riscv-iommu-hpm.c
19
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
20
const uint64_t ctr_prev = s->hpmcycle_prev;
21
const uint64_t ctr_val = s->hpmcycle_val;
22
23
+ trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val);
24
+
25
if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
26
/*
27
* Counter should not increment if inhibit bit is set. We can't really
28
@@ -XXX,XX +XXX,XX @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)
29
cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
30
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
31
32
+ trace_riscv_iommu_hpm_incr_ctr(cntr_val);
33
+
34
/* Handle the overflow scenario. */
35
if (cntr_val == UINT64_MAX) {
36
/*
37
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh)
38
return;
39
}
40
41
+ trace_riscv_iommu_hpm_iocntinh_cy(prev_cy_inh);
42
+
43
if (!(inhibit & RISCV_IOMMU_IOCOUNTINH_CY)) {
44
/*
45
* Cycle counter is enabled. Just start the timer again and update
46
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s)
47
const uint64_t val = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHPMCYCLES);
48
const uint32_t ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
49
50
+ trace_riscv_iommu_hpm_cycle_write(ovf, val);
51
+
52
/*
53
* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES register.
54
*/
55
@@ -XXX,XX +XXX,XX @@ void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg)
56
return;
57
}
58
59
+ trace_riscv_iommu_hpm_evt_write(ctr_idx, ovf, val);
60
+
61
/* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMEVT register. */
62
if (get_field(ovf, BIT(ctr_idx + 1)) &&
63
!get_field(val, RISCV_IOMMU_IOHPMEVT_OF)) {
64
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/riscv/trace-events
67
+++ b/hw/riscv/trace-events
68
@@ -XXX,XX +XXX,XX @@ riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
69
riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%"PRIx64" msi_data 0x%x result %u"
70
riscv_iommu_sys_reset_hold(int reset_type) "reset type %d"
71
riscv_iommu_pci_reset_hold(int reset_type) "reset type %d"
72
+riscv_iommu_hpm_read(uint64_t cycle, uint32_t inhibit, uint64_t ctr_prev, uint64_t ctr_val) "cycle 0x%"PRIx64" inhibit 0x%x ctr_prev 0x%"PRIx64" ctr_val 0x%"PRIx64
73
+riscv_iommu_hpm_incr_ctr(uint64_t cntr_val) "cntr_val 0x%"PRIx64
74
+riscv_iommu_hpm_iocntinh_cy(bool prev_cy_inh) "prev_cy_inh %d"
75
+riscv_iommu_hpm_cycle_write(uint32_t ovf, uint64_t val) "ovf 0x%x val 0x%"PRIx64
76
+riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf, uint64_t val) "ctr_idx 0x%x ovf 0x%x val 0x%"PRIx64
77
--
78
2.48.1
diff view generated by jsdifflib
New patch
[PULL 49/59] docs/specs/riscv-iommu.rst: add HPM support info
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-ID: <20250224190826.1858473-12-dbarboza@ventanamicro.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
8
docs/specs/riscv-iommu.rst | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/specs/riscv-iommu.rst
14
+++ b/docs/specs/riscv-iommu.rst
15
@@ -XXX,XX +XXX,XX @@ Several options are available to control the capabilities of the device, namely:
16
- "off" (Out-of-reset translation mode: 'on' for DMA disabled, 'off' for 'BARE' (passthrough))
17
- "s-stage": enable s-stage support
18
- "g-stage": enable g-stage support
19
+- "hpm-counters": number of hardware performance counters available. Maximum value is 31.
20
+ Default value is 31. Use 0 (zero) to disable HPM support
21
22
riscv-iommu-sys device
23
----------------------
24
--
25
2.48.1
diff view generated by jsdifflib
New patch
[PULL 50/59] target/riscv/kvm: Add some exts support
1
From: Quan Zhou <zhouquan@iscas.ac.cn>
1
2
3
When the Sscofpmf/Svade/Svadu/Smnpm/Ssnpm exts is available
4
expose it to the guest so that guest can use it.
5
6
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <303616ccad2b5309768157b50d93b3e89fecc9cb.1740371468.git.zhouquan@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/kvm/kvm-cpu.c | 5 +++++
12
1 file changed, 5 insertions(+)
13
14
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/kvm/kvm-cpu.c
17
+++ b/target/riscv/kvm/kvm-cpu.c
18
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
19
KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED),
20
KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH),
21
KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT),
22
+ KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM),
23
KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN),
24
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
25
+ KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF),
26
+ KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM),
27
KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
28
+ KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE),
29
+ KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU),
30
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
31
KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT),
32
KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
33
--
34
2.48.1
diff view generated by jsdifflib
New patch
[PULL 51/59] binfmt: Shuffle things around
1
From: Andrea Bolognani <abologna@redhat.com>
1
2
3
This should make no difference from the functional point of
4
view and it's just preparation for upcoming changes.
5
6
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
9
Message-ID: <20250127182924.103510-2-abologna@redhat.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
scripts/qemu-binfmt-conf.sh | 17 ++++++++++-------
13
1 file changed, 10 insertions(+), 7 deletions(-)
14
15
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
16
index XXXXXXX..XXXXXXX 100755
17
--- a/scripts/qemu-binfmt-conf.sh
18
+++ b/scripts/qemu-binfmt-conf.sh
19
@@ -XXX,XX +XXX,XX @@ qemu_set_binfmts() {
20
mask=$(eval echo \$${cpu}_mask)
21
family=$(eval echo \$${cpu}_family)
22
23
+ target="$cpu"
24
+ if [ "$cpu" = "i486" ] ; then
25
+ target="i386"
26
+ fi
27
+
28
+ qemu="$QEMU_PATH/qemu-$target$QEMU_SUFFIX"
29
+
30
if [ "$magic" = "" ] || [ "$mask" = "" ] || [ "$family" = "" ] ; then
31
echo "INTERNAL ERROR: unknown cpu $cpu" 1>&2
32
continue
33
fi
34
35
- qemu="$QEMU_PATH/qemu-$cpu"
36
- if [ "$cpu" = "i486" ] ; then
37
- qemu="$QEMU_PATH/qemu-i386"
38
+ if [ "$host_family" = "$family" ] ; then
39
+ continue
40
fi
41
42
- qemu="$qemu$QEMU_SUFFIX"
43
- if [ "$host_family" != "$family" ] ; then
44
- $BINFMT_SET
45
- fi
46
+ $BINFMT_SET
47
done
48
}
49
50
--
51
2.48.1
diff view generated by jsdifflib
New patch
[PULL 52/59] binfmt: Normalize host CPU architecture
1
From: Andrea Bolognani <abologna@redhat.com>
1
2
3
Right now information regarding the family each CPU type belongs
4
to is recorded in two places: the large data table at the top of
5
the script, and the qemu_host_family() function.
6
7
We can make things better by mapping host CPU architecture to
8
QEMU target in the few cases where the two don't already match
9
and then using the data table to look up the family, same as
10
we're already doing for the guest CPU architecture.
11
12
Being able to reason in terms of QEMU target regardless of
13
whether we're looking at the host or guest CPU architecture will
14
come in handy to implement upcoming changes.
15
16
A couple of entries are dropped in the process: BePC and Power
17
Macintosh. I'm quite certain neither of those have ever been
18
reported as CPU architectures by Linux. I believe many more of
19
the entries that are carried forward could be dropped as well,
20
but I don't have the same level of confidence there so I
21
decided to play it safe just in case.
22
23
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
26
Message-ID: <20250127182924.103510-3-abologna@redhat.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
scripts/qemu-binfmt-conf.sh | 44 +++++++++++++++++++++----------------
30
1 file changed, 25 insertions(+), 19 deletions(-)
31
32
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
33
index XXXXXXX..XXXXXXX 100755
34
--- a/scripts/qemu-binfmt-conf.sh
35
+++ b/scripts/qemu-binfmt-conf.sh
36
@@ -XXX,XX +XXX,XX @@ loongarch64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x
37
loongarch64_mask='\xff\xff\xff\xff\xff\xff\xff\xfc\x00\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
38
loongarch64_family=loongarch
39
40
-qemu_get_family() {
41
- cpu=${HOST_ARCH:-$(uname -m)}
42
+# Converts the name of a host CPU architecture to the corresponding QEMU
43
+# target.
44
+#
45
+# FIXME: This can probably be simplified a lot by dropping most entries.
46
+# Remember that the script is only used on Linux, so we only need to
47
+# handle the strings Linux uses to report the host CPU architecture.
48
+qemu_normalize() {
49
+ cpu="$1"
50
case "$cpu" in
51
- amd64|i386|i486|i586|i686|i86pc|BePC|x86_64)
52
+ i[3-6]86)
53
echo "i386"
54
;;
55
- mips*)
56
- echo "mips"
57
+ amd64)
58
+ echo "x86_64"
59
;;
60
- "Power Macintosh"|ppc64|powerpc|ppc)
61
+ powerpc)
62
echo "ppc"
63
;;
64
- ppc64el|ppc64le)
65
- echo "ppcle"
66
+ ppc64el)
67
+ echo "ppc64le"
68
;;
69
- arm|armel|armhf|arm64|armv[4-9]*l|aarch64)
70
+ armel|armhf|armv[4-9]*l)
71
echo "arm"
72
;;
73
- armeb|armv[4-9]*b|aarch64_be)
74
+ armv[4-9]*b)
75
echo "armeb"
76
;;
77
- sparc*)
78
- echo "sparc"
79
- ;;
80
- riscv*)
81
- echo "riscv"
82
- ;;
83
- loongarch*)
84
- echo "loongarch"
85
+ arm64)
86
+ echo "aarch64"
87
;;
88
*)
89
echo "$cpu"
90
@@ -XXX,XX +XXX,XX @@ EOF
91
92
qemu_set_binfmts() {
93
# probe cpu type
94
- host_family=$(qemu_get_family)
95
+ host_cpu=$(qemu_normalize ${HOST_ARCH:-$(uname -m)})
96
+ host_family=$(eval echo \$${host_cpu}_family)
97
+
98
+ if [ "$host_family" = "" ] ; then
99
+ echo "INTERNAL ERROR: unknown host cpu $host_cpu" 1>&2
100
+ exit 1
101
+ fi
102
103
# register the interpreter for each cpu except for the native one
104
105
--
106
2.48.1
diff view generated by jsdifflib
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
[PULL 53/59] binfmt: Add --ignore-family option
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Andrea Bolognani <abologna@redhat.com>
2
2
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
3
Until now, the script has worked under the assumption that a
4
the address bytes. Note only SPI mode is supported by SST flashes.
4
host CPU can run binaries targeting any CPU in the same family.
5
That's a fair enough assumption when it comes to running i386
6
binaries on x86_64, but it doesn't quite apply in the general
7
case.
5
8
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
9
For example, while riscv64 CPUs could theoretically run riscv32
10
applications natively, in practice there exist few (if any?)
11
CPUs that implement the necessary silicon; moreover, even if you
12
had one such CPU, your host OS would most likely not have
13
enabled the necessary kernel bits.
7
14
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
15
This new option gives distro packagers the ability to opt out of
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
the assumption, likely on a per-architecture basis, and make
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
17
things work out of the box for a larger fraction of their user
18
base.
19
20
As an interesting side effect, this makes it possible to enable
21
execution of 64-bit binaries on 32-bit CPUs of the same family,
22
which is a perfectly valid use case that apparently hadn't been
23
considered until now.
24
25
Link: https://src.fedoraproject.org/rpms/qemu/pull-request/72
26
Thanks: David Abdurachmanov <davidlt@rivosinc.com>
27
Thanks: Daniel P. Berrangé <berrange@redhat.com>
28
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
29
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
31
Message-ID: <20250127182924.103510-4-abologna@redhat.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
33
---
13
hw/block/m25p80.c | 3 +++
34
scripts/qemu-binfmt-conf.sh | 19 ++++++++++++++++---
14
1 file changed, 3 insertions(+)
35
1 file changed, 16 insertions(+), 3 deletions(-)
15
36
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
37
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
17
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100755
18
--- a/hw/block/m25p80.c
39
--- a/scripts/qemu-binfmt-conf.sh
19
+++ b/hw/block/m25p80.c
40
+++ b/scripts/qemu-binfmt-conf.sh
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
41
@@ -XXX,XX +XXX,XX @@ Usage: qemu-binfmt-conf.sh [--qemu-path PATH][--debian][--systemd CPU]
21
s->needed_bytes = get_addr_length(s);
42
--persistent: if yes, the interpreter is loaded when binfmt is
22
switch (get_man(s)) {
43
configured and remains in memory. All future uses
23
/* Dummy cycles - modeled with bytes writes instead of bits */
44
are cloned from the open file.
24
+ case MAN_SST:
45
+ --ignore-family: if yes, it is assumed that the host CPU (e.g. riscv64)
25
+ s->needed_bytes += 1;
46
+ can't natively run programs targeting a CPU that is
26
+ break;
47
+ part of the same family (e.g. riscv32).
27
case MAN_WINBOND:
48
--preserve-argv0 preserve argv[0]
28
s->needed_bytes += 8;
49
29
break;
50
To import templates with update-binfmts, use :
51
@@ -XXX,XX +XXX,XX @@ qemu_set_binfmts() {
52
fi
53
54
if [ "$host_family" = "$family" ] ; then
55
- continue
56
+ # When --ignore-family is used, we have to generate rules even
57
+ # for targets that are in the same family as the host CPU. The
58
+ # only exception is of course when the CPU types exactly match
59
+ if [ "$target" = "$host_cpu" ] || [ "$IGNORE_FAMILY" = "no" ] ; then
60
+ continue
61
+ fi
62
fi
63
64
$BINFMT_SET
65
@@ -XXX,XX +XXX,XX @@ CREDENTIAL=no
66
PERSISTENT=no
67
PRESERVE_ARG0=no
68
QEMU_SUFFIX=""
69
+IGNORE_FAMILY=no
70
71
_longopts="debian,systemd:,qemu-path:,qemu-suffix:,exportdir:,help,credential:,\
72
-persistent:,preserve-argv0:"
73
-options=$(getopt -o ds:Q:S:e:hc:p:g:F: -l ${_longopts} -- "$@")
74
+persistent:,preserve-argv0:,ignore-family:"
75
+options=$(getopt -o ds:Q:S:e:hc:p:g:F:i: -l ${_longopts} -- "$@")
76
eval set -- "$options"
77
78
while true ; do
79
@@ -XXX,XX +XXX,XX @@ while true ; do
80
shift
81
PRESERVE_ARG0="$1"
82
;;
83
+ -i|--ignore-family)
84
+ shift
85
+ IGNORE_FAMILY="$1"
86
+ ;;
87
*)
88
break
89
;;
30
--
90
--
31
2.30.1
91
2.48.1
32
92
33
93
diff view generated by jsdifflib
New patch
[PULL 54/59] hw/intc/imsic: refine the IMSIC realize
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
1
2
3
When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs
4
and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC
5
trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in
6
kernel.
7
8
This patch also move the code that claim the CPU interrupts to the
9
beginning of IMSIC realization. This can avoid the unnecessary resource
10
allocation before checking failed.
11
12
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-ID: <20250224025722.3999-2-yongxuan.wang@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
hw/intc/riscv_imsic.c | 47 ++++++++++++++++++++++++-------------------
18
1 file changed, 26 insertions(+), 21 deletions(-)
19
20
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/riscv_imsic.c
23
+++ b/hw/intc/riscv_imsic.c
24
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
25
CPUState *cpu = cpu_by_arch_id(imsic->hartid);
26
CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
27
28
+ /* Claim the CPU interrupt to be triggered by this IMSIC */
29
+ if (riscv_cpu_claim_interrupts(rcpu,
30
+ (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
31
+ error_setg(errp, "%s already claimed",
32
+ (imsic->mmode) ? "MEIP" : "SEIP");
33
+ return;
34
+ }
35
+
36
if (!kvm_irqchip_in_kernel()) {
37
+ /* Create output IRQ lines */
38
+ imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
39
+ qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
40
+
41
imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
42
imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
43
imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
44
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
45
IMSIC_MMIO_SIZE(imsic->num_pages));
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
47
48
- /* Claim the CPU interrupt to be triggered by this IMSIC */
49
- if (riscv_cpu_claim_interrupts(rcpu,
50
- (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
51
- error_setg(errp, "%s already claimed",
52
- (imsic->mmode) ? "MEIP" : "SEIP");
53
- return;
54
- }
55
-
56
- /* Create output IRQ lines */
57
- imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
58
- qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
59
-
60
/* Force select AIA feature and setup CSR read-modify-write callback */
61
if (env) {
62
if (!imsic->mmode) {
63
@@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
64
} else {
65
rcpu->cfg.ext_smaia = true;
66
}
67
- riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
68
- riscv_imsic_rmw, imsic);
69
+
70
+ if (!kvm_irqchip_in_kernel()) {
71
+ riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
72
+ riscv_imsic_rmw, imsic);
73
+ }
74
}
75
76
msi_nonbroken = true;
77
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
78
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
79
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
80
81
- for (i = 0; i < num_pages; i++) {
82
- if (!i) {
83
- qdev_connect_gpio_out_named(dev, NULL, i,
84
- qdev_get_gpio_in(DEVICE(cpu),
85
+ if (!kvm_irqchip_in_kernel()) {
86
+ for (i = 0; i < num_pages; i++) {
87
+ if (!i) {
88
+ qdev_connect_gpio_out_named(dev, NULL, i,
89
+ qdev_get_gpio_in(DEVICE(cpu),
90
(mmode) ? IRQ_M_EXT : IRQ_S_EXT));
91
- } else {
92
- qdev_connect_gpio_out_named(dev, NULL, i,
93
- qdev_get_gpio_in(DEVICE(cpu),
94
+ } else {
95
+ qdev_connect_gpio_out_named(dev, NULL, i,
96
+ qdev_get_gpio_in(DEVICE(cpu),
97
IRQ_LOCAL_MAX + i - 1));
98
+ }
99
}
100
}
101
102
--
103
2.48.1
diff view generated by jsdifflib
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
[PULL 55/59] hw/intc/aplic: refine the APLIC realize
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
3
When the APLIC is emulated in the kernel, the GPIO output lines to CPUs
4
the newest received byte. The rx_level variable is added to allow the use of
4
can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs.
5
the existing OpenTitan driver libraries.
6
5
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
6
This patch also move the code that claim the CPU interrupts to the
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
beginning of APLIC realization. This can avoid the unnecessary resource
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
8
allocation before checking failed.
9
10
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-ID: <20250224025722.3999-3-yongxuan.wang@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
include/hw/char/ibex_uart.h | 4 ++++
15
hw/intc/riscv_aplic.c | 49 +++++++++++++++++++++++--------------------
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
16
1 file changed, 26 insertions(+), 23 deletions(-)
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
17
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
18
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
20
--- a/hw/intc/riscv_aplic.c
19
+++ b/include/hw/char/ibex_uart.h
21
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
22
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
23
RISCVAPLICState *aplic = RISCV_APLIC(dev);
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
24
23
REG32(FIFO_STATUS, 0x20)
25
if (riscv_use_emulated_aplic(aplic->msimode)) {
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
26
+ /* Create output IRQ lines for non-MSI mode */
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
27
+ if (!aplic->msimode) {
26
REG32(OVRD, 0x24)
28
+ /* Claim the CPU interrupt to be triggered by this APLIC */
27
REG32(VAL, 0x28)
29
+ for (i = 0; i < aplic->num_harts; i++) {
28
REG32(TIMEOUT_CTRL, 0x2c)
30
+ RISCVCPU *cpu;
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
31
uint32_t tx_level;
32
33
+ uint32_t rx_level;
34
+
31
+
35
QEMUTimer *fifo_trigger_handle;
32
+ cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
36
uint64_t char_tx_time;
33
+ if (riscv_cpu_claim_interrupts(cpu,
37
34
+ (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
35
+ error_report("%s already claimed",
39
index XXXXXXX..XXXXXXX 100644
36
+ (aplic->mmode) ? "MEIP" : "SEIP");
40
--- a/hw/char/ibex_uart.c
37
+ exit(1);
41
+++ b/hw/char/ibex_uart.c
38
+ }
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
39
+ }
43
{
40
+
44
IbexUartState *s = opaque;
41
+ aplic->external_irqs = g_malloc(sizeof(qemu_irq) *
45
42
+ aplic->num_harts);
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
43
+ qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
44
+ }
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
45
+
49
return 1;
46
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
47
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
48
aplic->state = g_new0(uint32_t, aplic->num_irqs);
49
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
50
}
50
}
51
}
51
52
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
53
- /* Create output IRQ lines for non-MSI mode */
53
54
- if (!aplic->msimode) {
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
- aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
- qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
56
+ /* The RXFULL is set after receiving a single byte
57
-
57
+ * as the FIFO buffers are not yet implemented.
58
- /* Claim the CPU interrupt to be triggered by this APLIC */
58
+ */
59
- for (i = 0; i < aplic->num_harts; i++) {
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
- RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
60
+ s->rx_level += 1;
61
- if (riscv_cpu_claim_interrupts(cpu,
61
62
- (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
62
if (size > rx_fifo_level) {
63
- error_report("%s already claimed",
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
- (aplic->mmode) ? "MEIP" : "SEIP");
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
- exit(1);
65
s->uart_timeout_ctrl = 0x00000000;
66
- }
66
67
- }
67
s->tx_level = 0;
68
- }
68
+ s->rx_level = 0;
69
-
69
70
msi_nonbroken = true;
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
}
71
72
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
73
74
74
case R_RDATA:
75
if (riscv_use_emulated_aplic(msimode)) {
75
retvalue = s->uart_rdata;
76
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
- }
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
78
qemu_chr_fe_accept_input(&s->chr);
79
- if (!msimode) {
79
80
- for (i = 0; i < num_harts; i++) {
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- CPUState *cpu = cpu_by_arch_id(hartid_base + i);
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ if (!msimode) {
82
+ s->rx_level -= 1;
83
+ for (i = 0; i < num_harts; i++) {
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
84
+ if (s->rx_level == 0) {
85
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
- qdev_connect_gpio_out_named(dev, NULL, i,
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
- qdev_get_gpio_in(DEVICE(cpu),
88
+ qdev_connect_gpio_out_named(dev, NULL, i,
89
+ qdev_get_gpio_in(DEVICE(cpu),
90
(mmode) ? IRQ_M_EXT : IRQ_S_EXT));
87
+ }
91
+ }
88
}
92
}
89
break;
93
}
90
case R_WDATA:
94
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
95
--
110
2.30.1
96
2.48.1
111
112
diff view generated by jsdifflib
New patch
[PULL 56/59] hw/intc/aplic: refine kvm_msicfgaddr
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
1
2
3
Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr.
4
5
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Message-ID: <20250224025722.3999-4-yongxuan.wang@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
hw/intc/riscv_aplic.c | 24 +++++++++++++-----------
11
1 file changed, 13 insertions(+), 11 deletions(-)
12
13
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/riscv_aplic.c
16
+++ b/hw/intc/riscv_aplic.c
17
@@ -XXX,XX +XXX,XX @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
18
{
19
#ifdef CONFIG_KVM
20
if (riscv_use_emulated_aplic(aplic->msimode)) {
21
+ addr >>= APLIC_xMSICFGADDR_PPN_SHIFT;
22
aplic->kvm_msicfgaddr = extract64(addr, 0, 32);
23
- aplic->kvm_msicfgaddrH = extract64(addr, 32, 32);
24
+ aplic->kvm_msicfgaddrH = extract64(addr, 32, 32) &
25
+ APLIC_xMSICFGADDRH_VALID_MASK;
26
}
27
#endif
28
}
29
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
30
}
31
}
32
33
- if (aplic->mmode) {
34
- msicfgaddr = aplic_m->mmsicfgaddr;
35
- msicfgaddrH = aplic_m->mmsicfgaddrH;
36
+ if (aplic->kvm_splitmode) {
37
+ msicfgaddr = aplic->kvm_msicfgaddr;
38
+ msicfgaddrH = ((uint64_t)aplic->kvm_msicfgaddrH << 32);
39
} else {
40
- msicfgaddr = aplic_m->smsicfgaddr;
41
- msicfgaddrH = aplic_m->smsicfgaddrH;
42
+ if (aplic->mmode) {
43
+ msicfgaddr = aplic_m->mmsicfgaddr;
44
+ msicfgaddrH = aplic_m->mmsicfgaddrH;
45
+ } else {
46
+ msicfgaddr = aplic_m->smsicfgaddr;
47
+ msicfgaddrH = aplic_m->smsicfgaddrH;
48
+ }
49
}
50
51
lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
52
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
53
addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
54
addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
55
56
- if (aplic->kvm_splitmode) {
57
- addr |= aplic->kvm_msicfgaddr;
58
- addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32);
59
- }
60
-
61
address_space_stl_le(&address_space_memory, addr,
62
eiid, MEMTXATTRS_UNSPECIFIED, &result);
63
if (result != MEMTX_OK) {
64
--
65
2.48.1
diff view generated by jsdifflib
New patch
[PULL 57/59] target/riscv/cpu: remove unneeded !kvm_enabled() check
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Remove the !kvm_enabled() check in kvm_riscv_reset_vcpu() since the
4
function is already being gated by kvm_enabled() in
5
riscv_cpu_reset_hold().
6
7
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20250224123120.1644186-2-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/kvm/kvm-cpu.c | 3 ---
14
1 file changed, 3 deletions(-)
15
16
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/kvm/kvm-cpu.c
19
+++ b/target/riscv/kvm/kvm-cpu.c
20
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
21
CPURISCVState *env = &cpu->env;
22
int i;
23
24
- if (!kvm_enabled()) {
25
- return;
26
- }
27
for (i = 0; i < 32; i++) {
28
env->gpr[i] = 0;
29
}
30
--
31
2.48.1
diff view generated by jsdifflib
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
[PULL 58/59] target/riscv/kvm: add kvm_riscv_reset_regs_csr()
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Provides fw_cfg for the virt machine on riscv. This enables
3
We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but
4
using e.g. ramfb later.
4
in no particular order and missing some of them (like env->mstatus).
5
5
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
6
Create a helper to do that, unclogging reset_vcpu(), and initialize
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
env->mstatus as well. Keep the regs in the same order they appear in
8
struct kvm_riscv_csr from the KVM UAPI, similar to what
9
kvm_riscv_(get|put)_regs_csr are doing. This will make a bit easier to
10
add new KVM CSRs and to verify which values we're writing back to KVM
11
during vcpu reset.
12
13
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
16
Message-ID: <20250224123120.1644186-3-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
include/hw/riscv/virt.h | 2 ++
19
target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++--------
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
20
1 file changed, 15 insertions(+), 8 deletions(-)
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 33 insertions(+)
16
21
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
22
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
18
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
24
--- a/target/riscv/kvm/kvm-cpu.c
20
+++ b/include/hw/riscv/virt.h
25
+++ b/target/riscv/kvm/kvm-cpu.c
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
26
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_core(CPUState *cs)
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
27
return ret;
23
DeviceState *plic[VIRT_SOCKETS_MAX];
24
PFlashCFI01 *flash[2];
25
+ FWCfgState *fw_cfg;
26
27
int fdt_size;
28
};
29
@@ -XXX,XX +XXX,XX @@ enum {
30
VIRT_PLIC,
31
VIRT_UART0,
32
VIRT_VIRTIO,
33
+ VIRT_FW_CFG,
34
VIRT_FLASH,
35
VIRT_DRAM,
36
VIRT_PCIE_MMIO,
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/riscv/virt.c
40
+++ b/hw/riscv/virt.c
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
43
[VIRT_UART0] = { 0x10000000, 0x100 },
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
50
return dev;
51
}
28
}
52
29
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
30
+static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
54
+{
31
+{
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
32
+ env->mstatus = 0;
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
33
+ env->mie = 0;
57
+ FWCfgState *fw_cfg;
34
+ env->stvec = 0;
58
+ char *nodename;
35
+ env->sscratch = 0;
59
+
36
+ env->sepc = 0;
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
37
+ env->scause = 0;
61
+ &address_space_memory);
38
+ env->stval = 0;
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
39
+ env->mip = 0;
63
+
40
+ env->satp = 0;
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
67
+ "compatible", "qemu,fw-cfg-mmio");
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
73
+}
41
+}
74
+
42
+
75
static void virt_machine_init(MachineState *machine)
43
static int kvm_riscv_get_regs_csr(CPUState *cs)
76
{
44
{
77
const MemMapEntry *memmap = virt_memmap;
45
CPURISCVState *env = &RISCV_CPU(cs)->env;
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
46
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
79
start_addr = virt_memmap[VIRT_FLASH].base;
47
env->pc = cpu->env.kernel_addr;
80
}
48
env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
81
49
env->gpr[11] = cpu->env.fdt_addr; /* a1 */
82
+ /*
50
- env->satp = 0;
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
51
- env->mie = 0;
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
52
- env->stvec = 0;
85
+ */
53
- env->sscratch = 0;
86
+ s->fw_cfg = create_fw_cfg(machine);
54
- env->sepc = 0;
87
+ rom_set_fw(s->fw_cfg);
55
- env->scause = 0;
56
- env->stval = 0;
57
- env->mip = 0;
88
+
58
+
89
/* Compute the fdt load address in dram */
59
+ kvm_riscv_reset_regs_csr(env);
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
60
}
91
machine->ram_size, machine->fdt);
61
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
62
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/riscv/Kconfig
95
+++ b/hw/riscv/Kconfig
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
97
select SIFIVE_PLIC
98
select SIFIVE_TEST
99
select VIRTIO_MMIO
100
+ select FW_CFG_DMA
101
102
config SIFIVE_E
103
bool
104
--
63
--
105
2.30.1
64
2.48.1
106
107
diff view generated by jsdifflib
New patch
[PULL 59/59] target/riscv/kvm: add missing KVM CSRs
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're missing scounteren and senvcfg CSRs, both already present in the
4
KVM UAPI.
5
6
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20250224123120.1644186-4-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/kvm/kvm-cpu.c | 6 ++++++
13
1 file changed, 6 insertions(+)
14
15
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/kvm/kvm-cpu.c
18
+++ b/target/riscv/kvm/kvm-cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
20
env->stval = 0;
21
env->mip = 0;
22
env->satp = 0;
23
+ env->scounteren = 0;
24
+ env->senvcfg = 0;
25
}
26
27
static int kvm_riscv_get_regs_csr(CPUState *cs)
28
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
29
KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
30
KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
31
KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
32
+ KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren);
33
+ KVM_RISCV_GET_CSR(cs, env, senvcfg, env->senvcfg);
34
35
return 0;
36
}
37
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
38
KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
39
KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
40
KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
41
+ KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren);
42
+ KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg);
43
44
return 0;
45
}
46
--
47
2.48.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.