[PULL 00/16] riscv-to-apply queue
[PULL 00/28] riscv-to-apply queue
1
The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
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The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
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Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
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Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
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8
9
for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
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for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
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target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
11
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
RISC-V PR for 6.0
14
RISC-V PR for 9.1
15
15
16
This PR includes:
16
* APLICs add child earlier than realize
17
- Fix for vector CSR access
17
* Fix exposure of Zkr
18
- Improvements to the Ibex UART device
18
* Raise exceptions on wrs.nto
19
- PMP improvements and bug fixes
19
* Implement SBI debug console (DBCN) calls for KVM
20
- Hypervisor extension bug fixes
20
* Support 64-bit addresses for initrd
21
- ramfb support for the virt machine
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
- Fast read support for SST flash
22
* Tolerate KVM disable ext errors
23
- Improvements to the microchip_pfsoc machine
23
* Set tval in breakpoints
24
* Add support for Zve32x extension
25
* Add support for Zve64x extension
26
* Relax vector register check in RISCV gdbstub
27
* Fix the element agnostic Vector function problem
28
* Fix Zvkb extension config
29
* Implement dynamic establishment of custom decoder
30
* Add th.sxstatus CSR emulation
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Check single width operator for vector fp widen instructions
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
24
43
25
----------------------------------------------------------------
44
----------------------------------------------------------------
26
Alexander Wagner (1):
45
Alexei Filippov (1):
27
hw/char: disable ibex uart receive if the buffer is full
46
target/riscv: do not set mtval2 for non guest-page faults
28
47
29
Asherah Connor (2):
48
Alistair Francis (2):
30
hw/riscv: Add fw_cfg support to virt
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
31
hw/riscv: allow ramfb on virt
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
32
51
33
Bin Meng (3):
52
Andrew Jones (2):
34
hw/block: m25p80: Support fast read for SST flashes
53
target/riscv/kvm: Fix exposure of Zkr
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
54
target/riscv: Raise exceptions on wrs.nto
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
37
55
38
Frank Chang (1):
56
Cheng Yang (1):
39
target/riscv: fix vs() to return proper error code
57
hw/riscv/boot.c: Support 64-bit address for initrd
40
58
41
Georg Kotheimer (6):
59
Christoph Müllner (1):
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
60
riscv: thead: Add th.sxstatus CSR emulation
43
target/riscv: Make VSTIP and VSEIP read-only in hip
44
target/riscv: Use background registers also for MSTATUS_MPV
45
target/riscv: Fix read and write accesses to vsip and vsie
46
target/riscv: Add proper two-stage lookup exception detection
47
target/riscv: Prevent lost illegal instruction exceptions
48
61
49
Jim Shu (3):
62
Clément Léger (1):
50
target/riscv: propagate PMP permission to TLB page
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
51
target/riscv: add log of PMP permission checking
52
target/riscv: flush TLB pages if PMP permission has been changed
53
64
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
65
Daniel Henrique Barboza (6):
55
docs/system/target-riscv.rst | 1 +
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
56
include/hw/char/ibex_uart.h | 4 +
67
target/riscv/kvm: tolerate KVM disable ext errors
57
include/hw/riscv/microchip_pfsoc.h | 1 +
68
target/riscv/debug: set tval=pc in breakpoint exceptions
58
include/hw/riscv/virt.h | 2 +
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
59
target/riscv/cpu.h | 4 +
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
60
target/riscv/pmp.h | 4 +-
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
61
hw/block/m25p80.c | 3 +
62
hw/char/ibex_uart.c | 23 +++-
63
hw/riscv/microchip_pfsoc.c | 6 +
64
hw/riscv/virt.c | 33 ++++++
65
target/riscv/cpu.c | 1 +
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
67
target/riscv/csr.c | 77 +++++++------
68
target/riscv/pmp.c | 84 ++++++++++----
69
target/riscv/translate.c | 179 +----------------------------
70
hw/riscv/Kconfig | 1 +
71
17 files changed, 367 insertions(+), 289 deletions(-)
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
73
72
73
Huang Tao (2):
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
76
77
Jason Chien (3):
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
81
82
Max Chou (4):
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
87
88
Rob Bradford (1):
89
target/riscv: Remove experimental prefix from "B" extension
90
91
Yangyu Chen (1):
92
target/riscv/cpu.c: fix Zvkb extension config
93
94
Yong-Xuan Wang (1):
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
96
97
Yu-Ming Chang (1):
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
100
yang.zhang (1):
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
103
MAINTAINERS | 1 +
104
target/riscv/cpu.h | 11 ++
105
target/riscv/cpu_bits.h | 2 +-
106
target/riscv/cpu_cfg.h | 2 +
107
target/riscv/helper.h | 1 +
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
disas/riscv.c | 65 +++++++++-
111
hw/intc/riscv_aplic.c | 8 +-
112
hw/riscv/boot.c | 4 +-
113
target/riscv/cpu.c | 10 +-
114
target/riscv/cpu_helper.c | 37 +++---
115
target/riscv/csr.c | 71 +++++++++--
116
target/riscv/debug.c | 3 +
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
target/riscv/op_helper.c | 17 ++-
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
target/riscv/th_csr.c | 79 +++++++++++++
122
target/riscv/translate.c | 31 +++--
123
target/riscv/vector_internals.c | 22 ++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/meson.build | 1 +
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
create mode 100644 target/riscv/th_csr.c
131
diff view generated by jsdifflib
New patch
[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
1
From: "yang.zhang" <yang.zhang@hexintek.com>
1
2
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
be initialized first.
5
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/intc/riscv_aplic.c | 8 ++++----
14
1 file changed, 4 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/riscv_aplic.c
19
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
21
qdev_prop_set_bit(dev, "msimode", msimode);
22
qdev_prop_set_bit(dev, "mmode", mmode);
23
24
+ if (parent) {
25
+ riscv_aplic_add_child(parent, dev);
26
+ }
27
+
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
30
if (!is_kvm_aia(msimode)) {
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
32
}
33
34
- if (parent) {
35
- riscv_aplic_add_child(parent, dev);
36
- }
37
-
38
if (!msimode) {
39
for (i = 0; i < num_harts; i++) {
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
41
--
42
2.45.1
diff view generated by jsdifflib
[PULL 01/16] target/riscv: fix vs() to return proper error code
[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
is not enabled.
4
implements the SEED CSR. Use the same implementation as TCG.
5
5
6
If -1 is returned, exception will be raised and cs->exception_index will
6
Without this patch, running with a KVM which does not forward the
7
be set to the negative return value. The exception will then be treated
7
SEED CSR access to QEMU will result in an ILL exception being
8
as an instruction access fault instead of illegal instruction fault.
8
injected into the guest (this results in Linux guests crashing on
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
9
11
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
15
Cc: qemu-stable <qemu-stable@nongnu.org>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
18
---
16
target/riscv/csr.c | 2 +-
19
target/riscv/cpu.h | 3 +++
17
1 file changed, 1 insertion(+), 1 deletion(-)
20
target/riscv/csr.c | 18 ++++++++++++++----
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
18
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
29
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
31
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
33
+ target_ulong write_mask);
34
+
35
uint8_t satp_mode_max_from_map(uint32_t map);
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
37
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
40
--- a/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
24
if (env->misa & RVV) {
43
#endif
25
return 0;
44
45
/* Crypto Extension */
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
47
- target_ulong *ret_value,
48
- target_ulong new_value,
49
- target_ulong write_mask)
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
51
+ target_ulong write_mask)
52
{
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
26
}
57
}
27
- return -1;
58
28
+ return -RISCV_EXCP_ILLEGAL_INST;
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
29
}
80
}
30
81
31
static int ctr(CPURISCVState *env, int csrno)
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
83
+{
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
85
+ target_ulong new_value = run->riscv_csr.new_value;
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
32
--
117
--
33
2.30.1
118
2.45.1
34
35
diff view generated by jsdifflib
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
3
Implementing wrs.nto to always just return is consistent with the
4
been updated to use a register mapped at 0x4f000000 instead of a
4
specification, as the instruction is permitted to terminate the
5
GPIO to control whether eMMC or SD card is to be used. With this
5
stall for any reason, but it's not useful for virtualization, where
6
support the same HSS image can be used for both eMMC and SD card
6
we'd like the guest to trap to the hypervisor in order to allow
7
boot flow, while previously two different board configurations were
7
scheduling of the lock holding VCPU. Change to always immediately
8
used. This is undocumented but one can take a look at the HSS code
8
raise exceptions when the appropriate conditions are present,
9
HSS_MMCInit() in services/mmc/mmc_api.c.
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
10
13
11
With this commit, HSS image built from 2020.12 release boots again.
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
12
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
20
---
18
include/hw/riscv/microchip_pfsoc.h | 1 +
21
target/riscv/helper.h | 1 +
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
22
target/riscv/op_helper.c | 11 ++++++++
20
2 files changed, 7 insertions(+)
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
24
3 files changed, 32 insertions(+), 9 deletions(-)
21
25
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
23
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/riscv/microchip_pfsoc.h
28
--- a/target/riscv/helper.h
25
+++ b/include/hw/riscv/microchip_pfsoc.h
29
+++ b/target/riscv/helper.h
26
@@ -XXX,XX +XXX,XX @@ enum {
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
27
MICROCHIP_PFSOC_ENVM_DATA,
31
DEF_HELPER_1(sret, tl, env)
28
MICROCHIP_PFSOC_QSPI_XIP,
32
DEF_HELPER_1(mret, tl, env)
29
MICROCHIP_PFSOC_IOSCB,
33
DEF_HELPER_1(wfi, void, env)
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
34
+DEF_HELPER_1(wrs_nto, void, env)
31
MICROCHIP_PFSOC_DRAM_LO,
35
DEF_HELPER_1(tlb_flush, void, env)
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
36
DEF_HELPER_1(tlb_flush_all, void, env)
33
MICROCHIP_PFSOC_DRAM_HI,
37
/* Native Debug */
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
35
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/riscv/microchip_pfsoc.c
40
--- a/target/riscv/op_helper.c
37
+++ b/hw/riscv/microchip_pfsoc.c
41
+++ b/target/riscv/op_helper.c
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
43
}
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
44
}
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
45
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
46
+void helper_wrs_nto(CPURISCVState *env)
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
47
+{
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
49
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
50
+ /* eMMC/SD mux */
54
+ }
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
55
+}
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
54
+
56
+
55
/* QSPI Flash */
57
void helper_tlb_flush(CPURISCVState *env)
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
58
{
57
"microchip.pfsoc.qspi_xip",
59
CPUState *cs = env_cpu(env);
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
64
@@ -XXX,XX +XXX,XX @@
65
* this program. If not, see <http://www.gnu.org/licenses/>.
66
*/
67
68
-static bool trans_wrs(DisasContext *ctx)
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
70
{
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
75
}
76
77
-#define GEN_TRANS_WRS(insn) \
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
79
-{ \
80
- (void)a; \
81
- return trans_wrs(ctx); \
82
-}
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
84
+{
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
86
+ return false;
87
+ }
88
89
-GEN_TRANS_WRS(wrs_nto)
90
-GEN_TRANS_WRS(wrs_sto)
91
+ /*
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
93
+ * should raise an exception when the implementation-specific bounded time
94
+ * limit has expired. Our time limit is zero, so we either return
95
+ * immediately, as does our implementation of wrs.sto, or raise an
96
+ * exception, as handled by the wrs.nto helper.
97
+ */
98
+#ifndef CONFIG_USER_ONLY
99
+ gen_helper_wrs_nto(tcg_env);
100
+#endif
101
+
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
103
+ return trans_wrs_sto(ctx, NULL);
104
+}
58
--
105
--
59
2.30.1
106
2.45.1
60
107
61
108
diff view generated by jsdifflib
New patch
[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
1
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
the legacy console putchar and getchar SBI extensions.
5
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
read/written in the SBI console in a single SBI call.
8
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
module to userspace. But this will only happens if the KVM module
11
actually supports this SBI extension and we activate it.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
25
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/sbi_ecall_interface.h | 17 +++++
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
33
2 files changed, 128 insertions(+)
34
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/sbi_ecall_interface.h
38
+++ b/target/riscv/sbi_ecall_interface.h
39
@@ -XXX,XX +XXX,XX @@
40
41
/* clang-format off */
42
43
+#define SBI_SUCCESS 0
44
+#define SBI_ERR_FAILED -1
45
+#define SBI_ERR_NOT_SUPPORTED -2
46
+#define SBI_ERR_INVALID_PARAM -3
47
+#define SBI_ERR_DENIED -4
48
+#define SBI_ERR_INVALID_ADDRESS -5
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
50
+#define SBI_ERR_ALREADY_STARTED -7
51
+#define SBI_ERR_ALREADY_STOPPED -8
52
+#define SBI_ERR_NO_SHMEM -9
53
+
54
/* SBI Extension IDs */
55
#define SBI_EXT_0_1_SET_TIMER 0x0
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
57
@@ -XXX,XX +XXX,XX @@
58
#define SBI_EXT_IPI 0x735049
59
#define SBI_EXT_RFENCE 0x52464E43
60
#define SBI_EXT_HSM 0x48534D
61
+#define SBI_EXT_DBCN 0x4442434E
62
63
/* SBI function IDs for BASE extension */
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
65
@@ -XXX,XX +XXX,XX @@
66
#define SBI_EXT_HSM_HART_STOP 0x1
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
68
69
+/* SBI function IDs for DBCN extension */
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
73
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/kvm/kvm-cpu.c
80
+++ b/target/riscv/kvm/kvm-cpu.c
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
83
};
84
85
+static KVMCPUConfig kvm_sbi_dbcn = {
86
+ .name = "sbi_dbcn",
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
89
+};
90
+
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
92
{
93
CPURISCVState *env = &cpu->env;
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
95
return 0;
96
}
97
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
99
+ KVMScratchCPU *kvmcpu,
100
+ struct kvm_reg_list *reglist)
101
+{
102
+ struct kvm_reg_list *reg_search;
103
+
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
105
+ sizeof(uint64_t), uint64_cmp);
106
+
107
+ if (reg_search) {
108
+ kvm_sbi_dbcn.supported = true;
109
+ }
110
+}
111
+
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
129
+{
130
+ target_ulong reg = 1;
131
+
132
+ if (!kvm_sbi_dbcn.supported) {
133
+ return 0;
134
+ }
135
+
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
137
+}
138
+
139
int kvm_arch_init_vcpu(CPUState *cs)
140
{
141
int ret = 0;
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
145
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
147
+
148
return ret;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
156
+{
157
+ g_autofree uint8_t *buf = NULL;
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
159
+ target_ulong num_bytes;
160
+ uint64_t addr;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
225
+ }
226
+}
227
+
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
229
{
230
int ret = 0;
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
232
}
233
ret = 0;
234
break;
235
+ case SBI_EXT_DBCN:
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
237
+ break;
238
default:
239
qemu_log_mask(LOG_UNIMP,
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
241
--
242
2.45.1
diff view generated by jsdifflib
New patch
[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
1
From: Cheng Yang <yangcheng.work@foxmail.com>
1
2
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
to set the address of initrd in FDT to support 64-bit address.
5
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/riscv/boot.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/boot.c
17
+++ b/hw/riscv/boot.c
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
20
if (fdt) {
21
end = start + size;
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
26
}
27
}
28
29
--
30
2.45.1
diff view generated by jsdifflib
[PULL 10/16] hw/riscv: allow ramfb on virt
[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
Allow ramfb on virt. This lets `-device ramfb' work.
3
The current semihost exception number (16) is a reserved number (range
4
[16-17]). The upcoming double trap specification uses that number for
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
4
9
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
15
---
11
hw/riscv/virt.c | 3 +++
16
target/riscv/cpu_bits.h | 2 +-
12
1 file changed, 3 insertions(+)
17
1 file changed, 1 insertion(+), 1 deletion(-)
13
18
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
21
--- a/target/riscv/cpu_bits.h
17
+++ b/hw/riscv/virt.c
22
+++ b/target/riscv/cpu_bits.h
18
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
19
#include "sysemu/sysemu.h"
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
20
#include "hw/pci/pci.h"
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
21
#include "hw/pci-host/gpex.h"
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
22
+#include "hw/display/ramfb.h"
27
- RISCV_EXCP_SEMIHOST = 0x10,
23
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
24
static const MemMapEntry virt_memmap[] = {
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
25
[VIRT_DEBUG] = { 0x0, 0x100 },
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
33
} RISCVException;
29
mc->numa_mem_supported = true;
34
30
+
35
#define RISCV_EXCP_INT_FLAG 0x80000000
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
32
}
33
34
static const TypeInfo virt_machine_typeinfo = {
35
--
36
--
36
2.30.1
37
2.45.1
37
38
38
39
diff view generated by jsdifflib
New patch
[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
allow it we'll error out and never boot.
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
37
1 file changed, 8 insertions(+), 4 deletions(-)
38
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/kvm/kvm-cpu.c
42
+++ b/target/riscv/kvm/kvm-cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
45
ret = kvm_set_one_reg(cs, id, &reg);
46
if (ret != 0) {
47
- error_report("Unable to %s extension %s in KVM, error %d",
48
- reg ? "enable" : "disable",
49
- multi_ext_cfg->name, ret);
50
- exit(EXIT_FAILURE);
51
+ if (!reg && ret == -EINVAL) {
52
+ warn_report("KVM cannot disable extension %s",
53
+ multi_ext_cfg->name);
54
+ } else {
55
+ error_report("Unable to enable extension %s in KVM, error %d",
56
+ multi_ext_cfg->name, ret);
57
+ exit(EXIT_FAILURE);
58
+ }
59
}
60
}
61
}
62
--
63
2.45.1
diff view generated by jsdifflib
New patch
[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
5.7.12, "Match Control Type 6":
6
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
24
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/cpu_helper.c | 1 +
32
target/riscv/debug.c | 3 +++
33
2 files changed, 4 insertions(+)
34
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_helper.c
38
+++ b/target/riscv/cpu_helper.c
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
40
tval = env->bins;
41
break;
42
case RISCV_EXCP_BREAKPOINT:
43
+ tval = env->badaddr;
44
if (cs->watchpoint_hit) {
45
tval = cs->watchpoint_hit->hitaddr;
46
cs->watchpoint_hit = NULL;
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/debug.c
50
+++ b/target/riscv/debug.c
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
53
/* check U/S/M bit against current privilege level */
54
if ((ctrl >> 3) & BIT(env->priv)) {
55
+ env->badaddr = pc;
56
return true;
57
}
58
}
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
60
if (env->virt_enabled) {
61
/* check VU/VS bit against current privilege level */
62
if ((ctrl >> 23) & BIT(env->priv)) {
63
+ env->badaddr = pc;
64
return true;
65
}
66
} else {
67
/* check U/S/M bit against current privilege level */
68
if ((ctrl >> 3) & BIT(env->priv)) {
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
73
--
74
2.45.1
diff view generated by jsdifflib
New patch
[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Privileged spec section 4.1.9 mentions:
4
5
"When a trap is taken into S-mode, stval is written with
6
exception-specific information to assist software in handling the trap.
7
(...)
8
9
If stval is written with a nonzero value when a breakpoint,
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
instruction fetch, load, or store, then stval will contain the faulting
12
virtual address."
13
14
A similar text is found for mtval in section 3.1.16.
15
16
Setting mtval/stval in this scenario is optional, but some softwares read
17
these regs when handling ebreaks.
18
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
20
'tval' during riscv_do_cpu_interrrupt().
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
30
1 file changed, 2 insertions(+)
31
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
39
} else {
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
41
+ offsetof(CPURISCVState, badaddr));
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
43
}
44
return true;
45
--
46
2.45.1
diff view generated by jsdifflib
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
[PULL 10/28] target/riscv: Add support for Zve32x extension
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
According to the specification the "field SPVP of hstatus controls the
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
privilege level of the access" for the hypervisor virtual-machine load
4
Zve32x, since Zve32f depends on Zve32x.
5
and store instructions HLV, HLVX and HSV.
6
5
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
8
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
13
target/riscv/cpu_cfg.h | 1 +
13
1 file changed, 14 insertions(+), 11 deletions(-)
14
target/riscv/cpu.c | 2 ++
15
target/riscv/cpu_helper.c | 2 +-
16
target/riscv/csr.c | 2 +-
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
19
6 files changed, 15 insertions(+), 12 deletions(-)
14
20
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_cfg.h
24
+++ b/target/riscv/cpu_cfg.h
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
26
bool ext_zhinx;
27
bool ext_zhinxmin;
28
bool ext_zve32f;
29
+ bool ext_zve32x;
30
bool ext_zve64f;
31
bool ext_zve64d;
32
bool ext_zvbb;
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
55
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
20
use_background = true;
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
59
*cs_base = 0;
60
61
- if (cpu->cfg.ext_zve32f) {
62
+ if (cpu->cfg.ext_zve32x) {
63
/*
64
* If env->vl equals to VLMAX, we can use generic vector operation
65
* expanders (GVEC) to accerlate the vector operations.
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
76
#if !defined(CONFIG_USER_ONLY)
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
78
return RISCV_EXCP_ILLEGAL_INST;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/tcg/tcg-cpu.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
84
return;
21
}
85
}
22
86
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
24
+ /* MPRV does not affect the virtual-machine load/store
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
25
+ instructions, HLV, HLVX, and HSV. */
89
- return;
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
90
+ /* The Zve32f extension depends on the Zve32x extension */
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
91
+ if (cpu->cfg.ext_zve32f) {
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
92
+ if (!riscv_has_ext(env, RVF)) {
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
30
mode = get_field(env->mstatus, MSTATUS_MPP);
94
+ return;
31
}
95
+ }
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
34
__func__, address, access_type, mmu_idx);
35
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
39
+ /* MPRV does not affect the virtual-machine load/store
40
+ instructions, HLV, HLVX, and HSV. */
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
47
+ two_stage_lookup = true;
48
}
49
}
97
}
50
98
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
99
if (cpu->cfg.ext_zvfh) {
52
- access_type != MMU_INST_FETCH &&
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
54
- get_field(env->mstatus, MSTATUS_MPV)) {
102
}
55
- two_stage_lookup = true;
103
56
- }
104
- /*
57
-
105
- * In principle Zve*x would also suffice here, were they supported
58
if (riscv_cpu_virt_enabled(env) ||
106
- * in qemu
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
107
- */
60
access_type != MMU_INST_FETCH)) {
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
112
error_setg(errp,
113
"Vector crypto extensions require V or Zve* extensions");
114
return;
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
116
index XXXXXXX..XXXXXXX 100644
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
120
{
121
TCGv s1, dst;
122
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
125
return false;
126
}
127
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
129
{
130
TCGv dst;
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
135
}
136
61
--
137
--
62
2.30.1
138
2.45.1
63
64
diff view generated by jsdifflib
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
[PULL 11/28] target/riscv: Add support for Zve64x extension
1
From: Jim Shu <cwshu@andestech.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
4
Fix it by propagating PMP permission to TLB page permission.
4
enabling Zve64x enables Zve32x according to their dependency.
5
5
6
PMP permission checking also use MMU-style API to change TLB permission
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
7
and size.
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
9
Reviewed-by: Max Chou <max.chou@sifive.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
13
---
14
target/riscv/pmp.h | 4 +-
14
target/riscv/cpu_cfg.h | 1 +
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
15
target/riscv/cpu.c | 2 ++
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
17
3 files changed, 125 insertions(+), 43 deletions(-)
17
3 files changed, 14 insertions(+), 6 deletions(-)
18
18
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/pmp.h
21
--- a/target/riscv/cpu_cfg.h
22
+++ b/target/riscv/pmp.h
22
+++ b/target/riscv/cpu_cfg.h
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
target_ulong val);
24
bool ext_zve32x;
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
25
bool ext_zve64f;
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
26
bool ext_zve64d;
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
27
+ bool ext_zve64x;
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
28
bool ext_zvbb;
29
+ target_ulong mode);
29
bool ext_zvbc;
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
30
bool ext_zvkb;
31
target_ulong *tlb_size);
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
33
void pmp_update_rule_nums(CPURISCVState *env);
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
36
37
#endif
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
33
--- a/target/riscv/cpu.c
41
+++ b/target/riscv/cpu_helper.c
34
+++ b/target/riscv/cpu.c
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
43
env->load_res = -1;
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
44
}
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
45
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
46
+/*
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
47
+ * get_physical_address_pmp - check PMP permission for this physical address
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
48
+ *
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
49
+ * Match the PMP region and check permission for this physical address and it's
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
50
+ * TLB page. Returns 0 if the permission checking was successful
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
51
+ *
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
52
+ * @env: CPURISCVState
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
53
+ * @prot: The returned protection attributes
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
55
+ * permission checking. NULL if not set TLB page for addr.
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
56
+ * @addr: The physical address to be checked permission
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
57
+ * @access_type: The type of MMU access
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
58
+ * @mode: Indicates current privilege level.
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
59
+ */
52
index XXXXXXX..XXXXXXX 100644
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
53
--- a/target/riscv/tcg/tcg-cpu.c
61
+ target_ulong *tlb_size, hwaddr addr,
54
+++ b/target/riscv/tcg/tcg-cpu.c
62
+ int size, MMUAccessType access_type,
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
63
+ int mode)
56
64
+{
57
/* The Zve64d extension depends on the Zve64f extension */
65
+ pmp_priv_t pmp_priv;
58
if (cpu->cfg.ext_zve64d) {
66
+ target_ulong tlb_size_pmp = 0;
59
+ if (!riscv_has_ext(env, RVD)) {
67
+
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
61
+ return;
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
70
+ return TRANSLATE_SUCCESS;
71
+ }
72
+
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
74
+ mode)) {
75
+ *prot = 0;
76
+ return TRANSLATE_PMP_FAIL;
77
+ }
78
+
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
80
+ if (tlb_size != NULL) {
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
82
+ *tlb_size = tlb_size_pmp;
83
+ }
62
+ }
84
+ }
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
85
+
86
+ return TRANSLATE_SUCCESS;
87
+}
88
+
89
/* get_physical_address - get the physical address for this virtual address
90
*
91
* Do a page table walk to obtain the physical address corresponding to a
92
@@ -XXX,XX +XXX,XX @@ restart:
93
pte_addr = base + idx * ptesize;
94
}
95
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
99
+ int pmp_prot;
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
101
+ sizeof(target_ulong),
102
+ MMU_DATA_LOAD, PRV_S);
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
104
return TRANSLATE_PMP_FAIL;
105
}
106
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
#ifndef CONFIG_USER_ONLY
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
154
}
64
}
155
+
65
156
if (ret == TRANSLATE_PMP_FAIL) {
66
- /* The Zve64f extension depends on the Zve32f extension */
157
pmp_violation = true;
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
68
if (cpu->cfg.ext_zve64f) {
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
158
}
71
}
159
72
160
if (ret == TRANSLATE_SUCCESS) {
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
74
- error_setg(errp, "Zve64d/V extensions require D extension");
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
75
- return;
163
- prot, mmu_idx, tlb_size);
76
+ /* The Zve64x extension depends on the Zve32x extension */
164
- } else {
77
+ if (cpu->cfg.ext_zve64x) {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/target/riscv/pmp.c
176
+++ b/target/riscv/pmp.c
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
178
return result;
179
}
180
181
+/*
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
183
+ */
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
186
+ target_ulong mode)
187
+{
188
+ bool ret;
189
+
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
191
+ /*
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
194
+ */
195
+ ret = true;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
197
+ } else {
198
+ /*
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
200
+ * but there are rules. We've checked for no rule earlier in this
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
206
+
207
+ return ret;
208
+}
209
+
210
211
/*
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
215
*/
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
219
+ target_ulong mode)
220
{
221
int i = 0;
222
int ret = -1;
223
int pmp_size = 0;
224
target_ulong s = 0;
225
target_ulong e = 0;
226
- pmp_priv_t allowed_privs = 0;
227
228
/* Short cut if no rules */
229
if (0 == pmp_get_num_rules(env)) {
230
- return (env->priv == PRV_M) ? true : false;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
232
+ allowed_privs, mode);
233
}
79
}
234
80
235
if (size == 0) {
81
/* The Zve32f extension depends on the Zve32x extension */
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
237
* check
83
return;
238
*/
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
245
}
246
247
- if ((privs & allowed_privs) == privs) {
248
- ret = 1;
249
- break;
250
- } else {
251
- ret = 0;
252
- break;
253
- }
254
+ ret = ((privs & *allowed_privs) == privs);
255
+ break;
256
}
257
}
84
}
258
85
259
/* No rule matched */
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
260
if (ret == -1) {
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
261
- if (mode == PRV_M) {
88
error_setg(
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
89
errp,
263
- * M-Mode access, the access succeeds */
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
264
- } else {
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
92
return;
266
- * match a rule, but there are rules. We've checked for
267
- * no rule earlier in this function. */
268
- }
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
270
+ allowed_privs, mode);
271
}
93
}
272
94
273
return ret == 1 ? true : false;
274
}
275
276
-
277
/*
278
* Handle a write to a pmpcfg CSP
279
*/
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
281
282
return false;
283
}
284
+
285
+/*
286
+ * Convert PMP privilege to TLB page privilege.
287
+ */
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
289
+{
290
+ int prot = 0;
291
+
292
+ if (pmp_priv & PMP_READ) {
293
+ prot |= PAGE_READ;
294
+ }
295
+ if (pmp_priv & PMP_WRITE) {
296
+ prot |= PAGE_WRITE;
297
+ }
298
+ if (pmp_priv & PMP_EXEC) {
299
+ prot |= PAGE_EXEC;
300
+ }
301
+
302
+ return prot;
303
+}
304
--
95
--
305
2.30.1
96
2.45.1
306
307
diff view generated by jsdifflib
New patch
[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
In current implementation, the gdbstub allows reading vector registers
4
only if V extension is supported. However, all vector extensions and
5
vector crypto extensions have the vector registers and they all depend
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/gdbstub.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/gdbstub.c
20
+++ b/target/riscv/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
23
0);
24
}
25
- if (env->misa_ext & RVV) {
26
+ if (cpu->cfg.ext_zve32x) {
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
28
riscv_gdb_set_vector,
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
30
--
31
2.45.1
diff view generated by jsdifflib
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
[PULL 13/28] target/riscv: Fix the element agnostic function problem
1
From: Jim Shu <cwshu@andestech.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
If PMP permission of any address has been changed by updating PMP entry,
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
flush all TLB pages to prevent from getting old permission.
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
agnostic policy.
5
6
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
7
However, this function can't deal the big endian situation. This patch fixes
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
the problem by adding handling of such case.
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
9
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/pmp.c | 4 ++++
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
12
1 file changed, 4 insertions(+)
18
1 file changed, 22 insertions(+)
13
19
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/pmp.c
22
--- a/target/riscv/vector_internals.c
17
+++ b/target/riscv/pmp.c
23
+++ b/target/riscv/vector_internals.c
18
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
19
#include "qapi/error.h"
25
if (tot - cnt == 0) {
20
#include "cpu.h"
26
return ;
21
#include "trace.h"
22
+#include "exec/exec-all.h"
23
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
25
uint8_t val);
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
27
cfg_val = (val >> 8 * i) & 0xff;
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
29
}
27
}
30
+
28
+
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
29
+ if (HOST_BIG_ENDIAN) {
32
+ tlb_flush(env_cpu(env));
30
+ /*
31
+ * Deal the situation when the elements are insdie
32
+ * only one uint64 block including setting the
33
+ * masked-off element.
34
+ */
35
+ if (((tot - 1) ^ cnt) < 8) {
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
37
+ return;
38
+ }
39
+ /*
40
+ * Otherwise, at least cross two uint64_t blocks.
41
+ * Set first unaligned block.
42
+ */
43
+ if (cnt % 8 != 0) {
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
47
+ }
48
+ /* Set other 64bit aligend blocks */
49
+ }
50
memset(base + cnt, -1, tot - cnt);
33
}
51
}
34
52
35
36
--
53
--
37
2.30.1
54
2.45.1
38
39
diff view generated by jsdifflib
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Yangyu Chen <cyy@cyyself.name>
2
2
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
the address bytes. Note only SPI mode is supported by SST flashes.
4
enable zvkb through the config. This patch gets this fixed.
5
5
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
7
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
15
---
13
hw/block/m25p80.c | 3 +++
16
target/riscv/cpu.c | 2 +-
14
1 file changed, 3 insertions(+)
17
1 file changed, 1 insertion(+), 1 deletion(-)
15
18
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
21
--- a/target/riscv/cpu.c
19
+++ b/hw/block/m25p80.c
22
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
21
s->needed_bytes = get_addr_length(s);
24
/* Vector cryptography extensions */
22
switch (get_man(s)) {
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
23
/* Dummy cycles - modeled with bytes writes instead of bits */
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
24
+ case MAN_SST:
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
25
+ s->needed_bytes += 1;
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
26
+ break;
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
27
case MAN_WINBOND:
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
28
s->needed_bytes += 8;
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
29
break;
30
--
32
--
31
2.30.1
33
2.45.1
32
34
33
35
diff view generated by jsdifflib
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
3
In this patch, we modify the decoder to be a freely composable data
4
short of its purpose, as all it checks is whether two-stage address
4
structure instead of a hardcoded one. It can be dynamically builded up
5
translation either via the hypervisor-load store instructions or the
5
according to the extensions.
6
MPRV feature would be allowed.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
7
20
8
What we really need instead is whether two-stage address translation was
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
10
we do not have the information to reliably detect this. Therefore, when
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
we raise a memory fault exception we have to record whether two-stage
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
address translation is active.
13
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
28
---
19
target/riscv/cpu.h | 4 ++++
29
target/riscv/cpu.h | 1 +
20
target/riscv/cpu.c | 1 +
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
31
target/riscv/cpu.c | 1 +
22
3 files changed, 13 insertions(+), 13 deletions(-)
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
33
target/riscv/translate.c | 31 +++++++++++++++----------------
34
5 files changed, 47 insertions(+), 16 deletions(-)
23
35
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
38
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
39
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
29
target_ulong satp_hs;
41
uint32_t pmu_avail_ctrs;
30
uint64_t mstatus_hs;
42
/* Mapping of events to counters */
31
43
GHashTable *pmu_event_ctr_map;
32
+ /* Signals whether the current exception occurred with two-stage address
44
+ const GPtrArray *decoders;
33
+ translation active. */
45
};
34
+ bool two_stage_lookup;
46
47
/**
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/tcg/tcg-cpu.h
51
+++ b/target/riscv/tcg/tcg-cpu.h
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
55
56
+struct DisasContext;
57
+struct RISCVCPUConfig;
58
+typedef struct RISCVDecoder {
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
61
+} RISCVDecoder;
35
+
62
+
36
target_ulong scounteren;
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
37
target_ulong mcounteren;
64
+
38
65
+extern const size_t decoder_table_size;
66
+
67
+extern const RISCVDecoder decoder_table[];
68
+
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
70
+
71
#endif
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu.c
74
--- a/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
75
+++ b/target/riscv/cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
77
error_propagate(errp, local_err);
45
env->mcause = 0;
78
return;
46
env->pc = env->resetvec;
79
}
47
+ env->two_stage_lookup = false;
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
48
#endif
81
} else if (kvm_enabled()) {
49
cs->exception_index = EXCP_NONE;
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
50
env->load_res = -1;
83
if (local_err != NULL) {
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
52
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
86
--- a/target/riscv/tcg/tcg-cpu.c
54
+++ b/target/riscv/cpu_helper.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
56
g_assert_not_reached();
57
}
89
}
58
env->badaddr = address;
59
+ env->two_stage_lookup = two_stage;
60
}
90
}
61
91
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
93
+{
64
}
94
+ GPtrArray *dynamic_decoders;
65
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
66
env->badaddr = addr;
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
97
+ if (decoder_table[i].guard_func &&
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
99
+ g_ptr_array_add(dynamic_decoders,
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
101
+ }
102
+ }
103
+
104
+ cpu->decoders = dynamic_decoders;
105
+}
106
+
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
108
{
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/riscv/translate.c
113
+++ b/target/riscv/translate.c
114
@@ -XXX,XX +XXX,XX @@
115
#include "exec/helper-info.c.inc"
116
#undef HELPER_H
117
118
+#include "tcg/tcg-cpu.h"
119
+
120
/* global register indices */
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
124
/* FRM is known to contain a valid value. */
125
bool frm_valid;
126
bool insn_start_updated;
127
+ const GPtrArray *decoders;
128
} DisasContext;
129
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
132
return (first_word & 3) == 3 ? 4 : 2;
70
}
133
}
71
134
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
135
+const RISCVDecoder decoder_table[] = {
73
g_assert_not_reached();
136
+ { always_true_p, decode_insn32 },
74
}
137
+ { has_xthead_p, decode_xthead},
75
env->badaddr = addr;
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
139
+};
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
140
+
78
riscv_raise_exception(env, cs->exception_index, retaddr);
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
79
}
142
+
80
#endif /* !CONFIG_USER_ONLY */
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
144
{
82
/* handle the trap in S-mode */
145
- /*
83
if (riscv_has_ext(env, RVH)) {
146
- * A table with predicate (i.e., guard) functions and decoder functions
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
147
- * that are tested in-order until a decoder matches onto the opcode.
85
- bool two_stage_lookup = false;
148
- */
86
149
- static const struct {
87
- if (env->priv == PRV_M ||
150
- bool (*guard_func)(const RISCVCPUConfig *);
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
151
- bool (*decode_func)(DisasContext *, uint32_t);
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
152
- } decoders[] = {
90
- get_field(env->hstatus, HSTATUS_HU))) {
153
- { always_true_p, decode_insn32 },
91
- two_stage_lookup = true;
154
- { has_xthead_p, decode_xthead },
92
- }
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
156
- };
93
-
157
-
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
158
ctx->virt_inst_excp = false;
95
+ if (env->two_stage_lookup && write_tval) {
159
ctx->cur_insn_len = insn_len(opcode);
96
/*
160
/* Check for compressed insn */
97
* If we are writing a guest virtual address to stval, set
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
98
* this to 1. If we are trapping to VS we will set this to 0
162
ctx->base.pc_next + 2));
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
163
ctx->opcode = opcode32;
100
riscv_cpu_set_force_hs_excep(env, 0);
164
101
} else {
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
102
/* Trap into HS mode */
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
103
- if (!two_stage_lookup) {
167
- decoders[i].decode_func(ctx, opcode32)) {
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
105
- riscv_cpu_virt_enabled(env));
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
106
- }
170
+ if (func(ctx, opcode32)) {
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
171
return;
108
htval = env->guest_phys_fault_addr;
109
}
172
}
110
}
173
}
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
112
* RISC-V ISA Specification.
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
113
*/
176
ctx->zero = tcg_constant_tl(0);
114
177
ctx->virt_inst_excp = false;
115
+ env->two_stage_lookup = false;
178
+ ctx->decoders = cpu->decoders;
116
#endif
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
118
}
179
}
180
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
119
--
182
--
120
2.30.1
183
2.45.1
121
122
diff view generated by jsdifflib
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
This adds the documentation to describe what is supported for the
3
The th.sxstatus CSR can be used to identify available custom extension
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
4
on T-Head CPUs. The CSR is documented here:
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
An important property of this patch is, that the th.sxstatus MAEE field
8
is not set (indicating that XTheadMae is not available).
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
25
---
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
26
MAINTAINERS | 1 +
12
docs/system/target-riscv.rst | 1 +
27
target/riscv/cpu.h | 3 ++
13
2 files changed, 90 insertions(+)
28
target/riscv/cpu.c | 1 +
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
30
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
15
33
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
34
diff --git a/MAINTAINERS b/MAINTAINERS
35
index XXXXXXX..XXXXXXX 100644
36
--- a/MAINTAINERS
37
+++ b/MAINTAINERS
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
39
S: Supported
40
F: target/riscv/insn_trans/trans_xthead.c.inc
41
F: target/riscv/xthead*.decode
42
+F: target/riscv/th_*
43
F: disas/riscv-xthead*
44
45
RISC-V XVentanaCondOps extension
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
51
uint8_t satp_mode_max_from_map(uint32_t map);
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
53
54
+/* Implemented in th_csr.c */
55
+void th_register_custom_csrs(RISCVCPU *cpu);
56
+
57
#endif /* RISCV_CPU_H */
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/cpu.c
61
+++ b/target/riscv/cpu.c
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
64
#ifndef CONFIG_USER_ONLY
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
66
+ th_register_custom_csrs(cpu);
67
#endif
68
69
/* inherited from parent obj via riscv_cpu_init() */
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
17
new file mode 100644
71
new file mode 100644
18
index XXXXXXX..XXXXXXX
72
index XXXXXXX..XXXXXXX
19
--- /dev/null
73
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
74
+++ b/target/riscv/th_csr.c
21
@@ -XXX,XX +XXX,XX @@
75
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
76
+/*
23
+=============================================================
77
+ * T-Head-specific CSRs.
78
+ *
79
+ * Copyright (c) 2024 VRULL GmbH
80
+ *
81
+ * This program is free software; you can redistribute it and/or modify it
82
+ * under the terms and conditions of the GNU General Public License,
83
+ * version 2 or later, as published by the Free Software Foundation.
84
+ *
85
+ * This program is distributed in the hope it will be useful, but WITHOUT
86
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
87
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
88
+ * more details.
89
+ *
90
+ * You should have received a copy of the GNU General Public License along with
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
92
+ */
24
+
93
+
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
94
+#include "qemu/osdep.h"
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
95
+#include "cpu.h"
96
+#include "cpu_vendorid.h"
27
+
97
+
28
+For more details about Microchip PolarFire SoC, please see:
98
+#define CSR_TH_SXSTATUS 0x5c0
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
30
+
99
+
31
+The Icicle Kit board information can be found here:
100
+/* TH_SXSTATUS bits */
32
+https://www.microsemi.com/existing-parts/parts/152514
101
+#define TH_SXSTATUS_UCME BIT(16)
102
+#define TH_SXSTATUS_MAEE BIT(21)
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
33
+
104
+
34
+Supported devices
105
+typedef struct {
35
+-----------------
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
36
+
110
+
37
+The ``microchip-icicle-kit`` machine supports the following devices:
111
+static RISCVException smode(CPURISCVState *env, int csrno)
112
+{
113
+ if (riscv_has_ext(env, RVS)) {
114
+ return RISCV_EXCP_NONE;
115
+ }
38
+
116
+
39
+ * 1 E51 core
117
+ return RISCV_EXCP_ILLEGAL_INST;
40
+ * 4 U54 cores
118
+}
41
+ * Core Level Interruptor (CLINT)
42
+ * Platform-Level Interrupt Controller (PLIC)
43
+ * L2 Loosely Integrated Memory (L2-LIM)
44
+ * DDR memory controller
45
+ * 5 MMUARTs
46
+ * 1 DMA controller
47
+ * 2 GEM Ethernet controllers
48
+ * 1 SDHC storage controller
49
+
119
+
50
+Boot options
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
51
+------------
121
+{
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
123
+ return -1;
124
+ }
52
+
125
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
126
+ return 0;
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
127
+}
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
56
+support direct kernel loading via the -kernel option. One has to load kernel
57
+from U-Boot.
58
+
128
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
60
+memory size by HSS. A sanity check on ram size is performed in the machine
130
+ target_ulong *val)
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
131
+{
62
+than 1537 MiB ram is detected.
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
134
+ return RISCV_EXCP_NONE;
135
+}
63
+
136
+
64
+Boot the machine
137
+static riscv_csr th_csr_list[] = {
65
+----------------
138
+ {
139
+ .csrno = CSR_TH_SXSTATUS,
140
+ .insertion_test = test_thead_mvendorid,
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
142
+ }
143
+};
66
+
144
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
145
+void th_register_custom_csrs(RISCVCPU *cpu)
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
146
+{
69
+in the HSS source tree:
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
70
+
148
+ int csrno = th_csr_list[i].csrno;
71
+.. code-block:: bash
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
72
+
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
73
+ $ export CROSS_COMPILE=riscv64-linux-
151
+ riscv_set_csr_ops(csrno, csr_ops);
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
152
+ }
75
+ $ make BOARD=mpfs-icicle-kit-es
153
+ }
76
+
154
+}
77
+Download the official SD card image released by Microchip and prepare it for
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
78
+QEMU usage:
79
+
80
+.. code-block:: bash
81
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
86
+Then we can boot the machine by:
87
+
88
+.. code-block:: bash
89
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
92
+ -nic user,model=cadence_gem \
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
94
+ -display none -serial stdio \
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
96
+ -serial chardev:serial1
97
+
98
+With above command line, current terminal session will be used for the first
99
+serial port. Open another terminal window, and use `minicom` to connect the
100
+second serial port.
101
+
102
+.. code-block:: bash
103
+
104
+ $ minicom -D unix\#serial1.sock
105
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
107
+second serial port. U-Boot will automatically load the Linux kernel from
108
+the SD card image.
109
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
112
index XXXXXXX..XXXXXXX 100644
156
index XXXXXXX..XXXXXXX 100644
113
--- a/docs/system/target-riscv.rst
157
--- a/target/riscv/meson.build
114
+++ b/docs/system/target-riscv.rst
158
+++ b/target/riscv/meson.build
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
116
.. toctree::
160
'monitor.c',
117
:maxdepth: 1
161
'machine.c',
118
162
'pmu.c',
119
+ riscv/microchip-icicle-kit
163
+ 'th_csr.c',
120
riscv/sifive_u
164
'time_helper.c',
121
165
'riscv-qmp-cmds.c',
122
RISC-V CPU features
166
))
123
--
167
--
124
2.30.1
168
2.45.1
125
169
126
170
diff view generated by jsdifflib
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Provides fw_cfg for the virt machine on riscv. This enables
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
using e.g. ramfb later.
4
instructions will be affected by Zvfhmin extension.
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
5
7
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
8
* From 1*SEW(16/32) to 2*SEW(32/64)
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
* From 2*SEW(32/64) to 1*SEW(16/32)
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
include/hw/riscv/virt.h | 2 ++
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
18
1 file changed, 18 insertions(+), 2 deletions(-)
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 33 insertions(+)
16
19
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
20
+++ b/include/hw/riscv/virt.h
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
25
}
23
DeviceState *plic[VIRT_SOCKETS_MAX];
24
PFlashCFI01 *flash[2];
25
+ FWCfgState *fw_cfg;
26
27
int fdt_size;
28
};
29
@@ -XXX,XX +XXX,XX @@ enum {
30
VIRT_PLIC,
31
VIRT_UART0,
32
VIRT_VIRTIO,
33
+ VIRT_FW_CFG,
34
VIRT_FLASH,
35
VIRT_DRAM,
36
VIRT_PCIE_MMIO,
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/riscv/virt.c
40
+++ b/hw/riscv/virt.c
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
43
[VIRT_UART0] = { 0x10000000, 0x100 },
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
50
return dev;
51
}
26
}
52
27
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
28
+static bool require_rvfmin(DisasContext *s)
54
+{
29
+{
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
31
+ return false;
57
+ FWCfgState *fw_cfg;
32
+ }
58
+ char *nodename;
59
+
33
+
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
34
+ switch (s->sew) {
61
+ &address_space_memory);
35
+ case MO_16:
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
36
+ return s->cfg_ptr->ext_zvfhmin;
63
+
37
+ case MO_32:
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
38
+ return s->cfg_ptr->ext_zve32f;
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
39
+ default:
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
40
+ return false;
67
+ "compatible", "qemu,fw-cfg-mmio");
41
+ }
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
73
+}
42
+}
74
+
43
+
75
static void virt_machine_init(MachineState *machine)
44
static bool require_scale_rvf(DisasContext *s)
76
{
45
{
77
const MemMapEntry *memmap = virt_memmap;
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
79
start_addr = virt_memmap[VIRT_FLASH].base;
80
}
48
}
81
49
82
+ /*
50
switch (s->sew) {
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
51
- case MO_8:
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
52
- return s->cfg_ptr->ext_zvfhmin;
85
+ */
53
case MO_16:
86
+ s->fw_cfg = create_fw_cfg(machine);
54
return s->cfg_ptr->ext_zve32f;
87
+ rom_set_fw(s->fw_cfg);
55
case MO_32:
88
+
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
89
/* Compute the fdt load address in dram */
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
58
{
91
machine->ram_size, machine->fdt);
59
return opfv_widen_check(s, a) &&
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
60
+ require_rvfmin(s) &&
93
index XXXXXXX..XXXXXXX 100644
61
require_scale_rvfmin(s) &&
94
--- a/hw/riscv/Kconfig
62
(s->sew != MO_8);
95
+++ b/hw/riscv/Kconfig
63
}
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
97
select SIFIVE_PLIC
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
98
select SIFIVE_TEST
66
{
99
select VIRTIO_MMIO
67
return opfv_narrow_check(s, a) &&
100
+ select FW_CFG_DMA
68
+ require_rvfmin(s) &&
101
69
require_scale_rvfmin(s) &&
102
config SIFIVE_E
70
(s->sew != MO_8);
103
bool
71
}
104
--
72
--
105
2.30.1
73
2.45.1
106
107
diff view generated by jsdifflib
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
3
The require_scale_rvf function only checks the double width operator for
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
the vector floating point widen instructions, so most of the widen
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
5
checking functions need to add require_rvf for single width operator.
6
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
8
integer to double width float, so the opfxv_widen_check function doesn’t
9
need require_rvf for the single width operator(integer).
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
16
---
8
target/riscv/csr.c | 7 ++++---
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
9
1 file changed, 4 insertions(+), 3 deletions(-)
18
1 file changed, 5 insertions(+)
10
19
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/csr.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
14
+++ b/target/riscv/csr.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
23
24
static const char valid_vm_1_10_32[16] = {
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
26
target_ulong new_value, target_ulong write_mask)
27
{
26
{
28
int ret = rmw_mip(env, 0, ret_value, new_value,
27
return require_rvv(s) &&
29
- write_mask & hip_writable_mask);
28
+ require_rvf(s) &&
30
+ write_mask & hvip_writable_mask);
29
require_scale_rvf(s) &&
31
30
(s->sew != MO_8) &&
32
- *ret_value &= hip_writable_mask;
31
vext_check_isa_ill(s) &&
33
+ *ret_value &= hvip_writable_mask;
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
34
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
35
return ret;
34
{
35
return require_rvv(s) &&
36
+ require_rvf(s) &&
37
require_scale_rvf(s) &&
38
(s->sew != MO_8) &&
39
vext_check_isa_ill(s) &&
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
42
{
43
return require_rvv(s) &&
44
+ require_rvf(s) &&
45
require_scale_rvf(s) &&
46
(s->sew != MO_8) &&
47
vext_check_isa_ill(s) &&
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
50
{
51
return require_rvv(s) &&
52
+ require_rvf(s) &&
53
require_scale_rvf(s) &&
54
(s->sew != MO_8) &&
55
vext_check_isa_ill(s) &&
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
58
{
59
return reduction_widen_check(s, a) &&
60
+ require_rvf(s) &&
61
require_scale_rvf(s) &&
62
(s->sew != MO_8);
36
}
63
}
37
--
64
--
38
2.30.1
65
2.45.1
39
66
40
67
diff view generated by jsdifflib
New patch
[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
1
From: Max Chou <max.chou@sifive.com>
1
2
3
The opfv_narrow_check needs to check the single width float operator by
4
require_rvf.
5
6
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
21
{
22
return opfv_narrow_check(s, a) &&
23
+ require_rvf(s) &&
24
require_scale_rvf(s) &&
25
(s->sew != MO_8);
26
}
27
--
28
2.45.1
diff view generated by jsdifflib
New patch
[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
1
From: Max Chou <max.chou@sifive.com>
1
2
3
If the checking functions check both the single and double width
4
operators at the same time, then the single width operator checking
5
functions (require_rvf[min]) will check whether the SEW is 8.
6
7
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
14
1 file changed, 4 insertions(+), 12 deletions(-)
15
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
return require_rvv(s) &&
22
require_rvf(s) &&
23
require_scale_rvf(s) &&
24
- (s->sew != MO_8) &&
25
vext_check_isa_ill(s) &&
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
27
}
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
return require_rvv(s) &&
30
require_rvf(s) &&
31
require_scale_rvf(s) &&
32
- (s->sew != MO_8) &&
33
vext_check_isa_ill(s) &&
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
37
return require_rvv(s) &&
38
require_rvf(s) &&
39
require_scale_rvf(s) &&
40
- (s->sew != MO_8) &&
41
vext_check_isa_ill(s) &&
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
45
return require_rvv(s) &&
46
require_rvf(s) &&
47
require_scale_rvf(s) &&
48
- (s->sew != MO_8) &&
49
vext_check_isa_ill(s) &&
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
51
}
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
53
{
54
return opfv_widen_check(s, a) &&
55
require_rvfmin(s) &&
56
- require_scale_rvfmin(s) &&
57
- (s->sew != MO_8);
58
+ require_scale_rvfmin(s);
59
}
60
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
63
{
64
return opfv_narrow_check(s, a) &&
65
require_rvfmin(s) &&
66
- require_scale_rvfmin(s) &&
67
- (s->sew != MO_8);
68
+ require_scale_rvfmin(s);
69
}
70
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
72
{
73
return opfv_narrow_check(s, a) &&
74
require_rvf(s) &&
75
- require_scale_rvf(s) &&
76
- (s->sew != MO_8);
77
+ require_scale_rvf(s);
78
}
79
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
82
{
83
return reduction_widen_check(s, a) &&
84
require_rvf(s) &&
85
- require_scale_rvf(s) &&
86
- (s->sew != MO_8);
87
+ require_scale_rvf(s);
88
}
89
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
91
--
92
2.45.1
diff view generated by jsdifflib
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
The current condition for the use of background registers only
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
considers the hypervisor load and store instructions,
4
checking first if virt_enabled && !first_stage, and then considering the
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
5
regular inst/load/store faults.
6
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
There's no mention in the spec about guest page fault being a higher
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
34
---
12
target/riscv/cpu_helper.c | 2 +-
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
13
1 file changed, 1 insertion(+), 1 deletion(-)
36
1 file changed, 12 insertions(+), 10 deletions(-)
14
37
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
40
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
20
* was called. Background registers will be used if the guest has
43
21
* forced a two stage translation to be on (in HS or M mode).
44
switch (access_type) {
22
*/
45
case MMU_INST_FETCH:
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
46
- if (env->virt_enabled && !first_stage) {
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
47
+ if (pmp_violation) {
25
use_background = true;
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
26
}
49
+ } else if (env->virt_enabled && !first_stage) {
27
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
51
} else {
52
- cs->exception_index = pmp_violation ?
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
55
}
56
break;
57
case MMU_DATA_LOAD:
58
- if (two_stage && !first_stage) {
59
+ if (pmp_violation) {
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
61
+ } else if (two_stage && !first_stage) {
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
63
} else {
64
- cs->exception_index = pmp_violation ?
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
67
}
68
break;
69
case MMU_DATA_STORE:
70
- if (two_stage && !first_stage) {
71
+ if (pmp_violation) {
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
73
+ } else if (two_stage && !first_stage) {
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
75
} else {
76
- cs->exception_index = pmp_violation ?
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
78
- RISCV_EXCP_STORE_PAGE_FAULT;
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
80
}
81
break;
82
default:
28
--
83
--
29
2.30.1
84
2.45.1
30
31
diff view generated by jsdifflib
[PULL 04/16] target/riscv: add log of PMP permission checking
[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
1
From: Jim Shu <cwshu@andestech.com>
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
2
2
3
Like MMU translation, add qemu log of PMP permission checking for
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
debugging.
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
5
7
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
14
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
21
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
22
target/riscv/cpu_helper.c | 12 ++++++------
12
1 file changed, 12 insertions(+)
23
1 file changed, 6 insertions(+), 6 deletions(-)
13
24
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
27
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
28
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
19
if (ret == TRANSLATE_SUCCESS) {
30
__func__, pa, ret, prot_pmp, tlb_size);
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
31
21
size, access_type, mode);
22
+
23
+ qemu_log_mask(CPU_LOG_MMU,
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
26
+ __func__, pa, ret, prot_pmp, tlb_size);
27
+
28
prot &= prot_pmp;
32
prot &= prot_pmp;
33
- }
34
-
35
- if (ret != TRANSLATE_SUCCESS) {
36
+ } else {
37
/*
38
* Guest physical address translation failed, this is a HS
39
* level exception
40
*/
41
first_stage_error = false;
42
- env->guest_phys_fault_addr = (im_address |
43
- (address &
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
45
+ if (ret != TRANSLATE_PMP_FAIL) {
46
+ env->guest_phys_fault_addr = (im_address |
47
+ (address &
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
49
+ }
29
}
50
}
30
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
32
if (ret == TRANSLATE_SUCCESS) {
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
34
size, access_type, mode);
35
+
36
+ qemu_log_mask(CPU_LOG_MMU,
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
39
+ __func__, pa, ret, prot_pmp, tlb_size);
40
+
41
prot &= prot_pmp;
42
}
51
}
43
}
52
} else {
44
--
53
--
45
2.30.1
54
2.45.1
46
47
diff view generated by jsdifflib
New patch
[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
1
From: Rob Bradford <rbradford@rivosinc.com>
1
2
3
This extension has now been ratified:
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
removed.
6
7
Since this is now a ratified extension add it to the list of extensions
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.c | 2 +-
19
target/riscv/tcg/tcg-cpu.c | 2 +-
20
2 files changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
32
};
33
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/tcg/tcg-cpu.c
38
+++ b/target/riscv/tcg/tcg-cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
40
const RISCVCPUMultiExtConfig *prop;
41
42
/* Enable RVG, RVJ and RVV that are disabled by default */
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
45
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
47
isa_ext_update_enabled(cpu, prop->offset, true);
48
--
49
2.45.1
diff view generated by jsdifflib
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
3
When running the instruction
4
further compressed instruction decoding. However, prior to this change,
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
6
fails to decode the instruction. This means that we skipped illegal
7
compressed instructions instead of raising an illegal instruction
8
exception.
9
4
10
Instead of patching decode_RV32_64C(), we can just remove it,
5
```
11
as it is dead code since f330433b363 anyway.
6
cbo.flush 0(x0)
7
```
12
8
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
9
QEMU would segfault.
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
26
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
31
Cc: qemu-stable <qemu-stable@nongnu.org>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
34
---
19
target/riscv/translate.c | 179 +--------------------------------------
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
20
1 file changed, 1 insertion(+), 178 deletions(-)
36
1 file changed, 12 insertions(+), 4 deletions(-)
21
37
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
23
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
25
+++ b/target/riscv/translate.c
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
42
@@ -XXX,XX +XXX,XX @@
27
CPUState *cs;
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
28
} DisasContext;
44
{
29
45
REQUIRE_ZICBOM(ctx);
30
-#ifdef TARGET_RISCV64
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
31
-/* convert riscv funct3 to qemu memop for load/store */
47
+ TCGv src = get_address(ctx, a->rs1, 0);
32
-static const int tcg_memop_lookup[8] = {
48
+
33
- [0 ... 7] = -1,
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
34
- [0] = MO_SB,
50
return true;
35
- [1] = MO_TESW,
36
- [2] = MO_TESL,
37
- [3] = MO_TEQ,
38
- [4] = MO_UB,
39
- [5] = MO_TEUW,
40
- [6] = MO_TEUL,
41
-};
42
-#endif
43
-
44
#ifdef TARGET_RISCV64
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
46
#else
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
48
ctx->base.is_jmp = DISAS_NORETURN;
49
}
51
}
50
52
51
-#ifdef TARGET_RISCV64
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
53
- target_long imm)
54
-{
55
- TCGv t0 = tcg_temp_new();
56
- TCGv t1 = tcg_temp_new();
57
- gen_get_gpr(t0, rs1);
58
- tcg_gen_addi_tl(t0, t0, imm);
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
60
-
61
- if (memop < 0) {
62
- gen_exception_illegal(ctx);
63
- return;
64
- }
65
-
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
67
- gen_set_gpr(rd, t1);
68
- tcg_temp_free(t0);
69
- tcg_temp_free(t1);
70
-}
71
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
73
- target_long imm)
74
-{
75
- TCGv t0 = tcg_temp_new();
76
- TCGv dat = tcg_temp_new();
77
- gen_get_gpr(t0, rs1);
78
- tcg_gen_addi_tl(t0, t0, imm);
79
- gen_get_gpr(dat, rs2);
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
81
-
82
- if (memop < 0) {
83
- gen_exception_illegal(ctx);
84
- return;
85
- }
86
-
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
88
- tcg_temp_free(t0);
89
- tcg_temp_free(dat);
90
-}
91
-#endif
92
-
93
#ifndef CONFIG_USER_ONLY
94
/* The states of mstatus_fs are:
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
98
#endif
99
100
-#if !defined(TARGET_RISCV64)
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
102
- int rs1, target_long imm)
103
-{
104
- TCGv t0;
105
-
106
- if (ctx->mstatus_fs == 0) {
107
- gen_exception_illegal(ctx);
108
- return;
109
- }
110
-
111
- t0 = tcg_temp_new();
112
- gen_get_gpr(t0, rs1);
113
- tcg_gen_addi_tl(t0, t0, imm);
114
-
115
- switch (opc) {
116
- case OPC_RISC_FLW:
117
- if (!has_ext(ctx, RVF)) {
118
- goto do_illegal;
119
- }
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
123
- break;
124
- case OPC_RISC_FLD:
125
- if (!has_ext(ctx, RVD)) {
126
- goto do_illegal;
127
- }
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
129
- break;
130
- do_illegal:
131
- default:
132
- gen_exception_illegal(ctx);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
139
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
141
- int rs2, target_long imm)
142
-{
143
- TCGv t0;
144
-
145
- if (ctx->mstatus_fs == 0) {
146
- gen_exception_illegal(ctx);
147
- return;
148
- }
149
-
150
- t0 = tcg_temp_new();
151
- gen_get_gpr(t0, rs1);
152
- tcg_gen_addi_tl(t0, t0, imm);
153
-
154
- switch (opc) {
155
- case OPC_RISC_FSW:
156
- if (!has_ext(ctx, RVF)) {
157
- goto do_illegal;
158
- }
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
54
{
179
TCGv_i32 t0;
55
REQUIRE_ZICBOM(ctx);
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
181
tcg_temp_free_i32(t0);
57
+ TCGv src = get_address(ctx, a->rs1, 0);
58
+
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
60
return true;
182
}
61
}
183
62
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
185
-{
186
- uint8_t funct3 = extract16(opcode, 13, 3);
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
188
- uint8_t rs1s = GET_C_RS1S(opcode);
189
-
190
- switch (funct3) {
191
- case 3:
192
-#if defined(TARGET_RISCV64)
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
195
- GET_C_LD_IMM(opcode));
196
-#else
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
199
- GET_C_LW_IMM(opcode));
200
-#endif
201
- break;
202
- case 7:
203
-#if defined(TARGET_RISCV64)
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
206
- GET_C_LD_IMM(opcode));
207
-#else
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
210
- GET_C_LW_IMM(opcode));
211
-#endif
212
- break;
213
- }
214
-}
215
-
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
64
{
229
return nf + 1;
65
REQUIRE_ZICBOM(ctx);
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
231
} else {
67
+ TCGv src = get_address(ctx, a->rs1, 0);
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
68
+
233
if (!decode_insn16(ctx, opcode)) {
69
+ gen_helper_cbo_inval(tcg_env, src);
234
- /* fall back to old decoder */
70
return true;
235
- decode_RV32_64C(ctx, opcode);
71
}
236
+ gen_exception_illegal(ctx);
72
237
}
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
238
}
74
{
239
} else {
75
REQUIRE_ZICBOZ(ctx);
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
77
+ TCGv src = get_address(ctx, a->rs1, 0);
78
+
79
+ gen_helper_cbo_zero(tcg_env, src);
80
return true;
81
}
240
--
82
--
241
2.30.1
83
2.45.1
242
243
diff view generated by jsdifflib
New patch
[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
1
2
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
number to locate the memory pages of interrupt files in the address
5
space. The number of bits required to represent any hart number is equal
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
8
9
However, if the largest hart number among groups is a power of 2, QEMU
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
27
1 file changed, 8 insertions(+), 1 deletion(-)
28
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/kvm/kvm-cpu.c
32
+++ b/target/riscv/kvm/kvm-cpu.c
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
34
}
35
}
36
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
38
+
39
+ if (max_hart_per_socket > 1) {
40
+ max_hart_per_socket--;
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
42
+ } else {
43
+ hart_bits = 0;
44
+ }
45
+
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
48
&hart_bits, true, NULL);
49
--
50
2.45.1
diff view generated by jsdifflib
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
the newest received byte. The rx_level variable is added to allow the use of
4
in bytes, when in this context we want 'reg_width' as the length in
5
the existing OpenTitan driver libraries.
5
bits.
6
6
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
9
beforehand.
10
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
12
clarity about what the variable represents. 'bitsize' is also used in
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
15
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
17
Cc: Alex Bennée <alex.bennee@linaro.org>
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
28
---
12
include/hw/char/ibex_uart.h | 4 ++++
29
target/riscv/gdbstub.c | 6 +++---
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
30
1 file changed, 3 insertions(+), 3 deletions(-)
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
31
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
17
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
34
--- a/target/riscv/gdbstub.c
19
+++ b/include/hw/char/ibex_uart.h
35
+++ b/target/riscv/gdbstub.c
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
23
REG32(FIFO_STATUS, 0x20)
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
26
REG32(OVRD, 0x24)
27
REG32(VAL, 0x28)
28
REG32(TIMEOUT_CTRL, 0x2c)
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
31
uint32_t tx_level;
32
33
+ uint32_t rx_level;
34
+
35
QEMUTimer *fifo_trigger_handle;
36
uint64_t char_tx_time;
37
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/char/ibex_uart.c
41
+++ b/hw/char/ibex_uart.c
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
43
{
38
{
44
IbexUartState *s = opaque;
39
RISCVCPU *cpu = RISCV_CPU(cs);
45
40
- int reg_width = cpu->cfg.vlenb;
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
41
+ int bitsize = cpu->cfg.vlenb << 3;
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
42
GDBFeatureBuilder builder;
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
43
int i;
49
return 1;
44
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
46
47
/* First define types and totals in a whole VL */
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
49
- int count = reg_width / vec_lanes[i].size;
50
+ int count = bitsize / vec_lanes[i].size;
51
gdb_feature_builder_append_tag(
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
55
/* Define vector registers */
56
for (i = 0; i < 32; i++) {
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
58
- reg_width, i, "riscv_vector", "vector");
59
+ bitsize, i, "riscv_vector", "vector");
50
}
60
}
51
61
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
62
gdb_feature_builder_end(&builder);
53
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
+ /* The RXFULL is set after receiving a single byte
57
+ * as the FIFO buffers are not yet implemented.
58
+ */
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
+ s->rx_level += 1;
61
62
if (size > rx_fifo_level) {
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
s->uart_timeout_ctrl = 0x00000000;
66
67
s->tx_level = 0;
68
+ s->rx_level = 0;
69
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
74
case R_RDATA:
75
retvalue = s->uart_rdata;
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
qemu_chr_fe_accept_input(&s->chr);
79
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ s->rx_level -= 1;
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ if (s->rx_level == 0) {
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
+ }
88
}
89
break;
90
case R_WDATA:
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
63
--
110
2.30.1
64
2.45.1
111
65
112
66
diff view generated by jsdifflib
New patch
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
1
From: Alistair Francis <alistair23@gmail.com>
1
2
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
CSRs are part of the disassembly.
6
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Fixes: ea10325917 ("RISC-V Disassembler")
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
16
1 file changed, 64 insertions(+), 1 deletion(-)
17
18
diff --git a/disas/riscv.c b/disas/riscv.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/disas/riscv.c
21
+++ b/disas/riscv.c
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
23
case 0x0383: return "mibound";
24
case 0x0384: return "mdbase";
25
case 0x0385: return "mdbound";
26
- case 0x03a0: return "pmpcfg3";
27
+ case 0x03a0: return "pmpcfg0";
28
+ case 0x03a1: return "pmpcfg1";
29
+ case 0x03a2: return "pmpcfg2";
30
+ case 0x03a3: return "pmpcfg3";
31
+ case 0x03a4: return "pmpcfg4";
32
+ case 0x03a5: return "pmpcfg5";
33
+ case 0x03a6: return "pmpcfg6";
34
+ case 0x03a7: return "pmpcfg7";
35
+ case 0x03a8: return "pmpcfg8";
36
+ case 0x03a9: return "pmpcfg9";
37
+ case 0x03aa: return "pmpcfg10";
38
+ case 0x03ab: return "pmpcfg11";
39
+ case 0x03ac: return "pmpcfg12";
40
+ case 0x03ad: return "pmpcfg13";
41
+ case 0x03ae: return "pmpcfg14";
42
+ case 0x03af: return "pmpcfg15";
43
case 0x03b0: return "pmpaddr0";
44
case 0x03b1: return "pmpaddr1";
45
case 0x03b2: return "pmpaddr2";
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
47
case 0x03bd: return "pmpaddr13";
48
case 0x03be: return "pmpaddr14";
49
case 0x03bf: return "pmpaddr15";
50
+ case 0x03c0: return "pmpaddr16";
51
+ case 0x03c1: return "pmpaddr17";
52
+ case 0x03c2: return "pmpaddr18";
53
+ case 0x03c3: return "pmpaddr19";
54
+ case 0x03c4: return "pmpaddr20";
55
+ case 0x03c5: return "pmpaddr21";
56
+ case 0x03c6: return "pmpaddr22";
57
+ case 0x03c7: return "pmpaddr23";
58
+ case 0x03c8: return "pmpaddr24";
59
+ case 0x03c9: return "pmpaddr25";
60
+ case 0x03ca: return "pmpaddr26";
61
+ case 0x03cb: return "pmpaddr27";
62
+ case 0x03cc: return "pmpaddr28";
63
+ case 0x03cd: return "pmpaddr29";
64
+ case 0x03ce: return "pmpaddr30";
65
+ case 0x03cf: return "pmpaddr31";
66
+ case 0x03d0: return "pmpaddr32";
67
+ case 0x03d1: return "pmpaddr33";
68
+ case 0x03d2: return "pmpaddr34";
69
+ case 0x03d3: return "pmpaddr35";
70
+ case 0x03d4: return "pmpaddr36";
71
+ case 0x03d5: return "pmpaddr37";
72
+ case 0x03d6: return "pmpaddr38";
73
+ case 0x03d7: return "pmpaddr39";
74
+ case 0x03d8: return "pmpaddr40";
75
+ case 0x03d9: return "pmpaddr41";
76
+ case 0x03da: return "pmpaddr42";
77
+ case 0x03db: return "pmpaddr43";
78
+ case 0x03dc: return "pmpaddr44";
79
+ case 0x03dd: return "pmpaddr45";
80
+ case 0x03de: return "pmpaddr46";
81
+ case 0x03df: return "pmpaddr47";
82
+ case 0x03e0: return "pmpaddr48";
83
+ case 0x03e1: return "pmpaddr49";
84
+ case 0x03e2: return "pmpaddr50";
85
+ case 0x03e3: return "pmpaddr51";
86
+ case 0x03e4: return "pmpaddr52";
87
+ case 0x03e5: return "pmpaddr53";
88
+ case 0x03e6: return "pmpaddr54";
89
+ case 0x03e7: return "pmpaddr55";
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
101
--
102
2.45.1
diff view generated by jsdifflib
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Yu-Ming Chang <yumin686@andestech.com>
2
2
3
The previous implementation was broken in many ways:
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
- Used mideleg instead of hideleg to mask accesses
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
5
holding a zero value other than x0, the instruction will still attempt to write
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
6
the unmodified value back to the CSR and will cause any attendant side effects.
7
7
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
16
---
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
17
target/riscv/cpu.h | 4 ++++
14
1 file changed, 34 insertions(+), 34 deletions(-)
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
15
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
27
void riscv_cpu_update_mask(CPURISCVState *env);
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
29
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
31
+ target_ulong *ret_value);
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
33
target_ulong *ret_value,
34
target_ulong new_value, target_ulong write_mask);
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
36
target_ulong new_value,
37
target_ulong write_mask);
38
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
40
+ Int128 *ret_value);
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
42
Int128 *ret_value,
43
Int128 new_value, Int128 write_mask);
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
46
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
47
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
21
return write_mstatus(env, CSR_MSTATUS, newval);
49
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
51
int csrno,
52
- bool write_mask)
53
+ bool write)
54
{
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
56
bool read_only = get_field(csrno, 0xC00) == 3;
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
58
}
59
60
/* read / write check */
61
- if (write_mask && read_only) {
62
+ if (write && read_only) {
63
return RISCV_EXCP_ILLEGAL_INST;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
67
return RISCV_EXCP_NONE;
22
}
68
}
23
69
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
71
+ target_ulong *ret_value)
25
+{
72
+{
26
+ /* Shift the VS bits to their S bit location in vsie */
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
74
+ if (ret != RISCV_EXCP_NONE) {
28
+ return 0;
75
+ return ret;
76
+ }
77
+
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
29
+}
79
+}
30
+
80
+
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
32
{
84
{
33
if (riscv_cpu_virt_enabled(env)) {
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
87
if (ret != RISCV_EXCP_NONE) {
36
+ read_vsie(env, CSR_VSIE, val);
88
return ret;
37
} else {
38
*val = env->mie & env->mideleg;
39
}
89
}
40
return 0;
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
91
return RISCV_EXCP_NONE;
41
}
92
}
42
93
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
95
+ Int128 *ret_value)
45
{
46
- target_ulong newval;
47
+ /* Shift the S bits to their VS bit location in mie */
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
50
+ return write_mie(env, CSR_MIE, newval);
51
+}
52
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
54
+{
96
+{
55
if (riscv_cpu_virt_enabled(env)) {
97
+ RISCVException ret;
56
- /* Shift the guests S bits to VS */
98
+
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
99
+ ret = riscv_csrrw_check(env, csrno, false);
58
- ((val << 1) & VS_MODE_INTERRUPTS);
100
+ if (ret != RISCV_EXCP_NONE) {
59
+ write_vsie(env, CSR_VSIE, val);
101
+ return ret;
60
} else {
102
+ }
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
103
+
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
104
+ if (csr_ops[csrno].read128) {
63
+ (val & S_MODE_INTERRUPTS);
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
64
+ write_mie(env, CSR_MIE, newval);
106
+ int128_zero(), int128_zero());
65
}
107
+ }
66
108
+
67
- return write_mie(env, CSR_MIE, newval);
109
+ /*
68
+ return 0;
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
69
}
111
+ * at all defined.
70
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
113
+ * significant), for those, this fallback is correctly handling the
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
114
+ * accesses
73
return 0;
115
+ */
74
}
116
+ target_ulong old_value;
75
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
118
+ (target_ulong)0,
77
+ target_ulong new_value, target_ulong write_mask)
119
+ (target_ulong)0);
78
+{
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
79
+ /* Shift the S bits to their VS bit location in mip */
121
+ *ret_value = int128_make64(old_value);
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
122
+ }
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
123
+ return ret;
86
+}
124
+}
87
+
125
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
89
target_ulong new_value, target_ulong write_mask)
127
Int128 *ret_value,
128
Int128 new_value, Int128 write_mask)
90
{
129
{
91
int ret;
130
RISCVException ret;
92
131
93
if (riscv_cpu_virt_enabled(env)) {
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
94
- /* Shift the new values to line up with the VS bits */
133
+ ret = riscv_csrrw_check(env, csrno, true);
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
134
if (ret != RISCV_EXCP_NONE) {
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
135
return ret;
97
- ret &= vsip_writable_mask;
136
}
98
- ret >>= 1;
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
138
index XXXXXXX..XXXXXXX 100644
100
} else {
139
--- a/target/riscv/op_helper.c
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
140
+++ b/target/riscv/op_helper.c
102
write_mask & env->mideleg & sip_writable_mask);
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
142
}
104
return 0;
143
105
}
144
target_ulong val = 0;
106
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
108
- target_ulong new_value, target_ulong write_mask)
147
109
-{
148
if (ret != RISCV_EXCP_NONE) {
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
149
riscv_raise_exception(env, ret, GETPC());
111
- write_mask & env->mideleg & vsip_writable_mask);
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
112
- return ret;
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
152
{
129
*val = env->vstvec;
153
Int128 rv = int128_zero();
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
155
- int128_zero(),
156
- int128_zero());
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
158
159
if (ret != RISCV_EXCP_NONE) {
160
riscv_raise_exception(env, ret, GETPC());
130
--
161
--
131
2.30.1
162
2.45.1
132
133
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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