[PULL 00/16] riscv-to-apply queue
[PULL 00/34] riscv-to-apply queue
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The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240308-1
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for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
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for you to fetch changes up to 301876597112218c1e465ecc2b2fef6b27d5c27b:
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target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
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target/riscv: fix ACPI MCFG table (2024-03-08 21:00:37 +1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
14
RISC-V PR for 6.0
14
RISC-V PR for 9.0
15
15
16
This PR includes:
16
* Update $ra with current $pc in trans_cm_jalt
17
- Fix for vector CSR access
17
* Enable SPCR for SCPI virt machine
18
- Improvements to the Ibex UART device
18
* Allow large kernels to boot by moving the initrd further away in RAM
19
- PMP improvements and bug fixes
19
* Sync hwprobe keys with kernel
20
- Hypervisor extension bug fixes
20
* Named features riscv,isa, 'svade' rework
21
- ramfb support for the virt machine
21
* FIX xATP_MODE validation
22
- Fast read support for SST flash
22
* Add missing include guard in pmu.h
23
- Improvements to the microchip_pfsoc machine
23
* Add SRAT and SLIT ACPI tables
24
* libqos fixes and add a riscv machine
25
* Add Ztso extension
26
* Use 'zfa' instead of 'Zfa'
27
* Update KVM exts to Linux 6.8
28
* move ratified/frozen exts to non-experimental
29
* Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit
30
* mark_vs_dirty() before loads and stores
31
* Remove 'is_store' bool from load/store fns
32
* Fix shift count overflow
33
* Fix setipnum_le write emulation for APLIC MSI-mode
34
* Fix in_clrip[x] read emulation
35
* Fix privilege mode of G-stage translation for debugging
36
* Fix ACPI MCFG table for virt machine
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Alexander Wagner (1):
39
Alexandre Ghiti (1):
27
hw/char: disable ibex uart receive if the buffer is full
40
hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM
28
41
29
Asherah Connor (2):
42
Andrew Jones (3):
30
hw/riscv: Add fw_cfg support to virt
43
target/riscv: Reset henvcfg to zero
31
hw/riscv: allow ramfb on virt
44
target/riscv: Gate hardware A/D PTE bit updating
45
target/riscv: Promote svade to a normal extension
32
46
33
Bin Meng (3):
47
Anup Patel (2):
34
hw/block: m25p80: Support fast read for SST flashes
48
hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
49
hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
50
51
Christoph Müllner (4):
52
linux-user/riscv: Add Zicboz extensions to hwprobe
53
linux-user/riscv: Sync hwprobe keys with Linux
54
linux-user/riscv: Add Ztso extension to hwprobe
55
tests: riscv64: Use 'zfa' instead of 'Zfa'
56
57
Daniel Henrique Barboza (12):
58
target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
59
target/riscv: add riscv,isa to named features
60
target/riscv: add remaining named features
61
hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
62
hw/riscv/virt.c: add virtio-iommu-pci hotplug support
63
hw/riscv/virt.c: make aclint compatible with 'qtest' accel
64
tests/libqos: add riscv/virt machine nodes
65
linux-headers: Update to Linux v6.8-rc6
66
target/riscv/kvm: update KVM exts to Linux 6.8
67
target/riscv: move ratified/frozen exts to non-experimental
68
trans_rvv.c.inc: mark_vs_dirty() before loads and stores
69
trans_rvv.c.inc: remove 'is_store' bool from load/store fns
37
70
38
Frank Chang (1):
71
Frank Chang (1):
39
target/riscv: fix vs() to return proper error code
72
target/riscv: Add missing include guard in pmu.h
40
73
41
Georg Kotheimer (6):
74
Haibo Xu (1):
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
75
hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
43
target/riscv: Make VSTIP and VSEIP read-only in hip
44
target/riscv: Use background registers also for MSTATUS_MPV
45
target/riscv: Fix read and write accesses to vsip and vsie
46
target/riscv: Add proper two-stage lookup exception detection
47
target/riscv: Prevent lost illegal instruction exceptions
48
76
49
Jim Shu (3):
77
Hiroaki Yamamoto (1):
50
target/riscv: propagate PMP permission to TLB page
78
target/riscv: Fix privilege mode of G-stage translation for debugging
51
target/riscv: add log of PMP permission checking
52
target/riscv: flush TLB pages if PMP permission has been changed
53
79
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
80
Ilya Chugin (1):
55
docs/system/target-riscv.rst | 1 +
81
target/riscv: fix ACPI MCFG table
56
include/hw/char/ibex_uart.h | 4 +
57
include/hw/riscv/microchip_pfsoc.h | 1 +
58
include/hw/riscv/virt.h | 2 +
59
target/riscv/cpu.h | 4 +
60
target/riscv/pmp.h | 4 +-
61
hw/block/m25p80.c | 3 +
62
hw/char/ibex_uart.c | 23 +++-
63
hw/riscv/microchip_pfsoc.c | 6 +
64
hw/riscv/virt.c | 33 ++++++
65
target/riscv/cpu.c | 1 +
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
67
target/riscv/csr.c | 77 +++++++------
68
target/riscv/pmp.c | 84 ++++++++++----
69
target/riscv/translate.c | 179 +----------------------------
70
hw/riscv/Kconfig | 1 +
71
17 files changed, 367 insertions(+), 289 deletions(-)
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
73
82
83
Irina Ryapolova (2):
84
target/riscv: FIX xATP_MODE validation
85
target/riscv: UPDATE xATP write CSR
86
87
Jason Chien (1):
88
target/riscv: Update $ra with current $pc in trans_cm_jalt()
89
90
Palmer Dabbelt (1):
91
RISC-V: Add support for Ztso
92
93
Sia Jee Heng (2):
94
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
95
hw/riscv/virt-acpi-build.c: Generate SPCR table
96
97
Vadim Shakirov (1):
98
target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
99
100
demin.han (1):
101
target/riscv: Fix shift count overflow
102
103
include/hw/acpi/acpi-defs.h | 33 ++++++
104
include/hw/acpi/aml-build.h | 4 +
105
include/standard-headers/drm/drm_fourcc.h | 10 +-
106
include/standard-headers/linux/ethtool.h | 41 +++++---
107
include/standard-headers/linux/virtio_config.h | 8 +-
108
include/standard-headers/linux/virtio_pci.h | 68 ++++++++++++
109
include/standard-headers/linux/virtio_pmem.h | 7 ++
110
linux-headers/asm-generic/unistd.h | 15 ++-
111
linux-headers/asm-mips/mman.h | 2 +-
112
linux-headers/asm-mips/unistd_n32.h | 5 +
113
linux-headers/asm-mips/unistd_n64.h | 5 +
114
linux-headers/asm-mips/unistd_o32.h | 5 +
115
linux-headers/asm-powerpc/unistd_32.h | 5 +
116
linux-headers/asm-powerpc/unistd_64.h | 5 +
117
linux-headers/asm-riscv/kvm.h | 40 +++++++
118
linux-headers/asm-s390/unistd_32.h | 5 +
119
linux-headers/asm-s390/unistd_64.h | 5 +
120
linux-headers/asm-x86/kvm.h | 3 +
121
linux-headers/asm-x86/unistd_32.h | 5 +
122
linux-headers/asm-x86/unistd_64.h | 5 +
123
linux-headers/asm-x86/unistd_x32.h | 5 +
124
linux-headers/linux/iommufd.h | 79 ++++++++++++++
125
linux-headers/linux/kvm.h | 140 +++++++++----------------
126
linux-headers/linux/userfaultfd.h | 29 ++++-
127
linux-headers/linux/vfio.h | 1 +
128
target/riscv/cpu.h | 8 +-
129
target/riscv/cpu_cfg.h | 13 ++-
130
target/riscv/pmu.h | 5 +
131
hw/acpi/aml-build.c | 53 ++++++++++
132
hw/arm/virt-acpi-build.c | 68 +++++-------
133
hw/intc/riscv_aplic.c | 37 +++++--
134
hw/riscv/boot.c | 12 +--
135
hw/riscv/virt-acpi-build.c | 103 +++++++++++++++++-
136
hw/riscv/virt.c | 97 ++++++++++++-----
137
linux-user/syscall.c | 104 ++++++++++++++++--
138
target/riscv/cpu.c | 94 +++++++++++------
139
target/riscv/cpu_helper.c | 21 +++-
140
target/riscv/csr.c | 58 +++++-----
141
target/riscv/kvm/kvm-cpu.c | 29 +++++
142
target/riscv/machine.c | 16 +--
143
target/riscv/tcg/tcg-cpu.c | 34 +++---
144
target/riscv/translate.c | 3 +
145
target/riscv/vector_helper.c | 5 +-
146
tests/qtest/libqos/riscv-virt-machine.c | 137 ++++++++++++++++++++++++
147
target/riscv/insn_trans/trans_rva.c.inc | 11 +-
148
target/riscv/insn_trans/trans_rvi.c.inc | 16 ++-
149
target/riscv/insn_trans/trans_rvv.c.inc | 97 +++++++++--------
150
target/riscv/insn_trans/trans_rvzce.c.inc | 6 +-
151
tests/qtest/libqos/meson.build | 1 +
152
tests/tcg/riscv64/Makefile.target | 2 +-
153
50 files changed, 1213 insertions(+), 347 deletions(-)
154
create mode 100644 tests/qtest/libqos/riscv-virt-machine.c
155
diff view generated by jsdifflib
New patch
[PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
The original implementation sets $pc to the address read from the jump
4
vector table first and links $ra with the address of the next instruction
5
after the updated $pc. After jumping to the updated $pc and executing the
6
next ret instruction, the program jumps to $ra, which is in the same
7
function currently executing, which results in an infinite loop.
8
This commit stores the jump address in a temporary, updates $ra with the
9
current $pc, and copies the temporary to $pc.
10
11
Signed-off-by: Jason Chien <jason.chien@sifive.com>
12
Reviewed-by: Frank Chang <frank.chang@sifive.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-ID: <20240207081820.28559-1-jason.chien@sifive.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
23
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
24
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
25
{
26
REQUIRE_ZCMT(ctx);
27
28
+ TCGv addr = tcg_temp_new();
29
+
30
/*
31
* Update pc to current for the non-unwinding exception
32
* that might come from cpu_ld*_code() in the helper.
33
*/
34
gen_update_pc(ctx, 0);
35
- gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
36
+ gen_helper_cm_jalt(addr, tcg_env, tcg_constant_i32(a->index));
37
38
/* c.jt vs c.jalt depends on the index. */
39
if (a->index >= 32) {
40
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
41
gen_set_gpr(ctx, xRA, succ_pc);
42
}
43
44
+ tcg_gen_mov_tl(cpu_pc, addr);
45
+
46
tcg_gen_lookup_and_goto_ptr();
47
ctx->base.is_jmp = DISAS_NORETURN;
48
return true;
49
--
50
2.44.0
diff view generated by jsdifflib
New patch
[PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
1
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
1
2
3
RISC-V should also generate the SPCR in a manner similar to ARM.
4
Therefore, instead of replicating the code, relocate this function
5
to the common AML build.
6
7
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20240129021440.17640-2-jeeheng.sia@starfivetech.com>
10
[ Changes by AF:
11
- Add missing Language SPCR entry
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/acpi/acpi-defs.h | 33 ++++++++++++++++++
16
include/hw/acpi/aml-build.h | 4 +++
17
hw/acpi/aml-build.c | 53 +++++++++++++++++++++++++++++
18
hw/arm/virt-acpi-build.c | 68 +++++++++++++++----------------------
19
4 files changed, 117 insertions(+), 41 deletions(-)
20
21
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/acpi/acpi-defs.h
24
+++ b/include/hw/acpi/acpi-defs.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AcpiFadtData {
26
unsigned *xdsdt_tbl_offset;
27
} AcpiFadtData;
28
29
+typedef struct AcpiGas {
30
+ uint8_t id; /* Address space ID */
31
+ uint8_t width; /* Register bit width */
32
+ uint8_t offset; /* Register bit offset */
33
+ uint8_t size; /* Access size */
34
+ uint64_t addr; /* Address */
35
+} AcpiGas;
36
+
37
+/* SPCR (Serial Port Console Redirection table) */
38
+typedef struct AcpiSpcrData {
39
+ uint8_t interface_type;
40
+ uint8_t reserved[3];
41
+ struct AcpiGas base_addr;
42
+ uint8_t interrupt_type;
43
+ uint8_t pc_interrupt;
44
+ uint32_t interrupt; /* Global system interrupt */
45
+ uint8_t baud_rate;
46
+ uint8_t parity;
47
+ uint8_t stop_bits;
48
+ uint8_t flow_control;
49
+ uint8_t terminal_type;
50
+ uint8_t language;
51
+ uint8_t reserved1;
52
+ uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
53
+ uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
54
+ uint8_t pci_bus;
55
+ uint8_t pci_device;
56
+ uint8_t pci_function;
57
+ uint32_t pci_flags;
58
+ uint8_t pci_segment;
59
+ uint32_t reserved2;
60
+} AcpiSpcrData;
61
+
62
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
63
#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
64
65
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/acpi/aml-build.h
68
+++ b/include/hw/acpi/aml-build.h
69
@@ -XXX,XX +XXX,XX @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
70
71
void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
72
const char *oem_id, const char *oem_table_id);
73
+
74
+void build_spcr(GArray *table_data, BIOSLinker *linker,
75
+ const AcpiSpcrData *f, const uint8_t rev,
76
+ const char *oem_id, const char *oem_table_id);
77
#endif
78
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/acpi/aml-build.c
81
+++ b/hw/acpi/aml-build.c
82
@@ -XXX,XX +XXX,XX @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
83
}
84
}
85
86
+void build_spcr(GArray *table_data, BIOSLinker *linker,
87
+ const AcpiSpcrData *f, const uint8_t rev,
88
+ const char *oem_id, const char *oem_table_id)
89
+{
90
+ AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
91
+ .oem_table_id = oem_table_id };
92
+
93
+ acpi_table_begin(&table, table_data);
94
+ /* Interface type */
95
+ build_append_int_noprefix(table_data, f->interface_type, 1);
96
+ /* Reserved */
97
+ build_append_int_noprefix(table_data, 0, 3);
98
+ /* Base Address */
99
+ build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
100
+ f->base_addr.offset, f->base_addr.size,
101
+ f->base_addr.addr);
102
+ /* Interrupt type */
103
+ build_append_int_noprefix(table_data, f->interrupt_type, 1);
104
+ /* IRQ */
105
+ build_append_int_noprefix(table_data, f->pc_interrupt, 1);
106
+ /* Global System Interrupt */
107
+ build_append_int_noprefix(table_data, f->interrupt, 4);
108
+ /* Baud Rate */
109
+ build_append_int_noprefix(table_data, f->baud_rate, 1);
110
+ /* Parity */
111
+ build_append_int_noprefix(table_data, f->parity, 1);
112
+ /* Stop Bits */
113
+ build_append_int_noprefix(table_data, f->stop_bits, 1);
114
+ /* Flow Control */
115
+ build_append_int_noprefix(table_data, f->flow_control, 1);
116
+ /* Language */
117
+ build_append_int_noprefix(table_data, f->language, 1);
118
+ /* Terminal Type */
119
+ build_append_int_noprefix(table_data, f->terminal_type, 1);
120
+ /* PCI Device ID */
121
+ build_append_int_noprefix(table_data, f->pci_device_id, 2);
122
+ /* PCI Vendor ID */
123
+ build_append_int_noprefix(table_data, f->pci_vendor_id, 2);
124
+ /* PCI Bus Number */
125
+ build_append_int_noprefix(table_data, f->pci_bus, 1);
126
+ /* PCI Device Number */
127
+ build_append_int_noprefix(table_data, f->pci_device, 1);
128
+ /* PCI Function Number */
129
+ build_append_int_noprefix(table_data, f->pci_function, 1);
130
+ /* PCI Flags */
131
+ build_append_int_noprefix(table_data, f->pci_flags, 4);
132
+ /* PCI Segment */
133
+ build_append_int_noprefix(table_data, f->pci_segment, 1);
134
+ /* Reserved */
135
+ build_append_int_noprefix(table_data, 0, 4);
136
+
137
+ acpi_table_end(linker, &table);
138
+}
139
/*
140
* ACPI spec, Revision 6.3
141
* 5.2.29 Processor Properties Topology Table (PPTT)
142
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/hw/arm/virt-acpi-build.c
145
+++ b/hw/arm/virt-acpi-build.c
146
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
147
* Rev: 1.07
148
*/
149
static void
150
-build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
151
+spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
152
{
153
- AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
154
- .oem_table_id = vms->oem_table_id };
155
-
156
- acpi_table_begin(&table, table_data);
157
-
158
- /* Interface Type */
159
- build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
160
- build_append_int_noprefix(table_data, 0, 3); /* Reserved */
161
- /* Base Address */
162
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
163
- vms->memmap[VIRT_UART].base);
164
- /* Interrupt Type */
165
- build_append_int_noprefix(table_data,
166
- (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
167
- build_append_int_noprefix(table_data, 0, 1); /* IRQ */
168
- /* Global System Interrupt */
169
- build_append_int_noprefix(table_data,
170
- vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
171
- build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
172
- build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
173
- /* Stop Bits */
174
- build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
175
- /* Flow Control */
176
- build_append_int_noprefix(table_data,
177
- (1 << 1) /* RTS/CTS hardware flow control */, 1);
178
- /* Terminal Type */
179
- build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
180
- build_append_int_noprefix(table_data, 0, 1); /* Language */
181
- /* PCI Device ID */
182
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
183
- /* PCI Vendor ID */
184
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
185
- build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
186
- build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
187
- build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
188
- build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
189
- build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
190
- build_append_int_noprefix(table_data, 0, 4); /* Reserved */
191
+ AcpiSpcrData serial = {
192
+ .interface_type = 3, /* ARM PL011 UART */
193
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
194
+ .base_addr.width = 32,
195
+ .base_addr.offset = 0,
196
+ .base_addr.size = 3,
197
+ .base_addr.addr = vms->memmap[VIRT_UART].base,
198
+ .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
199
+ .pc_interrupt = 0, /* IRQ */
200
+ .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE),
201
+ .baud_rate = 3, /* 9600 */
202
+ .parity = 0, /* No Parity */
203
+ .stop_bits = 1, /* 1 Stop bit */
204
+ .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
205
+ .terminal_type = 0, /* VT100 */
206
+ .language = 0, /* Language */
207
+ .pci_device_id = 0xffff, /* not a PCI device*/
208
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
209
+ .pci_bus = 0,
210
+ .pci_device = 0,
211
+ .pci_function = 0,
212
+ .pci_flags = 0,
213
+ .pci_segment = 0,
214
+ };
215
216
- acpi_table_end(linker, &table);
217
+ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
218
}
219
220
/*
221
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
222
}
223
224
acpi_add_table(table_offsets, tables_blob);
225
- build_spcr(tables_blob, tables->linker, vms);
226
+ spcr_setup(tables_blob, tables->linker, vms);
227
228
acpi_add_table(table_offsets, tables_blob);
229
build_dbg2(tables_blob, tables->linker, vms);
230
--
231
2.44.0
diff view generated by jsdifflib
New patch
[PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table
1
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
1
2
3
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
4
virtual machine.
5
6
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++
12
1 file changed, 39 insertions(+)
13
14
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt-acpi-build.c
17
+++ b/hw/riscv/virt-acpi-build.c
18
@@ -XXX,XX +XXX,XX @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
19
aml_append(scope, dev);
20
}
21
22
+/*
23
+ * Serial Port Console Redirection Table (SPCR)
24
+ * Rev: 1.07
25
+ */
26
+
27
+static void
28
+spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
29
+{
30
+ AcpiSpcrData serial = {
31
+ .interface_type = 0, /* 16550 compatible */
32
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
33
+ .base_addr.width = 32,
34
+ .base_addr.offset = 0,
35
+ .base_addr.size = 1,
36
+ .base_addr.addr = s->memmap[VIRT_UART0].base,
37
+ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
38
+ .pc_interrupt = 0,
39
+ .interrupt = UART0_IRQ,
40
+ .baud_rate = 7, /* 15200 */
41
+ .parity = 0,
42
+ .stop_bits = 1,
43
+ .flow_control = 0,
44
+ .terminal_type = 3, /* ANSI */
45
+ .language = 0, /* Language */
46
+ .pci_device_id = 0xffff, /* not a PCI device*/
47
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
48
+ .pci_bus = 0,
49
+ .pci_device = 0,
50
+ .pci_function = 0,
51
+ .pci_flags = 0,
52
+ .pci_segment = 0,
53
+ };
54
+
55
+ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
56
+}
57
+
58
/* RHCT Node[N] starts at offset 56 */
59
#define RHCT_NODE_ARRAY_OFFSET 56
60
61
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
62
acpi_add_table(table_offsets, tables_blob);
63
build_rhct(tables_blob, tables->linker, s);
64
65
+ acpi_add_table(table_offsets, tables_blob);
66
+ spcr_setup(tables_blob, tables->linker, s);
67
+
68
acpi_add_table(table_offsets, tables_blob);
69
{
70
AcpiMcfgInfo mcfg = {
71
--
72
2.44.0
diff view generated by jsdifflib
New patch
[PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM
1
From: Alexandre Ghiti <alexghiti@rivosinc.com>
1
2
3
Currently, the initrd is placed at 128MB, which overlaps with the kernel
4
when it is large (for example syzbot kernels are). From the kernel side,
5
there is no reason we could not push the initrd further away in memory
6
to accommodate large kernels, so move the initrd at 512MB when possible.
7
8
The ideal solution would have been to place the initrd based on the
9
kernel size but we actually can't since the bss size is not known when
10
the image is loaded by load_image_targphys_as() and the initrd would
11
then overlap with this section.
12
13
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
16
Message-ID: <20240206154042.514698-1-alexghiti@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
hw/riscv/boot.c | 12 ++++++------
20
1 file changed, 6 insertions(+), 6 deletions(-)
21
22
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/riscv/boot.c
25
+++ b/hw/riscv/boot.c
26
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
27
* kernel is uncompressed it will not clobber the initrd. However
28
* on boards without much RAM we must ensure that we still leave
29
* enough room for a decent sized initrd, and on boards with large
30
- * amounts of RAM we must avoid the initrd being so far up in RAM
31
- * that it is outside lowmem and inaccessible to the kernel.
32
- * So for boards with less than 256MB of RAM we put the initrd
33
- * halfway into RAM, and for boards with 256MB of RAM or more we put
34
- * the initrd at 128MB.
35
+ * amounts of RAM, we put the initrd at 512MB to allow large kernels
36
+ * to boot.
37
+ * So for boards with less than 1GB of RAM we put the initrd
38
+ * halfway into RAM, and for boards with 1GB of RAM or more we put
39
+ * the initrd at 512MB.
40
*/
41
- start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
42
+ start = kernel_entry + MIN(mem_size / 2, 512 * MiB);
43
44
size = load_ramdisk(filename, start, mem_size - start);
45
if (size == -1) {
46
--
47
2.44.0
diff view generated by jsdifflib
New patch
[PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
1
2
3
Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
4
This patch introduces this for QEMU's user space emulator.
5
6
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <20240207115926.887816-2-christoph.muellner@vrull.eu>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
linux-user/syscall.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/syscall.c
17
+++ b/linux-user/syscall.c
18
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
19
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
20
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
21
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
22
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
23
24
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
25
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
26
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
27
RISCV_HWPROBE_EXT_ZBB : 0;
28
value |= cfg->ext_zbs ?
29
RISCV_HWPROBE_EXT_ZBS : 0;
30
+ value |= cfg->ext_zicboz ?
31
+ RISCV_HWPROBE_EXT_ZICBOZ : 0;
32
__put_user(value, &pair->value);
33
break;
34
case RISCV_HWPROBE_KEY_CPUPERF_0:
35
--
36
2.44.0
37
38
diff view generated by jsdifflib
New patch
[PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
1
2
3
Upstream Linux recently added many additional keys to the hwprobe API.
4
This patch adds support for all of them with the exception of Ztso,
5
which is currently not supported in QEMU.
6
7
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-ID: <20240207115926.887816-3-christoph.muellner@vrull.eu>
10
[ Changes by AF:
11
- Fixup whitespace
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
linux-user/syscall.c | 100 +++++++++++++++++++++++++++++++++++++++----
16
1 file changed, 92 insertions(+), 8 deletions(-)
17
18
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/linux-user/syscall.c
21
+++ b/linux-user/syscall.c
22
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
23
#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
24
#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
25
26
-#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
27
-#define RISCV_HWPROBE_IMA_FD (1 << 0)
28
-#define RISCV_HWPROBE_IMA_C (1 << 1)
29
-#define RISCV_HWPROBE_IMA_V (1 << 2)
30
-#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
31
-#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
32
-#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
33
-#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
34
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
35
+#define RISCV_HWPROBE_IMA_FD (1 << 0)
36
+#define RISCV_HWPROBE_IMA_C (1 << 1)
37
+#define RISCV_HWPROBE_IMA_V (1 << 2)
38
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
39
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
40
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
41
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
42
+#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
43
+#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
44
+#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
45
+#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
46
+#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
47
+#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
48
+#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
49
+#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
50
+#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
51
+#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
52
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
53
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
54
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
55
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
56
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
57
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
58
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
59
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
60
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
61
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
62
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
63
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
64
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
65
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
66
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
67
+#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
68
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
69
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
70
71
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
72
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
73
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
74
RISCV_HWPROBE_EXT_ZBS : 0;
75
value |= cfg->ext_zicboz ?
76
RISCV_HWPROBE_EXT_ZICBOZ : 0;
77
+ value |= cfg->ext_zbc ?
78
+ RISCV_HWPROBE_EXT_ZBC : 0;
79
+ value |= cfg->ext_zbkb ?
80
+ RISCV_HWPROBE_EXT_ZBKB : 0;
81
+ value |= cfg->ext_zbkc ?
82
+ RISCV_HWPROBE_EXT_ZBKC : 0;
83
+ value |= cfg->ext_zbkx ?
84
+ RISCV_HWPROBE_EXT_ZBKX : 0;
85
+ value |= cfg->ext_zknd ?
86
+ RISCV_HWPROBE_EXT_ZKND : 0;
87
+ value |= cfg->ext_zkne ?
88
+ RISCV_HWPROBE_EXT_ZKNE : 0;
89
+ value |= cfg->ext_zknh ?
90
+ RISCV_HWPROBE_EXT_ZKNH : 0;
91
+ value |= cfg->ext_zksed ?
92
+ RISCV_HWPROBE_EXT_ZKSED : 0;
93
+ value |= cfg->ext_zksh ?
94
+ RISCV_HWPROBE_EXT_ZKSH : 0;
95
+ value |= cfg->ext_zkt ?
96
+ RISCV_HWPROBE_EXT_ZKT : 0;
97
+ value |= cfg->ext_zvbb ?
98
+ RISCV_HWPROBE_EXT_ZVBB : 0;
99
+ value |= cfg->ext_zvbc ?
100
+ RISCV_HWPROBE_EXT_ZVBC : 0;
101
+ value |= cfg->ext_zvkb ?
102
+ RISCV_HWPROBE_EXT_ZVKB : 0;
103
+ value |= cfg->ext_zvkg ?
104
+ RISCV_HWPROBE_EXT_ZVKG : 0;
105
+ value |= cfg->ext_zvkned ?
106
+ RISCV_HWPROBE_EXT_ZVKNED : 0;
107
+ value |= cfg->ext_zvknha ?
108
+ RISCV_HWPROBE_EXT_ZVKNHA : 0;
109
+ value |= cfg->ext_zvknhb ?
110
+ RISCV_HWPROBE_EXT_ZVKNHB : 0;
111
+ value |= cfg->ext_zvksed ?
112
+ RISCV_HWPROBE_EXT_ZVKSED : 0;
113
+ value |= cfg->ext_zvksh ?
114
+ RISCV_HWPROBE_EXT_ZVKSH : 0;
115
+ value |= cfg->ext_zvkt ?
116
+ RISCV_HWPROBE_EXT_ZVKT : 0;
117
+ value |= cfg->ext_zfh ?
118
+ RISCV_HWPROBE_EXT_ZFH : 0;
119
+ value |= cfg->ext_zfhmin ?
120
+ RISCV_HWPROBE_EXT_ZFHMIN : 0;
121
+ value |= cfg->ext_zihintntl ?
122
+ RISCV_HWPROBE_EXT_ZIHINTNTL : 0;
123
+ value |= cfg->ext_zvfh ?
124
+ RISCV_HWPROBE_EXT_ZVFH : 0;
125
+ value |= cfg->ext_zvfhmin ?
126
+ RISCV_HWPROBE_EXT_ZVFHMIN : 0;
127
+ value |= cfg->ext_zfa ?
128
+ RISCV_HWPROBE_EXT_ZFA : 0;
129
+ value |= cfg->ext_zacas ?
130
+ RISCV_HWPROBE_EXT_ZACAS : 0;
131
+ value |= cfg->ext_zicond ?
132
+ RISCV_HWPROBE_EXT_ZICOND : 0;
133
__put_user(value, &pair->value);
134
break;
135
case RISCV_HWPROBE_KEY_CPUPERF_0:
136
--
137
2.44.0
138
139
diff view generated by jsdifflib
New patch
[PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Recent changes in options handling removed the 'mmu' default the bare
4
CPUs had, meaning that we must enable 'mmu' by hand when using the
5
rva22s64 profile CPU.
6
7
Given that this profile is setting a satp mode, it already implies that
8
we need a 'mmu'. Enable the 'mmu' in this case.
9
10
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/tcg/tcg-cpu.c | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/tcg/tcg-cpu.c
21
+++ b/target/riscv/tcg/tcg-cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
23
24
#ifndef CONFIG_USER_ONLY
25
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
26
+ object_property_set_bool(obj, "mmu", true, NULL);
27
const char *satp_prop = satp_mode_str(profile->satp_mode,
28
riscv_cpu_is_32bit(cpu));
29
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
30
--
31
2.44.0
diff view generated by jsdifflib
New patch
[PULL 08/34] target/riscv: add riscv,isa to named features
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Further discussions after the introduction of rva22 support in QEMU
4
revealed that what we've been calling 'named features' are actually
5
regular extensions, with their respective riscv,isa DTs. This is
6
clarified in [1]. [2] is a bug tracker asking for the profile spec to be
7
less cryptic about it.
8
9
As far as QEMU goes we understand extensions as something that the user
10
can enable/disable in the command line. This isn't the case for named
11
features, so we'll have to reach a middle ground.
12
13
We'll keep our existing nomenclature 'named features' to refer to any
14
extension that the user can't control in the command line. We'll also do
15
the following:
16
17
- 'svade' and 'zic64b' flags are renamed to 'ext_svade' and
18
'ext_zic64b'. 'ext_svade' and 'ext_zic64b' now have riscv,isa strings and
19
priv_spec versions;
20
21
- skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that
22
named features have a riscv,isa and an entry in isa_edata_arr[] we
23
don't need to gate the call to cpu_cfg_ext_get_min_version() anymore.
24
25
[1] https://github.com/riscv/riscv-profiles/issues/121
26
[2] https://github.com/riscv/riscv-profiles/issues/142
27
28
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20240215223955.969568-3-dbarboza@ventanamicro.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
---
34
target/riscv/cpu_cfg.h | 6 ++++--
35
target/riscv/cpu.c | 17 +++++++++++++----
36
target/riscv/tcg/tcg-cpu.c | 16 ++++++----------
37
3 files changed, 23 insertions(+), 16 deletions(-)
38
39
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu_cfg.h
42
+++ b/target/riscv/cpu_cfg.h
43
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
44
bool ext_smepmp;
45
bool rvv_ta_all_1s;
46
bool rvv_ma_all_1s;
47
- bool svade;
48
- bool zic64b;
49
50
uint32_t mvendorid;
51
uint64_t marchid;
52
uint64_t mimpid;
53
54
+ /* Named features */
55
+ bool ext_svade;
56
+ bool ext_zic64b;
57
+
58
/* Vendor-specific custom extensions */
59
bool ext_xtheadba;
60
bool ext_xtheadbb;
61
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/cpu.c
64
+++ b/target/riscv/cpu.c
65
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_option_set(const char *optname)
66
* instead.
67
*/
68
const RISCVIsaExtData isa_edata_arr[] = {
69
+ ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b),
70
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
71
ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
72
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
73
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
74
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
75
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
76
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
77
+ ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
78
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
79
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
80
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
81
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
82
DEFINE_PROP_END_OF_LIST(),
83
};
84
85
+/*
86
+ * 'Named features' is the name we give to extensions that we
87
+ * don't want to expose to users. They are either immutable
88
+ * (always enabled/disable) or they'll vary depending on
89
+ * the resulting CPU state. They have riscv,isa strings
90
+ * and priv_ver like regular extensions.
91
+ */
92
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
93
- MULTI_EXT_CFG_BOOL("svade", svade, true),
94
- MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
95
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
96
+ MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
97
98
DEFINE_PROP_END_OF_LIST(),
99
};
100
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22U64 = {
101
CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
102
103
/* mandatory named features for this profile */
104
- CPU_CFG_OFFSET(zic64b),
105
+ CPU_CFG_OFFSET(ext_zic64b),
106
107
RISCV_PROFILE_EXT_LIST_END
108
}
109
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22S64 = {
110
CPU_CFG_OFFSET(ext_svinval),
111
112
/* rva22s64 named features */
113
- CPU_CFG_OFFSET(svade),
114
+ CPU_CFG_OFFSET(ext_svade),
115
116
RISCV_PROFILE_EXT_LIST_END
117
}
118
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/tcg/tcg-cpu.c
121
+++ b/target/riscv/tcg/tcg-cpu.c
122
@@ -XXX,XX +XXX,XX @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
123
static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
124
{
125
switch (feat_offset) {
126
- case CPU_CFG_OFFSET(zic64b):
127
+ case CPU_CFG_OFFSET(ext_zic64b):
128
cpu->cfg.cbom_blocksize = 64;
129
cpu->cfg.cbop_blocksize = 64;
130
cpu->cfg.cboz_blocksize = 64;
131
break;
132
- case CPU_CFG_OFFSET(svade):
133
+ case CPU_CFG_OFFSET(ext_svade):
134
cpu->cfg.ext_svadu = false;
135
break;
136
default:
137
@@ -XXX,XX +XXX,XX @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
138
return;
139
}
140
141
- if (cpu_cfg_offset_is_named_feat(ext_offset)) {
142
- return;
143
- }
144
-
145
ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset);
146
147
if (env->priv_ver < ext_priv_ver) {
148
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
149
150
static void riscv_cpu_update_named_features(RISCVCPU *cpu)
151
{
152
- cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
153
- cpu->cfg.cbop_blocksize == 64 &&
154
- cpu->cfg.cboz_blocksize == 64;
155
+ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
156
+ cpu->cfg.cbop_blocksize == 64 &&
157
+ cpu->cfg.cboz_blocksize == 64;
158
159
- cpu->cfg.svade = !cpu->cfg.ext_svadu;
160
+ cpu->cfg.ext_svade = !cpu->cfg.ext_svadu;
161
}
162
163
static void riscv_cpu_validate_g(RISCVCPU *cpu)
164
--
165
2.44.0
diff view generated by jsdifflib
New patch
[PULL 09/34] target/riscv: add remaining named features
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
4
until now, we were implying that they were available.
5
6
We can't do this anymore since named features also has a riscv,isa
7
entry. Let's add them to riscv_cpu_named_features[].
8
9
Instead of adding one bool for each named feature that we'll always
10
implement, i.e. can't be turned off, add a 'ext_always_enabled' bool in
11
cpu->cfg. This bool will be set to 'true' in TCG accel init, and all
12
named features will point to it. This also means that KVM won't see
13
these features as always enable, which is our intention.
14
15
If any accelerator adds support to disable one of these features, we'll
16
have to promote them to regular extensions and allow users to disable it
17
via command line.
18
19
After this patch, here's the riscv,isa from a buildroot using the
20
'rva22s64' CPU:
21
22
# cat /proc/device-tree/cpus/cpu@0/riscv,isa
23
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
24
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
25
zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
26
27
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
28
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
29
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
30
Message-ID: <20240215223955.969568-4-dbarboza@ventanamicro.com>
31
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
32
---
33
target/riscv/cpu_cfg.h | 6 ++++++
34
target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++-------
35
target/riscv/tcg/tcg-cpu.c | 2 ++
36
3 files changed, 43 insertions(+), 7 deletions(-)
37
38
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_cfg.h
41
+++ b/target/riscv/cpu_cfg.h
42
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
43
bool ext_svade;
44
bool ext_zic64b;
45
46
+ /*
47
+ * Always 'true' boolean for named features
48
+ * TCG always implement/can't be disabled.
49
+ */
50
+ bool ext_always_enabled;
51
+
52
/* Vendor-specific custom extensions */
53
bool ext_xtheadba;
54
bool ext_xtheadbb;
55
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/cpu.c
58
+++ b/target/riscv/cpu.c
59
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
60
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
61
ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
62
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
63
+ ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, ext_always_enabled),
64
+ ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, ext_always_enabled),
65
+ ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_always_enabled),
66
+ ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_always_enabled),
67
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
68
ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
69
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
70
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
71
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
72
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
73
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
74
+ ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, ext_always_enabled),
75
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
76
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
77
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
78
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
79
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
80
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
81
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
82
+ ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, ext_always_enabled),
83
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
84
+ ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, ext_always_enabled),
85
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
86
+ ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, ext_always_enabled),
87
+ ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, ext_always_enabled),
88
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
89
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
90
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
91
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
92
DEFINE_PROP_END_OF_LIST(),
93
};
94
95
+#define ALWAYS_ENABLED_FEATURE(_name) \
96
+ {.name = _name, \
97
+ .offset = CPU_CFG_OFFSET(ext_always_enabled), \
98
+ .enabled = true}
99
+
100
/*
101
* 'Named features' is the name we give to extensions that we
102
* don't want to expose to users. They are either immutable
103
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
104
MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
105
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
106
107
+ /*
108
+ * cache-related extensions that are always enabled
109
+ * in TCG since QEMU RISC-V does not have a cache
110
+ * model.
111
+ */
112
+ ALWAYS_ENABLED_FEATURE("za64rs"),
113
+ ALWAYS_ENABLED_FEATURE("ziccif"),
114
+ ALWAYS_ENABLED_FEATURE("ziccrse"),
115
+ ALWAYS_ENABLED_FEATURE("ziccamoa"),
116
+ ALWAYS_ENABLED_FEATURE("zicclsm"),
117
+ ALWAYS_ENABLED_FEATURE("ssccptr"),
118
+
119
+ /* Other named features that TCG always implements */
120
+ ALWAYS_ENABLED_FEATURE("sstvecd"),
121
+ ALWAYS_ENABLED_FEATURE("sstvala"),
122
+ ALWAYS_ENABLED_FEATURE("sscounterenw"),
123
+
124
DEFINE_PROP_END_OF_LIST(),
125
};
126
127
@@ -XXX,XX +XXX,XX @@ static const PropertyInfo prop_marchid = {
128
};
129
130
/*
131
- * RVA22U64 defines some 'named features' or 'synthetic extensions'
132
- * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
133
- * and Zicclsm. We do not implement caching in QEMU so we'll consider
134
- * all these named features as always enabled.
135
- *
136
- * There's no riscv,isa update for them (nor for zic64b, despite it
137
- * having a cfg offset) at this moment.
138
+ * RVA22U64 defines some 'named features' that are cache
139
+ * related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
140
+ * and Zicclsm. They are always implemented in TCG and
141
+ * doesn't need to be manually enabled by the profile.
142
*/
143
static RISCVCPUProfile RVA22U64 = {
144
.parent = NULL,
145
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/target/riscv/tcg/tcg-cpu.c
148
+++ b/target/riscv/tcg/tcg-cpu.c
149
@@ -XXX,XX +XXX,XX @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
150
RISCVCPU *cpu = RISCV_CPU(cs);
151
Object *obj = OBJECT(cpu);
152
153
+ cpu->cfg.ext_always_enabled = true;
154
+
155
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
156
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
157
riscv_cpu_add_user_properties(obj);
158
--
159
2.44.0
diff view generated by jsdifflib
New patch
[PULL 10/34] target/riscv: Reset henvcfg to zero
1
From: Andrew Jones <ajones@ventanamicro.com>
1
2
3
The hypervisor should decide what it wants to enable. Zero all
4
configuration enable bits on reset.
5
6
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
7
svadu extension") missed one reference to 'hade'. Change it now.
8
9
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
10
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.c | 3 +--
18
target/riscv/csr.c | 2 +-
19
2 files changed, 2 insertions(+), 3 deletions(-)
20
21
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.c
24
+++ b/target/riscv/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
26
27
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
28
(cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
29
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
30
- (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
31
+ env->henvcfg = 0;
32
33
/* Initialized default priorities of local interrupts. */
34
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
38
+++ b/target/riscv/csr.c
39
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
40
/*
41
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
42
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
43
- * henvcfg.hade is read_only 0 when menvcfg.hade = 0
44
+ * henvcfg.adue is read_only 0 when menvcfg.adue = 0
45
*/
46
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
47
env->menvcfg);
48
--
49
2.44.0
diff view generated by jsdifflib
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
[PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
3
Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only
4
short of its purpose, as all it checks is whether two-stage address
4
enable menvcfg.ADUE on reset if svade has not been selected. Now
5
translation either via the hypervisor-load store instructions or the
5
that we also consider svade, we have four possible configurations:
6
MPRV feature would be allowed.
7
6
8
What we really need instead is whether two-stage address translation was
7
1) !svade && !svadu
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
8
use hardware updating and there's no way to disable it
10
we do not have the information to reliably detect this. Therefore, when
9
(the default, which maintains past behavior. Maintaining
11
we raise a memory fault exception we have to record whether two-stage
10
the default, even with !svadu is a change that fixes [1])
12
address translation is active.
13
11
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
12
2) !svade && svadu
13
use hardware updating, but also provide {m,h}envcfg.ADUE,
14
allowing software to switch to exception mode
15
(being able to switch is a change which fixes [1])
16
17
3) svade && !svadu
18
use exception mode and there's no way to switch to hardware
19
updating
20
(this behavior change fixes [2])
21
22
4) svade && svadu
23
use exception mode, but also provide {m,h}envcfg.ADUE,
24
allowing software to switch to hardware updating
25
(this behavior change fixes [2])
26
27
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation") [1]
28
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
29
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
32
Message-ID: <20240215223955.969568-6-dbarboza@ventanamicro.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
34
---
19
target/riscv/cpu.h | 4 ++++
35
target/riscv/cpu.c | 3 ++-
20
target/riscv/cpu.c | 1 +
36
target/riscv/cpu_helper.c | 19 +++++++++++++++----
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
37
target/riscv/tcg/tcg-cpu.c | 15 +++++----------
22
3 files changed, 13 insertions(+), 13 deletions(-)
38
3 files changed, 22 insertions(+), 15 deletions(-)
23
39
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
29
target_ulong satp_hs;
30
uint64_t mstatus_hs;
31
32
+ /* Signals whether the current exception occurred with two-stage address
33
+ translation active. */
34
+ bool two_stage_lookup;
35
+
36
target_ulong scounteren;
37
target_ulong mcounteren;
38
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu.c
42
--- a/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
43
+++ b/target/riscv/cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
44
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
45
env->two_stage_lookup = false;
45
env->mcause = 0;
46
46
env->pc = env->resetvec;
47
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
47
+ env->two_stage_lookup = false;
48
- (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
48
#endif
49
+ (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ?
49
cs->exception_index = EXCP_NONE;
50
+ MENVCFG_ADUE : 0);
50
env->load_res = -1;
51
env->henvcfg = 0;
52
53
/* Initialized default priorities of local interrupts. */
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
52
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
56
--- a/target/riscv/cpu_helper.c
54
+++ b/target/riscv/cpu_helper.c
57
+++ b/target/riscv/cpu_helper.c
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
58
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
56
g_assert_not_reached();
57
}
59
}
58
env->badaddr = address;
60
59
+ env->two_stage_lookup = two_stage;
61
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
62
- bool adue = env->menvcfg & MENVCFG_ADUE;
63
+ bool svade = riscv_cpu_cfg(env)->ext_svade;
64
+ bool svadu = riscv_cpu_cfg(env)->ext_svadu;
65
+ bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
66
67
if (first_stage && two_stage && env->virt_enabled) {
68
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
69
@@ -XXX,XX +XXX,XX @@ restart:
70
return TRANSLATE_FAIL;
71
}
72
73
- /* If necessary, set accessed and dirty bits. */
74
- target_ulong updated_pte = pte | PTE_A |
75
- (access_type == MMU_DATA_STORE ? PTE_D : 0);
76
+ target_ulong updated_pte = pte;
77
+
78
+ /*
79
+ * If ADUE is enabled, set accessed and dirty bits.
80
+ * Otherwise raise an exception if necessary.
81
+ */
82
+ if (adue) {
83
+ updated_pte |= PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0);
84
+ } else if (!(pte & PTE_A) ||
85
+ (access_type == MMU_DATA_STORE && !(pte & PTE_D))) {
86
+ return TRANSLATE_FAIL;
87
+ }
88
89
/* Page table updates need to be atomic with MTTCG enabled */
90
if (updated_pte != pte && !is_debug) {
91
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/riscv/tcg/tcg-cpu.c
94
+++ b/target/riscv/tcg/tcg-cpu.c
95
@@ -XXX,XX +XXX,XX @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
96
97
static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
98
{
99
- switch (feat_offset) {
100
- case CPU_CFG_OFFSET(ext_zic64b):
101
+ /*
102
+ * All other named features are already enabled
103
+ * in riscv_tcg_cpu_instance_init().
104
+ */
105
+ if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
106
cpu->cfg.cbom_blocksize = 64;
107
cpu->cfg.cbop_blocksize = 64;
108
cpu->cfg.cboz_blocksize = 64;
109
- break;
110
- case CPU_CFG_OFFSET(ext_svade):
111
- cpu->cfg.ext_svadu = false;
112
- break;
113
- default:
114
- g_assert_not_reached();
115
}
60
}
116
}
61
117
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
118
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
119
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
64
}
120
cpu->cfg.cbop_blocksize == 64 &&
65
121
cpu->cfg.cboz_blocksize == 64;
66
env->badaddr = addr;
122
-
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
123
- cpu->cfg.ext_svade = !cpu->cfg.ext_svadu;
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
70
}
124
}
71
125
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
126
static void riscv_cpu_validate_g(RISCVCPU *cpu)
73
g_assert_not_reached();
74
}
75
env->badaddr = addr;
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
78
riscv_raise_exception(env, cs->exception_index, retaddr);
79
}
80
#endif /* !CONFIG_USER_ONLY */
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
82
/* handle the trap in S-mode */
83
if (riscv_has_ext(env, RVH)) {
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
85
- bool two_stage_lookup = false;
86
87
- if (env->priv == PRV_M ||
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
90
- get_field(env->hstatus, HSTATUS_HU))) {
91
- two_stage_lookup = true;
92
- }
93
-
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
95
+ if (env->two_stage_lookup && write_tval) {
96
/*
97
* If we are writing a guest virtual address to stval, set
98
* this to 1. If we are trapping to VS we will set this to 0
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
100
riscv_cpu_set_force_hs_excep(env, 0);
101
} else {
102
/* Trap into HS mode */
103
- if (!two_stage_lookup) {
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
105
- riscv_cpu_virt_enabled(env));
106
- }
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
108
htval = env->guest_phys_fault_addr;
109
}
110
}
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
112
* RISC-V ISA Specification.
113
*/
114
115
+ env->two_stage_lookup = false;
116
#endif
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
118
}
119
--
127
--
120
2.30.1
128
2.44.0
121
122
diff view generated by jsdifflib
New patch
[PULL 12/34] target/riscv: Promote svade to a normal extension
1
From: Andrew Jones <ajones@ventanamicro.com>
1
2
3
Named features are extensions which don't make sense for users to
4
control and are therefore not exposed on the command line. However,
5
svade is an extension which makes sense for users to control, so treat
6
it like a "normal" extension. The default is false, even for the max
7
cpu type, since QEMU has always implemented hardware A/D PTE bit
8
updating, so users must opt into svade (or get it from a CPU type
9
which enables it by default).
10
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20240215223955.969568-7-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.c | 9 ++-------
18
target/riscv/tcg/tcg-cpu.c | 6 ++++++
19
2 files changed, 8 insertions(+), 7 deletions(-)
20
21
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.c
24
+++ b/target/riscv/cpu.c
25
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
26
27
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
28
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
29
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
30
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
31
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
32
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
33
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
34
* and priv_ver like regular extensions.
35
*/
36
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
37
- MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
38
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
39
40
/*
41
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22U64 = {
42
* Other named features that we already implement: Sstvecd, Sstvala,
43
* Sscounterenw
44
*
45
- * Named features that we need to enable: svade
46
- *
47
* The remaining features/extensions comes from RVA22U64.
48
*/
49
static RISCVCPUProfile RVA22S64 = {
50
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22S64 = {
51
.ext_offsets = {
52
/* rva22s64 exts */
53
CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
54
- CPU_CFG_OFFSET(ext_svinval),
55
-
56
- /* rva22s64 named features */
57
- CPU_CFG_OFFSET(ext_svade),
58
+ CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
59
60
RISCV_PROFILE_EXT_LIST_END
61
}
62
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/riscv/tcg/tcg-cpu.c
65
+++ b/target/riscv/tcg/tcg-cpu.c
66
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
67
isa_ext_update_enabled(cpu, prop->offset, true);
68
}
69
70
+ /*
71
+ * Some extensions can't be added without backward compatibilty concerns.
72
+ * Disable those, the user can still opt in to them on the command line.
73
+ */
74
+ cpu->cfg.ext_svade = false;
75
+
76
/* set vector version */
77
env->vext_ver = VEXT_VERSION_1_00_0;
78
79
--
80
2.44.0
diff view generated by jsdifflib
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
[PULL 13/34] target/riscv: FIX xATP_MODE validation
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
2
2
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
3
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined
4
for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal
5
value whenever read (See riscv-privileged-20211203, SATP CSR).
6
7
For example on rv64 we are trying to write to SATP CSR val = 0x1000000000000000 (SATP_MODE = 1 - Reserved for standard use)
8
and after that we are trying to read SATP_CSR. We read from the SATP CSR value = 0x1000000000000000, which is not a correct
9
operation (return illegal value).
10
11
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
14
Message-ID: <20240109145923.37893-1-irina.ryapolova@syntacore.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
16
---
8
target/riscv/csr.c | 7 ++++---
17
target/riscv/csr.c | 4 ++--
9
1 file changed, 4 insertions(+), 3 deletions(-)
18
1 file changed, 2 insertions(+), 2 deletions(-)
10
19
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/csr.c
22
--- a/target/riscv/csr.c
14
+++ b/target/riscv/csr.c
23
+++ b/target/riscv/csr.c
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
24
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
25
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
26
static bool validate_vm(CPURISCVState *env, target_ulong vm)
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
23
24
static const char valid_vm_1_10_32[16] = {
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
26
target_ulong new_value, target_ulong write_mask)
27
{
27
{
28
int ret = rmw_mip(env, 0, ret_value, new_value,
28
- return (vm & 0xf) <=
29
- write_mask & hip_writable_mask);
29
- satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
30
+ write_mask & hvip_writable_mask);
30
+ uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
31
31
+ return get_field(mode_supported, (1 << vm));
32
- *ret_value &= hip_writable_mask;
33
+ *ret_value &= hvip_writable_mask;
34
35
return ret;
36
}
32
}
33
34
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
37
--
35
--
38
2.30.1
36
2.44.0
39
40
diff view generated by jsdifflib
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
[PULL 14/34] target/riscv: UPDATE xATP write CSR
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
2
2
3
The previous implementation was broken in many ways:
3
Added xATP_MODE validation for vsatp/hgatp CSRs.
4
- Used mideleg instead of hideleg to mask accesses
4
The xATP register is an SXLEN-bit read/write WARL register, so
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
5
the legal value must be returned (See riscv-privileged-20211203, SATP/VSATP/HGATP CSRs).
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
7
6
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
10
Message-ID: <20240109145923.37893-2-irina.ryapolova@syntacore.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
13
target/riscv/csr.c | 52 ++++++++++++++++++++++++++--------------------
14
1 file changed, 34 insertions(+), 34 deletions(-)
14
1 file changed, 29 insertions(+), 23 deletions(-)
15
15
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
18
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
20
@@ -XXX,XX +XXX,XX @@ static bool validate_vm(CPURISCVState *env, target_ulong vm)
21
return write_mstatus(env, CSR_MSTATUS, newval);
21
return get_field(mode_supported, (1 << vm));
22
}
22
}
23
23
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
24
+static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
25
+ target_ulong val)
25
+{
26
+{
26
+ /* Shift the VS bits to their S bit location in vsie */
27
+ target_ulong mask;
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
28
+ bool vm;
28
+ return 0;
29
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
30
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
31
+ mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
32
+ } else {
33
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
34
+ mask = (val ^ old_xatp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
35
+ }
36
+
37
+ if (vm && mask) {
38
+ /*
39
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
40
+ * pass these through QEMU's TLB emulation as it improves
41
+ * performance. Flushing the TLB on SATP writes with paging
42
+ * enabled avoids leaking those invalid cached mappings.
43
+ */
44
+ tlb_flush(env_cpu(env));
45
+ return val;
46
+ }
47
+ return old_xatp;
29
+}
48
+}
30
+
49
+
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
50
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
51
target_ulong val)
32
{
52
{
33
if (riscv_cpu_virt_enabled(env)) {
53
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
54
static RISCVException write_satp(CPURISCVState *env, int csrno,
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
55
target_ulong val)
36
+ read_vsie(env, CSR_VSIE, val);
56
{
37
} else {
57
- target_ulong mask;
38
*val = env->mie & env->mideleg;
58
- bool vm;
59
-
60
if (!riscv_cpu_cfg(env)->mmu) {
61
return RISCV_EXCP_NONE;
39
}
62
}
40
return 0;
63
64
- if (riscv_cpu_mxl(env) == MXL_RV32) {
65
- vm = validate_vm(env, get_field(val, SATP32_MODE));
66
- mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
67
- } else {
68
- vm = validate_vm(env, get_field(val, SATP64_MODE));
69
- mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
70
- }
71
-
72
- if (vm && mask) {
73
- /*
74
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
75
- * pass these through QEMU's TLB emulation as it improves
76
- * performance. Flushing the TLB on SATP writes with paging
77
- * enabled avoids leaking those invalid cached mappings.
78
- */
79
- tlb_flush(env_cpu(env));
80
- env->satp = val;
81
- }
82
+ env->satp = legalize_xatp(env, env->satp, val);
83
return RISCV_EXCP_NONE;
41
}
84
}
42
85
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
86
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hgatp(CPURISCVState *env, int csrno,
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
87
static RISCVException write_hgatp(CPURISCVState *env, int csrno,
88
target_ulong val)
45
{
89
{
46
- target_ulong newval;
90
- env->hgatp = val;
47
+ /* Shift the S bits to their VS bit location in mie */
91
+ env->hgatp = legalize_xatp(env, env->hgatp, val);
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
92
return RISCV_EXCP_NONE;
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
50
+ return write_mie(env, CSR_MIE, newval);
51
+}
52
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
54
+{
55
if (riscv_cpu_virt_enabled(env)) {
56
- /* Shift the guests S bits to VS */
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
58
- ((val << 1) & VS_MODE_INTERRUPTS);
59
+ write_vsie(env, CSR_VSIE, val);
60
} else {
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
63
+ (val & S_MODE_INTERRUPTS);
64
+ write_mie(env, CSR_MIE, newval);
65
}
66
67
- return write_mie(env, CSR_MIE, newval);
68
+ return 0;
69
}
93
}
70
94
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
95
@@ -XXX,XX +XXX,XX @@ static RISCVException read_vsatp(CPURISCVState *env, int csrno,
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
96
static RISCVException write_vsatp(CPURISCVState *env, int csrno,
73
return 0;
97
target_ulong val)
98
{
99
- env->vsatp = val;
100
+ env->vsatp = legalize_xatp(env, env->vsatp, val);
101
return RISCV_EXCP_NONE;
74
}
102
}
75
103
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
77
+ target_ulong new_value, target_ulong write_mask)
78
+{
79
+ /* Shift the S bits to their VS bit location in mip */
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
86
+}
87
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
89
target_ulong new_value, target_ulong write_mask)
90
{
91
int ret;
92
93
if (riscv_cpu_virt_enabled(env)) {
94
- /* Shift the new values to line up with the VS bits */
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
97
- ret &= vsip_writable_mask;
98
- ret >>= 1;
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
100
} else {
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
102
write_mask & env->mideleg & sip_writable_mask);
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
104
return 0;
105
}
106
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
108
- target_ulong new_value, target_ulong write_mask)
109
-{
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
111
- write_mask & env->mideleg & vsip_writable_mask);
112
- return ret;
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
129
*val = env->vstvec;
130
--
104
--
131
2.30.1
105
2.44.0
132
133
diff view generated by jsdifflib
[PULL 01/16] target/riscv: fix vs() to return proper error code
[PULL 15/34] target/riscv: Add missing include guard in pmu.h
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
3
Add missing include guard in pmu.h to avoid the problem of double
4
is not enabled.
4
inclusion.
5
6
If -1 is returned, exception will be raised and cs->exception_index will
7
be set to the negative return value. The exception will then be treated
8
as an instruction access fault instead of illegal instruction fault.
9
5
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Atish Patra <atishp@rivosinc.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
11
Message-ID: <20240220110907.10479-1-frank.chang@sifive.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
13
---
16
target/riscv/csr.c | 2 +-
14
target/riscv/pmu.h | 5 +++++
17
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 5 insertions(+)
18
16
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
19
--- a/target/riscv/pmu.h
22
+++ b/target/riscv/csr.c
20
+++ b/target/riscv/pmu.h
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
21
@@ -XXX,XX +XXX,XX @@
24
if (env->misa & RVV) {
22
* this program. If not, see <http://www.gnu.org/licenses/>.
25
return 0;
23
*/
26
}
24
27
- return -1;
25
+#ifndef RISCV_PMU_H
28
+ return -RISCV_EXCP_ILLEGAL_INST;
26
+#define RISCV_PMU_H
29
}
27
+
30
28
#include "cpu.h"
31
static int ctr(CPURISCVState *env, int csrno)
29
#include "qapi/error.h"
30
31
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
32
void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
33
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
34
uint32_t ctr_idx);
35
+
36
+#endif /* RISCV_PMU_H */
32
--
37
--
33
2.30.1
38
2.44.0
34
39
35
40
diff view generated by jsdifflib
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
[PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
1
From: Jim Shu <cwshu@andestech.com>
1
From: Haibo Xu <haibo1.xu@intel.com>
2
2
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
3
Enable ACPI NUMA support by adding the following 2 ACPI tables:
4
Fix it by propagating PMP permission to TLB page permission.
4
SRAT: provides the association for memory/Harts and Proximity Domains
5
SLIT: provides the relative distance between Proximity Domains
5
6
6
PMP permission checking also use MMU-style API to change TLB permission
7
The SRAT RINTC Affinity Structure definition[1] was based on the recently
7
and size.
8
approved ACPI CodeFirst ECR[2].
8
9
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
10
[1] https://github.com/riscv-non-isa/riscv-acpi/issues/25
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
[2] https://mantis.uefi.org/mantis/view.php?id=2433
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
12
13
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
14
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
15
Message-ID: <20240129094200.3581037-1-haibo1.xu@intel.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
17
---
14
target/riscv/pmp.h | 4 +-
18
hw/riscv/virt-acpi-build.c | 60 ++++++++++++++++++++++++++++++++++++++
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
19
1 file changed, 60 insertions(+)
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
17
3 files changed, 125 insertions(+), 43 deletions(-)
18
20
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
21
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
20
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/pmp.h
23
--- a/hw/riscv/virt-acpi-build.c
22
+++ b/target/riscv/pmp.h
24
+++ b/hw/riscv/virt-acpi-build.c
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
25
@@ -XXX,XX +XXX,XX @@ static void build_madt(GArray *table_data,
24
target_ulong val);
26
acpi_table_end(linker, &table);
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
29
+ target_ulong mode);
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
31
target_ulong *tlb_size);
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
33
void pmp_update_rule_nums(CPURISCVState *env);
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
36
37
#endif
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
43
env->load_res = -1;
44
}
27
}
45
28
46
+/*
29
+/*
47
+ * get_physical_address_pmp - check PMP permission for this physical address
30
+ * ACPI spec, Revision 6.5+
48
+ *
31
+ * 5.2.16 System Resource Affinity Table (SRAT)
49
+ * Match the PMP region and check permission for this physical address and it's
32
+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
50
+ * TLB page. Returns 0 if the permission checking was successful
33
+ * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
51
+ *
52
+ * @env: CPURISCVState
53
+ * @prot: The returned protection attributes
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
55
+ * permission checking. NULL if not set TLB page for addr.
56
+ * @addr: The physical address to be checked permission
57
+ * @access_type: The type of MMU access
58
+ * @mode: Indicates current privilege level.
59
+ */
34
+ */
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
35
+static void
61
+ target_ulong *tlb_size, hwaddr addr,
36
+build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms)
62
+ int size, MMUAccessType access_type,
63
+ int mode)
64
+{
37
+{
65
+ pmp_priv_t pmp_priv;
38
+ int i;
66
+ target_ulong tlb_size_pmp = 0;
39
+ uint64_t mem_base;
40
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
41
+ MachineState *ms = MACHINE(vms);
42
+ const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
43
+ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
44
+ .oem_table_id = vms->oem_table_id };
67
+
45
+
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
46
+ acpi_table_begin(&table, table_data);
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
47
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
70
+ return TRANSLATE_SUCCESS;
48
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
49
+
50
+ for (i = 0; i < cpu_list->len; ++i) {
51
+ uint32_t nodeid = cpu_list->cpus[i].props.node_id;
52
+ /*
53
+ * 5.2.16.8 RINTC Affinity Structure
54
+ */
55
+ build_append_int_noprefix(table_data, 7, 1); /* Type */
56
+ build_append_int_noprefix(table_data, 20, 1); /* Length */
57
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
58
+ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
59
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
60
+ /* Flags, Table 5-70 */
61
+ build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4);
62
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
71
+ }
63
+ }
72
+
64
+
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
65
+ mem_base = vms->memmap[VIRT_DRAM].base;
74
+ mode)) {
66
+ for (i = 0; i < ms->numa_state->num_nodes; ++i) {
75
+ *prot = 0;
67
+ if (ms->numa_state->nodes[i].node_mem > 0) {
76
+ return TRANSLATE_PMP_FAIL;
68
+ build_srat_memory(table_data, mem_base,
77
+ }
69
+ ms->numa_state->nodes[i].node_mem, i,
78
+
70
+ MEM_AFFINITY_ENABLED);
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
71
+ mem_base += ms->numa_state->nodes[i].node_mem;
80
+ if (tlb_size != NULL) {
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
82
+ *tlb_size = tlb_size_pmp;
83
+ }
72
+ }
84
+ }
73
+ }
85
+
74
+
86
+ return TRANSLATE_SUCCESS;
75
+ acpi_table_end(linker, &table);
87
+}
76
+}
88
+
77
+
89
/* get_physical_address - get the physical address for this virtual address
78
static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
90
*
79
{
91
* Do a page table walk to obtain the physical address corresponding to a
80
GArray *table_offsets;
92
@@ -XXX,XX +XXX,XX @@ restart:
81
unsigned dsdt, xsdt;
93
pte_addr = base + idx * ptesize;
82
GArray *tables_blob = tables->table_data;
94
}
83
+ MachineState *ms = MACHINE(s);
95
84
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
85
table_offsets = g_array_new(false, true,
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
86
sizeof(uint32_t));
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
87
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
99
+ int pmp_prot;
88
s->oem_table_id);
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
89
}
101
+ sizeof(target_ulong),
90
102
+ MMU_DATA_LOAD, PRV_S);
91
+ if (ms->numa_state->num_nodes > 0) {
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
92
+ acpi_add_table(table_offsets, tables_blob);
104
return TRANSLATE_PMP_FAIL;
93
+ build_srat(tables_blob, tables->linker, s);
105
}
94
+ if (ms->numa_state->have_numa_distance) {
106
95
+ acpi_add_table(table_offsets, tables_blob);
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
96
+ build_slit(tables_blob, tables->linker, ms, s->oem_id,
108
#ifndef CONFIG_USER_ONLY
97
+ s->oem_table_id);
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
98
+ }
154
}
155
+
156
if (ret == TRANSLATE_PMP_FAIL) {
157
pmp_violation = true;
158
}
159
160
if (ret == TRANSLATE_SUCCESS) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
163
- prot, mmu_idx, tlb_size);
164
- } else {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/target/riscv/pmp.c
176
+++ b/target/riscv/pmp.c
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
178
return result;
179
}
180
181
+/*
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
183
+ */
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
186
+ target_ulong mode)
187
+{
188
+ bool ret;
189
+
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
191
+ /*
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
194
+ */
195
+ ret = true;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
197
+ } else {
198
+ /*
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
200
+ * but there are rules. We've checked for no rule earlier in this
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
99
+ }
206
+
100
+
207
+ return ret;
101
/* XSDT is pointed to by RSDP */
208
+}
102
xsdt = tables_blob->len;
209
+
103
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
210
211
/*
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
215
*/
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
219
+ target_ulong mode)
220
{
221
int i = 0;
222
int ret = -1;
223
int pmp_size = 0;
224
target_ulong s = 0;
225
target_ulong e = 0;
226
- pmp_priv_t allowed_privs = 0;
227
228
/* Short cut if no rules */
229
if (0 == pmp_get_num_rules(env)) {
230
- return (env->priv == PRV_M) ? true : false;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
232
+ allowed_privs, mode);
233
}
234
235
if (size == 0) {
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
237
* check
238
*/
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
245
}
246
247
- if ((privs & allowed_privs) == privs) {
248
- ret = 1;
249
- break;
250
- } else {
251
- ret = 0;
252
- break;
253
- }
254
+ ret = ((privs & *allowed_privs) == privs);
255
+ break;
256
}
257
}
258
259
/* No rule matched */
260
if (ret == -1) {
261
- if (mode == PRV_M) {
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
263
- * M-Mode access, the access succeeds */
264
- } else {
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
266
- * match a rule, but there are rules. We've checked for
267
- * no rule earlier in this function. */
268
- }
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
270
+ allowed_privs, mode);
271
}
272
273
return ret == 1 ? true : false;
274
}
275
276
-
277
/*
278
* Handle a write to a pmpcfg CSP
279
*/
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
281
282
return false;
283
}
284
+
285
+/*
286
+ * Convert PMP privilege to TLB page privilege.
287
+ */
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
289
+{
290
+ int prot = 0;
291
+
292
+ if (pmp_priv & PMP_READ) {
293
+ prot |= PAGE_READ;
294
+ }
295
+ if (pmp_priv & PMP_WRITE) {
296
+ prot |= PAGE_WRITE;
297
+ }
298
+ if (pmp_priv & PMP_EXEC) {
299
+ prot |= PAGE_EXEC;
300
+ }
301
+
302
+ return prot;
303
+}
304
--
104
--
305
2.30.1
105
2.44.0
306
307
diff view generated by jsdifflib
New patch
[PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Hotplugged FDT nodes will attempt to write this node that, at this
4
moment, is being created only in create_fdt_pcie() during
5
finalize_fdt().
6
7
Create it earlier.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-ID: <20240217192607.32565-4-dbarboza@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
hw/riscv/virt.c | 9 ++++++++-
15
1 file changed, 8 insertions(+), 1 deletion(-)
16
17
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/riscv/virt.c
20
+++ b/hw/riscv/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
22
23
name = g_strdup_printf("/soc/pci@%lx",
24
(long) memmap[VIRT_PCIE_ECAM].base);
25
- qemu_fdt_add_subnode(ms->fdt, name);
26
qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
27
FDT_PCI_ADDR_CELLS);
28
qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
29
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
30
{
31
MachineState *ms = MACHINE(s);
32
uint8_t rng_seed[32];
33
+ g_autofree char *name = NULL;
34
35
ms->fdt = create_device_tree(&s->fdt_size);
36
if (!ms->fdt) {
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
38
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
39
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
40
41
+ /*
42
+ * The "/soc/pci@..." node is needed for PCIE hotplugs
43
+ * that might happen before finalize_fdt().
44
+ */
45
+ name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base);
46
+ qemu_fdt_add_subnode(ms->fdt, name);
47
+
48
qemu_fdt_add_subnode(ms->fdt, "/chosen");
49
50
/* Pass seed to RNG */
51
--
52
2.44.0
diff view generated by jsdifflib
[PULL 10/16] hw/riscv: allow ramfb on virt
[PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Allow ramfb on virt. This lets `-device ramfb' work.
3
We want to add a RISC-V 'virt' libqos machine to increase our test
4
coverage. Some of the tests will try to plug a virtio-iommu-pci
5
device into the board and do some tests with it.
4
6
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
7
Enable virtio-iommu-pci in the 'virt' machine.
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-ID: <20240217192607.32565-5-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
13
---
11
hw/riscv/virt.c | 3 +++
14
hw/riscv/virt.c | 36 +++++++++++++++++++++++++++++++++++-
12
1 file changed, 3 insertions(+)
15
1 file changed, 35 insertions(+), 1 deletion(-)
13
16
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
17
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
19
--- a/hw/riscv/virt.c
17
+++ b/hw/riscv/virt.c
20
+++ b/hw/riscv/virt.c
18
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
19
#include "sysemu/sysemu.h"
22
#include "hw/display/ramfb.h"
20
#include "hw/pci/pci.h"
23
#include "hw/acpi/aml-build.h"
21
#include "hw/pci-host/gpex.h"
24
#include "qapi/qapi-visit-common.h"
22
+#include "hw/display/ramfb.h"
25
+#include "hw/virtio/virtio-iommu.h"
23
26
24
static const MemMapEntry virt_memmap[] = {
27
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
25
[VIRT_DEBUG] = { 0x0, 0x100 },
28
static bool virt_use_kvm_aia(RISCVVirtState *s)
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
29
@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
31
}
29
mc->numa_mem_supported = true;
32
33
+static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
34
+{
35
+ const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
36
+ void *fdt = MACHINE(s)->fdt;
37
+ uint32_t iommu_phandle;
38
+ g_autofree char *iommu_node = NULL;
39
+ g_autofree char *pci_node = NULL;
30
+
40
+
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
41
+ pci_node = g_strdup_printf("/soc/pci@%lx",
42
+ (long) virt_memmap[VIRT_PCIE_ECAM].base);
43
+ iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
44
+ PCI_SLOT(bdf), PCI_FUNC(bdf));
45
+ iommu_phandle = qemu_fdt_alloc_phandle(fdt);
46
+
47
+ qemu_fdt_add_subnode(fdt, iommu_node);
48
+
49
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
50
+ qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
51
+ 1, bdf << 8, 1, 0, 1, 0,
52
+ 1, 0, 1, 0);
53
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
54
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
55
+
56
+ qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
57
+ 0, iommu_phandle, 0, bdf,
58
+ bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
59
+}
60
+
61
static void finalize_fdt(RISCVVirtState *s)
62
{
63
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
64
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
65
{
66
MachineClass *mc = MACHINE_GET_CLASS(machine);
67
68
- if (device_is_dynamic_sysbus(mc, dev)) {
69
+ if (device_is_dynamic_sysbus(mc, dev) ||
70
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
71
return HOTPLUG_HANDLER(machine);
72
}
73
return NULL;
74
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
75
SYS_BUS_DEVICE(dev));
76
}
77
}
78
+
79
+ if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
80
+ create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
81
+ }
32
}
82
}
33
83
34
static const TypeInfo virt_machine_typeinfo = {
84
static void virt_machine_class_init(ObjectClass *oc, void *data)
35
--
85
--
36
2.30.1
86
2.44.0
37
38
diff view generated by jsdifflib
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
[PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Provides fw_cfg for the virt machine on riscv. This enables
3
The 'virt' machine makes assumptions on the Advanced Core-Local
4
using e.g. ramfb later.
4
Interruptor, or aclint, based on 'tcg_enabled()' conditionals. This
5
will impact MSI related tests support when adding a RISC-V 'virt' libqos
6
machine. The accelerator used in that case, 'qtest', isn't being
7
accounted for and we'll error out if we try to enable aclint.
5
8
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
9
Create a new virt_aclint_allowed() helper to gate the aclint code
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
considering both TCG and 'qtest' accelerators. The error message is
11
left untouched, mentioning TCG only, because we don't expect the
12
regular user to be aware of 'qtest'.
13
14
We want to add 'qtest' support for aclint only, leaving the TCG specific
15
bits out of it. This is done by changing the current format we use
16
today:
17
18
if (tcg_enabled()) {
19
if (s->have_aclint) { - aclint logic - }
20
else { - non-aclint, TCG logic - }
21
}
22
23
into:
24
25
if (virt_aclint_allowed() && s->have_aclint) {
26
- aclint logic -
27
} else if (tcg_enabled()) {
28
- non-aclint, TCG logic -
29
}
30
31
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
33
Message-ID: <20240217192607.32565-6-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
35
---
12
include/hw/riscv/virt.h | 2 ++
36
hw/riscv/virt.c | 52 +++++++++++++++++++++++++------------------------
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
37
1 file changed, 27 insertions(+), 25 deletions(-)
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 33 insertions(+)
16
38
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
20
+++ b/include/hw/riscv/virt.h
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
23
DeviceState *plic[VIRT_SOCKETS_MAX];
24
PFlashCFI01 *flash[2];
25
+ FWCfgState *fw_cfg;
26
27
int fdt_size;
28
};
29
@@ -XXX,XX +XXX,XX @@ enum {
30
VIRT_PLIC,
31
VIRT_UART0,
32
VIRT_VIRTIO,
33
+ VIRT_FW_CFG,
34
VIRT_FLASH,
35
VIRT_DRAM,
36
VIRT_PCIE_MMIO,
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
39
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/riscv/virt.c
41
--- a/hw/riscv/virt.c
40
+++ b/hw/riscv/virt.c
42
+++ b/hw/riscv/virt.c
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
43
@@ -XXX,XX +XXX,XX @@
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
44
#include "sysemu/tcg.h"
43
[VIRT_UART0] = { 0x10000000, 0x100 },
45
#include "sysemu/kvm.h"
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
46
#include "sysemu/tpm.h"
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
47
+#include "sysemu/qtest.h"
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
48
#include "hw/pci/pci.h"
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
49
#include "hw/pci-host/gpex.h"
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
50
#include "hw/display/ramfb.h"
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
51
@@ -XXX,XX +XXX,XX @@ static bool virt_use_kvm_aia(RISCVVirtState *s)
50
return dev;
52
return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
51
}
53
}
52
54
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
55
+static bool virt_aclint_allowed(void)
54
+{
56
+{
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
57
+ return tcg_enabled() || qtest_enabled();
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
57
+ FWCfgState *fw_cfg;
58
+ char *nodename;
59
+
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
61
+ &address_space_memory);
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
63
+
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
67
+ "compatible", "qemu,fw-cfg-mmio");
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
73
+}
58
+}
74
+
59
+
75
static void virt_machine_init(MachineState *machine)
60
static const MemMapEntry virt_memmap[] = {
76
{
61
[VIRT_DEBUG] = { 0x0, 0x100 },
77
const MemMapEntry *memmap = virt_memmap;
62
[VIRT_MROM] = { 0x1000, 0xf000 },
63
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
64
65
create_fdt_socket_memory(s, memmap, socket);
66
67
- if (tcg_enabled()) {
68
- if (s->have_aclint) {
69
- create_fdt_socket_aclint(s, memmap, socket,
70
- &intc_phandles[phandle_pos]);
71
- } else {
72
- create_fdt_socket_clint(s, memmap, socket,
73
- &intc_phandles[phandle_pos]);
74
- }
75
+ if (virt_aclint_allowed() && s->have_aclint) {
76
+ create_fdt_socket_aclint(s, memmap, socket,
77
+ &intc_phandles[phandle_pos]);
78
+ } else if (tcg_enabled()) {
79
+ create_fdt_socket_clint(s, memmap, socket,
80
+ &intc_phandles[phandle_pos]);
81
}
82
}
83
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
84
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
79
start_addr = virt_memmap[VIRT_FLASH].base;
85
exit(1);
80
}
86
}
81
87
82
+ /*
88
- if (!tcg_enabled() && s->have_aclint) {
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
89
+ if (!virt_aclint_allowed() && s->have_aclint) {
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
90
error_report("'aclint' is only available with TCG acceleration");
85
+ */
91
exit(1);
86
+ s->fw_cfg = create_fw_cfg(machine);
92
}
87
+ rom_set_fw(s->fw_cfg);
93
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
88
+
94
hart_count, &error_abort);
89
/* Compute the fdt load address in dram */
95
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
96
91
machine->ram_size, machine->fdt);
97
- if (tcg_enabled()) {
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
98
- if (s->have_aclint) {
93
index XXXXXXX..XXXXXXX 100644
99
- if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
94
--- a/hw/riscv/Kconfig
100
- /* Per-socket ACLINT MTIMER */
95
+++ b/hw/riscv/Kconfig
101
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
102
+ if (virt_aclint_allowed() && s->have_aclint) {
97
select SIFIVE_PLIC
103
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
98
select SIFIVE_TEST
104
+ /* Per-socket ACLINT MTIMER */
99
select VIRTIO_MMIO
105
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
100
+ select FW_CFG_DMA
106
i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
101
107
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
102
config SIFIVE_E
108
base_hartid, hart_count,
103
bool
109
RISCV_ACLINT_DEFAULT_MTIMECMP,
110
RISCV_ACLINT_DEFAULT_MTIME,
111
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
112
- } else {
113
- /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
114
- riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
115
+ } else {
116
+ /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
117
+ riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
118
i * memmap[VIRT_CLINT].size,
119
base_hartid, hart_count, false);
120
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
121
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
122
i * memmap[VIRT_CLINT].size +
123
RISCV_ACLINT_SWI_SIZE,
124
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
125
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
126
RISCV_ACLINT_DEFAULT_MTIMECMP,
127
RISCV_ACLINT_DEFAULT_MTIME,
128
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
129
- riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
130
+ riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
131
i * memmap[VIRT_ACLINT_SSWI].size,
132
base_hartid, hart_count, true);
133
- }
134
- } else {
135
- /* Per-socket SiFive CLINT */
136
- riscv_aclint_swi_create(
137
+ }
138
+ } else if (tcg_enabled()) {
139
+ /* Per-socket SiFive CLINT */
140
+ riscv_aclint_swi_create(
141
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
142
base_hartid, hart_count, false);
143
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
144
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
145
i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
146
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
147
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
148
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
149
- }
150
}
151
152
/* Per-socket interrupt controller */
104
--
153
--
105
2.30.1
154
2.44.0
106
107
diff view generated by jsdifflib
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PULL 20/34] tests/libqos: add riscv/virt machine nodes
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
This adds the documentation to describe what is supported for the
3
Add a RISC-V 'virt' machine to the graph. This implementation is a
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
4
modified copy of the existing arm machine in arm-virt-machine.c
5
5
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
It contains a virtio-mmio and a generic-pcihost controller. The
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
generic-pcihost controller hardcodes assumptions from the ARM 'virt'
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
8
machine, like ecam and pio_base addresses, so we'll add an extra step to
9
set its parameters after creating it.
10
11
Our command line is incremented with 'aclint' parameters to allow the
12
machine to run MSI tests.
13
14
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
Acked-by: Thomas Huth <thuth@redhat.com>
17
Message-ID: <20240217192607.32565-7-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
19
---
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
20
tests/qtest/libqos/riscv-virt-machine.c | 137 ++++++++++++++++++++++++
12
docs/system/target-riscv.rst | 1 +
21
tests/qtest/libqos/meson.build | 1 +
13
2 files changed, 90 insertions(+)
22
2 files changed, 138 insertions(+)
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
23
create mode 100644 tests/qtest/libqos/riscv-virt-machine.c
15
24
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
25
diff --git a/tests/qtest/libqos/riscv-virt-machine.c b/tests/qtest/libqos/riscv-virt-machine.c
17
new file mode 100644
26
new file mode 100644
18
index XXXXXXX..XXXXXXX
27
index XXXXXXX..XXXXXXX
19
--- /dev/null
28
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
29
+++ b/tests/qtest/libqos/riscv-virt-machine.c
21
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
31
+/*
23
+=============================================================
32
+ * libqos driver framework for risc-v
33
+ *
34
+ * Initial version based on arm-virt-machine.c
35
+ *
36
+ * Copyright (c) 2024 Ventana Micro
37
+ *
38
+ * This library is free software; you can redistribute it and/or
39
+ * modify it under the terms of the GNU Lesser General Public
40
+ * License version 2.1 as published by the Free Software Foundation.
41
+ *
42
+ * This library is distributed in the hope that it will be useful,
43
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
44
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
45
+ * Lesser General Public License for more details.
46
+ *
47
+ * You should have received a copy of the GNU Lesser General Public
48
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
49
+ */
24
+
50
+
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
51
+#include "qemu/osdep.h"
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
52
+#include "../libqtest.h"
53
+#include "qemu/module.h"
54
+#include "libqos-malloc.h"
55
+#include "qgraph.h"
56
+#include "virtio-mmio.h"
57
+#include "generic-pcihost.h"
58
+#include "hw/pci/pci_regs.h"
27
+
59
+
28
+For more details about Microchip PolarFire SoC, please see:
60
+#define RISCV_PAGE_SIZE 4096
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
30
+
61
+
31
+The Icicle Kit board information can be found here:
62
+/* VIRT_DRAM */
32
+https://www.microsemi.com/existing-parts/parts/152514
63
+#define RISCV_VIRT_RAM_ADDR 0x80000000
64
+#define RISCV_VIRT_RAM_SIZE 0x20000000
33
+
65
+
34
+Supported devices
66
+/*
35
+-----------------
67
+ * VIRT_VIRTIO. BASE_ADDR points to the last
68
+ * virtio_mmio device.
69
+ */
70
+#define VIRTIO_MMIO_BASE_ADDR 0x10008000
71
+#define VIRTIO_MMIO_SIZE 0x00001000
36
+
72
+
37
+The ``microchip-icicle-kit`` machine supports the following devices:
73
+/* VIRT_PCIE_PIO */
74
+#define RISCV_GPEX_PIO_BASE 0x3000000
75
+#define RISCV_BUS_PIO_LIMIT 0x10000
38
+
76
+
39
+ * 1 E51 core
77
+/* VIRT_PCIE_MMIO */
40
+ * 4 U54 cores
78
+#define RISCV_BUS_MMIO_ALLOC_PTR 0x40000000
41
+ * Core Level Interruptor (CLINT)
79
+#define RISCV_BUS_MMIO_LIMIT 0x80000000
42
+ * Platform-Level Interrupt Controller (PLIC)
43
+ * L2 Loosely Integrated Memory (L2-LIM)
44
+ * DDR memory controller
45
+ * 5 MMUARTs
46
+ * 1 DMA controller
47
+ * 2 GEM Ethernet controllers
48
+ * 1 SDHC storage controller
49
+
80
+
50
+Boot options
81
+/* VIRT_PCIE_ECAM */
51
+------------
82
+#define RISCV_ECAM_ALLOC_PTR 0x30000000
52
+
83
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
84
+typedef struct QVirtMachine QVirtMachine;
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
56
+support direct kernel loading via the -kernel option. One has to load kernel
57
+from U-Boot.
58
+
85
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
86
+struct QVirtMachine {
60
+memory size by HSS. A sanity check on ram size is performed in the machine
87
+ QOSGraphObject obj;
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
88
+ QGuestAllocator alloc;
62
+than 1537 MiB ram is detected.
89
+ QVirtioMMIODevice virtio_mmio;
90
+ QGenericPCIHost bridge;
91
+};
63
+
92
+
64
+Boot the machine
93
+static void virt_destructor(QOSGraphObject *obj)
65
+----------------
94
+{
95
+ QVirtMachine *machine = (QVirtMachine *) obj;
96
+ alloc_destroy(&machine->alloc);
97
+}
66
+
98
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
99
+static void *virt_get_driver(void *object, const char *interface)
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
100
+{
69
+in the HSS source tree:
101
+ QVirtMachine *machine = object;
102
+ if (!g_strcmp0(interface, "memory")) {
103
+ return &machine->alloc;
104
+ }
70
+
105
+
71
+.. code-block:: bash
106
+ fprintf(stderr, "%s not present in riscv/virtio\n", interface);
107
+ g_assert_not_reached();
108
+}
72
+
109
+
73
+ $ export CROSS_COMPILE=riscv64-linux-
110
+static QOSGraphObject *virt_get_device(void *obj, const char *device)
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
111
+{
75
+ $ make BOARD=mpfs-icicle-kit-es
112
+ QVirtMachine *machine = obj;
113
+ if (!g_strcmp0(device, "generic-pcihost")) {
114
+ return &machine->bridge.obj;
115
+ } else if (!g_strcmp0(device, "virtio-mmio")) {
116
+ return &machine->virtio_mmio.obj;
117
+ }
76
+
118
+
77
+Download the official SD card image released by Microchip and prepare it for
119
+ fprintf(stderr, "%s not present in riscv/virt\n", device);
78
+QEMU usage:
120
+ g_assert_not_reached();
121
+}
79
+
122
+
80
+.. code-block:: bash
123
+static void riscv_config_qpci_bus(QGenericPCIBus *qpci)
124
+{
125
+ qpci->gpex_pio_base = RISCV_GPEX_PIO_BASE;
126
+ qpci->bus.pio_limit = RISCV_BUS_PIO_LIMIT;
81
+
127
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
128
+ qpci->bus.mmio_alloc_ptr = RISCV_BUS_MMIO_ALLOC_PTR;
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
129
+ qpci->bus.mmio_limit = RISCV_BUS_MMIO_LIMIT;
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
130
+
86
+Then we can boot the machine by:
131
+ qpci->ecam_alloc_ptr = RISCV_ECAM_ALLOC_PTR;
132
+}
87
+
133
+
88
+.. code-block:: bash
134
+static void *qos_create_machine_riscv_virt(QTestState *qts)
135
+{
136
+ QVirtMachine *machine = g_new0(QVirtMachine, 1);
89
+
137
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
138
+ alloc_init(&machine->alloc, 0,
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
139
+ RISCV_VIRT_RAM_ADDR,
92
+ -nic user,model=cadence_gem \
140
+ RISCV_VIRT_RAM_ADDR + RISCV_VIRT_RAM_SIZE,
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
141
+ RISCV_PAGE_SIZE);
94
+ -display none -serial stdio \
142
+ qvirtio_mmio_init_device(&machine->virtio_mmio, qts, VIRTIO_MMIO_BASE_ADDR,
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
143
+ VIRTIO_MMIO_SIZE);
96
+ -serial chardev:serial1
97
+
144
+
98
+With above command line, current terminal session will be used for the first
145
+ qos_create_generic_pcihost(&machine->bridge, qts, &machine->alloc);
99
+serial port. Open another terminal window, and use `minicom` to connect the
146
+ riscv_config_qpci_bus(&machine->bridge.pci);
100
+second serial port.
101
+
147
+
102
+.. code-block:: bash
148
+ machine->obj.get_device = virt_get_device;
149
+ machine->obj.get_driver = virt_get_driver;
150
+ machine->obj.destructor = virt_destructor;
151
+ return machine;
152
+}
103
+
153
+
104
+ $ minicom -D unix\#serial1.sock
154
+static void virt_machine_register_nodes(void)
155
+{
156
+ qos_node_create_machine_args("riscv32/virt", qos_create_machine_riscv_virt,
157
+ "aclint=on,aia=aplic-imsic");
158
+ qos_node_contains("riscv32/virt", "virtio-mmio", NULL);
159
+ qos_node_contains("riscv32/virt", "generic-pcihost", NULL);
105
+
160
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
161
+ qos_node_create_machine_args("riscv64/virt", qos_create_machine_riscv_virt,
107
+second serial port. U-Boot will automatically load the Linux kernel from
162
+ "aclint=on,aia=aplic-imsic");
108
+the SD card image.
163
+ qos_node_contains("riscv64/virt", "virtio-mmio", NULL);
164
+ qos_node_contains("riscv64/virt", "generic-pcihost", NULL);
165
+}
109
+
166
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
167
+libqos_init(virt_machine_register_nodes);
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
168
diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build
112
index XXXXXXX..XXXXXXX 100644
169
index XXXXXXX..XXXXXXX 100644
113
--- a/docs/system/target-riscv.rst
170
--- a/tests/qtest/libqos/meson.build
114
+++ b/docs/system/target-riscv.rst
171
+++ b/tests/qtest/libqos/meson.build
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
172
@@ -XXX,XX +XXX,XX @@ libqos_srcs = files(
116
.. toctree::
173
'arm-xilinx-zynq-a9-machine.c',
117
:maxdepth: 1
174
'ppc64_pseries-machine.c',
118
175
'x86_64_pc-machine.c',
119
+ riscv/microchip-icicle-kit
176
+ 'riscv-virt-machine.c',
120
riscv/sifive_u
177
)
121
178
122
RISC-V CPU features
179
if have_virtfs
123
--
180
--
124
2.30.1
181
2.44.0
125
126
diff view generated by jsdifflib
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
[PULL 21/34] RISC-V: Add support for Ztso
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Palmer Dabbelt <palmer@rivosinc.com>
2
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
3
The Ztso extension is already ratified, this adds it as a CPU property
4
further compressed instruction decoding. However, prior to this change,
4
and adds various fences throughout the port in order to allow TSO
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
5
targets to function on weaker hosts. We need no fences for AMOs as
6
fails to decode the instruction. This means that we skipped illegal
6
they're already SC, the places we need barriers are described.
7
compressed instructions instead of raising an illegal instruction
7
These fences are placed in the RISC-V backend rather than TCG as is
8
exception.
8
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
9
likely soon dynamic) hart memory models.
9
10
10
Instead of patching decode_RV32_64C(), we can just remove it,
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
as it is dead code since f330433b363 anyway.
12
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
12
13
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
14
Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
16
---
19
target/riscv/translate.c | 179 +--------------------------------------
17
target/riscv/cpu_cfg.h | 1 +
20
1 file changed, 1 insertion(+), 178 deletions(-)
18
target/riscv/cpu.c | 2 ++
19
target/riscv/translate.c | 3 +++
20
target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
21
target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
22
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
23
6 files changed, 48 insertions(+), 5 deletions(-)
21
24
25
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu_cfg.h
28
+++ b/target/riscv/cpu_cfg.h
29
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
30
bool ext_zihintntl;
31
bool ext_zihintpause;
32
bool ext_zihpm;
33
+ bool ext_ztso;
34
bool ext_smstateen;
35
bool ext_sstc;
36
bool ext_svadu;
37
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/cpu.c
40
+++ b/target/riscv/cpu.c
41
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
42
ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
43
ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
44
ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
45
+ ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
46
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
47
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
48
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
49
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
50
MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
51
MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
52
MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
53
+ MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
54
55
MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
56
MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
57
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
23
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
59
--- a/target/riscv/translate.c
25
+++ b/target/riscv/translate.c
60
+++ b/target/riscv/translate.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
61
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
27
CPUState *cs;
62
/* PointerMasking extension */
28
} DisasContext;
63
bool pm_mask_enabled;
29
64
bool pm_base_enabled;
30
-#ifdef TARGET_RISCV64
65
+ /* Ztso */
31
-/* convert riscv funct3 to qemu memop for load/store */
66
+ bool ztso;
32
-static const int tcg_memop_lookup[8] = {
67
/* Use icount trigger for native debug */
33
- [0 ... 7] = -1,
68
bool itrigger;
34
- [0] = MO_SB,
69
/* FRM is known to contain a valid value. */
35
- [1] = MO_TESW,
70
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
36
- [2] = MO_TESL,
71
ctx->cs = cs;
37
- [3] = MO_TEQ,
72
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
38
- [4] = MO_UB,
73
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
39
- [5] = MO_TEUW,
74
+ ctx->ztso = cpu->cfg.ext_ztso;
40
- [6] = MO_TEUL,
75
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
41
-};
76
ctx->zero = tcg_constant_tl(0);
42
-#endif
77
ctx->virt_inst_excp = false;
43
-
78
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
44
#ifdef TARGET_RISCV64
79
index XXXXXXX..XXXXXXX 100644
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
80
--- a/target/riscv/insn_trans/trans_rva.c.inc
46
#else
81
+++ b/target/riscv/insn_trans/trans_rva.c.inc
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
82
@@ -XXX,XX +XXX,XX @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
48
ctx->base.is_jmp = DISAS_NORETURN;
83
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
84
}
85
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
86
- if (a->aq) {
87
+ /*
88
+ * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
89
+ * AMOs. Instead treat them like loads.
90
+ */
91
+ if (a->aq || ctx->ztso) {
92
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
93
}
94
95
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
96
gen_set_label(l1);
97
/*
98
* Address comparison failure. However, we still need to
99
- * provide the memory barrier implied by AQ/RL.
100
+ * provide the memory barrier implied by AQ/RL/TSO.
101
*/
102
- tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
103
+ TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
104
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
105
gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
106
107
gen_set_label(l2);
108
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/riscv/insn_trans/trans_rvi.c.inc
111
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
112
@@ -XXX,XX +XXX,XX @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
113
114
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
115
{
116
+ bool out;
117
+
118
decode_save_opc(ctx);
119
if (get_xl(ctx) == MXL_RV128) {
120
- return gen_load_i128(ctx, a, memop);
121
+ out = gen_load_i128(ctx, a, memop);
122
} else {
123
- return gen_load_tl(ctx, a, memop);
124
+ out = gen_load_tl(ctx, a, memop);
125
+ }
126
+
127
+ if (ctx->ztso) {
128
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
129
}
130
+
131
+ return out;
49
}
132
}
50
133
51
-#ifdef TARGET_RISCV64
134
static bool trans_lb(DisasContext *ctx, arg_lb *a)
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
135
@@ -XXX,XX +XXX,XX @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
53
- target_long imm)
136
TCGv addr = get_address(ctx, a->rs1, a->imm);
54
-{
137
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
55
- TCGv t0 = tcg_temp_new();
138
56
- TCGv t1 = tcg_temp_new();
139
+ if (ctx->ztso) {
57
- gen_get_gpr(t0, rs1);
140
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
58
- tcg_gen_addi_tl(t0, t0, imm);
141
+ }
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
142
+
60
-
143
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
61
- if (memop < 0) {
144
return true;
62
- gen_exception_illegal(ctx);
63
- return;
64
- }
65
-
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
67
- gen_set_gpr(rd, t1);
68
- tcg_temp_free(t0);
69
- tcg_temp_free(t1);
70
-}
71
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
73
- target_long imm)
74
-{
75
- TCGv t0 = tcg_temp_new();
76
- TCGv dat = tcg_temp_new();
77
- gen_get_gpr(t0, rs1);
78
- tcg_gen_addi_tl(t0, t0, imm);
79
- gen_get_gpr(dat, rs2);
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
81
-
82
- if (memop < 0) {
83
- gen_exception_illegal(ctx);
84
- return;
85
- }
86
-
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
88
- tcg_temp_free(t0);
89
- tcg_temp_free(dat);
90
-}
91
-#endif
92
-
93
#ifndef CONFIG_USER_ONLY
94
/* The states of mstatus_fs are:
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
98
#endif
99
100
-#if !defined(TARGET_RISCV64)
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
102
- int rs1, target_long imm)
103
-{
104
- TCGv t0;
105
-
106
- if (ctx->mstatus_fs == 0) {
107
- gen_exception_illegal(ctx);
108
- return;
109
- }
110
-
111
- t0 = tcg_temp_new();
112
- gen_get_gpr(t0, rs1);
113
- tcg_gen_addi_tl(t0, t0, imm);
114
-
115
- switch (opc) {
116
- case OPC_RISC_FLW:
117
- if (!has_ext(ctx, RVF)) {
118
- goto do_illegal;
119
- }
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
123
- break;
124
- case OPC_RISC_FLD:
125
- if (!has_ext(ctx, RVD)) {
126
- goto do_illegal;
127
- }
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
129
- break;
130
- do_illegal:
131
- default:
132
- gen_exception_illegal(ctx);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
139
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
141
- int rs2, target_long imm)
142
-{
143
- TCGv t0;
144
-
145
- if (ctx->mstatus_fs == 0) {
146
- gen_exception_illegal(ctx);
147
- return;
148
- }
149
-
150
- t0 = tcg_temp_new();
151
- gen_get_gpr(t0, rs1);
152
- tcg_gen_addi_tl(t0, t0, imm);
153
-
154
- switch (opc) {
155
- case OPC_RISC_FSW:
156
- if (!has_ext(ctx, RVF)) {
157
- goto do_illegal;
158
- }
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
179
TCGv_i32 t0;
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
181
tcg_temp_free_i32(t0);
182
}
145
}
183
146
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
147
index XXXXXXX..XXXXXXX 100644
185
-{
148
--- a/target/riscv/insn_trans/trans_rvv.c.inc
186
- uint8_t funct3 = extract16(opcode, 13, 3);
149
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
150
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
188
- uint8_t rs1s = GET_C_RS1S(opcode);
151
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
189
-
152
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
190
- switch (funct3) {
153
191
- case 3:
154
+ /*
192
-#if defined(TARGET_RISCV64)
155
+ * According to the specification
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
156
+ *
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
157
+ * Additionally, if the Ztso extension is implemented, then vector memory
195
- GET_C_LD_IMM(opcode));
158
+ * instructions in the V extension and Zve family of extensions follow
196
-#else
159
+ * RVTSO at the instruction level. The Ztso extension does not
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
160
+ * strengthen the ordering of intra-instruction element accesses.
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
161
+ *
199
- GET_C_LW_IMM(opcode));
162
+ * as a result neither ordered nor unordered accesses from the V
200
-#endif
163
+ * instructions need ordering within the loop but we do still need barriers
201
- break;
164
+ * around the loop.
202
- case 7:
165
+ */
203
-#if defined(TARGET_RISCV64)
166
+ if (is_store && s->ztso) {
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
167
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
168
+ }
206
- GET_C_LD_IMM(opcode));
169
+
207
-#else
170
fn(dest, mask, base, tcg_env, desc);
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
171
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
172
+ if (!is_store && s->ztso) {
210
- GET_C_LW_IMM(opcode));
173
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
211
-#endif
174
+ }
212
- break;
175
+
213
- }
176
if (!is_store) {
214
-}
177
mark_vs_dirty(s);
215
-
178
}
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
229
return nf + 1;
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
231
} else {
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
233
if (!decode_insn16(ctx, opcode)) {
234
- /* fall back to old decoder */
235
- decode_RV32_64C(ctx, opcode);
236
+ gen_exception_illegal(ctx);
237
}
238
}
239
} else {
240
--
179
--
241
2.30.1
180
2.44.0
242
181
243
182
diff view generated by jsdifflib
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
[PULL 22/34] linux-user/riscv: Add Ztso extension to hwprobe
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
3
This patch exposes Ztso via hwprobe in QEMU's user space emulator.
4
the address bytes. Note only SPI mode is supported by SST flashes.
5
4
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
5
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
7
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Message-ID: <20240207122256.902627-3-christoph.muellner@vrull.eu>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
9
---
13
hw/block/m25p80.c | 3 +++
10
linux-user/syscall.c | 3 +++
14
1 file changed, 3 insertions(+)
11
1 file changed, 3 insertions(+)
15
12
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
13
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
15
--- a/linux-user/syscall.c
19
+++ b/hw/block/m25p80.c
16
+++ b/linux-user/syscall.c
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
17
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
21
s->needed_bytes = get_addr_length(s);
18
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
22
switch (get_man(s)) {
19
#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
23
/* Dummy cycles - modeled with bytes writes instead of bits */
20
#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
24
+ case MAN_SST:
21
+#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
25
+ s->needed_bytes += 1;
22
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
26
+ break;
23
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
27
case MAN_WINBOND:
24
28
s->needed_bytes += 8;
25
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
29
break;
26
RISCV_HWPROBE_EXT_ZVFHMIN : 0;
27
value |= cfg->ext_zfa ?
28
RISCV_HWPROBE_EXT_ZFA : 0;
29
+ value |= cfg->ext_ztso ?
30
+ RISCV_HWPROBE_EXT_ZTSO : 0;
31
value |= cfg->ext_zacas ?
32
RISCV_HWPROBE_EXT_ZACAS : 0;
33
value |= cfg->ext_zicond ?
30
--
34
--
31
2.30.1
35
2.44.0
32
36
33
37
diff view generated by jsdifflib
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
[PULL 23/34] tests: riscv64: Use 'zfa' instead of 'Zfa'
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
The current condition for the use of background registers only
3
Running test-fcvtmod triggers the following deprecation warning:
4
considers the hypervisor load and store instructions,
4
warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
5
Let's fix that.
6
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-ID: <20240229180656.1208881-1-christoph.muellner@vrull.eu>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
13
---
12
target/riscv/cpu_helper.c | 2 +-
14
tests/tcg/riscv64/Makefile.target | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
14
16
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
19
--- a/tests/tcg/riscv64/Makefile.target
18
+++ b/target/riscv/cpu_helper.c
20
+++ b/tests/tcg/riscv64/Makefile.target
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
21
@@ -XXX,XX +XXX,XX @@ run-test-aes: QEMU_OPTS += -cpu rv64,zk=on
20
* was called. Background registers will be used if the guest has
22
TESTS += test-fcvtmod
21
* forced a two stage translation to be on (in HS or M mode).
23
test-fcvtmod: CFLAGS += -march=rv64imafdc
22
*/
24
test-fcvtmod: LDFLAGS += -static
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
25
-run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
26
+run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,zfa=true
25
use_background = true;
26
}
27
28
--
27
--
29
2.30.1
28
2.44.0
30
29
31
30
diff view generated by jsdifflib
New patch
[PULL 24/34] linux-headers: Update to Linux v6.8-rc6
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The idea with this update is to get the latest KVM caps for RISC-V.
4
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-ID: <20240304134732.386590-2-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
include/standard-headers/drm/drm_fourcc.h | 10 +-
11
include/standard-headers/linux/ethtool.h | 41 +++--
12
.../standard-headers/linux/virtio_config.h | 8 +-
13
include/standard-headers/linux/virtio_pci.h | 68 +++++++++
14
include/standard-headers/linux/virtio_pmem.h | 7 +
15
linux-headers/asm-generic/unistd.h | 15 +-
16
linux-headers/asm-mips/mman.h | 2 +-
17
linux-headers/asm-mips/unistd_n32.h | 5 +
18
linux-headers/asm-mips/unistd_n64.h | 5 +
19
linux-headers/asm-mips/unistd_o32.h | 5 +
20
linux-headers/asm-powerpc/unistd_32.h | 5 +
21
linux-headers/asm-powerpc/unistd_64.h | 5 +
22
linux-headers/asm-riscv/kvm.h | 40 +++++
23
linux-headers/asm-s390/unistd_32.h | 5 +
24
linux-headers/asm-s390/unistd_64.h | 5 +
25
linux-headers/asm-x86/kvm.h | 3 +
26
linux-headers/asm-x86/unistd_32.h | 5 +
27
linux-headers/asm-x86/unistd_64.h | 5 +
28
linux-headers/asm-x86/unistd_x32.h | 5 +
29
linux-headers/linux/iommufd.h | 79 ++++++++++
30
linux-headers/linux/kvm.h | 140 +++++++-----------
31
linux-headers/linux/userfaultfd.h | 29 +++-
32
linux-headers/linux/vfio.h | 1 +
33
23 files changed, 381 insertions(+), 112 deletions(-)
34
35
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/standard-headers/drm/drm_fourcc.h
38
+++ b/include/standard-headers/drm/drm_fourcc.h
39
@@ -XXX,XX +XXX,XX @@ extern "C" {
40
* Format modifiers may change any property of the buffer, including the number
41
* of planes and/or the required allocation size. Format modifiers are
42
* vendor-namespaced, and as such the relationship between a fourcc code and a
43
- * modifier is specific to the modifer being used. For example, some modifiers
44
+ * modifier is specific to the modifier being used. For example, some modifiers
45
* may preserve meaning - such as number of planes - from the fourcc code,
46
* whereas others may not.
47
*
48
@@ -XXX,XX +XXX,XX @@ extern "C" {
49
* format.
50
* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
51
* see modifiers as opaque tokens they can check for equality and intersect.
52
- * These users musn't need to know to reason about the modifier value
53
+ * These users mustn't need to know to reason about the modifier value
54
* (i.e. they are not expected to extract information out of the modifier).
55
*
56
* Vendors should document their modifier usage in as much detail as
57
@@ -XXX,XX +XXX,XX @@ extern "C" {
58
* This is a tiled layout using 4Kb tiles in row-major layout.
59
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
60
* are arranged in four groups (two wide, two high) with column-major layout.
61
- * Each group therefore consits out of four 256 byte units, which are also laid
62
+ * Each group therefore consists out of four 256 byte units, which are also laid
63
* out as 2x2 column-major.
64
* 256 byte units are made out of four 64 byte blocks of pixels, producing
65
* either a square block or a 2:1 unit.
66
@@ -XXX,XX +XXX,XX @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
67
*/
68
69
/*
70
- * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
71
+ * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
72
* modifiers) denote the category for modifiers. Currently we have three
73
* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
74
* sixteen different categories.
75
@@ -XXX,XX +XXX,XX @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
76
* Amlogic FBC Memory Saving mode
77
*
78
* Indicates the storage is packed when pixel size is multiple of word
79
- * boudaries, i.e. 8bit should be stored in this mode to save allocation
80
+ * boundaries, i.e. 8bit should be stored in this mode to save allocation
81
* memory.
82
*
83
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
84
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/standard-headers/linux/ethtool.h
87
+++ b/include/standard-headers/linux/ethtool.h
88
@@ -XXX,XX +XXX,XX @@ struct ethtool_rxfh_indir {
89
*    hardware hash key.
90
* @hfunc: Defines the current RSS hash function used by HW (or to be set to).
91
*    Valid values are one of the %ETH_RSS_HASH_*.
92
+ * @input_xfrm: Defines how the input data is transformed. Valid values are one
93
+ *    of %RXH_XFRM_*.
94
* @rsvd8: Reserved for future use; see the note on reserved space.
95
* @rsvd32: Reserved for future use; see the note on reserved space.
96
* @rss_config: RX ring/queue index for each hash value i.e., indirection table
97
@@ -XXX,XX +XXX,XX @@ struct ethtool_rxfh {
98
    uint32_t indir_size;
99
    uint32_t key_size;
100
    uint8_t    hfunc;
101
-    uint8_t    rsvd8[3];
102
+    uint8_t    input_xfrm;
103
+    uint8_t    rsvd8[2];
104
    uint32_t    rsvd32;
105
    uint32_t rss_config[];
106
};
107
@@ -XXX,XX +XXX,XX @@ static inline int ethtool_validate_duplex(uint8_t duplex)
108
109
#define WOL_MODE_COUNT        8
110
111
+/* RSS hash function data
112
+ * XOR the corresponding source and destination fields of each specified
113
+ * protocol. Both copies of the XOR'ed fields are fed into the RSS and RXHASH
114
+ * calculation. Note that this XORing reduces the input set entropy and could
115
+ * be exploited to reduce the RSS queue spread.
116
+ */
117
+#define    RXH_XFRM_SYM_XOR    (1 << 0)
118
+#define    RXH_XFRM_NO_CHANGE    0xff
119
+
120
/* L2-L4 network traffic flow types */
121
#define    TCP_V4_FLOW    0x01    /* hash or spec (tcp_ip4_spec) */
122
#define    UDP_V4_FLOW    0x02    /* hash or spec (udp_ip4_spec) */
123
@@ -XXX,XX +XXX,XX @@ enum ethtool_reset_flags {
124
*    refused. For drivers: ignore this field (use kernel's
125
*    __ETHTOOL_LINK_MODE_MASK_NBITS instead), any change to it will
126
*    be overwritten by kernel.
127
- * @supported: Bitmap with each bit meaning given by
128
- *    %ethtool_link_mode_bit_indices for the link modes, physical
129
- *    connectors and other link features for which the interface
130
- *    supports autonegotiation or auto-detection. Read-only.
131
- * @advertising: Bitmap with each bit meaning given by
132
- *    %ethtool_link_mode_bit_indices for the link modes, physical
133
- *    connectors and other link features that are advertised through
134
- *    autonegotiation or enabled for auto-detection.
135
- * @lp_advertising: Bitmap with each bit meaning given by
136
- *    %ethtool_link_mode_bit_indices for the link modes, and other
137
- *    link features that the link partner advertised through
138
- *    autonegotiation; 0 if unknown or not applicable. Read-only.
139
* @transceiver: Used to distinguish different possible PHY types,
140
*    reported consistently by PHYLIB. Read-only.
141
* @master_slave_cfg: Master/slave port mode.
142
@@ -XXX,XX +XXX,XX @@ enum ethtool_reset_flags {
143
* %set_link_ksettings() should validate all fields other than @cmd
144
* and @link_mode_masks_nwords that are not described as read-only or
145
* deprecated, and must ignore all fields described as read-only.
146
+ *
147
+ * @link_mode_masks is divided into three bitfields, each of length
148
+ * @link_mode_masks_nwords:
149
+ * - supported: Bitmap with each bit meaning given by
150
+ *    %ethtool_link_mode_bit_indices for the link modes, physical
151
+ *    connectors and other link features for which the interface
152
+ *    supports autonegotiation or auto-detection. Read-only.
153
+ * - advertising: Bitmap with each bit meaning given by
154
+ *    %ethtool_link_mode_bit_indices for the link modes, physical
155
+ *    connectors and other link features that are advertised through
156
+ *    autonegotiation or enabled for auto-detection.
157
+ * - lp_advertising: Bitmap with each bit meaning given by
158
+ *    %ethtool_link_mode_bit_indices for the link modes, and other
159
+ *    link features that the link partner advertised through
160
+ *    autonegotiation; 0 if unknown or not applicable. Read-only.
161
*/
162
struct ethtool_link_settings {
163
    uint32_t    cmd;
164
diff --git a/include/standard-headers/linux/virtio_config.h b/include/standard-headers/linux/virtio_config.h
165
index XXXXXXX..XXXXXXX 100644
166
--- a/include/standard-headers/linux/virtio_config.h
167
+++ b/include/standard-headers/linux/virtio_config.h
168
@@ -XXX,XX +XXX,XX @@
169
* rest are per-device feature bits.
170
*/
171
#define VIRTIO_TRANSPORT_F_START    28
172
-#define VIRTIO_TRANSPORT_F_END        41
173
+#define VIRTIO_TRANSPORT_F_END        42
174
175
#ifndef VIRTIO_CONFIG_NO_LEGACY
176
/* Do we get callbacks when the ring is completely used, even if we've
177
@@ -XXX,XX +XXX,XX @@
178
* This feature indicates that the driver can reset a queue individually.
179
*/
180
#define VIRTIO_F_RING_RESET        40
181
+
182
+/*
183
+ * This feature indicates that the device support administration virtqueues.
184
+ */
185
+#define VIRTIO_F_ADMIN_VQ        41
186
+
187
#endif /* _LINUX_VIRTIO_CONFIG_H */
188
diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h
189
index XXXXXXX..XXXXXXX 100644
190
--- a/include/standard-headers/linux/virtio_pci.h
191
+++ b/include/standard-headers/linux/virtio_pci.h
192
@@ -XXX,XX +XXX,XX @@ struct virtio_pci_modern_common_cfg {
193
194
    uint16_t queue_notify_data;    /* read-write */
195
    uint16_t queue_reset;        /* read-write */
196
+
197
+    uint16_t admin_queue_index;    /* read-only */
198
+    uint16_t admin_queue_num;        /* read-only */
199
};
200
201
/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
202
@@ -XXX,XX +XXX,XX @@ struct virtio_pci_cfg_cap {
203
#define VIRTIO_PCI_COMMON_Q_USEDHI    52
204
#define VIRTIO_PCI_COMMON_Q_NDATA    56
205
#define VIRTIO_PCI_COMMON_Q_RESET    58
206
+#define VIRTIO_PCI_COMMON_ADM_Q_IDX    60
207
+#define VIRTIO_PCI_COMMON_ADM_Q_NUM    62
208
209
#endif /* VIRTIO_PCI_NO_MODERN */
210
211
+/* Admin command status. */
212
+#define VIRTIO_ADMIN_STATUS_OK        0
213
+
214
+/* Admin command opcode. */
215
+#define VIRTIO_ADMIN_CMD_LIST_QUERY    0x0
216
+#define VIRTIO_ADMIN_CMD_LIST_USE    0x1
217
+
218
+/* Admin command group type. */
219
+#define VIRTIO_ADMIN_GROUP_TYPE_SRIOV    0x1
220
+
221
+/* Transitional device admin command. */
222
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE    0x2
223
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ        0x3
224
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE        0x4
225
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ        0x5
226
+#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO        0x6
227
+
228
+struct QEMU_PACKED virtio_admin_cmd_hdr {
229
+    uint16_t opcode;
230
+    /*
231
+     * 1 - SR-IOV
232
+     * 2-65535 - reserved
233
+     */
234
+    uint16_t group_type;
235
+    /* Unused, reserved for future extensions. */
236
+    uint8_t reserved1[12];
237
+    uint64_t group_member_id;
238
+};
239
+
240
+struct QEMU_PACKED virtio_admin_cmd_status {
241
+    uint16_t status;
242
+    uint16_t status_qualifier;
243
+    /* Unused, reserved for future extensions. */
244
+    uint8_t reserved2[4];
245
+};
246
+
247
+struct QEMU_PACKED virtio_admin_cmd_legacy_wr_data {
248
+    uint8_t offset; /* Starting offset of the register(s) to write. */
249
+    uint8_t reserved[7];
250
+    uint8_t registers[];
251
+};
252
+
253
+struct QEMU_PACKED virtio_admin_cmd_legacy_rd_data {
254
+    uint8_t offset; /* Starting offset of the register(s) to read. */
255
+};
256
+
257
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
258
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
259
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
260
+
261
+#define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
262
+
263
+struct QEMU_PACKED virtio_admin_cmd_notify_info_data {
264
+    uint8_t flags; /* 0 = end of list, 1 = owner device, 2 = member device */
265
+    uint8_t bar; /* BAR of the member or the owner device */
266
+    uint8_t padding[6];
267
+    uint64_t offset; /* Offset within bar. */
268
+};
269
+
270
+struct virtio_admin_cmd_notify_info_result {
271
+    struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
272
+};
273
+
274
#endif
275
diff --git a/include/standard-headers/linux/virtio_pmem.h b/include/standard-headers/linux/virtio_pmem.h
276
index XXXXXXX..XXXXXXX 100644
277
--- a/include/standard-headers/linux/virtio_pmem.h
278
+++ b/include/standard-headers/linux/virtio_pmem.h
279
@@ -XXX,XX +XXX,XX @@
280
#include "standard-headers/linux/virtio_ids.h"
281
#include "standard-headers/linux/virtio_config.h"
282
283
+/* Feature bits */
284
+/* guest physical address range will be indicated as shared memory region 0 */
285
+#define VIRTIO_PMEM_F_SHMEM_REGION 0
286
+
287
+/* shmid of the shared memory region corresponding to the pmem */
288
+#define VIRTIO_PMEM_SHMEM_REGION_ID 0
289
+
290
struct virtio_pmem_config {
291
    uint64_t start;
292
    uint64_t size;
293
diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h
294
index XXXXXXX..XXXXXXX 100644
295
--- a/linux-headers/asm-generic/unistd.h
296
+++ b/linux-headers/asm-generic/unistd.h
297
@@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_futex_wait, sys_futex_wait)
298
#define __NR_futex_requeue 456
299
__SYSCALL(__NR_futex_requeue, sys_futex_requeue)
300
301
+#define __NR_statmount 457
302
+__SYSCALL(__NR_statmount, sys_statmount)
303
+
304
+#define __NR_listmount 458
305
+__SYSCALL(__NR_listmount, sys_listmount)
306
+
307
+#define __NR_lsm_get_self_attr 459
308
+__SYSCALL(__NR_lsm_get_self_attr, sys_lsm_get_self_attr)
309
+#define __NR_lsm_set_self_attr 460
310
+__SYSCALL(__NR_lsm_set_self_attr, sys_lsm_set_self_attr)
311
+#define __NR_lsm_list_modules 461
312
+__SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)
313
+
314
#undef __NR_syscalls
315
-#define __NR_syscalls 457
316
+#define __NR_syscalls 462
317
318
/*
319
* 32 bit systems traditionally used different
320
diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h
321
index XXXXXXX..XXXXXXX 100644
322
--- a/linux-headers/asm-mips/mman.h
323
+++ b/linux-headers/asm-mips/mman.h
324
@@ -XXX,XX +XXX,XX @@
325
#define MADV_HUGEPAGE    14        /* Worth backing with hugepages */
326
#define MADV_NOHUGEPAGE 15        /* Not worth backing with hugepages */
327
328
-#define MADV_DONTDUMP    16        /* Explicity exclude from the core dump,
329
+#define MADV_DONTDUMP    16        /* Explicitly exclude from core dump,
330
                     overrides the coredump filter bits */
331
#define MADV_DODUMP    17        /* Clear the MADV_NODUMP flag */
332
333
diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h
334
index XXXXXXX..XXXXXXX 100644
335
--- a/linux-headers/asm-mips/unistd_n32.h
336
+++ b/linux-headers/asm-mips/unistd_n32.h
337
@@ -XXX,XX +XXX,XX @@
338
#define __NR_futex_wake (__NR_Linux + 454)
339
#define __NR_futex_wait (__NR_Linux + 455)
340
#define __NR_futex_requeue (__NR_Linux + 456)
341
+#define __NR_statmount (__NR_Linux + 457)
342
+#define __NR_listmount (__NR_Linux + 458)
343
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
344
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
345
+#define __NR_lsm_list_modules (__NR_Linux + 461)
346
347
#endif /* _ASM_UNISTD_N32_H */
348
diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h
349
index XXXXXXX..XXXXXXX 100644
350
--- a/linux-headers/asm-mips/unistd_n64.h
351
+++ b/linux-headers/asm-mips/unistd_n64.h
352
@@ -XXX,XX +XXX,XX @@
353
#define __NR_futex_wake (__NR_Linux + 454)
354
#define __NR_futex_wait (__NR_Linux + 455)
355
#define __NR_futex_requeue (__NR_Linux + 456)
356
+#define __NR_statmount (__NR_Linux + 457)
357
+#define __NR_listmount (__NR_Linux + 458)
358
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
359
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
360
+#define __NR_lsm_list_modules (__NR_Linux + 461)
361
362
#endif /* _ASM_UNISTD_N64_H */
363
diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h
364
index XXXXXXX..XXXXXXX 100644
365
--- a/linux-headers/asm-mips/unistd_o32.h
366
+++ b/linux-headers/asm-mips/unistd_o32.h
367
@@ -XXX,XX +XXX,XX @@
368
#define __NR_futex_wake (__NR_Linux + 454)
369
#define __NR_futex_wait (__NR_Linux + 455)
370
#define __NR_futex_requeue (__NR_Linux + 456)
371
+#define __NR_statmount (__NR_Linux + 457)
372
+#define __NR_listmount (__NR_Linux + 458)
373
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
374
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
375
+#define __NR_lsm_list_modules (__NR_Linux + 461)
376
377
#endif /* _ASM_UNISTD_O32_H */
378
diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h
379
index XXXXXXX..XXXXXXX 100644
380
--- a/linux-headers/asm-powerpc/unistd_32.h
381
+++ b/linux-headers/asm-powerpc/unistd_32.h
382
@@ -XXX,XX +XXX,XX @@
383
#define __NR_futex_wake 454
384
#define __NR_futex_wait 455
385
#define __NR_futex_requeue 456
386
+#define __NR_statmount 457
387
+#define __NR_listmount 458
388
+#define __NR_lsm_get_self_attr 459
389
+#define __NR_lsm_set_self_attr 460
390
+#define __NR_lsm_list_modules 461
391
392
393
#endif /* _ASM_UNISTD_32_H */
394
diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h
395
index XXXXXXX..XXXXXXX 100644
396
--- a/linux-headers/asm-powerpc/unistd_64.h
397
+++ b/linux-headers/asm-powerpc/unistd_64.h
398
@@ -XXX,XX +XXX,XX @@
399
#define __NR_futex_wake 454
400
#define __NR_futex_wait 455
401
#define __NR_futex_requeue 456
402
+#define __NR_statmount 457
403
+#define __NR_listmount 458
404
+#define __NR_lsm_get_self_attr 459
405
+#define __NR_lsm_set_self_attr 460
406
+#define __NR_lsm_list_modules 461
407
408
409
#endif /* _ASM_UNISTD_64_H */
410
diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
411
index XXXXXXX..XXXXXXX 100644
412
--- a/linux-headers/asm-riscv/kvm.h
413
+++ b/linux-headers/asm-riscv/kvm.h
414
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_ISA_EXT_ID {
415
    KVM_RISCV_ISA_EXT_ZIHPM,
416
    KVM_RISCV_ISA_EXT_SMSTATEEN,
417
    KVM_RISCV_ISA_EXT_ZICOND,
418
+    KVM_RISCV_ISA_EXT_ZBC,
419
+    KVM_RISCV_ISA_EXT_ZBKB,
420
+    KVM_RISCV_ISA_EXT_ZBKC,
421
+    KVM_RISCV_ISA_EXT_ZBKX,
422
+    KVM_RISCV_ISA_EXT_ZKND,
423
+    KVM_RISCV_ISA_EXT_ZKNE,
424
+    KVM_RISCV_ISA_EXT_ZKNH,
425
+    KVM_RISCV_ISA_EXT_ZKR,
426
+    KVM_RISCV_ISA_EXT_ZKSED,
427
+    KVM_RISCV_ISA_EXT_ZKSH,
428
+    KVM_RISCV_ISA_EXT_ZKT,
429
+    KVM_RISCV_ISA_EXT_ZVBB,
430
+    KVM_RISCV_ISA_EXT_ZVBC,
431
+    KVM_RISCV_ISA_EXT_ZVKB,
432
+    KVM_RISCV_ISA_EXT_ZVKG,
433
+    KVM_RISCV_ISA_EXT_ZVKNED,
434
+    KVM_RISCV_ISA_EXT_ZVKNHA,
435
+    KVM_RISCV_ISA_EXT_ZVKNHB,
436
+    KVM_RISCV_ISA_EXT_ZVKSED,
437
+    KVM_RISCV_ISA_EXT_ZVKSH,
438
+    KVM_RISCV_ISA_EXT_ZVKT,
439
+    KVM_RISCV_ISA_EXT_ZFH,
440
+    KVM_RISCV_ISA_EXT_ZFHMIN,
441
+    KVM_RISCV_ISA_EXT_ZIHINTNTL,
442
+    KVM_RISCV_ISA_EXT_ZVFH,
443
+    KVM_RISCV_ISA_EXT_ZVFHMIN,
444
+    KVM_RISCV_ISA_EXT_ZFA,
445
    KVM_RISCV_ISA_EXT_MAX,
446
};
447
448
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_SBI_EXT_ID {
449
    KVM_RISCV_SBI_EXT_EXPERIMENTAL,
450
    KVM_RISCV_SBI_EXT_VENDOR,
451
    KVM_RISCV_SBI_EXT_DBCN,
452
+    KVM_RISCV_SBI_EXT_STA,
453
    KVM_RISCV_SBI_EXT_MAX,
454
};
455
456
+/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
457
+struct kvm_riscv_sbi_sta {
458
+    unsigned long shmem_lo;
459
+    unsigned long shmem_hi;
460
+};
461
+
462
/* Possible states for kvm_riscv_timer */
463
#define KVM_RISCV_TIMER_STATE_OFF    0
464
#define KVM_RISCV_TIMER_STATE_ON    1
465
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_SBI_EXT_ID {
466
#define KVM_REG_RISCV_VECTOR_REG(n)    \
467
        ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
468
469
+/* Registers for specific SBI extensions are mapped as type 10 */
470
+#define KVM_REG_RISCV_SBI_STATE        (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
471
+#define KVM_REG_RISCV_SBI_STA        (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
472
+#define KVM_REG_RISCV_SBI_STA_REG(name)        \
473
+        (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
474
+
475
/* Device Control API: RISC-V AIA */
476
#define KVM_DEV_RISCV_APLIC_ALIGN        0x1000
477
#define KVM_DEV_RISCV_APLIC_SIZE        0x4000
478
diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h
479
index XXXXXXX..XXXXXXX 100644
480
--- a/linux-headers/asm-s390/unistd_32.h
481
+++ b/linux-headers/asm-s390/unistd_32.h
482
@@ -XXX,XX +XXX,XX @@
483
#define __NR_futex_wake 454
484
#define __NR_futex_wait 455
485
#define __NR_futex_requeue 456
486
+#define __NR_statmount 457
487
+#define __NR_listmount 458
488
+#define __NR_lsm_get_self_attr 459
489
+#define __NR_lsm_set_self_attr 460
490
+#define __NR_lsm_list_modules 461
491
492
#endif /* _ASM_S390_UNISTD_32_H */
493
diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h
494
index XXXXXXX..XXXXXXX 100644
495
--- a/linux-headers/asm-s390/unistd_64.h
496
+++ b/linux-headers/asm-s390/unistd_64.h
497
@@ -XXX,XX +XXX,XX @@
498
#define __NR_futex_wake 454
499
#define __NR_futex_wait 455
500
#define __NR_futex_requeue 456
501
+#define __NR_statmount 457
502
+#define __NR_listmount 458
503
+#define __NR_lsm_get_self_attr 459
504
+#define __NR_lsm_set_self_attr 460
505
+#define __NR_lsm_list_modules 461
506
507
#endif /* _ASM_S390_UNISTD_64_H */
508
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
509
index XXXXXXX..XXXXXXX 100644
510
--- a/linux-headers/asm-x86/kvm.h
511
+++ b/linux-headers/asm-x86/kvm.h
512
@@ -XXX,XX +XXX,XX @@ struct kvm_pmu_event_filter {
513
/* x86-specific KVM_EXIT_HYPERCALL flags. */
514
#define KVM_EXIT_HYPERCALL_LONG_MODE    BIT(0)
515
516
+#define KVM_X86_DEFAULT_VM    0
517
+#define KVM_X86_SW_PROTECTED_VM    1
518
+
519
#endif /* _ASM_X86_KVM_H */
520
diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h
521
index XXXXXXX..XXXXXXX 100644
522
--- a/linux-headers/asm-x86/unistd_32.h
523
+++ b/linux-headers/asm-x86/unistd_32.h
524
@@ -XXX,XX +XXX,XX @@
525
#define __NR_futex_wake 454
526
#define __NR_futex_wait 455
527
#define __NR_futex_requeue 456
528
+#define __NR_statmount 457
529
+#define __NR_listmount 458
530
+#define __NR_lsm_get_self_attr 459
531
+#define __NR_lsm_set_self_attr 460
532
+#define __NR_lsm_list_modules 461
533
534
535
#endif /* _ASM_UNISTD_32_H */
536
diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h
537
index XXXXXXX..XXXXXXX 100644
538
--- a/linux-headers/asm-x86/unistd_64.h
539
+++ b/linux-headers/asm-x86/unistd_64.h
540
@@ -XXX,XX +XXX,XX @@
541
#define __NR_futex_wake 454
542
#define __NR_futex_wait 455
543
#define __NR_futex_requeue 456
544
+#define __NR_statmount 457
545
+#define __NR_listmount 458
546
+#define __NR_lsm_get_self_attr 459
547
+#define __NR_lsm_set_self_attr 460
548
+#define __NR_lsm_list_modules 461
549
550
551
#endif /* _ASM_UNISTD_64_H */
552
diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h
553
index XXXXXXX..XXXXXXX 100644
554
--- a/linux-headers/asm-x86/unistd_x32.h
555
+++ b/linux-headers/asm-x86/unistd_x32.h
556
@@ -XXX,XX +XXX,XX @@
557
#define __NR_futex_wake (__X32_SYSCALL_BIT + 454)
558
#define __NR_futex_wait (__X32_SYSCALL_BIT + 455)
559
#define __NR_futex_requeue (__X32_SYSCALL_BIT + 456)
560
+#define __NR_statmount (__X32_SYSCALL_BIT + 457)
561
+#define __NR_listmount (__X32_SYSCALL_BIT + 458)
562
+#define __NR_lsm_get_self_attr (__X32_SYSCALL_BIT + 459)
563
+#define __NR_lsm_set_self_attr (__X32_SYSCALL_BIT + 460)
564
+#define __NR_lsm_list_modules (__X32_SYSCALL_BIT + 461)
565
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
566
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
567
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
568
diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
569
index XXXXXXX..XXXXXXX 100644
570
--- a/linux-headers/linux/iommufd.h
571
+++ b/linux-headers/linux/iommufd.h
572
@@ -XXX,XX +XXX,XX @@ enum {
573
    IOMMUFD_CMD_GET_HW_INFO,
574
    IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING,
575
    IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP,
576
+    IOMMUFD_CMD_HWPT_INVALIDATE,
577
};
578
579
/**
580
@@ -XXX,XX +XXX,XX @@ struct iommu_hwpt_get_dirty_bitmap {
581
#define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \
582
                    IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP)
583
584
+/**
585
+ * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
586
+ * Data Type
587
+ * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
588
+ */
589
+enum iommu_hwpt_invalidate_data_type {
590
+    IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
591
+};
592
+
593
+/**
594
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
595
+ * stage-1 cache invalidation
596
+ * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
597
+ * to all-levels page structure cache or just
598
+ * the leaf PTE cache.
599
+ */
600
+enum iommu_hwpt_vtd_s1_invalidate_flags {
601
+    IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
602
+};
603
+
604
+/**
605
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
606
+ * (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
607
+ * @addr: The start address of the range to be invalidated. It needs to
608
+ * be 4KB aligned.
609
+ * @npages: Number of contiguous 4K pages to be invalidated.
610
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
611
+ * @__reserved: Must be 0
612
+ *
613
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
614
+ * invalidation in nested translation. Userspace uses this structure to
615
+ * tell the impacted cache scope after modifying the stage-1 page table.
616
+ *
617
+ * Invalidating all the caches related to the page table by setting @addr
618
+ * to be 0 and @npages to be U64_MAX.
619
+ *
620
+ * The device TLB will be invalidated automatically if ATS is enabled.
621
+ */
622
+struct iommu_hwpt_vtd_s1_invalidate {
623
+    __aligned_u64 addr;
624
+    __aligned_u64 npages;
625
+    __u32 flags;
626
+    __u32 __reserved;
627
+};
628
+
629
+/**
630
+ * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
631
+ * @size: sizeof(struct iommu_hwpt_invalidate)
632
+ * @hwpt_id: ID of a nested HWPT for cache invalidation
633
+ * @data_uptr: User pointer to an array of driver-specific cache invalidation
634
+ * data.
635
+ * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data
636
+ * type of all the entries in the invalidation request array. It
637
+ * should be a type supported by the hwpt pointed by @hwpt_id.
638
+ * @entry_len: Length (in bytes) of a request entry in the request array
639
+ * @entry_num: Input the number of cache invalidation requests in the array.
640
+ * Output the number of requests successfully handled by kernel.
641
+ * @__reserved: Must be 0.
642
+ *
643
+ * Invalidate the iommu cache for user-managed page table. Modifications on a
644
+ * user-managed page table should be followed by this operation to sync cache.
645
+ * Each ioctl can support one or more cache invalidation requests in the array
646
+ * that has a total size of @entry_len * @entry_num.
647
+ *
648
+ * An empty invalidation request array by setting @entry_num==0 is allowed, and
649
+ * @entry_len and @data_uptr would be ignored in this case. This can be used to
650
+ * check if the given @data_type is supported or not by kernel.
651
+ */
652
+struct iommu_hwpt_invalidate {
653
+    __u32 size;
654
+    __u32 hwpt_id;
655
+    __aligned_u64 data_uptr;
656
+    __u32 data_type;
657
+    __u32 entry_len;
658
+    __u32 entry_num;
659
+    __u32 __reserved;
660
+};
661
+#define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE)
662
#endif
663
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
664
index XXXXXXX..XXXXXXX 100644
665
--- a/linux-headers/linux/kvm.h
666
+++ b/linux-headers/linux/kvm.h
667
@@ -XXX,XX +XXX,XX @@
668
669
#define KVM_API_VERSION 12
670
671
-/* *** Deprecated interfaces *** */
672
-
673
-#define KVM_TRC_SHIFT 16
674
-
675
-#define KVM_TRC_ENTRYEXIT (1 << KVM_TRC_SHIFT)
676
-#define KVM_TRC_HANDLER (1 << (KVM_TRC_SHIFT + 1))
677
-
678
-#define KVM_TRC_VMENTRY (KVM_TRC_ENTRYEXIT + 0x01)
679
-#define KVM_TRC_VMEXIT (KVM_TRC_ENTRYEXIT + 0x02)
680
-#define KVM_TRC_PAGE_FAULT (KVM_TRC_HANDLER + 0x01)
681
-
682
-#define KVM_TRC_HEAD_SIZE 12
683
-#define KVM_TRC_CYCLE_SIZE 8
684
-#define KVM_TRC_EXTRA_MAX 7
685
-
686
-#define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02)
687
-#define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03)
688
-#define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04)
689
-#define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05)
690
-#define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06)
691
-#define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07)
692
-#define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08)
693
-#define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09)
694
-#define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A)
695
-#define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B)
696
-#define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C)
697
-#define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D)
698
-#define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E)
699
-#define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F)
700
-#define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10)
701
-#define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11)
702
-#define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12)
703
-#define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13)
704
-#define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14)
705
-#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15)
706
-#define KVM_TRC_GTLB_WRITE (KVM_TRC_HANDLER + 0x16)
707
-#define KVM_TRC_STLB_WRITE (KVM_TRC_HANDLER + 0x17)
708
-#define KVM_TRC_STLB_INVAL (KVM_TRC_HANDLER + 0x18)
709
-#define KVM_TRC_PPC_INSTR (KVM_TRC_HANDLER + 0x19)
710
-
711
-struct kvm_user_trace_setup {
712
-    __u32 buf_size;
713
-    __u32 buf_nr;
714
-};
715
-
716
-#define __KVM_DEPRECATED_MAIN_W_0x06 \
717
-    _IOW(KVMIO, 0x06, struct kvm_user_trace_setup)
718
-#define __KVM_DEPRECATED_MAIN_0x07 _IO(KVMIO, 0x07)
719
-#define __KVM_DEPRECATED_MAIN_0x08 _IO(KVMIO, 0x08)
720
-
721
-#define __KVM_DEPRECATED_VM_R_0x70 _IOR(KVMIO, 0x70, struct kvm_assigned_irq)
722
-
723
-struct kvm_breakpoint {
724
-    __u32 enabled;
725
-    __u32 padding;
726
-    __u64 address;
727
-};
728
-
729
-struct kvm_debug_guest {
730
-    __u32 enabled;
731
-    __u32 pad;
732
-    struct kvm_breakpoint breakpoints[4];
733
-    __u32 singlestep;
734
-};
735
-
736
-#define __KVM_DEPRECATED_VCPU_W_0x87 _IOW(KVMIO, 0x87, struct kvm_debug_guest)
737
-
738
-/* *** End of deprecated interfaces *** */
739
-
740
-
741
/* for KVM_SET_USER_MEMORY_REGION */
742
struct kvm_userspace_memory_region {
743
    __u32 slot;
744
@@ -XXX,XX +XXX,XX @@ struct kvm_userspace_memory_region {
745
    __u64 userspace_addr; /* start of the userspace allocated memory */
746
};
747
748
+/* for KVM_SET_USER_MEMORY_REGION2 */
749
+struct kvm_userspace_memory_region2 {
750
+    __u32 slot;
751
+    __u32 flags;
752
+    __u64 guest_phys_addr;
753
+    __u64 memory_size;
754
+    __u64 userspace_addr;
755
+    __u64 guest_memfd_offset;
756
+    __u32 guest_memfd;
757
+    __u32 pad1;
758
+    __u64 pad2[14];
759
+};
760
+
761
/*
762
* The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
763
* userspace, other bits are reserved for kvm internal use which are defined
764
@@ -XXX,XX +XXX,XX @@ struct kvm_userspace_memory_region {
765
*/
766
#define KVM_MEM_LOG_DIRTY_PAGES    (1UL << 0)
767
#define KVM_MEM_READONLY    (1UL << 1)
768
+#define KVM_MEM_GUEST_MEMFD    (1UL << 2)
769
770
/* for KVM_IRQ_LINE */
771
struct kvm_irq_level {
772
@@ -XXX,XX +XXX,XX @@ struct kvm_xen_exit {
773
#define KVM_EXIT_RISCV_CSR 36
774
#define KVM_EXIT_NOTIFY 37
775
#define KVM_EXIT_LOONGARCH_IOCSR 38
776
+#define KVM_EXIT_MEMORY_FAULT 39
777
778
/* For KVM_EXIT_INTERNAL_ERROR */
779
/* Emulate instruction failed. */
780
@@ -XXX,XX +XXX,XX @@ struct kvm_run {
781
#define KVM_NOTIFY_CONTEXT_INVALID    (1 << 0)
782
            __u32 flags;
783
        } notify;
784
+        /* KVM_EXIT_MEMORY_FAULT */
785
+        struct {
786
+#define KVM_MEMORY_EXIT_FLAG_PRIVATE    (1ULL << 3)
787
+            __u64 flags;
788
+            __u64 gpa;
789
+            __u64 size;
790
+        } memory_fault;
791
        /* Fix the size of the union. */
792
        char padding[256];
793
    };
794
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
795
*/
796
#define KVM_GET_VCPU_MMAP_SIZE _IO(KVMIO, 0x04) /* in bytes */
797
#define KVM_GET_SUPPORTED_CPUID _IOWR(KVMIO, 0x05, struct kvm_cpuid2)
798
-#define KVM_TRACE_ENABLE __KVM_DEPRECATED_MAIN_W_0x06
799
-#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
800
-#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
801
#define KVM_GET_EMULATED_CPUID     _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
802
#define KVM_GET_MSR_FEATURE_INDEX_LIST _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
803
804
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
805
#define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
806
#define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
807
#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
808
+#define KVM_CAP_USER_MEMORY2 231
809
+#define KVM_CAP_MEMORY_FAULT_INFO 232
810
+#define KVM_CAP_MEMORY_ATTRIBUTES 233
811
+#define KVM_CAP_GUEST_MEMFD 234
812
+#define KVM_CAP_VM_TYPES 235
813
814
#ifdef KVM_CAP_IRQ_ROUTING
815
816
@@ -XXX,XX +XXX,XX @@ struct kvm_x86_mce {
817
#define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL    (1 << 4)
818
#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND        (1 << 5)
819
#define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG    (1 << 6)
820
+#define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE    (1 << 7)
821
822
struct kvm_xen_hvm_config {
823
    __u32 flags;
824
@@ -XXX,XX +XXX,XX @@ struct kvm_vfio_spapr_tce {
825
                    struct kvm_userspace_memory_region)
826
#define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47)
827
#define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64)
828
+#define KVM_SET_USER_MEMORY_REGION2 _IOW(KVMIO, 0x49, \
829
+                     struct kvm_userspace_memory_region2)
830
831
/* enable ucontrol for s390 */
832
struct kvm_s390_ucas_mapping {
833
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
834
            _IOW(KVMIO, 0x67, struct kvm_coalesced_mmio_zone)
835
#define KVM_UNREGISTER_COALESCED_MMIO \
836
            _IOW(KVMIO, 0x68, struct kvm_coalesced_mmio_zone)
837
-#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
838
-                 struct kvm_assigned_pci_dev)
839
#define KVM_SET_GSI_ROUTING _IOW(KVMIO, 0x6a, struct kvm_irq_routing)
840
-/* deprecated, replaced by KVM_ASSIGN_DEV_IRQ */
841
-#define KVM_ASSIGN_IRQ __KVM_DEPRECATED_VM_R_0x70
842
-#define KVM_ASSIGN_DEV_IRQ _IOW(KVMIO, 0x70, struct kvm_assigned_irq)
843
#define KVM_REINJECT_CONTROL _IO(KVMIO, 0x71)
844
-#define KVM_DEASSIGN_PCI_DEVICE _IOW(KVMIO, 0x72, \
845
-                 struct kvm_assigned_pci_dev)
846
-#define KVM_ASSIGN_SET_MSIX_NR _IOW(KVMIO, 0x73, \
847
-                 struct kvm_assigned_msix_nr)
848
-#define KVM_ASSIGN_SET_MSIX_ENTRY _IOW(KVMIO, 0x74, \
849
-                 struct kvm_assigned_msix_entry)
850
-#define KVM_DEASSIGN_DEV_IRQ _IOW(KVMIO, 0x75, struct kvm_assigned_irq)
851
#define KVM_IRQFD _IOW(KVMIO, 0x76, struct kvm_irqfd)
852
#define KVM_CREATE_PIT2         _IOW(KVMIO, 0x77, struct kvm_pit_config)
853
#define KVM_SET_BOOT_CPU_ID _IO(KVMIO, 0x78)
854
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
855
* KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */
856
#define KVM_SET_TSC_KHZ _IO(KVMIO, 0xa2)
857
#define KVM_GET_TSC_KHZ _IO(KVMIO, 0xa3)
858
-/* Available with KVM_CAP_PCI_2_3 */
859
-#define KVM_ASSIGN_SET_INTX_MASK _IOW(KVMIO, 0xa4, \
860
-                 struct kvm_assigned_pci_dev)
861
/* Available with KVM_CAP_SIGNAL_MSI */
862
#define KVM_SIGNAL_MSI _IOW(KVMIO, 0xa5, struct kvm_msi)
863
/* Available with KVM_CAP_PPC_GET_SMMU_INFO */
864
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
865
#define KVM_SET_SREGS _IOW(KVMIO, 0x84, struct kvm_sregs)
866
#define KVM_TRANSLATE _IOWR(KVMIO, 0x85, struct kvm_translation)
867
#define KVM_INTERRUPT _IOW(KVMIO, 0x86, struct kvm_interrupt)
868
-/* KVM_DEBUG_GUEST is no longer supported, use KVM_SET_GUEST_DEBUG instead */
869
-#define KVM_DEBUG_GUEST __KVM_DEPRECATED_VCPU_W_0x87
870
#define KVM_GET_MSRS _IOWR(KVMIO, 0x88, struct kvm_msrs)
871
#define KVM_SET_MSRS _IOW(KVMIO, 0x89, struct kvm_msrs)
872
#define KVM_SET_CPUID _IOW(KVMIO, 0x8a, struct kvm_cpuid)
873
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_zpci_op {
874
/* flags for kvm_s390_zpci_op->u.reg_aen.flags */
875
#define KVM_S390_ZPCIOP_REGAEN_HOST (1 << 0)
876
877
+/* Available with KVM_CAP_MEMORY_ATTRIBUTES */
878
+#define KVM_SET_MEMORY_ATTRIBUTES _IOW(KVMIO, 0xd2, struct kvm_memory_attributes)
879
+
880
+struct kvm_memory_attributes {
881
+    __u64 address;
882
+    __u64 size;
883
+    __u64 attributes;
884
+    __u64 flags;
885
+};
886
+
887
+#define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3)
888
+
889
+#define KVM_CREATE_GUEST_MEMFD    _IOWR(KVMIO, 0xd4, struct kvm_create_guest_memfd)
890
+
891
+struct kvm_create_guest_memfd {
892
+    __u64 size;
893
+    __u64 flags;
894
+    __u64 reserved[6];
895
+};
896
+
897
#endif /* __LINUX_KVM_H */
898
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
899
index XXXXXXX..XXXXXXX 100644
900
--- a/linux-headers/linux/userfaultfd.h
901
+++ b/linux-headers/linux/userfaultfd.h
902
@@ -XXX,XX +XXX,XX @@
903
             UFFD_FEATURE_WP_HUGETLBFS_SHMEM |    \
904
             UFFD_FEATURE_WP_UNPOPULATED |    \
905
             UFFD_FEATURE_POISON |        \
906
-             UFFD_FEATURE_WP_ASYNC)
907
+             UFFD_FEATURE_WP_ASYNC |        \
908
+             UFFD_FEATURE_MOVE)
909
#define UFFD_API_IOCTLS                \
910
    ((__u64)1 << _UFFDIO_REGISTER |        \
911
     (__u64)1 << _UFFDIO_UNREGISTER |    \
912
@@ -XXX,XX +XXX,XX @@
913
    ((__u64)1 << _UFFDIO_WAKE |        \
914
     (__u64)1 << _UFFDIO_COPY |        \
915
     (__u64)1 << _UFFDIO_ZEROPAGE |        \
916
+     (__u64)1 << _UFFDIO_MOVE |        \
917
     (__u64)1 << _UFFDIO_WRITEPROTECT |    \
918
     (__u64)1 << _UFFDIO_CONTINUE |        \
919
     (__u64)1 << _UFFDIO_POISON)
920
@@ -XXX,XX +XXX,XX @@
921
#define _UFFDIO_WAKE            (0x02)
922
#define _UFFDIO_COPY            (0x03)
923
#define _UFFDIO_ZEROPAGE        (0x04)
924
+#define _UFFDIO_MOVE            (0x05)
925
#define _UFFDIO_WRITEPROTECT        (0x06)
926
#define _UFFDIO_CONTINUE        (0x07)
927
#define _UFFDIO_POISON            (0x08)
928
@@ -XXX,XX +XXX,XX @@
929
                 struct uffdio_copy)
930
#define UFFDIO_ZEROPAGE        _IOWR(UFFDIO, _UFFDIO_ZEROPAGE,    \
931
                 struct uffdio_zeropage)
932
+#define UFFDIO_MOVE        _IOWR(UFFDIO, _UFFDIO_MOVE,    \
933
+                 struct uffdio_move)
934
#define UFFDIO_WRITEPROTECT    _IOWR(UFFDIO, _UFFDIO_WRITEPROTECT, \
935
                 struct uffdio_writeprotect)
936
#define UFFDIO_CONTINUE        _IOWR(UFFDIO, _UFFDIO_CONTINUE,    \
937
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
938
     * asynchronous mode is supported in which the write fault is
939
     * automatically resolved and write-protection is un-set.
940
     * It implies UFFD_FEATURE_WP_UNPOPULATED.
941
+     *
942
+     * UFFD_FEATURE_MOVE indicates that the kernel supports moving an
943
+     * existing page contents from userspace.
944
     */
945
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
946
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
947
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
948
#define UFFD_FEATURE_WP_UNPOPULATED        (1<<13)
949
#define UFFD_FEATURE_POISON            (1<<14)
950
#define UFFD_FEATURE_WP_ASYNC            (1<<15)
951
+#define UFFD_FEATURE_MOVE            (1<<16)
952
    __u64 features;
953
954
    __u64 ioctls;
955
@@ -XXX,XX +XXX,XX @@ struct uffdio_poison {
956
    __s64 updated;
957
};
958
959
+struct uffdio_move {
960
+    __u64 dst;
961
+    __u64 src;
962
+    __u64 len;
963
+    /*
964
+     * Especially if used to atomically remove memory from the
965
+     * address space the wake on the dst range is not needed.
966
+     */
967
+#define UFFDIO_MOVE_MODE_DONTWAKE        ((__u64)1<<0)
968
+#define UFFDIO_MOVE_MODE_ALLOW_SRC_HOLES    ((__u64)1<<1)
969
+    __u64 mode;
970
+    /*
971
+     * "move" is written by the ioctl and must be at the end: the
972
+     * copy_from_user will not read the last 8 bytes.
973
+     */
974
+    __s64 move;
975
+};
976
+
977
/*
978
* Flags for the userfaultfd(2) system call itself.
979
*/
980
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
981
index XXXXXXX..XXXXXXX 100644
982
--- a/linux-headers/linux/vfio.h
983
+++ b/linux-headers/linux/vfio.h
984
@@ -XXX,XX +XXX,XX @@ enum vfio_device_mig_state {
985
    VFIO_DEVICE_STATE_RUNNING_P2P = 5,
986
    VFIO_DEVICE_STATE_PRE_COPY = 6,
987
    VFIO_DEVICE_STATE_PRE_COPY_P2P = 7,
988
+    VFIO_DEVICE_STATE_NR,
989
};
990
991
/**
992
--
993
2.44.0
diff view generated by jsdifflib
New patch
[PULL 25/34] target/riscv/kvm: update KVM exts to Linux 6.8
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The last KVM extensions added were back in 6.6. Sync them to Linux 6.8.
4
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-ID: <20240304134732.386590-3-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
target/riscv/kvm/kvm-cpu.c | 29 +++++++++++++++++++++++++++++
11
1 file changed, 29 insertions(+)
12
13
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/kvm/kvm-cpu.c
16
+++ b/target/riscv/kvm/kvm-cpu.c
17
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
18
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
19
KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
20
KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR),
21
+ KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND),
22
KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR),
23
KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI),
24
+ KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL),
25
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
26
KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
27
+ KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA),
28
+ KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH),
29
+ KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN),
30
KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA),
31
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
32
+ KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC),
33
+ KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB),
34
+ KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC),
35
+ KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX),
36
KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS),
37
+ KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
38
+ KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
39
+ KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
40
+ KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR),
41
+ KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED),
42
+ KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH),
43
+ KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT),
44
+ KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB),
45
+ KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC),
46
+ KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH),
47
+ KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN),
48
+ KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB),
49
+ KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG),
50
+ KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED),
51
+ KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA),
52
+ KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB),
53
+ KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED),
54
+ KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH),
55
+ KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT),
56
+ KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN),
57
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
58
KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
59
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
60
--
61
2.44.0
diff view generated by jsdifflib
New patch
[PULL 26/34] target/riscv: move ratified/frozen exts to non-experimental
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
smaia and ssaia were ratified in August 25th 2023 [1].
4
5
zvfh and zvfhmin were ratified in August 2nd 2023 [2].
6
7
zfbfmin and zvfbf(min|wma) are frozen and moved to public review since
8
Dec 16th 2023 [3].
9
10
zaamo and zalrsc are both marked as "Frozen" since January 24th 2024
11
[4].
12
13
[1] https://jira.riscv.org/browse/RVS-438
14
[2] https://jira.riscv.org/browse/RVS-871
15
[3] https://jira.riscv.org/browse/RVS-704
16
[4] https://jira.riscv.org/browse/RVS-1995
17
18
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
19
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
20
Message-ID: <20240301144053.265964-1-dbarboza@ventanamicro.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
23
target/riscv/cpu.c | 22 +++++++++-------------
24
1 file changed, 9 insertions(+), 13 deletions(-)
25
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.c
29
+++ b/target/riscv/cpu.c
30
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
31
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
32
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
33
MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
34
+ MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
35
+ MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
36
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
37
MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
38
+ MULTI_EXT_CFG_BOOL("zfbfmin", ext_zfbfmin, false),
39
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
40
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
41
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
42
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
43
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
44
+ MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
45
+ MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
46
+ MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
47
+ MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
48
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
49
50
+ MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
51
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
52
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
53
+ MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
54
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
55
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
56
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
57
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
58
59
/* These are experimental so mark with 'x-' */
60
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
61
- MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
62
- MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
63
-
64
- MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false),
65
- MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false),
66
-
67
- MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
68
- MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
69
-
70
- MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
71
- MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
72
- MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
73
-
74
DEFINE_PROP_END_OF_LIST(),
75
};
76
77
--
78
2.44.0
diff view generated by jsdifflib
New patch
[PULL 27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
1
From: Vadim Shakirov <vadim.shakirov@syntacore.com>
1
2
3
mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
4
by privileged spec
5
6
Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
9
Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu.h | 8 ++++----
13
target/riscv/machine.c | 16 ++++++++--------
14
2 files changed, 12 insertions(+), 12 deletions(-)
15
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
19
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
21
target_ulong hstatus;
22
target_ulong hedeleg;
23
uint64_t hideleg;
24
- target_ulong hcounteren;
25
+ uint32_t hcounteren;
26
target_ulong htval;
27
target_ulong htinst;
28
target_ulong hgatp;
29
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
30
*/
31
bool two_stage_indirect_lookup;
32
33
- target_ulong scounteren;
34
- target_ulong mcounteren;
35
+ uint32_t scounteren;
36
+ uint32_t mcounteren;
37
38
- target_ulong mcountinhibit;
39
+ uint32_t mcountinhibit;
40
41
/* PMU counter state */
42
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
43
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/machine.c
46
+++ b/target/riscv/machine.c
47
@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
48
49
static const VMStateDescription vmstate_hyper = {
50
.name = "cpu/hyper",
51
- .version_id = 3,
52
- .minimum_version_id = 3,
53
+ .version_id = 4,
54
+ .minimum_version_id = 4,
55
.needed = hyper_needed,
56
.fields = (const VMStateField[]) {
57
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
58
VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
59
VMSTATE_UINT64(env.hideleg, RISCVCPU),
60
- VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
61
+ VMSTATE_UINT32(env.hcounteren, RISCVCPU),
62
VMSTATE_UINTTL(env.htval, RISCVCPU),
63
VMSTATE_UINTTL(env.htinst, RISCVCPU),
64
VMSTATE_UINTTL(env.hgatp, RISCVCPU),
65
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_jvt = {
66
67
const VMStateDescription vmstate_riscv_cpu = {
68
.name = "cpu",
69
- .version_id = 9,
70
- .minimum_version_id = 9,
71
+ .version_id = 10,
72
+ .minimum_version_id = 10,
73
.post_load = riscv_cpu_post_load,
74
.fields = (const VMStateField[]) {
75
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
76
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
77
VMSTATE_UINTTL(env.mtval, RISCVCPU),
78
VMSTATE_UINTTL(env.miselect, RISCVCPU),
79
VMSTATE_UINTTL(env.siselect, RISCVCPU),
80
- VMSTATE_UINTTL(env.scounteren, RISCVCPU),
81
- VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
82
- VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
83
+ VMSTATE_UINT32(env.scounteren, RISCVCPU),
84
+ VMSTATE_UINT32(env.mcounteren, RISCVCPU),
85
+ VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
86
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
87
vmstate_pmu_ctr_state, PMUCTRState),
88
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
89
--
90
2.44.0
diff view generated by jsdifflib
New patch
[PULL 28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
While discussing a problem with how we're (not) setting vstart_eq_zero
4
Richard had the following to say w.r.t the conditional mark_vs_dirty()
5
calls on load/store functions [1]:
6
7
"I think it's required to have stores set dirty unconditionally, before
8
the operation.
9
10
Consider a store that traps on the 2nd element, leaving vstart = 2, and
11
exiting to the main loop via exception. The exception enters the kernel
12
page fault handler. The kernel may need to fault in the page for the
13
process, and in the meantime task switch.
14
15
If vs dirty is not already set, the kernel won't know to save vector
16
state on task switch."
17
18
Do a mark_vs_dirty() before both loads and stores.
19
20
[1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/
21
22
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
23
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-ID: <20240306171932.549549-2-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
target/riscv/insn_trans/trans_rvv.c.inc | 23 ++++++++---------------
30
1 file changed, 8 insertions(+), 15 deletions(-)
31
32
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_rvv.c.inc
35
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
37
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
38
}
39
40
+ mark_vs_dirty(s);
41
+
42
fn(dest, mask, base, tcg_env, desc);
43
44
if (!is_store && s->ztso) {
45
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
46
}
47
48
- if (!is_store) {
49
- mark_vs_dirty(s);
50
- }
51
-
52
gen_set_label(over);
53
return true;
54
}
55
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
56
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
57
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
58
59
- fn(dest, mask, base, stride, tcg_env, desc);
60
+ mark_vs_dirty(s);
61
62
- if (!is_store) {
63
- mark_vs_dirty(s);
64
- }
65
+ fn(dest, mask, base, stride, tcg_env, desc);
66
67
gen_set_label(over);
68
return true;
69
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
70
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
71
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
72
73
- fn(dest, mask, base, index, tcg_env, desc);
74
+ mark_vs_dirty(s);
75
76
- if (!is_store) {
77
- mark_vs_dirty(s);
78
- }
79
+ fn(dest, mask, base, index, tcg_env, desc);
80
81
gen_set_label(over);
82
return true;
83
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
84
base = get_gpr(s, rs1, EXT_NONE);
85
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
86
87
+ mark_vs_dirty(s);
88
+
89
fn(dest, base, tcg_env, desc);
90
91
- if (!is_store) {
92
- mark_vs_dirty(s);
93
- }
94
gen_set_label(over);
95
96
return true;
97
--
98
2.44.0
diff view generated by jsdifflib
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
[PULL 29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns
1
From: Jim Shu <cwshu@andestech.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
If PMP permission of any address has been changed by updating PMP entry,
3
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
4
flush all TLB pages to prevent from getting old permission.
4
bool is unused in some load/store functions that were changed. Remove it.
5
5
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
6
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
10
Message-ID: <20240306171932.549549-3-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
12
---
11
target/riscv/pmp.c | 4 ++++
13
target/riscv/insn_trans/trans_rvv.c.inc | 58 ++++++++++++-------------
12
1 file changed, 4 insertions(+)
14
1 file changed, 29 insertions(+), 29 deletions(-)
13
15
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/pmp.c
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
17
+++ b/target/riscv/pmp.c
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
18
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
19
#include "qapi/error.h"
21
20
#include "cpu.h"
22
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
21
#include "trace.h"
23
uint32_t data, gen_helper_ldst_stride *fn,
22
+#include "exec/exec-all.h"
24
- DisasContext *s, bool is_store)
23
25
+ DisasContext *s)
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
26
{
25
uint8_t val);
27
TCGv_ptr dest, mask;
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
28
TCGv base, stride;
27
cfg_val = (val >> 8 * i) & 0xff;
29
@@ -XXX,XX +XXX,XX @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
30
data = FIELD_DP32(data, VDATA, NF, a->nf);
31
data = FIELD_DP32(data, VDATA, VTA, s->vta);
32
data = FIELD_DP32(data, VDATA, VMA, s->vma);
33
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
34
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
35
}
36
37
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
38
@@ -XXX,XX +XXX,XX @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
39
return false;
29
}
40
}
30
+
41
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
42
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
32
+ tlb_flush(env_cpu(env));
43
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
33
}
44
}
34
45
35
46
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
47
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
48
49
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
50
uint32_t data, gen_helper_ldst_index *fn,
51
- DisasContext *s, bool is_store)
52
+ DisasContext *s)
53
{
54
TCGv_ptr dest, mask, index;
55
TCGv base;
56
@@ -XXX,XX +XXX,XX @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
57
data = FIELD_DP32(data, VDATA, NF, a->nf);
58
data = FIELD_DP32(data, VDATA, VTA, s->vta);
59
data = FIELD_DP32(data, VDATA, VMA, s->vma);
60
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
61
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
62
}
63
64
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
65
@@ -XXX,XX +XXX,XX @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
66
data = FIELD_DP32(data, VDATA, VM, a->vm);
67
data = FIELD_DP32(data, VDATA, LMUL, emul);
68
data = FIELD_DP32(data, VDATA, NF, a->nf);
69
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
70
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
71
}
72
73
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
74
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
75
76
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
77
uint32_t width, gen_helper_ldst_whole *fn,
78
- DisasContext *s, bool is_store)
79
+ DisasContext *s)
80
{
81
uint32_t evl = s->cfg_ptr->vlenb * nf / width;
82
TCGLabel *over = gen_new_label();
83
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
84
* load and store whole register instructions ignore vtype and vl setting.
85
* Thus, we don't need to check vill bit. (Section 7.9)
86
*/
87
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
88
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
89
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
90
{ \
91
if (require_rvv(s) && \
92
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
93
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
94
- gen_helper_##NAME, s, IS_STORE); \
95
+ gen_helper_##NAME, s); \
96
} \
97
return false; \
98
}
99
100
-GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
101
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
102
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
103
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
104
-GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
105
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
106
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
107
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
108
-GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
109
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
110
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
111
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
112
-GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
113
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
114
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
115
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
116
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
117
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
118
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
119
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
120
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
121
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
122
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
123
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
124
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
125
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
126
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
127
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
128
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
129
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
130
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
131
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
132
133
/*
134
* The vector whole register store instructions are encoded similar to
135
* unmasked unit-stride store of elements with EEW=8.
136
*/
137
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
138
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
139
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
140
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
141
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
142
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
143
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
144
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
145
146
/*
147
*** Vector Integer Arithmetic Instructions
36
--
148
--
37
2.30.1
149
2.44.0
38
150
39
151
diff view generated by jsdifflib
New patch
[PULL 30/34] target/riscv: Fix shift count overflow
1
From: "demin.han" <demin.han@starfivetech.com>
1
2
3
The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
4
and results in wrong vill.
5
6
Signed-off-by: demin.han <demin.han@starfivetech.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/vector_helper.c | 5 ++---
12
1 file changed, 2 insertions(+), 3 deletions(-)
13
14
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/vector_helper.c
17
+++ b/target/riscv/vector_helper.c
18
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
19
target_ulong reserved = s2 &
20
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
21
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
22
+ uint16_t vlen = cpu->cfg.vlenb << 3;
23
int8_t lmul;
24
25
if (vlmul & 4) {
26
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
27
* VLEN * LMUL >= SEW
28
* VLEN >> (8 - lmul) >= sew
29
* (vlenb << 3) >> (8 - lmul) >= sew
30
- * vlenb >> (8 - 3 - lmul) >= sew
31
*/
32
- if (vlmul == 4 ||
33
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
34
+ if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
35
vill = true;
36
}
37
}
38
--
39
2.44.0
diff view generated by jsdifflib
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
[PULL 31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
According to the specification the "field SPVP of hstatus controls the
3
The writes to setipnum_le register in APLIC MSI-mode have special
4
privilege level of the access" for the hypervisor virtual-machine load
4
consideration for level-triggered interrupts as-per section "4.9.2
5
and store instructions HLV, HLVX and HSV.
5
Special consideration for level-sensitive interrupt sources" of the
6
RISC-V AIA specification.
6
7
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
Particularly, the below text from the RISC-V specification defines
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
the behaviour of writes to setipnum_le for level-triggered interrupts:
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
10
11
"A second option is for the interrupt service routine to write the
12
APLIC’s source identity number for the interrupt to the domain’s
13
setipnum register just before exiting. This will cause the interrupt’s
14
pending bit to be set to one again if the source is still asserting
15
an interrupt, but not if the source is not asserting an interrupt."
16
17
Fix setipnum_le write emulation for APLIC MSI-mode by implementing
18
the above behaviour in riscv_aplic_set_pending() function.
19
20
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
21
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
22
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Message-ID: <20240306095722.463296-2-apatel@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
25
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
26
hw/intc/riscv_aplic.c | 20 ++++++++++++++++----
13
1 file changed, 14 insertions(+), 11 deletions(-)
27
1 file changed, 16 insertions(+), 4 deletions(-)
14
28
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
29
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
16
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
31
--- a/hw/intc/riscv_aplic.c
18
+++ b/target/riscv/cpu_helper.c
32
+++ b/hw/intc/riscv_aplic.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
33
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
20
use_background = true;
21
}
34
}
22
35
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
36
sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
24
+ /* MPRV does not affect the virtual-machine load/store
37
- if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
25
+ instructions, HLV, HLVX, and HSV. */
38
- ((!aplic->msimode || (aplic->msimode && !pending)) &&
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
39
- ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
40
- (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
41
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
42
return;
30
mode = get_field(env->mstatus, MSTATUS_MPP);
31
}
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
34
__func__, address, access_type, mmu_idx);
35
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
39
+ /* MPRV does not affect the virtual-machine load/store
40
+ instructions, HLV, HLVX, and HSV. */
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
47
+ two_stage_lookup = true;
48
}
49
}
43
}
50
44
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
45
+ if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
52
- access_type != MMU_INST_FETCH &&
46
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
47
+ if (!aplic->msimode || (aplic->msimode && !pending)) {
54
- get_field(env->mstatus, MSTATUS_MPV)) {
48
+ return;
55
- two_stage_lookup = true;
49
+ }
56
- }
50
+ if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
57
-
51
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
58
if (riscv_cpu_virt_enabled(env) ||
52
+ return;
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
53
+ }
60
access_type != MMU_INST_FETCH)) {
54
+ if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) &&
55
+ (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) {
56
+ return;
57
+ }
58
+ }
59
+
60
riscv_aplic_set_pending_raw(aplic, irq, pending);
61
}
62
61
--
63
--
62
2.30.1
64
2.44.0
63
65
64
66
diff view generated by jsdifflib
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
[PULL 32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
3
The reads to in_clrip[x] registers return rectified input values of the
4
the newest received byte. The rx_level variable is added to allow the use of
4
interrupt sources.
5
the existing OpenTitan driver libraries.
6
5
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
6
A rectified input value of an interrupt source is defined by the section
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
"4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
8
AIA specification as:
9
"rectified input value = (incoming wire value) XOR (source is inverted)"
10
11
Update the riscv_aplic_read_input_word() implementation to match the above.
12
13
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
14
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
15
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
16
Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
include/hw/char/ibex_uart.h | 4 ++++
19
hw/intc/riscv_aplic.c | 17 +++++++++++++++--
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
20
1 file changed, 15 insertions(+), 2 deletions(-)
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
21
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
22
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
24
--- a/hw/intc/riscv_aplic.c
19
+++ b/include/hw/char/ibex_uart.h
25
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
26
@@ -XXX,XX +XXX,XX @@ static bool is_kvm_aia(bool msimode)
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
27
static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
28
uint32_t word)
23
REG32(FIFO_STATUS, 0x20)
29
{
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
30
- uint32_t i, irq, ret = 0;
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
31
+ uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret = 0;
26
REG32(OVRD, 0x24)
32
27
REG32(VAL, 0x28)
33
for (i = 0; i < 32; i++) {
28
REG32(TIMEOUT_CTRL, 0x2c)
34
irq = word * 32 + i;
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
35
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
36
continue;
31
uint32_t tx_level;
37
}
32
38
33
+ uint32_t rx_level;
39
- ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
40
+ sourcecfg = aplic->sourcecfg[irq];
41
+ if (sourcecfg & APLIC_SOURCECFG_D) {
42
+ continue;
43
+ }
34
+
44
+
35
QEMUTimer *fifo_trigger_handle;
45
+ sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
36
uint64_t char_tx_time;
46
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
37
47
+ continue;
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
48
+ }
39
index XXXXXXX..XXXXXXX 100644
49
+
40
--- a/hw/char/ibex_uart.c
50
+ raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0;
41
+++ b/hw/char/ibex_uart.c
51
+ irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW ||
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
52
+ sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0;
43
{
53
+ ret |= (raw_input ^ irq_inverted) << i;
44
IbexUartState *s = opaque;
45
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
49
return 1;
50
}
54
}
51
55
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
56
return ret;
53
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
+ /* The RXFULL is set after receiving a single byte
57
+ * as the FIFO buffers are not yet implemented.
58
+ */
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
+ s->rx_level += 1;
61
62
if (size > rx_fifo_level) {
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
s->uart_timeout_ctrl = 0x00000000;
66
67
s->tx_level = 0;
68
+ s->rx_level = 0;
69
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
74
case R_RDATA:
75
retvalue = s->uart_rdata;
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
qemu_chr_fe_accept_input(&s->chr);
79
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ s->rx_level -= 1;
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ if (s->rx_level == 0) {
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
+ }
88
}
89
break;
90
case R_WDATA:
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
57
--
110
2.30.1
58
2.44.0
111
59
112
60
diff view generated by jsdifflib
[PULL 04/16] target/riscv: add log of PMP permission checking
[PULL 33/34] target/riscv: Fix privilege mode of G-stage translation for debugging
1
From: Jim Shu <cwshu@andestech.com>
1
From: Hiroaki Yamamoto <hrak1529@gmail.com>
2
2
3
Like MMU translation, add qemu log of PMP permission checking for
3
G-stage translation should be considered to be user-level access in
4
debugging.
4
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().
5
5
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
6
This fixes a bug that prevents gdb from reading memory while the VM is
7
running in VS-mode.
8
9
Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
11
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
13
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
14
target/riscv/cpu_helper.c | 2 +-
12
1 file changed, 12 insertions(+)
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
16
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
19
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
21
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
19
if (ret == TRANSLATE_SUCCESS) {
22
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
23
if (env->virt_enabled) {
21
size, access_type, mode);
24
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
22
+
25
- 0, mmu_idx, false, true, true)) {
23
+ qemu_log_mask(CPU_LOG_MMU,
26
+ 0, MMUIdx_U, false, true, true)) {
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
27
return -1;
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
26
+ __func__, pa, ret, prot_pmp, tlb_size);
27
+
28
prot &= prot_pmp;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
32
if (ret == TRANSLATE_SUCCESS) {
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
34
size, access_type, mode);
35
+
36
+ qemu_log_mask(CPU_LOG_MMU,
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
39
+ __func__, pa, ret, prot_pmp, tlb_size);
40
+
41
prot &= prot_pmp;
42
}
28
}
43
}
29
}
44
--
30
--
45
2.30.1
31
2.44.0
46
47
diff view generated by jsdifflib
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
[PULL 34/34] target/riscv: fix ACPI MCFG table
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Ilya Chugin <danger_mail@list.ru>
2
2
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
3
MCFG segments should point to PCI configuration range, not BAR MMIO.
4
been updated to use a register mapped at 0x4f000000 instead of a
5
GPIO to control whether eMMC or SD card is to be used. With this
6
support the same HSS image can be used for both eMMC and SD card
7
boot flow, while previously two different board configurations were
8
used. This is undocumented but one can take a look at the HSS code
9
HSS_MMCInit() in services/mmc/mmc_api.c.
10
4
11
With this commit, HSS image built from 2020.12 release boots again.
5
Signed-off-by: Ilya Chugin <danger_mail@list.ru>
12
6
Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and devices")
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
9
Message-ID: <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
11
---
18
include/hw/riscv/microchip_pfsoc.h | 1 +
12
hw/riscv/virt-acpi-build.c | 4 ++--
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
13
1 file changed, 2 insertions(+), 2 deletions(-)
20
2 files changed, 7 insertions(+)
21
14
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
15
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/riscv/microchip_pfsoc.h
17
--- a/hw/riscv/virt-acpi-build.c
25
+++ b/include/hw/riscv/microchip_pfsoc.h
18
+++ b/hw/riscv/virt-acpi-build.c
26
@@ -XXX,XX +XXX,XX @@ enum {
19
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
27
MICROCHIP_PFSOC_ENVM_DATA,
20
acpi_add_table(table_offsets, tables_blob);
28
MICROCHIP_PFSOC_QSPI_XIP,
21
{
29
MICROCHIP_PFSOC_IOSCB,
22
AcpiMcfgInfo mcfg = {
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
23
- .base = s->memmap[VIRT_PCIE_MMIO].base,
31
MICROCHIP_PFSOC_DRAM_LO,
24
- .size = s->memmap[VIRT_PCIE_MMIO].size,
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
25
+ .base = s->memmap[VIRT_PCIE_ECAM].base,
33
MICROCHIP_PFSOC_DRAM_HI,
26
+ .size = s->memmap[VIRT_PCIE_ECAM].size,
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
27
};
35
index XXXXXXX..XXXXXXX 100644
28
build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
36
--- a/hw/riscv/microchip_pfsoc.c
29
s->oem_table_id);
37
+++ b/hw/riscv/microchip_pfsoc.c
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
49
50
+ /* eMMC/SD mux */
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
54
+
55
/* QSPI Flash */
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
57
"microchip.pfsoc.qspi_xip",
58
--
30
--
59
2.30.1
31
2.44.0
60
32
61
33
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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