| 1 | The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a: | 1 | The following changes since commit fcb237e64f9d026c03d635579c7b288d0008a6e5: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000) | 3 | Merge tag 'pull-vfio-20230710' of https://github.com/legoater/qemu into staging (2023-07-10 09:17:06 +0100) |
| 4 | 4 | ||
| 5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 6 | 6 | ||
| 7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2 | 7 | https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230710-1 |
| 8 | 8 | ||
| 9 | for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5: | 9 | for you to fetch changes up to a47842d16653b4f73b5d56ff0c252dd8a329481b: |
| 10 | 10 | ||
| 11 | target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400) | 11 | riscv: Add support for the Zfa extension (2023-07-10 22:29:20 +1000) |
| 12 | 12 | ||
| 13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 14 | RISC-V PR for 6.0 | 14 | Third RISC-V PR for 8.1 |
| 15 | 15 | ||
| 16 | This PR includes: | 16 | * Use xl instead of mxl for disassemble |
| 17 | - Fix for vector CSR access | 17 | * Factor out extension tests to cpu_cfg.h |
| 18 | - Improvements to the Ibex UART device | 18 | * disas/riscv: Add vendor extension support |
| 19 | - PMP improvements and bug fixes | 19 | * disas/riscv: Add support for XVentanaCondOps |
| 20 | - Hypervisor extension bug fixes | 20 | * disas/riscv: Add support for XThead* instructions |
| 21 | - ramfb support for the virt machine | 21 | * Fix mstatus related problems |
| 22 | - Fast read support for SST flash | 22 | * Fix veyron-v1 CPU properties |
| 23 | - Improvements to the microchip_pfsoc machine | 23 | * Fix the xlen for data address when MPRV=1 |
| 24 | * opensbi: Upgrade from v1.2 to v1.3 | ||
| 25 | * Enable 32-bit Spike OpenSBI boot testing | ||
| 26 | * Support the watchdog timer of HiFive 1 rev b | ||
| 27 | * Only build qemu-system-riscv$$ on rv$$ host | ||
| 28 | * Add RVV registers to log | ||
| 29 | * Restrict ACLINT to TCG | ||
| 30 | * Add syscall riscv_hwprobe | ||
| 31 | * Add support for BF16 extensions | ||
| 32 | * KVM_RISCV_SET_TIMER macro is not configured correctly | ||
| 33 | * Generate devicetree only after machine initialization is complete | ||
| 34 | * virt: Convert fdt_load_addr to uint64_t | ||
| 35 | * KVM: fixes and enhancements | ||
| 36 | * Add support for the Zfa extension | ||
| 24 | 37 | ||
| 25 | ---------------------------------------------------------------- | 38 | ---------------------------------------------------------------- |
| 26 | Alexander Wagner (1): | 39 | Bin Meng (2): |
| 27 | hw/char: disable ibex uart receive if the buffer is full | 40 | roms/opensbi: Upgrade from v1.2 to v1.3 |
| 41 | tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing | ||
| 28 | 42 | ||
| 29 | Asherah Connor (2): | 43 | Christoph Müllner (8): |
| 30 | hw/riscv: Add fw_cfg support to virt | 44 | target/riscv: Factor out extension tests to cpu_cfg.h |
| 31 | hw/riscv: allow ramfb on virt | 45 | disas/riscv: Move types/constants to new header file |
| 46 | disas/riscv: Make rv_op_illegal a shared enum value | ||
| 47 | disas/riscv: Encapsulate opcode_data into decode | ||
| 48 | disas/riscv: Provide infrastructure for vendor extensions | ||
| 49 | disas/riscv: Add support for XVentanaCondOps | ||
| 50 | disas/riscv: Add support for XThead* instructions | ||
| 51 | riscv: Add support for the Zfa extension | ||
| 32 | 52 | ||
| 33 | Bin Meng (3): | 53 | Daniel Henrique Barboza (20): |
| 34 | hw/block: m25p80: Support fast read for SST flashes | 54 | target/riscv/cpu.c: fix veyron-v1 CPU properties |
| 35 | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register | 55 | target/riscv: skip features setup for KVM CPUs |
| 36 | docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine | 56 | hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set |
| 57 | target/riscv/cpu.c: restrict 'mvendorid' value | ||
| 58 | target/riscv/cpu.c: restrict 'mimpid' value | ||
| 59 | target/riscv/cpu.c: restrict 'marchid' value | ||
| 60 | target/riscv: use KVM scratch CPUs to init KVM properties | ||
| 61 | target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() | ||
| 62 | target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs | ||
| 63 | target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU | ||
| 64 | target/riscv/cpu: add misa_ext_info_arr[] | ||
| 65 | target/riscv: add KVM specific MISA properties | ||
| 66 | target/riscv/kvm.c: update KVM MISA bits | ||
| 67 | target/riscv/kvm.c: add multi-letter extension KVM properties | ||
| 68 | target/riscv/cpu.c: add satp_mode properties earlier | ||
| 69 | target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() | ||
| 70 | target/riscv/cpu.c: create KVM mock properties | ||
| 71 | target/riscv: update multi-letter extension KVM properties | ||
| 72 | target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper | ||
| 73 | target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM | ||
| 37 | 74 | ||
| 38 | Frank Chang (1): | 75 | Guenter Roeck (1): |
| 39 | target/riscv: fix vs() to return proper error code | 76 | riscv: Generate devicetree only after machine initialization is complete |
| 40 | 77 | ||
| 41 | Georg Kotheimer (6): | 78 | Ivan Klokov (1): |
| 42 | target/riscv: Adjust privilege level for HLV(X)/HSV instructions | 79 | target/riscv: Add RVV registers to log |
| 43 | target/riscv: Make VSTIP and VSEIP read-only in hip | ||
| 44 | target/riscv: Use background registers also for MSTATUS_MPV | ||
| 45 | target/riscv: Fix read and write accesses to vsip and vsie | ||
| 46 | target/riscv: Add proper two-stage lookup exception detection | ||
| 47 | target/riscv: Prevent lost illegal instruction exceptions | ||
| 48 | 80 | ||
| 49 | Jim Shu (3): | 81 | Jason Chien (1): |
| 50 | target/riscv: propagate PMP permission to TLB page | 82 | target/riscv: Set the correct exception for implict G-stage translation fail |
| 51 | target/riscv: add log of PMP permission checking | ||
| 52 | target/riscv: flush TLB pages if PMP permission has been changed | ||
| 53 | 83 | ||
| 54 | docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++ | 84 | LIU Zhiwei (1): |
| 55 | docs/system/target-riscv.rst | 1 + | 85 | target/riscv: Use xl instead of mxl for disassemble |
| 56 | include/hw/char/ibex_uart.h | 4 + | ||
| 57 | include/hw/riscv/microchip_pfsoc.h | 1 + | ||
| 58 | include/hw/riscv/virt.h | 2 + | ||
| 59 | target/riscv/cpu.h | 4 + | ||
| 60 | target/riscv/pmp.h | 4 +- | ||
| 61 | hw/block/m25p80.c | 3 + | ||
| 62 | hw/char/ibex_uart.c | 23 +++- | ||
| 63 | hw/riscv/microchip_pfsoc.c | 6 + | ||
| 64 | hw/riscv/virt.c | 33 ++++++ | ||
| 65 | target/riscv/cpu.c | 1 + | ||
| 66 | target/riscv/cpu_helper.c | 144 +++++++++++++++-------- | ||
| 67 | target/riscv/csr.c | 77 +++++++------ | ||
| 68 | target/riscv/pmp.c | 84 ++++++++++---- | ||
| 69 | target/riscv/translate.c | 179 +---------------------------- | ||
| 70 | hw/riscv/Kconfig | 1 + | ||
| 71 | 17 files changed, 367 insertions(+), 289 deletions(-) | ||
| 72 | create mode 100644 docs/system/riscv/microchip-icicle-kit.rst | ||
| 73 | 86 | ||
| 87 | Lakshmi Bai Raja Subramanian (1): | ||
| 88 | hw/riscv: virt: Convert fdt_load_addr to uint64_t | ||
| 89 | |||
| 90 | Philippe Mathieu-Daudé (3): | ||
| 91 | target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson | ||
| 92 | target/riscv: Only build KVM guest with same wordsize as host | ||
| 93 | hw/riscv/virt: Restrict ACLINT to TCG | ||
| 94 | |||
| 95 | Robbin Ehn (1): | ||
| 96 | linux-user/riscv: Add syscall riscv_hwprobe | ||
| 97 | |||
| 98 | Tommy Wu (3): | ||
| 99 | hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. | ||
| 100 | hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. | ||
| 101 | tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e | ||
| 102 | |||
| 103 | Weiwei Li (11): | ||
| 104 | target/riscv: Make MPV only work when MPP != PRV_M | ||
| 105 | target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled | ||
| 106 | target/riscv: Remove redundant assignment to SXL | ||
| 107 | target/riscv: Add additional xlen for address when MPRV=1 | ||
| 108 | target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV | ||
| 109 | target/riscv: Add properties for BF16 extensions | ||
| 110 | target/riscv: Add support for Zfbfmin extension | ||
| 111 | target/riscv: Add support for Zvfbfmin extension | ||
| 112 | target/riscv: Add support for Zvfbfwma extension | ||
| 113 | target/riscv: Expose properties for BF16 extensions | ||
| 114 | target/riscv: Add disas support for BF16 extensions | ||
| 115 | |||
| 116 | yang.zhang (1): | ||
| 117 | target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly | ||
| 118 | |||
| 119 | docs/system/riscv/virt.rst | 1 + | ||
| 120 | meson.build | 15 +- | ||
| 121 | disas/riscv-xthead.h | 28 + | ||
| 122 | disas/riscv-xventana.h | 18 + | ||
| 123 | disas/riscv.h | 302 +++++++++++ | ||
| 124 | include/hw/misc/sifive_e_aon.h | 60 +++ | ||
| 125 | include/hw/riscv/sifive_e.h | 9 +- | ||
| 126 | linux-user/riscv/syscall32_nr.h | 1 + | ||
| 127 | linux-user/riscv/syscall64_nr.h | 1 + | ||
| 128 | target/riscv/cpu.h | 56 +- | ||
| 129 | target/riscv/cpu_cfg.h | 41 ++ | ||
| 130 | target/riscv/helper.h | 29 + | ||
| 131 | target/riscv/kvm_riscv.h | 1 + | ||
| 132 | target/riscv/insn32.decode | 38 ++ | ||
| 133 | disas/riscv-xthead.c | 707 +++++++++++++++++++++++++ | ||
| 134 | disas/riscv-xventana.c | 41 ++ | ||
| 135 | disas/riscv.c | 559 +++++++++---------- | ||
| 136 | hw/misc/sifive_e_aon.c | 319 +++++++++++ | ||
| 137 | hw/riscv/sifive_e.c | 17 +- | ||
| 138 | hw/riscv/virt.c | 56 +- | ||
| 139 | linux-user/syscall.c | 146 +++++ | ||
| 140 | target/riscv/cpu.c | 439 +++++++++++++-- | ||
| 141 | target/riscv/cpu_helper.c | 12 +- | ||
| 142 | target/riscv/csr.c | 41 +- | ||
| 143 | target/riscv/fpu_helper.c | 166 ++++++ | ||
| 144 | target/riscv/kvm.c | 501 +++++++++++++++++- | ||
| 145 | target/riscv/op_helper.c | 3 +- | ||
| 146 | target/riscv/translate.c | 42 +- | ||
| 147 | target/riscv/vector_helper.c | 17 + | ||
| 148 | tests/qtest/sifive-e-aon-watchdog-test.c | 450 ++++++++++++++++ | ||
| 149 | tests/tcg/riscv64/test-fcvtmod.c | 345 ++++++++++++ | ||
| 150 | target/riscv/insn_trans/trans_rvbf16.c.inc | 175 ++++++ | ||
| 151 | target/riscv/insn_trans/trans_rvzfa.c.inc | 521 ++++++++++++++++++ | ||
| 152 | target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +- | ||
| 153 | disas/meson.build | 6 +- | ||
| 154 | hw/misc/Kconfig | 3 + | ||
| 155 | hw/misc/meson.build | 1 + | ||
| 156 | hw/riscv/Kconfig | 1 + | ||
| 157 | pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 123072 -> 135344 bytes | ||
| 158 | pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 121800 -> 138304 bytes | ||
| 159 | roms/opensbi | 2 +- | ||
| 160 | tests/avocado/riscv_opensbi.py | 2 - | ||
| 161 | tests/qtest/meson.build | 3 + | ||
| 162 | tests/tcg/riscv64/Makefile.target | 6 + | ||
| 163 | 44 files changed, 4751 insertions(+), 442 deletions(-) | ||
| 164 | create mode 100644 disas/riscv-xthead.h | ||
| 165 | create mode 100644 disas/riscv-xventana.h | ||
| 166 | create mode 100644 disas/riscv.h | ||
| 167 | create mode 100644 include/hw/misc/sifive_e_aon.h | ||
| 168 | create mode 100644 disas/riscv-xthead.c | ||
| 169 | create mode 100644 disas/riscv-xventana.c | ||
| 170 | create mode 100644 hw/misc/sifive_e_aon.c | ||
| 171 | create mode 100644 tests/qtest/sifive-e-aon-watchdog-test.c | ||
| 172 | create mode 100644 tests/tcg/riscv64/test-fcvtmod.c | ||
| 173 | create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 174 | create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc | ||
| 175 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Per SST25VF016B datasheet [1], SST flash requires a dummy byte after | 3 | Disassemble function(plugin_disas, target_disas, monitor_disas) will |
| 4 | the address bytes. Note only SPI mode is supported by SST flashes. | 4 | always call set_disas_info before disassembling instructions. |
| 5 | 5 | ||
| 6 | [1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf | 6 | plugin_disas and target_disas will always be called under a TB, which |
| 7 | has the same XLEN. | ||
| 7 | 8 | ||
| 8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 9 | We can't ensure that monitor_disas will always be called under a TB, |
| 9 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | 10 | but current XLEN will still be a better choice, thus we can ensure at |
| 10 | Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com | 11 | least the disassemble of the nearest one TB is right. |
| 12 | |||
| 13 | Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 17 | Message-Id: <20230612111034.3955227-2-christoph.muellner@vrull.eu> | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 12 | --- | 19 | --- |
| 13 | hw/block/m25p80.c | 3 +++ | 20 | target/riscv/cpu.c | 3 ++- |
| 14 | 1 file changed, 3 insertions(+) | 21 | 1 file changed, 2 insertions(+), 1 deletion(-) |
| 15 | 22 | ||
| 16 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | 23 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/block/m25p80.c | 25 | --- a/target/riscv/cpu.c |
| 19 | +++ b/hw/block/m25p80.c | 26 | +++ b/target/riscv/cpu.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s) | 27 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj) |
| 21 | s->needed_bytes = get_addr_length(s); | 28 | static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) |
| 22 | switch (get_man(s)) { | 29 | { |
| 23 | /* Dummy cycles - modeled with bytes writes instead of bits */ | 30 | RISCVCPU *cpu = RISCV_CPU(s); |
| 24 | + case MAN_SST: | 31 | + CPURISCVState *env = &cpu->env; |
| 25 | + s->needed_bytes += 1; | 32 | info->target_info = &cpu->cfg; |
| 26 | + break; | 33 | |
| 27 | case MAN_WINBOND: | 34 | - switch (riscv_cpu_mxl(&cpu->env)) { |
| 28 | s->needed_bytes += 8; | 35 | + switch (env->xl) { |
| 36 | case MXL_RV32: | ||
| 37 | info->print_insn = print_insn_riscv32; | ||
| 29 | break; | 38 | break; |
| 30 | -- | 39 | -- |
| 31 | 2.30.1 | 40 | 2.40.1 |
| 32 | 41 | ||
| 33 | 42 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The previous implementation was broken in many ways: | 3 | This patch moves the extension test functions that are used |
| 4 | - Used mideleg instead of hideleg to mask accesses | 4 | to gate vendor extension decoders, into cpu_cfg.h. |
| 5 | - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie | 5 | This allows to reuse them in the disassembler. |
| 6 | - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) | ||
| 7 | 6 | ||
| 8 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 7 | This patch does not introduce new functionality. |
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | However, the patch includes a small change: |
| 10 | Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com | 9 | The parameter for the extension test functions has been changed |
| 10 | from 'DisasContext*' to 'const RISCVCPUConfig*' to keep | ||
| 11 | the code in cpu_cfg.h self-contained. | ||
| 12 | |||
| 13 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 14 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 15 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 16 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 17 | Message-Id: <20230612111034.3955227-3-christoph.muellner@vrull.eu> | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 12 | --- | 19 | --- |
| 13 | target/riscv/csr.c | 68 +++++++++++++++++++++++----------------------- | 20 | target/riscv/cpu_cfg.h | 26 ++++++++++++++++++++++++++ |
| 14 | 1 file changed, 34 insertions(+), 34 deletions(-) | 21 | target/riscv/translate.c | 27 ++------------------------- |
| 22 | 2 files changed, 28 insertions(+), 25 deletions(-) | ||
| 15 | 23 | ||
| 16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 24 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/riscv/csr.c | 26 | --- a/target/riscv/cpu_cfg.h |
| 19 | +++ b/target/riscv/csr.c | 27 | +++ b/target/riscv/cpu_cfg.h |
| 20 | @@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) | 28 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { |
| 21 | return write_mstatus(env, CSR_MSTATUS, newval); | 29 | }; |
| 22 | } | 30 | |
| 23 | 31 | typedef struct RISCVCPUConfig RISCVCPUConfig; | |
| 24 | +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) | 32 | + |
| 33 | +/* Helper functions to test for extensions. */ | ||
| 34 | + | ||
| 35 | +static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__))) | ||
| 25 | +{ | 36 | +{ |
| 26 | + /* Shift the VS bits to their S bit location in vsie */ | 37 | + return true; |
| 27 | + *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | ||
| 28 | + return 0; | ||
| 29 | +} | 38 | +} |
| 30 | + | 39 | + |
| 31 | static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) | 40 | +static inline bool has_xthead_p(const RISCVCPUConfig *cfg) |
| 32 | { | ||
| 33 | if (riscv_cpu_virt_enabled(env)) { | ||
| 34 | - /* Tell the guest the VS bits, shifted to the S bit locations */ | ||
| 35 | - *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; | ||
| 36 | + read_vsie(env, CSR_VSIE, val); | ||
| 37 | } else { | ||
| 38 | *val = env->mie & env->mideleg; | ||
| 39 | } | ||
| 40 | return 0; | ||
| 41 | } | ||
| 42 | |||
| 43 | -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 44 | +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 45 | { | ||
| 46 | - target_ulong newval; | ||
| 47 | + /* Shift the S bits to their VS bit location in mie */ | ||
| 48 | + target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | ||
| 49 | + ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | ||
| 50 | + return write_mie(env, CSR_MIE, newval); | ||
| 51 | +} | ||
| 52 | |||
| 53 | +static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 54 | +{ | 41 | +{ |
| 55 | if (riscv_cpu_virt_enabled(env)) { | 42 | + return cfg->ext_xtheadba || cfg->ext_xtheadbb || |
| 56 | - /* Shift the guests S bits to VS */ | 43 | + cfg->ext_xtheadbs || cfg->ext_xtheadcmo || |
| 57 | - newval = (env->mie & ~VS_MODE_INTERRUPTS) | | 44 | + cfg->ext_xtheadcondmov || |
| 58 | - ((val << 1) & VS_MODE_INTERRUPTS); | 45 | + cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv || |
| 59 | + write_vsie(env, CSR_VSIE, val); | 46 | + cfg->ext_xtheadmac || cfg->ext_xtheadmemidx || |
| 60 | } else { | 47 | + cfg->ext_xtheadmempair || cfg->ext_xtheadsync; |
| 61 | - newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); | ||
| 62 | + target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | | ||
| 63 | + (val & S_MODE_INTERRUPTS); | ||
| 64 | + write_mie(env, CSR_MIE, newval); | ||
| 65 | } | ||
| 66 | |||
| 67 | - return write_mie(env, CSR_MIE, newval); | ||
| 68 | + return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) | ||
| 73 | return 0; | ||
| 74 | } | ||
| 75 | |||
| 76 | +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 77 | + target_ulong new_value, target_ulong write_mask) | ||
| 78 | +{ | ||
| 79 | + /* Shift the S bits to their VS bit location in mip */ | ||
| 80 | + int ret = rmw_mip(env, 0, ret_value, new_value << 1, | ||
| 81 | + (write_mask << 1) & vsip_writable_mask & env->hideleg); | ||
| 82 | + *ret_value &= VS_MODE_INTERRUPTS; | ||
| 83 | + /* Shift the VS bits to their S bit location in vsip */ | ||
| 84 | + *ret_value >>= 1; | ||
| 85 | + return ret; | ||
| 86 | +} | 48 | +} |
| 87 | + | 49 | + |
| 88 | static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, | 50 | +#define MATERIALISE_EXT_PREDICATE(ext) \ |
| 89 | target_ulong new_value, target_ulong write_mask) | 51 | + static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \ |
| 90 | { | 52 | + { \ |
| 91 | int ret; | 53 | + return cfg->ext_ ## ext ; \ |
| 92 | 54 | + } | |
| 93 | if (riscv_cpu_virt_enabled(env)) { | 55 | + |
| 94 | - /* Shift the new values to line up with the VS bits */ | 56 | +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) |
| 95 | - ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, | 57 | + |
| 96 | - (write_mask & sip_writable_mask) << 1 & env->mideleg); | 58 | #endif |
| 97 | - ret &= vsip_writable_mask; | 59 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c |
| 98 | - ret >>= 1; | 60 | index XXXXXXX..XXXXXXX 100644 |
| 99 | + ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); | 61 | --- a/target/riscv/translate.c |
| 100 | } else { | 62 | +++ b/target/riscv/translate.c |
| 101 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | 63 | @@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
| 102 | write_mask & env->mideleg & sip_writable_mask); | 64 | return ctx->misa_ext & ext; |
| 103 | @@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 104 | return 0; | ||
| 105 | } | 65 | } |
| 106 | 66 | ||
| 107 | -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, | 67 | -static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) |
| 108 | - target_ulong new_value, target_ulong write_mask) | ||
| 109 | -{ | 68 | -{ |
| 110 | - int ret = rmw_mip(env, 0, ret_value, new_value, | 69 | - return true; |
| 111 | - write_mask & env->mideleg & vsip_writable_mask); | ||
| 112 | - return ret; | ||
| 113 | -} | 70 | -} |
| 114 | - | 71 | - |
| 115 | -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) | 72 | -static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) |
| 116 | -{ | 73 | -{ |
| 117 | - *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; | 74 | - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || |
| 118 | - return 0; | 75 | - ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || |
| 76 | - ctx->cfg_ptr->ext_xtheadcondmov || | ||
| 77 | - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || | ||
| 78 | - ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || | ||
| 79 | - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; | ||
| 119 | -} | 80 | -} |
| 120 | - | 81 | - |
| 121 | -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) | 82 | -#define MATERIALISE_EXT_PREDICATE(ext) \ |
| 122 | -{ | 83 | - static bool has_ ## ext ## _p(DisasContext *ctx) \ |
| 123 | - target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); | 84 | - { \ |
| 124 | - return write_mie(env, CSR_MIE, newval); | 85 | - return ctx->cfg_ptr->ext_ ## ext ; \ |
| 125 | -} | 86 | - } |
| 126 | - | 87 | - |
| 127 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) | 88 | -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); |
| 128 | { | 89 | - |
| 129 | *val = env->vstvec; | 90 | #ifdef TARGET_RISCV32 |
| 91 | #define get_xl(ctx) MXL_RV32 | ||
| 92 | #elif defined(CONFIG_USER_ONLY) | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) | ||
| 94 | * that are tested in-order until a decoder matches onto the opcode. | ||
| 95 | */ | ||
| 96 | static const struct { | ||
| 97 | - bool (*guard_func)(DisasContext *); | ||
| 98 | + bool (*guard_func)(const RISCVCPUConfig *); | ||
| 99 | bool (*decode_func)(DisasContext *, uint32_t); | ||
| 100 | } decoders[] = { | ||
| 101 | { always_true_p, decode_insn32 }, | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) | ||
| 103 | ctx->opcode = opcode32; | ||
| 104 | |||
| 105 | for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { | ||
| 106 | - if (decoders[i].guard_func(ctx) && | ||
| 107 | + if (decoders[i].guard_func(ctx->cfg_ptr) && | ||
| 108 | decoders[i].decode_func(ctx, opcode32)) { | ||
| 109 | return; | ||
| 110 | } | ||
| 130 | -- | 111 | -- |
| 131 | 2.30.1 | 112 | 2.40.1 |
| 132 | 113 | ||
| 133 | 114 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | In order to enable vendor disassembler support, we need to | ||
| 4 | move types and constants into a header file so that other | ||
| 5 | compilation units can use them as well. | ||
| 6 | |||
| 7 | This patch does not introduce any functional changes. | ||
| 8 | |||
| 9 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 12 | Message-Id: <20230612111034.3955227-4-christoph.muellner@vrull.eu> | ||
| 13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 14 | --- | ||
| 15 | disas/riscv.h | 282 ++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 16 | disas/riscv.c | 270 +---------------------------------------------- | ||
| 17 | 2 files changed, 283 insertions(+), 269 deletions(-) | ||
| 18 | create mode 100644 disas/riscv.h | ||
| 19 | |||
| 20 | diff --git a/disas/riscv.h b/disas/riscv.h | ||
| 21 | new file mode 100644 | ||
| 22 | index XXXXXXX..XXXXXXX | ||
| 23 | --- /dev/null | ||
| 24 | +++ b/disas/riscv.h | ||
| 25 | @@ -XXX,XX +XXX,XX @@ | ||
| 26 | +/* | ||
| 27 | + * QEMU disassembler -- RISC-V specific header. | ||
| 28 | + * | ||
| 29 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 30 | + */ | ||
| 31 | + | ||
| 32 | +#ifndef DISAS_RISCV_H | ||
| 33 | +#define DISAS_RISCV_H | ||
| 34 | + | ||
| 35 | +#include "qemu/osdep.h" | ||
| 36 | +#include "target/riscv/cpu_cfg.h" | ||
| 37 | + | ||
| 38 | +/* types */ | ||
| 39 | + | ||
| 40 | +typedef uint64_t rv_inst; | ||
| 41 | +typedef uint16_t rv_opcode; | ||
| 42 | + | ||
| 43 | +/* enums */ | ||
| 44 | + | ||
| 45 | +typedef enum { | ||
| 46 | + rv32, | ||
| 47 | + rv64, | ||
| 48 | + rv128 | ||
| 49 | +} rv_isa; | ||
| 50 | + | ||
| 51 | +typedef enum { | ||
| 52 | + rv_rm_rne = 0, | ||
| 53 | + rv_rm_rtz = 1, | ||
| 54 | + rv_rm_rdn = 2, | ||
| 55 | + rv_rm_rup = 3, | ||
| 56 | + rv_rm_rmm = 4, | ||
| 57 | + rv_rm_dyn = 7, | ||
| 58 | +} rv_rm; | ||
| 59 | + | ||
| 60 | +typedef enum { | ||
| 61 | + rv_fence_i = 8, | ||
| 62 | + rv_fence_o = 4, | ||
| 63 | + rv_fence_r = 2, | ||
| 64 | + rv_fence_w = 1, | ||
| 65 | +} rv_fence; | ||
| 66 | + | ||
| 67 | +typedef enum { | ||
| 68 | + rv_ireg_zero, | ||
| 69 | + rv_ireg_ra, | ||
| 70 | + rv_ireg_sp, | ||
| 71 | + rv_ireg_gp, | ||
| 72 | + rv_ireg_tp, | ||
| 73 | + rv_ireg_t0, | ||
| 74 | + rv_ireg_t1, | ||
| 75 | + rv_ireg_t2, | ||
| 76 | + rv_ireg_s0, | ||
| 77 | + rv_ireg_s1, | ||
| 78 | + rv_ireg_a0, | ||
| 79 | + rv_ireg_a1, | ||
| 80 | + rv_ireg_a2, | ||
| 81 | + rv_ireg_a3, | ||
| 82 | + rv_ireg_a4, | ||
| 83 | + rv_ireg_a5, | ||
| 84 | + rv_ireg_a6, | ||
| 85 | + rv_ireg_a7, | ||
| 86 | + rv_ireg_s2, | ||
| 87 | + rv_ireg_s3, | ||
| 88 | + rv_ireg_s4, | ||
| 89 | + rv_ireg_s5, | ||
| 90 | + rv_ireg_s6, | ||
| 91 | + rv_ireg_s7, | ||
| 92 | + rv_ireg_s8, | ||
| 93 | + rv_ireg_s9, | ||
| 94 | + rv_ireg_s10, | ||
| 95 | + rv_ireg_s11, | ||
| 96 | + rv_ireg_t3, | ||
| 97 | + rv_ireg_t4, | ||
| 98 | + rv_ireg_t5, | ||
| 99 | + rv_ireg_t6, | ||
| 100 | +} rv_ireg; | ||
| 101 | + | ||
| 102 | +typedef enum { | ||
| 103 | + rvc_end, | ||
| 104 | + rvc_rd_eq_ra, | ||
| 105 | + rvc_rd_eq_x0, | ||
| 106 | + rvc_rs1_eq_x0, | ||
| 107 | + rvc_rs2_eq_x0, | ||
| 108 | + rvc_rs2_eq_rs1, | ||
| 109 | + rvc_rs1_eq_ra, | ||
| 110 | + rvc_imm_eq_zero, | ||
| 111 | + rvc_imm_eq_n1, | ||
| 112 | + rvc_imm_eq_p1, | ||
| 113 | + rvc_csr_eq_0x001, | ||
| 114 | + rvc_csr_eq_0x002, | ||
| 115 | + rvc_csr_eq_0x003, | ||
| 116 | + rvc_csr_eq_0xc00, | ||
| 117 | + rvc_csr_eq_0xc01, | ||
| 118 | + rvc_csr_eq_0xc02, | ||
| 119 | + rvc_csr_eq_0xc80, | ||
| 120 | + rvc_csr_eq_0xc81, | ||
| 121 | + rvc_csr_eq_0xc82, | ||
| 122 | +} rvc_constraint; | ||
| 123 | + | ||
| 124 | +typedef enum { | ||
| 125 | + rv_codec_illegal, | ||
| 126 | + rv_codec_none, | ||
| 127 | + rv_codec_u, | ||
| 128 | + rv_codec_uj, | ||
| 129 | + rv_codec_i, | ||
| 130 | + rv_codec_i_sh5, | ||
| 131 | + rv_codec_i_sh6, | ||
| 132 | + rv_codec_i_sh7, | ||
| 133 | + rv_codec_i_csr, | ||
| 134 | + rv_codec_s, | ||
| 135 | + rv_codec_sb, | ||
| 136 | + rv_codec_r, | ||
| 137 | + rv_codec_r_m, | ||
| 138 | + rv_codec_r4_m, | ||
| 139 | + rv_codec_r_a, | ||
| 140 | + rv_codec_r_l, | ||
| 141 | + rv_codec_r_f, | ||
| 142 | + rv_codec_cb, | ||
| 143 | + rv_codec_cb_imm, | ||
| 144 | + rv_codec_cb_sh5, | ||
| 145 | + rv_codec_cb_sh6, | ||
| 146 | + rv_codec_ci, | ||
| 147 | + rv_codec_ci_sh5, | ||
| 148 | + rv_codec_ci_sh6, | ||
| 149 | + rv_codec_ci_16sp, | ||
| 150 | + rv_codec_ci_lwsp, | ||
| 151 | + rv_codec_ci_ldsp, | ||
| 152 | + rv_codec_ci_lqsp, | ||
| 153 | + rv_codec_ci_li, | ||
| 154 | + rv_codec_ci_lui, | ||
| 155 | + rv_codec_ci_none, | ||
| 156 | + rv_codec_ciw_4spn, | ||
| 157 | + rv_codec_cj, | ||
| 158 | + rv_codec_cj_jal, | ||
| 159 | + rv_codec_cl_lw, | ||
| 160 | + rv_codec_cl_ld, | ||
| 161 | + rv_codec_cl_lq, | ||
| 162 | + rv_codec_cr, | ||
| 163 | + rv_codec_cr_mv, | ||
| 164 | + rv_codec_cr_jalr, | ||
| 165 | + rv_codec_cr_jr, | ||
| 166 | + rv_codec_cs, | ||
| 167 | + rv_codec_cs_sw, | ||
| 168 | + rv_codec_cs_sd, | ||
| 169 | + rv_codec_cs_sq, | ||
| 170 | + rv_codec_css_swsp, | ||
| 171 | + rv_codec_css_sdsp, | ||
| 172 | + rv_codec_css_sqsp, | ||
| 173 | + rv_codec_k_bs, | ||
| 174 | + rv_codec_k_rnum, | ||
| 175 | + rv_codec_v_r, | ||
| 176 | + rv_codec_v_ldst, | ||
| 177 | + rv_codec_v_i, | ||
| 178 | + rv_codec_vsetvli, | ||
| 179 | + rv_codec_vsetivli, | ||
| 180 | + rv_codec_zcb_ext, | ||
| 181 | + rv_codec_zcb_mul, | ||
| 182 | + rv_codec_zcb_lb, | ||
| 183 | + rv_codec_zcb_lh, | ||
| 184 | + rv_codec_zcmp_cm_pushpop, | ||
| 185 | + rv_codec_zcmp_cm_mv, | ||
| 186 | + rv_codec_zcmt_jt, | ||
| 187 | +} rv_codec; | ||
| 188 | + | ||
| 189 | +/* structures */ | ||
| 190 | + | ||
| 191 | +typedef struct { | ||
| 192 | + RISCVCPUConfig *cfg; | ||
| 193 | + uint64_t pc; | ||
| 194 | + uint64_t inst; | ||
| 195 | + int32_t imm; | ||
| 196 | + uint16_t op; | ||
| 197 | + uint8_t codec; | ||
| 198 | + uint8_t rd; | ||
| 199 | + uint8_t rs1; | ||
| 200 | + uint8_t rs2; | ||
| 201 | + uint8_t rs3; | ||
| 202 | + uint8_t rm; | ||
| 203 | + uint8_t pred; | ||
| 204 | + uint8_t succ; | ||
| 205 | + uint8_t aq; | ||
| 206 | + uint8_t rl; | ||
| 207 | + uint8_t bs; | ||
| 208 | + uint8_t rnum; | ||
| 209 | + uint8_t vm; | ||
| 210 | + uint32_t vzimm; | ||
| 211 | + uint8_t rlist; | ||
| 212 | +} rv_decode; | ||
| 213 | + | ||
| 214 | +typedef struct { | ||
| 215 | + const int op; | ||
| 216 | + const rvc_constraint *constraints; | ||
| 217 | +} rv_comp_data; | ||
| 218 | + | ||
| 219 | +enum { | ||
| 220 | + rvcd_imm_nz = 0x1 | ||
| 221 | +}; | ||
| 222 | + | ||
| 223 | +typedef struct { | ||
| 224 | + const char * const name; | ||
| 225 | + const rv_codec codec; | ||
| 226 | + const char * const format; | ||
| 227 | + const rv_comp_data *pseudo; | ||
| 228 | + const short decomp_rv32; | ||
| 229 | + const short decomp_rv64; | ||
| 230 | + const short decomp_rv128; | ||
| 231 | + const short decomp_data; | ||
| 232 | +} rv_opcode_data; | ||
| 233 | + | ||
| 234 | +/* instruction formats */ | ||
| 235 | + | ||
| 236 | +#define rv_fmt_none "O\t" | ||
| 237 | +#define rv_fmt_rs1 "O\t1" | ||
| 238 | +#define rv_fmt_offset "O\to" | ||
| 239 | +#define rv_fmt_pred_succ "O\tp,s" | ||
| 240 | +#define rv_fmt_rs1_rs2 "O\t1,2" | ||
| 241 | +#define rv_fmt_rd_imm "O\t0,i" | ||
| 242 | +#define rv_fmt_rd_offset "O\t0,o" | ||
| 243 | +#define rv_fmt_rd_rs1_rs2 "O\t0,1,2" | ||
| 244 | +#define rv_fmt_frd_rs1 "O\t3,1" | ||
| 245 | +#define rv_fmt_frd_frs1 "O\t3,4" | ||
| 246 | +#define rv_fmt_rd_frs1 "O\t0,4" | ||
| 247 | +#define rv_fmt_rd_frs1_frs2 "O\t0,4,5" | ||
| 248 | +#define rv_fmt_frd_frs1_frs2 "O\t3,4,5" | ||
| 249 | +#define rv_fmt_rm_frd_frs1 "O\tr,3,4" | ||
| 250 | +#define rv_fmt_rm_frd_rs1 "O\tr,3,1" | ||
| 251 | +#define rv_fmt_rm_rd_frs1 "O\tr,0,4" | ||
| 252 | +#define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5" | ||
| 253 | +#define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6" | ||
| 254 | +#define rv_fmt_rd_rs1_imm "O\t0,1,i" | ||
| 255 | +#define rv_fmt_rd_rs1_offset "O\t0,1,i" | ||
| 256 | +#define rv_fmt_rd_offset_rs1 "O\t0,i(1)" | ||
| 257 | +#define rv_fmt_frd_offset_rs1 "O\t3,i(1)" | ||
| 258 | +#define rv_fmt_rd_csr_rs1 "O\t0,c,1" | ||
| 259 | +#define rv_fmt_rd_csr_zimm "O\t0,c,7" | ||
| 260 | +#define rv_fmt_rs2_offset_rs1 "O\t2,i(1)" | ||
| 261 | +#define rv_fmt_frs2_offset_rs1 "O\t5,i(1)" | ||
| 262 | +#define rv_fmt_rs1_rs2_offset "O\t1,2,o" | ||
| 263 | +#define rv_fmt_rs2_rs1_offset "O\t2,1,o" | ||
| 264 | +#define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)" | ||
| 265 | +#define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)" | ||
| 266 | +#define rv_fmt_rd "O\t0" | ||
| 267 | +#define rv_fmt_rd_zimm "O\t0,7" | ||
| 268 | +#define rv_fmt_rd_rs1 "O\t0,1" | ||
| 269 | +#define rv_fmt_rd_rs2 "O\t0,2" | ||
| 270 | +#define rv_fmt_rs1_offset "O\t1,o" | ||
| 271 | +#define rv_fmt_rs2_offset "O\t2,o" | ||
| 272 | +#define rv_fmt_rs1_rs2_bs "O\t1,2,b" | ||
| 273 | +#define rv_fmt_rd_rs1_rnum "O\t0,1,n" | ||
| 274 | +#define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" | ||
| 275 | +#define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" | ||
| 276 | +#define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" | ||
| 277 | +#define rv_fmt_vd_vs2_vs1 "O\tD,F,E" | ||
| 278 | +#define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" | ||
| 279 | +#define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" | ||
| 280 | +#define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" | ||
| 281 | +#define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" | ||
| 282 | +#define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" | ||
| 283 | +#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" | ||
| 284 | +#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" | ||
| 285 | +#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" | ||
| 286 | +#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" | ||
| 287 | +#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" | ||
| 288 | +#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" | ||
| 289 | +#define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" | ||
| 290 | +#define rv_fmt_vd_vs1 "O\tD,E" | ||
| 291 | +#define rv_fmt_vd_rs1 "O\tD,1" | ||
| 292 | +#define rv_fmt_vd_fs1 "O\tD,4" | ||
| 293 | +#define rv_fmt_vd_imm "O\tD,i" | ||
| 294 | +#define rv_fmt_vd_vs2 "O\tD,F" | ||
| 295 | +#define rv_fmt_vd_vs2_vm "O\tD,Fm" | ||
| 296 | +#define rv_fmt_rd_vs2_vm "O\t0,Fm" | ||
| 297 | +#define rv_fmt_rd_vs2 "O\t0,F" | ||
| 298 | +#define rv_fmt_fd_vs2 "O\t3,F" | ||
| 299 | +#define rv_fmt_vd_vm "O\tDm" | ||
| 300 | +#define rv_fmt_vsetvli "O\t0,1,v" | ||
| 301 | +#define rv_fmt_vsetivli "O\t0,u,v" | ||
| 302 | +#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" | ||
| 303 | +#define rv_fmt_push_rlist "O\tx,-i" | ||
| 304 | +#define rv_fmt_pop_rlist "O\tx,i" | ||
| 305 | +#define rv_fmt_zcmt_index "O\ti" | ||
| 306 | + | ||
| 307 | +#endif /* DISAS_RISCV_H */ | ||
| 308 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 309 | index XXXXXXX..XXXXXXX 100644 | ||
| 310 | --- a/disas/riscv.c | ||
| 311 | +++ b/disas/riscv.c | ||
| 312 | @@ -XXX,XX +XXX,XX @@ | ||
| 313 | #include "qemu/osdep.h" | ||
| 314 | #include "disas/dis-asm.h" | ||
| 315 | #include "target/riscv/cpu_cfg.h" | ||
| 316 | - | ||
| 317 | -/* types */ | ||
| 318 | - | ||
| 319 | -typedef uint64_t rv_inst; | ||
| 320 | -typedef uint16_t rv_opcode; | ||
| 321 | - | ||
| 322 | -/* enums */ | ||
| 323 | - | ||
| 324 | -typedef enum { | ||
| 325 | - rv32, | ||
| 326 | - rv64, | ||
| 327 | - rv128 | ||
| 328 | -} rv_isa; | ||
| 329 | - | ||
| 330 | -typedef enum { | ||
| 331 | - rv_rm_rne = 0, | ||
| 332 | - rv_rm_rtz = 1, | ||
| 333 | - rv_rm_rdn = 2, | ||
| 334 | - rv_rm_rup = 3, | ||
| 335 | - rv_rm_rmm = 4, | ||
| 336 | - rv_rm_dyn = 7, | ||
| 337 | -} rv_rm; | ||
| 338 | - | ||
| 339 | -typedef enum { | ||
| 340 | - rv_fence_i = 8, | ||
| 341 | - rv_fence_o = 4, | ||
| 342 | - rv_fence_r = 2, | ||
| 343 | - rv_fence_w = 1, | ||
| 344 | -} rv_fence; | ||
| 345 | - | ||
| 346 | -typedef enum { | ||
| 347 | - rv_ireg_zero, | ||
| 348 | - rv_ireg_ra, | ||
| 349 | - rv_ireg_sp, | ||
| 350 | - rv_ireg_gp, | ||
| 351 | - rv_ireg_tp, | ||
| 352 | - rv_ireg_t0, | ||
| 353 | - rv_ireg_t1, | ||
| 354 | - rv_ireg_t2, | ||
| 355 | - rv_ireg_s0, | ||
| 356 | - rv_ireg_s1, | ||
| 357 | - rv_ireg_a0, | ||
| 358 | - rv_ireg_a1, | ||
| 359 | - rv_ireg_a2, | ||
| 360 | - rv_ireg_a3, | ||
| 361 | - rv_ireg_a4, | ||
| 362 | - rv_ireg_a5, | ||
| 363 | - rv_ireg_a6, | ||
| 364 | - rv_ireg_a7, | ||
| 365 | - rv_ireg_s2, | ||
| 366 | - rv_ireg_s3, | ||
| 367 | - rv_ireg_s4, | ||
| 368 | - rv_ireg_s5, | ||
| 369 | - rv_ireg_s6, | ||
| 370 | - rv_ireg_s7, | ||
| 371 | - rv_ireg_s8, | ||
| 372 | - rv_ireg_s9, | ||
| 373 | - rv_ireg_s10, | ||
| 374 | - rv_ireg_s11, | ||
| 375 | - rv_ireg_t3, | ||
| 376 | - rv_ireg_t4, | ||
| 377 | - rv_ireg_t5, | ||
| 378 | - rv_ireg_t6, | ||
| 379 | -} rv_ireg; | ||
| 380 | - | ||
| 381 | -typedef enum { | ||
| 382 | - rvc_end, | ||
| 383 | - rvc_rd_eq_ra, | ||
| 384 | - rvc_rd_eq_x0, | ||
| 385 | - rvc_rs1_eq_x0, | ||
| 386 | - rvc_rs2_eq_x0, | ||
| 387 | - rvc_rs2_eq_rs1, | ||
| 388 | - rvc_rs1_eq_ra, | ||
| 389 | - rvc_imm_eq_zero, | ||
| 390 | - rvc_imm_eq_n1, | ||
| 391 | - rvc_imm_eq_p1, | ||
| 392 | - rvc_csr_eq_0x001, | ||
| 393 | - rvc_csr_eq_0x002, | ||
| 394 | - rvc_csr_eq_0x003, | ||
| 395 | - rvc_csr_eq_0xc00, | ||
| 396 | - rvc_csr_eq_0xc01, | ||
| 397 | - rvc_csr_eq_0xc02, | ||
| 398 | - rvc_csr_eq_0xc80, | ||
| 399 | - rvc_csr_eq_0xc81, | ||
| 400 | - rvc_csr_eq_0xc82, | ||
| 401 | -} rvc_constraint; | ||
| 402 | - | ||
| 403 | -typedef enum { | ||
| 404 | - rv_codec_illegal, | ||
| 405 | - rv_codec_none, | ||
| 406 | - rv_codec_u, | ||
| 407 | - rv_codec_uj, | ||
| 408 | - rv_codec_i, | ||
| 409 | - rv_codec_i_sh5, | ||
| 410 | - rv_codec_i_sh6, | ||
| 411 | - rv_codec_i_sh7, | ||
| 412 | - rv_codec_i_csr, | ||
| 413 | - rv_codec_s, | ||
| 414 | - rv_codec_sb, | ||
| 415 | - rv_codec_r, | ||
| 416 | - rv_codec_r_m, | ||
| 417 | - rv_codec_r4_m, | ||
| 418 | - rv_codec_r_a, | ||
| 419 | - rv_codec_r_l, | ||
| 420 | - rv_codec_r_f, | ||
| 421 | - rv_codec_cb, | ||
| 422 | - rv_codec_cb_imm, | ||
| 423 | - rv_codec_cb_sh5, | ||
| 424 | - rv_codec_cb_sh6, | ||
| 425 | - rv_codec_ci, | ||
| 426 | - rv_codec_ci_sh5, | ||
| 427 | - rv_codec_ci_sh6, | ||
| 428 | - rv_codec_ci_16sp, | ||
| 429 | - rv_codec_ci_lwsp, | ||
| 430 | - rv_codec_ci_ldsp, | ||
| 431 | - rv_codec_ci_lqsp, | ||
| 432 | - rv_codec_ci_li, | ||
| 433 | - rv_codec_ci_lui, | ||
| 434 | - rv_codec_ci_none, | ||
| 435 | - rv_codec_ciw_4spn, | ||
| 436 | - rv_codec_cj, | ||
| 437 | - rv_codec_cj_jal, | ||
| 438 | - rv_codec_cl_lw, | ||
| 439 | - rv_codec_cl_ld, | ||
| 440 | - rv_codec_cl_lq, | ||
| 441 | - rv_codec_cr, | ||
| 442 | - rv_codec_cr_mv, | ||
| 443 | - rv_codec_cr_jalr, | ||
| 444 | - rv_codec_cr_jr, | ||
| 445 | - rv_codec_cs, | ||
| 446 | - rv_codec_cs_sw, | ||
| 447 | - rv_codec_cs_sd, | ||
| 448 | - rv_codec_cs_sq, | ||
| 449 | - rv_codec_css_swsp, | ||
| 450 | - rv_codec_css_sdsp, | ||
| 451 | - rv_codec_css_sqsp, | ||
| 452 | - rv_codec_k_bs, | ||
| 453 | - rv_codec_k_rnum, | ||
| 454 | - rv_codec_v_r, | ||
| 455 | - rv_codec_v_ldst, | ||
| 456 | - rv_codec_v_i, | ||
| 457 | - rv_codec_vsetvli, | ||
| 458 | - rv_codec_vsetivli, | ||
| 459 | - rv_codec_zcb_ext, | ||
| 460 | - rv_codec_zcb_mul, | ||
| 461 | - rv_codec_zcb_lb, | ||
| 462 | - rv_codec_zcb_lh, | ||
| 463 | - rv_codec_zcmp_cm_pushpop, | ||
| 464 | - rv_codec_zcmp_cm_mv, | ||
| 465 | - rv_codec_zcmt_jt, | ||
| 466 | -} rv_codec; | ||
| 467 | +#include "disas/riscv.h" | ||
| 468 | |||
| 469 | typedef enum { | ||
| 470 | rv_op_illegal = 0, | ||
| 471 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 472 | rv_op_czero_nez = 790, | ||
| 473 | } rv_op; | ||
| 474 | |||
| 475 | -/* structures */ | ||
| 476 | - | ||
| 477 | -typedef struct { | ||
| 478 | - RISCVCPUConfig *cfg; | ||
| 479 | - uint64_t pc; | ||
| 480 | - uint64_t inst; | ||
| 481 | - int32_t imm; | ||
| 482 | - uint16_t op; | ||
| 483 | - uint8_t codec; | ||
| 484 | - uint8_t rd; | ||
| 485 | - uint8_t rs1; | ||
| 486 | - uint8_t rs2; | ||
| 487 | - uint8_t rs3; | ||
| 488 | - uint8_t rm; | ||
| 489 | - uint8_t pred; | ||
| 490 | - uint8_t succ; | ||
| 491 | - uint8_t aq; | ||
| 492 | - uint8_t rl; | ||
| 493 | - uint8_t bs; | ||
| 494 | - uint8_t rnum; | ||
| 495 | - uint8_t vm; | ||
| 496 | - uint32_t vzimm; | ||
| 497 | - uint8_t rlist; | ||
| 498 | -} rv_decode; | ||
| 499 | - | ||
| 500 | -typedef struct { | ||
| 501 | - const int op; | ||
| 502 | - const rvc_constraint *constraints; | ||
| 503 | -} rv_comp_data; | ||
| 504 | - | ||
| 505 | -enum { | ||
| 506 | - rvcd_imm_nz = 0x1 | ||
| 507 | -}; | ||
| 508 | - | ||
| 509 | -typedef struct { | ||
| 510 | - const char * const name; | ||
| 511 | - const rv_codec codec; | ||
| 512 | - const char * const format; | ||
| 513 | - const rv_comp_data *pseudo; | ||
| 514 | - const short decomp_rv32; | ||
| 515 | - const short decomp_rv64; | ||
| 516 | - const short decomp_rv128; | ||
| 517 | - const short decomp_data; | ||
| 518 | -} rv_opcode_data; | ||
| 519 | - | ||
| 520 | /* register names */ | ||
| 521 | |||
| 522 | static const char rv_ireg_name_sym[32][5] = { | ||
| 523 | @@ -XXX,XX +XXX,XX @@ static const char rv_vreg_name_sym[32][4] = { | ||
| 524 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" | ||
| 525 | }; | ||
| 526 | |||
| 527 | -/* instruction formats */ | ||
| 528 | - | ||
| 529 | -#define rv_fmt_none "O\t" | ||
| 530 | -#define rv_fmt_rs1 "O\t1" | ||
| 531 | -#define rv_fmt_offset "O\to" | ||
| 532 | -#define rv_fmt_pred_succ "O\tp,s" | ||
| 533 | -#define rv_fmt_rs1_rs2 "O\t1,2" | ||
| 534 | -#define rv_fmt_rd_imm "O\t0,i" | ||
| 535 | -#define rv_fmt_rd_offset "O\t0,o" | ||
| 536 | -#define rv_fmt_rd_rs1_rs2 "O\t0,1,2" | ||
| 537 | -#define rv_fmt_frd_rs1 "O\t3,1" | ||
| 538 | -#define rv_fmt_frd_frs1 "O\t3,4" | ||
| 539 | -#define rv_fmt_rd_frs1 "O\t0,4" | ||
| 540 | -#define rv_fmt_rd_frs1_frs2 "O\t0,4,5" | ||
| 541 | -#define rv_fmt_frd_frs1_frs2 "O\t3,4,5" | ||
| 542 | -#define rv_fmt_rm_frd_frs1 "O\tr,3,4" | ||
| 543 | -#define rv_fmt_rm_frd_rs1 "O\tr,3,1" | ||
| 544 | -#define rv_fmt_rm_rd_frs1 "O\tr,0,4" | ||
| 545 | -#define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5" | ||
| 546 | -#define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6" | ||
| 547 | -#define rv_fmt_rd_rs1_imm "O\t0,1,i" | ||
| 548 | -#define rv_fmt_rd_rs1_offset "O\t0,1,i" | ||
| 549 | -#define rv_fmt_rd_offset_rs1 "O\t0,i(1)" | ||
| 550 | -#define rv_fmt_frd_offset_rs1 "O\t3,i(1)" | ||
| 551 | -#define rv_fmt_rd_csr_rs1 "O\t0,c,1" | ||
| 552 | -#define rv_fmt_rd_csr_zimm "O\t0,c,7" | ||
| 553 | -#define rv_fmt_rs2_offset_rs1 "O\t2,i(1)" | ||
| 554 | -#define rv_fmt_frs2_offset_rs1 "O\t5,i(1)" | ||
| 555 | -#define rv_fmt_rs1_rs2_offset "O\t1,2,o" | ||
| 556 | -#define rv_fmt_rs2_rs1_offset "O\t2,1,o" | ||
| 557 | -#define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)" | ||
| 558 | -#define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)" | ||
| 559 | -#define rv_fmt_rd "O\t0" | ||
| 560 | -#define rv_fmt_rd_zimm "O\t0,7" | ||
| 561 | -#define rv_fmt_rd_rs1 "O\t0,1" | ||
| 562 | -#define rv_fmt_rd_rs2 "O\t0,2" | ||
| 563 | -#define rv_fmt_rs1_offset "O\t1,o" | ||
| 564 | -#define rv_fmt_rs2_offset "O\t2,o" | ||
| 565 | -#define rv_fmt_rs1_rs2_bs "O\t1,2,b" | ||
| 566 | -#define rv_fmt_rd_rs1_rnum "O\t0,1,n" | ||
| 567 | -#define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" | ||
| 568 | -#define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" | ||
| 569 | -#define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" | ||
| 570 | -#define rv_fmt_vd_vs2_vs1 "O\tD,F,E" | ||
| 571 | -#define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" | ||
| 572 | -#define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" | ||
| 573 | -#define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" | ||
| 574 | -#define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" | ||
| 575 | -#define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" | ||
| 576 | -#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" | ||
| 577 | -#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" | ||
| 578 | -#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" | ||
| 579 | -#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" | ||
| 580 | -#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" | ||
| 581 | -#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" | ||
| 582 | -#define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" | ||
| 583 | -#define rv_fmt_vd_vs1 "O\tD,E" | ||
| 584 | -#define rv_fmt_vd_rs1 "O\tD,1" | ||
| 585 | -#define rv_fmt_vd_fs1 "O\tD,4" | ||
| 586 | -#define rv_fmt_vd_imm "O\tD,i" | ||
| 587 | -#define rv_fmt_vd_vs2 "O\tD,F" | ||
| 588 | -#define rv_fmt_vd_vs2_vm "O\tD,Fm" | ||
| 589 | -#define rv_fmt_rd_vs2_vm "O\t0,Fm" | ||
| 590 | -#define rv_fmt_rd_vs2 "O\t0,F" | ||
| 591 | -#define rv_fmt_fd_vs2 "O\t3,F" | ||
| 592 | -#define rv_fmt_vd_vm "O\tDm" | ||
| 593 | -#define rv_fmt_vsetvli "O\t0,1,v" | ||
| 594 | -#define rv_fmt_vsetivli "O\t0,u,v" | ||
| 595 | -#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" | ||
| 596 | -#define rv_fmt_push_rlist "O\tx,-i" | ||
| 597 | -#define rv_fmt_pop_rlist "O\tx,i" | ||
| 598 | -#define rv_fmt_zcmt_index "O\ti" | ||
| 599 | - | ||
| 600 | /* pseudo-instruction constraints */ | ||
| 601 | |||
| 602 | static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; | ||
| 603 | -- | ||
| 604 | 2.40.1 | ||
| 605 | |||
| 606 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | The enum value 'rv_op_illegal' does not represent an | ||
| 4 | instruction, but is a catch-all value in case we have | ||
| 5 | no match in the decoder. Let's make the value a shared | ||
| 6 | one, so that other compile units can reuse it. | ||
| 7 | |||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 10 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 11 | Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu> | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | disas/riscv.h | 4 ++++ | ||
| 15 | disas/riscv.c | 2 +- | ||
| 16 | 2 files changed, 5 insertions(+), 1 deletion(-) | ||
| 17 | |||
| 18 | diff --git a/disas/riscv.h b/disas/riscv.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/disas/riscv.h | ||
| 21 | +++ b/disas/riscv.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 23 | const rvc_constraint *constraints; | ||
| 24 | } rv_comp_data; | ||
| 25 | |||
| 26 | +enum { | ||
| 27 | + rv_op_illegal = 0 | ||
| 28 | +}; | ||
| 29 | + | ||
| 30 | enum { | ||
| 31 | rvcd_imm_nz = 0x1 | ||
| 32 | }; | ||
| 33 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/disas/riscv.c | ||
| 36 | +++ b/disas/riscv.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ | ||
| 38 | #include "disas/riscv.h" | ||
| 39 | |||
| 40 | typedef enum { | ||
| 41 | - rv_op_illegal = 0, | ||
| 42 | + /* 0 is reserved for rv_op_illegal. */ | ||
| 43 | rv_op_lui = 1, | ||
| 44 | rv_op_auipc = 2, | ||
| 45 | rv_op_jal = 3, | ||
| 46 | -- | ||
| 47 | 2.40.1 | ||
| 48 | |||
| 49 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | This patch adds a reference to a struct rv_opcode_data object | ||
| 4 | into struct rv_decode. This further allows to remove all references | ||
| 5 | to the global variable opcode_data (which is renamed to rvi_opcode_data). | ||
| 6 | |||
| 7 | This patch does not introduce any functional change, but prepares | ||
| 8 | the code for more struct rv_opcode_data objects in the future. | ||
| 9 | |||
| 10 | This patch is based on previous work from Liu Zhiwei: | ||
| 11 | https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html | ||
| 12 | |||
| 13 | Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 16 | Message-Id: <20230612111034.3955227-6-christoph.muellner@vrull.eu> | ||
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 18 | --- | ||
| 19 | disas/riscv.h | 33 +++++++++++++++++---------------- | ||
| 20 | disas/riscv.c | 9 ++++++++- | ||
| 21 | 2 files changed, 25 insertions(+), 17 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/disas/riscv.h b/disas/riscv.h | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/disas/riscv.h | ||
| 26 | +++ b/disas/riscv.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 28 | |||
| 29 | /* structures */ | ||
| 30 | |||
| 31 | +typedef struct { | ||
| 32 | + const int op; | ||
| 33 | + const rvc_constraint *constraints; | ||
| 34 | +} rv_comp_data; | ||
| 35 | + | ||
| 36 | +typedef struct { | ||
| 37 | + const char * const name; | ||
| 38 | + const rv_codec codec; | ||
| 39 | + const char * const format; | ||
| 40 | + const rv_comp_data *pseudo; | ||
| 41 | + const short decomp_rv32; | ||
| 42 | + const short decomp_rv64; | ||
| 43 | + const short decomp_rv128; | ||
| 44 | + const short decomp_data; | ||
| 45 | +} rv_opcode_data; | ||
| 46 | + | ||
| 47 | typedef struct { | ||
| 48 | RISCVCPUConfig *cfg; | ||
| 49 | uint64_t pc; | ||
| 50 | uint64_t inst; | ||
| 51 | + const rv_opcode_data *opcode_data; | ||
| 52 | int32_t imm; | ||
| 53 | uint16_t op; | ||
| 54 | uint8_t codec; | ||
| 55 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 56 | uint8_t rlist; | ||
| 57 | } rv_decode; | ||
| 58 | |||
| 59 | -typedef struct { | ||
| 60 | - const int op; | ||
| 61 | - const rvc_constraint *constraints; | ||
| 62 | -} rv_comp_data; | ||
| 63 | - | ||
| 64 | enum { | ||
| 65 | rv_op_illegal = 0 | ||
| 66 | }; | ||
| 67 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 68 | rvcd_imm_nz = 0x1 | ||
| 69 | }; | ||
| 70 | |||
| 71 | -typedef struct { | ||
| 72 | - const char * const name; | ||
| 73 | - const rv_codec codec; | ||
| 74 | - const char * const format; | ||
| 75 | - const rv_comp_data *pseudo; | ||
| 76 | - const short decomp_rv32; | ||
| 77 | - const short decomp_rv64; | ||
| 78 | - const short decomp_rv128; | ||
| 79 | - const short decomp_data; | ||
| 80 | -} rv_opcode_data; | ||
| 81 | - | ||
| 82 | /* instruction formats */ | ||
| 83 | |||
| 84 | #define rv_fmt_none "O\t" | ||
| 85 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 86 | index XXXXXXX..XXXXXXX 100644 | ||
| 87 | --- a/disas/riscv.c | ||
| 88 | +++ b/disas/riscv.c | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static const rv_comp_data rvcp_fsgnjx_q[] = { | ||
| 90 | |||
| 91 | /* instruction metadata */ | ||
| 92 | |||
| 93 | -const rv_opcode_data opcode_data[] = { | ||
| 94 | +const rv_opcode_data rvi_opcode_data[] = { | ||
| 95 | { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 96 | { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 }, | ||
| 97 | { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 }, | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static uint32_t operand_tbl_index(rv_inst inst) | ||
| 99 | |||
| 100 | static void decode_inst_operands(rv_decode *dec, rv_isa isa) | ||
| 101 | { | ||
| 102 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 103 | rv_inst inst = dec->inst; | ||
| 104 | dec->codec = opcode_data[dec->op].codec; | ||
| 105 | switch (dec->codec) { | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static void append(char *s1, const char *s2, size_t n) | ||
| 107 | |||
| 108 | static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 109 | { | ||
| 110 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 111 | char tmp[64]; | ||
| 112 | const char *fmt; | ||
| 113 | |||
| 114 | @@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 115 | |||
| 116 | static void decode_inst_lift_pseudo(rv_decode *dec) | ||
| 117 | { | ||
| 118 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 119 | const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; | ||
| 120 | if (!comp_data) { | ||
| 121 | return; | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_lift_pseudo(rv_decode *dec) | ||
| 123 | |||
| 124 | static void decode_inst_decompress_rv32(rv_decode *dec) | ||
| 125 | { | ||
| 126 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 127 | int decomp_op = opcode_data[dec->op].decomp_rv32; | ||
| 128 | if (decomp_op != rv_op_illegal) { | ||
| 129 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_decompress_rv32(rv_decode *dec) | ||
| 131 | |||
| 132 | static void decode_inst_decompress_rv64(rv_decode *dec) | ||
| 133 | { | ||
| 134 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 135 | int decomp_op = opcode_data[dec->op].decomp_rv64; | ||
| 136 | if (decomp_op != rv_op_illegal) { | ||
| 137 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) | ||
| 138 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_decompress_rv64(rv_decode *dec) | ||
| 139 | |||
| 140 | static void decode_inst_decompress_rv128(rv_decode *dec) | ||
| 141 | { | ||
| 142 | + const rv_opcode_data *opcode_data = dec->opcode_data; | ||
| 143 | int decomp_op = opcode_data[dec->op].decomp_rv128; | ||
| 144 | if (decomp_op != rv_op_illegal) { | ||
| 145 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) | ||
| 146 | @@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, | ||
| 147 | rv_decode dec = { 0 }; | ||
| 148 | dec.pc = pc; | ||
| 149 | dec.inst = inst; | ||
| 150 | + dec.opcode_data = rvi_opcode_data; | ||
| 151 | dec.cfg = cfg; | ||
| 152 | decode_inst_opcode(&dec, isa); | ||
| 153 | decode_inst_operands(&dec, isa); | ||
| 154 | -- | ||
| 155 | 2.40.1 | ||
| 156 | |||
| 157 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | A previous patch provides a pointer to the RISCVCPUConfig data. | ||
| 4 | Let's use this to add the necessary code for vendor extensions. | ||
| 5 | This patch does not change the current behaviour, but clearly | ||
| 6 | defines how vendor extension support can be added to the disassembler. | ||
| 7 | |||
| 8 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 11 | Message-Id: <20230612111034.3955227-7-christoph.muellner@vrull.eu> | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | disas/riscv.c | 28 ++++++++++++++++++++++++++-- | ||
| 15 | 1 file changed, 26 insertions(+), 2 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/disas/riscv.c | ||
| 20 | +++ b/disas/riscv.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, | ||
| 22 | rv_decode dec = { 0 }; | ||
| 23 | dec.pc = pc; | ||
| 24 | dec.inst = inst; | ||
| 25 | - dec.opcode_data = rvi_opcode_data; | ||
| 26 | dec.cfg = cfg; | ||
| 27 | - decode_inst_opcode(&dec, isa); | ||
| 28 | + | ||
| 29 | + static const struct { | ||
| 30 | + bool (*guard_func)(const RISCVCPUConfig *); | ||
| 31 | + const rv_opcode_data *opcode_data; | ||
| 32 | + void (*decode_func)(rv_decode *, rv_isa); | ||
| 33 | + } decoders[] = { | ||
| 34 | + { always_true_p, rvi_opcode_data, decode_inst_opcode }, | ||
| 35 | + }; | ||
| 36 | + | ||
| 37 | + for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { | ||
| 38 | + bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; | ||
| 39 | + const rv_opcode_data *opcode_data = decoders[i].opcode_data; | ||
| 40 | + void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; | ||
| 41 | + | ||
| 42 | + if (guard_func(cfg)) { | ||
| 43 | + dec.opcode_data = opcode_data; | ||
| 44 | + decode_func(&dec, isa); | ||
| 45 | + if (dec.op != rv_op_illegal) | ||
| 46 | + break; | ||
| 47 | + } | ||
| 48 | + } | ||
| 49 | + | ||
| 50 | + if (dec.op == rv_op_illegal) { | ||
| 51 | + dec.opcode_data = rvi_opcode_data; | ||
| 52 | + } | ||
| 53 | + | ||
| 54 | decode_inst_operands(&dec, isa); | ||
| 55 | decode_inst_decompress(&dec, isa); | ||
| 56 | decode_inst_lift_pseudo(&dec); | ||
| 57 | -- | ||
| 58 | 2.40.1 | ||
| 59 | |||
| 60 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | This patch adds XVentanaCondOps support to the RISC-V disassembler. | ||
| 4 | |||
| 5 | Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 6 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 7 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 9 | Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | disas/riscv-xventana.h | 18 ++++++++++++++++++ | ||
| 13 | disas/riscv-xventana.c | 41 +++++++++++++++++++++++++++++++++++++++++ | ||
| 14 | disas/riscv.c | 4 ++++ | ||
| 15 | disas/meson.build | 5 ++++- | ||
| 16 | 4 files changed, 67 insertions(+), 1 deletion(-) | ||
| 17 | create mode 100644 disas/riscv-xventana.h | ||
| 18 | create mode 100644 disas/riscv-xventana.c | ||
| 19 | |||
| 20 | diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h | ||
| 21 | new file mode 100644 | ||
| 22 | index XXXXXXX..XXXXXXX | ||
| 23 | --- /dev/null | ||
| 24 | +++ b/disas/riscv-xventana.h | ||
| 25 | @@ -XXX,XX +XXX,XX @@ | ||
| 26 | +/* | ||
| 27 | + * QEMU disassembler -- RISC-V specific header (xventana*). | ||
| 28 | + * | ||
| 29 | + * Copyright (c) 2023 VRULL GmbH | ||
| 30 | + * | ||
| 31 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 32 | + */ | ||
| 33 | + | ||
| 34 | +#ifndef DISAS_RISCV_XVENTANA_H | ||
| 35 | +#define DISAS_RISCV_XVENTANA_H | ||
| 36 | + | ||
| 37 | +#include "disas/riscv.h" | ||
| 38 | + | ||
| 39 | +extern const rv_opcode_data ventana_opcode_data[]; | ||
| 40 | + | ||
| 41 | +void decode_xventanacondops(rv_decode*, rv_isa); | ||
| 42 | + | ||
| 43 | +#endif /* DISAS_RISCV_XVENTANA_H */ | ||
| 44 | diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c | ||
| 45 | new file mode 100644 | ||
| 46 | index XXXXXXX..XXXXXXX | ||
| 47 | --- /dev/null | ||
| 48 | +++ b/disas/riscv-xventana.c | ||
| 49 | @@ -XXX,XX +XXX,XX @@ | ||
| 50 | +/* | ||
| 51 | + * QEMU RISC-V Disassembler for xventana. | ||
| 52 | + * | ||
| 53 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 54 | + */ | ||
| 55 | + | ||
| 56 | +#include "disas/riscv.h" | ||
| 57 | +#include "disas/riscv-xventana.h" | ||
| 58 | + | ||
| 59 | +typedef enum { | ||
| 60 | + /* 0 is reserved for rv_op_illegal. */ | ||
| 61 | + ventana_op_vt_maskc = 1, | ||
| 62 | + ventana_op_vt_maskcn = 2, | ||
| 63 | +} rv_ventana_op; | ||
| 64 | + | ||
| 65 | +const rv_opcode_data ventana_opcode_data[] = { | ||
| 66 | + { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 67 | + { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 68 | + { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 69 | +}; | ||
| 70 | + | ||
| 71 | +void decode_xventanacondops(rv_decode *dec, rv_isa isa) | ||
| 72 | +{ | ||
| 73 | + rv_inst inst = dec->inst; | ||
| 74 | + rv_opcode op = rv_op_illegal; | ||
| 75 | + | ||
| 76 | + switch (((inst >> 0) & 0b11)) { | ||
| 77 | + case 3: | ||
| 78 | + switch (((inst >> 2) & 0b11111)) { | ||
| 79 | + case 30: | ||
| 80 | + switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { | ||
| 81 | + case 6: op = ventana_op_vt_maskc; break; | ||
| 82 | + case 7: op = ventana_op_vt_maskcn; break; | ||
| 83 | + } | ||
| 84 | + break; | ||
| 85 | + } | ||
| 86 | + break; | ||
| 87 | + } | ||
| 88 | + | ||
| 89 | + dec->op = op; | ||
| 90 | +} | ||
| 91 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 92 | index XXXXXXX..XXXXXXX 100644 | ||
| 93 | --- a/disas/riscv.c | ||
| 94 | +++ b/disas/riscv.c | ||
| 95 | @@ -XXX,XX +XXX,XX @@ | ||
| 96 | #include "target/riscv/cpu_cfg.h" | ||
| 97 | #include "disas/riscv.h" | ||
| 98 | |||
| 99 | +/* Vendor extensions */ | ||
| 100 | +#include "disas/riscv-xventana.h" | ||
| 101 | + | ||
| 102 | typedef enum { | ||
| 103 | /* 0 is reserved for rv_op_illegal. */ | ||
| 104 | rv_op_lui = 1, | ||
| 105 | @@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, | ||
| 106 | void (*decode_func)(rv_decode *, rv_isa); | ||
| 107 | } decoders[] = { | ||
| 108 | { always_true_p, rvi_opcode_data, decode_inst_opcode }, | ||
| 109 | + { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, | ||
| 110 | }; | ||
| 111 | |||
| 112 | for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { | ||
| 113 | diff --git a/disas/meson.build b/disas/meson.build | ||
| 114 | index XXXXXXX..XXXXXXX 100644 | ||
| 115 | --- a/disas/meson.build | ||
| 116 | +++ b/disas/meson.build | ||
| 117 | @@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c')) | ||
| 118 | common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c')) | ||
| 119 | common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c')) | ||
| 120 | common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c')) | ||
| 121 | -common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('riscv.c')) | ||
| 122 | +common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( | ||
| 123 | + 'riscv.c', | ||
| 124 | + 'riscv-xventana.c' | ||
| 125 | +)) | ||
| 126 | common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) | ||
| 127 | common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) | ||
| 128 | common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c')) | ||
| 129 | -- | ||
| 130 | 2.40.1 | ||
| 131 | |||
| 132 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 1 | 2 | ||
| 3 | Support for emulating XThead* instruction has been added recently. | ||
| 4 | This patch adds support for these instructions to the RISC-V disassembler. | ||
| 5 | |||
| 6 | Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 7 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 9 | Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | disas/riscv-xthead.h | 28 ++ | ||
| 13 | disas/riscv.h | 12 + | ||
| 14 | target/riscv/cpu_cfg.h | 11 + | ||
| 15 | disas/riscv-xthead.c | 707 +++++++++++++++++++++++++++++++++++++++++ | ||
| 16 | disas/riscv.c | 69 ++++ | ||
| 17 | disas/meson.build | 1 + | ||
| 18 | 6 files changed, 828 insertions(+) | ||
| 19 | create mode 100644 disas/riscv-xthead.h | ||
| 20 | create mode 100644 disas/riscv-xthead.c | ||
| 21 | |||
| 22 | diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h | ||
| 23 | new file mode 100644 | ||
| 24 | index XXXXXXX..XXXXXXX | ||
| 25 | --- /dev/null | ||
| 26 | +++ b/disas/riscv-xthead.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ | ||
| 28 | +/* | ||
| 29 | + * QEMU disassembler -- RISC-V specific header (xthead*). | ||
| 30 | + * | ||
| 31 | + * Copyright (c) 2023 VRULL GmbH | ||
| 32 | + * | ||
| 33 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 34 | + */ | ||
| 35 | + | ||
| 36 | +#ifndef DISAS_RISCV_XTHEAD_H | ||
| 37 | +#define DISAS_RISCV_XTHEAD_H | ||
| 38 | + | ||
| 39 | +#include "disas/riscv.h" | ||
| 40 | + | ||
| 41 | +extern const rv_opcode_data xthead_opcode_data[]; | ||
| 42 | + | ||
| 43 | +void decode_xtheadba(rv_decode *, rv_isa); | ||
| 44 | +void decode_xtheadbb(rv_decode *, rv_isa); | ||
| 45 | +void decode_xtheadbs(rv_decode *, rv_isa); | ||
| 46 | +void decode_xtheadcmo(rv_decode *, rv_isa); | ||
| 47 | +void decode_xtheadcondmov(rv_decode *, rv_isa); | ||
| 48 | +void decode_xtheadfmemidx(rv_decode *, rv_isa); | ||
| 49 | +void decode_xtheadfmv(rv_decode *, rv_isa); | ||
| 50 | +void decode_xtheadmac(rv_decode *, rv_isa); | ||
| 51 | +void decode_xtheadmemidx(rv_decode *, rv_isa); | ||
| 52 | +void decode_xtheadmempair(rv_decode *, rv_isa); | ||
| 53 | +void decode_xtheadsync(rv_decode *, rv_isa); | ||
| 54 | + | ||
| 55 | +#endif /* DISAS_RISCV_XTHEAD_H */ | ||
| 56 | diff --git a/disas/riscv.h b/disas/riscv.h | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | ||
| 58 | --- a/disas/riscv.h | ||
| 59 | +++ b/disas/riscv.h | ||
| 60 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 61 | rv_codec_zcmp_cm_pushpop, | ||
| 62 | rv_codec_zcmp_cm_mv, | ||
| 63 | rv_codec_zcmt_jt, | ||
| 64 | + rv_codec_r2_imm5, | ||
| 65 | + rv_codec_r2, | ||
| 66 | + rv_codec_r2_imm6, | ||
| 67 | + rv_codec_r_imm2, | ||
| 68 | + rv_codec_r2_immhl, | ||
| 69 | + rv_codec_r2_imm2_imm5, | ||
| 70 | } rv_codec; | ||
| 71 | |||
| 72 | /* structures */ | ||
| 73 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 74 | uint64_t inst; | ||
| 75 | const rv_opcode_data *opcode_data; | ||
| 76 | int32_t imm; | ||
| 77 | + int32_t imm1; | ||
| 78 | uint16_t op; | ||
| 79 | uint8_t codec; | ||
| 80 | uint8_t rd; | ||
| 81 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 82 | #define rv_fmt_push_rlist "O\tx,-i" | ||
| 83 | #define rv_fmt_pop_rlist "O\tx,i" | ||
| 84 | #define rv_fmt_zcmt_index "O\ti" | ||
| 85 | +#define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i" | ||
| 86 | +#define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i" | ||
| 87 | +#define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j" | ||
| 88 | +#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j" | ||
| 89 | +#define rv_fmt_rd2_imm "O\t0,2,(1),i" | ||
| 90 | |||
| 91 | #endif /* DISAS_RISCV_H */ | ||
| 92 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
| 93 | index XXXXXXX..XXXXXXX 100644 | ||
| 94 | --- a/target/riscv/cpu_cfg.h | ||
| 95 | +++ b/target/riscv/cpu_cfg.h | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static inline bool has_xthead_p(const RISCVCPUConfig *cfg) | ||
| 97 | return cfg->ext_ ## ext ; \ | ||
| 98 | } | ||
| 99 | |||
| 100 | +MATERIALISE_EXT_PREDICATE(xtheadba) | ||
| 101 | +MATERIALISE_EXT_PREDICATE(xtheadbb) | ||
| 102 | +MATERIALISE_EXT_PREDICATE(xtheadbs) | ||
| 103 | +MATERIALISE_EXT_PREDICATE(xtheadcmo) | ||
| 104 | +MATERIALISE_EXT_PREDICATE(xtheadcondmov) | ||
| 105 | +MATERIALISE_EXT_PREDICATE(xtheadfmemidx) | ||
| 106 | +MATERIALISE_EXT_PREDICATE(xtheadfmv) | ||
| 107 | +MATERIALISE_EXT_PREDICATE(xtheadmac) | ||
| 108 | +MATERIALISE_EXT_PREDICATE(xtheadmemidx) | ||
| 109 | +MATERIALISE_EXT_PREDICATE(xtheadmempair) | ||
| 110 | +MATERIALISE_EXT_PREDICATE(xtheadsync) | ||
| 111 | MATERIALISE_EXT_PREDICATE(XVentanaCondOps) | ||
| 112 | |||
| 113 | #endif | ||
| 114 | diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c | ||
| 115 | new file mode 100644 | ||
| 116 | index XXXXXXX..XXXXXXX | ||
| 117 | --- /dev/null | ||
| 118 | +++ b/disas/riscv-xthead.c | ||
| 119 | @@ -XXX,XX +XXX,XX @@ | ||
| 120 | +/* | ||
| 121 | + * QEMU RISC-V Disassembler for xthead. | ||
| 122 | + * | ||
| 123 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 124 | + */ | ||
| 125 | + | ||
| 126 | +#include "disas/riscv.h" | ||
| 127 | +#include "disas/riscv-xthead.h" | ||
| 128 | + | ||
| 129 | +typedef enum { | ||
| 130 | + /* 0 is reserved for rv_op_illegal. */ | ||
| 131 | + /* XTheadBa */ | ||
| 132 | + rv_op_th_addsl = 1, | ||
| 133 | + /* XTheadBb */ | ||
| 134 | + rv_op_th_srri, | ||
| 135 | + rv_op_th_srriw, | ||
| 136 | + rv_op_th_ext, | ||
| 137 | + rv_op_th_extu, | ||
| 138 | + rv_op_th_ff0, | ||
| 139 | + rv_op_th_ff1, | ||
| 140 | + rv_op_th_rev, | ||
| 141 | + rv_op_th_revw, | ||
| 142 | + rv_op_th_tstnbz, | ||
| 143 | + /* XTheadBs */ | ||
| 144 | + rv_op_th_tst, | ||
| 145 | + /* XTheadCmo */ | ||
| 146 | + rv_op_th_dcache_call, | ||
| 147 | + rv_op_th_dcache_ciall, | ||
| 148 | + rv_op_th_dcache_iall, | ||
| 149 | + rv_op_th_dcache_cpa, | ||
| 150 | + rv_op_th_dcache_cipa, | ||
| 151 | + rv_op_th_dcache_ipa, | ||
| 152 | + rv_op_th_dcache_cva, | ||
| 153 | + rv_op_th_dcache_civa, | ||
| 154 | + rv_op_th_dcache_iva, | ||
| 155 | + rv_op_th_dcache_csw, | ||
| 156 | + rv_op_th_dcache_cisw, | ||
| 157 | + rv_op_th_dcache_isw, | ||
| 158 | + rv_op_th_dcache_cpal1, | ||
| 159 | + rv_op_th_dcache_cval1, | ||
| 160 | + rv_op_th_icache_iall, | ||
| 161 | + rv_op_th_icache_ialls, | ||
| 162 | + rv_op_th_icache_ipa, | ||
| 163 | + rv_op_th_icache_iva, | ||
| 164 | + rv_op_th_l2cache_call, | ||
| 165 | + rv_op_th_l2cache_ciall, | ||
| 166 | + rv_op_th_l2cache_iall, | ||
| 167 | + /* XTheadCondMov */ | ||
| 168 | + rv_op_th_mveqz, | ||
| 169 | + rv_op_th_mvnez, | ||
| 170 | + /* XTheadFMemIdx */ | ||
| 171 | + rv_op_th_flrd, | ||
| 172 | + rv_op_th_flrw, | ||
| 173 | + rv_op_th_flurd, | ||
| 174 | + rv_op_th_flurw, | ||
| 175 | + rv_op_th_fsrd, | ||
| 176 | + rv_op_th_fsrw, | ||
| 177 | + rv_op_th_fsurd, | ||
| 178 | + rv_op_th_fsurw, | ||
| 179 | + /* XTheadFmv */ | ||
| 180 | + rv_op_th_fmv_hw_x, | ||
| 181 | + rv_op_th_fmv_x_hw, | ||
| 182 | + /* XTheadMac */ | ||
| 183 | + rv_op_th_mula, | ||
| 184 | + rv_op_th_mulah, | ||
| 185 | + rv_op_th_mulaw, | ||
| 186 | + rv_op_th_muls, | ||
| 187 | + rv_op_th_mulsw, | ||
| 188 | + rv_op_th_mulsh, | ||
| 189 | + /* XTheadMemIdx */ | ||
| 190 | + rv_op_th_lbia, | ||
| 191 | + rv_op_th_lbib, | ||
| 192 | + rv_op_th_lbuia, | ||
| 193 | + rv_op_th_lbuib, | ||
| 194 | + rv_op_th_lhia, | ||
| 195 | + rv_op_th_lhib, | ||
| 196 | + rv_op_th_lhuia, | ||
| 197 | + rv_op_th_lhuib, | ||
| 198 | + rv_op_th_lwia, | ||
| 199 | + rv_op_th_lwib, | ||
| 200 | + rv_op_th_lwuia, | ||
| 201 | + rv_op_th_lwuib, | ||
| 202 | + rv_op_th_ldia, | ||
| 203 | + rv_op_th_ldib, | ||
| 204 | + rv_op_th_sbia, | ||
| 205 | + rv_op_th_sbib, | ||
| 206 | + rv_op_th_shia, | ||
| 207 | + rv_op_th_shib, | ||
| 208 | + rv_op_th_swia, | ||
| 209 | + rv_op_th_swib, | ||
| 210 | + rv_op_th_sdia, | ||
| 211 | + rv_op_th_sdib, | ||
| 212 | + rv_op_th_lrb, | ||
| 213 | + rv_op_th_lrbu, | ||
| 214 | + rv_op_th_lrh, | ||
| 215 | + rv_op_th_lrhu, | ||
| 216 | + rv_op_th_lrw, | ||
| 217 | + rv_op_th_lrwu, | ||
| 218 | + rv_op_th_lrd, | ||
| 219 | + rv_op_th_srb, | ||
| 220 | + rv_op_th_srh, | ||
| 221 | + rv_op_th_srw, | ||
| 222 | + rv_op_th_srd, | ||
| 223 | + rv_op_th_lurb, | ||
| 224 | + rv_op_th_lurbu, | ||
| 225 | + rv_op_th_lurh, | ||
| 226 | + rv_op_th_lurhu, | ||
| 227 | + rv_op_th_lurw, | ||
| 228 | + rv_op_th_lurwu, | ||
| 229 | + rv_op_th_lurd, | ||
| 230 | + rv_op_th_surb, | ||
| 231 | + rv_op_th_surh, | ||
| 232 | + rv_op_th_surw, | ||
| 233 | + rv_op_th_surd, | ||
| 234 | + /* XTheadMemPair */ | ||
| 235 | + rv_op_th_ldd, | ||
| 236 | + rv_op_th_lwd, | ||
| 237 | + rv_op_th_lwud, | ||
| 238 | + rv_op_th_sdd, | ||
| 239 | + rv_op_th_swd, | ||
| 240 | + /* XTheadSync */ | ||
| 241 | + rv_op_th_sfence_vmas, | ||
| 242 | + rv_op_th_sync, | ||
| 243 | + rv_op_th_sync_i, | ||
| 244 | + rv_op_th_sync_is, | ||
| 245 | + rv_op_th_sync_s, | ||
| 246 | +} rv_xthead_op; | ||
| 247 | + | ||
| 248 | +const rv_opcode_data xthead_opcode_data[] = { | ||
| 249 | + { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 250 | + /* XTheadBa */ | ||
| 251 | + { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 252 | + /* XTheadBb */ | ||
| 253 | + { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, | ||
| 254 | + { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, | ||
| 255 | + { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 }, | ||
| 256 | + { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 }, | ||
| 257 | + { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 258 | + { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 259 | + { "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 260 | + { "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 261 | + { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 262 | + /* XTheadBs */ | ||
| 263 | + { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, | ||
| 264 | + /* XTheadCmo */ | ||
| 265 | + { "th.dcache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 266 | + { "th.dcache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 267 | + { "th.dcache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 268 | + { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 269 | + { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 270 | + { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 271 | + { "th.dcache.cva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 272 | + { "th.dcache.civa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 273 | + { "th.dcache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 274 | + { "th.dcache.csw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 275 | + { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 276 | + { "th.dcache.isw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 277 | + { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 278 | + { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 279 | + { "th.icache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 280 | + { "th.icache.ialls", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 281 | + { "th.icache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 282 | + { "th.icache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, | ||
| 283 | + { "th.l2cache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 284 | + { "th.l2cache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 285 | + { "th.l2cache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 286 | + /* XTheadCondMov */ | ||
| 287 | + { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 288 | + { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 289 | + /* XTheadFMemIdx */ | ||
| 290 | + { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 291 | + { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 292 | + { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 293 | + { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 294 | + { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 295 | + { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 296 | + { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 297 | + { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 298 | + /* XTheadFmv */ | ||
| 299 | + { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 300 | + { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 301 | + /* XTheadMac */ | ||
| 302 | + { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 303 | + { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 304 | + { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 305 | + { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 306 | + { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 307 | + { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 308 | + /* XTheadMemIdx */ | ||
| 309 | + { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 310 | + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 }, | ||
| 311 | + { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 312 | + { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 313 | + { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 314 | + { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 315 | + { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 316 | + { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 317 | + { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 318 | + { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 319 | + { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 320 | + { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 321 | + { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 322 | + { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 323 | + { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 324 | + { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 325 | + { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 326 | + { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 327 | + { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 328 | + { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 329 | + { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 330 | + { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, | ||
| 331 | + { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 332 | + { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 333 | + { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 334 | + { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 335 | + { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 336 | + { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 337 | + { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 338 | + { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 339 | + { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 340 | + { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 341 | + { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 342 | + { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 343 | + { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 344 | + { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 345 | + { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 346 | + { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 347 | + { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 348 | + { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 349 | + { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 350 | + { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 351 | + { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 352 | + { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, | ||
| 353 | + /* XTheadMemPair */ | ||
| 354 | + { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, | ||
| 355 | + { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, | ||
| 356 | + { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, | ||
| 357 | + { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, | ||
| 358 | + { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, | ||
| 359 | + /* XTheadSync */ | ||
| 360 | + { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 361 | + { "th.sync", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 362 | + { "th.sync.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 363 | + { "th.sync.is", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 364 | + { "th.sync.s", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, | ||
| 365 | +}; | ||
| 366 | + | ||
| 367 | +void decode_xtheadba(rv_decode *dec, rv_isa isa) | ||
| 368 | +{ | ||
| 369 | + rv_inst inst = dec->inst; | ||
| 370 | + rv_opcode op = rv_op_illegal; | ||
| 371 | + | ||
| 372 | + switch (((inst >> 0) & 0b11)) { | ||
| 373 | + case 3: | ||
| 374 | + switch (((inst >> 2) & 0b11111)) { | ||
| 375 | + case 2: | ||
| 376 | + /* custom-0 */ | ||
| 377 | + switch ((inst >> 12) & 0b111) { | ||
| 378 | + case 1: | ||
| 379 | + switch ((inst >> 25) & 0b1111111) { | ||
| 380 | + case 0b0000000: | ||
| 381 | + case 0b0000001: | ||
| 382 | + case 0b0000010: | ||
| 383 | + case 0b0000011: op = rv_op_th_addsl; break; | ||
| 384 | + } | ||
| 385 | + break; | ||
| 386 | + } | ||
| 387 | + break; | ||
| 388 | + /* custom-0 */ | ||
| 389 | + } | ||
| 390 | + break; | ||
| 391 | + } | ||
| 392 | + | ||
| 393 | + dec->op = op; | ||
| 394 | +} | ||
| 395 | + | ||
| 396 | +void decode_xtheadbb(rv_decode *dec, rv_isa isa) | ||
| 397 | +{ | ||
| 398 | + rv_inst inst = dec->inst; | ||
| 399 | + rv_opcode op = rv_op_illegal; | ||
| 400 | + | ||
| 401 | + switch (((inst >> 0) & 0b11)) { | ||
| 402 | + case 3: | ||
| 403 | + switch (((inst >> 2) & 0b11111)) { | ||
| 404 | + case 2: | ||
| 405 | + /* custom-0 */ | ||
| 406 | + switch ((inst >> 12) & 0b111) { | ||
| 407 | + case 1: | ||
| 408 | + switch ((inst >> 25) & 0b1111111) { | ||
| 409 | + case 0b0001010: op = rv_op_th_srriw; break; | ||
| 410 | + case 0b1000000: | ||
| 411 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 412 | + op = rv_op_th_tstnbz; | ||
| 413 | + } | ||
| 414 | + break; | ||
| 415 | + case 0b1000001: | ||
| 416 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 417 | + op = rv_op_th_rev; | ||
| 418 | + } | ||
| 419 | + break; | ||
| 420 | + case 0b1000010: | ||
| 421 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 422 | + op = rv_op_th_ff0; | ||
| 423 | + } | ||
| 424 | + break; | ||
| 425 | + case 0b1000011: | ||
| 426 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 427 | + op = rv_op_th_ff1; | ||
| 428 | + } | ||
| 429 | + break; | ||
| 430 | + case 0b1000100: | ||
| 431 | + case 0b1001000: | ||
| 432 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 433 | + op = rv_op_th_revw; | ||
| 434 | + } | ||
| 435 | + break; | ||
| 436 | + case 0b0000100: | ||
| 437 | + case 0b0000101: op = rv_op_th_srri; break; | ||
| 438 | + } | ||
| 439 | + break; | ||
| 440 | + case 2: op = rv_op_th_ext; break; | ||
| 441 | + case 3: op = rv_op_th_extu; break; | ||
| 442 | + } | ||
| 443 | + break; | ||
| 444 | + /* custom-0 */ | ||
| 445 | + } | ||
| 446 | + break; | ||
| 447 | + } | ||
| 448 | + | ||
| 449 | + dec->op = op; | ||
| 450 | +} | ||
| 451 | + | ||
| 452 | +void decode_xtheadbs(rv_decode *dec, rv_isa isa) | ||
| 453 | +{ | ||
| 454 | + rv_inst inst = dec->inst; | ||
| 455 | + rv_opcode op = rv_op_illegal; | ||
| 456 | + | ||
| 457 | + switch (((inst >> 0) & 0b11)) { | ||
| 458 | + case 3: | ||
| 459 | + switch (((inst >> 2) & 0b11111)) { | ||
| 460 | + case 2: | ||
| 461 | + /* custom-0 */ | ||
| 462 | + switch ((inst >> 12) & 0b111) { | ||
| 463 | + case 1: | ||
| 464 | + switch ((inst >> 26) & 0b111111) { | ||
| 465 | + case 0b100010: op = rv_op_th_tst; break; | ||
| 466 | + } | ||
| 467 | + break; | ||
| 468 | + } | ||
| 469 | + break; | ||
| 470 | + /* custom-0 */ | ||
| 471 | + } | ||
| 472 | + break; | ||
| 473 | + } | ||
| 474 | + | ||
| 475 | + dec->op = op; | ||
| 476 | +} | ||
| 477 | + | ||
| 478 | +void decode_xtheadcmo(rv_decode *dec, rv_isa isa) | ||
| 479 | +{ | ||
| 480 | + rv_inst inst = dec->inst; | ||
| 481 | + rv_opcode op = rv_op_illegal; | ||
| 482 | + | ||
| 483 | + switch (((inst >> 0) & 0b11)) { | ||
| 484 | + case 3: | ||
| 485 | + switch (((inst >> 2) & 0b11111)) { | ||
| 486 | + case 2: | ||
| 487 | + /* custom-0 */ | ||
| 488 | + switch ((inst >> 12) & 0b111) { | ||
| 489 | + case 0: | ||
| 490 | + switch ((inst >> 20 & 0b111111111111)) { | ||
| 491 | + case 0b000000000001: | ||
| 492 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 493 | + op = rv_op_th_dcache_call; | ||
| 494 | + } | ||
| 495 | + break; | ||
| 496 | + case 0b000000000011: | ||
| 497 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 498 | + op = rv_op_th_dcache_ciall; | ||
| 499 | + } | ||
| 500 | + break; | ||
| 501 | + case 0b000000000010: | ||
| 502 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 503 | + op = rv_op_th_dcache_iall; | ||
| 504 | + } | ||
| 505 | + break; | ||
| 506 | + case 0b000000101001: op = rv_op_th_dcache_cpa; break; | ||
| 507 | + case 0b000000101011: op = rv_op_th_dcache_cipa; break; | ||
| 508 | + case 0b000000101010: op = rv_op_th_dcache_ipa; break; | ||
| 509 | + case 0b000000100101: op = rv_op_th_dcache_cva; break; | ||
| 510 | + case 0b000000100111: op = rv_op_th_dcache_civa; break; | ||
| 511 | + case 0b000000100110: op = rv_op_th_dcache_iva; break; | ||
| 512 | + case 0b000000100001: op = rv_op_th_dcache_csw; break; | ||
| 513 | + case 0b000000100011: op = rv_op_th_dcache_cisw; break; | ||
| 514 | + case 0b000000100010: op = rv_op_th_dcache_isw; break; | ||
| 515 | + case 0b000000101000: op = rv_op_th_dcache_cpal1; break; | ||
| 516 | + case 0b000000100100: op = rv_op_th_dcache_cval1; break; | ||
| 517 | + case 0b000000010000: | ||
| 518 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 519 | + op = rv_op_th_icache_iall; | ||
| 520 | + } | ||
| 521 | + break; | ||
| 522 | + case 0b000000010001: | ||
| 523 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 524 | + op = rv_op_th_icache_ialls; | ||
| 525 | + } | ||
| 526 | + break; | ||
| 527 | + case 0b000000111000: op = rv_op_th_icache_ipa; break; | ||
| 528 | + case 0b000000110000: op = rv_op_th_icache_iva; break; | ||
| 529 | + case 0b000000010101: | ||
| 530 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 531 | + op = rv_op_th_l2cache_call; | ||
| 532 | + } | ||
| 533 | + break; | ||
| 534 | + case 0b000000010111: | ||
| 535 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 536 | + op = rv_op_th_l2cache_ciall; | ||
| 537 | + } | ||
| 538 | + break; | ||
| 539 | + case 0b000000010110: | ||
| 540 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 541 | + op = rv_op_th_l2cache_iall; | ||
| 542 | + } | ||
| 543 | + break; | ||
| 544 | + } | ||
| 545 | + break; | ||
| 546 | + } | ||
| 547 | + break; | ||
| 548 | + /* custom-0 */ | ||
| 549 | + } | ||
| 550 | + break; | ||
| 551 | + } | ||
| 552 | + | ||
| 553 | + dec->op = op; | ||
| 554 | +} | ||
| 555 | + | ||
| 556 | +void decode_xtheadcondmov(rv_decode *dec, rv_isa isa) | ||
| 557 | +{ | ||
| 558 | + rv_inst inst = dec->inst; | ||
| 559 | + rv_opcode op = rv_op_illegal; | ||
| 560 | + | ||
| 561 | + switch (((inst >> 0) & 0b11)) { | ||
| 562 | + case 3: | ||
| 563 | + switch (((inst >> 2) & 0b11111)) { | ||
| 564 | + case 2: | ||
| 565 | + /* custom-0 */ | ||
| 566 | + switch ((inst >> 12) & 0b111) { | ||
| 567 | + case 1: | ||
| 568 | + switch ((inst >> 25) & 0b1111111) { | ||
| 569 | + case 0b0100000: op = rv_op_th_mveqz; break; | ||
| 570 | + case 0b0100001: op = rv_op_th_mvnez; break; | ||
| 571 | + } | ||
| 572 | + break; | ||
| 573 | + } | ||
| 574 | + break; | ||
| 575 | + /* custom-0 */ | ||
| 576 | + } | ||
| 577 | + break; | ||
| 578 | + } | ||
| 579 | + | ||
| 580 | + dec->op = op; | ||
| 581 | +} | ||
| 582 | + | ||
| 583 | +void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa) | ||
| 584 | +{ | ||
| 585 | + rv_inst inst = dec->inst; | ||
| 586 | + rv_opcode op = rv_op_illegal; | ||
| 587 | + | ||
| 588 | + switch (((inst >> 0) & 0b11)) { | ||
| 589 | + case 3: | ||
| 590 | + switch (((inst >> 2) & 0b11111)) { | ||
| 591 | + case 2: | ||
| 592 | + /* custom-0 */ | ||
| 593 | + switch ((inst >> 12) & 0b111) { | ||
| 594 | + case 6: | ||
| 595 | + switch ((inst >> 27) & 0b11111) { | ||
| 596 | + case 8: op = rv_op_th_flrw; break; | ||
| 597 | + case 10: op = rv_op_th_flurw; break; | ||
| 598 | + case 12: op = rv_op_th_flrd; break; | ||
| 599 | + case 14: op = rv_op_th_flurd; break; | ||
| 600 | + } | ||
| 601 | + break; | ||
| 602 | + case 7: | ||
| 603 | + switch ((inst >> 27) & 0b11111) { | ||
| 604 | + case 8: op = rv_op_th_fsrw; break; | ||
| 605 | + case 10: op = rv_op_th_fsurw; break; | ||
| 606 | + case 12: op = rv_op_th_fsrd; break; | ||
| 607 | + case 14: op = rv_op_th_fsurd; break; | ||
| 608 | + } | ||
| 609 | + break; | ||
| 610 | + } | ||
| 611 | + break; | ||
| 612 | + /* custom-0 */ | ||
| 613 | + } | ||
| 614 | + break; | ||
| 615 | + } | ||
| 616 | + | ||
| 617 | + dec->op = op; | ||
| 618 | +} | ||
| 619 | + | ||
| 620 | +void decode_xtheadfmv(rv_decode *dec, rv_isa isa) | ||
| 621 | +{ | ||
| 622 | + rv_inst inst = dec->inst; | ||
| 623 | + rv_opcode op = rv_op_illegal; | ||
| 624 | + | ||
| 625 | + switch (((inst >> 0) & 0b11)) { | ||
| 626 | + case 3: | ||
| 627 | + switch (((inst >> 2) & 0b11111)) { | ||
| 628 | + case 2: | ||
| 629 | + /* custom-0 */ | ||
| 630 | + switch ((inst >> 12) & 0b111) { | ||
| 631 | + case 1: | ||
| 632 | + switch ((inst >> 25) & 0b1111111) { | ||
| 633 | + case 0b1010000: | ||
| 634 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 635 | + op = rv_op_th_fmv_hw_x; | ||
| 636 | + } | ||
| 637 | + break; | ||
| 638 | + case 0b1100000: | ||
| 639 | + if (((inst >> 20) & 0b11111) == 0) { | ||
| 640 | + op = rv_op_th_fmv_x_hw; | ||
| 641 | + } | ||
| 642 | + break; | ||
| 643 | + } | ||
| 644 | + break; | ||
| 645 | + } | ||
| 646 | + break; | ||
| 647 | + /* custom-0 */ | ||
| 648 | + } | ||
| 649 | + break; | ||
| 650 | + } | ||
| 651 | + | ||
| 652 | + dec->op = op; | ||
| 653 | +} | ||
| 654 | + | ||
| 655 | +void decode_xtheadmac(rv_decode *dec, rv_isa isa) | ||
| 656 | +{ | ||
| 657 | + rv_inst inst = dec->inst; | ||
| 658 | + rv_opcode op = rv_op_illegal; | ||
| 659 | + | ||
| 660 | + switch (((inst >> 0) & 0b11)) { | ||
| 661 | + case 3: | ||
| 662 | + switch (((inst >> 2) & 0b11111)) { | ||
| 663 | + case 2: | ||
| 664 | + /* custom-0 */ | ||
| 665 | + switch ((inst >> 12) & 0b111) { | ||
| 666 | + case 1: | ||
| 667 | + switch ((inst >> 25) & 0b1111111) { | ||
| 668 | + case 0b0010000: op = rv_op_th_mula; break; | ||
| 669 | + case 0b0010001: op = rv_op_th_muls; break; | ||
| 670 | + case 0b0010010: op = rv_op_th_mulaw; break; | ||
| 671 | + case 0b0010011: op = rv_op_th_mulsw; break; | ||
| 672 | + case 0b0010100: op = rv_op_th_mulah; break; | ||
| 673 | + case 0b0010101: op = rv_op_th_mulsh; break; | ||
| 674 | + } | ||
| 675 | + break; | ||
| 676 | + } | ||
| 677 | + break; | ||
| 678 | + /* custom-0 */ | ||
| 679 | + } | ||
| 680 | + break; | ||
| 681 | + } | ||
| 682 | + | ||
| 683 | + dec->op = op; | ||
| 684 | +} | ||
| 685 | + | ||
| 686 | +void decode_xtheadmemidx(rv_decode *dec, rv_isa isa) | ||
| 687 | +{ | ||
| 688 | + rv_inst inst = dec->inst; | ||
| 689 | + rv_opcode op = rv_op_illegal; | ||
| 690 | + | ||
| 691 | + switch (((inst >> 0) & 0b11)) { | ||
| 692 | + case 3: | ||
| 693 | + switch (((inst >> 2) & 0b11111)) { | ||
| 694 | + case 2: | ||
| 695 | + /* custom-0 */ | ||
| 696 | + switch ((inst >> 12) & 0b111) { | ||
| 697 | + case 4: | ||
| 698 | + switch ((inst >> 27) & 0b11111) { | ||
| 699 | + case 0: op = rv_op_th_lrb; break; | ||
| 700 | + case 1: op = rv_op_th_lbib; break; | ||
| 701 | + case 2: op = rv_op_th_lurb; break; | ||
| 702 | + case 3: op = rv_op_th_lbia; break; | ||
| 703 | + case 4: op = rv_op_th_lrh; break; | ||
| 704 | + case 5: op = rv_op_th_lhib; break; | ||
| 705 | + case 6: op = rv_op_th_lurh; break; | ||
| 706 | + case 7: op = rv_op_th_lhia; break; | ||
| 707 | + case 8: op = rv_op_th_lrw; break; | ||
| 708 | + case 9: op = rv_op_th_lwib; break; | ||
| 709 | + case 10: op = rv_op_th_lurw; break; | ||
| 710 | + case 11: op = rv_op_th_lwia; break; | ||
| 711 | + case 12: op = rv_op_th_lrd; break; | ||
| 712 | + case 13: op = rv_op_th_ldib; break; | ||
| 713 | + case 14: op = rv_op_th_lurd; break; | ||
| 714 | + case 15: op = rv_op_th_ldia; break; | ||
| 715 | + case 16: op = rv_op_th_lrbu; break; | ||
| 716 | + case 17: op = rv_op_th_lbuib; break; | ||
| 717 | + case 18: op = rv_op_th_lurbu; break; | ||
| 718 | + case 19: op = rv_op_th_lbuia; break; | ||
| 719 | + case 20: op = rv_op_th_lrhu; break; | ||
| 720 | + case 21: op = rv_op_th_lhuib; break; | ||
| 721 | + case 22: op = rv_op_th_lurhu; break; | ||
| 722 | + case 23: op = rv_op_th_lhuia; break; | ||
| 723 | + case 24: op = rv_op_th_lrwu; break; | ||
| 724 | + case 25: op = rv_op_th_lwuib; break; | ||
| 725 | + case 26: op = rv_op_th_lurwu; break; | ||
| 726 | + case 27: op = rv_op_th_lwuia; break; | ||
| 727 | + } | ||
| 728 | + break; | ||
| 729 | + case 5: | ||
| 730 | + switch ((inst >> 27) & 0b11111) { | ||
| 731 | + case 0: op = rv_op_th_srb; break; | ||
| 732 | + case 1: op = rv_op_th_sbib; break; | ||
| 733 | + case 2: op = rv_op_th_surb; break; | ||
| 734 | + case 3: op = rv_op_th_sbia; break; | ||
| 735 | + case 4: op = rv_op_th_srh; break; | ||
| 736 | + case 5: op = rv_op_th_shib; break; | ||
| 737 | + case 6: op = rv_op_th_surh; break; | ||
| 738 | + case 7: op = rv_op_th_shia; break; | ||
| 739 | + case 8: op = rv_op_th_srw; break; | ||
| 740 | + case 9: op = rv_op_th_swib; break; | ||
| 741 | + case 10: op = rv_op_th_surw; break; | ||
| 742 | + case 11: op = rv_op_th_swia; break; | ||
| 743 | + case 12: op = rv_op_th_srd; break; | ||
| 744 | + case 13: op = rv_op_th_sdib; break; | ||
| 745 | + case 14: op = rv_op_th_surd; break; | ||
| 746 | + case 15: op = rv_op_th_sdia; break; | ||
| 747 | + } | ||
| 748 | + break; | ||
| 749 | + break; | ||
| 750 | + } | ||
| 751 | + break; | ||
| 752 | + /* custom-0 */ | ||
| 753 | + } | ||
| 754 | + break; | ||
| 755 | + } | ||
| 756 | + | ||
| 757 | + dec->op = op; | ||
| 758 | +} | ||
| 759 | + | ||
| 760 | +void decode_xtheadmempair(rv_decode *dec, rv_isa isa) | ||
| 761 | +{ | ||
| 762 | + rv_inst inst = dec->inst; | ||
| 763 | + rv_opcode op = rv_op_illegal; | ||
| 764 | + | ||
| 765 | + switch (((inst >> 0) & 0b11)) { | ||
| 766 | + case 3: | ||
| 767 | + switch (((inst >> 2) & 0b11111)) { | ||
| 768 | + case 2: | ||
| 769 | + /* custom-0 */ | ||
| 770 | + switch ((inst >> 12) & 0b111) { | ||
| 771 | + case 4: | ||
| 772 | + switch ((inst >> 27) & 0b11111) { | ||
| 773 | + case 28: op = rv_op_th_lwd; break; | ||
| 774 | + case 30: op = rv_op_th_lwud; break; | ||
| 775 | + case 31: op = rv_op_th_ldd; break; | ||
| 776 | + } | ||
| 777 | + break; | ||
| 778 | + case 5: | ||
| 779 | + switch ((inst >> 27) & 0b11111) { | ||
| 780 | + case 28: op = rv_op_th_swd; break; | ||
| 781 | + case 31: op = rv_op_th_sdd; break; | ||
| 782 | + } | ||
| 783 | + break; | ||
| 784 | + } | ||
| 785 | + break; | ||
| 786 | + /* custom-0 */ | ||
| 787 | + } | ||
| 788 | + break; | ||
| 789 | + } | ||
| 790 | + | ||
| 791 | + dec->op = op; | ||
| 792 | +} | ||
| 793 | + | ||
| 794 | +void decode_xtheadsync(rv_decode *dec, rv_isa isa) | ||
| 795 | +{ | ||
| 796 | + rv_inst inst = dec->inst; | ||
| 797 | + rv_opcode op = rv_op_illegal; | ||
| 798 | + | ||
| 799 | + switch (((inst >> 0) & 0b11)) { | ||
| 800 | + case 3: | ||
| 801 | + switch (((inst >> 2) & 0b11111)) { | ||
| 802 | + case 2: | ||
| 803 | + /* custom-0 */ | ||
| 804 | + switch ((inst >> 12) & 0b111) { | ||
| 805 | + case 0: | ||
| 806 | + switch ((inst >> 25) & 0b1111111) { | ||
| 807 | + case 0b0000010: op = rv_op_th_sfence_vmas; break; | ||
| 808 | + case 0b0000000: | ||
| 809 | + switch ((inst >> 20) & 0b11111) { | ||
| 810 | + case 0b11000: op = rv_op_th_sync; break; | ||
| 811 | + case 0b11010: op = rv_op_th_sync_i; break; | ||
| 812 | + case 0b11011: op = rv_op_th_sync_is; break; | ||
| 813 | + case 0b11001: op = rv_op_th_sync_s; break; | ||
| 814 | + } | ||
| 815 | + break; | ||
| 816 | + } | ||
| 817 | + break; | ||
| 818 | + } | ||
| 819 | + break; | ||
| 820 | + /* custom-0 */ | ||
| 821 | + } | ||
| 822 | + break; | ||
| 823 | + } | ||
| 824 | + | ||
| 825 | + dec->op = op; | ||
| 826 | +} | ||
| 827 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 828 | index XXXXXXX..XXXXXXX 100644 | ||
| 829 | --- a/disas/riscv.c | ||
| 830 | +++ b/disas/riscv.c | ||
| 831 | @@ -XXX,XX +XXX,XX @@ | ||
| 832 | */ | ||
| 833 | |||
| 834 | #include "qemu/osdep.h" | ||
| 835 | +#include "qemu/bitops.h" | ||
| 836 | #include "disas/dis-asm.h" | ||
| 837 | #include "target/riscv/cpu_cfg.h" | ||
| 838 | #include "disas/riscv.h" | ||
| 839 | |||
| 840 | /* Vendor extensions */ | ||
| 841 | +#include "disas/riscv-xthead.h" | ||
| 842 | #include "disas/riscv-xventana.h" | ||
| 843 | |||
| 844 | typedef enum { | ||
| 845 | @@ -XXX,XX +XXX,XX @@ static uint32_t operand_zcmp_rlist(rv_inst inst) | ||
| 846 | return ((inst << 56) >> 60); | ||
| 847 | } | ||
| 848 | |||
| 849 | +static uint32_t operand_imm6(rv_inst inst) | ||
| 850 | +{ | ||
| 851 | + return (inst << 38) >> 60; | ||
| 852 | +} | ||
| 853 | + | ||
| 854 | +static uint32_t operand_imm2(rv_inst inst) | ||
| 855 | +{ | ||
| 856 | + return (inst << 37) >> 62; | ||
| 857 | +} | ||
| 858 | + | ||
| 859 | +static uint32_t operand_immh(rv_inst inst) | ||
| 860 | +{ | ||
| 861 | + return (inst << 32) >> 58; | ||
| 862 | +} | ||
| 863 | + | ||
| 864 | +static uint32_t operand_imml(rv_inst inst) | ||
| 865 | +{ | ||
| 866 | + return (inst << 38) >> 58; | ||
| 867 | +} | ||
| 868 | + | ||
| 869 | static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) | ||
| 870 | { | ||
| 871 | int xlen_bytes_log2 = isa == rv64 ? 3 : 2; | ||
| 872 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) | ||
| 873 | case rv_codec_zcmt_jt: | ||
| 874 | dec->imm = operand_tbl_index(inst); | ||
| 875 | break; | ||
| 876 | + case rv_codec_r2_imm5: | ||
| 877 | + dec->rd = operand_rd(inst); | ||
| 878 | + dec->rs1 = operand_rs1(inst); | ||
| 879 | + dec->imm = operand_rs2(inst); | ||
| 880 | + break; | ||
| 881 | + case rv_codec_r2: | ||
| 882 | + dec->rd = operand_rd(inst); | ||
| 883 | + dec->rs1 = operand_rs1(inst); | ||
| 884 | + break; | ||
| 885 | + case rv_codec_r2_imm6: | ||
| 886 | + dec->rd = operand_rd(inst); | ||
| 887 | + dec->rs1 = operand_rs1(inst); | ||
| 888 | + dec->imm = operand_imm6(inst); | ||
| 889 | + break; | ||
| 890 | + case rv_codec_r_imm2: | ||
| 891 | + dec->rd = operand_rd(inst); | ||
| 892 | + dec->rs1 = operand_rs1(inst); | ||
| 893 | + dec->rs2 = operand_rs2(inst); | ||
| 894 | + dec->imm = operand_imm2(inst); | ||
| 895 | + break; | ||
| 896 | + case rv_codec_r2_immhl: | ||
| 897 | + dec->rd = operand_rd(inst); | ||
| 898 | + dec->rs1 = operand_rs1(inst); | ||
| 899 | + dec->imm = operand_immh(inst); | ||
| 900 | + dec->imm1 = operand_imml(inst); | ||
| 901 | + break; | ||
| 902 | + case rv_codec_r2_imm2_imm5: | ||
| 903 | + dec->rd = operand_rd(inst); | ||
| 904 | + dec->rs1 = operand_rs1(inst); | ||
| 905 | + dec->imm = sextract32(operand_rs2(inst), 0, 5); | ||
| 906 | + dec->imm1 = operand_imm2(inst); | ||
| 907 | + break; | ||
| 908 | }; | ||
| 909 | } | ||
| 910 | |||
| 911 | @@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 912 | snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); | ||
| 913 | append(buf, tmp, buflen); | ||
| 914 | break; | ||
| 915 | + case 'j': | ||
| 916 | + snprintf(tmp, sizeof(tmp), "%d", dec->imm1); | ||
| 917 | + append(buf, tmp, buflen); | ||
| 918 | + break; | ||
| 919 | case 'o': | ||
| 920 | snprintf(tmp, sizeof(tmp), "%d", dec->imm); | ||
| 921 | append(buf, tmp, buflen); | ||
| 922 | @@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, | ||
| 923 | void (*decode_func)(rv_decode *, rv_isa); | ||
| 924 | } decoders[] = { | ||
| 925 | { always_true_p, rvi_opcode_data, decode_inst_opcode }, | ||
| 926 | + { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, | ||
| 927 | + { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, | ||
| 928 | + { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, | ||
| 929 | + { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, | ||
| 930 | + { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, | ||
| 931 | + { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, | ||
| 932 | + { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, | ||
| 933 | + { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, | ||
| 934 | + { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, | ||
| 935 | + { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, | ||
| 936 | + { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, | ||
| 937 | { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, | ||
| 938 | }; | ||
| 939 | |||
| 940 | diff --git a/disas/meson.build b/disas/meson.build | ||
| 941 | index XXXXXXX..XXXXXXX 100644 | ||
| 942 | --- a/disas/meson.build | ||
| 943 | +++ b/disas/meson.build | ||
| 944 | @@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c')) | ||
| 945 | common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c')) | ||
| 946 | common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( | ||
| 947 | 'riscv.c', | ||
| 948 | + 'riscv-xthead.c', | ||
| 949 | 'riscv-xventana.c' | ||
| 950 | )) | ||
| 951 | common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) | ||
| 952 | -- | ||
| 953 | 2.40.1 | ||
| 954 | |||
| 955 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The current condition for the use of background registers only | 3 | Upon MRET or explicit memory access with MPRV=1, MPV should be ignored |
| 4 | considers the hypervisor load and store instructions, | 4 | when MPP=PRV_M. |
| 5 | but not accesses from M mode via MSTATUS_MPRV+MPV. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 6 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> |
| 7 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 9 | Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com | 10 | Message-Id: <20230603134236.15719-2-liweiwei@iscas.ac.cn> |
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 12 | --- |
| 12 | target/riscv/cpu_helper.c | 2 +- | 13 | target/riscv/cpu_helper.c | 3 ++- |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | target/riscv/op_helper.c | 3 ++- |
| 15 | 2 files changed, 4 insertions(+), 2 deletions(-) | ||
| 14 | 16 | ||
| 15 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 17 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/riscv/cpu_helper.c | 19 | --- a/target/riscv/cpu_helper.c |
| 18 | +++ b/target/riscv/cpu_helper.c | 20 | +++ b/target/riscv/cpu_helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, | 21 | @@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) |
| 20 | * was called. Background registers will be used if the guest has | 22 | |
| 21 | * forced a two stage translation to be on (in HS or M mode). | 23 | if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { |
| 22 | */ | 24 | mode = get_field(env->mstatus, MSTATUS_MPP); |
| 23 | - if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) { | 25 | - virt = get_field(env->mstatus, MSTATUS_MPV); |
| 24 | + if (!riscv_cpu_virt_enabled(env) && two_stage) { | 26 | + virt = get_field(env->mstatus, MSTATUS_MPV) && |
| 25 | use_background = true; | 27 | + (mode != PRV_M); |
| 28 | if (virt) { | ||
| 29 | status = env->vsstatus; | ||
| 30 | } | ||
| 31 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/target/riscv/op_helper.c | ||
| 34 | +++ b/target/riscv/op_helper.c | ||
| 35 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env) | ||
| 36 | riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); | ||
| 26 | } | 37 | } |
| 27 | 38 | ||
| 39 | - target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); | ||
| 40 | + target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) && | ||
| 41 | + (prev_priv != PRV_M); | ||
| 42 | mstatus = set_field(mstatus, MSTATUS_MIE, | ||
| 43 | get_field(mstatus, MSTATUS_MPIE)); | ||
| 44 | mstatus = set_field(mstatus, MSTATUS_MPIE, 1); | ||
| 28 | -- | 45 | -- |
| 29 | 2.30.1 | 46 | 2.40.1 |
| 30 | |||
| 31 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 3 | MPV and GVA bits are added by hypervisor extension to mstatus |
| 4 | and mstatush (if MXLEN=32). | ||
| 5 | |||
| 6 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 7 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 5 | Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com | 10 | Message-Id: <20230603134236.15719-3-liweiwei@iscas.ac.cn> |
| 6 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 7 | --- | 12 | --- |
| 8 | target/riscv/csr.c | 7 ++++--- | 13 | target/riscv/csr.c | 10 ++++------ |
| 9 | 1 file changed, 4 insertions(+), 3 deletions(-) | 14 | 1 file changed, 4 insertions(+), 6 deletions(-) |
| 10 | 15 | ||
| 11 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/riscv/csr.c | 18 | --- a/target/riscv/csr.c |
| 14 | +++ b/target/riscv/csr.c | 19 | +++ b/target/riscv/csr.c |
| 15 | @@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | 20 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
| 16 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | 21 | } |
| 17 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; | 22 | |
| 18 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; | 23 | if (xl != MXL_RV32 || env->debugger) { |
| 19 | -static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | 24 | - /* |
| 20 | +static const target_ulong hip_writable_mask = MIP_VSSIP; | 25 | - * RV32: MPV and GVA are not in mstatus. The current plan is to |
| 21 | +static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | 26 | - * add them to mstatush. For now, we just don't support it. |
| 22 | static const target_ulong vsip_writable_mask = MIP_VSSIP; | 27 | - */ |
| 23 | 28 | - mask |= MSTATUS_MPV | MSTATUS_GVA; | |
| 24 | static const char valid_vm_1_10_32[16] = { | 29 | + if (riscv_has_ext(env, RVH)) { |
| 25 | @@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, | 30 | + mask |= MSTATUS_MPV | MSTATUS_GVA; |
| 26 | target_ulong new_value, target_ulong write_mask) | 31 | + } |
| 32 | if ((val & MSTATUS64_UXL) != 0) { | ||
| 33 | mask |= MSTATUS64_UXL; | ||
| 34 | } | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, | ||
| 36 | target_ulong val) | ||
| 27 | { | 37 | { |
| 28 | int ret = rmw_mip(env, 0, ret_value, new_value, | 38 | uint64_t valh = (uint64_t)val << 32; |
| 29 | - write_mask & hip_writable_mask); | 39 | - uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; |
| 30 | + write_mask & hvip_writable_mask); | 40 | + uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; |
| 31 | 41 | ||
| 32 | - *ret_value &= hip_writable_mask; | 42 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
| 33 | + *ret_value &= hvip_writable_mask; | 43 | |
| 34 | |||
| 35 | return ret; | ||
| 36 | } | ||
| 37 | -- | 44 | -- |
| 38 | 2.30.1 | 45 | 2.40.1 |
| 39 | |||
| 40 | diff view generated by jsdifflib |
| 1 | From: Frank Chang <frank.chang@sifive.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature | 3 | SXL is initialized as env->misa_mxl which is also the mxl value. |
| 4 | is not enabled. | 4 | So we can just remain it unchanged to keep it read-only. |
| 5 | 5 | ||
| 6 | If -1 is returned, exception will be raised and cs->exception_index will | 6 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> |
| 7 | be set to the negative return value. The exception will then be treated | 7 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> |
| 8 | as an instruction access fault instead of illegal instruction fault. | 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
| 9 | |||
| 10 | Signed-off-by: Frank Chang <frank.chang@sifive.com> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | Message-id: 20210223065935.20208-1-frank.chang@sifive.com | 10 | Message-Id: <20230603134236.15719-4-liweiwei@iscas.ac.cn> |
| 14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 15 | --- | 12 | --- |
| 16 | target/riscv/csr.c | 2 +- | 13 | target/riscv/csr.c | 4 ---- |
| 17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 4 deletions(-) |
| 18 | 15 | ||
| 19 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/riscv/csr.c | 18 | --- a/target/riscv/csr.c |
| 22 | +++ b/target/riscv/csr.c | 19 | +++ b/target/riscv/csr.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno) | 20 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
| 24 | if (env->misa & RVV) { | 21 | |
| 25 | return 0; | 22 | mstatus = (mstatus & ~mask) | (val & mask); |
| 26 | } | 23 | |
| 27 | - return -1; | 24 | - if (xl > MXL_RV32) { |
| 28 | + return -RISCV_EXCP_ILLEGAL_INST; | 25 | - /* SXL field is for now read only */ |
| 29 | } | 26 | - mstatus = set_field(mstatus, MSTATUS64_SXL, xl); |
| 30 | 27 | - } | |
| 31 | static int ctr(CPURISCVState *env, int csrno) | 28 | env->mstatus = mstatus; |
| 29 | |||
| 30 | /* | ||
| 32 | -- | 31 | -- |
| 33 | 2.30.1 | 32 | 2.40.1 |
| 34 | |||
| 35 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from | ||
| 4 | riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei | ||
| 5 | and ext_icsr from riscv_cpu_init(), the init() function of | ||
| 6 | TYPE_RISCV_CPU, parent type of all RISC-V CPUss. This was done to force | ||
| 7 | CPUs to explictly enable all extensions and features it requires, | ||
| 8 | without any 'magic values' that were inherited by the parent type. | ||
| 9 | |||
| 10 | This commit failed to make appropriate changes in the 'veyron-v1' CPU, | ||
| 11 | added earlier by commit e1d084a8524a. The result is that the veyron-v1 | ||
| 12 | CPU has ext_ifencei, ext_icsr and pmp set to 'false', which is not the | ||
| 13 | case. | ||
| 14 | |||
| 15 | The reason why it took this long to notice (thanks LIU Zhiwei for | ||
| 16 | reporting it) is because Linux doesn't mind 'ifencei' and 'icsr' being | ||
| 17 | absent in the 'riscv,isa' DT, implying that they're both present if the | ||
| 18 | 'i' extension is enabled. OpenSBI also doesn't error out or warns about | ||
| 19 | the lack of 'pmp', it'll just not protect memory pages. | ||
| 20 | |||
| 21 | Fix it by setting them to 'true' in rv64_veyron_v1_cpu_init() like | ||
| 22 | 7f0bdfb5bfc2 already did with other CPUs. | ||
| 23 | |||
| 24 | Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 25 | Fixes: 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") | ||
| 26 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 27 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 28 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
| 29 | Message-Id: <20230620152443.137079-1-dbarboza@ventanamicro.com> | ||
| 30 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 31 | --- | ||
| 32 | target/riscv/cpu.c | 3 +++ | ||
| 33 | 1 file changed, 3 insertions(+) | ||
| 34 | |||
| 35 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/riscv/cpu.c | ||
| 38 | +++ b/target/riscv/cpu.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj) | ||
| 40 | |||
| 41 | /* Enable ISA extensions */ | ||
| 42 | cpu->cfg.mmu = true; | ||
| 43 | + cpu->cfg.ext_ifencei = true; | ||
| 44 | + cpu->cfg.ext_icsr = true; | ||
| 45 | + cpu->cfg.pmp = true; | ||
| 46 | cpu->cfg.ext_icbom = true; | ||
| 47 | cpu->cfg.cbom_blocksize = 64; | ||
| 48 | cpu->cfg.cboz_blocksize = 64; | ||
| 49 | -- | ||
| 50 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When decode_insn16() fails, we fall back to decode_RV32_64C() for | 3 | As specified in privilege spec:"When MPRV=1, load and store memory |
| 4 | further compressed instruction decoding. However, prior to this change, | 4 | addresses are treated as though the current XLEN were set to MPP’s |
| 5 | we did not raise an illegal instruction exception, if decode_RV32_64C() | 5 | XLEN". So the xlen for address may be different from current xlen. |
| 6 | fails to decode the instruction. This means that we skipped illegal | ||
| 7 | compressed instructions instead of raising an illegal instruction | ||
| 8 | exception. | ||
| 9 | 6 | ||
| 10 | Instead of patching decode_RV32_64C(), we can just remove it, | 7 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> |
| 11 | as it is dead code since f330433b363 anyway. | 8 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> |
| 12 | 9 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
| 13 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 10 | Message-Id: <20230614032547.35895-2-liweiwei@iscas.ac.cn> |
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 16 | Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com | ||
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 18 | --- | 12 | --- |
| 19 | target/riscv/translate.c | 179 +-------------------------------------- | 13 | target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------ |
| 20 | 1 file changed, 1 insertion(+), 178 deletions(-) | 14 | target/riscv/cpu_helper.c | 1 + |
| 15 | target/riscv/translate.c | 13 ++++++++++- | ||
| 16 | 3 files changed, 55 insertions(+), 8 deletions(-) | ||
| 21 | 17 | ||
| 18 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/riscv/cpu.h | ||
| 21 | +++ b/target/riscv/cpu.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) | ||
| 23 | /* Virtual mode enabled */ | ||
| 24 | FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) | ||
| 25 | FIELD(TB_FLAGS, PRIV, 24, 2) | ||
| 26 | +FIELD(TB_FLAGS, AXL, 26, 2) | ||
| 27 | |||
| 28 | #ifdef TARGET_RISCV32 | ||
| 29 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) | ||
| 31 | return &env_archcpu(env)->cfg; | ||
| 32 | } | ||
| 33 | |||
| 34 | -#if defined(TARGET_RISCV32) | ||
| 35 | -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | ||
| 36 | -#else | ||
| 37 | -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | ||
| 38 | +#if !defined(CONFIG_USER_ONLY) | ||
| 39 | +static inline int cpu_address_mode(CPURISCVState *env) | ||
| 40 | +{ | ||
| 41 | + int mode = env->priv; | ||
| 42 | + | ||
| 43 | + if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 44 | + mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 45 | + } | ||
| 46 | + return mode; | ||
| 47 | +} | ||
| 48 | + | ||
| 49 | +static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) | ||
| 50 | { | ||
| 51 | RISCVMXL xl = env->misa_mxl; | ||
| 52 | -#if !defined(CONFIG_USER_ONLY) | ||
| 53 | /* | ||
| 54 | * When emulating a 32-bit-only cpu, use RV32. | ||
| 55 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | ||
| 57 | * back to RV64 for lower privs. | ||
| 58 | */ | ||
| 59 | if (xl != MXL_RV32) { | ||
| 60 | - switch (env->priv) { | ||
| 61 | + switch (mode) { | ||
| 62 | case PRV_M: | ||
| 63 | break; | ||
| 64 | case PRV_U: | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | } | ||
| 69 | -#endif | ||
| 70 | return xl; | ||
| 71 | } | ||
| 72 | #endif | ||
| 73 | |||
| 74 | +#if defined(TARGET_RISCV32) | ||
| 75 | +#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) | ||
| 76 | +#else | ||
| 77 | +static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) | ||
| 78 | +{ | ||
| 79 | +#if !defined(CONFIG_USER_ONLY) | ||
| 80 | + return cpu_get_xl(env, env->priv); | ||
| 81 | +#else | ||
| 82 | + return env->misa_mxl; | ||
| 83 | +#endif | ||
| 84 | +} | ||
| 85 | +#endif | ||
| 86 | + | ||
| 87 | +#if defined(TARGET_RISCV32) | ||
| 88 | +#define cpu_address_xl(env) ((void)(env), MXL_RV32) | ||
| 89 | +#else | ||
| 90 | +static inline RISCVMXL cpu_address_xl(CPURISCVState *env) | ||
| 91 | +{ | ||
| 92 | +#ifdef CONFIG_USER_ONLY | ||
| 93 | + return env->xl; | ||
| 94 | +#else | ||
| 95 | + int mode = cpu_address_mode(env); | ||
| 96 | + | ||
| 97 | + return cpu_get_xl(env, mode); | ||
| 98 | +#endif | ||
| 99 | +} | ||
| 100 | +#endif | ||
| 101 | + | ||
| 102 | static inline int riscv_cpu_xlen(CPURISCVState *env) | ||
| 103 | { | ||
| 104 | return 16 << env->xl; | ||
| 105 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | ||
| 106 | index XXXXXXX..XXXXXXX 100644 | ||
| 107 | --- a/target/riscv/cpu_helper.c | ||
| 108 | +++ b/target/riscv/cpu_helper.c | ||
| 109 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, | ||
| 110 | flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); | ||
| 111 | flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); | ||
| 112 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); | ||
| 113 | + flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); | ||
| 114 | if (env->cur_pmmask != 0) { | ||
| 115 | flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); | ||
| 116 | } | ||
| 22 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | 117 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c |
| 23 | index XXXXXXX..XXXXXXX 100644 | 118 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/target/riscv/translate.c | 119 | --- a/target/riscv/translate.c |
| 25 | +++ b/target/riscv/translate.c | 120 | +++ b/target/riscv/translate.c |
| 26 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 121 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
| 27 | CPUState *cs; | 122 | target_ulong priv_ver; |
| 28 | } DisasContext; | 123 | RISCVMXL misa_mxl_max; |
| 29 | 124 | RISCVMXL xl; | |
| 30 | -#ifdef TARGET_RISCV64 | 125 | + RISCVMXL address_xl; |
| 31 | -/* convert riscv funct3 to qemu memop for load/store */ | 126 | uint32_t misa_ext; |
| 32 | -static const int tcg_memop_lookup[8] = { | 127 | uint32_t opcode; |
| 33 | - [0 ... 7] = -1, | 128 | RISCVExtStatus mstatus_fs; |
| 34 | - [0] = MO_SB, | 129 | @@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
| 35 | - [1] = MO_TESW, | 130 | #define get_xl(ctx) ((ctx)->xl) |
| 36 | - [2] = MO_TESL, | 131 | #endif |
| 37 | - [3] = MO_TEQ, | 132 | |
| 38 | - [4] = MO_UB, | 133 | +#ifdef TARGET_RISCV32 |
| 39 | - [5] = MO_TEUW, | 134 | +#define get_address_xl(ctx) MXL_RV32 |
| 40 | - [6] = MO_TEUL, | 135 | +#elif defined(CONFIG_USER_ONLY) |
| 41 | -}; | 136 | +#define get_address_xl(ctx) MXL_RV64 |
| 42 | -#endif | 137 | +#else |
| 43 | - | 138 | +#define get_address_xl(ctx) ((ctx)->address_xl) |
| 44 | #ifdef TARGET_RISCV64 | 139 | +#endif |
| 45 | #define CASE_OP_32_64(X) case X: case glue(X, W) | 140 | + |
| 46 | #else | 141 | /* The word size for this machine mode. */ |
| 47 | @@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) | 142 | static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) |
| 48 | ctx->base.is_jmp = DISAS_NORETURN; | 143 | { |
| 144 | @@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) | ||
| 145 | tcg_gen_addi_tl(addr, src1, imm); | ||
| 146 | if (ctx->pm_mask_enabled) { | ||
| 147 | tcg_gen_andc_tl(addr, addr, pm_mask); | ||
| 148 | - } else if (get_xl(ctx) == MXL_RV32) { | ||
| 149 | + } else if (get_address_xl(ctx) == MXL_RV32) { | ||
| 150 | tcg_gen_ext32u_tl(addr, addr); | ||
| 151 | } | ||
| 152 | if (ctx->pm_base_enabled) { | ||
| 153 | tcg_gen_or_tl(addr, addr, pm_base); | ||
| 154 | } | ||
| 155 | + | ||
| 156 | return addr; | ||
| 49 | } | 157 | } |
| 50 | 158 | ||
| 51 | -#ifdef TARGET_RISCV64 | 159 | @@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
| 52 | -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, | 160 | ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); |
| 53 | - target_long imm) | 161 | ctx->misa_mxl_max = env->misa_mxl_max; |
| 54 | -{ | 162 | ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); |
| 55 | - TCGv t0 = tcg_temp_new(); | 163 | + ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); |
| 56 | - TCGv t1 = tcg_temp_new(); | 164 | ctx->cs = cs; |
| 57 | - gen_get_gpr(t0, rs1); | 165 | ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); |
| 58 | - tcg_gen_addi_tl(t0, t0, imm); | 166 | ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); |
| 59 | - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | ||
| 60 | - | ||
| 61 | - if (memop < 0) { | ||
| 62 | - gen_exception_illegal(ctx); | ||
| 63 | - return; | ||
| 64 | - } | ||
| 65 | - | ||
| 66 | - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); | ||
| 67 | - gen_set_gpr(rd, t1); | ||
| 68 | - tcg_temp_free(t0); | ||
| 69 | - tcg_temp_free(t1); | ||
| 70 | -} | ||
| 71 | - | ||
| 72 | -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, | ||
| 73 | - target_long imm) | ||
| 74 | -{ | ||
| 75 | - TCGv t0 = tcg_temp_new(); | ||
| 76 | - TCGv dat = tcg_temp_new(); | ||
| 77 | - gen_get_gpr(t0, rs1); | ||
| 78 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 79 | - gen_get_gpr(dat, rs2); | ||
| 80 | - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | ||
| 81 | - | ||
| 82 | - if (memop < 0) { | ||
| 83 | - gen_exception_illegal(ctx); | ||
| 84 | - return; | ||
| 85 | - } | ||
| 86 | - | ||
| 87 | - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); | ||
| 88 | - tcg_temp_free(t0); | ||
| 89 | - tcg_temp_free(dat); | ||
| 90 | -} | ||
| 91 | -#endif | ||
| 92 | - | ||
| 93 | #ifndef CONFIG_USER_ONLY | ||
| 94 | /* The states of mstatus_fs are: | ||
| 95 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx) | ||
| 97 | static inline void mark_fs_dirty(DisasContext *ctx) { } | ||
| 98 | #endif | ||
| 99 | |||
| 100 | -#if !defined(TARGET_RISCV64) | ||
| 101 | -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, | ||
| 102 | - int rs1, target_long imm) | ||
| 103 | -{ | ||
| 104 | - TCGv t0; | ||
| 105 | - | ||
| 106 | - if (ctx->mstatus_fs == 0) { | ||
| 107 | - gen_exception_illegal(ctx); | ||
| 108 | - return; | ||
| 109 | - } | ||
| 110 | - | ||
| 111 | - t0 = tcg_temp_new(); | ||
| 112 | - gen_get_gpr(t0, rs1); | ||
| 113 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 114 | - | ||
| 115 | - switch (opc) { | ||
| 116 | - case OPC_RISC_FLW: | ||
| 117 | - if (!has_ext(ctx, RVF)) { | ||
| 118 | - goto do_illegal; | ||
| 119 | - } | ||
| 120 | - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); | ||
| 121 | - /* RISC-V requires NaN-boxing of narrower width floating point values */ | ||
| 122 | - tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); | ||
| 123 | - break; | ||
| 124 | - case OPC_RISC_FLD: | ||
| 125 | - if (!has_ext(ctx, RVD)) { | ||
| 126 | - goto do_illegal; | ||
| 127 | - } | ||
| 128 | - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); | ||
| 129 | - break; | ||
| 130 | - do_illegal: | ||
| 131 | - default: | ||
| 132 | - gen_exception_illegal(ctx); | ||
| 133 | - break; | ||
| 134 | - } | ||
| 135 | - tcg_temp_free(t0); | ||
| 136 | - | ||
| 137 | - mark_fs_dirty(ctx); | ||
| 138 | -} | ||
| 139 | - | ||
| 140 | -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, | ||
| 141 | - int rs2, target_long imm) | ||
| 142 | -{ | ||
| 143 | - TCGv t0; | ||
| 144 | - | ||
| 145 | - if (ctx->mstatus_fs == 0) { | ||
| 146 | - gen_exception_illegal(ctx); | ||
| 147 | - return; | ||
| 148 | - } | ||
| 149 | - | ||
| 150 | - t0 = tcg_temp_new(); | ||
| 151 | - gen_get_gpr(t0, rs1); | ||
| 152 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 153 | - | ||
| 154 | - switch (opc) { | ||
| 155 | - case OPC_RISC_FSW: | ||
| 156 | - if (!has_ext(ctx, RVF)) { | ||
| 157 | - goto do_illegal; | ||
| 158 | - } | ||
| 159 | - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); | ||
| 160 | - break; | ||
| 161 | - case OPC_RISC_FSD: | ||
| 162 | - if (!has_ext(ctx, RVD)) { | ||
| 163 | - goto do_illegal; | ||
| 164 | - } | ||
| 165 | - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); | ||
| 166 | - break; | ||
| 167 | - do_illegal: | ||
| 168 | - default: | ||
| 169 | - gen_exception_illegal(ctx); | ||
| 170 | - break; | ||
| 171 | - } | ||
| 172 | - | ||
| 173 | - tcg_temp_free(t0); | ||
| 174 | -} | ||
| 175 | -#endif | ||
| 176 | - | ||
| 177 | static void gen_set_rm(DisasContext *ctx, int rm) | ||
| 178 | { | ||
| 179 | TCGv_i32 t0; | ||
| 180 | @@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm) | ||
| 181 | tcg_temp_free_i32(t0); | ||
| 182 | } | ||
| 183 | |||
| 184 | -static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) | ||
| 185 | -{ | ||
| 186 | - uint8_t funct3 = extract16(opcode, 13, 3); | ||
| 187 | - uint8_t rd_rs2 = GET_C_RS2S(opcode); | ||
| 188 | - uint8_t rs1s = GET_C_RS1S(opcode); | ||
| 189 | - | ||
| 190 | - switch (funct3) { | ||
| 191 | - case 3: | ||
| 192 | -#if defined(TARGET_RISCV64) | ||
| 193 | - /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ | ||
| 194 | - gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, | ||
| 195 | - GET_C_LD_IMM(opcode)); | ||
| 196 | -#else | ||
| 197 | - /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ | ||
| 198 | - gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, | ||
| 199 | - GET_C_LW_IMM(opcode)); | ||
| 200 | -#endif | ||
| 201 | - break; | ||
| 202 | - case 7: | ||
| 203 | -#if defined(TARGET_RISCV64) | ||
| 204 | - /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ | ||
| 205 | - gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, | ||
| 206 | - GET_C_LD_IMM(opcode)); | ||
| 207 | -#else | ||
| 208 | - /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ | ||
| 209 | - gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, | ||
| 210 | - GET_C_LW_IMM(opcode)); | ||
| 211 | -#endif | ||
| 212 | - break; | ||
| 213 | - } | ||
| 214 | -} | ||
| 215 | - | ||
| 216 | -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) | ||
| 217 | -{ | ||
| 218 | - uint8_t op = extract16(opcode, 0, 2); | ||
| 219 | - | ||
| 220 | - switch (op) { | ||
| 221 | - case 0: | ||
| 222 | - decode_RV32_64C0(ctx, opcode); | ||
| 223 | - break; | ||
| 224 | - } | ||
| 225 | -} | ||
| 226 | - | ||
| 227 | static int ex_plus_1(DisasContext *ctx, int nf) | ||
| 228 | { | ||
| 229 | return nf + 1; | ||
| 230 | @@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) | ||
| 231 | } else { | ||
| 232 | ctx->pc_succ_insn = ctx->base.pc_next + 2; | ||
| 233 | if (!decode_insn16(ctx, opcode)) { | ||
| 234 | - /* fall back to old decoder */ | ||
| 235 | - decode_RV32_64C(ctx, opcode); | ||
| 236 | + gen_exception_illegal(ctx); | ||
| 237 | } | ||
| 238 | } | ||
| 239 | } else { | ||
| 240 | -- | 167 | -- |
| 241 | 2.30.1 | 168 | 2.40.1 |
| 242 | 169 | ||
| 243 | 170 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | According to the specification the "field SPVP of hstatus controls the | 3 | Pointer mask is also affected by MPRV which means cur_pmbase/pmmask |
| 4 | privilege level of the access" for the hypervisor virtual-machine load | 4 | should also take MPRV into consideration. As pointer mask for instruction |
| 5 | and store instructions HLV, HLVX and HSV. | 5 | is not supported currently, so we can directly update cur_pmbase/pmmask |
| 6 | based on address related mode and xlen affected by MPRV now. | ||
| 6 | 7 | ||
| 7 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 8 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> |
| 9 | Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com | 10 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
| 11 | Message-Id: <20230614032547.35895-3-liweiwei@iscas.ac.cn> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 13 | --- |
| 12 | target/riscv/cpu_helper.c | 25 ++++++++++++++----------- | 14 | target/riscv/cpu_helper.c | 7 +++++-- |
| 13 | 1 file changed, 14 insertions(+), 11 deletions(-) | 15 | target/riscv/csr.c | 27 ++++++++++++++++++++------- |
| 16 | 2 files changed, 25 insertions(+), 9 deletions(-) | ||
| 14 | 17 | ||
| 15 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 18 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/riscv/cpu_helper.c | 20 | --- a/target/riscv/cpu_helper.c |
| 18 | +++ b/target/riscv/cpu_helper.c | 21 | +++ b/target/riscv/cpu_helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, | 22 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, |
| 20 | use_background = true; | 23 | void riscv_cpu_update_mask(CPURISCVState *env) |
| 21 | } | 24 | { |
| 22 | 25 | target_ulong mask = 0, base = 0; | |
| 23 | - if (mode == PRV_M && access_type != MMU_INST_FETCH) { | 26 | + RISCVMXL xl = env->xl; |
| 24 | + /* MPRV does not affect the virtual-machine load/store | 27 | /* |
| 25 | + instructions, HLV, HLVX, and HSV. */ | 28 | * TODO: Current RVJ spec does not specify |
| 26 | + if (riscv_cpu_two_stage_lookup(mmu_idx)) { | 29 | * how the extension interacts with XLEN. |
| 27 | + mode = get_field(env->hstatus, HSTATUS_SPVP); | 30 | */ |
| 28 | + } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { | 31 | #ifndef CONFIG_USER_ONLY |
| 29 | if (get_field(env->mstatus, MSTATUS_MPRV)) { | 32 | + int mode = cpu_address_mode(env); |
| 30 | mode = get_field(env->mstatus, MSTATUS_MPP); | 33 | + xl = cpu_get_xl(env, mode); |
| 31 | } | 34 | if (riscv_has_ext(env, RVJ)) { |
| 32 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | 35 | - switch (env->priv) { |
| 33 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | 36 | + switch (mode) { |
| 34 | __func__, address, access_type, mmu_idx); | 37 | case PRV_M: |
| 35 | 38 | if (env->mmte & M_PM_ENABLE) { | |
| 36 | - if (mode == PRV_M && access_type != MMU_INST_FETCH) { | 39 | mask = env->mpmmask; |
| 37 | - if (get_field(env->mstatus, MSTATUS_MPRV)) { | 40 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_update_mask(CPURISCVState *env) |
| 38 | - mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 39 | + /* MPRV does not affect the virtual-machine load/store | ||
| 40 | + instructions, HLV, HLVX, and HSV. */ | ||
| 41 | + if (riscv_cpu_two_stage_lookup(mmu_idx)) { | ||
| 42 | + mode = get_field(env->hstatus, HSTATUS_SPVP); | ||
| 43 | + } else if (mode == PRV_M && access_type != MMU_INST_FETCH && | ||
| 44 | + get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 45 | + mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 46 | + if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { | ||
| 47 | + two_stage_lookup = true; | ||
| 48 | } | 41 | } |
| 49 | } | 42 | } |
| 50 | 43 | #endif | |
| 51 | - if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | 44 | - if (env->xl == MXL_RV32) { |
| 52 | - access_type != MMU_INST_FETCH && | 45 | + if (xl == MXL_RV32) { |
| 53 | - get_field(env->mstatus, MSTATUS_MPRV) && | 46 | env->cur_pmmask = mask & UINT32_MAX; |
| 54 | - get_field(env->mstatus, MSTATUS_MPV)) { | 47 | env->cur_pmbase = base & UINT32_MAX; |
| 55 | - two_stage_lookup = true; | 48 | } else { |
| 56 | - } | 49 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 57 | - | 50 | index XXXXXXX..XXXXXXX 100644 |
| 58 | if (riscv_cpu_virt_enabled(env) || | 51 | --- a/target/riscv/csr.c |
| 59 | ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && | 52 | +++ b/target/riscv/csr.c |
| 60 | access_type != MMU_INST_FETCH)) { | 53 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
| 54 | */ | ||
| 55 | if (env->debugger) { | ||
| 56 | env->xl = cpu_recompute_xl(env); | ||
| 57 | - riscv_cpu_update_mask(env); | ||
| 58 | } | ||
| 59 | + | ||
| 60 | + riscv_cpu_update_mask(env); | ||
| 61 | return RISCV_EXCP_NONE; | ||
| 62 | } | ||
| 63 | |||
| 64 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno, | ||
| 65 | uint64_t mstatus; | ||
| 66 | |||
| 67 | env->mpmmask = val; | ||
| 68 | - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { | ||
| 69 | + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { | ||
| 70 | env->cur_pmmask = val; | ||
| 71 | } | ||
| 72 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno, | ||
| 74 | return RISCV_EXCP_NONE; | ||
| 75 | } | ||
| 76 | env->spmmask = val; | ||
| 77 | - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { | ||
| 78 | + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { | ||
| 79 | env->cur_pmmask = val; | ||
| 80 | + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { | ||
| 81 | + env->cur_pmmask &= UINT32_MAX; | ||
| 82 | + } | ||
| 83 | } | ||
| 84 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 85 | |||
| 86 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno, | ||
| 87 | return RISCV_EXCP_NONE; | ||
| 88 | } | ||
| 89 | env->upmmask = val; | ||
| 90 | - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { | ||
| 91 | + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { | ||
| 92 | env->cur_pmmask = val; | ||
| 93 | + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { | ||
| 94 | + env->cur_pmmask &= UINT32_MAX; | ||
| 95 | + } | ||
| 96 | } | ||
| 97 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 98 | |||
| 99 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno, | ||
| 100 | uint64_t mstatus; | ||
| 101 | |||
| 102 | env->mpmbase = val; | ||
| 103 | - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { | ||
| 104 | + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { | ||
| 105 | env->cur_pmbase = val; | ||
| 106 | } | ||
| 107 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno, | ||
| 109 | return RISCV_EXCP_NONE; | ||
| 110 | } | ||
| 111 | env->spmbase = val; | ||
| 112 | - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { | ||
| 113 | + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { | ||
| 114 | env->cur_pmbase = val; | ||
| 115 | + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { | ||
| 116 | + env->cur_pmbase &= UINT32_MAX; | ||
| 117 | + } | ||
| 118 | } | ||
| 119 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 120 | |||
| 121 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, | ||
| 122 | return RISCV_EXCP_NONE; | ||
| 123 | } | ||
| 124 | env->upmbase = val; | ||
| 125 | - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { | ||
| 126 | + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { | ||
| 127 | env->cur_pmbase = val; | ||
| 128 | + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { | ||
| 129 | + env->cur_pmbase &= UINT32_MAX; | ||
| 130 | + } | ||
| 131 | } | ||
| 132 | env->mmte |= EXT_STATUS_DIRTY; | ||
| 133 | |||
| 61 | -- | 134 | -- |
| 62 | 2.30.1 | 135 | 2.40.1 |
| 63 | |||
| 64 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bmeng@tinylab.org> | ||
| 1 | 2 | ||
| 3 | Upgrade OpenSBI from v1.2 to v1.3 and the pre-built bios images. | ||
| 4 | |||
| 5 | The v1.3 release includes the following commits: | ||
| 6 | |||
| 7 | 440fa81 treewide: Replace TRUE/FALSE with true/false | ||
| 8 | 6509127 Makefile: Remove -N ldflag to prevent linker RWX warning | ||
| 9 | 65638f8 lib: utils/sys: Allow custom HTIF base address for RV32 | ||
| 10 | f14595a lib: sbi: Allow platform to influence cold boot HART selection | ||
| 11 | 6957ae0 platform: generic: Allow platform_override to select cold boot HART | ||
| 12 | cb7e7c3 platform: generic: Allow platform_override to perform firmware init | ||
| 13 | 8020df8 generic/starfive: Add Starfive JH7110 platform implementation | ||
| 14 | 6997552 lib: sbi_hsm: Rename 'priv' argument to 'arg1' | ||
| 15 | 9e397e3 docs: domain_support: Use capital letter for privilege modes | ||
| 16 | 9e0ba09 include: sbi: Fine grain the permissions for M and SU modes | ||
| 17 | aace1e1 lib: sbi: Use finer permission semantics for address validation | ||
| 18 | 22dbdb3 lib: sbi: Add permissions for the firmware start till end | ||
| 19 | 1ac14f1 lib: sbi: Use finer permission sematics to decide on PMP bits | ||
| 20 | 44f736c lib: sbi: Modify the boot time region flag prints | ||
| 21 | 20646e0 lib: utils: Use SU-{R/W/X} flags for region permissions during parsing | ||
| 22 | 3e2f573 lib: utils: Disallow non-root domains from adding M-mode regions | ||
| 23 | 59a08cd lib: utils: Add M-mode {R/W} flags to the MMIO regions | ||
| 24 | 001106d docs: Update domain's region permissions and requirements | ||
| 25 | da5594b platform: generic: allwinner: Fix PLIC array bounds | ||
| 26 | ce2a834 docs: generic.md: fix typo of andes-ae350 | ||
| 27 | 8ecbe6d lib: sbi_hsm: handle failure when hart_stop returns SBI_ENOTSUPP | ||
| 28 | b1818ee include: types: add always inline compiler attribute | ||
| 29 | 9c4eb35 lib: utils: atcsmu: Add Andes System Management Unit support | ||
| 30 | 787296a platform: andes/ae350: Implement hart hotplug using HSM extension | ||
| 31 | 7aaeeab lib: reset/fdt_reset_atcwdt200: Use defined macros and function in atcsmu.h | ||
| 32 | a990309 lib: utils: Fix reserved memory node for firmware memory | ||
| 33 | fefa548 firmware: Split RO/RX and RW sections | ||
| 34 | 2f40a99 firmware: Move dynsym and reladyn sections to RX section | ||
| 35 | c10e3fe firmware: Add RW section offset in scratch | ||
| 36 | b666760 lib: sbi: Print the RW section offset | ||
| 37 | 230278d lib: sbi: Add separate entries for firmware RX and RW regions | ||
| 38 | dea0922 platform: renesas/rzfive: Configure Local memory regions as part of root domain | ||
| 39 | 33bf917 lib: utils: Add fdt_add_cpu_idle_states() helper function | ||
| 40 | c45992c platform: generic: allwinner: Advertise nonretentive suspend | ||
| 41 | c8ea836 firmware: Fix fw_rw_offset computation in fw_base.S | ||
| 42 | 8050081 firmware: Not to clear all the MIP | ||
| 43 | 84d15f4 lib: sbi_hsm: Use csr_set to restore the MIP | ||
| 44 | 199189b lib: utils: Mark only the largest region as reserved in FDT | ||
| 45 | 66b0e23 lib: sbi: Ensure domidx_to_domain_table is null-terminated | ||
| 46 | 642f3de Makefile: Add missing .dep files for fw_*.elf.ld | ||
| 47 | 09b34d8 include: Add support for byteorder/endianness conversion | ||
| 48 | 680bea0 lib: utils/fdt: Use byteorder conversion functions in libfdt_env.h | ||
| 49 | b224ddb include: types: Add typedefs for endianness | ||
| 50 | aa5dafc include: sbi: Fix BSWAPx() macros for big-endian host | ||
| 51 | e3bf1af include: Add defines for SBI debug console extension | ||
| 52 | 0ee3a86 lib: sbi: Add sbi_nputs() function | ||
| 53 | 4e0572f lib: sbi: Add sbi_ngets() function | ||
| 54 | eab48c3 lib: sbi: Add sbi_domain_check_addr_range() function | ||
| 55 | 5a41a38 lib: sbi: Implement SBI debug console extension | ||
| 56 | c43903c lib: sbi: Add console_puts() callback in the console device | ||
| 57 | 29285ae lib: utils/serial: Implement console_puts() for semihosting | ||
| 58 | 65c2190 lib: sbi: Speed-up sbi_printf() and friends using nputs() | ||
| 59 | 321293c lib: utils/fdt: Fix fdt_pmu.c header dependency | ||
| 60 | aafcc90 platform: generic/allwinner: Fix sun20i-d1.c header dependency | ||
| 61 | 745aaec platform: generic/andes: Fix ae350.c header dependency | ||
| 62 | 99d09b6 include: fdt/fdt_helper: Change fdt_get_address() to return root.next_arg1 | ||
| 63 | 6861ee9 lib: utils: fdt_fixup: Fix compile error | ||
| 64 | 4f2be40 docs: fix typo in fw.md | ||
| 65 | 30ea806 lib: sbi_hart: Enable hcontext and scontext | ||
| 66 | 81adc62 lib: sbi: Align SBI vendor extension id with mvendorid CSR | ||
| 67 | 31b82e0 include: sbi: Remove extid parameter from vendor_ext_provider() callback | ||
| 68 | c100951 platform: generic: renesas: rzfive: Add support to configure the PMA | ||
| 69 | 2491242 platform: generic: renesas: rzfive: Configure the PMA region | ||
| 70 | 67b2a40 lib: sbi: sbi_ecall: Check the range of SBI error | ||
| 71 | 5a75f53 lib: sbi/sbi_domain: cosmetic style fixes | ||
| 72 | bc06ff6 lib: utils/fdt/fdt_domain: Simplify region access permission check | ||
| 73 | 17b3776 docs: domain_support: Update the DT example | ||
| 74 | 1364d5a lib: sbi_hsm: Factor out invalid state detection | ||
| 75 | 40f16a8 lib: sbi_hsm: Don't try to restore state on failed change | ||
| 76 | c88e039 lib: sbi_hsm: Ensure errors are consistent with spec | ||
| 77 | b1ae6ef lib: sbi_hsm: Move misplaced comment | ||
| 78 | 07673fc lib: sbi_hsm: Remove unnecessary include | ||
| 79 | 8a40306 lib: sbi_hsm: Export some functions | ||
| 80 | 73623a0 lib: sbi: Add system suspend skeleton | ||
| 81 | c9917b6 lib: sbi: Add system_suspend_allowed domain property | ||
| 82 | 7c964e2 lib: sbi: Implement system suspend | ||
| 83 | 37558dc docs: Correct opensbi-domain property name | ||
| 84 | 5ccebf0 platform: generic: Add system suspend test | ||
| 85 | 908be1b gpio/starfive: add gpio driver and support gpio reset | ||
| 86 | 4b28afc make: Add a command line option for debugging OpenSBI | ||
| 87 | e9d08bd lib: utils/i2c: Add minimal StarFive jh7110 I2C driver | ||
| 88 | 568ea49 platform: starfive: add PMIC power ops in JH7110 visionfive2 board | ||
| 89 | 506144f lib: serial: Cadence: Enable compatibility for cdns,uart-r1p8 | ||
| 90 | 1fe8dc9 lib: sbi_pmu: add callback for counter width | ||
| 91 | 51951d9 lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi | ||
| 92 | 60c358e lib: sbi_pmu: Reserve space for implementation specific firmware events | ||
| 93 | 548e4b4 lib: sbi_pmu: Rename fw_counter_value | ||
| 94 | b51ddff lib: sbi_pmu: Update sbi_pmu dev ops | ||
| 95 | 641d2e9 lib: sbi_pmu: Use dedicated event code for platform firmware events | ||
| 96 | 57d3aa3 lib: sbi_pmu: Introduce fw_counter_write_value API | ||
| 97 | c631a7d lib: sbi_pmu: Add hartid parameter PMU device ops | ||
| 98 | d56049e lib: sbi: Refactor the calls to sbi_hart_switch_mode() | ||
| 99 | e8e9ed3 lib: sbi: Set the state of a hart to START_PENDING after the hart is ready | ||
| 100 | c6a092c lib: sbi: Clear IPIs before init_warm_startup in non-boot harts | ||
| 101 | ed88a63 lib: sbi_scratch: Optimize the alignment code for alloc size | ||
| 102 | 73ab11d lib: sbi: Fix how to check whether the domain contains fw_region | ||
| 103 | f64dfcd lib: sbi: Introduce sbi_entry_count() function | ||
| 104 | 30b9e7e lib: sbi_hsm: Fix sbi_hsm_hart_start() for platform with hart hotplug | ||
| 105 | 8e90259 lib: sbi_hart: clear mip csr during hart init | ||
| 106 | 45ba2b2 include: Add defines for SBI CPPC extension | ||
| 107 | 33caae8 lib: sbi: Implement SBI CPPC extension | ||
| 108 | 91767d0 lib: sbi: Print the CPPC device name | ||
| 109 | edc9914 lib: sbi_pmu: Align the event type offset as per SBI specification | ||
| 110 | ee016a7 docs: Correct FW_JUMP_FDT_ADDR calculation example | ||
| 111 | 2868f26 lib: utils: fdt_fixup: avoid buffer overrun | ||
| 112 | 66fa925 lib: sbi: Optimize sbi_tlb | ||
| 113 | 24dde46 lib: sbi: Optimize sbi_ipi | ||
| 114 | 80078ab sbi: tlb: Simplify to tlb_process_count/tlb_process function | ||
| 115 | bf40e07 lib: sbi: Optimize sbi_tlb queue waiting | ||
| 116 | eeab500 platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata | ||
| 117 | f692289 firmware: Optimize loading relocation type | ||
| 118 | e41dbb5 firmware: Change to use positive offset to access relocation entries | ||
| 119 | bdb3c42 lib: sbi: Do not clear active_events for cycle/instret when stopping | ||
| 120 | 674e019 lib: sbi: Fix counter index calculation for SBI_PMU_CFG_FLAG_SKIP_MATCH | ||
| 121 | f5dfd99 lib: sbi: Don't check SBI error range for legacy console getchar | ||
| 122 | 7919530 lib: sbi: Add debug print when sbi_pmu_init fails | ||
| 123 | 4e33530 lib: sbi: Remove unnecessary semicolon | ||
| 124 | 6bc02de lib: sbi: Simplify sbi_ipi_process remove goto | ||
| 125 | dc1c7db lib: sbi: Simplify BITS_PER_LONG definition | ||
| 126 | f58c140 lib: sbi: Introduce register_extensions extension callback | ||
| 127 | e307ba7 lib: sbi: Narrow vendor extension range | ||
| 128 | 042f0c3 lib: sbi: pmu: Remove unnecessary probe function | ||
| 129 | 8b952d4 lib: sbi: Only register available extensions | ||
| 130 | 767b5fc lib: sbi: Optimize probe of srst/susp | ||
| 131 | c3e31cb lib: sbi: Remove 0/1 probe implementations | ||
| 132 | 33f1722 lib: sbi: Document sbi_ecall_extension members | ||
| 133 | d4c46e0 Makefile: Dereference symlinks on install | ||
| 134 | 8b99a7f lib: sbi: Fix return of sbi_console_init | ||
| 135 | 264d0be lib: utils: Improve fdt_serial_init | ||
| 136 | 9a0bdd0 lib: utils: Improve fdt_ipi | ||
| 137 | 122f226 lib: utils: Improve fdt_timer | ||
| 138 | df75e09 lib: utils/ipi: buffer overrun aclint_mswi_cold_init | ||
| 139 | bdde2ec lib: sbi: Align system suspend errors with spec | ||
| 140 | aad7a37 include: sbi_scratch: Add helper macros to access data type | ||
| 141 | 5cf9a54 platform: Allow platforms to specify heap size | ||
| 142 | 40d36a6 lib: sbi: Introduce simple heap allocator | ||
| 143 | 2a04f70 lib: sbi: Print scratch size and usage at boot time | ||
| 144 | bbff53f lib: sbi_pmu: Use heap for per-HART PMU state | ||
| 145 | ef4542d lib: sbi: Use heap for root domain creation | ||
| 146 | 66daafe lib: sbi: Use scratch space to save per-HART domain pointer | ||
| 147 | fa5ad2e lib: utils/gpio: Use heap in SiFive and StartFive GPIO drivers | ||
| 148 | 903e88c lib: utils/i2c: Use heap in DesignWare and SiFive I2C drivers | ||
| 149 | 5a8cfcd lib: utils/ipi: Use heap in ACLINT MSWI driver | ||
| 150 | 3013716 lib: utils/irqchip: Use heap in PLIC, APLIC and IMSIC drivers | ||
| 151 | 7e5636a lib: utils/timer: Use heap in ACLINT MTIMER driver | ||
| 152 | 3c1c972 lib: utils/fdt: Use heap in FDT domain parsing | ||
| 153 | acbd8fc lib: utils/ipi: Use scratch space to save per-HART MSWI pointer | ||
| 154 | f0516be lib: utils/timer: Use scratch space to save per-HART MTIMER pointer | ||
| 155 | b3594ac lib: utils/irqchip: Use scratch space to save per-HART PLIC pointer | ||
| 156 | 1df52fa lib: utils/irqchip: Don't check hartid in imsic_update_hartid_table() | ||
| 157 | 355796c lib: utils/irqchip: Use scratch space to save per-HART IMSIC pointer | ||
| 158 | 524feec docs: Add OpenSBI logo and use it in the top-level README.md | ||
| 159 | 932be2c README.md: Improve project copyright information | ||
| 160 | 8153b26 platform/lib: Set no-map attribute on all PMP regions | ||
| 161 | d64942f firmware: Fix find hart index | ||
| 162 | 27c957a lib: reset: Move fdt_reset_init into generic_early_init | ||
| 163 | 8bd666a lib: sbi: check A2 register in ecall_dbcn_handler. | ||
| 164 | 2552799 include: Bump-up version to 1.3 | ||
| 165 | |||
| 166 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
| 167 | Message-Id: <20230630160717.843044-1-bmeng@tinylab.org> | ||
| 168 | Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 169 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 170 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 171 | --- | ||
| 172 | .../opensbi-riscv32-generic-fw_dynamic.bin | Bin 123072 -> 135344 bytes | ||
| 173 | .../opensbi-riscv64-generic-fw_dynamic.bin | Bin 121800 -> 138304 bytes | ||
| 174 | roms/opensbi | 2 +- | ||
| 175 | 3 files changed, 1 insertion(+), 1 deletion(-) | ||
| 176 | |||
| 177 | diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin b/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | ||
| 178 | index XXXXXXX..XXXXXXX 100644 | ||
| 179 | Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin and b/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin differ | ||
| 180 | diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin b/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | ||
| 181 | index XXXXXXX..XXXXXXX 100644 | ||
| 182 | Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin and b/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin differ | ||
| 183 | diff --git a/roms/opensbi b/roms/opensbi | ||
| 184 | index XXXXXXX..XXXXXXX 160000 | ||
| 185 | --- a/roms/opensbi | ||
| 186 | +++ b/roms/opensbi | ||
| 187 | @@ -1 +1 @@ | ||
| 188 | -Subproject commit 6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf8 | ||
| 189 | +Subproject commit 2552799a1df30a3dcd2321a8b75d61d06f5fb9fc | ||
| 190 | -- | ||
| 191 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bmeng@tinylab.org> | ||
| 1 | 2 | ||
| 3 | The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3. | ||
| 4 | Let's enable the 32-bit Spike OpenSBI boot testing. | ||
| 5 | |||
| 6 | Signed-off-by: Bin Meng <bmeng@tinylab.org> | ||
| 7 | Message-Id: <20230630160717.843044-2-bmeng@tinylab.org> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | tests/avocado/riscv_opensbi.py | 2 -- | ||
| 13 | 1 file changed, 2 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/tests/avocado/riscv_opensbi.py | ||
| 18 | +++ b/tests/avocado/riscv_opensbi.py | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | # later. See the COPYING file in the top-level directory. | ||
| 21 | |||
| 22 | from avocado_qemu import QemuSystemTest | ||
| 23 | -from avocado import skip | ||
| 24 | from avocado_qemu import wait_for_console_pattern | ||
| 25 | |||
| 26 | class RiscvOpenSBI(QemuSystemTest): | ||
| 27 | @@ -XXX,XX +XXX,XX @@ def boot_opensbi(self): | ||
| 28 | wait_for_console_pattern(self, 'Platform Name') | ||
| 29 | wait_for_console_pattern(self, 'Boot HART MEDELEG') | ||
| 30 | |||
| 31 | - @skip("requires OpenSBI fix to work") | ||
| 32 | def test_riscv32_spike(self): | ||
| 33 | """ | ||
| 34 | :avocado: tags=arch:riscv32 | ||
| 35 | -- | ||
| 36 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Tommy Wu <tommy.wu@sifive.com> | ||
| 1 | 2 | ||
| 3 | The watchdog timer is in the always-on domain device of HiFive 1 rev b, | ||
| 4 | so this patch added the AON device to the sifive_e machine. This patch | ||
| 5 | only implemented the functionality of the watchdog timer. | ||
| 6 | |||
| 7 | Signed-off-by: Tommy Wu <tommy.wu@sifive.com> | ||
| 8 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
| 9 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-Id: <20230627141216.3962299-2-tommy.wu@sifive.com> | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | include/hw/misc/sifive_e_aon.h | 60 +++++++ | ||
| 14 | hw/misc/sifive_e_aon.c | 319 +++++++++++++++++++++++++++++++++ | ||
| 15 | hw/misc/Kconfig | 3 + | ||
| 16 | hw/misc/meson.build | 1 + | ||
| 17 | 4 files changed, 383 insertions(+) | ||
| 18 | create mode 100644 include/hw/misc/sifive_e_aon.h | ||
| 19 | create mode 100644 hw/misc/sifive_e_aon.c | ||
| 20 | |||
| 21 | diff --git a/include/hw/misc/sifive_e_aon.h b/include/hw/misc/sifive_e_aon.h | ||
| 22 | new file mode 100644 | ||
| 23 | index XXXXXXX..XXXXXXX | ||
| 24 | --- /dev/null | ||
| 25 | +++ b/include/hw/misc/sifive_e_aon.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ | ||
| 27 | +/* | ||
| 28 | + * SiFive HiFive1 AON (Always On Domain) interface. | ||
| 29 | + * | ||
| 30 | + * Copyright (c) 2022 SiFive, Inc. All rights reserved. | ||
| 31 | + * | ||
| 32 | + * This program is free software; you can redistribute it and/or modify it | ||
| 33 | + * under the terms and conditions of the GNU General Public License, | ||
| 34 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 35 | + * | ||
| 36 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 37 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 38 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 39 | + * more details. | ||
| 40 | + * | ||
| 41 | + * You should have received a copy of the GNU General Public License along with | ||
| 42 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 43 | + */ | ||
| 44 | + | ||
| 45 | +#ifndef HW_SIFIVE_AON_H | ||
| 46 | +#define HW_SIFIVE_AON_H | ||
| 47 | + | ||
| 48 | +#include "hw/sysbus.h" | ||
| 49 | +#include "qom/object.h" | ||
| 50 | + | ||
| 51 | +#define TYPE_SIFIVE_E_AON "riscv.sifive.e.aon" | ||
| 52 | +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveEAONState, SIFIVE_E_AON) | ||
| 53 | + | ||
| 54 | +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) | ||
| 55 | +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) | ||
| 56 | +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) | ||
| 57 | + | ||
| 58 | +enum { | ||
| 59 | + SIFIVE_E_AON_WDT = 0x0, | ||
| 60 | + SIFIVE_E_AON_RTC = 0x40, | ||
| 61 | + SIFIVE_E_AON_LFROSC = 0x70, | ||
| 62 | + SIFIVE_E_AON_BACKUP = 0x80, | ||
| 63 | + SIFIVE_E_AON_PMU = 0x100, | ||
| 64 | + SIFIVE_E_AON_MAX = 0x150 | ||
| 65 | +}; | ||
| 66 | + | ||
| 67 | +struct SiFiveEAONState { | ||
| 68 | + /*< private >*/ | ||
| 69 | + SysBusDevice parent_obj; | ||
| 70 | + | ||
| 71 | + /*< public >*/ | ||
| 72 | + MemoryRegion mmio; | ||
| 73 | + | ||
| 74 | + /*< watchdog timer >*/ | ||
| 75 | + QEMUTimer *wdog_timer; | ||
| 76 | + qemu_irq wdog_irq; | ||
| 77 | + uint64_t wdog_restart_time; | ||
| 78 | + uint64_t wdogclk_freq; | ||
| 79 | + | ||
| 80 | + uint32_t wdogcfg; | ||
| 81 | + uint16_t wdogcmp0; | ||
| 82 | + uint32_t wdogcount; | ||
| 83 | + uint8_t wdogunlock; | ||
| 84 | +}; | ||
| 85 | + | ||
| 86 | +#endif | ||
| 87 | diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c | ||
| 88 | new file mode 100644 | ||
| 89 | index XXXXXXX..XXXXXXX | ||
| 90 | --- /dev/null | ||
| 91 | +++ b/hw/misc/sifive_e_aon.c | ||
| 92 | @@ -XXX,XX +XXX,XX @@ | ||
| 93 | +/* | ||
| 94 | + * SiFive HiFive1 AON (Always On Domain) for QEMU. | ||
| 95 | + * | ||
| 96 | + * Copyright (c) 2022 SiFive, Inc. All rights reserved. | ||
| 97 | + * | ||
| 98 | + * This program is free software; you can redistribute it and/or modify it | ||
| 99 | + * under the terms and conditions of the GNU General Public License, | ||
| 100 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 101 | + * | ||
| 102 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 103 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 104 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 105 | + * more details. | ||
| 106 | + * | ||
| 107 | + * You should have received a copy of the GNU General Public License along with | ||
| 108 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 109 | + */ | ||
| 110 | + | ||
| 111 | +#include "qemu/osdep.h" | ||
| 112 | +#include "qemu/timer.h" | ||
| 113 | +#include "qemu/log.h" | ||
| 114 | +#include "hw/irq.h" | ||
| 115 | +#include "hw/registerfields.h" | ||
| 116 | +#include "hw/misc/sifive_e_aon.h" | ||
| 117 | +#include "qapi/visitor.h" | ||
| 118 | +#include "qapi/error.h" | ||
| 119 | +#include "sysemu/watchdog.h" | ||
| 120 | +#include "hw/qdev-properties.h" | ||
| 121 | + | ||
| 122 | +REG32(AON_WDT_WDOGCFG, 0x0) | ||
| 123 | + FIELD(AON_WDT_WDOGCFG, SCALE, 0, 4) | ||
| 124 | + FIELD(AON_WDT_WDOGCFG, RSVD0, 4, 4) | ||
| 125 | + FIELD(AON_WDT_WDOGCFG, RSTEN, 8, 1) | ||
| 126 | + FIELD(AON_WDT_WDOGCFG, ZEROCMP, 9, 1) | ||
| 127 | + FIELD(AON_WDT_WDOGCFG, RSVD1, 10, 2) | ||
| 128 | + FIELD(AON_WDT_WDOGCFG, EN_ALWAYS, 12, 1) | ||
| 129 | + FIELD(AON_WDT_WDOGCFG, EN_CORE_AWAKE, 13, 1) | ||
| 130 | + FIELD(AON_WDT_WDOGCFG, RSVD2, 14, 14) | ||
| 131 | + FIELD(AON_WDT_WDOGCFG, IP0, 28, 1) | ||
| 132 | + FIELD(AON_WDT_WDOGCFG, RSVD3, 29, 3) | ||
| 133 | +REG32(AON_WDT_WDOGCOUNT, 0x8) | ||
| 134 | + FIELD(AON_WDT_WDOGCOUNT, VALUE, 0, 31) | ||
| 135 | +REG32(AON_WDT_WDOGS, 0x10) | ||
| 136 | +REG32(AON_WDT_WDOGFEED, 0x18) | ||
| 137 | +REG32(AON_WDT_WDOGKEY, 0x1c) | ||
| 138 | +REG32(AON_WDT_WDOGCMP0, 0x20) | ||
| 139 | + | ||
| 140 | +static void sifive_e_aon_wdt_update_wdogcount(SiFiveEAONState *r) | ||
| 141 | +{ | ||
| 142 | + int64_t now; | ||
| 143 | + if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 0 && | ||
| 144 | + FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 0) { | ||
| 145 | + return; | ||
| 146 | + } | ||
| 147 | + | ||
| 148 | + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 149 | + r->wdogcount += muldiv64(now - r->wdog_restart_time, | ||
| 150 | + r->wdogclk_freq, NANOSECONDS_PER_SECOND); | ||
| 151 | + | ||
| 152 | + /* Clean the most significant bit. */ | ||
| 153 | + r->wdogcount &= R_AON_WDT_WDOGCOUNT_VALUE_MASK; | ||
| 154 | + r->wdog_restart_time = now; | ||
| 155 | +} | ||
| 156 | + | ||
| 157 | +static void sifive_e_aon_wdt_update_state(SiFiveEAONState *r) | ||
| 158 | +{ | ||
| 159 | + uint16_t wdogs; | ||
| 160 | + bool cmp_signal = false; | ||
| 161 | + sifive_e_aon_wdt_update_wdogcount(r); | ||
| 162 | + wdogs = (uint16_t)(r->wdogcount >> | ||
| 163 | + FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 164 | + | ||
| 165 | + if (wdogs >= r->wdogcmp0) { | ||
| 166 | + cmp_signal = true; | ||
| 167 | + if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, ZEROCMP) == 1) { | ||
| 168 | + r->wdogcount = 0; | ||
| 169 | + wdogs = 0; | ||
| 170 | + } | ||
| 171 | + } | ||
| 172 | + | ||
| 173 | + if (cmp_signal) { | ||
| 174 | + if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, RSTEN) == 1) { | ||
| 175 | + watchdog_perform_action(); | ||
| 176 | + } | ||
| 177 | + r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, IP0, 1); | ||
| 178 | + } | ||
| 179 | + | ||
| 180 | + qemu_set_irq(r->wdog_irq, FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, IP0)); | ||
| 181 | + | ||
| 182 | + if (wdogs < r->wdogcmp0 && | ||
| 183 | + (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 1 || | ||
| 184 | + FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 1)) { | ||
| 185 | + int64_t next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 186 | + next += muldiv64((r->wdogcmp0 - wdogs) << | ||
| 187 | + FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE), | ||
| 188 | + NANOSECONDS_PER_SECOND, r->wdogclk_freq); | ||
| 189 | + timer_mod(r->wdog_timer, next); | ||
| 190 | + } else { | ||
| 191 | + timer_mod(r->wdog_timer, INT64_MAX); | ||
| 192 | + } | ||
| 193 | +} | ||
| 194 | + | ||
| 195 | +/* | ||
| 196 | + * Callback used when the timer set using timer_mod expires. | ||
| 197 | + */ | ||
| 198 | +static void sifive_e_aon_wdt_expired_cb(void *opaque) | ||
| 199 | +{ | ||
| 200 | + SiFiveEAONState *r = SIFIVE_E_AON(opaque); | ||
| 201 | + sifive_e_aon_wdt_update_state(r); | ||
| 202 | +} | ||
| 203 | + | ||
| 204 | +static uint64_t | ||
| 205 | +sifive_e_aon_wdt_read(void *opaque, hwaddr addr, unsigned int size) | ||
| 206 | +{ | ||
| 207 | + SiFiveEAONState *r = SIFIVE_E_AON(opaque); | ||
| 208 | + | ||
| 209 | + switch (addr) { | ||
| 210 | + case A_AON_WDT_WDOGCFG: | ||
| 211 | + return r->wdogcfg; | ||
| 212 | + case A_AON_WDT_WDOGCOUNT: | ||
| 213 | + sifive_e_aon_wdt_update_wdogcount(r); | ||
| 214 | + return r->wdogcount; | ||
| 215 | + case A_AON_WDT_WDOGS: | ||
| 216 | + sifive_e_aon_wdt_update_wdogcount(r); | ||
| 217 | + return r->wdogcount >> | ||
| 218 | + FIELD_EX32(r->wdogcfg, | ||
| 219 | + AON_WDT_WDOGCFG, | ||
| 220 | + SCALE); | ||
| 221 | + case A_AON_WDT_WDOGFEED: | ||
| 222 | + return 0; | ||
| 223 | + case A_AON_WDT_WDOGKEY: | ||
| 224 | + return r->wdogunlock; | ||
| 225 | + case A_AON_WDT_WDOGCMP0: | ||
| 226 | + return r->wdogcmp0; | ||
| 227 | + default: | ||
| 228 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", | ||
| 229 | + __func__, (int)addr); | ||
| 230 | + } | ||
| 231 | + | ||
| 232 | + return 0; | ||
| 233 | +} | ||
| 234 | + | ||
| 235 | +static void | ||
| 236 | +sifive_e_aon_wdt_write(void *opaque, hwaddr addr, | ||
| 237 | + uint64_t val64, unsigned int size) | ||
| 238 | +{ | ||
| 239 | + SiFiveEAONState *r = SIFIVE_E_AON(opaque); | ||
| 240 | + uint32_t value = val64; | ||
| 241 | + | ||
| 242 | + switch (addr) { | ||
| 243 | + case A_AON_WDT_WDOGCFG: { | ||
| 244 | + uint8_t new_en_always; | ||
| 245 | + uint8_t new_en_core_awake; | ||
| 246 | + uint8_t old_en_always; | ||
| 247 | + uint8_t old_en_core_awake; | ||
| 248 | + if (r->wdogunlock == 0) { | ||
| 249 | + return; | ||
| 250 | + } | ||
| 251 | + | ||
| 252 | + new_en_always = FIELD_EX32(value, AON_WDT_WDOGCFG, EN_ALWAYS); | ||
| 253 | + new_en_core_awake = FIELD_EX32(value, AON_WDT_WDOGCFG, EN_CORE_AWAKE); | ||
| 254 | + old_en_always = FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS); | ||
| 255 | + old_en_core_awake = FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, | ||
| 256 | + EN_CORE_AWAKE); | ||
| 257 | + | ||
| 258 | + if ((old_en_always || | ||
| 259 | + old_en_core_awake) == 1 && | ||
| 260 | + (new_en_always || | ||
| 261 | + new_en_core_awake) == 0) { | ||
| 262 | + sifive_e_aon_wdt_update_wdogcount(r); | ||
| 263 | + } else if ((old_en_always || | ||
| 264 | + old_en_core_awake) == 0 && | ||
| 265 | + (new_en_always || | ||
| 266 | + new_en_core_awake) == 1) { | ||
| 267 | + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 268 | + } | ||
| 269 | + r->wdogcfg = value; | ||
| 270 | + r->wdogunlock = 0; | ||
| 271 | + break; | ||
| 272 | + } | ||
| 273 | + case A_AON_WDT_WDOGCOUNT: | ||
| 274 | + if (r->wdogunlock == 0) { | ||
| 275 | + return; | ||
| 276 | + } | ||
| 277 | + r->wdogcount = value & R_AON_WDT_WDOGCOUNT_VALUE_MASK; | ||
| 278 | + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 279 | + r->wdogunlock = 0; | ||
| 280 | + break; | ||
| 281 | + case A_AON_WDT_WDOGS: | ||
| 282 | + return; | ||
| 283 | + case A_AON_WDT_WDOGFEED: | ||
| 284 | + if (r->wdogunlock == 0) { | ||
| 285 | + return; | ||
| 286 | + } | ||
| 287 | + if (value == SIFIVE_E_AON_WDOGFEED) { | ||
| 288 | + r->wdogcount = 0; | ||
| 289 | + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 290 | + } | ||
| 291 | + r->wdogunlock = 0; | ||
| 292 | + break; | ||
| 293 | + case A_AON_WDT_WDOGKEY: | ||
| 294 | + if (value == SIFIVE_E_AON_WDOGKEY) { | ||
| 295 | + r->wdogunlock = 1; | ||
| 296 | + } | ||
| 297 | + break; | ||
| 298 | + case A_AON_WDT_WDOGCMP0: | ||
| 299 | + if (r->wdogunlock == 0) { | ||
| 300 | + return; | ||
| 301 | + } | ||
| 302 | + r->wdogcmp0 = (uint16_t) value; | ||
| 303 | + r->wdogunlock = 0; | ||
| 304 | + break; | ||
| 305 | + default: | ||
| 306 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", | ||
| 307 | + __func__, (int)addr, (int)value); | ||
| 308 | + } | ||
| 309 | + sifive_e_aon_wdt_update_state(r); | ||
| 310 | +} | ||
| 311 | + | ||
| 312 | +static uint64_t | ||
| 313 | +sifive_e_aon_read(void *opaque, hwaddr addr, unsigned int size) | ||
| 314 | +{ | ||
| 315 | + if (addr < SIFIVE_E_AON_RTC) { | ||
| 316 | + return sifive_e_aon_wdt_read(opaque, addr, size); | ||
| 317 | + } else if (addr < SIFIVE_E_AON_MAX) { | ||
| 318 | + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented read: addr=0x%x\n", | ||
| 319 | + __func__, (int)addr); | ||
| 320 | + } else { | ||
| 321 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", | ||
| 322 | + __func__, (int)addr); | ||
| 323 | + } | ||
| 324 | + return 0; | ||
| 325 | +} | ||
| 326 | + | ||
| 327 | +static void | ||
| 328 | +sifive_e_aon_write(void *opaque, hwaddr addr, | ||
| 329 | + uint64_t val64, unsigned int size) | ||
| 330 | +{ | ||
| 331 | + if (addr < SIFIVE_E_AON_RTC) { | ||
| 332 | + sifive_e_aon_wdt_write(opaque, addr, val64, size); | ||
| 333 | + } else if (addr < SIFIVE_E_AON_MAX) { | ||
| 334 | + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented write: addr=0x%x\n", | ||
| 335 | + __func__, (int)addr); | ||
| 336 | + } else { | ||
| 337 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x\n", | ||
| 338 | + __func__, (int)addr); | ||
| 339 | + } | ||
| 340 | +} | ||
| 341 | + | ||
| 342 | +static const MemoryRegionOps sifive_e_aon_ops = { | ||
| 343 | + .read = sifive_e_aon_read, | ||
| 344 | + .write = sifive_e_aon_write, | ||
| 345 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
| 346 | + .impl = { | ||
| 347 | + .min_access_size = 4, | ||
| 348 | + .max_access_size = 4 | ||
| 349 | + }, | ||
| 350 | + .valid = { | ||
| 351 | + .min_access_size = 4, | ||
| 352 | + .max_access_size = 4 | ||
| 353 | + } | ||
| 354 | +}; | ||
| 355 | + | ||
| 356 | +static void sifive_e_aon_reset(DeviceState *dev) | ||
| 357 | +{ | ||
| 358 | + SiFiveEAONState *r = SIFIVE_E_AON(dev); | ||
| 359 | + | ||
| 360 | + r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, RSTEN, 0); | ||
| 361 | + r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS, 0); | ||
| 362 | + r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE, 0); | ||
| 363 | + r->wdogcmp0 = 0xbeef; | ||
| 364 | + | ||
| 365 | + sifive_e_aon_wdt_update_state(r); | ||
| 366 | +} | ||
| 367 | + | ||
| 368 | +static void sifive_e_aon_init(Object *obj) | ||
| 369 | +{ | ||
| 370 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
| 371 | + SiFiveEAONState *r = SIFIVE_E_AON(obj); | ||
| 372 | + | ||
| 373 | + memory_region_init_io(&r->mmio, OBJECT(r), &sifive_e_aon_ops, r, | ||
| 374 | + TYPE_SIFIVE_E_AON, SIFIVE_E_AON_MAX); | ||
| 375 | + sysbus_init_mmio(sbd, &r->mmio); | ||
| 376 | + | ||
| 377 | + /* watchdog timer */ | ||
| 378 | + r->wdog_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | ||
| 379 | + sifive_e_aon_wdt_expired_cb, r); | ||
| 380 | + r->wdogclk_freq = SIFIVE_E_LFCLK_DEFAULT_FREQ; | ||
| 381 | + sysbus_init_irq(sbd, &r->wdog_irq); | ||
| 382 | +} | ||
| 383 | + | ||
| 384 | +static Property sifive_e_aon_properties[] = { | ||
| 385 | + DEFINE_PROP_UINT64("wdogclk-frequency", SiFiveEAONState, wdogclk_freq, | ||
| 386 | + SIFIVE_E_LFCLK_DEFAULT_FREQ), | ||
| 387 | + DEFINE_PROP_END_OF_LIST(), | ||
| 388 | +}; | ||
| 389 | + | ||
| 390 | +static void sifive_e_aon_class_init(ObjectClass *oc, void *data) | ||
| 391 | +{ | ||
| 392 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 393 | + | ||
| 394 | + dc->reset = sifive_e_aon_reset; | ||
| 395 | + device_class_set_props(dc, sifive_e_aon_properties); | ||
| 396 | +} | ||
| 397 | + | ||
| 398 | +static const TypeInfo sifive_e_aon_info = { | ||
| 399 | + .name = TYPE_SIFIVE_E_AON, | ||
| 400 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 401 | + .instance_size = sizeof(SiFiveEAONState), | ||
| 402 | + .instance_init = sifive_e_aon_init, | ||
| 403 | + .class_init = sifive_e_aon_class_init, | ||
| 404 | +}; | ||
| 405 | + | ||
| 406 | +static void sifive_e_aon_register_types(void) | ||
| 407 | +{ | ||
| 408 | + type_register_static(&sifive_e_aon_info); | ||
| 409 | +} | ||
| 410 | + | ||
| 411 | +type_init(sifive_e_aon_register_types) | ||
| 412 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
| 413 | index XXXXXXX..XXXXXXX 100644 | ||
| 414 | --- a/hw/misc/Kconfig | ||
| 415 | +++ b/hw/misc/Kconfig | ||
| 416 | @@ -XXX,XX +XXX,XX @@ config SIFIVE_TEST | ||
| 417 | config SIFIVE_E_PRCI | ||
| 418 | bool | ||
| 419 | |||
| 420 | +config SIFIVE_E_AON | ||
| 421 | + bool | ||
| 422 | + | ||
| 423 | config SIFIVE_U_OTP | ||
| 424 | bool | ||
| 425 | |||
| 426 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
| 427 | index XXXXXXX..XXXXXXX 100644 | ||
| 428 | --- a/hw/misc/meson.build | ||
| 429 | +++ b/hw/misc/meson.build | ||
| 430 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb. | ||
| 431 | system_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) | ||
| 432 | system_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
| 433 | system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
| 434 | +system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c')) | ||
| 435 | system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
| 436 | system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) | ||
| 437 | |||
| 438 | -- | ||
| 439 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Asherah Connor <ashe@kivikakk.ee> | 1 | From: Tommy Wu <tommy.wu@sifive.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Provides fw_cfg for the virt machine on riscv. This enables | 3 | Create the AON device when we realize the sifive_e machine. |
| 4 | using e.g. ramfb later. | 4 | This patch only implemented the functionality of the watchdog timer, |
| 5 | not all the functionality of the AON device. | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Asherah Connor <ashe@kivikakk.ee> | 7 | Signed-off-by: Tommy Wu <tommy.wu@sifive.com> |
| 7 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | 8 | Reviewed-by: Frank Chang <frank.chang@sifive.com> |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 9 | Message-id: 20210318235041.17175-2-ashe@kivikakk.ee | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 11 | Message-Id: <20230627141216.3962299-3-tommy.wu@sifive.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 13 | --- |
| 12 | include/hw/riscv/virt.h | 2 ++ | 14 | include/hw/riscv/sifive_e.h | 9 ++++++--- |
| 13 | hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++ | 15 | hw/riscv/sifive_e.c | 17 +++++++++++++++-- |
| 14 | hw/riscv/Kconfig | 1 + | 16 | hw/riscv/Kconfig | 1 + |
| 15 | 3 files changed, 33 insertions(+) | 17 | 3 files changed, 22 insertions(+), 5 deletions(-) |
| 16 | 18 | ||
| 17 | diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h | 19 | diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h |
| 18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/riscv/virt.h | 21 | --- a/include/hw/riscv/sifive_e.h |
| 20 | +++ b/include/hw/riscv/virt.h | 22 | +++ b/include/hw/riscv/sifive_e.h |
| 21 | @@ -XXX,XX +XXX,XX @@ struct RISCVVirtState { | 23 | @@ -XXX,XX +XXX,XX @@ |
| 22 | RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; | 24 | #include "hw/riscv/riscv_hart.h" |
| 23 | DeviceState *plic[VIRT_SOCKETS_MAX]; | 25 | #include "hw/riscv/sifive_cpu.h" |
| 24 | PFlashCFI01 *flash[2]; | 26 | #include "hw/gpio/sifive_gpio.h" |
| 25 | + FWCfgState *fw_cfg; | 27 | +#include "hw/misc/sifive_e_aon.h" |
| 26 | 28 | #include "hw/boards.h" | |
| 27 | int fdt_size; | 29 | |
| 30 | #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" | ||
| 31 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFiveESoCState { | ||
| 32 | /*< public >*/ | ||
| 33 | RISCVHartArrayState cpus; | ||
| 34 | DeviceState *plic; | ||
| 35 | + SiFiveEAONState aon; | ||
| 36 | SIFIVEGPIOState gpio; | ||
| 37 | MemoryRegion xip_mem; | ||
| 38 | MemoryRegion mask_rom; | ||
| 39 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 28 | }; | 40 | }; |
| 29 | @@ -XXX,XX +XXX,XX @@ enum { | 41 | |
| 30 | VIRT_PLIC, | 42 | enum { |
| 31 | VIRT_UART0, | 43 | - SIFIVE_E_UART0_IRQ = 3, |
| 32 | VIRT_VIRTIO, | 44 | - SIFIVE_E_UART1_IRQ = 4, |
| 33 | + VIRT_FW_CFG, | 45 | - SIFIVE_E_GPIO0_IRQ0 = 8 |
| 34 | VIRT_FLASH, | 46 | + SIFIVE_E_AON_WDT_IRQ = 1, |
| 35 | VIRT_DRAM, | 47 | + SIFIVE_E_UART0_IRQ = 3, |
| 36 | VIRT_PCIE_MMIO, | 48 | + SIFIVE_E_UART1_IRQ = 4, |
| 37 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | 49 | + SIFIVE_E_GPIO0_IRQ0 = 8 |
| 50 | }; | ||
| 51 | |||
| 52 | #define SIFIVE_E_PLIC_HART_CONFIG "M" | ||
| 53 | diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
| 39 | --- a/hw/riscv/virt.c | 55 | --- a/hw/riscv/sifive_e.c |
| 40 | +++ b/hw/riscv/virt.c | 56 | +++ b/hw/riscv/sifive_e.c |
| 41 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = { | 57 | @@ -XXX,XX +XXX,XX @@ |
| 42 | [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, | 58 | #include "hw/intc/riscv_aclint.h" |
| 43 | [VIRT_UART0] = { 0x10000000, 0x100 }, | 59 | #include "hw/intc/sifive_plic.h" |
| 44 | [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, | 60 | #include "hw/misc/sifive_e_prci.h" |
| 45 | + [VIRT_FW_CFG] = { 0x10100000, 0x18 }, | 61 | +#include "hw/misc/sifive_e_aon.h" |
| 46 | [VIRT_FLASH] = { 0x20000000, 0x4000000 }, | 62 | #include "chardev/char.h" |
| 47 | [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, | 63 | #include "sysemu/sysemu.h" |
| 48 | [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, | 64 | |
| 49 | @@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, | 65 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj) |
| 50 | return dev; | 66 | object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); |
| 67 | object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, | ||
| 68 | TYPE_SIFIVE_GPIO); | ||
| 69 | + object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, | ||
| 70 | + TYPE_SIFIVE_E_AON); | ||
| 51 | } | 71 | } |
| 52 | 72 | ||
| 53 | +static FWCfgState *create_fw_cfg(const MachineState *mc) | 73 | static void sifive_e_soc_realize(DeviceState *dev, Error **errp) |
| 54 | +{ | 74 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) |
| 55 | + hwaddr base = virt_memmap[VIRT_FW_CFG].base; | 75 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, |
| 56 | + hwaddr size = virt_memmap[VIRT_FW_CFG].size; | 76 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, |
| 57 | + FWCfgState *fw_cfg; | 77 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); |
| 58 | + char *nodename; | 78 | - create_unimplemented_device("riscv.sifive.e.aon", |
| 79 | - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); | ||
| 80 | sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); | ||
| 81 | |||
| 82 | + /* AON */ | ||
| 59 | + | 83 | + |
| 60 | + fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, | 84 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { |
| 61 | + &address_space_memory); | 85 | + return; |
| 62 | + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); | 86 | + } |
| 63 | + | 87 | + |
| 64 | + nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | 88 | + /* Map AON registers */ |
| 65 | + qemu_fdt_add_subnode(mc->fdt, nodename); | 89 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); |
| 66 | + qemu_fdt_setprop_string(mc->fdt, nodename, | ||
| 67 | + "compatible", "qemu,fw-cfg-mmio"); | ||
| 68 | + qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", | ||
| 69 | + 2, base, 2, size); | ||
| 70 | + qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); | ||
| 71 | + g_free(nodename); | ||
| 72 | + return fw_cfg; | ||
| 73 | +} | ||
| 74 | + | 90 | + |
| 75 | static void virt_machine_init(MachineState *machine) | 91 | /* GPIO */ |
| 76 | { | 92 | |
| 77 | const MemMapEntry *memmap = virt_memmap; | 93 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
| 78 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | 94 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) |
| 79 | start_addr = virt_memmap[VIRT_FLASH].base; | 95 | qdev_get_gpio_in(DEVICE(s->plic), |
| 96 | SIFIVE_E_GPIO0_IRQ0 + i)); | ||
| 80 | } | 97 | } |
| 81 | 98 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, | |
| 82 | + /* | 99 | + qdev_get_gpio_in(DEVICE(s->plic), |
| 83 | + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | 100 | + SIFIVE_E_AON_WDT_IRQ)); |
| 84 | + * tree cannot be altered and we get FDT_ERR_NOSPACE. | 101 | |
| 85 | + */ | 102 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, |
| 86 | + s->fw_cfg = create_fw_cfg(machine); | 103 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); |
| 87 | + rom_set_fw(s->fw_cfg); | ||
| 88 | + | ||
| 89 | /* Compute the fdt load address in dram */ | ||
| 90 | fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, | ||
| 91 | machine->ram_size, machine->fdt); | ||
| 92 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | 104 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig |
| 93 | index XXXXXXX..XXXXXXX 100644 | 105 | index XXXXXXX..XXXXXXX 100644 |
| 94 | --- a/hw/riscv/Kconfig | 106 | --- a/hw/riscv/Kconfig |
| 95 | +++ b/hw/riscv/Kconfig | 107 | +++ b/hw/riscv/Kconfig |
| 96 | @@ -XXX,XX +XXX,XX @@ config RISCV_VIRT | 108 | @@ -XXX,XX +XXX,XX @@ config SIFIVE_E |
| 97 | select SIFIVE_PLIC | 109 | select SIFIVE_PLIC |
| 98 | select SIFIVE_TEST | 110 | select SIFIVE_UART |
| 99 | select VIRTIO_MMIO | 111 | select SIFIVE_E_PRCI |
| 100 | + select FW_CFG_DMA | 112 | + select SIFIVE_E_AON |
| 101 | 113 | select UNIMP | |
| 102 | config SIFIVE_E | 114 | |
| 103 | bool | 115 | config SIFIVE_U |
| 104 | -- | 116 | -- |
| 105 | 2.30.1 | 117 | 2.40.1 |
| 106 | 118 | ||
| 107 | 119 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Tommy Wu <tommy.wu@sifive.com> | ||
| 1 | 2 | ||
| 3 | Add some simple tests of the watchdog timer in the always-on domain device | ||
| 4 | of HiFive 1 rev b. | ||
| 5 | |||
| 6 | Signed-off-by: Tommy Wu <tommy.wu@sifive.com> | ||
| 7 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
| 8 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
| 9 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-Id: <20230627141216.3962299-4-tommy.wu@sifive.com> | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | tests/qtest/sifive-e-aon-watchdog-test.c | 450 +++++++++++++++++++++++ | ||
| 14 | tests/qtest/meson.build | 3 + | ||
| 15 | 2 files changed, 453 insertions(+) | ||
| 16 | create mode 100644 tests/qtest/sifive-e-aon-watchdog-test.c | ||
| 17 | |||
| 18 | diff --git a/tests/qtest/sifive-e-aon-watchdog-test.c b/tests/qtest/sifive-e-aon-watchdog-test.c | ||
| 19 | new file mode 100644 | ||
| 20 | index XXXXXXX..XXXXXXX | ||
| 21 | --- /dev/null | ||
| 22 | +++ b/tests/qtest/sifive-e-aon-watchdog-test.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ | ||
| 24 | +/* | ||
| 25 | + * QTest testcase for the watchdog timer of HiFive 1 rev b. | ||
| 26 | + * | ||
| 27 | + * Copyright (c) 2023 SiFive, Inc. | ||
| 28 | + * | ||
| 29 | + * This program is free software; you can redistribute it and/or modify it | ||
| 30 | + * under the terms and conditions of the GNU General Public License, | ||
| 31 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 32 | + * | ||
| 33 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 34 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 35 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 36 | + * more details. | ||
| 37 | + * | ||
| 38 | + * You should have received a copy of the GNU General Public License along with | ||
| 39 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 40 | + */ | ||
| 41 | + | ||
| 42 | +#include "qemu/osdep.h" | ||
| 43 | +#include "qemu/timer.h" | ||
| 44 | +#include "qemu/bitops.h" | ||
| 45 | +#include "libqtest.h" | ||
| 46 | +#include "hw/registerfields.h" | ||
| 47 | +#include "hw/misc/sifive_e_aon.h" | ||
| 48 | + | ||
| 49 | +FIELD(AON_WDT_WDOGCFG, SCALE, 0, 4) | ||
| 50 | +FIELD(AON_WDT_WDOGCFG, RSVD0, 4, 4) | ||
| 51 | +FIELD(AON_WDT_WDOGCFG, RSTEN, 8, 1) | ||
| 52 | +FIELD(AON_WDT_WDOGCFG, ZEROCMP, 9, 1) | ||
| 53 | +FIELD(AON_WDT_WDOGCFG, RSVD1, 10, 2) | ||
| 54 | +FIELD(AON_WDT_WDOGCFG, EN_ALWAYS, 12, 1) | ||
| 55 | +FIELD(AON_WDT_WDOGCFG, EN_CORE_AWAKE, 13, 1) | ||
| 56 | +FIELD(AON_WDT_WDOGCFG, RSVD2, 14, 14) | ||
| 57 | +FIELD(AON_WDT_WDOGCFG, IP0, 28, 1) | ||
| 58 | +FIELD(AON_WDT_WDOGCFG, RSVD3, 29, 3) | ||
| 59 | + | ||
| 60 | +#define WDOG_BASE (0x10000000) | ||
| 61 | +#define WDOGCFG (0x0) | ||
| 62 | +#define WDOGCOUNT (0x8) | ||
| 63 | +#define WDOGS (0x10) | ||
| 64 | +#define WDOGFEED (0x18) | ||
| 65 | +#define WDOGKEY (0x1c) | ||
| 66 | +#define WDOGCMP0 (0x20) | ||
| 67 | + | ||
| 68 | +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) | ||
| 69 | +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) | ||
| 70 | +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) | ||
| 71 | + | ||
| 72 | +static void test_init(QTestState *qts) | ||
| 73 | +{ | ||
| 74 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 75 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); | ||
| 76 | + | ||
| 77 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 78 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, 0); | ||
| 79 | + | ||
| 80 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 81 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF); | ||
| 82 | +} | ||
| 83 | + | ||
| 84 | +static void test_wdogcount(void) | ||
| 85 | +{ | ||
| 86 | + uint64_t tmp; | ||
| 87 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 88 | + | ||
| 89 | + test_init(qts); | ||
| 90 | + | ||
| 91 | + tmp = qtest_readl(qts, WDOG_BASE + WDOGCOUNT); | ||
| 92 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF); | ||
| 93 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == tmp); | ||
| 94 | + | ||
| 95 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 96 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF); | ||
| 97 | + g_assert(0xBEEF == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 98 | + | ||
| 99 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 100 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xAAAAAAAA); | ||
| 101 | + g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 102 | + | ||
| 103 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 104 | + qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xAAAAAAAA); | ||
| 105 | + g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 106 | + | ||
| 107 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 108 | + qtest_writel(qts, WDOG_BASE + WDOGFEED, SIFIVE_E_AON_WDOGFEED); | ||
| 109 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 110 | + | ||
| 111 | + qtest_quit(qts); | ||
| 112 | +} | ||
| 113 | + | ||
| 114 | +static void test_wdogcfg(void) | ||
| 115 | +{ | ||
| 116 | + uint32_t tmp_cfg; | ||
| 117 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 118 | + | ||
| 119 | + test_init(qts); | ||
| 120 | + | ||
| 121 | + tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 122 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, 0xFFFFFFFF); | ||
| 123 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCFG) == tmp_cfg); | ||
| 124 | + | ||
| 125 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 126 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, 0xFFFFFFFF); | ||
| 127 | + g_assert(0xFFFFFFFF == qtest_readl(qts, WDOG_BASE + WDOGCFG)); | ||
| 128 | + | ||
| 129 | + tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 130 | + g_assert(15 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 131 | + g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 132 | + g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 133 | + g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 134 | + g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 135 | + g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 136 | + | ||
| 137 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 138 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, 0); | ||
| 139 | + tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 140 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 141 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 142 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 143 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 144 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 145 | + g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 146 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCFG)); | ||
| 147 | + | ||
| 148 | + qtest_quit(qts); | ||
| 149 | +} | ||
| 150 | + | ||
| 151 | +static void test_wdogcmp0(void) | ||
| 152 | +{ | ||
| 153 | + uint32_t tmp; | ||
| 154 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 155 | + | ||
| 156 | + test_init(qts); | ||
| 157 | + | ||
| 158 | + tmp = qtest_readl(qts, WDOG_BASE + WDOGCMP0); | ||
| 159 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF); | ||
| 160 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCMP0) == tmp); | ||
| 161 | + | ||
| 162 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 163 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF); | ||
| 164 | + g_assert(0xBEEF == qtest_readl(qts, WDOG_BASE + WDOGCMP0)); | ||
| 165 | + | ||
| 166 | + qtest_quit(qts); | ||
| 167 | +} | ||
| 168 | + | ||
| 169 | +static void test_wdogkey(void) | ||
| 170 | +{ | ||
| 171 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 172 | + | ||
| 173 | + test_init(qts); | ||
| 174 | + | ||
| 175 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY)); | ||
| 176 | + | ||
| 177 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, 0xFFFF); | ||
| 178 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY)); | ||
| 179 | + | ||
| 180 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 181 | + g_assert(1 == qtest_readl(qts, WDOG_BASE + WDOGKEY)); | ||
| 182 | + | ||
| 183 | + qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xAAAAAAAA); | ||
| 184 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY)); | ||
| 185 | + | ||
| 186 | + qtest_quit(qts); | ||
| 187 | +} | ||
| 188 | + | ||
| 189 | +static void test_wdogfeed(void) | ||
| 190 | +{ | ||
| 191 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 192 | + | ||
| 193 | + test_init(qts); | ||
| 194 | + | ||
| 195 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGFEED)); | ||
| 196 | + | ||
| 197 | + qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xFFFF); | ||
| 198 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGFEED)); | ||
| 199 | + | ||
| 200 | + qtest_quit(qts); | ||
| 201 | +} | ||
| 202 | + | ||
| 203 | +static void test_scaled_wdogs(void) | ||
| 204 | +{ | ||
| 205 | + uint32_t cfg; | ||
| 206 | + uint32_t fake_count = 0x12345678; | ||
| 207 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 208 | + | ||
| 209 | + test_init(qts); | ||
| 210 | + | ||
| 211 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 212 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, fake_count); | ||
| 213 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == fake_count); | ||
| 214 | + g_assert((uint16_t)qtest_readl(qts, WDOG_BASE + WDOGS) == | ||
| 215 | + (uint16_t)fake_count); | ||
| 216 | + | ||
| 217 | + for (int i = 0; i < 16; i++) { | ||
| 218 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 219 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, i); | ||
| 220 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 221 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 222 | + g_assert((uint16_t)qtest_readl(qts, WDOG_BASE + WDOGS) == | ||
| 223 | + (uint16_t)(fake_count >> | ||
| 224 | + FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE))); | ||
| 225 | + } | ||
| 226 | + | ||
| 227 | + qtest_quit(qts); | ||
| 228 | +} | ||
| 229 | + | ||
| 230 | +static void test_watchdog(void) | ||
| 231 | +{ | ||
| 232 | + uint32_t cfg; | ||
| 233 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 234 | + | ||
| 235 | + test_init(qts); | ||
| 236 | + | ||
| 237 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 238 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); | ||
| 239 | + | ||
| 240 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 241 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0); | ||
| 242 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); | ||
| 243 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 244 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 245 | + | ||
| 246 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND); | ||
| 247 | + | ||
| 248 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == | ||
| 249 | + SIFIVE_E_LFCLK_DEFAULT_FREQ); | ||
| 250 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGS) == | ||
| 251 | + SIFIVE_E_LFCLK_DEFAULT_FREQ); | ||
| 252 | + | ||
| 253 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 254 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 255 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 256 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 257 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 258 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 259 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 260 | + | ||
| 261 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 262 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); | ||
| 263 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); | ||
| 264 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 265 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 266 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 267 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 268 | + | ||
| 269 | + qtest_quit(qts); | ||
| 270 | +} | ||
| 271 | + | ||
| 272 | +static void test_scaled_watchdog(void) | ||
| 273 | +{ | ||
| 274 | + uint32_t cfg; | ||
| 275 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 276 | + | ||
| 277 | + test_init(qts); | ||
| 278 | + | ||
| 279 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 280 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, 10); | ||
| 281 | + | ||
| 282 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 283 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 15); | ||
| 284 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); | ||
| 285 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 286 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 287 | + | ||
| 288 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 10); | ||
| 289 | + | ||
| 290 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == | ||
| 291 | + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); | ||
| 292 | + | ||
| 293 | + g_assert(10 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 294 | + | ||
| 295 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 296 | + g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 297 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 298 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 299 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 300 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 301 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 302 | + | ||
| 303 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 304 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); | ||
| 305 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); | ||
| 306 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 307 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 308 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 309 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 310 | + | ||
| 311 | + qtest_quit(qts); | ||
| 312 | +} | ||
| 313 | + | ||
| 314 | +static void test_periodic_int(void) | ||
| 315 | +{ | ||
| 316 | + uint32_t cfg; | ||
| 317 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 318 | + | ||
| 319 | + test_init(qts); | ||
| 320 | + | ||
| 321 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 322 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); | ||
| 323 | + | ||
| 324 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 325 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0); | ||
| 326 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, ZEROCMP, 1); | ||
| 327 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); | ||
| 328 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 329 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 330 | + | ||
| 331 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND); | ||
| 332 | + | ||
| 333 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 334 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 335 | + | ||
| 336 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 337 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 338 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 339 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 340 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 341 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 342 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 343 | + | ||
| 344 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); | ||
| 345 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 346 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 347 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 348 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 349 | + | ||
| 350 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND); | ||
| 351 | + | ||
| 352 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); | ||
| 353 | + g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 354 | + | ||
| 355 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 356 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 357 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 358 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 359 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 360 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 361 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 362 | + | ||
| 363 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); | ||
| 364 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 365 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 366 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 367 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 368 | + | ||
| 369 | + qtest_quit(qts); | ||
| 370 | +} | ||
| 371 | + | ||
| 372 | +static void test_enable_disable(void) | ||
| 373 | +{ | ||
| 374 | + uint32_t cfg; | ||
| 375 | + QTestState *qts = qtest_init("-machine sifive_e"); | ||
| 376 | + | ||
| 377 | + test_init(qts); | ||
| 378 | + | ||
| 379 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 380 | + qtest_writel(qts, WDOG_BASE + WDOGCMP0, 10); | ||
| 381 | + | ||
| 382 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 383 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 15); | ||
| 384 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); | ||
| 385 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 386 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 387 | + | ||
| 388 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 2); | ||
| 389 | + | ||
| 390 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == | ||
| 391 | + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); | ||
| 392 | + g_assert(2 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 393 | + | ||
| 394 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 395 | + g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 396 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 397 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 398 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 399 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 400 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 401 | + | ||
| 402 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 403 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 0); | ||
| 404 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 405 | + | ||
| 406 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 8); | ||
| 407 | + | ||
| 408 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == | ||
| 409 | + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); | ||
| 410 | + g_assert(2 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 411 | + | ||
| 412 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 413 | + g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 414 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 415 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 416 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 417 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 418 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 419 | + | ||
| 420 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); | ||
| 421 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 422 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 423 | + | ||
| 424 | + qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 8); | ||
| 425 | + | ||
| 426 | + g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == | ||
| 427 | + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); | ||
| 428 | + g_assert(10 == qtest_readl(qts, WDOG_BASE + WDOGS)); | ||
| 429 | + | ||
| 430 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 431 | + g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)); | ||
| 432 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN)); | ||
| 433 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP)); | ||
| 434 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); | ||
| 435 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); | ||
| 436 | + g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 437 | + | ||
| 438 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 439 | + qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); | ||
| 440 | + cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); | ||
| 441 | + qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); | ||
| 442 | + qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); | ||
| 443 | + cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); | ||
| 444 | + g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); | ||
| 445 | + | ||
| 446 | + qtest_quit(qts); | ||
| 447 | +} | ||
| 448 | + | ||
| 449 | +int main(int argc, char *argv[]) | ||
| 450 | +{ | ||
| 451 | + g_test_init(&argc, &argv, NULL); | ||
| 452 | + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcount", | ||
| 453 | + test_wdogcount); | ||
| 454 | + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcfg", | ||
| 455 | + test_wdogcfg); | ||
| 456 | + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcmp0", | ||
| 457 | + test_wdogcmp0); | ||
| 458 | + qtest_add_func("/sifive-e-aon-watchdog-test/wdogkey", | ||
| 459 | + test_wdogkey); | ||
| 460 | + qtest_add_func("/sifive-e-aon-watchdog-test/wdogfeed", | ||
| 461 | + test_wdogfeed); | ||
| 462 | + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_wdogs", | ||
| 463 | + test_scaled_wdogs); | ||
| 464 | + qtest_add_func("/sifive-e-aon-watchdog-test/watchdog", | ||
| 465 | + test_watchdog); | ||
| 466 | + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_watchdog", | ||
| 467 | + test_scaled_watchdog); | ||
| 468 | + qtest_add_func("/sifive-e-aon-watchdog-test/periodic_int", | ||
| 469 | + test_periodic_int); | ||
| 470 | + qtest_add_func("/sifive-e-aon-watchdog-test/enable_disable", | ||
| 471 | + test_enable_disable); | ||
| 472 | + return g_test_run(); | ||
| 473 | +} | ||
| 474 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
| 475 | index XXXXXXX..XXXXXXX 100644 | ||
| 476 | --- a/tests/qtest/meson.build | ||
| 477 | +++ b/tests/qtest/meson.build | ||
| 478 | @@ -XXX,XX +XXX,XX @@ qtests_s390x = \ | ||
| 479 | 'cpu-plug-test', | ||
| 480 | 'migration-test'] | ||
| 481 | |||
| 482 | +qtests_riscv32 = \ | ||
| 483 | + (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : []) | ||
| 484 | + | ||
| 485 | qos_test_ss = ss.source_set() | ||
| 486 | qos_test_ss.add( | ||
| 487 | 'ac97-test.c', | ||
| 488 | -- | ||
| 489 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 1 | 2 | ||
| 3 | We want to keep the ability to distinct between 32/64-bit host. | ||
| 4 | |||
| 5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-Id: <20230627143235.29947-2-philmd@linaro.org> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | meson.build | 11 ++++------- | ||
| 12 | 1 file changed, 4 insertions(+), 7 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/meson.build b/meson.build | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/meson.build | ||
| 17 | +++ b/meson.build | ||
| 18 | @@ -XXX,XX +XXX,XX @@ qapi_trace_events = [] | ||
| 19 | |||
| 20 | bsd_oses = ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly', 'darwin'] | ||
| 21 | supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] | ||
| 22 | -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', | ||
| 23 | +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', | ||
| 24 | 'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc64'] | ||
| 25 | |||
| 26 | cpu = host_machine.cpu_family() | ||
| 27 | |||
| 28 | -# Unify riscv* to a single family. | ||
| 29 | -if cpu in ['riscv32', 'riscv64'] | ||
| 30 | - cpu = 'riscv' | ||
| 31 | -endif | ||
| 32 | - | ||
| 33 | target_dirs = config_host['TARGET_DIRS'].split() | ||
| 34 | have_linux_user = false | ||
| 35 | have_bsd_user = false | ||
| 36 | @@ -XXX,XX +XXX,XX @@ elif cpu == 'x86' | ||
| 37 | host_arch = 'i386' | ||
| 38 | elif cpu == 'mips64' | ||
| 39 | host_arch = 'mips' | ||
| 40 | +elif cpu in ['riscv32', 'riscv64'] | ||
| 41 | + host_arch = 'riscv' | ||
| 42 | else | ||
| 43 | host_arch = cpu | ||
| 44 | endif | ||
| 45 | @@ -XXX,XX +XXX,XX @@ elif cpu in ['ppc', 'ppc64'] | ||
| 46 | kvm_targets = ['ppc-softmmu', 'ppc64-softmmu'] | ||
| 47 | elif cpu in ['mips', 'mips64'] | ||
| 48 | kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] | ||
| 49 | -elif cpu in ['riscv'] | ||
| 50 | +elif cpu in ['riscv32', 'riscv64'] | ||
| 51 | kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu'] | ||
| 52 | else | ||
| 53 | kvm_targets = [] | ||
| 54 | -- | ||
| 55 | 2.40.1 | ||
| 56 | |||
| 57 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Since HSS commit c20a89f8dcac, the Icicle Kit reference design has | 3 | Per Anup Patel in [*]: |
| 4 | been updated to use a register mapped at 0x4f000000 instead of a | ||
| 5 | GPIO to control whether eMMC or SD card is to be used. With this | ||
| 6 | support the same HSS image can be used for both eMMC and SD card | ||
| 7 | boot flow, while previously two different board configurations were | ||
| 8 | used. This is undocumented but one can take a look at the HSS code | ||
| 9 | HSS_MMCInit() in services/mmc/mmc_api.c. | ||
| 10 | 4 | ||
| 11 | With this commit, HSS image built from 2020.12 release boots again. | 5 | > Currently, we only support running rv64 guest on rv64 host |
| 6 | > and rv32 guest on rv32 host. | ||
| 7 | > | ||
| 8 | > In the future, we might support running rv32 guest on rv64 | ||
| 9 | > host but as of now we don't see a strong push for it. | ||
| 12 | 10 | ||
| 13 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 11 | Therefore, when only using the KVM accelerator it is pointless |
| 12 | to build qemu-system-riscv32 on a rv64 host (or qemu-system-riscv64 | ||
| 13 | on a rv32 host). Restrict meson to only build the correct binary, | ||
| 14 | avoiding to waste ressources building unusable code. | ||
| 15 | |||
| 16 | [*] https://lore.kernel.org/qemu-devel/CAAhSdy2JeRHeeoEc1XKQhPO3aDz4YKeyQsPT4S8yKJcYTA+AiQ@mail.gmail.com/ | ||
| 17 | |||
| 18 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 15 | Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com | 21 | Message-Id: <20230627143235.29947-3-philmd@linaro.org> |
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 17 | --- | 23 | --- |
| 18 | include/hw/riscv/microchip_pfsoc.h | 1 + | 24 | meson.build | 6 ++++-- |
| 19 | hw/riscv/microchip_pfsoc.c | 6 ++++++ | 25 | 1 file changed, 4 insertions(+), 2 deletions(-) |
| 20 | 2 files changed, 7 insertions(+) | ||
| 21 | 26 | ||
| 22 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 27 | diff --git a/meson.build b/meson.build |
| 23 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/include/hw/riscv/microchip_pfsoc.h | 29 | --- a/meson.build |
| 25 | +++ b/include/hw/riscv/microchip_pfsoc.h | 30 | +++ b/meson.build |
| 26 | @@ -XXX,XX +XXX,XX @@ enum { | 31 | @@ -XXX,XX +XXX,XX @@ elif cpu in ['ppc', 'ppc64'] |
| 27 | MICROCHIP_PFSOC_ENVM_DATA, | 32 | kvm_targets = ['ppc-softmmu', 'ppc64-softmmu'] |
| 28 | MICROCHIP_PFSOC_QSPI_XIP, | 33 | elif cpu in ['mips', 'mips64'] |
| 29 | MICROCHIP_PFSOC_IOSCB, | 34 | kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] |
| 30 | + MICROCHIP_PFSOC_EMMC_SD_MUX, | 35 | -elif cpu in ['riscv32', 'riscv64'] |
| 31 | MICROCHIP_PFSOC_DRAM_LO, | 36 | - kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu'] |
| 32 | MICROCHIP_PFSOC_DRAM_LO_ALIAS, | 37 | +elif cpu in ['riscv32'] |
| 33 | MICROCHIP_PFSOC_DRAM_HI, | 38 | + kvm_targets = ['riscv32-softmmu'] |
| 34 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | 39 | +elif cpu in ['riscv64'] |
| 35 | index XXXXXXX..XXXXXXX 100644 | 40 | + kvm_targets = ['riscv64-softmmu'] |
| 36 | --- a/hw/riscv/microchip_pfsoc.c | 41 | else |
| 37 | +++ b/hw/riscv/microchip_pfsoc.c | 42 | kvm_targets = [] |
| 38 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = { | 43 | endif |
| 39 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, | ||
| 40 | [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, | ||
| 41 | [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, | ||
| 42 | + [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 }, | ||
| 43 | [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, | ||
| 44 | [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, | ||
| 45 | [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
| 47 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, | ||
| 48 | memmap[MICROCHIP_PFSOC_IOSCB].base); | ||
| 49 | |||
| 50 | + /* eMMC/SD mux */ | ||
| 51 | + create_unimplemented_device("microchip.pfsoc.emmc_sd_mux", | ||
| 52 | + memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base, | ||
| 53 | + memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size); | ||
| 54 | + | ||
| 55 | /* QSPI Flash */ | ||
| 56 | memory_region_init_rom(qspi_xip_mem, OBJECT(dev), | ||
| 57 | "microchip.pfsoc.qspi_xip", | ||
| 58 | -- | 44 | -- |
| 59 | 2.30.1 | 45 | 2.40.1 |
| 60 | 46 | ||
| 61 | 47 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Ivan Klokov <ivan.klokov@syntacore.com> | ||
| 1 | 2 | ||
| 3 | Print RvV extension register to log if VPU option is enabled. | ||
| 4 | |||
| 5 | Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> | ||
| 6 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-Id: <20230629083730.386604-1-ivan.klokov@syntacore.com> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++- | ||
| 12 | 1 file changed, 56 insertions(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/riscv/cpu.c | ||
| 17 | +++ b/target/riscv/cpu.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ struct isa_ext_data { | ||
| 19 | #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ | ||
| 20 | {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} | ||
| 21 | |||
| 22 | +/* | ||
| 23 | + * From vector_helper.c | ||
| 24 | + * Note that vector data is stored in host-endian 64-bit chunks, | ||
| 25 | + * so addressing bytes needs a host-endian fixup. | ||
| 26 | + */ | ||
| 27 | +#if HOST_BIG_ENDIAN | ||
| 28 | +#define BYTE(x) ((x) ^ 7) | ||
| 29 | +#else | ||
| 30 | +#define BYTE(x) (x) | ||
| 31 | +#endif | ||
| 32 | + | ||
| 33 | /* | ||
| 34 | * Here are the ordering rules of extension naming defined by RISC-V | ||
| 35 | * specification : | ||
| 36 | @@ -XXX,XX +XXX,XX @@ const char * const riscv_fpr_regnames[] = { | ||
| 37 | "f30/ft10", "f31/ft11" | ||
| 38 | }; | ||
| 39 | |||
| 40 | +const char * const riscv_rvv_regnames[] = { | ||
| 41 | + "v0", "v1", "v2", "v3", "v4", "v5", "v6", | ||
| 42 | + "v7", "v8", "v9", "v10", "v11", "v12", "v13", | ||
| 43 | + "v14", "v15", "v16", "v17", "v18", "v19", "v20", | ||
| 44 | + "v21", "v22", "v23", "v24", "v25", "v26", "v27", | ||
| 45 | + "v28", "v29", "v30", "v31" | ||
| 46 | +}; | ||
| 47 | + | ||
| 48 | static const char * const riscv_excp_names[] = { | ||
| 49 | "misaligned_fetch", | ||
| 50 | "fault_fetch", | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) | ||
| 52 | { | ||
| 53 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 54 | CPURISCVState *env = &cpu->env; | ||
| 55 | - int i; | ||
| 56 | + int i, j; | ||
| 57 | + uint8_t *p; | ||
| 58 | |||
| 59 | #if !defined(CONFIG_USER_ONLY) | ||
| 60 | if (riscv_has_ext(env, RVH)) { | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) | ||
| 62 | } | ||
| 63 | } | ||
| 64 | } | ||
| 65 | + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { | ||
| 66 | + static const int dump_rvv_csrs[] = { | ||
| 67 | + CSR_VSTART, | ||
| 68 | + CSR_VXSAT, | ||
| 69 | + CSR_VXRM, | ||
| 70 | + CSR_VCSR, | ||
| 71 | + CSR_VL, | ||
| 72 | + CSR_VTYPE, | ||
| 73 | + CSR_VLENB, | ||
| 74 | + }; | ||
| 75 | + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { | ||
| 76 | + int csrno = dump_rvv_csrs[i]; | ||
| 77 | + target_ulong val = 0; | ||
| 78 | + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); | ||
| 79 | + | ||
| 80 | + /* | ||
| 81 | + * Rely on the smode, hmode, etc, predicates within csr.c | ||
| 82 | + * to do the filtering of the registers that are present. | ||
| 83 | + */ | ||
| 84 | + if (res == RISCV_EXCP_NONE) { | ||
| 85 | + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", | ||
| 86 | + csr_ops[csrno].name, val); | ||
| 87 | + } | ||
| 88 | + } | ||
| 89 | + uint16_t vlenb = cpu->cfg.vlen >> 3; | ||
| 90 | + | ||
| 91 | + for (i = 0; i < 32; i++) { | ||
| 92 | + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); | ||
| 93 | + p = (uint8_t *)env->vreg; | ||
| 94 | + for (j = vlenb - 1 ; j >= 0; j--) { | ||
| 95 | + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); | ||
| 96 | + } | ||
| 97 | + qemu_fprintf(f, "\n"); | ||
| 98 | + } | ||
| 99 | + } | ||
| 100 | } | ||
| 101 | |||
| 102 | static void riscv_cpu_set_pc(CPUState *cs, vaddr value) | ||
| 103 | -- | ||
| 104 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Alexander Wagner <alexander.wagner@ulal.de> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Not disabling the UART leads to QEMU overwriting the UART receive buffer with | 3 | The Advanced Core Local Interruptor (ACLINT) device can |
| 4 | the newest received byte. The rx_level variable is added to allow the use of | 4 | only be used with TCG. Check for TCG enabled instead of |
| 5 | the existing OpenTitan driver libraries. | 5 | KVM being not. Only add the property when TCG is used. |
| 6 | 6 | ||
| 7 | Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de> | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 9 | Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de | 10 | Message-Id: <20230629121103.87733-3-philmd@linaro.org> |
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 12 | --- |
| 12 | include/hw/char/ibex_uart.h | 4 ++++ | 13 | docs/system/riscv/virt.rst | 1 + |
| 13 | hw/char/ibex_uart.c | 23 ++++++++++++++++++----- | 14 | hw/riscv/virt.c | 18 ++++++++++-------- |
| 14 | 2 files changed, 22 insertions(+), 5 deletions(-) | 15 | 2 files changed, 11 insertions(+), 8 deletions(-) |
| 15 | 16 | ||
| 16 | diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h | 17 | diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst |
| 17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/char/ibex_uart.h | 19 | --- a/docs/system/riscv/virt.rst |
| 19 | +++ b/include/hw/char/ibex_uart.h | 20 | +++ b/docs/system/riscv/virt.rst |
| 20 | @@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c) | 21 | @@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported: |
| 21 | FIELD(FIFO_CTRL, RXILVL, 2, 3) | 22 | |
| 22 | FIELD(FIFO_CTRL, TXILVL, 5, 2) | 23 | When this option is "on", ACLINT devices will be emulated instead of |
| 23 | REG32(FIFO_STATUS, 0x20) | 24 | SiFive CLINT. When not specified, this option is assumed to be "off". |
| 24 | + FIELD(FIFO_STATUS, TXLVL, 0, 5) | 25 | + This option is restricted to the TCG accelerator. |
| 25 | + FIELD(FIFO_STATUS, RXLVL, 16, 5) | 26 | |
| 26 | REG32(OVRD, 0x24) | 27 | - aia=[none|aplic|aplic-imsic] |
| 27 | REG32(VAL, 0x28) | 28 | |
| 28 | REG32(TIMEOUT_CTRL, 0x2c) | 29 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 29 | @@ -XXX,XX +XXX,XX @@ struct IbexUartState { | ||
| 30 | uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; | ||
| 31 | uint32_t tx_level; | ||
| 32 | |||
| 33 | + uint32_t rx_level; | ||
| 34 | + | ||
| 35 | QEMUTimer *fifo_trigger_handle; | ||
| 36 | uint64_t char_tx_time; | ||
| 37 | |||
| 38 | diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
| 40 | --- a/hw/char/ibex_uart.c | 31 | --- a/hw/riscv/virt.c |
| 41 | +++ b/hw/char/ibex_uart.c | 32 | +++ b/hw/riscv/virt.c |
| 42 | @@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque) | 33 | @@ -XXX,XX +XXX,XX @@ |
| 43 | { | 34 | #include "chardev/char.h" |
| 44 | IbexUartState *s = opaque; | 35 | #include "sysemu/device_tree.h" |
| 45 | 36 | #include "sysemu/sysemu.h" | |
| 46 | - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { | 37 | +#include "sysemu/tcg.h" |
| 47 | + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) | 38 | #include "sysemu/kvm.h" |
| 48 | + && !(s->uart_status & R_STATUS_RXFULL_MASK)) { | 39 | #include "sysemu/tpm.h" |
| 49 | return 1; | 40 | #include "hw/pci/pci.h" |
| 50 | } | 41 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, |
| 51 | 42 | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) | 43 | g_free(clust_name); |
| 53 | 44 | ||
| 54 | s->uart_status &= ~R_STATUS_RXIDLE_MASK; | 45 | - if (!kvm_enabled()) { |
| 55 | s->uart_status &= ~R_STATUS_RXEMPTY_MASK; | 46 | + if (tcg_enabled()) { |
| 56 | + /* The RXFULL is set after receiving a single byte | 47 | if (s->have_aclint) { |
| 57 | + * as the FIFO buffers are not yet implemented. | 48 | create_fdt_socket_aclint(s, memmap, socket, |
| 58 | + */ | 49 | &intc_phandles[phandle_pos]); |
| 59 | + s->uart_status |= R_STATUS_RXFULL_MASK; | 50 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
| 60 | + s->rx_level += 1; | 51 | hart_count, &error_abort); |
| 61 | 52 | sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); | |
| 62 | if (size > rx_fifo_level) { | 53 | |
| 63 | s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; | 54 | - if (!kvm_enabled()) { |
| 64 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev) | 55 | + if (tcg_enabled()) { |
| 65 | s->uart_timeout_ctrl = 0x00000000; | 56 | if (s->have_aclint) { |
| 66 | 57 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { | |
| 67 | s->tx_level = 0; | 58 | /* Per-socket ACLINT MTIMER */ |
| 68 | + s->rx_level = 0; | 59 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) |
| 69 | 60 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); | |
| 70 | s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; | 61 | #endif |
| 71 | 62 | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, | 63 | - object_class_property_add_bool(oc, "aclint", virt_get_aclint, |
| 73 | 64 | - virt_set_aclint); | |
| 74 | case R_RDATA: | 65 | - object_class_property_set_description(oc, "aclint", |
| 75 | retvalue = s->uart_rdata; | 66 | - "Set on/off to enable/disable " |
| 76 | - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { | 67 | - "emulating ACLINT devices"); |
| 77 | + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { | 68 | - |
| 78 | qemu_chr_fe_accept_input(&s->chr); | 69 | + if (tcg_enabled()) { |
| 79 | 70 | + object_class_property_add_bool(oc, "aclint", virt_get_aclint, | |
| 80 | - s->uart_status |= R_STATUS_RXIDLE_MASK; | 71 | + virt_set_aclint); |
| 81 | - s->uart_status |= R_STATUS_RXEMPTY_MASK; | 72 | + object_class_property_set_description(oc, "aclint", |
| 82 | + s->rx_level -= 1; | 73 | + "Set on/off to enable/disable " |
| 83 | + s->uart_status &= ~R_STATUS_RXFULL_MASK; | 74 | + "emulating ACLINT devices"); |
| 84 | + if (s->rx_level == 0) { | 75 | + } |
| 85 | + s->uart_status |= R_STATUS_RXIDLE_MASK; | 76 | object_class_property_add_str(oc, "aia", virt_get_aia, |
| 86 | + s->uart_status |= R_STATUS_RXEMPTY_MASK; | 77 | virt_set_aia); |
| 87 | + } | 78 | object_class_property_set_description(oc, "aia", |
| 88 | } | ||
| 89 | break; | ||
| 90 | case R_WDATA: | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, | ||
| 92 | case R_FIFO_STATUS: | ||
| 93 | retvalue = s->uart_fifo_status; | ||
| 94 | |||
| 95 | - retvalue |= s->tx_level & 0x1F; | ||
| 96 | + retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; | ||
| 97 | + retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; | ||
| 98 | |||
| 99 | qemu_log_mask(LOG_UNIMP, | ||
| 100 | "%s: RX fifos are not supported\n", __func__); | ||
| 101 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr, | ||
| 102 | s->uart_fifo_ctrl = value; | ||
| 103 | |||
| 104 | if (value & R_FIFO_CTRL_RXRST_MASK) { | ||
| 105 | + s->rx_level = 0; | ||
| 106 | qemu_log_mask(LOG_UNIMP, | ||
| 107 | "%s: RX fifos are not supported\n", __func__); | ||
| 108 | } | ||
| 109 | -- | 79 | -- |
| 110 | 2.30.1 | 80 | 2.40.1 |
| 111 | 81 | ||
| 112 | 82 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Robbin Ehn <rehn@rivosinc.com> | ||
| 1 | 2 | ||
| 3 | This patch adds the new syscall for the | ||
| 4 | "RISC-V Hardware Probing Interface" | ||
| 5 | (https://docs.kernel.org/riscv/hwprobe.html). | ||
| 6 | |||
| 7 | Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> | ||
| 8 | Signed-off-by: Robbin Ehn <rehn@rivosinc.com> | ||
| 9 | Message-Id: <06a4543df2aa6101ca9a48f21a3198064b4f1f87.camel@rivosinc.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | linux-user/riscv/syscall32_nr.h | 1 + | ||
| 13 | linux-user/riscv/syscall64_nr.h | 1 + | ||
| 14 | linux-user/syscall.c | 146 ++++++++++++++++++++++++++++++++ | ||
| 15 | 3 files changed, 148 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_nr.h | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/linux-user/riscv/syscall32_nr.h | ||
| 20 | +++ b/linux-user/riscv/syscall32_nr.h | ||
| 21 | @@ -XXX,XX +XXX,XX @@ | ||
| 22 | #define TARGET_NR_accept4 242 | ||
| 23 | #define TARGET_NR_arch_specific_syscall 244 | ||
| 24 | #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) | ||
| 25 | +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) | ||
| 26 | #define TARGET_NR_prlimit64 261 | ||
| 27 | #define TARGET_NR_fanotify_init 262 | ||
| 28 | #define TARGET_NR_fanotify_mark 263 | ||
| 29 | diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_nr.h | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/linux-user/riscv/syscall64_nr.h | ||
| 32 | +++ b/linux-user/riscv/syscall64_nr.h | ||
| 33 | @@ -XXX,XX +XXX,XX @@ | ||
| 34 | #define TARGET_NR_recvmmsg 243 | ||
| 35 | #define TARGET_NR_arch_specific_syscall 244 | ||
| 36 | #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) | ||
| 37 | +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) | ||
| 38 | #define TARGET_NR_wait4 260 | ||
| 39 | #define TARGET_NR_prlimit64 261 | ||
| 40 | #define TARGET_NR_fanotify_init 262 | ||
| 41 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/linux-user/syscall.c | ||
| 44 | +++ b/linux-user/syscall.c | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) | ||
| 46 | } | ||
| 47 | #endif /* TARGET_NR_getdents64 */ | ||
| 48 | |||
| 49 | +#if defined(TARGET_NR_riscv_hwprobe) | ||
| 50 | + | ||
| 51 | +#define RISCV_HWPROBE_KEY_MVENDORID 0 | ||
| 52 | +#define RISCV_HWPROBE_KEY_MARCHID 1 | ||
| 53 | +#define RISCV_HWPROBE_KEY_MIMPID 2 | ||
| 54 | + | ||
| 55 | +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 | ||
| 56 | +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) | ||
| 57 | + | ||
| 58 | +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 | ||
| 59 | +#define RISCV_HWPROBE_IMA_FD (1 << 0) | ||
| 60 | +#define RISCV_HWPROBE_IMA_C (1 << 1) | ||
| 61 | + | ||
| 62 | +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 | ||
| 63 | +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) | ||
| 64 | +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) | ||
| 65 | +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) | ||
| 66 | +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) | ||
| 67 | +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) | ||
| 68 | +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) | ||
| 69 | + | ||
| 70 | +struct riscv_hwprobe { | ||
| 71 | + abi_llong key; | ||
| 72 | + abi_ullong value; | ||
| 73 | +}; | ||
| 74 | + | ||
| 75 | +static void risc_hwprobe_fill_pairs(CPURISCVState *env, | ||
| 76 | + struct riscv_hwprobe *pair, | ||
| 77 | + size_t pair_count) | ||
| 78 | +{ | ||
| 79 | + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); | ||
| 80 | + | ||
| 81 | + for (; pair_count > 0; pair_count--, pair++) { | ||
| 82 | + abi_llong key; | ||
| 83 | + abi_ullong value; | ||
| 84 | + __put_user(0, &pair->value); | ||
| 85 | + __get_user(key, &pair->key); | ||
| 86 | + switch (key) { | ||
| 87 | + case RISCV_HWPROBE_KEY_MVENDORID: | ||
| 88 | + __put_user(cfg->mvendorid, &pair->value); | ||
| 89 | + break; | ||
| 90 | + case RISCV_HWPROBE_KEY_MARCHID: | ||
| 91 | + __put_user(cfg->marchid, &pair->value); | ||
| 92 | + break; | ||
| 93 | + case RISCV_HWPROBE_KEY_MIMPID: | ||
| 94 | + __put_user(cfg->mimpid, &pair->value); | ||
| 95 | + break; | ||
| 96 | + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: | ||
| 97 | + value = riscv_has_ext(env, RVI) && | ||
| 98 | + riscv_has_ext(env, RVM) && | ||
| 99 | + riscv_has_ext(env, RVA) ? | ||
| 100 | + RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0; | ||
| 101 | + __put_user(value, &pair->value); | ||
| 102 | + break; | ||
| 103 | + case RISCV_HWPROBE_KEY_IMA_EXT_0: | ||
| 104 | + value = riscv_has_ext(env, RVF) && | ||
| 105 | + riscv_has_ext(env, RVD) ? | ||
| 106 | + RISCV_HWPROBE_IMA_FD : 0; | ||
| 107 | + value |= riscv_has_ext(env, RVC) ? | ||
| 108 | + RISCV_HWPROBE_IMA_C : pair->value; | ||
| 109 | + __put_user(value, &pair->value); | ||
| 110 | + break; | ||
| 111 | + case RISCV_HWPROBE_KEY_CPUPERF_0: | ||
| 112 | + __put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value); | ||
| 113 | + break; | ||
| 114 | + default: | ||
| 115 | + __put_user(-1, &pair->key); | ||
| 116 | + break; | ||
| 117 | + } | ||
| 118 | + } | ||
| 119 | +} | ||
| 120 | + | ||
| 121 | +static int cpu_set_valid(abi_long arg3, abi_long arg4) | ||
| 122 | +{ | ||
| 123 | + int ret, i, tmp; | ||
| 124 | + size_t host_mask_size, target_mask_size; | ||
| 125 | + unsigned long *host_mask; | ||
| 126 | + | ||
| 127 | + /* | ||
| 128 | + * cpu_set_t represent CPU masks as bit masks of type unsigned long *. | ||
| 129 | + * arg3 contains the cpu count. | ||
| 130 | + */ | ||
| 131 | + tmp = (8 * sizeof(abi_ulong)); | ||
| 132 | + target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong); | ||
| 133 | + host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) & | ||
| 134 | + ~(sizeof(*host_mask) - 1); | ||
| 135 | + | ||
| 136 | + host_mask = alloca(host_mask_size); | ||
| 137 | + | ||
| 138 | + ret = target_to_host_cpu_mask(host_mask, host_mask_size, | ||
| 139 | + arg4, target_mask_size); | ||
| 140 | + if (ret != 0) { | ||
| 141 | + return ret; | ||
| 142 | + } | ||
| 143 | + | ||
| 144 | + for (i = 0 ; i < host_mask_size / sizeof(*host_mask); i++) { | ||
| 145 | + if (host_mask[i] != 0) { | ||
| 146 | + return 0; | ||
| 147 | + } | ||
| 148 | + } | ||
| 149 | + return -TARGET_EINVAL; | ||
| 150 | +} | ||
| 151 | + | ||
| 152 | +static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1, | ||
| 153 | + abi_long arg2, abi_long arg3, | ||
| 154 | + abi_long arg4, abi_long arg5) | ||
| 155 | +{ | ||
| 156 | + int ret; | ||
| 157 | + struct riscv_hwprobe *host_pairs; | ||
| 158 | + | ||
| 159 | + /* flags must be 0 */ | ||
| 160 | + if (arg5 != 0) { | ||
| 161 | + return -TARGET_EINVAL; | ||
| 162 | + } | ||
| 163 | + | ||
| 164 | + /* check cpu_set */ | ||
| 165 | + if (arg3 != 0) { | ||
| 166 | + ret = cpu_set_valid(arg3, arg4); | ||
| 167 | + if (ret != 0) { | ||
| 168 | + return ret; | ||
| 169 | + } | ||
| 170 | + } else if (arg4 != 0) { | ||
| 171 | + return -TARGET_EINVAL; | ||
| 172 | + } | ||
| 173 | + | ||
| 174 | + /* no pairs */ | ||
| 175 | + if (arg2 == 0) { | ||
| 176 | + return 0; | ||
| 177 | + } | ||
| 178 | + | ||
| 179 | + host_pairs = lock_user(VERIFY_WRITE, arg1, | ||
| 180 | + sizeof(*host_pairs) * (size_t)arg2, 0); | ||
| 181 | + if (host_pairs == NULL) { | ||
| 182 | + return -TARGET_EFAULT; | ||
| 183 | + } | ||
| 184 | + risc_hwprobe_fill_pairs(cpu_env, host_pairs, arg2); | ||
| 185 | + unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2); | ||
| 186 | + return 0; | ||
| 187 | +} | ||
| 188 | +#endif /* TARGET_NR_riscv_hwprobe */ | ||
| 189 | + | ||
| 190 | #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root) | ||
| 191 | _syscall2(int, pivot_root, const char *, new_root, const char *, put_old) | ||
| 192 | #endif | ||
| 193 | @@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, | ||
| 194 | return ret; | ||
| 195 | #endif | ||
| 196 | |||
| 197 | +#if defined(TARGET_NR_riscv_hwprobe) | ||
| 198 | + case TARGET_NR_riscv_hwprobe: | ||
| 199 | + return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5); | ||
| 200 | +#endif | ||
| 201 | + | ||
| 202 | default: | ||
| 203 | qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num); | ||
| 204 | return -TARGET_ENOSYS; | ||
| 205 | -- | ||
| 206 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. | ||
| 4 | Add require check for BF16 extensions. | ||
| 5 | |||
| 6 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 7 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 9 | Message-Id: <20230615063302.102409-2-liweiwei@iscas.ac.cn> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | target/riscv/cpu_cfg.h | 3 +++ | ||
| 13 | target/riscv/cpu.c | 20 ++++++++++++++++++++ | ||
| 14 | 2 files changed, 23 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/riscv/cpu_cfg.h | ||
| 19 | +++ b/target/riscv/cpu_cfg.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
| 21 | bool ext_svpbmt; | ||
| 22 | bool ext_zdinx; | ||
| 23 | bool ext_zawrs; | ||
| 24 | + bool ext_zfbfmin; | ||
| 25 | bool ext_zfh; | ||
| 26 | bool ext_zfhmin; | ||
| 27 | bool ext_zfinx; | ||
| 28 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
| 29 | bool ext_zve64f; | ||
| 30 | bool ext_zve64d; | ||
| 31 | bool ext_zmmul; | ||
| 32 | + bool ext_zvfbfmin; | ||
| 33 | + bool ext_zvfbfwma; | ||
| 34 | bool ext_zvfh; | ||
| 35 | bool ext_zvfhmin; | ||
| 36 | bool ext_smaia; | ||
| 37 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/target/riscv/cpu.c | ||
| 40 | +++ b/target/riscv/cpu.c | ||
| 41 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
| 42 | return; | ||
| 43 | } | ||
| 44 | |||
| 45 | + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { | ||
| 46 | + error_setg(errp, "Zfbfmin extension depends on F extension"); | ||
| 47 | + return; | ||
| 48 | + } | ||
| 49 | + | ||
| 50 | if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { | ||
| 51 | error_setg(errp, "D extension requires F extension"); | ||
| 52 | return; | ||
| 53 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
| 54 | return; | ||
| 55 | } | ||
| 56 | |||
| 57 | + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { | ||
| 58 | + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); | ||
| 59 | + return; | ||
| 60 | + } | ||
| 61 | + | ||
| 62 | + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { | ||
| 63 | + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); | ||
| 64 | + return; | ||
| 65 | + } | ||
| 66 | + | ||
| 67 | + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { | ||
| 68 | + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); | ||
| 69 | + return; | ||
| 70 | + } | ||
| 71 | + | ||
| 72 | /* Set the ISA extensions, checks should have happened above */ | ||
| 73 | if (cpu->cfg.ext_zhinx) { | ||
| 74 | cpu->cfg.ext_zhinxmin = true; | ||
| 75 | -- | ||
| 76 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Add trans_* and helper function for Zfbfmin instructions. | ||
| 4 | |||
| 5 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 6 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-Id: <20230615063302.102409-3-liweiwei@iscas.ac.cn> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/helper.h | 4 ++ | ||
| 12 | target/riscv/insn32.decode | 4 ++ | ||
| 13 | target/riscv/fpu_helper.c | 12 +++++ | ||
| 14 | target/riscv/translate.c | 1 + | ||
| 15 | target/riscv/insn_trans/trans_rvbf16.c.inc | 53 ++++++++++++++++++++++ | ||
| 16 | target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++--- | ||
| 17 | 6 files changed, 80 insertions(+), 6 deletions(-) | ||
| 18 | create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 19 | |||
| 20 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/riscv/helper.h | ||
| 23 | +++ b/target/riscv/helper.h | ||
| 24 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) | ||
| 25 | |||
| 26 | /* Zce helper */ | ||
| 27 | DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) | ||
| 28 | + | ||
| 29 | +/* BF16 functions */ | ||
| 30 | +DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 31 | +DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 32 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/riscv/insn32.decode | ||
| 35 | +++ b/target/riscv/insn32.decode | ||
| 36 | @@ -XXX,XX +XXX,XX @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes | ||
| 37 | # *** RV32 Zicond Standard Extension *** | ||
| 38 | czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r | ||
| 39 | czero_nez 0000111 ..... ..... 111 ..... 0110011 @r | ||
| 40 | + | ||
| 41 | +# *** Zfbfmin Standard Extension *** | ||
| 42 | +fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm | ||
| 43 | +fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm | ||
| 44 | diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c | ||
| 45 | index XXXXXXX..XXXXXXX 100644 | ||
| 46 | --- a/target/riscv/fpu_helper.c | ||
| 47 | +++ b/target/riscv/fpu_helper.c | ||
| 48 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1) | ||
| 49 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 50 | return float16_to_float64(frs1, true, &env->fp_status); | ||
| 51 | } | ||
| 52 | + | ||
| 53 | +uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1) | ||
| 54 | +{ | ||
| 55 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 56 | + return nanbox_h(env, float32_to_bfloat16(frs1, &env->fp_status)); | ||
| 57 | +} | ||
| 58 | + | ||
| 59 | +uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1) | ||
| 60 | +{ | ||
| 61 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 62 | + return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status)); | ||
| 63 | +} | ||
| 64 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/target/riscv/translate.c | ||
| 67 | +++ b/target/riscv/translate.c | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) | ||
| 69 | #include "insn_trans/trans_rvk.c.inc" | ||
| 70 | #include "insn_trans/trans_privileged.c.inc" | ||
| 71 | #include "insn_trans/trans_svinval.c.inc" | ||
| 72 | +#include "insn_trans/trans_rvbf16.c.inc" | ||
| 73 | #include "decode-xthead.c.inc" | ||
| 74 | #include "insn_trans/trans_xthead.c.inc" | ||
| 75 | #include "insn_trans/trans_xventanacondops.c.inc" | ||
| 76 | diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 77 | new file mode 100644 | ||
| 78 | index XXXXXXX..XXXXXXX | ||
| 79 | --- /dev/null | ||
| 80 | +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 81 | @@ -XXX,XX +XXX,XX @@ | ||
| 82 | +/* | ||
| 83 | + * RISC-V translation routines for the BF16 Standard Extensions. | ||
| 84 | + * | ||
| 85 | + * Copyright (c) 2020-2023 PLCT Lab | ||
| 86 | + * | ||
| 87 | + * This program is free software; you can redistribute it and/or modify it | ||
| 88 | + * under the terms and conditions of the GNU General Public License, | ||
| 89 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 90 | + * | ||
| 91 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 92 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 93 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 94 | + * more details. | ||
| 95 | + * | ||
| 96 | + * You should have received a copy of the GNU General Public License along with | ||
| 97 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 98 | + */ | ||
| 99 | + | ||
| 100 | +#define REQUIRE_ZFBFMIN(ctx) do { \ | ||
| 101 | + if (!ctx->cfg_ptr->ext_zfbfmin) { \ | ||
| 102 | + return false; \ | ||
| 103 | + } \ | ||
| 104 | +} while (0) | ||
| 105 | + | ||
| 106 | +static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a) | ||
| 107 | +{ | ||
| 108 | + REQUIRE_FPU; | ||
| 109 | + REQUIRE_ZFBFMIN(ctx); | ||
| 110 | + | ||
| 111 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 112 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 113 | + | ||
| 114 | + gen_set_rm(ctx, a->rm); | ||
| 115 | + gen_helper_fcvt_bf16_s(dest, cpu_env, src1); | ||
| 116 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 117 | + mark_fs_dirty(ctx); | ||
| 118 | + return true; | ||
| 119 | +} | ||
| 120 | + | ||
| 121 | +static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a) | ||
| 122 | +{ | ||
| 123 | + REQUIRE_FPU; | ||
| 124 | + REQUIRE_ZFBFMIN(ctx); | ||
| 125 | + | ||
| 126 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 127 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 128 | + | ||
| 129 | + gen_set_rm(ctx, a->rm); | ||
| 130 | + gen_helper_fcvt_s_bf16(dest, cpu_env, src1); | ||
| 131 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 132 | + mark_fs_dirty(ctx); | ||
| 133 | + return true; | ||
| 134 | +} | ||
| 135 | diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc | ||
| 136 | index XXXXXXX..XXXXXXX 100644 | ||
| 137 | --- a/target/riscv/insn_trans/trans_rvzfh.c.inc | ||
| 138 | +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc | ||
| 139 | @@ -XXX,XX +XXX,XX @@ | ||
| 140 | } \ | ||
| 141 | } while (0) | ||
| 142 | |||
| 143 | -#define REQUIRE_ZFHMIN(ctx) do { \ | ||
| 144 | - if (!ctx->cfg_ptr->ext_zfhmin) { \ | ||
| 145 | +#define REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx) do { \ | ||
| 146 | + if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin) { \ | ||
| 147 | return false; \ | ||
| 148 | } \ | ||
| 149 | } while (0) | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) | ||
| 151 | TCGv t0; | ||
| 152 | |||
| 153 | REQUIRE_FPU; | ||
| 154 | - REQUIRE_ZFHMIN(ctx); | ||
| 155 | + REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); | ||
| 156 | |||
| 157 | decode_save_opc(ctx); | ||
| 158 | t0 = get_gpr(ctx, a->rs1, EXT_NONE); | ||
| 159 | @@ -XXX,XX +XXX,XX @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) | ||
| 160 | TCGv t0; | ||
| 161 | |||
| 162 | REQUIRE_FPU; | ||
| 163 | - REQUIRE_ZFHMIN(ctx); | ||
| 164 | + REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); | ||
| 165 | |||
| 166 | decode_save_opc(ctx); | ||
| 167 | t0 = get_gpr(ctx, a->rs1, EXT_NONE); | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) | ||
| 169 | static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) | ||
| 170 | { | ||
| 171 | REQUIRE_FPU; | ||
| 172 | - REQUIRE_ZFHMIN(ctx); | ||
| 173 | + REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); | ||
| 174 | |||
| 175 | TCGv dest = dest_gpr(ctx, a->rd); | ||
| 176 | |||
| 177 | @@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) | ||
| 178 | static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) | ||
| 179 | { | ||
| 180 | REQUIRE_FPU; | ||
| 181 | - REQUIRE_ZFHMIN(ctx); | ||
| 182 | + REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); | ||
| 183 | |||
| 184 | TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO); | ||
| 185 | |||
| 186 | -- | ||
| 187 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Add trans_* and helper function for Zvfbfmin instructions. | ||
| 4 | |||
| 5 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 6 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-Id: <20230615063302.102409-4-liweiwei@iscas.ac.cn> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/helper.h | 3 + | ||
| 12 | target/riscv/insn32.decode | 4 ++ | ||
| 13 | target/riscv/vector_helper.c | 6 ++ | ||
| 14 | target/riscv/insn_trans/trans_rvbf16.c.inc | 64 ++++++++++++++++++++++ | ||
| 15 | 4 files changed, 77 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/riscv/helper.h | ||
| 20 | +++ b/target/riscv/helper.h | ||
| 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) | ||
| 22 | /* BF16 functions */ | ||
| 23 | DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 24 | DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 25 | + | ||
| 26 | +DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32) | ||
| 27 | +DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32) | ||
| 28 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/riscv/insn32.decode | ||
| 31 | +++ b/target/riscv/insn32.decode | ||
| 32 | @@ -XXX,XX +XXX,XX @@ czero_nez 0000111 ..... ..... 111 ..... 0110011 @r | ||
| 33 | # *** Zfbfmin Standard Extension *** | ||
| 34 | fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm | ||
| 35 | fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm | ||
| 36 | + | ||
| 37 | +# *** Zvfbfmin Standard Extension *** | ||
| 38 | +vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm | ||
| 39 | +vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm | ||
| 40 | diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/riscv/vector_helper.c | ||
| 43 | +++ b/target/riscv/vector_helper.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) | ||
| 45 | GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4) | ||
| 46 | GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8) | ||
| 47 | |||
| 48 | +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v, WOP_UU_H, H4, H2, bfloat16_to_float32) | ||
| 49 | +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4) | ||
| 50 | + | ||
| 51 | /* Narrowing Floating-Point/Integer Type-Convert Instructions */ | ||
| 52 | /* (TD, T2, TX2) */ | ||
| 53 | #define NOP_UU_B uint8_t, uint16_t, uint32_t | ||
| 54 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) | ||
| 55 | GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2) | ||
| 56 | GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) | ||
| 57 | |||
| 58 | +RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16) | ||
| 59 | +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2) | ||
| 60 | + | ||
| 61 | /* | ||
| 62 | * Vector Reduction Operations | ||
| 63 | */ | ||
| 64 | diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 67 | +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 68 | @@ -XXX,XX +XXX,XX @@ | ||
| 69 | } \ | ||
| 70 | } while (0) | ||
| 71 | |||
| 72 | +#define REQUIRE_ZVFBFMIN(ctx) do { \ | ||
| 73 | + if (!ctx->cfg_ptr->ext_zvfbfmin) { \ | ||
| 74 | + return false; \ | ||
| 75 | + } \ | ||
| 76 | +} while (0) | ||
| 77 | + | ||
| 78 | static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a) | ||
| 79 | { | ||
| 80 | REQUIRE_FPU; | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a) | ||
| 82 | mark_fs_dirty(ctx); | ||
| 83 | return true; | ||
| 84 | } | ||
| 85 | + | ||
| 86 | +static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a) | ||
| 87 | +{ | ||
| 88 | + REQUIRE_FPU; | ||
| 89 | + REQUIRE_ZVFBFMIN(ctx); | ||
| 90 | + | ||
| 91 | + if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) { | ||
| 92 | + uint32_t data = 0; | ||
| 93 | + TCGLabel *over = gen_new_label(); | ||
| 94 | + | ||
| 95 | + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); | ||
| 96 | + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
| 97 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
| 98 | + | ||
| 99 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
| 100 | + data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul); | ||
| 101 | + data = FIELD_DP32(data, VDATA, VTA, ctx->vta); | ||
| 102 | + data = FIELD_DP32(data, VDATA, VMA, ctx->vma); | ||
| 103 | + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), | ||
| 104 | + vreg_ofs(ctx, a->rs2), cpu_env, | ||
| 105 | + ctx->cfg_ptr->vlen / 8, | ||
| 106 | + ctx->cfg_ptr->vlen / 8, data, | ||
| 107 | + gen_helper_vfncvtbf16_f_f_w); | ||
| 108 | + mark_vs_dirty(ctx); | ||
| 109 | + gen_set_label(over); | ||
| 110 | + return true; | ||
| 111 | + } | ||
| 112 | + return false; | ||
| 113 | +} | ||
| 114 | + | ||
| 115 | +static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a) | ||
| 116 | +{ | ||
| 117 | + REQUIRE_FPU; | ||
| 118 | + REQUIRE_ZVFBFMIN(ctx); | ||
| 119 | + | ||
| 120 | + if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) { | ||
| 121 | + uint32_t data = 0; | ||
| 122 | + TCGLabel *over = gen_new_label(); | ||
| 123 | + | ||
| 124 | + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); | ||
| 125 | + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
| 126 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
| 127 | + | ||
| 128 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
| 129 | + data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul); | ||
| 130 | + data = FIELD_DP32(data, VDATA, VTA, ctx->vta); | ||
| 131 | + data = FIELD_DP32(data, VDATA, VMA, ctx->vma); | ||
| 132 | + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), | ||
| 133 | + vreg_ofs(ctx, a->rs2), cpu_env, | ||
| 134 | + ctx->cfg_ptr->vlen / 8, | ||
| 135 | + ctx->cfg_ptr->vlen / 8, data, | ||
| 136 | + gen_helper_vfwcvtbf16_f_f_v); | ||
| 137 | + mark_vs_dirty(ctx); | ||
| 138 | + gen_set_label(over); | ||
| 139 | + return true; | ||
| 140 | + } | ||
| 141 | + return false; | ||
| 142 | +} | ||
| 143 | -- | ||
| 144 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Add trans_* and helper function for Zvfbfwma instructions. | ||
| 4 | |||
| 5 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 6 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-Id: <20230615063302.102409-5-liweiwei@iscas.ac.cn> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/helper.h | 3 ++ | ||
| 12 | target/riscv/insn32.decode | 4 ++ | ||
| 13 | target/riscv/vector_helper.c | 11 ++++ | ||
| 14 | target/riscv/insn_trans/trans_rvbf16.c.inc | 58 ++++++++++++++++++++++ | ||
| 15 | 4 files changed, 76 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/riscv/helper.h | ||
| 20 | +++ b/target/riscv/helper.h | ||
| 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 22 | |||
| 23 | DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32) | ||
| 24 | DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32) | ||
| 25 | + | ||
| 26 | +DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
| 27 | +DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) | ||
| 28 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/riscv/insn32.decode | ||
| 31 | +++ b/target/riscv/insn32.decode | ||
| 32 | @@ -XXX,XX +XXX,XX @@ fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm | ||
| 33 | # *** Zvfbfmin Standard Extension *** | ||
| 34 | vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm | ||
| 35 | vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm | ||
| 36 | + | ||
| 37 | +# *** Zvfbfwma Standard Extension *** | ||
| 38 | +vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm | ||
| 39 | +vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm | ||
| 40 | diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/riscv/vector_helper.c | ||
| 43 | +++ b/target/riscv/vector_helper.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32) | ||
| 45 | GEN_VEXT_VF(vfwmacc_vf_h, 4) | ||
| 46 | GEN_VEXT_VF(vfwmacc_vf_w, 8) | ||
| 47 | |||
| 48 | +static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s) | ||
| 49 | +{ | ||
| 50 | + return float32_muladd(bfloat16_to_float32(a, s), | ||
| 51 | + bfloat16_to_float32(b, s), d, 0, s); | ||
| 52 | +} | ||
| 53 | + | ||
| 54 | +RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16) | ||
| 55 | +GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4) | ||
| 56 | +RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16) | ||
| 57 | +GEN_VEXT_VF(vfwmaccbf16_vf, 4) | ||
| 58 | + | ||
| 59 | static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) | ||
| 60 | { | ||
| 61 | return float32_muladd(float16_to_float32(a, true, s), | ||
| 62 | diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 63 | index XXXXXXX..XXXXXXX 100644 | ||
| 64 | --- a/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 65 | +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc | ||
| 66 | @@ -XXX,XX +XXX,XX @@ | ||
| 67 | } \ | ||
| 68 | } while (0) | ||
| 69 | |||
| 70 | +#define REQUIRE_ZVFBFWMA(ctx) do { \ | ||
| 71 | + if (!ctx->cfg_ptr->ext_zvfbfwma) { \ | ||
| 72 | + return false; \ | ||
| 73 | + } \ | ||
| 74 | +} while (0) | ||
| 75 | + | ||
| 76 | static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a) | ||
| 77 | { | ||
| 78 | REQUIRE_FPU; | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a) | ||
| 80 | } | ||
| 81 | return false; | ||
| 82 | } | ||
| 83 | + | ||
| 84 | +static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a) | ||
| 85 | +{ | ||
| 86 | + REQUIRE_FPU; | ||
| 87 | + REQUIRE_ZVFBFWMA(ctx); | ||
| 88 | + | ||
| 89 | + if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) && | ||
| 90 | + vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) { | ||
| 91 | + uint32_t data = 0; | ||
| 92 | + TCGLabel *over = gen_new_label(); | ||
| 93 | + | ||
| 94 | + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); | ||
| 95 | + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
| 96 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
| 97 | + | ||
| 98 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
| 99 | + data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul); | ||
| 100 | + data = FIELD_DP32(data, VDATA, VTA, ctx->vta); | ||
| 101 | + data = FIELD_DP32(data, VDATA, VMA, ctx->vma); | ||
| 102 | + tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), | ||
| 103 | + vreg_ofs(ctx, a->rs1), | ||
| 104 | + vreg_ofs(ctx, a->rs2), cpu_env, | ||
| 105 | + ctx->cfg_ptr->vlen / 8, | ||
| 106 | + ctx->cfg_ptr->vlen / 8, data, | ||
| 107 | + gen_helper_vfwmaccbf16_vv); | ||
| 108 | + mark_vs_dirty(ctx); | ||
| 109 | + gen_set_label(over); | ||
| 110 | + return true; | ||
| 111 | + } | ||
| 112 | + return false; | ||
| 113 | +} | ||
| 114 | + | ||
| 115 | +static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a) | ||
| 116 | +{ | ||
| 117 | + REQUIRE_FPU; | ||
| 118 | + REQUIRE_ZVFBFWMA(ctx); | ||
| 119 | + | ||
| 120 | + if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) && | ||
| 121 | + vext_check_ds(ctx, a->rd, a->rs2, a->vm)) { | ||
| 122 | + uint32_t data = 0; | ||
| 123 | + | ||
| 124 | + gen_set_rm(ctx, RISCV_FRM_DYN); | ||
| 125 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
| 126 | + data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul); | ||
| 127 | + data = FIELD_DP32(data, VDATA, VTA, ctx->vta); | ||
| 128 | + data = FIELD_DP32(data, VDATA, VMA, ctx->vma); | ||
| 129 | + return opfvf_trans(a->rd, a->rs1, a->rs2, data, | ||
| 130 | + gen_helper_vfwmaccbf16_vf, ctx); | ||
| 131 | + } | ||
| 132 | + | ||
| 133 | + return false; | ||
| 134 | +} | ||
| 135 | -- | ||
| 136 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 4 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 5 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 6 | Message-Id: <20230615063302.102409-6-liweiwei@iscas.ac.cn> | ||
| 7 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | --- | ||
| 9 | target/riscv/cpu.c | 7 +++++++ | ||
| 10 | 1 file changed, 7 insertions(+) | ||
| 11 | |||
| 12 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/riscv/cpu.c | ||
| 15 | +++ b/target/riscv/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
| 17 | ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), | ||
| 18 | ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), | ||
| 19 | ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), | ||
| 20 | + ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), | ||
| 21 | ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), | ||
| 22 | ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), | ||
| 23 | ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
| 25 | ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), | ||
| 26 | ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), | ||
| 27 | ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), | ||
| 28 | + ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), | ||
| 29 | + ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), | ||
| 30 | ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), | ||
| 31 | ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), | ||
| 32 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
| 34 | DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), | ||
| 35 | DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), | ||
| 36 | |||
| 37 | + DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), | ||
| 38 | + DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), | ||
| 39 | + DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), | ||
| 40 | + | ||
| 41 | DEFINE_PROP_END_OF_LIST(), | ||
| 42 | }; | ||
| 43 | |||
| 44 | -- | ||
| 45 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | 1 | From: Jason Chien <jason.chien@sifive.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Like MMU translation, add qemu log of PMP permission checking for | 3 | The privileged spec states: |
| 4 | debugging. | 4 | For a memory access made to support VS-stage address translation (such as |
| 5 | to read/write a VS-level page table), permissions are checked as though | ||
| 6 | for a load or store, not for the original access type. However, any | ||
| 7 | exception is always reported for the original access type (instruction, | ||
| 8 | load, or store/AMO). | ||
| 5 | 9 | ||
| 6 | Signed-off-by: Jim Shu <cwshu@andestech.com> | 10 | The current implementation converts the access type to LOAD if implicit |
| 11 | G-stage translation fails which results in only reporting "Load guest-page | ||
| 12 | fault". This commit removes the convertion of access type, so the reported | ||
| 13 | exception conforms to the spec. | ||
| 14 | |||
| 15 | Signed-off-by: Jason Chien <jason.chien@sifive.com> | ||
| 16 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com | 18 | Message-Id: <20230627074915.7686-1-jason.chien@sifive.com> |
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 19 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 20 | --- |
| 11 | target/riscv/cpu_helper.c | 12 ++++++++++++ | 21 | target/riscv/cpu_helper.c | 1 - |
| 12 | 1 file changed, 12 insertions(+) | 22 | 1 file changed, 1 deletion(-) |
| 13 | 23 | ||
| 14 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 24 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/riscv/cpu_helper.c | 26 | --- a/target/riscv/cpu_helper.c |
| 17 | +++ b/target/riscv/cpu_helper.c | 27 | +++ b/target/riscv/cpu_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | 28 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 19 | if (ret == TRANSLATE_SUCCESS) { | 29 | if (ret == TRANSLATE_G_STAGE_FAIL) { |
| 20 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | 30 | first_stage_error = false; |
| 21 | size, access_type, mode); | 31 | two_stage_indirect_error = true; |
| 22 | + | 32 | - access_type = MMU_DATA_LOAD; |
| 23 | + qemu_log_mask(CPU_LOG_MMU, | ||
| 24 | + "%s PMP address=" TARGET_FMT_plx " ret %d prot" | ||
| 25 | + " %d tlb_size " TARGET_FMT_lu "\n", | ||
| 26 | + __func__, pa, ret, prot_pmp, tlb_size); | ||
| 27 | + | ||
| 28 | prot &= prot_pmp; | ||
| 29 | } | ||
| 30 | |||
| 31 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 32 | if (ret == TRANSLATE_SUCCESS) { | ||
| 33 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | ||
| 34 | size, access_type, mode); | ||
| 35 | + | ||
| 36 | + qemu_log_mask(CPU_LOG_MMU, | ||
| 37 | + "%s PMP address=" TARGET_FMT_plx " ret %d prot" | ||
| 38 | + " %d tlb_size " TARGET_FMT_lu "\n", | ||
| 39 | + __func__, pa, ret, prot_pmp, tlb_size); | ||
| 40 | + | ||
| 41 | prot &= prot_pmp; | ||
| 42 | } | 33 | } |
| 43 | } | 34 | |
| 35 | qemu_log_mask(CPU_LOG_MMU, | ||
| 44 | -- | 36 | -- |
| 45 | 2.30.1 | 37 | 2.40.1 |
| 46 | |||
| 47 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
| 4 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
| 5 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Message-Id: <20230703071759.86775-2-liweiwei@iscas.ac.cn> | ||
| 7 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | --- | ||
| 9 | disas/riscv.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ | ||
| 10 | 1 file changed, 44 insertions(+) | ||
| 11 | |||
| 12 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/disas/riscv.c | ||
| 15 | +++ b/disas/riscv.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 17 | rv_op_cm_jalt = 788, | ||
| 18 | rv_op_czero_eqz = 789, | ||
| 19 | rv_op_czero_nez = 790, | ||
| 20 | + rv_op_fcvt_bf16_s = 791, | ||
| 21 | + rv_op_fcvt_s_bf16 = 792, | ||
| 22 | + rv_op_vfncvtbf16_f_f_w = 793, | ||
| 23 | + rv_op_vfwcvtbf16_f_f_v = 794, | ||
| 24 | + rv_op_vfwmaccbf16_vv = 795, | ||
| 25 | + rv_op_vfwmaccbf16_vf = 796, | ||
| 26 | + rv_op_flh = 797, | ||
| 27 | + rv_op_fsh = 798, | ||
| 28 | + rv_op_fmv_h_x = 799, | ||
| 29 | + rv_op_fmv_x_h = 800, | ||
| 30 | } rv_op; | ||
| 31 | |||
| 32 | /* register names */ | ||
| 33 | @@ -XXX,XX +XXX,XX @@ const rv_opcode_data rvi_opcode_data[] = { | ||
| 34 | { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, | ||
| 35 | { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 36 | { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 37 | + { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 38 | + { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 39 | + { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, | ||
| 40 | + { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, | ||
| 41 | + { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, | ||
| 42 | + { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, | ||
| 43 | + { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, | ||
| 44 | + { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, | ||
| 45 | + { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, | ||
| 46 | + { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* CSR names */ | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 51 | case 3: op = rv_op_vloxei8_v; break; | ||
| 52 | } | ||
| 53 | break; | ||
| 54 | + case 1: op = rv_op_flh; break; | ||
| 55 | case 2: op = rv_op_flw; break; | ||
| 56 | case 3: op = rv_op_fld; break; | ||
| 57 | case 4: op = rv_op_flq; break; | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 59 | case 3: op = rv_op_vsoxei8_v; break; | ||
| 60 | } | ||
| 61 | break; | ||
| 62 | + case 1: op = rv_op_fsh; break; | ||
| 63 | case 2: op = rv_op_fsw; break; | ||
| 64 | case 3: op = rv_op_fsd; break; | ||
| 65 | case 4: op = rv_op_fsq; break; | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 67 | switch ((inst >> 20) & 0b11111) { | ||
| 68 | case 1: op = rv_op_fcvt_s_d; break; | ||
| 69 | case 3: op = rv_op_fcvt_s_q; break; | ||
| 70 | + case 6: op = rv_op_fcvt_s_bf16; break; | ||
| 71 | } | ||
| 72 | break; | ||
| 73 | case 33: | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 75 | case 3: op = rv_op_fcvt_d_q; break; | ||
| 76 | } | ||
| 77 | break; | ||
| 78 | + case 34: | ||
| 79 | + switch (((inst >> 20) & 0b11111)) { | ||
| 80 | + case 8: op = rv_op_fcvt_bf16_s; break; | ||
| 81 | + } | ||
| 82 | + break; | ||
| 83 | case 35: | ||
| 84 | switch ((inst >> 20) & 0b11111) { | ||
| 85 | case 0: op = rv_op_fcvt_q_s; break; | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 87 | case 1: op = rv_op_fclass_d; break; | ||
| 88 | } | ||
| 89 | break; | ||
| 90 | + case 114: | ||
| 91 | + switch (((inst >> 17) & 0b11111000) | | ||
| 92 | + ((inst >> 12) & 0b00000111)) { | ||
| 93 | + case 0: op = rv_op_fmv_x_h; break; | ||
| 94 | + } | ||
| 95 | + break; | ||
| 96 | case 115: | ||
| 97 | switch (((inst >> 17) & 0b11111000) | | ||
| 98 | ((inst >> 12) & 0b00000111)) { | ||
| 99 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 100 | case 0: op = rv_op_fmv_d_x; break; | ||
| 101 | } | ||
| 102 | break; | ||
| 103 | + case 122: | ||
| 104 | + switch (((inst >> 17) & 0b11111000) | | ||
| 105 | + ((inst >> 12) & 0b00000111)) { | ||
| 106 | + case 0: op = rv_op_fmv_h_x; break; | ||
| 107 | + } | ||
| 108 | + break; | ||
| 109 | case 123: | ||
| 110 | switch (((inst >> 17) & 0b11111000) | | ||
| 111 | ((inst >> 12) & 0b00000111)) { | ||
| 112 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 113 | case 10: op = rv_op_vfwcvt_f_xu_v; break; | ||
| 114 | case 11: op = rv_op_vfwcvt_f_x_v; break; | ||
| 115 | case 12: op = rv_op_vfwcvt_f_f_v; break; | ||
| 116 | + case 13: op = rv_op_vfwcvtbf16_f_f_v; break; | ||
| 117 | case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; | ||
| 118 | case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; | ||
| 119 | case 16: op = rv_op_vfncvt_xu_f_w; break; | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 121 | case 21: op = rv_op_vfncvt_rod_f_f_w; break; | ||
| 122 | case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; | ||
| 123 | case 23: op = rv_op_vfncvt_rtz_x_f_w; break; | ||
| 124 | + case 29: op = rv_op_vfncvtbf16_f_f_w; break; | ||
| 125 | } | ||
| 126 | break; | ||
| 127 | case 19: | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 129 | case 52: op = rv_op_vfwadd_wv; break; | ||
| 130 | case 54: op = rv_op_vfwsub_wv; break; | ||
| 131 | case 56: op = rv_op_vfwmul_vv; break; | ||
| 132 | + case 59: op = rv_op_vfwmaccbf16_vv; break; | ||
| 133 | case 60: op = rv_op_vfwmacc_vv; break; | ||
| 134 | case 61: op = rv_op_vfwnmacc_vv; break; | ||
| 135 | case 62: op = rv_op_vfwmsac_vv; break; | ||
| 136 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 137 | case 52: op = rv_op_vfwadd_wf; break; | ||
| 138 | case 54: op = rv_op_vfwsub_wf; break; | ||
| 139 | case 56: op = rv_op_vfwmul_vf; break; | ||
| 140 | + case 59: op = rv_op_vfwmaccbf16_vf; break; | ||
| 141 | case 60: op = rv_op_vfwmacc_vf; break; | ||
| 142 | case 61: op = rv_op_vfwnmacc_vf; break; | ||
| 143 | case 62: op = rv_op_vfwmsac_vf; break; | ||
| 144 | -- | ||
| 145 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: "yang.zhang" <yang.zhang@hexintek.com> | ||
| 1 | 2 | ||
| 3 | Should set/get riscv all reg timer,i.e, time/compare/frequency/state. | ||
| 4 | |||
| 5 | Signed-off-by: Yang Zhang <yang.zhang@hexintek.com> | ||
| 6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 9 | Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | target/riscv/kvm.c | 2 +- | ||
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/riscv/kvm.c | ||
| 18 | +++ b/target/riscv/kvm.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, | ||
| 20 | |||
| 21 | #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ | ||
| 22 | do { \ | ||
| 23 | - int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \ | ||
| 24 | + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ | ||
| 25 | if (ret) { \ | ||
| 26 | abort(); \ | ||
| 27 | } \ | ||
| 28 | -- | ||
| 29 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Lakshmi Bai Raja Subramanian <lakshmi.bai.rajasubramanian@bodhicomputing.com> | ||
| 1 | 2 | ||
| 3 | fdt_load_addr was previously declared as uint32_t which doe not match | ||
| 4 | with the return type of riscv_compute_fdt_addr(). | ||
| 5 | |||
| 6 | This patch modifies the fdt_load_addr type from a uint32_t to a uint64_t | ||
| 7 | to match the riscv_compute_fdt_addr() return type. | ||
| 8 | |||
| 9 | This fixes calculating the fdt address when DRAM is mapped to higher | ||
| 10 | 64-bit address. | ||
| 11 | |||
| 12 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 13 | Signed-off-by: Lakshmi Bai Raja Subramanian <lakshmi.bai.rajasubramanian@bodhicomputing.com> | ||
| 14 | [ Change by AF: | ||
| 15 | - Cleanup commit title and message | ||
| 16 | ] | ||
| 17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 18 | Message-Id: <168872495192.6334.3845988291412774261-1@git.sr.ht> | ||
| 19 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 20 | --- | ||
| 21 | hw/riscv/virt.c | 2 +- | ||
| 22 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 23 | |||
| 24 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/hw/riscv/virt.c | ||
| 27 | +++ b/hw/riscv/virt.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
| 29 | target_ulong start_addr = memmap[VIRT_DRAM].base; | ||
| 30 | target_ulong firmware_end_addr, kernel_start_addr; | ||
| 31 | const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); | ||
| 32 | - uint32_t fdt_load_addr; | ||
| 33 | + uint64_t fdt_load_addr; | ||
| 34 | uint64_t kernel_entry = 0; | ||
| 35 | BlockBackend *pflash_blk0; | ||
| 36 | |||
| 37 | -- | ||
| 38 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | As it is today it's not possible to use '-cpu host' if the RISC-V host | ||
| 4 | has RVH enabled. This is the resulting error: | ||
| 5 | |||
| 6 | $ ./qemu/build/qemu-system-riscv64 \ | ||
| 7 | -machine virt,accel=kvm -m 2G -smp 1 \ | ||
| 8 | -nographic -snapshot -kernel ./guest_imgs/Image \ | ||
| 9 | -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ | ||
| 10 | -append "earlycon=sbi root=/dev/ram rw" \ | ||
| 11 | -cpu host | ||
| 12 | qemu-system-riscv64: H extension requires priv spec 1.12.0 | ||
| 13 | |||
| 14 | This happens because we're checking for priv spec for all CPUs, and | ||
| 15 | since we're not setting env->priv_ver for the 'host' CPU, it's being | ||
| 16 | default to zero (i.e. PRIV_SPEC_1_10_0). | ||
| 17 | |||
| 18 | In reality env->priv_ver does not make sense when running with the KVM | ||
| 19 | 'host' CPU. It's used to gate certain CSRs/extensions during translation | ||
| 20 | to make them unavailable if the hart declares an older spec version. It | ||
| 21 | doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec | ||
| 22 | checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs | ||
| 23 | are available [1]. | ||
| 24 | |||
| 25 | 'priv_ver' is just one example. We're doing a lot of feature validation | ||
| 26 | and setup during riscv_cpu_realize() that it doesn't apply to KVM CPUs. | ||
| 27 | Validating the feature set for those CPUs is a KVM problem that should | ||
| 28 | be handled in KVM specific code. | ||
| 29 | |||
| 30 | The new riscv_cpu_realize_tcg() helper contains all validation logic that | ||
| 31 | are applicable to TCG CPUs only. riscv_cpu_realize() verifies if we're | ||
| 32 | running TCG and, if it's the case, proceed with the usual TCG realize() | ||
| 33 | logic. | ||
| 34 | |||
| 35 | [1] lib/sbi/sbi_hart.c, hart_detect_features() | ||
| 36 | |||
| 37 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 38 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 39 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 40 | Message-Id: <20230706101738.460804-2-dbarboza@ventanamicro.com> | ||
| 41 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 42 | --- | ||
| 43 | target/riscv/cpu.c | 35 +++++++++++++++++++++++++---------- | ||
| 44 | 1 file changed, 25 insertions(+), 10 deletions(-) | ||
| 45 | |||
| 46 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/target/riscv/cpu.c | ||
| 49 | +++ b/target/riscv/cpu.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | ||
| 51 | #include "migration/vmstate.h" | ||
| 52 | #include "fpu/softfloat-helpers.h" | ||
| 53 | #include "sysemu/kvm.h" | ||
| 54 | +#include "sysemu/tcg.h" | ||
| 55 | #include "kvm_riscv.h" | ||
| 56 | #include "tcg/tcg.h" | ||
| 57 | |||
| 58 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) | ||
| 59 | } | ||
| 60 | } | ||
| 61 | |||
| 62 | -static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
| 63 | +static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) | ||
| 64 | { | ||
| 65 | - CPUState *cs = CPU(dev); | ||
| 66 | RISCVCPU *cpu = RISCV_CPU(dev); | ||
| 67 | CPURISCVState *env = &cpu->env; | ||
| 68 | - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); | ||
| 69 | Error *local_err = NULL; | ||
| 70 | |||
| 71 | - cpu_exec_realizefn(cs, &local_err); | ||
| 72 | - if (local_err != NULL) { | ||
| 73 | - error_propagate(errp, local_err); | ||
| 74 | - return; | ||
| 75 | - } | ||
| 76 | - | ||
| 77 | riscv_cpu_validate_misa_mxl(cpu, &local_err); | ||
| 78 | if (local_err != NULL) { | ||
| 79 | error_propagate(errp, local_err); | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
| 81 | } | ||
| 82 | |||
| 83 | #ifndef CONFIG_USER_ONLY | ||
| 84 | - cs->tcg_cflags |= CF_PCREL; | ||
| 85 | + CPU(dev)->tcg_cflags |= CF_PCREL; | ||
| 86 | |||
| 87 | if (cpu->cfg.ext_sstc) { | ||
| 88 | riscv_timer_init(cpu); | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
| 90 | } | ||
| 91 | } | ||
| 92 | #endif | ||
| 93 | +} | ||
| 94 | + | ||
| 95 | +static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
| 96 | +{ | ||
| 97 | + CPUState *cs = CPU(dev); | ||
| 98 | + RISCVCPU *cpu = RISCV_CPU(dev); | ||
| 99 | + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); | ||
| 100 | + Error *local_err = NULL; | ||
| 101 | + | ||
| 102 | + cpu_exec_realizefn(cs, &local_err); | ||
| 103 | + if (local_err != NULL) { | ||
| 104 | + error_propagate(errp, local_err); | ||
| 105 | + return; | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + if (tcg_enabled()) { | ||
| 109 | + riscv_cpu_realize_tcg(dev, &local_err); | ||
| 110 | + if (local_err != NULL) { | ||
| 111 | + error_propagate(errp, local_err); | ||
| 112 | + return; | ||
| 113 | + } | ||
| 114 | + } | ||
| 115 | |||
| 116 | riscv_cpu_finalize_features(cpu, &local_err); | ||
| 117 | if (local_err != NULL) { | ||
| 118 | -- | ||
| 119 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Asherah Connor <ashe@kivikakk.ee> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Allow ramfb on virt. This lets `-device ramfb' work. | 3 | The absence of a satp mode in riscv_host_cpu_init() is causing the |
| 4 | following error: | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Asherah Connor <ashe@kivikakk.ee> | 6 | $ ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \ |
| 6 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | 7 | -m 2G -smp 1 -nographic -snapshot \ |
| 8 | -kernel ./guest_imgs/Image \ | ||
| 9 | -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ | ||
| 10 | -append "earlycon=sbi root=/dev/ram rw" \ | ||
| 11 | -cpu host | ||
| 12 | ** | ||
| 13 | ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be | ||
| 14 | reached | ||
| 15 | Bail out! ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should | ||
| 16 | not be reached | ||
| 17 | Aborted | ||
| 18 | |||
| 19 | The error is triggered from create_fdt_socket_cpus() in hw/riscv/virt.c. | ||
| 20 | It's trying to get satp_mode_str for a NULL cpu->cfg.satp_mode.map. | ||
| 21 | |||
| 22 | For this KVM cpu we would need to inherit the satp supported modes | ||
| 23 | from the RISC-V host. At this moment this is not possible because the | ||
| 24 | KVM driver does not support it. And even when it does we can't just let | ||
| 25 | this broken for every other older kernel. | ||
| 26 | |||
| 27 | Since mmu-type is not a required node, according to [1], skip the | ||
| 28 | 'mmu-type' FDT node if there's no satp_mode set. We'll revisit this | ||
| 29 | logic when we can get satp information from KVM. | ||
| 30 | |||
| 31 | [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml | ||
| 32 | |||
| 33 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 34 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 35 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Message-id: 20210318235041.17175-3-ashe@kivikakk.ee | 36 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 37 | Message-Id: <20230706101738.460804-3-dbarboza@ventanamicro.com> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 38 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 39 | --- |
| 11 | hw/riscv/virt.c | 3 +++ | 40 | hw/riscv/virt.c | 14 +++++++------- |
| 12 | 1 file changed, 3 insertions(+) | 41 | 1 file changed, 7 insertions(+), 7 deletions(-) |
| 13 | 42 | ||
| 14 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | 43 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/riscv/virt.c | 45 | --- a/hw/riscv/virt.c |
| 17 | +++ b/hw/riscv/virt.c | 46 | +++ b/hw/riscv/virt.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, |
| 19 | #include "sysemu/sysemu.h" | 48 | s->soc[socket].hartid_base + cpu); |
| 20 | #include "hw/pci/pci.h" | 49 | qemu_fdt_add_subnode(ms->fdt, cpu_name); |
| 21 | #include "hw/pci-host/gpex.h" | 50 | |
| 22 | +#include "hw/display/ramfb.h" | 51 | - satp_mode_max = satp_mode_max_from_map( |
| 23 | 52 | - s->soc[socket].harts[cpu].cfg.satp_mode.map); | |
| 24 | static const MemMapEntry virt_memmap[] = { | 53 | - sv_name = g_strdup_printf("riscv,%s", |
| 25 | [VIRT_DEBUG] = { 0x0, 0x100 }, | 54 | - satp_mode_str(satp_mode_max, is_32_bit)); |
| 26 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 55 | - qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); |
| 27 | mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | 56 | - g_free(sv_name); |
| 28 | mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | 57 | - |
| 29 | mc->numa_mem_supported = true; | 58 | + if (cpu_ptr->cfg.satp_mode.supported != 0) { |
| 30 | + | 59 | + satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); |
| 31 | + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); | 60 | + sv_name = g_strdup_printf("riscv,%s", |
| 32 | } | 61 | + satp_mode_str(satp_mode_max, is_32_bit)); |
| 33 | 62 | + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); | |
| 34 | static const TypeInfo virt_machine_typeinfo = { | 63 | + g_free(sv_name); |
| 64 | + } | ||
| 65 | |||
| 66 | name = riscv_isa_string(cpu_ptr); | ||
| 67 | qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); | ||
| 35 | -- | 68 | -- |
| 36 | 2.30.1 | 69 | 2.40.1 |
| 37 | 70 | ||
| 38 | 71 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | We're going to change the handling of mvendorid/marchid/mimpid by the | ||
| 4 | KVM driver. Since these are always present in all CPUs let's put the | ||
| 5 | same validation for everyone. | ||
| 6 | |||
| 7 | It doesn't make sense to allow 'mvendorid' to be different than it | ||
| 8 | is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have | ||
| 9 | any 'mvendorid' they want. | ||
| 10 | |||
| 11 | Change 'mvendorid' to be a class property created via | ||
| 12 | 'object_class_property_add', instead of using the DEFINE_PROP_UINT32() | ||
| 13 | macro. This allow us to define a custom setter for it that will verify, | ||
| 14 | for named CPUs, if mvendorid is different than it is already set by the | ||
| 15 | CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is | ||
| 16 | set to an invalid value: | ||
| 17 | |||
| 18 | $ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=2 | ||
| 19 | qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=2: | ||
| 20 | Unable to change veyron-v1-riscv-cpu mvendorid (0x61f) | ||
| 21 | |||
| 22 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 23 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 24 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 25 | Message-Id: <20230706101738.460804-4-dbarboza@ventanamicro.com> | ||
| 26 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 27 | --- | ||
| 28 | target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- | ||
| 29 | 1 file changed, 37 insertions(+), 1 deletion(-) | ||
| 30 | |||
| 31 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/target/riscv/cpu.c | ||
| 34 | +++ b/target/riscv/cpu.c | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) | ||
| 36 | static Property riscv_cpu_properties[] = { | ||
| 37 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | ||
| 38 | |||
| 39 | - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), | ||
| 40 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | ||
| 41 | DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | ||
| 42 | |||
| 43 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps riscv_tcg_ops = { | ||
| 44 | #endif /* !CONFIG_USER_ONLY */ | ||
| 45 | }; | ||
| 46 | |||
| 47 | +static bool riscv_cpu_is_dynamic(Object *cpu_obj) | ||
| 48 | +{ | ||
| 49 | + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; | ||
| 50 | +} | ||
| 51 | + | ||
| 52 | +static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, | ||
| 53 | + void *opaque, Error **errp) | ||
| 54 | +{ | ||
| 55 | + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); | ||
| 56 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 57 | + uint32_t prev_val = cpu->cfg.mvendorid; | ||
| 58 | + uint32_t value; | ||
| 59 | + | ||
| 60 | + if (!visit_type_uint32(v, name, &value, errp)) { | ||
| 61 | + return; | ||
| 62 | + } | ||
| 63 | + | ||
| 64 | + if (!dynamic_cpu && prev_val != value) { | ||
| 65 | + error_setg(errp, "Unable to change %s mvendorid (0x%x)", | ||
| 66 | + object_get_typename(obj), prev_val); | ||
| 67 | + return; | ||
| 68 | + } | ||
| 69 | + | ||
| 70 | + cpu->cfg.mvendorid = value; | ||
| 71 | +} | ||
| 72 | + | ||
| 73 | +static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, | ||
| 74 | + void *opaque, Error **errp) | ||
| 75 | +{ | ||
| 76 | + bool value = RISCV_CPU(obj)->cfg.mvendorid; | ||
| 77 | + | ||
| 78 | + visit_type_bool(v, name, &value, errp); | ||
| 79 | +} | ||
| 80 | + | ||
| 81 | static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 82 | { | ||
| 83 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 85 | cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; | ||
| 86 | cc->tcg_ops = &riscv_tcg_ops; | ||
| 87 | |||
| 88 | + object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, | ||
| 89 | + cpu_set_mvendorid, NULL, NULL); | ||
| 90 | + | ||
| 91 | device_class_set_props(dc, riscv_cpu_properties); | ||
| 92 | } | ||
| 93 | |||
| 94 | -- | ||
| 95 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Following the same logic used with 'mvendorid' let's also restrict | ||
| 4 | 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. | ||
| 5 | |||
| 6 | Note that we're getting rid of the default RISCV_CPU_MARCHID value. The | ||
| 7 | reason is that this is not a good default since it's dynamic, changing | ||
| 8 | with with every QEMU version, regardless of whether the actual | ||
| 9 | implementation of the CPU changed from one QEMU version to the other. | ||
| 10 | Named CPU should set it to a meaningful value instead and generic CPUs | ||
| 11 | can set whatever they want. | ||
| 12 | |||
| 13 | This is the error thrown for an invalid 'mimpid' value for the veyron-v1 | ||
| 14 | CPU: | ||
| 15 | |||
| 16 | $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=2 | ||
| 17 | qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=2: | ||
| 18 | Unable to change veyron-v1-riscv-cpu mimpid (0x111) | ||
| 19 | |||
| 20 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 21 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 22 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 23 | Message-Id: <20230706101738.460804-5-dbarboza@ventanamicro.com> | ||
| 24 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 25 | --- | ||
| 26 | target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- | ||
| 27 | 1 file changed, 32 insertions(+), 2 deletions(-) | ||
| 28 | |||
| 29 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/target/riscv/cpu.c | ||
| 32 | +++ b/target/riscv/cpu.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ | ||
| 34 | #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ | ||
| 35 | (QEMU_VERSION_MINOR << 8) | \ | ||
| 36 | (QEMU_VERSION_MICRO)) | ||
| 37 | -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID | ||
| 38 | |||
| 39 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; | ||
| 40 | |||
| 41 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = { | ||
| 42 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | ||
| 43 | |||
| 44 | DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | ||
| 45 | - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), | ||
| 46 | |||
| 47 | #ifndef CONFIG_USER_ONLY | ||
| 48 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | ||
| 49 | @@ -XXX,XX +XXX,XX @@ static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, | ||
| 50 | visit_type_bool(v, name, &value, errp); | ||
| 51 | } | ||
| 52 | |||
| 53 | +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, | ||
| 54 | + void *opaque, Error **errp) | ||
| 55 | +{ | ||
| 56 | + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); | ||
| 57 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 58 | + uint64_t prev_val = cpu->cfg.mimpid; | ||
| 59 | + uint64_t value; | ||
| 60 | + | ||
| 61 | + if (!visit_type_uint64(v, name, &value, errp)) { | ||
| 62 | + return; | ||
| 63 | + } | ||
| 64 | + | ||
| 65 | + if (!dynamic_cpu && prev_val != value) { | ||
| 66 | + error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", | ||
| 67 | + object_get_typename(obj), prev_val); | ||
| 68 | + return; | ||
| 69 | + } | ||
| 70 | + | ||
| 71 | + cpu->cfg.mimpid = value; | ||
| 72 | +} | ||
| 73 | + | ||
| 74 | +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, | ||
| 75 | + void *opaque, Error **errp) | ||
| 76 | +{ | ||
| 77 | + bool value = RISCV_CPU(obj)->cfg.mimpid; | ||
| 78 | + | ||
| 79 | + visit_type_bool(v, name, &value, errp); | ||
| 80 | +} | ||
| 81 | + | ||
| 82 | static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 83 | { | ||
| 84 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | ||
| 85 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 86 | object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, | ||
| 87 | cpu_set_mvendorid, NULL, NULL); | ||
| 88 | |||
| 89 | + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, | ||
| 90 | + cpu_set_mimpid, NULL, NULL); | ||
| 91 | + | ||
| 92 | device_class_set_props(dc, riscv_cpu_properties); | ||
| 93 | } | ||
| 94 | |||
| 95 | -- | ||
| 96 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | 'marchid' shouldn't be set to a different value as previously set for | ||
| 4 | named CPUs. | ||
| 5 | |||
| 6 | For all other CPUs it shouldn't be freely set either - the spec requires | ||
| 7 | that 'marchid' can't have the MSB (most significant bit) set and every | ||
| 8 | other bit set to zero, i.e. 0x80000000 is an invalid 'marchid' value for | ||
| 9 | 32 bit CPUs. | ||
| 10 | |||
| 11 | As with 'mimpid', setting a default value based on the current QEMU | ||
| 12 | version is not a good idea because it implies that the CPU | ||
| 13 | implementation changes from one QEMU version to the other. Named CPUs | ||
| 14 | should set 'marchid' to a meaningful value instead, and generic CPUs can | ||
| 15 | set to any valid value. | ||
| 16 | |||
| 17 | For the 'veyron-v1' CPU this is the error thrown if 'marchid' is set to | ||
| 18 | a different val: | ||
| 19 | |||
| 20 | $ ./build/qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,marchid=0x80000000 | ||
| 21 | qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.marchid=0x80000000: | ||
| 22 | Unable to change veyron-v1-riscv-cpu marchid (0x8000000000010000) | ||
| 23 | |||
| 24 | And, for generics CPUs, this is the error when trying to set to an | ||
| 25 | invalid val: | ||
| 26 | |||
| 27 | $ ./build/qemu-system-riscv64 -M virt -nographic -cpu rv64,marchid=0x8000000000000000 | ||
| 28 | qemu-system-riscv64: can't apply global rv64-riscv-cpu.marchid=0x8000000000000000: | ||
| 29 | Unable to set marchid with MSB (64) bit set and the remaining bits zero | ||
| 30 | |||
| 31 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 32 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 33 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 34 | Message-Id: <20230706101738.460804-6-dbarboza@ventanamicro.com> | ||
| 35 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 36 | --- | ||
| 37 | target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++------ | ||
| 38 | 1 file changed, 53 insertions(+), 7 deletions(-) | ||
| 39 | |||
| 40 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/riscv/cpu.c | ||
| 43 | +++ b/target/riscv/cpu.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ | ||
| 45 | #include "tcg/tcg.h" | ||
| 46 | |||
| 47 | /* RISC-V CPU definitions */ | ||
| 48 | - | ||
| 49 | -#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ | ||
| 50 | - (QEMU_VERSION_MINOR << 8) | \ | ||
| 51 | - (QEMU_VERSION_MICRO)) | ||
| 52 | - | ||
| 53 | static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; | ||
| 54 | |||
| 55 | struct isa_ext_data { | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) | ||
| 57 | static Property riscv_cpu_properties[] = { | ||
| 58 | DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), | ||
| 59 | |||
| 60 | - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), | ||
| 61 | - | ||
| 62 | #ifndef CONFIG_USER_ONLY | ||
| 63 | DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), | ||
| 64 | #endif | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, | ||
| 66 | visit_type_bool(v, name, &value, errp); | ||
| 67 | } | ||
| 68 | |||
| 69 | +static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, | ||
| 70 | + void *opaque, Error **errp) | ||
| 71 | +{ | ||
| 72 | + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); | ||
| 73 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 74 | + uint64_t prev_val = cpu->cfg.marchid; | ||
| 75 | + uint64_t value, invalid_val; | ||
| 76 | + uint32_t mxlen = 0; | ||
| 77 | + | ||
| 78 | + if (!visit_type_uint64(v, name, &value, errp)) { | ||
| 79 | + return; | ||
| 80 | + } | ||
| 81 | + | ||
| 82 | + if (!dynamic_cpu && prev_val != value) { | ||
| 83 | + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", | ||
| 84 | + object_get_typename(obj), prev_val); | ||
| 85 | + return; | ||
| 86 | + } | ||
| 87 | + | ||
| 88 | + switch (riscv_cpu_mxl(&cpu->env)) { | ||
| 89 | + case MXL_RV32: | ||
| 90 | + mxlen = 32; | ||
| 91 | + break; | ||
| 92 | + case MXL_RV64: | ||
| 93 | + case MXL_RV128: | ||
| 94 | + mxlen = 64; | ||
| 95 | + break; | ||
| 96 | + default: | ||
| 97 | + g_assert_not_reached(); | ||
| 98 | + } | ||
| 99 | + | ||
| 100 | + invalid_val = 1LL << (mxlen - 1); | ||
| 101 | + | ||
| 102 | + if (value == invalid_val) { | ||
| 103 | + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " | ||
| 104 | + "and the remaining bits zero", mxlen); | ||
| 105 | + return; | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + cpu->cfg.marchid = value; | ||
| 109 | +} | ||
| 110 | + | ||
| 111 | +static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, | ||
| 112 | + void *opaque, Error **errp) | ||
| 113 | +{ | ||
| 114 | + bool value = RISCV_CPU(obj)->cfg.marchid; | ||
| 115 | + | ||
| 116 | + visit_type_bool(v, name, &value, errp); | ||
| 117 | +} | ||
| 118 | + | ||
| 119 | static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 120 | { | ||
| 121 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 123 | object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, | ||
| 124 | cpu_set_mimpid, NULL, NULL); | ||
| 125 | |||
| 126 | + object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, | ||
| 127 | + cpu_set_marchid, NULL, NULL); | ||
| 128 | + | ||
| 129 | device_class_set_props(dc, riscv_cpu_properties); | ||
| 130 | } | ||
| 131 | |||
| 132 | -- | ||
| 133 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Certain validations, such as the validations done for the machine IDs | ||
| 4 | (mvendorid/marchid/mimpid), are done before starting the CPU. | ||
| 5 | Non-dynamic (named) CPUs tries to match user input with a preset | ||
| 6 | default. As it is today we can't prefetch a KVM default for these cases | ||
| 7 | because we're only able to read/write KVM regs after the vcpu is | ||
| 8 | spinning. | ||
| 9 | |||
| 10 | Our target/arm friends use a concept called "scratch CPU", which | ||
| 11 | consists of creating a vcpu for doing queries and validations and so on, | ||
| 12 | which is discarded shortly after use [1]. This is a suitable solution | ||
| 13 | for what we need so let's implement it in target/riscv as well. | ||
| 14 | |||
| 15 | kvm_riscv_init_machine_ids() will be used to do any pre-launch setup for | ||
| 16 | KVM CPUs, via riscv_cpu_add_user_properties(). The function will create | ||
| 17 | a KVM scratch CPU, fetch KVM regs that work as default values for user | ||
| 18 | properties, and then discard the scratch CPU afterwards. | ||
| 19 | |||
| 20 | We're starting by initializing 'mvendorid'. This concept will be used to | ||
| 21 | init other KVM specific properties in the next patches as well. | ||
| 22 | |||
| 23 | [1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu() | ||
| 24 | |||
| 25 | Suggested-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 26 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 27 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 28 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 29 | Message-Id: <20230706101738.460804-7-dbarboza@ventanamicro.com> | ||
| 30 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 31 | --- | ||
| 32 | target/riscv/kvm_riscv.h | 1 + | ||
| 33 | target/riscv/cpu.c | 6 +++ | ||
| 34 | target/riscv/kvm.c | 85 ++++++++++++++++++++++++++++++++++++++++ | ||
| 35 | 3 files changed, 92 insertions(+) | ||
| 36 | |||
| 37 | diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/target/riscv/kvm_riscv.h | ||
| 40 | +++ b/target/riscv/kvm_riscv.h | ||
| 41 | @@ -XXX,XX +XXX,XX @@ | ||
| 42 | #ifndef QEMU_KVM_RISCV_H | ||
| 43 | #define QEMU_KVM_RISCV_H | ||
| 44 | |||
| 45 | +void kvm_riscv_init_user_properties(Object *cpu_obj); | ||
| 46 | void kvm_riscv_reset_vcpu(RISCVCPU *cpu); | ||
| 47 | void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); | ||
| 48 | |||
| 49 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/target/riscv/cpu.c | ||
| 52 | +++ b/target/riscv/cpu.c | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) | ||
| 54 | Property *prop; | ||
| 55 | DeviceState *dev = DEVICE(obj); | ||
| 56 | |||
| 57 | +#ifndef CONFIG_USER_ONLY | ||
| 58 | + if (kvm_enabled()) { | ||
| 59 | + kvm_riscv_init_user_properties(obj); | ||
| 60 | + } | ||
| 61 | +#endif | ||
| 62 | + | ||
| 63 | riscv_cpu_add_misa_properties(obj); | ||
| 64 | |||
| 65 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { | ||
| 66 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 67 | index XXXXXXX..XXXXXXX 100644 | ||
| 68 | --- a/target/riscv/kvm.c | ||
| 69 | +++ b/target/riscv/kvm.c | ||
| 70 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_put_regs_timer(CPUState *cs) | ||
| 71 | env->kvm_timer_dirty = false; | ||
| 72 | } | ||
| 73 | |||
| 74 | +typedef struct KVMScratchCPU { | ||
| 75 | + int kvmfd; | ||
| 76 | + int vmfd; | ||
| 77 | + int cpufd; | ||
| 78 | +} KVMScratchCPU; | ||
| 79 | + | ||
| 80 | +/* | ||
| 81 | + * Heavily inspired by kvm_arm_create_scratch_host_vcpu() | ||
| 82 | + * from target/arm/kvm.c. | ||
| 83 | + */ | ||
| 84 | +static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) | ||
| 85 | +{ | ||
| 86 | + int kvmfd = -1, vmfd = -1, cpufd = -1; | ||
| 87 | + | ||
| 88 | + kvmfd = qemu_open_old("/dev/kvm", O_RDWR); | ||
| 89 | + if (kvmfd < 0) { | ||
| 90 | + goto err; | ||
| 91 | + } | ||
| 92 | + do { | ||
| 93 | + vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); | ||
| 94 | + } while (vmfd == -1 && errno == EINTR); | ||
| 95 | + if (vmfd < 0) { | ||
| 96 | + goto err; | ||
| 97 | + } | ||
| 98 | + cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); | ||
| 99 | + if (cpufd < 0) { | ||
| 100 | + goto err; | ||
| 101 | + } | ||
| 102 | + | ||
| 103 | + scratch->kvmfd = kvmfd; | ||
| 104 | + scratch->vmfd = vmfd; | ||
| 105 | + scratch->cpufd = cpufd; | ||
| 106 | + | ||
| 107 | + return true; | ||
| 108 | + | ||
| 109 | + err: | ||
| 110 | + if (cpufd >= 0) { | ||
| 111 | + close(cpufd); | ||
| 112 | + } | ||
| 113 | + if (vmfd >= 0) { | ||
| 114 | + close(vmfd); | ||
| 115 | + } | ||
| 116 | + if (kvmfd >= 0) { | ||
| 117 | + close(kvmfd); | ||
| 118 | + } | ||
| 119 | + | ||
| 120 | + return false; | ||
| 121 | +} | ||
| 122 | + | ||
| 123 | +static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) | ||
| 124 | +{ | ||
| 125 | + close(scratch->cpufd); | ||
| 126 | + close(scratch->vmfd); | ||
| 127 | + close(scratch->kvmfd); | ||
| 128 | +} | ||
| 129 | + | ||
| 130 | +static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 131 | +{ | ||
| 132 | + CPURISCVState *env = &cpu->env; | ||
| 133 | + struct kvm_one_reg reg; | ||
| 134 | + int ret; | ||
| 135 | + | ||
| 136 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 137 | + KVM_REG_RISCV_CONFIG_REG(mvendorid)); | ||
| 138 | + reg.addr = (uint64_t)&cpu->cfg.mvendorid; | ||
| 139 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 140 | + if (ret != 0) { | ||
| 141 | + error_report("Unable to retrieve mvendorid from host, error %d", ret); | ||
| 142 | + } | ||
| 143 | +} | ||
| 144 | + | ||
| 145 | +void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 146 | +{ | ||
| 147 | + RISCVCPU *cpu = RISCV_CPU(cpu_obj); | ||
| 148 | + KVMScratchCPU kvmcpu; | ||
| 149 | + | ||
| 150 | + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { | ||
| 151 | + return; | ||
| 152 | + } | ||
| 153 | + | ||
| 154 | + kvm_riscv_init_machine_ids(cpu, &kvmcpu); | ||
| 155 | + | ||
| 156 | + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); | ||
| 157 | +} | ||
| 158 | + | ||
| 159 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | ||
| 160 | KVM_CAP_LAST_INFO | ||
| 161 | }; | ||
| 162 | -- | ||
| 163 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Allow 'marchid' and 'mimpid' to also be initialized in | ||
| 4 | kvm_riscv_init_machine_ids(). | ||
| 5 | |||
| 6 | After this change, the handling of mvendorid/marchid/mimpid for the | ||
| 7 | 'host' CPU type will be equal to what we already have for TCG named | ||
| 8 | CPUs, i.e. the user is not able to set these values to a different val | ||
| 9 | than the one that is already preset. | ||
| 10 | |||
| 11 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 12 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 13 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 14 | Message-Id: <20230706101738.460804-8-dbarboza@ventanamicro.com> | ||
| 15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | --- | ||
| 17 | target/riscv/kvm.c | 16 ++++++++++++++++ | ||
| 18 | 1 file changed, 16 insertions(+) | ||
| 19 | |||
| 20 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/riscv/kvm.c | ||
| 23 | +++ b/target/riscv/kvm.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 25 | if (ret != 0) { | ||
| 26 | error_report("Unable to retrieve mvendorid from host, error %d", ret); | ||
| 27 | } | ||
| 28 | + | ||
| 29 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 30 | + KVM_REG_RISCV_CONFIG_REG(marchid)); | ||
| 31 | + reg.addr = (uint64_t)&cpu->cfg.marchid; | ||
| 32 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 33 | + if (ret != 0) { | ||
| 34 | + error_report("Unable to retrieve marchid from host, error %d", ret); | ||
| 35 | + } | ||
| 36 | + | ||
| 37 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 38 | + KVM_REG_RISCV_CONFIG_REG(mimpid)); | ||
| 39 | + reg.addr = (uint64_t)&cpu->cfg.mimpid; | ||
| 40 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 41 | + if (ret != 0) { | ||
| 42 | + error_report("Unable to retrieve mimpid from host, error %d", ret); | ||
| 43 | + } | ||
| 44 | } | ||
| 45 | |||
| 46 | void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 47 | -- | ||
| 48 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Currently, PMP permission checking of TLB page is bypassed if TLB hits | 3 | After changing user validation for mvendorid/marchid/mimpid to guarantee |
| 4 | Fix it by propagating PMP permission to TLB page permission. | 4 | that the value is validated on user input time, coupled with the work in |
| 5 | fetching KVM default values for them by using a scratch CPU, we're | ||
| 6 | certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are | ||
| 7 | already good to be written back to KVM. | ||
| 5 | 8 | ||
| 6 | PMP permission checking also use MMU-style API to change TLB permission | 9 | There's no need to write the values back for 'host' type CPUs since the |
| 7 | and size. | 10 | values can't be changed, so let's do that just for generic CPUs. |
| 8 | 11 | ||
| 9 | Signed-off-by: Jim Shu <cwshu@andestech.com> | 12 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 13 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> |
| 11 | Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com | 14 | Acked-by: Alistair Francis <alistair.francis@wdc.com> |
| 15 | Message-Id: <20230706101738.460804-9-dbarboza@ventanamicro.com> | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | --- | 17 | --- |
| 14 | target/riscv/pmp.h | 4 +- | 18 | target/riscv/kvm.c | 31 +++++++++++++++++++++++++++++++ |
| 15 | target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++---------- | 19 | 1 file changed, 31 insertions(+) |
| 16 | target/riscv/pmp.c | 80 +++++++++++++++++++++++++++---------- | ||
| 17 | 3 files changed, 125 insertions(+), 43 deletions(-) | ||
| 18 | 20 | ||
| 19 | diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h | 21 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/riscv/pmp.h | 23 | --- a/target/riscv/kvm.c |
| 22 | +++ b/target/riscv/pmp.h | 24 | +++ b/target/riscv/kvm.c |
| 23 | @@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, | 25 | @@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s) |
| 24 | target_ulong val); | 26 | { |
| 25 | target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); | ||
| 26 | bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 27 | - target_ulong size, pmp_priv_t priv, target_ulong mode); | ||
| 28 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | ||
| 29 | + target_ulong mode); | ||
| 30 | bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 31 | target_ulong *tlb_size); | ||
| 32 | void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); | ||
| 33 | void pmp_update_rule_nums(CPURISCVState *env); | ||
| 34 | uint32_t pmp_get_num_rules(CPURISCVState *env); | ||
| 35 | +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); | ||
| 36 | |||
| 37 | #endif | ||
| 38 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/target/riscv/cpu_helper.c | ||
| 41 | +++ b/target/riscv/cpu_helper.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) | ||
| 43 | env->load_res = -1; | ||
| 44 | } | 27 | } |
| 45 | 28 | ||
| 46 | +/* | 29 | +static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) |
| 47 | + * get_physical_address_pmp - check PMP permission for this physical address | ||
| 48 | + * | ||
| 49 | + * Match the PMP region and check permission for this physical address and it's | ||
| 50 | + * TLB page. Returns 0 if the permission checking was successful | ||
| 51 | + * | ||
| 52 | + * @env: CPURISCVState | ||
| 53 | + * @prot: The returned protection attributes | ||
| 54 | + * @tlb_size: TLB page size containing addr. It could be modified after PMP | ||
| 55 | + * permission checking. NULL if not set TLB page for addr. | ||
| 56 | + * @addr: The physical address to be checked permission | ||
| 57 | + * @access_type: The type of MMU access | ||
| 58 | + * @mode: Indicates current privilege level. | ||
| 59 | + */ | ||
| 60 | +static int get_physical_address_pmp(CPURISCVState *env, int *prot, | ||
| 61 | + target_ulong *tlb_size, hwaddr addr, | ||
| 62 | + int size, MMUAccessType access_type, | ||
| 63 | + int mode) | ||
| 64 | +{ | 30 | +{ |
| 65 | + pmp_priv_t pmp_priv; | 31 | + CPURISCVState *env = &cpu->env; |
| 66 | + target_ulong tlb_size_pmp = 0; | 32 | + uint64_t id; |
| 33 | + int ret; | ||
| 67 | + | 34 | + |
| 68 | + if (!riscv_feature(env, RISCV_FEATURE_PMP)) { | 35 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, |
| 69 | + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | 36 | + KVM_REG_RISCV_CONFIG_REG(mvendorid)); |
| 70 | + return TRANSLATE_SUCCESS; | 37 | + ret = kvm_set_one_reg(cs, id, &cpu->cfg.mvendorid); |
| 38 | + if (ret != 0) { | ||
| 39 | + return ret; | ||
| 71 | + } | 40 | + } |
| 72 | + | 41 | + |
| 73 | + if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, | 42 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, |
| 74 | + mode)) { | 43 | + KVM_REG_RISCV_CONFIG_REG(marchid)); |
| 75 | + *prot = 0; | 44 | + ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); |
| 76 | + return TRANSLATE_PMP_FAIL; | 45 | + if (ret != 0) { |
| 46 | + return ret; | ||
| 77 | + } | 47 | + } |
| 78 | + | 48 | + |
| 79 | + *prot = pmp_priv_to_page_prot(pmp_priv); | 49 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, |
| 80 | + if (tlb_size != NULL) { | 50 | + KVM_REG_RISCV_CONFIG_REG(mimpid)); |
| 81 | + if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { | 51 | + ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); |
| 82 | + *tlb_size = tlb_size_pmp; | ||
| 83 | + } | ||
| 84 | + } | ||
| 85 | + | ||
| 86 | + return TRANSLATE_SUCCESS; | ||
| 87 | +} | ||
| 88 | + | ||
| 89 | /* get_physical_address - get the physical address for this virtual address | ||
| 90 | * | ||
| 91 | * Do a page table walk to obtain the physical address corresponding to a | ||
| 92 | @@ -XXX,XX +XXX,XX @@ restart: | ||
| 93 | pte_addr = base + idx * ptesize; | ||
| 94 | } | ||
| 95 | |||
| 96 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 97 | - !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), | ||
| 98 | - 1 << MMU_DATA_LOAD, PRV_S)) { | ||
| 99 | + int pmp_prot; | ||
| 100 | + int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, | ||
| 101 | + sizeof(target_ulong), | ||
| 102 | + MMU_DATA_LOAD, PRV_S); | ||
| 103 | + if (pmp_ret != TRANSLATE_SUCCESS) { | ||
| 104 | return TRANSLATE_PMP_FAIL; | ||
| 105 | } | ||
| 106 | |||
| 107 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 108 | #ifndef CONFIG_USER_ONLY | ||
| 109 | vaddr im_address; | ||
| 110 | hwaddr pa = 0; | ||
| 111 | - int prot, prot2; | ||
| 112 | + int prot, prot2, prot_pmp; | ||
| 113 | bool pmp_violation = false; | ||
| 114 | bool first_stage_error = true; | ||
| 115 | bool two_stage_lookup = false; | ||
| 116 | int ret = TRANSLATE_FAIL; | ||
| 117 | int mode = mmu_idx; | ||
| 118 | - target_ulong tlb_size = 0; | ||
| 119 | + /* default TLB page size */ | ||
| 120 | + target_ulong tlb_size = TARGET_PAGE_SIZE; | ||
| 121 | |||
| 122 | env->guest_phys_fault_addr = 0; | ||
| 123 | |||
| 124 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 125 | |||
| 126 | prot &= prot2; | ||
| 127 | |||
| 128 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 129 | - (ret == TRANSLATE_SUCCESS) && | ||
| 130 | - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { | ||
| 131 | - ret = TRANSLATE_PMP_FAIL; | ||
| 132 | + if (ret == TRANSLATE_SUCCESS) { | ||
| 133 | + ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | ||
| 134 | + size, access_type, mode); | ||
| 135 | + prot &= prot_pmp; | ||
| 136 | } | ||
| 137 | |||
| 138 | if (ret != TRANSLATE_SUCCESS) { | ||
| 139 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 140 | "%s address=%" VADDR_PRIx " ret %d physical " | ||
| 141 | TARGET_FMT_plx " prot %d\n", | ||
| 142 | __func__, address, ret, pa, prot); | ||
| 143 | - } | ||
| 144 | |||
| 145 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 146 | - (ret == TRANSLATE_SUCCESS) && | ||
| 147 | - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { | ||
| 148 | - ret = TRANSLATE_PMP_FAIL; | ||
| 149 | + if (ret == TRANSLATE_SUCCESS) { | ||
| 150 | + ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | ||
| 151 | + size, access_type, mode); | ||
| 152 | + prot &= prot_pmp; | ||
| 153 | + } | ||
| 154 | } | ||
| 155 | + | ||
| 156 | if (ret == TRANSLATE_PMP_FAIL) { | ||
| 157 | pmp_violation = true; | ||
| 158 | } | ||
| 159 | |||
| 160 | if (ret == TRANSLATE_SUCCESS) { | ||
| 161 | - if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) { | ||
| 162 | - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), | ||
| 163 | - prot, mmu_idx, tlb_size); | ||
| 164 | - } else { | ||
| 165 | - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, | ||
| 166 | - prot, mmu_idx, TARGET_PAGE_SIZE); | ||
| 167 | - } | ||
| 168 | + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), | ||
| 169 | + prot, mmu_idx, tlb_size); | ||
| 170 | return true; | ||
| 171 | } else if (probe) { | ||
| 172 | return false; | ||
| 173 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 174 | index XXXXXXX..XXXXXXX 100644 | ||
| 175 | --- a/target/riscv/pmp.c | ||
| 176 | +++ b/target/riscv/pmp.c | ||
| 177 | @@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
| 178 | return result; | ||
| 179 | } | ||
| 180 | |||
| 181 | +/* | ||
| 182 | + * Check if the address has required RWX privs when no PMP entry is matched. | ||
| 183 | + */ | ||
| 184 | +static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, | ||
| 185 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | ||
| 186 | + target_ulong mode) | ||
| 187 | +{ | ||
| 188 | + bool ret; | ||
| 189 | + | ||
| 190 | + if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) { | ||
| 191 | + /* | ||
| 192 | + * Privileged spec v1.10 states if HW doesn't implement any PMP entry | ||
| 193 | + * or no PMP entry matches an M-Mode access, the access succeeds. | ||
| 194 | + */ | ||
| 195 | + ret = true; | ||
| 196 | + *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 197 | + } else { | ||
| 198 | + /* | ||
| 199 | + * Other modes are not allowed to succeed if they don't * match a rule, | ||
| 200 | + * but there are rules. We've checked for no rule earlier in this | ||
| 201 | + * function. | ||
| 202 | + */ | ||
| 203 | + ret = false; | ||
| 204 | + *allowed_privs = 0; | ||
| 205 | + } | ||
| 206 | + | 52 | + |
| 207 | + return ret; | 53 | + return ret; |
| 208 | +} | 54 | +} |
| 209 | + | 55 | + |
| 210 | 56 | int kvm_arch_init_vcpu(CPUState *cs) | |
| 211 | /* | ||
| 212 | * Public Interface | ||
| 213 | @@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
| 214 | * Check if the address has required RWX privs to complete desired operation | ||
| 215 | */ | ||
| 216 | bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 217 | - target_ulong size, pmp_priv_t privs, target_ulong mode) | ||
| 218 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | ||
| 219 | + target_ulong mode) | ||
| 220 | { | 57 | { |
| 221 | int i = 0; | 58 | int ret = 0; |
| 222 | int ret = -1; | 59 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) |
| 223 | int pmp_size = 0; | ||
| 224 | target_ulong s = 0; | ||
| 225 | target_ulong e = 0; | ||
| 226 | - pmp_priv_t allowed_privs = 0; | ||
| 227 | |||
| 228 | /* Short cut if no rules */ | ||
| 229 | if (0 == pmp_get_num_rules(env)) { | ||
| 230 | - return (env->priv == PRV_M) ? true : false; | ||
| 231 | + return pmp_hart_has_privs_default(env, addr, size, privs, | ||
| 232 | + allowed_privs, mode); | ||
| 233 | } | 60 | } |
| 234 | 61 | env->misa_ext = isa; | |
| 235 | if (size == 0) { | 62 | |
| 236 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | 63 | + if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { |
| 237 | * check | 64 | + ret = kvm_vcpu_set_machine_ids(cpu, cs); |
| 238 | */ | ||
| 239 | if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) { | ||
| 240 | - allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 241 | + *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 242 | if ((mode != PRV_M) || pmp_is_locked(env, i)) { | ||
| 243 | - allowed_privs &= env->pmp_state.pmp[i].cfg_reg; | ||
| 244 | + *allowed_privs &= env->pmp_state.pmp[i].cfg_reg; | ||
| 245 | } | ||
| 246 | |||
| 247 | - if ((privs & allowed_privs) == privs) { | ||
| 248 | - ret = 1; | ||
| 249 | - break; | ||
| 250 | - } else { | ||
| 251 | - ret = 0; | ||
| 252 | - break; | ||
| 253 | - } | ||
| 254 | + ret = ((privs & *allowed_privs) == privs); | ||
| 255 | + break; | ||
| 256 | } | ||
| 257 | } | ||
| 258 | |||
| 259 | /* No rule matched */ | ||
| 260 | if (ret == -1) { | ||
| 261 | - if (mode == PRV_M) { | ||
| 262 | - ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an | ||
| 263 | - * M-Mode access, the access succeeds */ | ||
| 264 | - } else { | ||
| 265 | - ret = 0; /* Other modes are not allowed to succeed if they don't | ||
| 266 | - * match a rule, but there are rules. We've checked for | ||
| 267 | - * no rule earlier in this function. */ | ||
| 268 | - } | ||
| 269 | + return pmp_hart_has_privs_default(env, addr, size, privs, | ||
| 270 | + allowed_privs, mode); | ||
| 271 | } | ||
| 272 | |||
| 273 | return ret == 1 ? true : false; | ||
| 274 | } | ||
| 275 | |||
| 276 | - | ||
| 277 | /* | ||
| 278 | * Handle a write to a pmpcfg CSP | ||
| 279 | */ | ||
| 280 | @@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 281 | |||
| 282 | return false; | ||
| 283 | } | ||
| 284 | + | ||
| 285 | +/* | ||
| 286 | + * Convert PMP privilege to TLB page privilege. | ||
| 287 | + */ | ||
| 288 | +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv) | ||
| 289 | +{ | ||
| 290 | + int prot = 0; | ||
| 291 | + | ||
| 292 | + if (pmp_priv & PMP_READ) { | ||
| 293 | + prot |= PAGE_READ; | ||
| 294 | + } | ||
| 295 | + if (pmp_priv & PMP_WRITE) { | ||
| 296 | + prot |= PAGE_WRITE; | ||
| 297 | + } | ||
| 298 | + if (pmp_priv & PMP_EXEC) { | ||
| 299 | + prot |= PAGE_EXEC; | ||
| 300 | + } | 65 | + } |
| 301 | + | 66 | + |
| 302 | + return prot; | 67 | return ret; |
| 303 | +} | 68 | } |
| 69 | |||
| 304 | -- | 70 | -- |
| 305 | 2.30.1 | 71 | 2.40.1 |
| 306 | |||
| 307 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | At this moment we're retrieving env->misa_ext during | ||
| 4 | kvm_arch_init_cpu(), leaving env->misa_ext_mask behind. | ||
| 5 | |||
| 6 | We want to set env->misa_ext_mask, and we want to set it as early as | ||
| 7 | possible. The reason is that we're going to use it in the validation | ||
| 8 | process of the KVM MISA properties we're going to add next. Setting it | ||
| 9 | during arch_init_cpu() is too late for user validation. | ||
| 10 | |||
| 11 | Move the code to a new helper that is going to be called during init() | ||
| 12 | time, via kvm_riscv_init_user_properties(), like we're already doing for | ||
| 13 | the machine ID properties. Set both misa_ext and misa_ext_mask to the | ||
| 14 | same value retrieved by the 'isa' config reg. | ||
| 15 | |||
| 16 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 17 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 18 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 19 | Message-Id: <20230706101738.460804-11-dbarboza@ventanamicro.com> | ||
| 20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 21 | --- | ||
| 22 | target/riscv/kvm.c | 34 +++++++++++++++++++++++----------- | ||
| 23 | 1 file changed, 23 insertions(+), 11 deletions(-) | ||
| 24 | |||
| 25 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/riscv/kvm.c | ||
| 28 | +++ b/target/riscv/kvm.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 30 | } | ||
| 31 | } | ||
| 32 | |||
| 33 | +static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, | ||
| 34 | + KVMScratchCPU *kvmcpu) | ||
| 35 | +{ | ||
| 36 | + CPURISCVState *env = &cpu->env; | ||
| 37 | + struct kvm_one_reg reg; | ||
| 38 | + int ret; | ||
| 39 | + | ||
| 40 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 41 | + KVM_REG_RISCV_CONFIG_REG(isa)); | ||
| 42 | + reg.addr = (uint64_t)&env->misa_ext_mask; | ||
| 43 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 44 | + | ||
| 45 | + if (ret) { | ||
| 46 | + error_report("Unable to fetch ISA register from KVM, " | ||
| 47 | + "error %d", ret); | ||
| 48 | + kvm_riscv_destroy_scratch_vcpu(kvmcpu); | ||
| 49 | + exit(EXIT_FAILURE); | ||
| 50 | + } | ||
| 51 | + | ||
| 52 | + env->misa_ext = env->misa_ext_mask; | ||
| 53 | +} | ||
| 54 | + | ||
| 55 | void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 56 | { | ||
| 57 | RISCVCPU *cpu = RISCV_CPU(cpu_obj); | ||
| 58 | @@ -XXX,XX +XXX,XX @@ void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 59 | } | ||
| 60 | |||
| 61 | kvm_riscv_init_machine_ids(cpu, &kvmcpu); | ||
| 62 | + kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); | ||
| 63 | |||
| 64 | kvm_riscv_destroy_scratch_vcpu(&kvmcpu); | ||
| 65 | } | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) | ||
| 67 | int kvm_arch_init_vcpu(CPUState *cs) | ||
| 68 | { | ||
| 69 | int ret = 0; | ||
| 70 | - target_ulong isa; | ||
| 71 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 72 | - CPURISCVState *env = &cpu->env; | ||
| 73 | - uint64_t id; | ||
| 74 | |||
| 75 | qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); | ||
| 76 | |||
| 77 | - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 78 | - KVM_REG_RISCV_CONFIG_REG(isa)); | ||
| 79 | - ret = kvm_get_one_reg(cs, id, &isa); | ||
| 80 | - if (ret) { | ||
| 81 | - return ret; | ||
| 82 | - } | ||
| 83 | - env->misa_ext = isa; | ||
| 84 | - | ||
| 85 | if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { | ||
| 86 | ret = kvm_vcpu_set_machine_ids(cpu, cs); | ||
| 87 | } | ||
| 88 | -- | ||
| 89 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The current two-stage lookup detection in riscv_cpu_do_interrupt falls | 3 | Next patch will add KVM specific user properties for both MISA and |
| 4 | short of its purpose, as all it checks is whether two-stage address | 4 | multi-letter extensions. For MISA extensions we want to make use of what |
| 5 | translation either via the hypervisor-load store instructions or the | 5 | is already available in misa_ext_cfgs[] to avoid code repetition. |
| 6 | MPRV feature would be allowed. | 6 | |
| 7 | 7 | misa_ext_info_arr[] array will hold name and description for each MISA | |
| 8 | What we really need instead is whether two-stage address translation was | 8 | extension that misa_ext_cfgs[] is declaring. We'll then use this new |
| 9 | active when the exception was raised. However, in riscv_cpu_do_interrupt | 9 | array in KVM code to avoid duplicating strings. Two getters were added |
| 10 | we do not have the information to reliably detect this. Therefore, when | 10 | to allow KVM to retrieve the 'name' and 'description' for each MISA |
| 11 | we raise a memory fault exception we have to record whether two-stage | 11 | property. |
| 12 | address translation is active. | 12 | |
| 13 | 13 | There's nothing holding us back from doing the same with multi-letter | |
| 14 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 14 | extensions. For now doing just with MISA extensions is enough. |
| 15 | |||
| 16 | It is worth documenting that even using the __bultin_ctz() directive to | ||
| 17 | populate the misa_ext_info_arr[] we are forced to assign 'name' and | ||
| 18 | 'description' during runtime in riscv_cpu_add_misa_properties(). The | ||
| 19 | reason is that some Gitlab runners ('clang-user' and 'tsan-build') will | ||
| 20 | throw errors like this if we fetch 'name' and 'description' from the | ||
| 21 | array in the MISA_CFG() macro: | ||
| 22 | |||
| 23 | ../target/riscv/cpu.c:1624:5: error: initializer element is not a | ||
| 24 | compile-time constant | ||
| 25 | MISA_CFG(RVA, true), | ||
| 26 | ^~~~~~~~~~~~~~~~~~~ | ||
| 27 | ../target/riscv/cpu.c:1619:53: note: expanded from macro 'MISA_CFG' | ||
| 28 | {.name = misa_ext_info_arr[MISA_INFO_IDX(_bit)].name, \ | ||
| 29 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~ | ||
| 30 | |||
| 31 | gcc and others compilers/builders were fine with that change. We can't | ||
| 32 | ignore failures in the Gitlab pipeline though, so code was changed to | ||
| 33 | make every runner happy. | ||
| 34 | |||
| 35 | As a side effect, misa_ext_cfg[] is no longer a 'const' array because | ||
| 36 | it must be set during runtime. | ||
| 37 | |||
| 38 | Suggested-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 39 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 40 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 41 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 42 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 16 | Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com | 43 | Message-Id: <20230706101738.460804-12-dbarboza@ventanamicro.com> |
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 44 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 18 | --- | 45 | --- |
| 19 | target/riscv/cpu.h | 4 ++++ | 46 | target/riscv/cpu.h | 7 ++- |
| 20 | target/riscv/cpu.c | 1 + | 47 | target/riscv/cpu.c | 110 +++++++++++++++++++++++++++++++++------------ |
| 21 | target/riscv/cpu_helper.c | 21 ++++++++------------- | 48 | 2 files changed, 88 insertions(+), 29 deletions(-) |
| 22 | 3 files changed, 13 insertions(+), 13 deletions(-) | ||
| 23 | 49 | ||
| 24 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | 50 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h |
| 25 | index XXXXXXX..XXXXXXX 100644 | 51 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/target/riscv/cpu.h | 52 | --- a/target/riscv/cpu.h |
| 27 | +++ b/target/riscv/cpu.h | 53 | +++ b/target/riscv/cpu.h |
| 28 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | 54 | @@ -XXX,XX +XXX,XX @@ |
| 29 | target_ulong satp_hs; | 55 | |
| 30 | uint64_t mstatus_hs; | 56 | #define RV(x) ((target_ulong)1 << (x - 'A')) |
| 31 | 57 | ||
| 32 | + /* Signals whether the current exception occurred with two-stage address | 58 | -/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ |
| 33 | + translation active. */ | 59 | +/* |
| 34 | + bool two_stage_lookup; | 60 | + * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] |
| 35 | + | 61 | + * when adding new MISA bits here. |
| 36 | target_ulong scounteren; | 62 | + */ |
| 37 | target_ulong mcounteren; | 63 | #define RVI RV('I') |
| 38 | 64 | #define RVE RV('E') /* E and I are mutually exclusive */ | |
| 65 | #define RVM RV('M') | ||
| 66 | @@ -XXX,XX +XXX,XX @@ | ||
| 67 | #define RVJ RV('J') | ||
| 68 | #define RVG RV('G') | ||
| 69 | |||
| 70 | +const char *riscv_get_misa_ext_name(uint32_t bit); | ||
| 71 | +const char *riscv_get_misa_ext_description(uint32_t bit); | ||
| 72 | |||
| 73 | /* Privileged specification version */ | ||
| 74 | enum { | ||
| 39 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | 75 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
| 40 | index XXXXXXX..XXXXXXX 100644 | 76 | index XXXXXXX..XXXXXXX 100644 |
| 41 | --- a/target/riscv/cpu.c | 77 | --- a/target/riscv/cpu.c |
| 42 | +++ b/target/riscv/cpu.c | 78 | +++ b/target/riscv/cpu.c |
| 43 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev) | 79 | @@ -XXX,XX +XXX,XX @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, |
| 44 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | 80 | visit_type_bool(v, name, &value, errp); |
| 45 | env->mcause = 0; | ||
| 46 | env->pc = env->resetvec; | ||
| 47 | + env->two_stage_lookup = false; | ||
| 48 | #endif | ||
| 49 | cs->exception_index = EXCP_NONE; | ||
| 50 | env->load_res = -1; | ||
| 51 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | ||
| 52 | index XXXXXXX..XXXXXXX 100644 | ||
| 53 | --- a/target/riscv/cpu_helper.c | ||
| 54 | +++ b/target/riscv/cpu_helper.c | ||
| 55 | @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | ||
| 56 | g_assert_not_reached(); | ||
| 57 | } | ||
| 58 | env->badaddr = address; | ||
| 59 | + env->two_stage_lookup = two_stage; | ||
| 60 | } | 81 | } |
| 61 | 82 | ||
| 62 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | 83 | -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { |
| 63 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | 84 | - {.name = "a", .description = "Atomic instructions", |
| 64 | } | 85 | - .misa_bit = RVA, .enabled = true}, |
| 65 | 86 | - {.name = "c", .description = "Compressed instructions", | |
| 66 | env->badaddr = addr; | 87 | - .misa_bit = RVC, .enabled = true}, |
| 67 | + env->two_stage_lookup = riscv_cpu_virt_enabled(env) || | 88 | - {.name = "d", .description = "Double-precision float point", |
| 68 | + riscv_cpu_two_stage_lookup(mmu_idx); | 89 | - .misa_bit = RVD, .enabled = true}, |
| 69 | riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); | 90 | - {.name = "f", .description = "Single-precision float point", |
| 70 | } | 91 | - .misa_bit = RVF, .enabled = true}, |
| 71 | 92 | - {.name = "i", .description = "Base integer instruction set", | |
| 72 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | 93 | - .misa_bit = RVI, .enabled = true}, |
| 73 | g_assert_not_reached(); | 94 | - {.name = "e", .description = "Base integer instruction set (embedded)", |
| 74 | } | 95 | - .misa_bit = RVE, .enabled = false}, |
| 75 | env->badaddr = addr; | 96 | - {.name = "m", .description = "Integer multiplication and division", |
| 76 | + env->two_stage_lookup = riscv_cpu_virt_enabled(env) || | 97 | - .misa_bit = RVM, .enabled = true}, |
| 77 | + riscv_cpu_two_stage_lookup(mmu_idx); | 98 | - {.name = "s", .description = "Supervisor-level instructions", |
| 78 | riscv_raise_exception(env, cs->exception_index, retaddr); | 99 | - .misa_bit = RVS, .enabled = true}, |
| 79 | } | 100 | - {.name = "u", .description = "User-level instructions", |
| 80 | #endif /* !CONFIG_USER_ONLY */ | 101 | - .misa_bit = RVU, .enabled = true}, |
| 81 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 102 | - {.name = "h", .description = "Hypervisor", |
| 82 | /* handle the trap in S-mode */ | 103 | - .misa_bit = RVH, .enabled = true}, |
| 83 | if (riscv_has_ext(env, RVH)) { | 104 | - {.name = "x-j", .description = "Dynamic translated languages", |
| 84 | target_ulong hdeleg = async ? env->hideleg : env->hedeleg; | 105 | - .misa_bit = RVJ, .enabled = false}, |
| 85 | - bool two_stage_lookup = false; | 106 | - {.name = "v", .description = "Vector operations", |
| 86 | 107 | - .misa_bit = RVV, .enabled = false}, | |
| 87 | - if (env->priv == PRV_M || | 108 | - {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", |
| 88 | - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | 109 | - .misa_bit = RVG, .enabled = false}, |
| 89 | - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | 110 | +typedef struct misa_ext_info { |
| 90 | - get_field(env->hstatus, HSTATUS_HU))) { | 111 | + const char *name; |
| 91 | - two_stage_lookup = true; | 112 | + const char *description; |
| 92 | - } | 113 | +} MISAExtInfo; |
| 93 | - | 114 | + |
| 94 | - if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) { | 115 | +#define MISA_INFO_IDX(_bit) \ |
| 95 | + if (env->two_stage_lookup && write_tval) { | 116 | + __builtin_ctz(_bit) |
| 96 | /* | 117 | + |
| 97 | * If we are writing a guest virtual address to stval, set | 118 | +#define MISA_EXT_INFO(_bit, _propname, _descr) \ |
| 98 | * this to 1. If we are trapping to VS we will set this to 0 | 119 | + [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr} |
| 99 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 120 | + |
| 100 | riscv_cpu_set_force_hs_excep(env, 0); | 121 | +static const MISAExtInfo misa_ext_info_arr[] = { |
| 101 | } else { | 122 | + MISA_EXT_INFO(RVA, "a", "Atomic instructions"), |
| 102 | /* Trap into HS mode */ | 123 | + MISA_EXT_INFO(RVC, "c", "Compressed instructions"), |
| 103 | - if (!two_stage_lookup) { | 124 | + MISA_EXT_INFO(RVD, "d", "Double-precision float point"), |
| 104 | - env->hstatus = set_field(env->hstatus, HSTATUS_SPV, | 125 | + MISA_EXT_INFO(RVF, "f", "Single-precision float point"), |
| 105 | - riscv_cpu_virt_enabled(env)); | 126 | + MISA_EXT_INFO(RVI, "i", "Base integer instruction set"), |
| 106 | - } | 127 | + MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"), |
| 107 | + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); | 128 | + MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"), |
| 108 | htval = env->guest_phys_fault_addr; | 129 | + MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), |
| 109 | } | 130 | + MISA_EXT_INFO(RVU, "u", "User-level instructions"), |
| 110 | } | 131 | + MISA_EXT_INFO(RVH, "h", "Hypervisor"), |
| 111 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 132 | + MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), |
| 112 | * RISC-V ISA Specification. | 133 | + MISA_EXT_INFO(RVV, "v", "Vector operations"), |
| 113 | */ | 134 | + MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), |
| 114 | 135 | +}; | |
| 115 | + env->two_stage_lookup = false; | 136 | + |
| 116 | #endif | 137 | +static int riscv_validate_misa_info_idx(uint32_t bit) |
| 117 | cs->exception_index = EXCP_NONE; /* mark handled to qemu */ | 138 | +{ |
| 118 | } | 139 | + int idx; |
| 140 | + | ||
| 141 | + /* | ||
| 142 | + * Our lowest valid input (RVA) is 1 and | ||
| 143 | + * __builtin_ctz() is UB with zero. | ||
| 144 | + */ | ||
| 145 | + g_assert(bit != 0); | ||
| 146 | + idx = MISA_INFO_IDX(bit); | ||
| 147 | + | ||
| 148 | + g_assert(idx < ARRAY_SIZE(misa_ext_info_arr)); | ||
| 149 | + return idx; | ||
| 150 | +} | ||
| 151 | + | ||
| 152 | +const char *riscv_get_misa_ext_name(uint32_t bit) | ||
| 153 | +{ | ||
| 154 | + int idx = riscv_validate_misa_info_idx(bit); | ||
| 155 | + const char *val = misa_ext_info_arr[idx].name; | ||
| 156 | + | ||
| 157 | + g_assert(val != NULL); | ||
| 158 | + return val; | ||
| 159 | +} | ||
| 160 | + | ||
| 161 | +const char *riscv_get_misa_ext_description(uint32_t bit) | ||
| 162 | +{ | ||
| 163 | + int idx = riscv_validate_misa_info_idx(bit); | ||
| 164 | + const char *val = misa_ext_info_arr[idx].description; | ||
| 165 | + | ||
| 166 | + g_assert(val != NULL); | ||
| 167 | + return val; | ||
| 168 | +} | ||
| 169 | + | ||
| 170 | +#define MISA_CFG(_bit, _enabled) \ | ||
| 171 | + {.misa_bit = _bit, .enabled = _enabled} | ||
| 172 | + | ||
| 173 | +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { | ||
| 174 | + MISA_CFG(RVA, true), | ||
| 175 | + MISA_CFG(RVC, true), | ||
| 176 | + MISA_CFG(RVD, true), | ||
| 177 | + MISA_CFG(RVF, true), | ||
| 178 | + MISA_CFG(RVI, true), | ||
| 179 | + MISA_CFG(RVE, false), | ||
| 180 | + MISA_CFG(RVM, true), | ||
| 181 | + MISA_CFG(RVS, true), | ||
| 182 | + MISA_CFG(RVU, true), | ||
| 183 | + MISA_CFG(RVH, true), | ||
| 184 | + MISA_CFG(RVJ, false), | ||
| 185 | + MISA_CFG(RVV, false), | ||
| 186 | + MISA_CFG(RVG, false), | ||
| 187 | }; | ||
| 188 | |||
| 189 | static void riscv_cpu_add_misa_properties(Object *cpu_obj) | ||
| 190 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) | ||
| 191 | int i; | ||
| 192 | |||
| 193 | for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { | ||
| 194 | - const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; | ||
| 195 | + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; | ||
| 196 | + int bit = misa_cfg->misa_bit; | ||
| 197 | + | ||
| 198 | + misa_cfg->name = riscv_get_misa_ext_name(bit); | ||
| 199 | + misa_cfg->description = riscv_get_misa_ext_description(bit); | ||
| 200 | |||
| 201 | object_property_add(cpu_obj, misa_cfg->name, "bool", | ||
| 202 | cpu_get_misa_ext_cfg, | ||
| 119 | -- | 203 | -- |
| 120 | 2.30.1 | 204 | 2.40.1 |
| 121 | 205 | ||
| 122 | 206 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Using all TCG user properties in KVM is tricky. First because KVM | ||
| 4 | supports only a small subset of what TCG provides, so most of the | ||
| 5 | cpu->cfg flags do nothing for KVM. | ||
| 6 | |||
| 7 | Second, and more important, we don't have a way of telling if any given | ||
| 8 | value is an user input or not. For TCG this has a small impact since we | ||
| 9 | just validating everything and error out if needed. But for KVM it would | ||
| 10 | be good to know if a given value was set by the user or if it's a value | ||
| 11 | already provided by KVM. Otherwise we don't know how to handle failed | ||
| 12 | kvm_set_one_regs() when writing the configurations back. | ||
| 13 | |||
| 14 | These characteristics make it overly complicated to use the same user | ||
| 15 | facing flags for both KVM and TCG. A simpler approach is to create KVM | ||
| 16 | specific properties that have specialized logic, forking KVM and TCG use | ||
| 17 | cases for those cases only. Fully separating KVM/TCG properties is | ||
| 18 | unneeded at this point - in fact we want the user experience to be as | ||
| 19 | equal as possible, regardless of the acceleration chosen. | ||
| 20 | |||
| 21 | We'll start this fork with the MISA properties, adding the MISA bits | ||
| 22 | that the KVM driver currently supports. A new KVMCPUConfig type is | ||
| 23 | introduced. It'll hold general information about an extension. For MISA | ||
| 24 | extensions we're going to use the newly created getters of | ||
| 25 | misa_ext_infos[] to populate their name and description. 'offset' holds | ||
| 26 | the MISA bit (RVA, RVC, ...). We're calling it 'offset' instead of | ||
| 27 | 'misa_bit' because this same KVMCPUConfig struct will be used to | ||
| 28 | multi-letter extensions later on. | ||
| 29 | |||
| 30 | This new type also holds a 'user_set' flag. This flag will be set when | ||
| 31 | the user set an option that's different than what is already configured | ||
| 32 | in the host, requiring KVM intervention to write the regs back during | ||
| 33 | kvm_arch_init_vcpu(). Similar mechanics will be implemented for | ||
| 34 | multi-letter extensions as well. | ||
| 35 | |||
| 36 | There is no need to duplicate more code than necessary, so we're going | ||
| 37 | to use the existing kvm_riscv_init_user_properties() to add the KVM | ||
| 38 | specific properties. Any code that is adding a TCG user prop is then | ||
| 39 | changed slightly to verify first if there's a KVM prop with the same | ||
| 40 | name already added. | ||
| 41 | |||
| 42 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 43 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 44 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 45 | Message-Id: <20230706101738.460804-13-dbarboza@ventanamicro.com> | ||
| 46 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 47 | --- | ||
| 48 | target/riscv/cpu.c | 5 +++ | ||
| 49 | target/riscv/kvm.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 50 | 2 files changed, 83 insertions(+) | ||
| 51 | |||
| 52 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/target/riscv/cpu.c | ||
| 55 | +++ b/target/riscv/cpu.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) | ||
| 57 | misa_cfg->name = riscv_get_misa_ext_name(bit); | ||
| 58 | misa_cfg->description = riscv_get_misa_ext_description(bit); | ||
| 59 | |||
| 60 | + /* Check if KVM already created the property */ | ||
| 61 | + if (object_property_find(cpu_obj, misa_cfg->name)) { | ||
| 62 | + continue; | ||
| 63 | + } | ||
| 64 | + | ||
| 65 | object_property_add(cpu_obj, misa_cfg->name, "bool", | ||
| 66 | cpu_get_misa_ext_cfg, | ||
| 67 | cpu_set_misa_ext_cfg, | ||
| 68 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 69 | index XXXXXXX..XXXXXXX 100644 | ||
| 70 | --- a/target/riscv/kvm.c | ||
| 71 | +++ b/target/riscv/kvm.c | ||
| 72 | @@ -XXX,XX +XXX,XX @@ | ||
| 73 | #include <linux/kvm.h> | ||
| 74 | |||
| 75 | #include "qemu/timer.h" | ||
| 76 | +#include "qapi/error.h" | ||
| 77 | #include "qemu/error-report.h" | ||
| 78 | #include "qemu/main-loop.h" | ||
| 79 | +#include "qapi/visitor.h" | ||
| 80 | #include "sysemu/sysemu.h" | ||
| 81 | #include "sysemu/kvm.h" | ||
| 82 | #include "sysemu/kvm_int.h" | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, | ||
| 84 | } \ | ||
| 85 | } while (0) | ||
| 86 | |||
| 87 | +typedef struct KVMCPUConfig { | ||
| 88 | + const char *name; | ||
| 89 | + const char *description; | ||
| 90 | + target_ulong offset; | ||
| 91 | + int kvm_reg_id; | ||
| 92 | + bool user_set; | ||
| 93 | +} KVMCPUConfig; | ||
| 94 | + | ||
| 95 | +#define KVM_MISA_CFG(_bit, _reg_id) \ | ||
| 96 | + {.offset = _bit, .kvm_reg_id = _reg_id} | ||
| 97 | + | ||
| 98 | +/* KVM ISA extensions */ | ||
| 99 | +static KVMCPUConfig kvm_misa_ext_cfgs[] = { | ||
| 100 | + KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), | ||
| 101 | + KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), | ||
| 102 | + KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), | ||
| 103 | + KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), | ||
| 104 | + KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), | ||
| 105 | + KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), | ||
| 106 | + KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), | ||
| 107 | +}; | ||
| 108 | + | ||
| 109 | +static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, | ||
| 110 | + const char *name, | ||
| 111 | + void *opaque, Error **errp) | ||
| 112 | +{ | ||
| 113 | + KVMCPUConfig *misa_ext_cfg = opaque; | ||
| 114 | + target_ulong misa_bit = misa_ext_cfg->offset; | ||
| 115 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 116 | + CPURISCVState *env = &cpu->env; | ||
| 117 | + bool value, host_bit; | ||
| 118 | + | ||
| 119 | + if (!visit_type_bool(v, name, &value, errp)) { | ||
| 120 | + return; | ||
| 121 | + } | ||
| 122 | + | ||
| 123 | + host_bit = env->misa_ext_mask & misa_bit; | ||
| 124 | + | ||
| 125 | + if (value == host_bit) { | ||
| 126 | + return; | ||
| 127 | + } | ||
| 128 | + | ||
| 129 | + if (!value) { | ||
| 130 | + misa_ext_cfg->user_set = true; | ||
| 131 | + return; | ||
| 132 | + } | ||
| 133 | + | ||
| 134 | + /* | ||
| 135 | + * Forbid users to enable extensions that aren't | ||
| 136 | + * available in the hart. | ||
| 137 | + */ | ||
| 138 | + error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " | ||
| 139 | + "enabled in the host", misa_ext_cfg->name); | ||
| 140 | +} | ||
| 141 | + | ||
| 142 | +static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 143 | +{ | ||
| 144 | + int i; | ||
| 145 | + | ||
| 146 | + for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { | ||
| 147 | + KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; | ||
| 148 | + int bit = misa_cfg->offset; | ||
| 149 | + | ||
| 150 | + misa_cfg->name = riscv_get_misa_ext_name(bit); | ||
| 151 | + misa_cfg->description = riscv_get_misa_ext_description(bit); | ||
| 152 | + | ||
| 153 | + object_property_add(cpu_obj, misa_cfg->name, "bool", | ||
| 154 | + NULL, | ||
| 155 | + kvm_cpu_set_misa_ext_cfg, | ||
| 156 | + NULL, misa_cfg); | ||
| 157 | + object_property_set_description(cpu_obj, misa_cfg->name, | ||
| 158 | + misa_cfg->description); | ||
| 159 | + } | ||
| 160 | +} | ||
| 161 | + | ||
| 162 | static int kvm_riscv_get_regs_core(CPUState *cs) | ||
| 163 | { | ||
| 164 | int ret = 0; | ||
| 165 | @@ -XXX,XX +XXX,XX @@ void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 166 | return; | ||
| 167 | } | ||
| 168 | |||
| 169 | + kvm_riscv_add_cpu_user_properties(cpu_obj); | ||
| 170 | kvm_riscv_init_machine_ids(cpu, &kvmcpu); | ||
| 171 | kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); | ||
| 172 | |||
| 173 | -- | ||
| 174 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | Our design philosophy with KVM properties can be resumed in two main | ||
| 4 | decisions based on KVM interface availability and what the user wants to | ||
| 5 | do: | ||
| 6 | |||
| 7 | - if the user disables an extension that the host KVM module doesn't | ||
| 8 | know about (i.e. it doesn't implement the kvm_get_one_reg() interface), | ||
| 9 | keep booting the CPU. This will avoid users having to deal with issues | ||
| 10 | with older KVM versions while disabling features they don't care; | ||
| 11 | |||
| 12 | - for any other case we're going to error out immediately. If the user | ||
| 13 | wants to enable a feature that KVM doesn't know about this a problem that | ||
| 14 | is worth aborting - the user must know that the feature wasn't enabled | ||
| 15 | in the hart. Likewise, if KVM knows about the extension, the user wants | ||
| 16 | to enable/disable it, and we fail to do it so, that's also a problem we | ||
| 17 | can't shrug it off. | ||
| 18 | |||
| 19 | In the case of MISA bits we won't even try enabling bits that aren't | ||
| 20 | already available in the host. The ioctl() is so likely to fail that | ||
| 21 | it's not worth trying. This check is already done in the previous patch, | ||
| 22 | in kvm_cpu_set_misa_ext_cfg(), thus we don't need to worry about it now. | ||
| 23 | |||
| 24 | In kvm_riscv_update_cpu_misa_ext() we'll go through every potential user | ||
| 25 | option and do as follows: | ||
| 26 | |||
| 27 | - if the user didn't set the property or set to the same value of the | ||
| 28 | host, do nothing; | ||
| 29 | |||
| 30 | - Disable the given extension in KVM. Error out if anything goes wrong. | ||
| 31 | |||
| 32 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 33 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 34 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 35 | Message-Id: <20230706101738.460804-14-dbarboza@ventanamicro.com> | ||
| 36 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 37 | --- | ||
| 38 | target/riscv/kvm.c | 40 ++++++++++++++++++++++++++++++++++++++++ | ||
| 39 | 1 file changed, 40 insertions(+) | ||
| 40 | |||
| 41 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/target/riscv/kvm.c | ||
| 44 | +++ b/target/riscv/kvm.c | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, | ||
| 46 | "enabled in the host", misa_ext_cfg->name); | ||
| 47 | } | ||
| 48 | |||
| 49 | +static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) | ||
| 50 | +{ | ||
| 51 | + CPURISCVState *env = &cpu->env; | ||
| 52 | + uint64_t id, reg; | ||
| 53 | + int i, ret; | ||
| 54 | + | ||
| 55 | + for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { | ||
| 56 | + KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; | ||
| 57 | + target_ulong misa_bit = misa_cfg->offset; | ||
| 58 | + | ||
| 59 | + if (!misa_cfg->user_set) { | ||
| 60 | + continue; | ||
| 61 | + } | ||
| 62 | + | ||
| 63 | + /* If we're here we're going to disable the MISA bit */ | ||
| 64 | + reg = 0; | ||
| 65 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, | ||
| 66 | + misa_cfg->kvm_reg_id); | ||
| 67 | + ret = kvm_set_one_reg(cs, id, ®); | ||
| 68 | + if (ret != 0) { | ||
| 69 | + /* | ||
| 70 | + * We're not checking for -EINVAL because if the bit is about | ||
| 71 | + * to be disabled, it means that it was already enabled by | ||
| 72 | + * KVM. We determined that by fetching the 'isa' register | ||
| 73 | + * during init() time. Any error at this point is worth | ||
| 74 | + * aborting. | ||
| 75 | + */ | ||
| 76 | + error_report("Unable to set KVM reg %s, error %d", | ||
| 77 | + misa_cfg->name, ret); | ||
| 78 | + exit(EXIT_FAILURE); | ||
| 79 | + } | ||
| 80 | + env->misa_ext &= ~misa_bit; | ||
| 81 | + } | ||
| 82 | +} | ||
| 83 | + | ||
| 84 | static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 85 | { | ||
| 86 | int i; | ||
| 87 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
| 88 | |||
| 89 | if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { | ||
| 90 | ret = kvm_vcpu_set_machine_ids(cpu, cs); | ||
| 91 | + if (ret != 0) { | ||
| 92 | + return ret; | ||
| 93 | + } | ||
| 94 | } | ||
| 95 | |||
| 96 | + kvm_riscv_update_cpu_misa_ext(cpu, cs); | ||
| 97 | + | ||
| 98 | return ret; | ||
| 99 | } | ||
| 100 | |||
| 101 | -- | ||
| 102 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
| 2 | |||
| 3 | Let's add KVM user properties for the multi-letter extensions that KVM | ||
| 4 | currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc, | ||
| 5 | svinval and svpbmt. | ||
| 6 | |||
| 7 | As with MISA extensions, we're using the KVMCPUConfig type to hold | ||
| 8 | information about the state of each extension. However, multi-letter | ||
| 9 | extensions have more cases to cover than MISA extensions, so we're | ||
| 10 | adding an extra 'supported' flag as well. This flag will reflect if a | ||
| 11 | given extension is supported by KVM, i.e. KVM knows how to handle it. | ||
| 12 | This is determined during KVM extension discovery in | ||
| 13 | kvm_riscv_init_multiext_cfg(), where we test for EINVAL errors. Any | ||
| 14 | other error will cause an abort. | ||
| 15 | |||
| 16 | The use of the 'user_set' is similar to what we already do with MISA | ||
| 17 | extensions: the flag set only if the user is changing the extension | ||
| 18 | state. | ||
| 19 | |||
| 20 | The 'supported' flag will be used later on to make an exception for | ||
| 21 | users that are disabling multi-letter extensions that are unknown to | ||
| 22 | KVM. | ||
| 23 | |||
| 24 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 25 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 26 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 27 | Message-Id: <20230706101738.460804-15-dbarboza@ventanamicro.com> | ||
| 28 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 29 | --- | ||
| 30 | target/riscv/cpu.c | 8 +++ | ||
| 31 | target/riscv/kvm.c | 119 +++++++++++++++++++++++++++++++++++++++++++++ | ||
| 32 | 2 files changed, 127 insertions(+) | ||
| 33 | |||
| 34 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/target/riscv/cpu.c | ||
| 37 | +++ b/target/riscv/cpu.c | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) | ||
| 39 | riscv_cpu_add_misa_properties(obj); | ||
| 40 | |||
| 41 | for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { | ||
| 42 | +#ifndef CONFIG_USER_ONLY | ||
| 43 | + if (kvm_enabled()) { | ||
| 44 | + /* Check if KVM created the property already */ | ||
| 45 | + if (object_property_find(obj, prop->name)) { | ||
| 46 | + continue; | ||
| 47 | + } | ||
| 48 | + } | ||
| 49 | +#endif | ||
| 50 | qdev_property_add_static(dev, prop); | ||
| 51 | } | ||
| 52 | |||
| 53 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/target/riscv/kvm.c | ||
| 56 | +++ b/target/riscv/kvm.c | ||
| 57 | @@ -XXX,XX +XXX,XX @@ typedef struct KVMCPUConfig { | ||
| 58 | target_ulong offset; | ||
| 59 | int kvm_reg_id; | ||
| 60 | bool user_set; | ||
| 61 | + bool supported; | ||
| 62 | } KVMCPUConfig; | ||
| 63 | |||
| 64 | #define KVM_MISA_CFG(_bit, _reg_id) \ | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) | ||
| 66 | } | ||
| 67 | } | ||
| 68 | |||
| 69 | +#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) | ||
| 70 | + | ||
| 71 | +#define KVM_EXT_CFG(_name, _prop, _reg_id) \ | ||
| 72 | + {.name = _name, .offset = CPUCFG(_prop), \ | ||
| 73 | + .kvm_reg_id = _reg_id} | ||
| 74 | + | ||
| 75 | +static KVMCPUConfig kvm_multi_ext_cfgs[] = { | ||
| 76 | + KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM), | ||
| 77 | + KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ), | ||
| 78 | + KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), | ||
| 79 | + KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), | ||
| 80 | + KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), | ||
| 81 | + KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), | ||
| 82 | + KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), | ||
| 83 | + KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), | ||
| 84 | +}; | ||
| 85 | + | ||
| 86 | +static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, | ||
| 87 | + uint32_t val) | ||
| 88 | +{ | ||
| 89 | + int cpu_cfg_offset = multi_ext->offset; | ||
| 90 | + bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset; | ||
| 91 | + | ||
| 92 | + *ext_enabled = val; | ||
| 93 | +} | ||
| 94 | + | ||
| 95 | +static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, | ||
| 96 | + KVMCPUConfig *multi_ext) | ||
| 97 | +{ | ||
| 98 | + int cpu_cfg_offset = multi_ext->offset; | ||
| 99 | + bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset; | ||
| 100 | + | ||
| 101 | + return *ext_enabled; | ||
| 102 | +} | ||
| 103 | + | ||
| 104 | +static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, | ||
| 105 | + const char *name, | ||
| 106 | + void *opaque, Error **errp) | ||
| 107 | +{ | ||
| 108 | + KVMCPUConfig *multi_ext_cfg = opaque; | ||
| 109 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 110 | + bool value, host_val; | ||
| 111 | + | ||
| 112 | + if (!visit_type_bool(v, name, &value, errp)) { | ||
| 113 | + return; | ||
| 114 | + } | ||
| 115 | + | ||
| 116 | + host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); | ||
| 117 | + | ||
| 118 | + /* | ||
| 119 | + * Ignore if the user is setting the same value | ||
| 120 | + * as the host. | ||
| 121 | + */ | ||
| 122 | + if (value == host_val) { | ||
| 123 | + return; | ||
| 124 | + } | ||
| 125 | + | ||
| 126 | + if (!multi_ext_cfg->supported) { | ||
| 127 | + /* | ||
| 128 | + * Error out if the user is trying to enable an | ||
| 129 | + * extension that KVM doesn't support. Ignore | ||
| 130 | + * option otherwise. | ||
| 131 | + */ | ||
| 132 | + if (value) { | ||
| 133 | + error_setg(errp, "KVM does not support disabling extension %s", | ||
| 134 | + multi_ext_cfg->name); | ||
| 135 | + } | ||
| 136 | + | ||
| 137 | + return; | ||
| 138 | + } | ||
| 139 | + | ||
| 140 | + multi_ext_cfg->user_set = true; | ||
| 141 | + kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); | ||
| 142 | +} | ||
| 143 | + | ||
| 144 | static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 145 | { | ||
| 146 | int i; | ||
| 147 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 148 | object_property_set_description(cpu_obj, misa_cfg->name, | ||
| 149 | misa_cfg->description); | ||
| 150 | } | ||
| 151 | + | ||
| 152 | + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { | ||
| 153 | + KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; | ||
| 154 | + | ||
| 155 | + object_property_add(cpu_obj, multi_cfg->name, "bool", | ||
| 156 | + NULL, | ||
| 157 | + kvm_cpu_set_multi_ext_cfg, | ||
| 158 | + NULL, multi_cfg); | ||
| 159 | + } | ||
| 160 | } | ||
| 161 | |||
| 162 | static int kvm_riscv_get_regs_core(CPUState *cs) | ||
| 163 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, | ||
| 164 | env->misa_ext = env->misa_ext_mask; | ||
| 165 | } | ||
| 166 | |||
| 167 | +static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 168 | +{ | ||
| 169 | + CPURISCVState *env = &cpu->env; | ||
| 170 | + uint64_t val; | ||
| 171 | + int i, ret; | ||
| 172 | + | ||
| 173 | + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { | ||
| 174 | + KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; | ||
| 175 | + struct kvm_one_reg reg; | ||
| 176 | + | ||
| 177 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, | ||
| 178 | + multi_ext_cfg->kvm_reg_id); | ||
| 179 | + reg.addr = (uint64_t)&val; | ||
| 180 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 181 | + if (ret != 0) { | ||
| 182 | + if (errno == EINVAL) { | ||
| 183 | + /* Silently default to 'false' if KVM does not support it. */ | ||
| 184 | + multi_ext_cfg->supported = false; | ||
| 185 | + val = false; | ||
| 186 | + } else { | ||
| 187 | + error_report("Unable to read ISA_EXT KVM register %s, " | ||
| 188 | + "error %d", multi_ext_cfg->name, ret); | ||
| 189 | + kvm_riscv_destroy_scratch_vcpu(kvmcpu); | ||
| 190 | + exit(EXIT_FAILURE); | ||
| 191 | + } | ||
| 192 | + } else { | ||
| 193 | + multi_ext_cfg->supported = true; | ||
| 194 | + } | ||
| 195 | + | ||
| 196 | + kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); | ||
| 197 | + } | ||
| 198 | +} | ||
| 199 | + | ||
| 200 | void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 201 | { | ||
| 202 | RISCVCPU *cpu = RISCV_CPU(cpu_obj); | ||
| 203 | @@ -XXX,XX +XXX,XX @@ void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 204 | kvm_riscv_add_cpu_user_properties(cpu_obj); | ||
| 205 | kvm_riscv_init_machine_ids(cpu, &kvmcpu); | ||
| 206 | kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); | ||
| 207 | + kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); | ||
| 208 | |||
| 209 | kvm_riscv_destroy_scratch_vcpu(&kvmcpu); | ||
| 210 | } | ||
| 211 | -- | ||
| 212 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | If PMP permission of any address has been changed by updating PMP entry, | 3 | riscv_cpu_add_user_properties() ended up with an excess of "#ifndef |
| 4 | flush all TLB pages to prevent from getting old permission. | 4 | CONFIG_USER_ONLY" blocks after changes that added KVM properties |
| 5 | handling. | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Jim Shu <cwshu@andestech.com> | 7 | KVM specific properties are required to be created earlier than their |
| 8 | TCG counterparts, but the remaining props can be created at any order. | ||
| 9 | Move riscv_add_satp_mode_properties() to the start of the function, | ||
| 10 | inside the !CONFIG_USER_ONLY block already present there, to remove the | ||
| 11 | last ifndef block. | ||
| 12 | |||
| 13 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 14 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com | 17 | Message-Id: <20230706101738.460804-16-dbarboza@ventanamicro.com> |
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 19 | --- |
| 11 | target/riscv/pmp.c | 4 ++++ | 20 | target/riscv/cpu.c | 6 ++---- |
| 12 | 1 file changed, 4 insertions(+) | 21 | 1 file changed, 2 insertions(+), 4 deletions(-) |
| 13 | 22 | ||
| 14 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | 23 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/riscv/pmp.c | 25 | --- a/target/riscv/cpu.c |
| 17 | +++ b/target/riscv/pmp.c | 26 | +++ b/target/riscv/cpu.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) |
| 19 | #include "qapi/error.h" | 28 | DeviceState *dev = DEVICE(obj); |
| 20 | #include "cpu.h" | 29 | |
| 21 | #include "trace.h" | 30 | #ifndef CONFIG_USER_ONLY |
| 22 | +#include "exec/exec-all.h" | 31 | + riscv_add_satp_mode_properties(obj); |
| 23 | 32 | + | |
| 24 | static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, | 33 | if (kvm_enabled()) { |
| 25 | uint8_t val); | 34 | kvm_riscv_init_user_properties(obj); |
| 26 | @@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, | ||
| 27 | cfg_val = (val >> 8 * i) & 0xff; | ||
| 28 | pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); | ||
| 29 | } | 35 | } |
| 30 | + | 36 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) |
| 31 | + /* If PMP permission of any addr has been changed, flush TLB pages. */ | 37 | #endif |
| 32 | + tlb_flush(env_cpu(env)); | 38 | qdev_property_add_static(dev, prop); |
| 39 | } | ||
| 40 | - | ||
| 41 | -#ifndef CONFIG_USER_ONLY | ||
| 42 | - riscv_add_satp_mode_properties(obj); | ||
| 43 | -#endif | ||
| 33 | } | 44 | } |
| 34 | 45 | ||
| 35 | 46 | static Property riscv_cpu_properties[] = { | |
| 36 | -- | 47 | -- |
| 37 | 2.30.1 | 48 | 2.40.1 |
| 38 | 49 | ||
| 39 | 50 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | riscv_isa_string_ext() is being used by riscv_isa_string(), which is | ||
| 4 | then used by boards to retrieve the 'riscv,isa' string to be written in | ||
| 5 | the FDT. All this happens after riscv_cpu_realize(), meaning that we're | ||
| 6 | already past riscv_cpu_validate_set_extensions() and, more important, | ||
| 7 | riscv_cpu_disable_priv_spec_isa_exts(). | ||
| 8 | |||
| 9 | This means that all extensions that needed to be disabled due to | ||
| 10 | priv_spec mismatch are already disabled. Checking this again during | ||
| 11 | riscv_isa_string_ext() is unneeded. Remove it. | ||
| 12 | |||
| 13 | As a bonus, riscv_isa_string_ext() can now be used with the 'host' | ||
| 14 | KVM-only CPU type since it doesn't have a env->priv_ver assigned and it | ||
| 15 | would fail this check for no good reason. | ||
| 16 | |||
| 17 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 18 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 19 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 20 | Message-Id: <20230706101738.460804-17-dbarboza@ventanamicro.com> | ||
| 21 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 22 | --- | ||
| 23 | target/riscv/cpu.c | 3 +-- | ||
| 24 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
| 25 | |||
| 26 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 27 | index XXXXXXX..XXXXXXX 100644 | ||
| 28 | --- a/target/riscv/cpu.c | ||
| 29 | +++ b/target/riscv/cpu.c | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, | ||
| 31 | int i; | ||
| 32 | |||
| 33 | for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { | ||
| 34 | - if (cpu->env.priv_ver >= isa_edata_arr[i].min_version && | ||
| 35 | - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | ||
| 36 | + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { | ||
| 37 | new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); | ||
| 38 | g_free(old); | ||
| 39 | old = new; | ||
| 40 | -- | ||
| 41 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | KVM-specific properties are being created inside target/riscv/kvm.c. But | ||
| 4 | at this moment we're gathering all the remaining properties from TCG and | ||
| 5 | adding them as is when running KVM. This creates a situation where | ||
| 6 | non-KVM properties are setting flags to 'true' due to its default | ||
| 7 | settings (e.g. Zawrs). Users can also freely enable them via command | ||
| 8 | line. | ||
| 9 | |||
| 10 | This doesn't impact runtime per se because KVM doesn't care about these | ||
| 11 | flags, but code such as riscv_isa_string_ext() take those flags into | ||
| 12 | account. The result is that, for a KVM guest, setting non-KVM properties | ||
| 13 | will make them appear in the riscv,isa DT. | ||
| 14 | |||
| 15 | We want to keep the same API for both TCG and KVM and at the same time, | ||
| 16 | when running KVM, forbid non-KVM extensions to be enabled internally. We | ||
| 17 | accomplish both by changing riscv_cpu_add_user_properties() to add a | ||
| 18 | mock boolean property for every non-KVM extension in | ||
| 19 | riscv_cpu_extensions[]. Then, when running KVM, users are still free to | ||
| 20 | set extensions at will, but we'll error out if a non-KVM extension is | ||
| 21 | enabled. Setting such extension to 'false' will be ignored. | ||
| 22 | |||
| 23 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 24 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 25 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 26 | Message-Id: <20230706101738.460804-18-dbarboza@ventanamicro.com> | ||
| 27 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 28 | --- | ||
| 29 | target/riscv/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ | ||
| 30 | 1 file changed, 36 insertions(+) | ||
| 31 | |||
| 32 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/riscv/cpu.c | ||
| 35 | +++ b/target/riscv/cpu.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
| 37 | DEFINE_PROP_END_OF_LIST(), | ||
| 38 | }; | ||
| 39 | |||
| 40 | + | ||
| 41 | +#ifndef CONFIG_USER_ONLY | ||
| 42 | +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, | ||
| 43 | + const char *name, | ||
| 44 | + void *opaque, Error **errp) | ||
| 45 | +{ | ||
| 46 | + const char *propname = opaque; | ||
| 47 | + bool value; | ||
| 48 | + | ||
| 49 | + if (!visit_type_bool(v, name, &value, errp)) { | ||
| 50 | + return; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + if (value) { | ||
| 54 | + error_setg(errp, "extension %s is not available with KVM", | ||
| 55 | + propname); | ||
| 56 | + } | ||
| 57 | +} | ||
| 58 | +#endif | ||
| 59 | + | ||
| 60 | /* | ||
| 61 | * Add CPU properties with user-facing flags. | ||
| 62 | * | ||
| 63 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj) | ||
| 64 | if (object_property_find(obj, prop->name)) { | ||
| 65 | continue; | ||
| 66 | } | ||
| 67 | + | ||
| 68 | + /* | ||
| 69 | + * Set the default to disabled for every extension | ||
| 70 | + * unknown to KVM and error out if the user attempts | ||
| 71 | + * to enable any of them. | ||
| 72 | + * | ||
| 73 | + * We're giving a pass for non-bool properties since they're | ||
| 74 | + * not related to the availability of extensions and can be | ||
| 75 | + * safely ignored as is. | ||
| 76 | + */ | ||
| 77 | + if (prop->info == &qdev_prop_bool) { | ||
| 78 | + object_property_add(obj, prop->name, "bool", | ||
| 79 | + NULL, cpu_set_cfg_unavailable, | ||
| 80 | + NULL, (void *)prop->name); | ||
| 81 | + continue; | ||
| 82 | + } | ||
| 83 | } | ||
| 84 | #endif | ||
| 85 | qdev_property_add_static(dev, prop); | ||
| 86 | -- | ||
| 87 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | We're now ready to update the multi-letter extensions status for KVM. | ||
| 4 | |||
| 5 | kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation | ||
| 6 | time to verify which user options changes host defaults (via the 'user_set' | ||
| 7 | flag) and tries to write them back to KVM. | ||
| 8 | |||
| 9 | Failure to commit a change to KVM is only ignored in case KVM doesn't | ||
| 10 | know about the extension (-EINVAL error code) and the user wanted to | ||
| 11 | disable the given extension. Otherwise we're going to abort the boot | ||
| 12 | process. | ||
| 13 | |||
| 14 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 15 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | Message-Id: <20230706101738.460804-19-dbarboza@ventanamicro.com> | ||
| 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 19 | --- | ||
| 20 | target/riscv/kvm.c | 27 +++++++++++++++++++++++++++ | ||
| 21 | 1 file changed, 27 insertions(+) | ||
| 22 | |||
| 23 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/target/riscv/kvm.c | ||
| 26 | +++ b/target/riscv/kvm.c | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, | ||
| 28 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); | ||
| 29 | } | ||
| 30 | |||
| 31 | +static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) | ||
| 32 | +{ | ||
| 33 | + CPURISCVState *env = &cpu->env; | ||
| 34 | + uint64_t id, reg; | ||
| 35 | + int i, ret; | ||
| 36 | + | ||
| 37 | + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { | ||
| 38 | + KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; | ||
| 39 | + | ||
| 40 | + if (!multi_ext_cfg->user_set) { | ||
| 41 | + continue; | ||
| 42 | + } | ||
| 43 | + | ||
| 44 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, | ||
| 45 | + multi_ext_cfg->kvm_reg_id); | ||
| 46 | + reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); | ||
| 47 | + ret = kvm_set_one_reg(cs, id, ®); | ||
| 48 | + if (ret != 0) { | ||
| 49 | + error_report("Unable to %s extension %s in KVM, error %d", | ||
| 50 | + reg ? "enable" : "disable", | ||
| 51 | + multi_ext_cfg->name, ret); | ||
| 52 | + exit(EXIT_FAILURE); | ||
| 53 | + } | ||
| 54 | + } | ||
| 55 | +} | ||
| 56 | + | ||
| 57 | static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 58 | { | ||
| 59 | int i; | ||
| 60 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
| 61 | } | ||
| 62 | |||
| 63 | kvm_riscv_update_cpu_misa_ext(cpu, cs); | ||
| 64 | + kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); | ||
| 65 | |||
| 66 | return ret; | ||
| 67 | } | ||
| 68 | -- | ||
| 69 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | There are 2 places in which we need to get a pointer to a certain | ||
| 4 | property of the cpu->cfg struct based on property offset. Next patch | ||
| 5 | will add a couple more. | ||
| 6 | |||
| 7 | Create a helper to avoid repeating this code over and over. | ||
| 8 | |||
| 9 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 10 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 11 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | Message-Id: <20230706101738.460804-20-dbarboza@ventanamicro.com> | ||
| 13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 14 | --- | ||
| 15 | target/riscv/kvm.c | 11 +++++++---- | ||
| 16 | 1 file changed, 7 insertions(+), 4 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/riscv/kvm.c | ||
| 21 | +++ b/target/riscv/kvm.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = { | ||
| 23 | KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), | ||
| 24 | }; | ||
| 25 | |||
| 26 | +static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) | ||
| 27 | +{ | ||
| 28 | + return (void *)&cpu->cfg + kvmcfg->offset; | ||
| 29 | +} | ||
| 30 | + | ||
| 31 | static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, | ||
| 32 | uint32_t val) | ||
| 33 | { | ||
| 34 | - int cpu_cfg_offset = multi_ext->offset; | ||
| 35 | - bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset; | ||
| 36 | + bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); | ||
| 37 | |||
| 38 | *ext_enabled = val; | ||
| 39 | } | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, | ||
| 41 | static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, | ||
| 42 | KVMCPUConfig *multi_ext) | ||
| 43 | { | ||
| 44 | - int cpu_cfg_offset = multi_ext->offset; | ||
| 45 | - bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset; | ||
| 46 | + bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); | ||
| 47 | |||
| 48 | return *ext_enabled; | ||
| 49 | } | ||
| 50 | -- | ||
| 51 | 2.40.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the | ||
| 4 | Linux Kernel will fail to detect the availability of the CBOM/CBOZ | ||
| 5 | extensions, regardless of the contents of the 'riscv,isa' DT prop. | ||
| 6 | |||
| 7 | The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes, | ||
| 8 | so let's expose them as user properties like it is already done with | ||
| 9 | TCG. | ||
| 10 | |||
| 11 | This will also require us to determine proper blocksize values during | ||
| 12 | init() time since the FDT is already created during realize(). We'll | ||
| 13 | take a ride in kvm_riscv_init_multiext_cfg() to do it. Note that we | ||
| 14 | don't need to fetch both cbom and cboz blocksizes every time: check for | ||
| 15 | their parent extensions (icbom and icboz) and only read the blocksizes | ||
| 16 | if needed. | ||
| 17 | |||
| 18 | In contrast with cbom|z_blocksize properties from TCG, the user is not | ||
| 19 | able to set any value that is different from the 'host' value when | ||
| 20 | running KVM. KVM can be particularly harsh dealing with it: a ENOTSUPP | ||
| 21 | can be thrown for the mere attempt of executing kvm_set_one_reg() for | ||
| 22 | these 2 regs. | ||
| 23 | |||
| 24 | Hopefully we don't need to call kvm_set_one_reg() for these regs. | ||
| 25 | We'll check if the user input matches the host value in | ||
| 26 | kvm_cpu_set_cbomz_blksize(), the set() accessor for both blocksize | ||
| 27 | properties. We'll fail fast since it's already known to not be | ||
| 28 | supported. | ||
| 29 | |||
| 30 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
| 31 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 32 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 33 | Message-Id: <20230706101738.460804-21-dbarboza@ventanamicro.com> | ||
| 34 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 35 | --- | ||
| 36 | target/riscv/kvm.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 37 | 1 file changed, 70 insertions(+) | ||
| 38 | |||
| 39 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/riscv/kvm.c | ||
| 42 | +++ b/target/riscv/kvm.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, | ||
| 44 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); | ||
| 45 | } | ||
| 46 | |||
| 47 | +static KVMCPUConfig kvm_cbom_blocksize = { | ||
| 48 | + .name = "cbom_blocksize", | ||
| 49 | + .offset = CPUCFG(cbom_blocksize), | ||
| 50 | + .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) | ||
| 51 | +}; | ||
| 52 | + | ||
| 53 | +static KVMCPUConfig kvm_cboz_blocksize = { | ||
| 54 | + .name = "cboz_blocksize", | ||
| 55 | + .offset = CPUCFG(cboz_blocksize), | ||
| 56 | + .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) | ||
| 57 | +}; | ||
| 58 | + | ||
| 59 | +static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, | ||
| 60 | + const char *name, | ||
| 61 | + void *opaque, Error **errp) | ||
| 62 | +{ | ||
| 63 | + KVMCPUConfig *cbomz_cfg = opaque; | ||
| 64 | + RISCVCPU *cpu = RISCV_CPU(obj); | ||
| 65 | + uint16_t value, *host_val; | ||
| 66 | + | ||
| 67 | + if (!visit_type_uint16(v, name, &value, errp)) { | ||
| 68 | + return; | ||
| 69 | + } | ||
| 70 | + | ||
| 71 | + host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); | ||
| 72 | + | ||
| 73 | + if (value != *host_val) { | ||
| 74 | + error_report("Unable to set %s to a different value than " | ||
| 75 | + "the host (%u)", | ||
| 76 | + cbomz_cfg->name, *host_val); | ||
| 77 | + exit(EXIT_FAILURE); | ||
| 78 | + } | ||
| 79 | + | ||
| 80 | + cbomz_cfg->user_set = true; | ||
| 81 | +} | ||
| 82 | + | ||
| 83 | static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) | ||
| 84 | { | ||
| 85 | CPURISCVState *env = &cpu->env; | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) | ||
| 87 | kvm_cpu_set_multi_ext_cfg, | ||
| 88 | NULL, multi_cfg); | ||
| 89 | } | ||
| 90 | + | ||
| 91 | + object_property_add(cpu_obj, "cbom_blocksize", "uint16", | ||
| 92 | + NULL, kvm_cpu_set_cbomz_blksize, | ||
| 93 | + NULL, &kvm_cbom_blocksize); | ||
| 94 | + | ||
| 95 | + object_property_add(cpu_obj, "cboz_blocksize", "uint16", | ||
| 96 | + NULL, kvm_cpu_set_cbomz_blksize, | ||
| 97 | + NULL, &kvm_cboz_blocksize); | ||
| 98 | } | ||
| 99 | |||
| 100 | static int kvm_riscv_get_regs_core(CPUState *cs) | ||
| 101 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, | ||
| 102 | env->misa_ext = env->misa_ext_mask; | ||
| 103 | } | ||
| 104 | |||
| 105 | +static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, | ||
| 106 | + KVMCPUConfig *cbomz_cfg) | ||
| 107 | +{ | ||
| 108 | + CPURISCVState *env = &cpu->env; | ||
| 109 | + struct kvm_one_reg reg; | ||
| 110 | + int ret; | ||
| 111 | + | ||
| 112 | + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | ||
| 113 | + cbomz_cfg->kvm_reg_id); | ||
| 114 | + reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); | ||
| 115 | + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); | ||
| 116 | + if (ret != 0) { | ||
| 117 | + error_report("Unable to read KVM reg %s, error %d", | ||
| 118 | + cbomz_cfg->name, ret); | ||
| 119 | + exit(EXIT_FAILURE); | ||
| 120 | + } | ||
| 121 | +} | ||
| 122 | + | ||
| 123 | static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 124 | { | ||
| 125 | CPURISCVState *env = &cpu->env; | ||
| 126 | @@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) | ||
| 127 | |||
| 128 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); | ||
| 129 | } | ||
| 130 | + | ||
| 131 | + if (cpu->cfg.ext_icbom) { | ||
| 132 | + kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); | ||
| 133 | + } | ||
| 134 | + | ||
| 135 | + if (cpu->cfg.ext_icboz) { | ||
| 136 | + kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); | ||
| 137 | + } | ||
| 138 | } | ||
| 139 | |||
| 140 | void kvm_riscv_init_user_properties(Object *cpu_obj) | ||
| 141 | -- | ||
| 142 | 2.40.1 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Christoph Müllner <christoph.muellner@vrull.eu> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This adds the documentation to describe what is supported for the | 3 | This patch introduces the RISC-V Zfa extension, which introduces |
| 4 | 'microchip-icicle-kit' machine, and how to boot the machine in QEMU. | 4 | additional floating-point instructions: |
| 5 | * fli (load-immediate) with pre-defined immediates | ||
| 6 | * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) | ||
| 7 | * fround/froundmx (round to integer) | ||
| 8 | * fcvtmod.w.d (Modular Convert-to-Integer) | ||
| 9 | * fmv* to access high bits of float register bigger than XLEN | ||
| 10 | * Quiet comparison instructions (fleq/fltq) | ||
| 5 | 11 | ||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 12 | Zfa defines its instructions in combination with the following extensions: |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 13 | * single-precision floating-point (F) |
| 8 | Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com | 14 | * double-precision floating-point (D) |
| 15 | * quad-precision floating-point (Q) | ||
| 16 | * half-precision floating-point (Zfh) | ||
| 17 | |||
| 18 | Since QEMU does not support the RISC-V quad-precision floating-point | ||
| 19 | ISA extension (Q), this patch does not include the instructions that | ||
| 20 | depend on this extension. All other instructions are included in this | ||
| 21 | patch. | ||
| 22 | |||
| 23 | The Zfa specification can be found here: | ||
| 24 | https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex | ||
| 25 | The Zfa specifciation is frozen and is in public review since May 3, 2023: | ||
| 26 | https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg | ||
| 27 | |||
| 28 | The patch also includes a TCG test for the fcvtmod.w.d instruction. | ||
| 29 | The test cases test for correct results and flag behaviour. | ||
| 30 | Note, that the Zfa specification requires fcvtmod's flag behaviour | ||
| 31 | to be identical to a fcvt with the same operands (which is also | ||
| 32 | tested). | ||
| 33 | |||
| 34 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 35 | Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> | ||
| 36 | Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 37 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 38 | --- |
| 11 | docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++ | 39 | disas/riscv.h | 3 + |
| 12 | docs/system/target-riscv.rst | 1 + | 40 | target/riscv/cpu_cfg.h | 1 + |
| 13 | 2 files changed, 90 insertions(+) | 41 | target/riscv/helper.h | 19 + |
| 14 | create mode 100644 docs/system/riscv/microchip-icicle-kit.rst | 42 | target/riscv/insn32.decode | 26 ++ |
| 43 | disas/riscv.c | 139 ++++++ | ||
| 44 | target/riscv/cpu.c | 8 + | ||
| 45 | target/riscv/fpu_helper.c | 154 +++++++ | ||
| 46 | target/riscv/translate.c | 1 + | ||
| 47 | tests/tcg/riscv64/test-fcvtmod.c | 345 ++++++++++++++ | ||
| 48 | target/riscv/insn_trans/trans_rvzfa.c.inc | 521 ++++++++++++++++++++++ | ||
| 49 | tests/tcg/riscv64/Makefile.target | 6 + | ||
| 50 | 11 files changed, 1223 insertions(+) | ||
| 51 | create mode 100644 tests/tcg/riscv64/test-fcvtmod.c | ||
| 52 | create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc | ||
| 15 | 53 | ||
| 16 | diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst | 54 | diff --git a/disas/riscv.h b/disas/riscv.h |
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/disas/riscv.h | ||
| 57 | +++ b/disas/riscv.h | ||
| 58 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 59 | rv_codec_r_imm2, | ||
| 60 | rv_codec_r2_immhl, | ||
| 61 | rv_codec_r2_imm2_imm5, | ||
| 62 | + rv_codec_fli, | ||
| 63 | } rv_codec; | ||
| 64 | |||
| 65 | /* structures */ | ||
| 66 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 67 | #define rv_fmt_rd_offset "O\t0,o" | ||
| 68 | #define rv_fmt_rd_rs1_rs2 "O\t0,1,2" | ||
| 69 | #define rv_fmt_frd_rs1 "O\t3,1" | ||
| 70 | +#define rv_fmt_frd_rs1_rs2 "O\t3,1,2" | ||
| 71 | #define rv_fmt_frd_frs1 "O\t3,4" | ||
| 72 | #define rv_fmt_rd_frs1 "O\t0,4" | ||
| 73 | #define rv_fmt_rd_frs1_frs2 "O\t0,4,5" | ||
| 74 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 75 | #define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j" | ||
| 76 | #define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j" | ||
| 77 | #define rv_fmt_rd2_imm "O\t0,2,(1),i" | ||
| 78 | +#define rv_fmt_fli "O\t3,h" | ||
| 79 | |||
| 80 | #endif /* DISAS_RISCV_H */ | ||
| 81 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
| 82 | index XXXXXXX..XXXXXXX 100644 | ||
| 83 | --- a/target/riscv/cpu_cfg.h | ||
| 84 | +++ b/target/riscv/cpu_cfg.h | ||
| 85 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
| 86 | bool ext_svpbmt; | ||
| 87 | bool ext_zdinx; | ||
| 88 | bool ext_zawrs; | ||
| 89 | + bool ext_zfa; | ||
| 90 | bool ext_zfbfmin; | ||
| 91 | bool ext_zfh; | ||
| 92 | bool ext_zfhmin; | ||
| 93 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
| 94 | index XXXXXXX..XXXXXXX 100644 | ||
| 95 | --- a/target/riscv/helper.h | ||
| 96 | +++ b/target/riscv/helper.h | ||
| 97 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 98 | DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 99 | DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 100 | DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 101 | +DEF_HELPER_FLAGS_3(fminm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 102 | DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 103 | +DEF_HELPER_FLAGS_3(fmaxm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 104 | DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 105 | DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 106 | +DEF_HELPER_FLAGS_3(fleq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 107 | DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 108 | +DEF_HELPER_FLAGS_3(fltq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 109 | DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 110 | DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 111 | DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 112 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 113 | DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 114 | DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 115 | DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, tl, env, i64) | ||
| 116 | +DEF_HELPER_FLAGS_2(fround_s, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 117 | +DEF_HELPER_FLAGS_2(froundnx_s, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 118 | |||
| 119 | /* Floating Point - Double Precision */ | ||
| 120 | DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 121 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 122 | DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 123 | DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 124 | DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 125 | +DEF_HELPER_FLAGS_3(fminm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 126 | DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 127 | +DEF_HELPER_FLAGS_3(fmaxm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 128 | DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 129 | DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 130 | DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 131 | DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 132 | +DEF_HELPER_FLAGS_3(fleq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 133 | DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 134 | +DEF_HELPER_FLAGS_3(fltq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 135 | DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 136 | DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 137 | +DEF_HELPER_FLAGS_2(fcvtmod_w_d, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 138 | DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 139 | DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 140 | DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64) | ||
| 141 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 142 | DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 143 | DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 144 | DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) | ||
| 145 | +DEF_HELPER_FLAGS_2(fround_d, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 146 | +DEF_HELPER_FLAGS_2(froundnx_d, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 147 | |||
| 148 | /* Bitmanip */ | ||
| 149 | DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) | ||
| 150 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 151 | DEF_HELPER_FLAGS_3(fmul_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 152 | DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 153 | DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 154 | +DEF_HELPER_FLAGS_3(fminm_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 155 | DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 156 | +DEF_HELPER_FLAGS_3(fmaxm_h, TCG_CALL_NO_RWG, i64, env, i64, i64) | ||
| 157 | DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 158 | DEF_HELPER_FLAGS_3(fle_h, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 159 | +DEF_HELPER_FLAGS_3(fleq_h, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 160 | DEF_HELPER_FLAGS_3(flt_h, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 161 | +DEF_HELPER_FLAGS_3(fltq_h, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 162 | DEF_HELPER_FLAGS_3(feq_h, TCG_CALL_NO_RWG, tl, env, i64, i64) | ||
| 163 | DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 164 | DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64) | ||
| 165 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 166 | DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 167 | DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl) | ||
| 168 | DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64) | ||
| 169 | +DEF_HELPER_FLAGS_2(fround_h, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 170 | +DEF_HELPER_FLAGS_2(froundnx_h, TCG_CALL_NO_RWG_SE, i64, env, i64) | ||
| 171 | |||
| 172 | /* Cache-block operations */ | ||
| 173 | DEF_HELPER_2(cbo_clean_flush, void, env, tl) | ||
| 174 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
| 175 | index XXXXXXX..XXXXXXX 100644 | ||
| 176 | --- a/target/riscv/insn32.decode | ||
| 177 | +++ b/target/riscv/insn32.decode | ||
| 178 | @@ -XXX,XX +XXX,XX @@ binvi 01101. ........... 001 ..... 0010011 @sh | ||
| 179 | bset 0010100 .......... 001 ..... 0110011 @r | ||
| 180 | bseti 00101. ........... 001 ..... 0010011 @sh | ||
| 181 | |||
| 182 | +# *** Zfa Standard Extension *** | ||
| 183 | +fli_s 1111000 00001 ..... 000 ..... 1010011 @r2 | ||
| 184 | +fli_d 1111001 00001 ..... 000 ..... 1010011 @r2 | ||
| 185 | +fli_h 1111010 00001 ..... 000 ..... 1010011 @r2 | ||
| 186 | +fminm_s 0010100 ..... ..... 010 ..... 1010011 @r | ||
| 187 | +fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r | ||
| 188 | +fminm_d 0010101 ..... ..... 010 ..... 1010011 @r | ||
| 189 | +fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r | ||
| 190 | +fminm_h 0010110 ..... ..... 010 ..... 1010011 @r | ||
| 191 | +fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r | ||
| 192 | +fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm | ||
| 193 | +froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm | ||
| 194 | +fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm | ||
| 195 | +froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm | ||
| 196 | +fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm | ||
| 197 | +froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm | ||
| 198 | +fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2 | ||
| 199 | +fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2 | ||
| 200 | +fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r | ||
| 201 | +fleq_s 1010000 ..... ..... 100 ..... 1010011 @r | ||
| 202 | +fltq_s 1010000 ..... ..... 101 ..... 1010011 @r | ||
| 203 | +fleq_d 1010001 ..... ..... 100 ..... 1010011 @r | ||
| 204 | +fltq_d 1010001 ..... ..... 101 ..... 1010011 @r | ||
| 205 | +fleq_h 1010010 ..... ..... 100 ..... 1010011 @r | ||
| 206 | +fltq_h 1010010 ..... ..... 101 ..... 1010011 @r | ||
| 207 | + | ||
| 208 | # *** RV32 Zfh Extension *** | ||
| 209 | flh ............ ..... 001 ..... 0000111 @i | ||
| 210 | fsh ....... ..... ..... 001 ..... 0100111 @s | ||
| 211 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 212 | index XXXXXXX..XXXXXXX 100644 | ||
| 213 | --- a/disas/riscv.c | ||
| 214 | +++ b/disas/riscv.c | ||
| 215 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 216 | rv_op_fsh = 798, | ||
| 217 | rv_op_fmv_h_x = 799, | ||
| 218 | rv_op_fmv_x_h = 800, | ||
| 219 | + rv_op_fli_s = 801, | ||
| 220 | + rv_op_fli_d = 802, | ||
| 221 | + rv_op_fli_q = 803, | ||
| 222 | + rv_op_fli_h = 804, | ||
| 223 | + rv_op_fminm_s = 805, | ||
| 224 | + rv_op_fmaxm_s = 806, | ||
| 225 | + rv_op_fminm_d = 807, | ||
| 226 | + rv_op_fmaxm_d = 808, | ||
| 227 | + rv_op_fminm_q = 809, | ||
| 228 | + rv_op_fmaxm_q = 810, | ||
| 229 | + rv_op_fminm_h = 811, | ||
| 230 | + rv_op_fmaxm_h = 812, | ||
| 231 | + rv_op_fround_s = 813, | ||
| 232 | + rv_op_froundnx_s = 814, | ||
| 233 | + rv_op_fround_d = 815, | ||
| 234 | + rv_op_froundnx_d = 816, | ||
| 235 | + rv_op_fround_q = 817, | ||
| 236 | + rv_op_froundnx_q = 818, | ||
| 237 | + rv_op_fround_h = 819, | ||
| 238 | + rv_op_froundnx_h = 820, | ||
| 239 | + rv_op_fcvtmod_w_d = 821, | ||
| 240 | + rv_op_fmvh_x_d = 822, | ||
| 241 | + rv_op_fmvp_d_x = 823, | ||
| 242 | + rv_op_fmvh_x_q = 824, | ||
| 243 | + rv_op_fmvp_q_x = 825, | ||
| 244 | + rv_op_fleq_s = 826, | ||
| 245 | + rv_op_fltq_s = 827, | ||
| 246 | + rv_op_fleq_d = 828, | ||
| 247 | + rv_op_fltq_d = 829, | ||
| 248 | + rv_op_fleq_q = 830, | ||
| 249 | + rv_op_fltq_q = 831, | ||
| 250 | + rv_op_fleq_h = 832, | ||
| 251 | + rv_op_fltq_h = 833, | ||
| 252 | } rv_op; | ||
| 253 | |||
| 254 | /* register names */ | ||
| 255 | @@ -XXX,XX +XXX,XX @@ static const char rv_vreg_name_sym[32][4] = { | ||
| 256 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" | ||
| 257 | }; | ||
| 258 | |||
| 259 | +/* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). | ||
| 260 | + * The constants use the hex floating-point literal representation | ||
| 261 | + * that is printed when using the printf %a format specifier, | ||
| 262 | + * which matches the output that is generated by the disassembler. | ||
| 263 | + */ | ||
| 264 | +static const char rv_fli_name_const[32][9] = | ||
| 265 | +{ | ||
| 266 | + "0x1p+0", "min", "0x1p-16", "0x1p-15", | ||
| 267 | + "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", | ||
| 268 | + "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", | ||
| 269 | + "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", | ||
| 270 | + "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", | ||
| 271 | + "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", | ||
| 272 | + "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", | ||
| 273 | + "0x1p+15", "0x1p+16", "inf", "nan" | ||
| 274 | +}; | ||
| 275 | + | ||
| 276 | /* pseudo-instruction constraints */ | ||
| 277 | |||
| 278 | static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; | ||
| 279 | @@ -XXX,XX +XXX,XX @@ const rv_opcode_data rvi_opcode_data[] = { | ||
| 280 | { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, | ||
| 281 | { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, | ||
| 282 | { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 283 | + { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, | ||
| 284 | + { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, | ||
| 285 | + { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, | ||
| 286 | + { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, | ||
| 287 | + { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 288 | + { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 289 | + { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 290 | + { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 291 | + { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 292 | + { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 293 | + { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 294 | + { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 295 | + { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 296 | + { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 297 | + { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 298 | + { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 299 | + { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 300 | + { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 301 | + { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 302 | + { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, | ||
| 303 | + { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, | ||
| 304 | + { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 305 | + { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 306 | + { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, | ||
| 307 | + { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 308 | + { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 309 | + { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 310 | + { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 311 | + { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 312 | + { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 313 | + { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 314 | + { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 315 | + { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, | ||
| 316 | }; | ||
| 317 | |||
| 318 | /* CSR names */ | ||
| 319 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 320 | switch ((inst >> 12) & 0b111) { | ||
| 321 | case 0: op = rv_op_fmin_s; break; | ||
| 322 | case 1: op = rv_op_fmax_s; break; | ||
| 323 | + case 2: op = rv_op_fminm_s; break; | ||
| 324 | + case 3: op = rv_op_fmaxm_s; break; | ||
| 325 | } | ||
| 326 | break; | ||
| 327 | case 21: | ||
| 328 | switch ((inst >> 12) & 0b111) { | ||
| 329 | case 0: op = rv_op_fmin_d; break; | ||
| 330 | case 1: op = rv_op_fmax_d; break; | ||
| 331 | + case 2: op = rv_op_fminm_d; break; | ||
| 332 | + case 3: op = rv_op_fmaxm_d; break; | ||
| 333 | + } | ||
| 334 | + break; | ||
| 335 | + case 22: | ||
| 336 | + switch (((inst >> 12) & 0b111)) { | ||
| 337 | + case 2: op = rv_op_fminm_h; break; | ||
| 338 | + case 3: op = rv_op_fmaxm_h; break; | ||
| 339 | } | ||
| 340 | break; | ||
| 341 | case 23: | ||
| 342 | switch ((inst >> 12) & 0b111) { | ||
| 343 | case 0: op = rv_op_fmin_q; break; | ||
| 344 | case 1: op = rv_op_fmax_q; break; | ||
| 345 | + case 2: op = rv_op_fminm_q; break; | ||
| 346 | + case 3: op = rv_op_fmaxm_q; break; | ||
| 347 | } | ||
| 348 | break; | ||
| 349 | case 32: | ||
| 350 | switch ((inst >> 20) & 0b11111) { | ||
| 351 | case 1: op = rv_op_fcvt_s_d; break; | ||
| 352 | case 3: op = rv_op_fcvt_s_q; break; | ||
| 353 | + case 4: op = rv_op_fround_s; break; | ||
| 354 | + case 5: op = rv_op_froundnx_s; break; | ||
| 355 | case 6: op = rv_op_fcvt_s_bf16; break; | ||
| 356 | } | ||
| 357 | break; | ||
| 358 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 359 | switch ((inst >> 20) & 0b11111) { | ||
| 360 | case 0: op = rv_op_fcvt_d_s; break; | ||
| 361 | case 3: op = rv_op_fcvt_d_q; break; | ||
| 362 | + case 4: op = rv_op_fround_d; break; | ||
| 363 | + case 5: op = rv_op_froundnx_d; break; | ||
| 364 | } | ||
| 365 | break; | ||
| 366 | case 34: | ||
| 367 | switch (((inst >> 20) & 0b11111)) { | ||
| 368 | + case 4: op = rv_op_fround_h; break; | ||
| 369 | + case 5: op = rv_op_froundnx_h; break; | ||
| 370 | case 8: op = rv_op_fcvt_bf16_s; break; | ||
| 371 | } | ||
| 372 | break; | ||
| 373 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 374 | switch ((inst >> 20) & 0b11111) { | ||
| 375 | case 0: op = rv_op_fcvt_q_s; break; | ||
| 376 | case 1: op = rv_op_fcvt_q_d; break; | ||
| 377 | + case 4: op = rv_op_fround_q; break; | ||
| 378 | + case 5: op = rv_op_froundnx_q; break; | ||
| 379 | } | ||
| 380 | break; | ||
| 381 | case 44: | ||
| 382 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 383 | case 0: op = rv_op_fle_s; break; | ||
| 384 | case 1: op = rv_op_flt_s; break; | ||
| 385 | case 2: op = rv_op_feq_s; break; | ||
| 386 | + case 4: op = rv_op_fleq_s; break; | ||
| 387 | + case 5: op = rv_op_fltq_s; break; | ||
| 388 | } | ||
| 389 | break; | ||
| 390 | case 81: | ||
| 391 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 392 | case 0: op = rv_op_fle_d; break; | ||
| 393 | case 1: op = rv_op_flt_d; break; | ||
| 394 | case 2: op = rv_op_feq_d; break; | ||
| 395 | + case 4: op = rv_op_fleq_d; break; | ||
| 396 | + case 5: op = rv_op_fltq_d; break; | ||
| 397 | + } | ||
| 398 | + break; | ||
| 399 | + case 82: | ||
| 400 | + switch (((inst >> 12) & 0b111)) { | ||
| 401 | + case 4: op = rv_op_fleq_h; break; | ||
| 402 | + case 5: op = rv_op_fltq_h; break; | ||
| 403 | } | ||
| 404 | break; | ||
| 405 | case 83: | ||
| 406 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 407 | case 0: op = rv_op_fle_q; break; | ||
| 408 | case 1: op = rv_op_flt_q; break; | ||
| 409 | case 2: op = rv_op_feq_q; break; | ||
| 410 | + case 4: op = rv_op_fleq_q; break; | ||
| 411 | + case 5: op = rv_op_fltq_q; break; | ||
| 412 | + } | ||
| 413 | + break; | ||
| 414 | + case 89: | ||
| 415 | + switch (((inst >> 12) & 0b111)) { | ||
| 416 | + case 0: op = rv_op_fmvp_d_x; break; | ||
| 417 | + } | ||
| 418 | + break; | ||
| 419 | + case 91: | ||
| 420 | + switch (((inst >> 12) & 0b111)) { | ||
| 421 | + case 0: op = rv_op_fmvp_q_x; break; | ||
| 422 | } | ||
| 423 | break; | ||
| 424 | case 96: | ||
| 425 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 426 | case 1: op = rv_op_fcvt_wu_d; break; | ||
| 427 | case 2: op = rv_op_fcvt_l_d; break; | ||
| 428 | case 3: op = rv_op_fcvt_lu_d; break; | ||
| 429 | + case 8: op = rv_op_fcvtmod_w_d; break; | ||
| 430 | } | ||
| 431 | break; | ||
| 432 | case 99: | ||
| 433 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 434 | ((inst >> 12) & 0b00000111)) { | ||
| 435 | case 0: op = rv_op_fmv_x_d; break; | ||
| 436 | case 1: op = rv_op_fclass_d; break; | ||
| 437 | + case 8: op = rv_op_fmvh_x_d; break; | ||
| 438 | } | ||
| 439 | break; | ||
| 440 | case 114: | ||
| 441 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 442 | ((inst >> 12) & 0b00000111)) { | ||
| 443 | case 0: op = rv_op_fmv_x_q; break; | ||
| 444 | case 1: op = rv_op_fclass_q; break; | ||
| 445 | + case 8: op = rv_op_fmvh_x_q; break; | ||
| 446 | } | ||
| 447 | break; | ||
| 448 | case 120: | ||
| 449 | switch (((inst >> 17) & 0b11111000) | | ||
| 450 | ((inst >> 12) & 0b00000111)) { | ||
| 451 | case 0: op = rv_op_fmv_s_x; break; | ||
| 452 | + case 8: op = rv_op_fli_s; break; | ||
| 453 | } | ||
| 454 | break; | ||
| 455 | case 121: | ||
| 456 | switch (((inst >> 17) & 0b11111000) | | ||
| 457 | ((inst >> 12) & 0b00000111)) { | ||
| 458 | case 0: op = rv_op_fmv_d_x; break; | ||
| 459 | + case 8: op = rv_op_fli_d; break; | ||
| 460 | } | ||
| 461 | break; | ||
| 462 | case 122: | ||
| 463 | switch (((inst >> 17) & 0b11111000) | | ||
| 464 | ((inst >> 12) & 0b00000111)) { | ||
| 465 | case 0: op = rv_op_fmv_h_x; break; | ||
| 466 | + case 8: op = rv_op_fli_h; break; | ||
| 467 | } | ||
| 468 | break; | ||
| 469 | case 123: | ||
| 470 | switch (((inst >> 17) & 0b11111000) | | ||
| 471 | ((inst >> 12) & 0b00000111)) { | ||
| 472 | case 0: op = rv_op_fmv_q_x; break; | ||
| 473 | + case 8: op = rv_op_fli_q; break; | ||
| 474 | } | ||
| 475 | break; | ||
| 476 | } | ||
| 477 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) | ||
| 478 | break; | ||
| 479 | case rv_codec_zcmt_jt: | ||
| 480 | dec->imm = operand_tbl_index(inst); | ||
| 481 | + break; | ||
| 482 | + case rv_codec_fli: | ||
| 483 | + dec->rd = operand_rd(inst); | ||
| 484 | + dec->imm = operand_rs1(inst); | ||
| 485 | break; | ||
| 486 | case rv_codec_r2_imm5: | ||
| 487 | dec->rd = operand_rd(inst); | ||
| 488 | @@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 489 | append(buf, tmp, buflen); | ||
| 490 | break; | ||
| 491 | } | ||
| 492 | + case 'h': | ||
| 493 | + append(buf, rv_fli_name_const[dec->imm], buflen); | ||
| 494 | + break; | ||
| 495 | default: | ||
| 496 | break; | ||
| 497 | } | ||
| 498 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 499 | index XXXXXXX..XXXXXXX 100644 | ||
| 500 | --- a/target/riscv/cpu.c | ||
| 501 | +++ b/target/riscv/cpu.c | ||
| 502 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
| 503 | ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), | ||
| 504 | ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), | ||
| 505 | ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), | ||
| 506 | + ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), | ||
| 507 | ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), | ||
| 508 | ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), | ||
| 509 | ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), | ||
| 510 | @@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj) | ||
| 511 | set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); | ||
| 512 | env->priv_ver = PRIV_VERSION_1_11_0; | ||
| 513 | |||
| 514 | + cpu->cfg.ext_zfa = true; | ||
| 515 | cpu->cfg.ext_zfh = true; | ||
| 516 | cpu->cfg.mmu = true; | ||
| 517 | cpu->cfg.ext_xtheadba = true; | ||
| 518 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
| 519 | return; | ||
| 520 | } | ||
| 521 | |||
| 522 | + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { | ||
| 523 | + error_setg(errp, "Zfa extension requires F extension"); | ||
| 524 | + return; | ||
| 525 | + } | ||
| 526 | + | ||
| 527 | if (cpu->cfg.ext_zfh) { | ||
| 528 | cpu->cfg.ext_zfhmin = true; | ||
| 529 | } | ||
| 530 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
| 531 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | ||
| 532 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), | ||
| 533 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), | ||
| 534 | + DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), | ||
| 535 | DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), | ||
| 536 | DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), | ||
| 537 | DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), | ||
| 538 | diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c | ||
| 539 | index XXXXXXX..XXXXXXX 100644 | ||
| 540 | --- a/target/riscv/fpu_helper.c | ||
| 541 | +++ b/target/riscv/fpu_helper.c | ||
| 542 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 543 | float32_minimum_number(frs1, frs2, &env->fp_status)); | ||
| 544 | } | ||
| 545 | |||
| 546 | +uint64_t helper_fminm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 547 | +{ | ||
| 548 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 549 | + float32 frs2 = check_nanbox_s(env, rs2); | ||
| 550 | + float32 ret = float32_min(frs1, frs2, &env->fp_status); | ||
| 551 | + return nanbox_s(env, ret); | ||
| 552 | +} | ||
| 553 | + | ||
| 554 | uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 555 | { | ||
| 556 | float32 frs1 = check_nanbox_s(env, rs1); | ||
| 557 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 558 | float32_maximum_number(frs1, frs2, &env->fp_status)); | ||
| 559 | } | ||
| 560 | |||
| 561 | +uint64_t helper_fmaxm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 562 | +{ | ||
| 563 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 564 | + float32 frs2 = check_nanbox_s(env, rs2); | ||
| 565 | + float32 ret = float32_max(frs1, frs2, &env->fp_status); | ||
| 566 | + return nanbox_s(env, ret); | ||
| 567 | +} | ||
| 568 | + | ||
| 569 | uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) | ||
| 570 | { | ||
| 571 | float32 frs1 = check_nanbox_s(env, rs1); | ||
| 572 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 573 | return float32_le(frs1, frs2, &env->fp_status); | ||
| 574 | } | ||
| 575 | |||
| 576 | +target_ulong helper_fleq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 577 | +{ | ||
| 578 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 579 | + float32 frs2 = check_nanbox_s(env, rs2); | ||
| 580 | + return float32_le_quiet(frs1, frs2, &env->fp_status); | ||
| 581 | +} | ||
| 582 | + | ||
| 583 | target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 584 | { | ||
| 585 | float32 frs1 = check_nanbox_s(env, rs1); | ||
| 586 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 587 | return float32_lt(frs1, frs2, &env->fp_status); | ||
| 588 | } | ||
| 589 | |||
| 590 | +target_ulong helper_fltq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 591 | +{ | ||
| 592 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 593 | + float32 frs2 = check_nanbox_s(env, rs2); | ||
| 594 | + return float32_lt_quiet(frs1, frs2, &env->fp_status); | ||
| 595 | +} | ||
| 596 | + | ||
| 597 | target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 598 | { | ||
| 599 | float32 frs1 = check_nanbox_s(env, rs1); | ||
| 600 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fclass_s(CPURISCVState *env, uint64_t rs1) | ||
| 601 | return fclass_s(frs1); | ||
| 602 | } | ||
| 603 | |||
| 604 | +uint64_t helper_fround_s(CPURISCVState *env, uint64_t rs1) | ||
| 605 | +{ | ||
| 606 | + float_status *fs = &env->fp_status; | ||
| 607 | + uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact; | ||
| 608 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 609 | + | ||
| 610 | + frs1 = float32_round_to_int(frs1, fs); | ||
| 611 | + | ||
| 612 | + /* Restore the original NX flag. */ | ||
| 613 | + uint16_t flags = get_float_exception_flags(fs); | ||
| 614 | + flags &= ~float_flag_inexact; | ||
| 615 | + flags |= nx_old; | ||
| 616 | + set_float_exception_flags(flags, fs); | ||
| 617 | + | ||
| 618 | + return nanbox_s(env, frs1); | ||
| 619 | +} | ||
| 620 | + | ||
| 621 | +uint64_t helper_froundnx_s(CPURISCVState *env, uint64_t rs1) | ||
| 622 | +{ | ||
| 623 | + float32 frs1 = check_nanbox_s(env, rs1); | ||
| 624 | + frs1 = float32_round_to_int(frs1, &env->fp_status); | ||
| 625 | + return nanbox_s(env, frs1); | ||
| 626 | +} | ||
| 627 | + | ||
| 628 | uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 629 | { | ||
| 630 | return float64_add(frs1, frs2, &env->fp_status); | ||
| 631 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 632 | float64_minimum_number(frs1, frs2, &env->fp_status); | ||
| 633 | } | ||
| 634 | |||
| 635 | +uint64_t helper_fminm_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 636 | +{ | ||
| 637 | + return float64_min(frs1, frs2, &env->fp_status); | ||
| 638 | +} | ||
| 639 | + | ||
| 640 | uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 641 | { | ||
| 642 | return env->priv_ver < PRIV_VERSION_1_11_0 ? | ||
| 643 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 644 | float64_maximum_number(frs1, frs2, &env->fp_status); | ||
| 645 | } | ||
| 646 | |||
| 647 | +uint64_t helper_fmaxm_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 648 | +{ | ||
| 649 | + return float64_max(frs1, frs2, &env->fp_status); | ||
| 650 | +} | ||
| 651 | + | ||
| 652 | uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) | ||
| 653 | { | ||
| 654 | return nanbox_s(env, float64_to_float32(rs1, &env->fp_status)); | ||
| 655 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 656 | return float64_le(frs1, frs2, &env->fp_status); | ||
| 657 | } | ||
| 658 | |||
| 659 | +target_ulong helper_fleq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 660 | +{ | ||
| 661 | + return float64_le_quiet(frs1, frs2, &env->fp_status); | ||
| 662 | +} | ||
| 663 | + | ||
| 664 | target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 665 | { | ||
| 666 | return float64_lt(frs1, frs2, &env->fp_status); | ||
| 667 | } | ||
| 668 | |||
| 669 | +target_ulong helper_fltq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 670 | +{ | ||
| 671 | + return float64_lt_quiet(frs1, frs2, &env->fp_status); | ||
| 672 | +} | ||
| 673 | + | ||
| 674 | target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | ||
| 675 | { | ||
| 676 | return float64_eq_quiet(frs1, frs2, &env->fp_status); | ||
| 677 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1) | ||
| 678 | return float64_to_int32(frs1, &env->fp_status); | ||
| 679 | } | ||
| 680 | |||
| 681 | +uint64_t helper_fcvtmod_w_d(CPURISCVState *env, uint64_t value) | ||
| 682 | +{ | ||
| 683 | + return float64_to_int32_modulo(value, float_round_to_zero, &env->fp_status); | ||
| 684 | +} | ||
| 685 | + | ||
| 686 | target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1) | ||
| 687 | { | ||
| 688 | return (int32_t)float64_to_uint32(frs1, &env->fp_status); | ||
| 689 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fclass_d(uint64_t frs1) | ||
| 690 | return fclass_d(frs1); | ||
| 691 | } | ||
| 692 | |||
| 693 | +uint64_t helper_fround_d(CPURISCVState *env, uint64_t frs1) | ||
| 694 | +{ | ||
| 695 | + float_status *fs = &env->fp_status; | ||
| 696 | + uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact; | ||
| 697 | + | ||
| 698 | + frs1 = float64_round_to_int(frs1, fs); | ||
| 699 | + | ||
| 700 | + /* Restore the original NX flag. */ | ||
| 701 | + uint16_t flags = get_float_exception_flags(fs); | ||
| 702 | + flags &= ~float_flag_inexact; | ||
| 703 | + flags |= nx_old; | ||
| 704 | + set_float_exception_flags(flags, fs); | ||
| 705 | + | ||
| 706 | + return frs1; | ||
| 707 | +} | ||
| 708 | + | ||
| 709 | +uint64_t helper_froundnx_d(CPURISCVState *env, uint64_t frs1) | ||
| 710 | +{ | ||
| 711 | + return float64_round_to_int(frs1, &env->fp_status); | ||
| 712 | +} | ||
| 713 | + | ||
| 714 | uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 715 | { | ||
| 716 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 717 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 718 | float16_minimum_number(frs1, frs2, &env->fp_status)); | ||
| 719 | } | ||
| 720 | |||
| 721 | +uint64_t helper_fminm_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 722 | +{ | ||
| 723 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 724 | + float16 frs2 = check_nanbox_h(env, rs2); | ||
| 725 | + float16 ret = float16_min(frs1, frs2, &env->fp_status); | ||
| 726 | + return nanbox_h(env, ret); | ||
| 727 | +} | ||
| 728 | + | ||
| 729 | uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 730 | { | ||
| 731 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 732 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 733 | float16_maximum_number(frs1, frs2, &env->fp_status)); | ||
| 734 | } | ||
| 735 | |||
| 736 | +uint64_t helper_fmaxm_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 737 | +{ | ||
| 738 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 739 | + float16 frs2 = check_nanbox_h(env, rs2); | ||
| 740 | + float16 ret = float16_max(frs1, frs2, &env->fp_status); | ||
| 741 | + return nanbox_h(env, ret); | ||
| 742 | +} | ||
| 743 | + | ||
| 744 | uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) | ||
| 745 | { | ||
| 746 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 747 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 748 | return float16_le(frs1, frs2, &env->fp_status); | ||
| 749 | } | ||
| 750 | |||
| 751 | +target_ulong helper_fleq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 752 | +{ | ||
| 753 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 754 | + float16 frs2 = check_nanbox_h(env, rs2); | ||
| 755 | + return float16_le_quiet(frs1, frs2, &env->fp_status); | ||
| 756 | +} | ||
| 757 | + | ||
| 758 | target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 759 | { | ||
| 760 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 761 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 762 | return float16_lt(frs1, frs2, &env->fp_status); | ||
| 763 | } | ||
| 764 | |||
| 765 | +target_ulong helper_fltq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 766 | +{ | ||
| 767 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 768 | + float16 frs2 = check_nanbox_h(env, rs2); | ||
| 769 | + return float16_lt_quiet(frs1, frs2, &env->fp_status); | ||
| 770 | +} | ||
| 771 | + | ||
| 772 | target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | ||
| 773 | { | ||
| 774 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 775 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_fclass_h(CPURISCVState *env, uint64_t rs1) | ||
| 776 | return fclass_h(frs1); | ||
| 777 | } | ||
| 778 | |||
| 779 | +uint64_t helper_fround_h(CPURISCVState *env, uint64_t rs1) | ||
| 780 | +{ | ||
| 781 | + float_status *fs = &env->fp_status; | ||
| 782 | + uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact; | ||
| 783 | + float16 frs1 = check_nanbox_h(env, rs1); | ||
| 784 | + | ||
| 785 | + frs1 = float16_round_to_int(frs1, fs); | ||
| 786 | + | ||
| 787 | + /* Restore the original NX flag. */ | ||
| 788 | + uint16_t flags = get_float_exception_flags(fs); | ||
| 789 | + flags &= ~float_flag_inexact; | ||
| 790 | + flags |= nx_old; | ||
| 791 | + set_float_exception_flags(flags, fs); | ||
| 792 | + | ||
| 793 | + return nanbox_h(env, frs1); | ||
| 794 | +} | ||
| 795 | + | ||
| 796 | +uint64_t helper_froundnx_h(CPURISCVState *env, uint64_t rs1) | ||
| 797 | +{ | ||
| 798 | + float16 frs1 = check_nanbox_s(env, rs1); | ||
| 799 | + frs1 = float16_round_to_int(frs1, &env->fp_status); | ||
| 800 | + return nanbox_h(env, frs1); | ||
| 801 | +} | ||
| 802 | + | ||
| 803 | target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) | ||
| 804 | { | ||
| 805 | float16 frs1 = check_nanbox_h(env, rs1); | ||
| 806 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
| 807 | index XXXXXXX..XXXXXXX 100644 | ||
| 808 | --- a/target/riscv/translate.c | ||
| 809 | +++ b/target/riscv/translate.c | ||
| 810 | @@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) | ||
| 811 | #include "insn_trans/trans_rvzicond.c.inc" | ||
| 812 | #include "insn_trans/trans_rvzawrs.c.inc" | ||
| 813 | #include "insn_trans/trans_rvzicbo.c.inc" | ||
| 814 | +#include "insn_trans/trans_rvzfa.c.inc" | ||
| 815 | #include "insn_trans/trans_rvzfh.c.inc" | ||
| 816 | #include "insn_trans/trans_rvk.c.inc" | ||
| 817 | #include "insn_trans/trans_privileged.c.inc" | ||
| 818 | diff --git a/tests/tcg/riscv64/test-fcvtmod.c b/tests/tcg/riscv64/test-fcvtmod.c | ||
| 17 | new file mode 100644 | 819 | new file mode 100644 |
| 18 | index XXXXXXX..XXXXXXX | 820 | index XXXXXXX..XXXXXXX |
| 19 | --- /dev/null | 821 | --- /dev/null |
| 20 | +++ b/docs/system/riscv/microchip-icicle-kit.rst | 822 | +++ b/tests/tcg/riscv64/test-fcvtmod.c |
| 21 | @@ -XXX,XX +XXX,XX @@ | 823 | @@ -XXX,XX +XXX,XX @@ |
| 22 | +Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``) | 824 | +#include <stdio.h> |
| 23 | +============================================================= | 825 | +#include <stddef.h> |
| 24 | + | 826 | +#include <stdint.h> |
| 25 | +Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one | 827 | + |
| 26 | +SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. | 828 | +#define FFLAG_NX_SHIFT 0 /* inexact */ |
| 27 | + | 829 | +#define FFLAG_UF_SHIFT 1 /* underflow */ |
| 28 | +For more details about Microchip PolarFire SoC, please see: | 830 | +#define FFLAG_OF_SHIFT 2 /* overflow */ |
| 29 | +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga | 831 | +#define FFLAG_DZ_SHIFT 3 /* divide by zero */ |
| 30 | + | 832 | +#define FFLAG_NV_SHIFT 4 /* invalid operation */ |
| 31 | +The Icicle Kit board information can be found here: | 833 | + |
| 32 | +https://www.microsemi.com/existing-parts/parts/152514 | 834 | +#define FFLAG_NV (1UL << FFLAG_NV_SHIFT) |
| 33 | + | 835 | +#define FFLAG_DZ (1UL << FFLAG_DZ_SHIFT) |
| 34 | +Supported devices | 836 | +#define FFLAG_OF (1UL << FFLAG_OF_SHIFT) |
| 35 | +----------------- | 837 | +#define FFLAG_UF (1UL << FFLAG_UF_SHIFT) |
| 36 | + | 838 | +#define FFLAG_NX (1UL << FFLAG_NX_SHIFT) |
| 37 | +The ``microchip-icicle-kit`` machine supports the following devices: | 839 | + |
| 38 | + | 840 | +typedef struct fp64_fcvt_fcvtmod_testcase { |
| 39 | + * 1 E51 core | 841 | + const char* name; |
| 40 | + * 4 U54 cores | 842 | + union { |
| 41 | + * Core Level Interruptor (CLINT) | 843 | + uint64_t inp_lu; |
| 42 | + * Platform-Level Interrupt Controller (PLIC) | 844 | + double inp_lf; |
| 43 | + * L2 Loosely Integrated Memory (L2-LIM) | 845 | + }; |
| 44 | + * DDR memory controller | 846 | + uint64_t exp_fcvt; |
| 45 | + * 5 MMUARTs | 847 | + uint8_t exp_fcvt_fflags; |
| 46 | + * 1 DMA controller | 848 | + uint64_t exp_fcvtmod; |
| 47 | + * 2 GEM Ethernet controllers | 849 | + uint8_t exp_fcvtmod_fflags; |
| 48 | + * 1 SDHC storage controller | 850 | +} fp64_fcvt_fcvtmod_testcase_t; |
| 49 | + | 851 | + |
| 50 | +Boot options | 852 | +void print_fflags(uint8_t fflags) |
| 51 | +------------ | 853 | +{ |
| 52 | + | 854 | + int set = 0; |
| 53 | +The ``microchip-icicle-kit`` machine can start using the standard -bios | 855 | + |
| 54 | +functionality for loading its BIOS image, aka Hart Software Services (HSS_). | 856 | + if (fflags == 0) { |
| 55 | +HSS loads the second stage bootloader U-Boot from an SD card. It does not | 857 | + printf("-"); |
| 56 | +support direct kernel loading via the -kernel option. One has to load kernel | 858 | + return; |
| 57 | +from U-Boot. | 859 | + } |
| 58 | + | 860 | + |
| 59 | +The memory is set to 1537 MiB by default which is the minimum required high | 861 | + if (fflags & FFLAG_NV) { |
| 60 | +memory size by HSS. A sanity check on ram size is performed in the machine | 862 | + printf("%sFFLAG_NV", set ? " | " : ""); |
| 61 | +init routine to prompt user to increase the RAM size to > 1537 MiB when less | 863 | + set = 1; |
| 62 | +than 1537 MiB ram is detected. | 864 | + } |
| 63 | + | 865 | + if (fflags & FFLAG_DZ) { |
| 64 | +Boot the machine | 866 | + printf("%sFFLAG_DZ", set ? " | " : ""); |
| 65 | +---------------- | 867 | + set = 1; |
| 66 | + | 868 | + } |
| 67 | +HSS 2020.12 release is tested at the time of writing. To build an HSS image | 869 | + if (fflags & FFLAG_OF) { |
| 68 | +that can be booted by the ``microchip-icicle-kit`` machine, type the following | 870 | + printf("%sFFLAG_OF", set ? " | " : ""); |
| 69 | +in the HSS source tree: | 871 | + set = 1; |
| 70 | + | 872 | + } |
| 71 | +.. code-block:: bash | 873 | + if (fflags & FFLAG_UF) { |
| 72 | + | 874 | + printf("%sFFLAG_UF", set ? " | " : ""); |
| 73 | + $ export CROSS_COMPILE=riscv64-linux- | 875 | + set = 1; |
| 74 | + $ cp boards/mpfs-icicle-kit-es/def_config .config | 876 | + } |
| 75 | + $ make BOARD=mpfs-icicle-kit-es | 877 | + if (fflags & FFLAG_NX) { |
| 76 | + | 878 | + printf("%sFFLAG_NX", set ? " | " : ""); |
| 77 | +Download the official SD card image released by Microchip and prepare it for | 879 | + set = 1; |
| 78 | +QEMU usage: | 880 | + } |
| 79 | + | 881 | +} |
| 80 | +.. code-block:: bash | 882 | + |
| 81 | + | 883 | +/* Clear all FP flags. */ |
| 82 | + $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | 884 | +static inline void clear_fflags() |
| 83 | + $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | 885 | +{ |
| 84 | + $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G | 886 | + __asm__ __volatile__("fsflags zero"); |
| 85 | + | 887 | +} |
| 86 | +Then we can boot the machine by: | 888 | + |
| 87 | + | 889 | +/* Read all FP flags. */ |
| 88 | +.. code-block:: bash | 890 | +static inline uint8_t get_fflags() |
| 89 | + | 891 | +{ |
| 90 | + $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ | 892 | + uint64_t v; |
| 91 | + -bios path/to/hss.bin -sd path/to/sdcard.img \ | 893 | + __asm__ __volatile__("frflags %0" : "=r"(v)); |
| 92 | + -nic user,model=cadence_gem \ | 894 | + return (uint8_t)v; |
| 93 | + -nic tap,ifname=tap,model=cadence_gem,script=no \ | 895 | +} |
| 94 | + -display none -serial stdio \ | 896 | + |
| 95 | + -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \ | 897 | +/* Move input value (without conversations) into an FP register. */ |
| 96 | + -serial chardev:serial1 | 898 | +static inline double do_fmv_d_x(uint64_t inp) |
| 97 | + | 899 | +{ |
| 98 | +With above command line, current terminal session will be used for the first | 900 | + double fpr; |
| 99 | +serial port. Open another terminal window, and use `minicom` to connect the | 901 | + __asm__ __volatile__("fmv.d.x %0, %1" : "=f"(fpr) : "r"(inp)); |
| 100 | +second serial port. | 902 | + return fpr; |
| 101 | + | 903 | +} |
| 102 | +.. code-block:: bash | 904 | + |
| 103 | + | 905 | +static inline uint64_t do_fcvt_w_d(uint64_t inp, uint8_t *fflags) |
| 104 | + $ minicom -D unix\#serial1.sock | 906 | +{ |
| 105 | + | 907 | + uint64_t ret; |
| 106 | +HSS output is on the first serial port (stdio) and U-Boot outputs on the | 908 | + double fpr = do_fmv_d_x(inp); |
| 107 | +second serial port. U-Boot will automatically load the Linux kernel from | 909 | + |
| 108 | +the SD card image. | 910 | + clear_fflags(); |
| 109 | + | 911 | + |
| 110 | +.. _HSS: https://github.com/polarfire-soc/hart-software-services | 912 | + __asm__ __volatile__("fcvt.w.d %0, %1, rtz" : "=r"(ret) : "f"(fpr)); |
| 111 | diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst | 913 | + |
| 914 | + *fflags = get_fflags(); | ||
| 915 | + | ||
| 916 | + return ret; | ||
| 917 | +} | ||
| 918 | + | ||
| 919 | +static inline uint64_t do_fcvtmod_w_d(uint64_t inp, uint8_t *fflags) | ||
| 920 | +{ | ||
| 921 | + uint64_t ret; | ||
| 922 | + double fpr = do_fmv_d_x(inp); | ||
| 923 | + | ||
| 924 | + clear_fflags(); | ||
| 925 | + | ||
| 926 | + /* fcvtmod.w.d rd, rs1, rtz = 1100001 01000 rs1 001 rd 1010011 */ | ||
| 927 | + asm(".insn r 0x53, 0x1, 0x61, %0, %1, f8" : "=r"(ret) : "f"(fpr)); | ||
| 928 | + | ||
| 929 | + *fflags = get_fflags(); | ||
| 930 | + | ||
| 931 | + return ret; | ||
| 932 | +} | ||
| 933 | + | ||
| 934 | +static const fp64_fcvt_fcvtmod_testcase_t tests[] = { | ||
| 935 | + /* Zero (exp=0, frac=0) */ | ||
| 936 | + { .name = "+0.0", | ||
| 937 | + .inp_lf = 0x0p0, | ||
| 938 | + .exp_fcvt = 0x0000000000000000, | ||
| 939 | + .exp_fcvt_fflags = 0, | ||
| 940 | + .exp_fcvtmod = 0x0000000000000000, | ||
| 941 | + .exp_fcvtmod_fflags = 0 }, | ||
| 942 | + { .name = "-0.0", | ||
| 943 | + .inp_lf = -0x0p0, | ||
| 944 | + .exp_fcvt = 0x0000000000000000, | ||
| 945 | + .exp_fcvt_fflags = 0, | ||
| 946 | + .exp_fcvtmod = 0x0000000000000000, | ||
| 947 | + .exp_fcvtmod_fflags = 0 }, | ||
| 948 | + | ||
| 949 | + /* Subnormal: exp=0 frac!=0 */ | ||
| 950 | + { .name = "Subnormal frac=1", | ||
| 951 | + .inp_lu = 0x0000000000000001, | ||
| 952 | + .exp_fcvt = 0x0000000000000000, | ||
| 953 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 954 | + .exp_fcvtmod = 0, | ||
| 955 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 956 | + { .name = "Subnormal frac=0xf..f", | ||
| 957 | + .inp_lu = 0x0000ffffffffffff, | ||
| 958 | + .exp_fcvt = 0x0000000000000000, | ||
| 959 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 960 | + .exp_fcvtmod = 0, | ||
| 961 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 962 | + { .name = "Neg subnormal frac=1", | ||
| 963 | + .inp_lu = 0x0000000000000001, | ||
| 964 | + .exp_fcvt = 0x0000000000000000, | ||
| 965 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 966 | + .exp_fcvtmod = 0, | ||
| 967 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 968 | + { .name = "Neg subnormal frac=0xf..f", | ||
| 969 | + .inp_lu = 0x8000ffffffffffff, | ||
| 970 | + .exp_fcvt = 0x0000000000000000, | ||
| 971 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 972 | + .exp_fcvtmod = 0, | ||
| 973 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 974 | + | ||
| 975 | + /* Infinity: exp=0x7ff, frac=0 */ | ||
| 976 | + { .name = "+INF", | ||
| 977 | + .inp_lu = 0x7ff0000000000000, | ||
| 978 | + .exp_fcvt = 0x000000007fffffff, /* int32 max */ | ||
| 979 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 980 | + .exp_fcvtmod = 0, | ||
| 981 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 982 | + { .name = "-INF", | ||
| 983 | + .inp_lu = 0xfff0000000000000, | ||
| 984 | + .exp_fcvt = 0xffffffff80000000, /* int32 min */ | ||
| 985 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 986 | + .exp_fcvtmod = 0, | ||
| 987 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 988 | + | ||
| 989 | + /* NaN: exp=7ff, frac!=0 */ | ||
| 990 | + { .name = "canonical NaN", | ||
| 991 | + .inp_lu = 0x7ff8000000000000, | ||
| 992 | + .exp_fcvt = 0x000000007fffffff, /* int32 max */ | ||
| 993 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 994 | + .exp_fcvtmod = 0, | ||
| 995 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 996 | + { .name = "non-canonical NaN", | ||
| 997 | + .inp_lu = 0x7ff8000000100000, | ||
| 998 | + .exp_fcvt = 0x000000007fffffff, /* int32 min */ | ||
| 999 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 1000 | + .exp_fcvtmod = 0, | ||
| 1001 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 1002 | + | ||
| 1003 | + /* Normal numbers: exp!=0, exp!=7ff */ | ||
| 1004 | + { .name = "+smallest normal value", | ||
| 1005 | + .inp_lu = 0x0010000000000000, | ||
| 1006 | + .exp_fcvt = 0, | ||
| 1007 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1008 | + .exp_fcvtmod = 0, | ||
| 1009 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1010 | + { .name = "-smallest normal value", | ||
| 1011 | + .inp_lu = 0x8010000000000000, | ||
| 1012 | + .exp_fcvt = 0, | ||
| 1013 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1014 | + .exp_fcvtmod = 0, | ||
| 1015 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1016 | + | ||
| 1017 | + { .name = "+0.5", | ||
| 1018 | + .inp_lf = 0x1p-1, | ||
| 1019 | + .exp_fcvt = 0, | ||
| 1020 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1021 | + .exp_fcvtmod = 0, | ||
| 1022 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1023 | + { .name = "-0.5", | ||
| 1024 | + .inp_lf = -0x1p-1, | ||
| 1025 | + .exp_fcvt = 0, | ||
| 1026 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1027 | + .exp_fcvtmod = 0, | ||
| 1028 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1029 | + | ||
| 1030 | + { .name = "+value just below 1.0", | ||
| 1031 | + .inp_lu = 0x3fefffffffffffff, | ||
| 1032 | + .exp_fcvt = 0, | ||
| 1033 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1034 | + .exp_fcvtmod = 0, | ||
| 1035 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1036 | + { .name = "-value just above -1.0", | ||
| 1037 | + .inp_lu = 0xbfefffffffffffff, | ||
| 1038 | + .exp_fcvt = 0, | ||
| 1039 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1040 | + .exp_fcvtmod = 0, | ||
| 1041 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1042 | + | ||
| 1043 | + { .name = "+1.0", | ||
| 1044 | + .inp_lf = 0x1p0, | ||
| 1045 | + .exp_fcvt = 0x0000000000000001, | ||
| 1046 | + .exp_fcvt_fflags = 0, | ||
| 1047 | + .exp_fcvtmod = 0x0000000000000001, | ||
| 1048 | + .exp_fcvtmod_fflags = 0 }, | ||
| 1049 | + { .name = "-1.0", | ||
| 1050 | + .inp_lf = -0x1p0, | ||
| 1051 | + .exp_fcvt = 0xffffffffffffffff, | ||
| 1052 | + .exp_fcvt_fflags = 0, | ||
| 1053 | + .exp_fcvtmod = 0xffffffffffffffff, | ||
| 1054 | + .exp_fcvtmod_fflags = 0 }, | ||
| 1055 | + | ||
| 1056 | + { .name = "+1.5", | ||
| 1057 | + .inp_lu = 0x3ff8000000000000, | ||
| 1058 | + .exp_fcvt = 1, | ||
| 1059 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1060 | + .exp_fcvtmod = 1, | ||
| 1061 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1062 | + { .name = "-1.5", | ||
| 1063 | + .inp_lu = 0xbff8000000000000, | ||
| 1064 | + .exp_fcvt = 0xffffffffffffffff, | ||
| 1065 | + .exp_fcvt_fflags = FFLAG_NX, | ||
| 1066 | + .exp_fcvtmod = 0xffffffffffffffff, | ||
| 1067 | + .exp_fcvtmod_fflags = FFLAG_NX }, | ||
| 1068 | + | ||
| 1069 | + { .name = "+max int32 (2147483647)", | ||
| 1070 | + .inp_lu = 0x41dfffffffc00000, | ||
| 1071 | + .exp_fcvt = 0x000000007fffffff, | ||
| 1072 | + .exp_fcvt_fflags = 0, | ||
| 1073 | + .exp_fcvtmod = 0x000000007fffffff, | ||
| 1074 | + .exp_fcvtmod_fflags = 0 }, | ||
| 1075 | + { .name = "+max int32 +1 (2147483648)", | ||
| 1076 | + .inp_lf = 0x1p31, | ||
| 1077 | + .exp_fcvt = 0x000000007fffffff, | ||
| 1078 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 1079 | + .exp_fcvtmod = (uint64_t)-2147483648l, /* int32 min */ | ||
| 1080 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 1081 | + { .name = "+max int32 +2 (2147483649)", | ||
| 1082 | + .inp_lu = 0x41e0000000200000, | ||
| 1083 | + .exp_fcvt = 0x000000007fffffff, | ||
| 1084 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 1085 | + .exp_fcvtmod = (uint64_t)-2147483647l, /* int32 min +1 */ | ||
| 1086 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 1087 | + | ||
| 1088 | + { .name = "-max int32 (-2147483648)", | ||
| 1089 | + .inp_lf = -0x1p31, | ||
| 1090 | + .exp_fcvt = 0xffffffff80000000, | ||
| 1091 | + .exp_fcvt_fflags = 0, | ||
| 1092 | + .exp_fcvtmod = 0xffffffff80000000, | ||
| 1093 | + .exp_fcvtmod_fflags = 0 }, | ||
| 1094 | + { .name = "-max int32 -1 (-2147483649)", | ||
| 1095 | + .inp_lf = -0x1.00000002p+31, | ||
| 1096 | + .exp_fcvt = 0xffffffff80000000, | ||
| 1097 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 1098 | + .exp_fcvtmod = 2147483647, /* int32 max */ | ||
| 1099 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 1100 | + { .name = "-max int32 -2 (-2147483650)", | ||
| 1101 | + .inp_lf = -0x1.00000004p+31, | ||
| 1102 | + .exp_fcvt = 0xffffffff80000000, | ||
| 1103 | + .exp_fcvt_fflags = FFLAG_NV, | ||
| 1104 | + .exp_fcvtmod = 2147483646, /* int32 max -1 */ | ||
| 1105 | + .exp_fcvtmod_fflags = FFLAG_NV }, | ||
| 1106 | +}; | ||
| 1107 | + | ||
| 1108 | +int run_fcvtmod_tests() | ||
| 1109 | +{ | ||
| 1110 | + uint64_t act_fcvt; | ||
| 1111 | + uint8_t act_fcvt_fflags; | ||
| 1112 | + uint64_t act_fcvtmod; | ||
| 1113 | + uint8_t act_fcvtmod_fflags; | ||
| 1114 | + | ||
| 1115 | + for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); i++) { | ||
| 1116 | + const fp64_fcvt_fcvtmod_testcase_t *t = &tests[i]; | ||
| 1117 | + | ||
| 1118 | + act_fcvt = do_fcvt_w_d(t->inp_lu, &act_fcvt_fflags); | ||
| 1119 | + int fcvt_correct = act_fcvt == t->exp_fcvt && | ||
| 1120 | + act_fcvt_fflags == t->exp_fcvt_fflags; | ||
| 1121 | + act_fcvtmod = do_fcvtmod_w_d(t->inp_lu, &act_fcvtmod_fflags); | ||
| 1122 | + int fcvtmod_correct = act_fcvtmod == t->exp_fcvtmod && | ||
| 1123 | + act_fcvtmod_fflags == t->exp_fcvtmod_fflags; | ||
| 1124 | + | ||
| 1125 | + if (fcvt_correct && fcvtmod_correct) { | ||
| 1126 | + continue; | ||
| 1127 | + } | ||
| 1128 | + | ||
| 1129 | + printf("Test %zu (%s) failed!\n", i, t->name); | ||
| 1130 | + | ||
| 1131 | + double fpr = do_fmv_d_x(t->inp_lu); | ||
| 1132 | + printf("inp_lu: 0x%016lx == %lf\n", t->inp_lu, fpr); | ||
| 1133 | + printf("inp_lf: %lf\n", t->inp_lf); | ||
| 1134 | + | ||
| 1135 | + uint32_t sign = (t->inp_lu >> 63); | ||
| 1136 | + uint32_t exp = (uint32_t)(t->inp_lu >> 52) & 0x7ff; | ||
| 1137 | + uint64_t frac = t->inp_lu & 0xfffffffffffffull; /* significand */ | ||
| 1138 | + int true_exp = exp - 1023; | ||
| 1139 | + int shift = true_exp - 52; | ||
| 1140 | + uint64_t true_frac = frac | 1ull << 52; | ||
| 1141 | + | ||
| 1142 | + printf("sign=%d, exp=0x%03x, frac=0x%012lx\n", sign, exp, frac); | ||
| 1143 | + printf("true_exp=%d, shift=%d, true_frac=0x%016lx\n", true_exp, shift, true_frac); | ||
| 1144 | + | ||
| 1145 | + if (!fcvt_correct) { | ||
| 1146 | + printf("act_fcvt: 0x%016lx == %li\n", act_fcvt, act_fcvt); | ||
| 1147 | + printf("exp_fcvt: 0x%016lx == %li\n", t->exp_fcvt, t->exp_fcvt); | ||
| 1148 | + printf("act_fcvt_fflags: "); print_fflags(act_fcvt_fflags); printf("\n"); | ||
| 1149 | + printf("exp_fcvt_fflags: "); print_fflags(t->exp_fcvt_fflags); printf("\n"); | ||
| 1150 | + } | ||
| 1151 | + | ||
| 1152 | + if (!fcvtmod_correct) { | ||
| 1153 | + printf("act_fcvtmod: 0x%016lx == %li\n", act_fcvtmod, act_fcvtmod); | ||
| 1154 | + printf("exp_fcvtmod: 0x%016lx == %li\n", t->exp_fcvtmod, t->exp_fcvtmod); | ||
| 1155 | + printf("act_fcvtmod_fflags: "); print_fflags(act_fcvtmod_fflags); printf("\n"); | ||
| 1156 | + printf("exp_fcvtmod_fflags: "); print_fflags(t->exp_fcvtmod_fflags); printf("\n"); | ||
| 1157 | + } | ||
| 1158 | + | ||
| 1159 | + return 1; | ||
| 1160 | + } | ||
| 1161 | + | ||
| 1162 | + return 0; | ||
| 1163 | +} | ||
| 1164 | + | ||
| 1165 | +int main() | ||
| 1166 | +{ | ||
| 1167 | + return run_fcvtmod_tests(); | ||
| 1168 | +} | ||
| 1169 | diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc | ||
| 1170 | new file mode 100644 | ||
| 1171 | index XXXXXXX..XXXXXXX | ||
| 1172 | --- /dev/null | ||
| 1173 | +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc | ||
| 1174 | @@ -XXX,XX +XXX,XX @@ | ||
| 1175 | +/* | ||
| 1176 | + * RISC-V translation routines for the Zfa Standard Extension. | ||
| 1177 | + * | ||
| 1178 | + * Copyright (c) 2023 Christoph Müllner, christoph.muellner@vrull.eu | ||
| 1179 | + * | ||
| 1180 | + * This program is free software; you can redistribute it and/or modify it | ||
| 1181 | + * under the terms and conditions of the GNU General Public License, | ||
| 1182 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 1183 | + * | ||
| 1184 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 1185 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 1186 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 1187 | + * more details. | ||
| 1188 | + * | ||
| 1189 | + * You should have received a copy of the GNU General Public License along with | ||
| 1190 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 1191 | + */ | ||
| 1192 | + | ||
| 1193 | +#define REQUIRE_ZFA(ctx) do { \ | ||
| 1194 | + if (!ctx->cfg_ptr->ext_zfa) { \ | ||
| 1195 | + return false; \ | ||
| 1196 | + } \ | ||
| 1197 | +} while (0) | ||
| 1198 | + | ||
| 1199 | +#define REQUIRE_ZFH(ctx) do { \ | ||
| 1200 | + if (!ctx->cfg_ptr->ext_zfh) { \ | ||
| 1201 | + return false; \ | ||
| 1202 | + } \ | ||
| 1203 | +} while (0) | ||
| 1204 | + | ||
| 1205 | +static bool trans_fli_s(DisasContext *ctx, arg_fli_s *a) | ||
| 1206 | +{ | ||
| 1207 | + REQUIRE_FPU; | ||
| 1208 | + REQUIRE_ZFA(ctx); | ||
| 1209 | + REQUIRE_EXT(ctx, RVF); | ||
| 1210 | + | ||
| 1211 | + /* Values below are NaN-boxed to avoid a gen_nanbox_s(). */ | ||
| 1212 | + static const uint64_t fli_s_table[] = { | ||
| 1213 | + 0xffffffffbf800000, /* -1.0 */ | ||
| 1214 | + 0xffffffff00800000, /* minimum positive normal */ | ||
| 1215 | + 0xffffffff37800000, /* 1.0 * 2^-16 */ | ||
| 1216 | + 0xffffffff38000000, /* 1.0 * 2^-15 */ | ||
| 1217 | + 0xffffffff3b800000, /* 1.0 * 2^-8 */ | ||
| 1218 | + 0xffffffff3c000000, /* 1.0 * 2^-7 */ | ||
| 1219 | + 0xffffffff3d800000, /* 1.0 * 2^-4 */ | ||
| 1220 | + 0xffffffff3e000000, /* 1.0 * 2^-3 */ | ||
| 1221 | + 0xffffffff3e800000, /* 0.25 */ | ||
| 1222 | + 0xffffffff3ea00000, /* 0.3125 */ | ||
| 1223 | + 0xffffffff3ec00000, /* 0.375 */ | ||
| 1224 | + 0xffffffff3ee00000, /* 0.4375 */ | ||
| 1225 | + 0xffffffff3f000000, /* 0.5 */ | ||
| 1226 | + 0xffffffff3f200000, /* 0.625 */ | ||
| 1227 | + 0xffffffff3f400000, /* 0.75 */ | ||
| 1228 | + 0xffffffff3f600000, /* 0.875 */ | ||
| 1229 | + 0xffffffff3f800000, /* 1.0 */ | ||
| 1230 | + 0xffffffff3fa00000, /* 1.25 */ | ||
| 1231 | + 0xffffffff3fc00000, /* 1.5 */ | ||
| 1232 | + 0xffffffff3fe00000, /* 1.75 */ | ||
| 1233 | + 0xffffffff40000000, /* 2.0 */ | ||
| 1234 | + 0xffffffff40200000, /* 2.5 */ | ||
| 1235 | + 0xffffffff40400000, /* 3 */ | ||
| 1236 | + 0xffffffff40800000, /* 4 */ | ||
| 1237 | + 0xffffffff41000000, /* 8 */ | ||
| 1238 | + 0xffffffff41800000, /* 16 */ | ||
| 1239 | + 0xffffffff43000000, /* 2^7 */ | ||
| 1240 | + 0xffffffff43800000, /* 2^8 */ | ||
| 1241 | + 0xffffffff47000000, /* 2^15 */ | ||
| 1242 | + 0xffffffff47800000, /* 2^16 */ | ||
| 1243 | + 0xffffffff7f800000, /* +inf */ | ||
| 1244 | + 0xffffffff7fc00000, /* Canonical NaN */ | ||
| 1245 | + }; | ||
| 1246 | + | ||
| 1247 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1248 | + tcg_gen_movi_i64(dest, fli_s_table[a->rs1]); | ||
| 1249 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1250 | + | ||
| 1251 | + mark_fs_dirty(ctx); | ||
| 1252 | + return true; | ||
| 1253 | +} | ||
| 1254 | + | ||
| 1255 | +static bool trans_fli_d(DisasContext *ctx, arg_fli_d *a) | ||
| 1256 | +{ | ||
| 1257 | + REQUIRE_FPU; | ||
| 1258 | + REQUIRE_ZFA(ctx); | ||
| 1259 | + REQUIRE_EXT(ctx, RVD); | ||
| 1260 | + | ||
| 1261 | + static const uint64_t fli_d_table[] = { | ||
| 1262 | + 0xbff0000000000000, /* -1.0 */ | ||
| 1263 | + 0x0010000000000000, /* minimum positive normal */ | ||
| 1264 | + 0x3ef0000000000000, /* 1.0 * 2^-16 */ | ||
| 1265 | + 0x3f00000000000000, /* 1.0 * 2^-15 */ | ||
| 1266 | + 0x3f70000000000000, /* 1.0 * 2^-8 */ | ||
| 1267 | + 0x3f80000000000000, /* 1.0 * 2^-7 */ | ||
| 1268 | + 0x3fb0000000000000, /* 1.0 * 2^-4 */ | ||
| 1269 | + 0x3fc0000000000000, /* 1.0 * 2^-3 */ | ||
| 1270 | + 0x3fd0000000000000, /* 0.25 */ | ||
| 1271 | + 0x3fd4000000000000, /* 0.3125 */ | ||
| 1272 | + 0x3fd8000000000000, /* 0.375 */ | ||
| 1273 | + 0x3fdc000000000000, /* 0.4375 */ | ||
| 1274 | + 0x3fe0000000000000, /* 0.5 */ | ||
| 1275 | + 0x3fe4000000000000, /* 0.625 */ | ||
| 1276 | + 0x3fe8000000000000, /* 0.75 */ | ||
| 1277 | + 0x3fec000000000000, /* 0.875 */ | ||
| 1278 | + 0x3ff0000000000000, /* 1.0 */ | ||
| 1279 | + 0x3ff4000000000000, /* 1.25 */ | ||
| 1280 | + 0x3ff8000000000000, /* 1.5 */ | ||
| 1281 | + 0x3ffc000000000000, /* 1.75 */ | ||
| 1282 | + 0x4000000000000000, /* 2.0 */ | ||
| 1283 | + 0x4004000000000000, /* 2.5 */ | ||
| 1284 | + 0x4008000000000000, /* 3 */ | ||
| 1285 | + 0x4010000000000000, /* 4 */ | ||
| 1286 | + 0x4020000000000000, /* 8 */ | ||
| 1287 | + 0x4030000000000000, /* 16 */ | ||
| 1288 | + 0x4060000000000000, /* 2^7 */ | ||
| 1289 | + 0x4070000000000000, /* 2^8 */ | ||
| 1290 | + 0x40e0000000000000, /* 2^15 */ | ||
| 1291 | + 0x40f0000000000000, /* 2^16 */ | ||
| 1292 | + 0x7ff0000000000000, /* +inf */ | ||
| 1293 | + 0x7ff8000000000000, /* Canonical NaN */ | ||
| 1294 | + }; | ||
| 1295 | + | ||
| 1296 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1297 | + tcg_gen_movi_i64(dest, fli_d_table[a->rs1]); | ||
| 1298 | + gen_set_fpr_d(ctx, a->rd, dest); | ||
| 1299 | + | ||
| 1300 | + mark_fs_dirty(ctx); | ||
| 1301 | + return true; | ||
| 1302 | +} | ||
| 1303 | + | ||
| 1304 | +static bool trans_fli_h(DisasContext *ctx, arg_fli_h *a) | ||
| 1305 | +{ | ||
| 1306 | + REQUIRE_FPU; | ||
| 1307 | + REQUIRE_ZFA(ctx); | ||
| 1308 | + REQUIRE_ZFH(ctx); | ||
| 1309 | + | ||
| 1310 | + /* Values below are NaN-boxed to avoid a gen_nanbox_h(). */ | ||
| 1311 | + static const uint64_t fli_h_table[] = { | ||
| 1312 | + 0xffffffffffffbc00, /* -1.0 */ | ||
| 1313 | + 0xffffffffffff0400, /* minimum positive normal */ | ||
| 1314 | + 0xffffffffffff0100, /* 1.0 * 2^-16 */ | ||
| 1315 | + 0xffffffffffff0200, /* 1.0 * 2^-15 */ | ||
| 1316 | + 0xffffffffffff1c00, /* 1.0 * 2^-8 */ | ||
| 1317 | + 0xffffffffffff2000, /* 1.0 * 2^-7 */ | ||
| 1318 | + 0xffffffffffff2c00, /* 1.0 * 2^-4 */ | ||
| 1319 | + 0xffffffffffff3000, /* 1.0 * 2^-3 */ | ||
| 1320 | + 0xffffffffffff3400, /* 0.25 */ | ||
| 1321 | + 0xffffffffffff3500, /* 0.3125 */ | ||
| 1322 | + 0xffffffffffff3600, /* 0.375 */ | ||
| 1323 | + 0xffffffffffff3700, /* 0.4375 */ | ||
| 1324 | + 0xffffffffffff3800, /* 0.5 */ | ||
| 1325 | + 0xffffffffffff3900, /* 0.625 */ | ||
| 1326 | + 0xffffffffffff3a00, /* 0.75 */ | ||
| 1327 | + 0xffffffffffff3b00, /* 0.875 */ | ||
| 1328 | + 0xffffffffffff3c00, /* 1.0 */ | ||
| 1329 | + 0xffffffffffff3d00, /* 1.25 */ | ||
| 1330 | + 0xffffffffffff3e00, /* 1.5 */ | ||
| 1331 | + 0xffffffffffff3f00, /* 1.75 */ | ||
| 1332 | + 0xffffffffffff4000, /* 2.0 */ | ||
| 1333 | + 0xffffffffffff4100, /* 2.5 */ | ||
| 1334 | + 0xffffffffffff4200, /* 3 */ | ||
| 1335 | + 0xffffffffffff4400, /* 4 */ | ||
| 1336 | + 0xffffffffffff4800, /* 8 */ | ||
| 1337 | + 0xffffffffffff4c00, /* 16 */ | ||
| 1338 | + 0xffffffffffff5800, /* 2^7 */ | ||
| 1339 | + 0xffffffffffff5c00, /* 2^8 */ | ||
| 1340 | + 0xffffffffffff7800, /* 2^15 */ | ||
| 1341 | + 0xffffffffffff7c00, /* 2^16 */ | ||
| 1342 | + 0xffffffffffff7c00, /* +inf */ | ||
| 1343 | + 0xffffffffffff7e00, /* Canonical NaN */ | ||
| 1344 | + }; | ||
| 1345 | + | ||
| 1346 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1347 | + tcg_gen_movi_i64(dest, fli_h_table[a->rs1]); | ||
| 1348 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1349 | + | ||
| 1350 | + mark_fs_dirty(ctx); | ||
| 1351 | + return true; | ||
| 1352 | +} | ||
| 1353 | + | ||
| 1354 | +static bool trans_fminm_s(DisasContext *ctx, arg_fminm_s *a) | ||
| 1355 | +{ | ||
| 1356 | + REQUIRE_FPU; | ||
| 1357 | + REQUIRE_ZFA(ctx); | ||
| 1358 | + REQUIRE_EXT(ctx, RVF); | ||
| 1359 | + | ||
| 1360 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1361 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1362 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1363 | + | ||
| 1364 | + gen_helper_fminm_s(dest, cpu_env, src1, src2); | ||
| 1365 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1366 | + | ||
| 1367 | + mark_fs_dirty(ctx); | ||
| 1368 | + return true; | ||
| 1369 | +} | ||
| 1370 | + | ||
| 1371 | +static bool trans_fmaxm_s(DisasContext *ctx, arg_fmaxm_s *a) | ||
| 1372 | +{ | ||
| 1373 | + REQUIRE_FPU; | ||
| 1374 | + REQUIRE_ZFA(ctx); | ||
| 1375 | + REQUIRE_EXT(ctx, RVF); | ||
| 1376 | + | ||
| 1377 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1378 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1379 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1380 | + | ||
| 1381 | + gen_helper_fmaxm_s(dest, cpu_env, src1, src2); | ||
| 1382 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1383 | + | ||
| 1384 | + mark_fs_dirty(ctx); | ||
| 1385 | + return true; | ||
| 1386 | +} | ||
| 1387 | + | ||
| 1388 | +static bool trans_fminm_d(DisasContext *ctx, arg_fminm_d *a) | ||
| 1389 | +{ | ||
| 1390 | + REQUIRE_FPU; | ||
| 1391 | + REQUIRE_ZFA(ctx); | ||
| 1392 | + REQUIRE_EXT(ctx, RVD); | ||
| 1393 | + | ||
| 1394 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1395 | + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); | ||
| 1396 | + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); | ||
| 1397 | + | ||
| 1398 | + gen_helper_fminm_d(dest, cpu_env, src1, src2); | ||
| 1399 | + gen_set_fpr_d(ctx, a->rd, dest); | ||
| 1400 | + | ||
| 1401 | + mark_fs_dirty(ctx); | ||
| 1402 | + return true; | ||
| 1403 | +} | ||
| 1404 | + | ||
| 1405 | +static bool trans_fmaxm_d(DisasContext *ctx, arg_fmaxm_d *a) | ||
| 1406 | +{ | ||
| 1407 | + REQUIRE_FPU; | ||
| 1408 | + REQUIRE_ZFA(ctx); | ||
| 1409 | + REQUIRE_EXT(ctx, RVD); | ||
| 1410 | + | ||
| 1411 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1412 | + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); | ||
| 1413 | + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); | ||
| 1414 | + | ||
| 1415 | + gen_helper_fmaxm_d(dest, cpu_env, src1, src2); | ||
| 1416 | + gen_set_fpr_d(ctx, a->rd, dest); | ||
| 1417 | + | ||
| 1418 | + mark_fs_dirty(ctx); | ||
| 1419 | + return true; | ||
| 1420 | +} | ||
| 1421 | + | ||
| 1422 | +static bool trans_fminm_h(DisasContext *ctx, arg_fminm_h *a) | ||
| 1423 | +{ | ||
| 1424 | + REQUIRE_FPU; | ||
| 1425 | + REQUIRE_ZFA(ctx); | ||
| 1426 | + REQUIRE_ZFH(ctx); | ||
| 1427 | + | ||
| 1428 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1429 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1430 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1431 | + | ||
| 1432 | + gen_helper_fminm_h(dest, cpu_env, src1, src2); | ||
| 1433 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1434 | + | ||
| 1435 | + mark_fs_dirty(ctx); | ||
| 1436 | + return true; | ||
| 1437 | +} | ||
| 1438 | + | ||
| 1439 | +static bool trans_fmaxm_h(DisasContext *ctx, arg_fmaxm_h *a) | ||
| 1440 | +{ | ||
| 1441 | + REQUIRE_FPU; | ||
| 1442 | + REQUIRE_ZFA(ctx); | ||
| 1443 | + REQUIRE_ZFH(ctx); | ||
| 1444 | + | ||
| 1445 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1446 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1447 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1448 | + | ||
| 1449 | + gen_helper_fmaxm_h(dest, cpu_env, src1, src2); | ||
| 1450 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1451 | + | ||
| 1452 | + mark_fs_dirty(ctx); | ||
| 1453 | + return true; | ||
| 1454 | +} | ||
| 1455 | + | ||
| 1456 | +static bool trans_fround_s(DisasContext *ctx, arg_fround_s *a) | ||
| 1457 | +{ | ||
| 1458 | + REQUIRE_FPU; | ||
| 1459 | + REQUIRE_ZFA(ctx); | ||
| 1460 | + REQUIRE_EXT(ctx, RVF); | ||
| 1461 | + | ||
| 1462 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1463 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1464 | + | ||
| 1465 | + gen_set_rm(ctx, a->rm); | ||
| 1466 | + gen_helper_fround_s(dest, cpu_env, src1); | ||
| 1467 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1468 | + | ||
| 1469 | + mark_fs_dirty(ctx); | ||
| 1470 | + return true; | ||
| 1471 | +} | ||
| 1472 | + | ||
| 1473 | +static bool trans_froundnx_s(DisasContext *ctx, arg_froundnx_s *a) | ||
| 1474 | +{ | ||
| 1475 | + REQUIRE_FPU; | ||
| 1476 | + REQUIRE_ZFA(ctx); | ||
| 1477 | + REQUIRE_EXT(ctx, RVF); | ||
| 1478 | + | ||
| 1479 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1480 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1481 | + | ||
| 1482 | + gen_set_rm(ctx, a->rm); | ||
| 1483 | + gen_helper_froundnx_s(dest, cpu_env, src1); | ||
| 1484 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1485 | + | ||
| 1486 | + mark_fs_dirty(ctx); | ||
| 1487 | + return true; | ||
| 1488 | +} | ||
| 1489 | + | ||
| 1490 | +static bool trans_fround_d(DisasContext *ctx, arg_fround_d *a) | ||
| 1491 | +{ | ||
| 1492 | + REQUIRE_FPU; | ||
| 1493 | + REQUIRE_ZFA(ctx); | ||
| 1494 | + REQUIRE_EXT(ctx, RVD); | ||
| 1495 | + | ||
| 1496 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1497 | + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); | ||
| 1498 | + | ||
| 1499 | + gen_set_rm(ctx, a->rm); | ||
| 1500 | + gen_helper_fround_d(dest, cpu_env, src1); | ||
| 1501 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1502 | + | ||
| 1503 | + mark_fs_dirty(ctx); | ||
| 1504 | + return true; | ||
| 1505 | +} | ||
| 1506 | + | ||
| 1507 | +static bool trans_froundnx_d(DisasContext *ctx, arg_froundnx_d *a) | ||
| 1508 | +{ | ||
| 1509 | + REQUIRE_FPU; | ||
| 1510 | + REQUIRE_ZFA(ctx); | ||
| 1511 | + REQUIRE_EXT(ctx, RVD); | ||
| 1512 | + | ||
| 1513 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1514 | + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); | ||
| 1515 | + | ||
| 1516 | + gen_set_rm(ctx, a->rm); | ||
| 1517 | + gen_helper_froundnx_d(dest, cpu_env, src1); | ||
| 1518 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1519 | + | ||
| 1520 | + mark_fs_dirty(ctx); | ||
| 1521 | + return true; | ||
| 1522 | +} | ||
| 1523 | + | ||
| 1524 | +static bool trans_fround_h(DisasContext *ctx, arg_fround_h *a) | ||
| 1525 | +{ | ||
| 1526 | + REQUIRE_FPU; | ||
| 1527 | + REQUIRE_ZFA(ctx); | ||
| 1528 | + REQUIRE_ZFH(ctx); | ||
| 1529 | + | ||
| 1530 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1531 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1532 | + | ||
| 1533 | + gen_set_rm(ctx, a->rm); | ||
| 1534 | + gen_helper_fround_h(dest, cpu_env, src1); | ||
| 1535 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1536 | + | ||
| 1537 | + mark_fs_dirty(ctx); | ||
| 1538 | + return true; | ||
| 1539 | +} | ||
| 1540 | + | ||
| 1541 | +static bool trans_froundnx_h(DisasContext *ctx, arg_froundnx_h *a) | ||
| 1542 | +{ | ||
| 1543 | + REQUIRE_FPU; | ||
| 1544 | + REQUIRE_ZFA(ctx); | ||
| 1545 | + REQUIRE_ZFH(ctx); | ||
| 1546 | + | ||
| 1547 | + TCGv_i64 dest = dest_fpr(ctx, a->rd); | ||
| 1548 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1549 | + | ||
| 1550 | + gen_set_rm(ctx, a->rm); | ||
| 1551 | + gen_helper_froundnx_h(dest, cpu_env, src1); | ||
| 1552 | + gen_set_fpr_hs(ctx, a->rd, dest); | ||
| 1553 | + | ||
| 1554 | + mark_fs_dirty(ctx); | ||
| 1555 | + return true; | ||
| 1556 | +} | ||
| 1557 | + | ||
| 1558 | +bool trans_fcvtmod_w_d(DisasContext *ctx, arg_fcvtmod_w_d *a) | ||
| 1559 | +{ | ||
| 1560 | + REQUIRE_FPU; | ||
| 1561 | + REQUIRE_ZFA(ctx); | ||
| 1562 | + REQUIRE_EXT(ctx, RVD); | ||
| 1563 | + | ||
| 1564 | + TCGv dst = dest_gpr(ctx, a->rd); | ||
| 1565 | + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); | ||
| 1566 | + TCGv_i64 t1 = tcg_temp_new_i64(); | ||
| 1567 | + | ||
| 1568 | + /* Rounding mode is RTZ. */ | ||
| 1569 | + gen_set_rm(ctx, RISCV_FRM_RTZ); | ||
| 1570 | + gen_helper_fcvtmod_w_d(t1, cpu_env, src1); | ||
| 1571 | + tcg_gen_trunc_i64_tl(dst, t1); | ||
| 1572 | + gen_set_gpr(ctx, a->rd, dst); | ||
| 1573 | + | ||
| 1574 | + return true; | ||
| 1575 | +} | ||
| 1576 | + | ||
| 1577 | +bool trans_fmvh_x_d(DisasContext *ctx, arg_fmvh_x_d *a) | ||
| 1578 | +{ | ||
| 1579 | + REQUIRE_FPU; | ||
| 1580 | + REQUIRE_ZFA(ctx); | ||
| 1581 | + REQUIRE_EXT(ctx, RVD); | ||
| 1582 | + REQUIRE_32BIT(ctx); | ||
| 1583 | + | ||
| 1584 | + TCGv dst = dest_gpr(ctx, a->rd); | ||
| 1585 | + TCGv_i64 t1 = tcg_temp_new_i64(); | ||
| 1586 | + tcg_gen_sari_i64(t1, cpu_fpr[a->rs1], 32); | ||
| 1587 | + tcg_gen_trunc_i64_tl(dst, t1); | ||
| 1588 | + gen_set_gpr(ctx, a->rd, dst); | ||
| 1589 | + return true; | ||
| 1590 | +} | ||
| 1591 | + | ||
| 1592 | +bool trans_fmvp_d_x(DisasContext *ctx, arg_fmvp_d_x *a) | ||
| 1593 | +{ | ||
| 1594 | + REQUIRE_FPU; | ||
| 1595 | + REQUIRE_ZFA(ctx); | ||
| 1596 | + REQUIRE_EXT(ctx, RVD); | ||
| 1597 | + REQUIRE_32BIT(ctx); | ||
| 1598 | + | ||
| 1599 | + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); | ||
| 1600 | + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); | ||
| 1601 | + tcg_gen_concat_tl_i64(cpu_fpr[a->rd], src1, src2); | ||
| 1602 | + | ||
| 1603 | + mark_fs_dirty(ctx); | ||
| 1604 | + return true; | ||
| 1605 | +} | ||
| 1606 | + | ||
| 1607 | +bool trans_fleq_s(DisasContext *ctx, arg_fleq_s *a) | ||
| 1608 | +{ | ||
| 1609 | + REQUIRE_FPU; | ||
| 1610 | + REQUIRE_ZFA(ctx); | ||
| 1611 | + REQUIRE_EXT(ctx, RVF); | ||
| 1612 | + | ||
| 1613 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1614 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1615 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1616 | + | ||
| 1617 | + gen_helper_fleq_s(dest, cpu_env, src1, src2); | ||
| 1618 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1619 | + return true; | ||
| 1620 | +} | ||
| 1621 | + | ||
| 1622 | +bool trans_fltq_s(DisasContext *ctx, arg_fltq_s *a) | ||
| 1623 | +{ | ||
| 1624 | + REQUIRE_FPU; | ||
| 1625 | + REQUIRE_ZFA(ctx); | ||
| 1626 | + REQUIRE_EXT(ctx, RVF); | ||
| 1627 | + | ||
| 1628 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1629 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1630 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1631 | + | ||
| 1632 | + gen_helper_fltq_s(dest, cpu_env, src1, src2); | ||
| 1633 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1634 | + return true; | ||
| 1635 | +} | ||
| 1636 | + | ||
| 1637 | +bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) | ||
| 1638 | +{ | ||
| 1639 | + REQUIRE_FPU; | ||
| 1640 | + REQUIRE_ZFA(ctx); | ||
| 1641 | + REQUIRE_EXT(ctx, RVD); | ||
| 1642 | + | ||
| 1643 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1644 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1645 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1646 | + | ||
| 1647 | + gen_helper_fltq_s(dest, cpu_env, src1, src2); | ||
| 1648 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1649 | + return true; | ||
| 1650 | +} | ||
| 1651 | + | ||
| 1652 | +bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) | ||
| 1653 | +{ | ||
| 1654 | + REQUIRE_FPU; | ||
| 1655 | + REQUIRE_ZFA(ctx); | ||
| 1656 | + REQUIRE_EXT(ctx, RVD); | ||
| 1657 | + | ||
| 1658 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1659 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1660 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1661 | + | ||
| 1662 | + gen_helper_fltq_s(dest, cpu_env, src1, src2); | ||
| 1663 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1664 | + return true; | ||
| 1665 | +} | ||
| 1666 | + | ||
| 1667 | +bool trans_fleq_h(DisasContext *ctx, arg_fleq_h *a) | ||
| 1668 | +{ | ||
| 1669 | + REQUIRE_FPU; | ||
| 1670 | + REQUIRE_ZFA(ctx); | ||
| 1671 | + REQUIRE_ZFH(ctx); | ||
| 1672 | + | ||
| 1673 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1674 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1675 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1676 | + | ||
| 1677 | + gen_helper_fleq_h(dest, cpu_env, src1, src2); | ||
| 1678 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1679 | + return true; | ||
| 1680 | +} | ||
| 1681 | + | ||
| 1682 | +bool trans_fltq_h(DisasContext *ctx, arg_fltq_h *a) | ||
| 1683 | +{ | ||
| 1684 | + REQUIRE_FPU; | ||
| 1685 | + REQUIRE_ZFA(ctx); | ||
| 1686 | + REQUIRE_ZFH(ctx); | ||
| 1687 | + | ||
| 1688 | + TCGv dest = dest_gpr(ctx, a->rd); | ||
| 1689 | + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
| 1690 | + TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
| 1691 | + | ||
| 1692 | + gen_helper_fltq_h(dest, cpu_env, src1, src2); | ||
| 1693 | + gen_set_gpr(ctx, a->rd, dest); | ||
| 1694 | + return true; | ||
| 1695 | +} | ||
| 1696 | diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target | ||
| 112 | index XXXXXXX..XXXXXXX 100644 | 1697 | index XXXXXXX..XXXXXXX 100644 |
| 113 | --- a/docs/system/target-riscv.rst | 1698 | --- a/tests/tcg/riscv64/Makefile.target |
| 114 | +++ b/docs/system/target-riscv.rst | 1699 | +++ b/tests/tcg/riscv64/Makefile.target |
| 115 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 1700 | @@ -XXX,XX +XXX,XX @@ run-test-noc: QEMU_OPTS += -cpu rv64,c=false |
| 116 | .. toctree:: | 1701 | |
| 117 | :maxdepth: 1 | 1702 | TESTS += test-aes |
| 118 | 1703 | run-test-aes: QEMU_OPTS += -cpu rv64,zk=on | |
| 119 | + riscv/microchip-icicle-kit | 1704 | + |
| 120 | riscv/sifive_u | 1705 | +# Test for fcvtmod |
| 121 | 1706 | +TESTS += test-fcvtmod | |
| 122 | RISC-V CPU features | 1707 | +test-fcvtmod: CFLAGS += -march=rv64imafdc |
| 1708 | +test-fcvtmod: LDFLAGS += -static | ||
| 1709 | +run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true | ||
| 123 | -- | 1710 | -- |
| 124 | 2.30.1 | 1711 | 2.40.1 |
| 125 | 1712 | ||
| 126 | 1713 | diff view generated by jsdifflib |