[PULL 00/16] riscv-to-apply queue
[PULL 00/89] riscv-to-apply queue
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The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
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The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
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Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
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Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
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for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
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for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
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target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
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target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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RISC-V PR for 6.0
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First RISC-V PR for 8.1
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This PR includes:
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* CPURISCVState related cleanup and simplification
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- Fix for vector CSR access
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* Refactor Zicond and reuse in XVentanaCondOps
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- Improvements to the Ibex UART device
18
* Fix invalid riscv,event-to-mhpmcounters entry
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- PMP improvements and bug fixes
19
* Support subsets of code size reduction extension
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- Hypervisor extension bug fixes
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* Fix itrigger when icount is used
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- ramfb support for the virt machine
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* Simplification for RVH related check and code style fix
22
- Fast read support for SST flash
22
* Add signature dump function for spike to run ACT tests
23
- Improvements to the microchip_pfsoc machine
23
* Rework MISA writing
24
* Fix mstatus.MPP related support
25
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
26
* Fix the H extension TVM trap
27
* A large collection of mstatus sum changes and cleanups
28
* Zero init APLIC internal state
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* Implement query-cpu-definitions
30
* Restore the predicate() NULL check behavior
31
* Fix Guest Physical Address Translation
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* Make sure an exception is raised if a pte is malformed
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* Add Ventana's Veyron V1 CPU
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----------------------------------------------------------------
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----------------------------------------------------------------
26
Alexander Wagner (1):
36
Alexandre Ghiti (1):
27
hw/char: disable ibex uart receive if the buffer is full
37
riscv: Make sure an exception is raised if a pte is malformed
28
38
29
Asherah Connor (2):
39
Bin Meng (1):
30
hw/riscv: Add fw_cfg support to virt
40
target/riscv: Restore the predicate() NULL check behavior
31
hw/riscv: allow ramfb on virt
41
32
42
Conor Dooley (1):
33
Bin Meng (3):
43
target/riscv: fix invalid riscv,event-to-mhpmcounters entry
34
hw/block: m25p80: Support fast read for SST flashes
44
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
45
Daniel Henrique Barboza (23):
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
46
target/riscv: sync env->misa_ext* with cpu->cfg in realize()
37
47
target/riscv: remove MISA properties from isa_edata_arr[]
38
Frank Chang (1):
48
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
39
target/riscv: fix vs() to return proper error code
49
target/riscv: introduce riscv_cpu_add_misa_properties()
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target/riscv: remove cpu->cfg.ext_a
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Georg Kotheimer (6):
51
target/riscv: remove cpu->cfg.ext_c
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
52
target/riscv: remove cpu->cfg.ext_d
43
target/riscv: Make VSTIP and VSEIP read-only in hip
53
target/riscv: remove cpu->cfg.ext_f
44
target/riscv: Use background registers also for MSTATUS_MPV
54
target/riscv: remove cpu->cfg.ext_i
45
target/riscv: Fix read and write accesses to vsip and vsie
55
target/riscv: remove cpu->cfg.ext_e
46
target/riscv: Add proper two-stage lookup exception detection
56
target/riscv: remove cpu->cfg.ext_m
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target/riscv: Prevent lost illegal instruction exceptions
57
target/riscv: remove cpu->cfg.ext_s
48
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target/riscv: remove cpu->cfg.ext_u
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Jim Shu (3):
59
target/riscv: remove cpu->cfg.ext_h
50
target/riscv: propagate PMP permission to TLB page
60
target/riscv: remove cpu->cfg.ext_j
51
target/riscv: add log of PMP permission checking
61
target/riscv: remove cpu->cfg.ext_v
52
target/riscv: flush TLB pages if PMP permission has been changed
62
target/riscv: remove riscv_cpu_sync_misa_cfg()
53
63
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
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target/riscv: add RVG and remove cpu->cfg.ext_g
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docs/system/target-riscv.rst | 1 +
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target/riscv/cpu.c: redesign register_cpu_props()
56
include/hw/char/ibex_uart.h | 4 +
66
target/riscv: add CPU QOM header
57
include/hw/riscv/microchip_pfsoc.h | 1 +
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target/riscv: add query-cpy-definitions support
58
include/hw/riscv/virt.h | 2 +
68
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
59
target/riscv/cpu.h | 4 +
69
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target/riscv/pmp.h | 4 +-
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Fei Wu (2):
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hw/block/m25p80.c | 3 +
71
target/riscv: Separate priv from mmu_idx
62
hw/char/ibex_uart.c | 23 +++-
72
target/riscv: Reduce overhead of MSTATUS_SUM change
63
hw/riscv/microchip_pfsoc.c | 6 +
73
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hw/riscv/virt.c | 33 ++++++
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Irina Ryapolova (1):
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target/riscv/cpu.c | 1 +
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target/riscv: Fix Guest Physical Address Translation
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
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target/riscv/csr.c | 77 +++++++------
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Ivan Klokov (1):
68
target/riscv/pmp.c | 84 ++++++++++----
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hw/intc/riscv_aplic: Zero init APLIC internal state
69
target/riscv/translate.c | 179 +----------------------------
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hw/riscv/Kconfig | 1 +
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LIU Zhiwei (7):
71
17 files changed, 367 insertions(+), 289 deletions(-)
81
target/riscv: Fix priv version dependency for vector and zfh
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
82
target/riscv: Fix itrigger when icount is used
73
83
target/riscv: Convert env->virt to a bool env->virt_enabled
84
target/riscv: Extract virt enabled state from tb flags
85
target/riscv: Add a general status enum for extensions
86
target/riscv: Encode the FS and VS on a normal way for tb flags
87
target/riscv: Add a tb flags field for vstart
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89
Philipp Tomsich (2):
90
target/riscv: refactor Zicond support
91
target/riscv: redirect XVentanaCondOps to use the Zicond functions
92
93
Rahul Pathak (1):
94
target/riscv: add Ventana's Veyron V1 CPU
95
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Richard Henderson (18):
97
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
98
target/riscv: Use cpu_ld*_code_mmu for HLVX
99
target/riscv: Handle HLV, HSV via helpers
100
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
101
target/riscv: Introduce mmuidx_sum
102
target/riscv: Introduce mmuidx_priv
103
target/riscv: Introduce mmuidx_2stage
104
target/riscv: Move hstatus.spvp check to check_access_hlsv
105
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
106
target/riscv: Check SUM in the correct register
107
target/riscv: Hoist second stage mode change to callers
108
target/riscv: Hoist pbmte and hade out of the level loop
109
target/riscv: Move leaf pte processing out of level loop
110
target/riscv: Suppress pte update with is_debug
111
target/riscv: Don't modify SUM with is_debug
112
target/riscv: Merge checks for reserved pte flags
113
target/riscv: Reorg access check in get_physical_address
114
target/riscv: Reorg sum check in get_physical_address
115
116
Weiwei Li (30):
117
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
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target/riscv: Simplify getting RISCVCPU pointer from env
119
target/riscv: Simplify type conversion for CPURISCVState
120
target/riscv: Simplify arguments for riscv_csrrw_check
121
target/riscv: add cfg properties for Zc* extension
122
target/riscv: add support for Zca extension
123
target/riscv: add support for Zcf extension
124
target/riscv: add support for Zcd extension
125
target/riscv: add support for Zcb extension
126
target/riscv: add support for Zcmp extension
127
target/riscv: add support for Zcmt extension
128
target/riscv: expose properties for Zc* extension
129
disas/riscv.c: add disasm support for Zc*
130
target/riscv: Add support for Zce
131
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
132
target/riscv: Remove redundant check on RVH
133
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
134
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
135
target/riscv: Remove redundant parentheses
136
target/riscv: Fix addr type for get_physical_address
137
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
138
target/riscv: Remove riscv_cpu_virt_enabled()
139
target/riscv: Fix format for indentation
140
target/riscv: Fix format for comments
141
target/riscv: Fix lines with over 80 characters
142
hw/riscv: Add signature dump function for spike to run ACT tests
143
target/riscv: Fix the mstatus.MPP value after executing MRET
144
target/riscv: Use PRV_RESERVED instead of PRV_H
145
target/riscv: Legalize MPP value in write_mstatus
146
target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
147
148
Yi Chen (1):
149
target/riscv: fix H extension TVM trap
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151
MAINTAINERS | 2 +-
152
qapi/machine-target.json | 6 +-
153
include/hw/char/riscv_htif.h | 3 +
154
target/riscv/cpu-qom.h | 71 +++
155
target/riscv/cpu.h | 155 ++---
156
target/riscv/cpu_bits.h | 27 +-
157
target/riscv/cpu_vendorid.h | 4 +
158
target/riscv/helper.h | 15 +-
159
target/riscv/internals.h | 35 ++
160
target/riscv/pmp.h | 9 +-
161
target/riscv/sbi_ecall_interface.h | 8 +-
162
target/riscv/time_helper.h | 2 +-
163
target/riscv/insn16.decode | 62 +-
164
disas/riscv.c | 228 ++++++-
165
hw/char/riscv_htif.c | 44 +-
166
hw/intc/riscv_aplic.c | 2 +-
167
hw/riscv/spike.c | 13 +
168
target/riscv/arch_dump.c | 7 +-
169
target/riscv/cpu.c | 571 +++++++++++-------
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target/riscv/cpu_helper.c | 671 +++++++++++----------
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target/riscv/csr.c | 331 +++++-----
172
target/riscv/debug.c | 21 +-
173
target/riscv/fpu_helper.c | 24 +-
174
target/riscv/gdbstub.c | 9 +-
175
target/riscv/m128_helper.c | 16 +-
176
target/riscv/machine.c | 43 +-
177
target/riscv/op_helper.c | 147 ++++-
178
target/riscv/pmp.c | 66 +-
179
target/riscv/pmu.c | 23 +-
180
target/riscv/riscv-qmp-cmds.c | 57 ++
181
target/riscv/time_helper.c | 15 +-
182
target/riscv/translate.c | 109 ++--
183
target/riscv/vector_helper.c | 317 +++++-----
184
target/riscv/zce_helper.c | 55 ++
185
target/riscv/insn_trans/trans_privileged.c.inc | 8 +-
186
target/riscv/insn_trans/trans_rvd.c.inc | 18 +
187
target/riscv/insn_trans/trans_rvf.c.inc | 20 +-
188
target/riscv/insn_trans/trans_rvh.c.inc | 127 ++--
189
target/riscv/insn_trans/trans_rvi.c.inc | 4 +-
190
target/riscv/insn_trans/trans_rvv.c.inc | 58 +-
191
target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++
192
target/riscv/insn_trans/trans_rvzicond.c.inc | 36 +-
193
target/riscv/insn_trans/trans_xthead.c.inc | 14 +-
194
.../riscv/insn_trans/trans_xventanacondops.c.inc | 18 +-
195
target/riscv/meson.build | 6 +-
196
45 files changed, 2488 insertions(+), 1300 deletions(-)
197
create mode 100644 target/riscv/cpu-qom.h
198
create mode 100644 target/riscv/riscv-qmp-cmds.c
199
create mode 100644 target/riscv/zce_helper.c
200
create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
diff view generated by jsdifflib
New patch
[PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
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From: Weiwei Li <liweiwei@iscas.ac.cn>
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3
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
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5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu_helper.c | 9 ++++-----
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target/riscv/csr.c | 40 ++++++++++++---------------------------
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target/riscv/gdbstub.c | 4 ++--
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3 files changed, 18 insertions(+), 35 deletions(-)
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diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
22
int extirq, unsigned int extirq_def_prio,
23
uint64_t pending, uint8_t *iprio)
24
{
25
- RISCVCPU *cpu = env_archcpu(env);
26
int irq, best_irq = RISCV_EXCP_NONE;
27
unsigned int prio, best_prio = UINT_MAX;
28
29
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
30
}
31
32
irq = ctz64(pending);
33
- if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
34
+ if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
35
+ riscv_cpu_cfg(env)->ext_ssaia)) {
36
return irq;
37
}
38
39
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
40
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
41
bool use_background = false;
42
hwaddr ppn;
43
- RISCVCPU *cpu = env_archcpu(env);
44
int napot_bits = 0;
45
target_ulong napot_mask;
46
47
@@ -XXX,XX +XXX,XX @@ restart:
48
49
if (riscv_cpu_sxl(env) == MXL_RV32) {
50
ppn = pte >> PTE_PPN_SHIFT;
51
- } else if (pbmte || cpu->cfg.ext_svnapot) {
52
+ } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
53
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
54
} else {
55
ppn = pte >> PTE_PPN_SHIFT;
56
@@ -XXX,XX +XXX,XX @@ restart:
57
benefit. */
58
target_ulong vpn = addr >> PGSHIFT;
59
60
- if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
61
+ if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
62
napot_bits = ctzl(ppn) + 1;
63
if ((i != (levels - 1)) || (napot_bits != 4)) {
64
return TRANSLATE_FAIL;
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diff --git a/target/riscv/csr.c b/target/riscv/csr.c
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index XXXXXXX..XXXXXXX 100644
67
--- a/target/riscv/csr.c
68
+++ b/target/riscv/csr.c
69
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
70
71
static RISCVException vs(CPURISCVState *env, int csrno)
72
{
73
- RISCVCPU *cpu = env_archcpu(env);
74
-
75
- if (cpu->cfg.ext_zve32f) {
76
+ if (riscv_cpu_cfg(env)->ext_zve32f) {
77
#if !defined(CONFIG_USER_ONLY)
78
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
79
return RISCV_EXCP_ILLEGAL_INST;
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@@ -XXX,XX +XXX,XX @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
81
82
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
83
{
84
- RISCVCPU *cpu = env_archcpu(env);
85
-
86
- if (!cpu->cfg.ext_sscofpmf) {
87
+ if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
88
return RISCV_EXCP_ILLEGAL_INST;
89
}
90
91
@@ -XXX,XX +XXX,XX @@ static RISCVException umode32(CPURISCVState *env, int csrno)
92
93
static RISCVException mstateen(CPURISCVState *env, int csrno)
94
{
95
- RISCVCPU *cpu = env_archcpu(env);
96
-
97
- if (!cpu->cfg.ext_smstateen) {
98
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
99
return RISCV_EXCP_ILLEGAL_INST;
100
}
101
102
@@ -XXX,XX +XXX,XX @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
103
104
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
105
{
106
- RISCVCPU *cpu = env_archcpu(env);
107
-
108
- if (!cpu->cfg.ext_smstateen) {
109
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
110
return RISCV_EXCP_ILLEGAL_INST;
111
}
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113
@@ -XXX,XX +XXX,XX @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
114
115
static RISCVException sstc(CPURISCVState *env, int csrno)
116
{
117
- RISCVCPU *cpu = env_archcpu(env);
118
bool hmode_check = false;
119
120
- if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
121
+ if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
122
return RISCV_EXCP_ILLEGAL_INST;
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}
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@@ -XXX,XX +XXX,XX @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
126
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
127
target_ulong *val)
128
{
129
- RISCVCPU *cpu = env_archcpu(env);
130
-
131
- *val = cpu->cfg.mvendorid;
132
+ *val = riscv_cpu_cfg(env)->mvendorid;
133
return RISCV_EXCP_NONE;
134
}
135
136
static RISCVException read_marchid(CPURISCVState *env, int csrno,
137
target_ulong *val)
138
{
139
- RISCVCPU *cpu = env_archcpu(env);
140
-
141
- *val = cpu->cfg.marchid;
142
+ *val = riscv_cpu_cfg(env)->marchid;
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return RISCV_EXCP_NONE;
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}
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146
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
147
target_ulong *val)
148
{
149
- RISCVCPU *cpu = env_archcpu(env);
150
-
151
- *val = cpu->cfg.mimpid;
152
+ *val = riscv_cpu_cfg(env)->mimpid;
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return RISCV_EXCP_NONE;
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}
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156
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
157
158
static bool validate_vm(CPURISCVState *env, target_ulong vm)
159
{
160
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
161
-
162
- return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
163
+ return (vm & 0xf) <=
164
+ satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
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}
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static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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@@ -XXX,XX +XXX,XX @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
169
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
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target_ulong val)
171
{
172
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
174
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
175
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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@@ -XXX,XX +XXX,XX @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
178
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
179
target_ulong val)
180
{
181
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
182
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
183
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
184
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
185
(cfg->ext_svadu ? MENVCFG_HADE : 0);
186
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/riscv/gdbstub.c
189
+++ b/target/riscv/gdbstub.c
190
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
191
192
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
193
{
194
- uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
195
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
196
if (n < 32) {
197
int i;
198
int cnt = 0;
199
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
200
201
static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
202
{
203
- uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
204
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
205
if (n < 32) {
206
int i;
207
for (i = 0; i < vlenb; i += 8) {
208
--
209
2.40.0
diff view generated by jsdifflib
New patch
[PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
4
only requires PRIV_1_10_0, these sub extensions should not require priv version
5
higher than that.
6
7
The same for Zfh.
8
9
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.c | 8 ++++----
16
1 file changed, 4 insertions(+), 4 deletions(-)
17
18
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu.c
21
+++ b/target/riscv/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
23
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
24
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
25
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
26
- ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
27
+ ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
28
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
29
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
30
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
31
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
32
ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
33
ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
34
ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
35
- ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
36
- ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
37
- ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
38
+ ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f),
39
+ ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f),
40
+ ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d),
41
ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
42
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
43
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
44
--
45
2.40.0
diff view generated by jsdifflib
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
[PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
3
Use env_archcpu() to get RISCVCPU pointer from env directly.
4
been updated to use a register mapped at 0x4f000000 instead of a
5
GPIO to control whether eMMC or SD card is to be used. With this
6
support the same HSS image can be used for both eMMC and SD card
7
boot flow, while previously two different board configurations were
8
used. This is undocumented but one can take a look at the HSS code
9
HSS_MMCInit() in services/mmc/mmc_api.c.
10
4
11
With this commit, HSS image built from 2020.12 release boots again.
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
12
---
18
include/hw/riscv/microchip_pfsoc.h | 1 +
13
target/riscv/pmu.c | 8 ++++----
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
14
1 file changed, 4 insertions(+), 4 deletions(-)
20
2 files changed, 7 insertions(+)
21
15
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
16
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/riscv/microchip_pfsoc.h
18
--- a/target/riscv/pmu.c
25
+++ b/include/hw/riscv/microchip_pfsoc.h
19
+++ b/target/riscv/pmu.c
26
@@ -XXX,XX +XXX,XX @@ enum {
20
@@ -XXX,XX +XXX,XX @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
27
MICROCHIP_PFSOC_ENVM_DATA,
21
return true;
28
MICROCHIP_PFSOC_QSPI_XIP,
22
}
29
MICROCHIP_PFSOC_IOSCB,
23
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
24
- cpu = RISCV_CPU(env_cpu(env));
31
MICROCHIP_PFSOC_DRAM_LO,
25
+ cpu = env_archcpu(env);
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
26
if (!cpu->pmu_event_ctr_map) {
33
MICROCHIP_PFSOC_DRAM_HI,
27
return false;
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
28
}
35
index XXXXXXX..XXXXXXX 100644
29
@@ -XXX,XX +XXX,XX @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
36
--- a/hw/riscv/microchip_pfsoc.c
30
return true;
37
+++ b/hw/riscv/microchip_pfsoc.c
31
}
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
32
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
33
- cpu = RISCV_CPU(env_cpu(env));
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
34
+ cpu = env_archcpu(env);
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
35
if (!cpu->pmu_event_ctr_map) {
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
36
return false;
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
37
}
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
38
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
39
uint32_t ctr_idx)
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
40
{
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
41
uint32_t event_idx;
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
42
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
49
43
+ RISCVCPU *cpu = env_archcpu(env);
50
+ /* eMMC/SD mux */
44
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
45
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
46
return -1;
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
47
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
54
+
48
{
55
/* QSPI Flash */
49
uint64_t overflow_delta, overflow_at;
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
50
int64_t overflow_ns, overflow_left = 0;
57
"microchip.pfsoc.qspi_xip",
51
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
52
+ RISCVCPU *cpu = env_archcpu(env);
53
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
54
55
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
58
--
56
--
59
2.30.1
57
2.40.0
60
58
61
59
diff view generated by jsdifflib
New patch
[PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
4
riscv_timer_write_timecmp, since type converts from CPURISCVState to
5
RISCVCPU in many caller of them and then back to CPURISCVState in them.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu.h | 3 ++-
15
target/riscv/time_helper.h | 2 +-
16
target/riscv/cpu.c | 6 +++---
17
target/riscv/cpu_helper.c | 8 ++++----
18
target/riscv/csr.c | 35 +++++++++++------------------------
19
target/riscv/pmu.c | 6 +++---
20
target/riscv/time_helper.c | 15 +++++++--------
21
7 files changed, 31 insertions(+), 44 deletions(-)
22
23
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/cpu.h
26
+++ b/target/riscv/cpu.h
27
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
28
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
29
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
30
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
31
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
32
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
33
+ uint64_t value);
34
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
35
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
36
void *arg);
37
diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/time_helper.h
40
+++ b/target/riscv/time_helper.h
41
@@ -XXX,XX +XXX,XX @@
42
#include "cpu.h"
43
#include "qemu/timer.h"
44
45
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
46
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
47
uint64_t timecmp, uint64_t delta,
48
uint32_t timer_irq);
49
void riscv_timer_init(RISCVCPU *cpu);
50
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/riscv/cpu.c
53
+++ b/target/riscv/cpu.c
54
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
55
if (kvm_enabled()) {
56
kvm_riscv_set_irq(cpu, irq, level);
57
} else {
58
- riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
59
+ riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
60
}
61
break;
62
case IRQ_S_EXT:
63
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
64
kvm_riscv_set_irq(cpu, irq, level);
65
} else {
66
env->external_seip = level;
67
- riscv_cpu_update_mip(cpu, 1 << irq,
68
+ riscv_cpu_update_mip(env, 1 << irq,
69
BOOL_TO_MASK(level | env->software_seip));
70
}
71
break;
72
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
73
}
74
75
/* Update mip.SGEIP bit */
76
- riscv_cpu_update_mip(cpu, MIP_SGEIP,
77
+ riscv_cpu_update_mip(env, MIP_SGEIP,
78
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
79
} else {
80
g_assert_not_reached();
81
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/riscv/cpu_helper.c
84
+++ b/target/riscv/cpu_helper.c
85
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
86
*
87
* To solve this, we check and inject interrupt after setting V=1.
88
*/
89
- riscv_cpu_update_mip(env_archcpu(env), 0, 0);
90
+ riscv_cpu_update_mip(env, 0, 0);
91
}
92
}
93
94
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
95
}
96
}
97
98
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
99
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
100
+ uint64_t value)
101
{
102
- CPURISCVState *env = &cpu->env;
103
- CPUState *cs = CPU(cpu);
104
+ CPUState *cs = env_cpu(env);
105
uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
106
107
if (riscv_cpu_virt_enabled(env)) {
108
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/riscv/csr.c
111
+++ b/target/riscv/csr.c
112
@@ -XXX,XX +XXX,XX @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
113
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
114
target_ulong val)
115
{
116
- RISCVCPU *cpu = env_archcpu(env);
117
-
118
if (riscv_cpu_mxl(env) == MXL_RV32) {
119
env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
120
} else {
121
env->vstimecmp = val;
122
}
123
124
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
125
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
126
env->htimedelta, MIP_VSTIP);
127
128
return RISCV_EXCP_NONE;
129
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
130
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
131
target_ulong val)
132
{
133
- RISCVCPU *cpu = env_archcpu(env);
134
-
135
env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
136
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
137
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
138
env->htimedelta, MIP_VSTIP);
139
140
return RISCV_EXCP_NONE;
141
@@ -XXX,XX +XXX,XX @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
142
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
143
target_ulong val)
144
{
145
- RISCVCPU *cpu = env_archcpu(env);
146
-
147
if (riscv_cpu_virt_enabled(env)) {
148
if (env->hvictl & HVICTL_VTI) {
149
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
150
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
151
env->stimecmp = val;
152
}
153
154
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
155
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
156
157
return RISCV_EXCP_NONE;
158
}
159
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
160
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
161
target_ulong val)
162
{
163
- RISCVCPU *cpu = env_archcpu(env);
164
-
165
if (riscv_cpu_virt_enabled(env)) {
166
if (env->hvictl & HVICTL_VTI) {
167
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
168
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
169
}
170
171
env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
172
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
173
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
174
175
return RISCV_EXCP_NONE;
176
}
177
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
178
uint64_t *ret_val,
179
uint64_t new_val, uint64_t wr_mask)
180
{
181
- RISCVCPU *cpu = env_archcpu(env);
182
uint64_t old_mip, mask = wr_mask & delegable_ints;
183
uint32_t gin;
184
185
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
186
new_val |= env->external_seip * MIP_SEIP;
187
}
188
189
- if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
190
+ if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
191
get_field(env->menvcfg, MENVCFG_STCE)) {
192
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
193
mask = mask & ~(MIP_STIP | MIP_VSTIP);
194
}
195
196
if (mask) {
197
- old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
198
+ old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
199
} else {
200
old_mip = env->mip;
201
}
202
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
203
val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
204
env->hgeie = val;
205
/* Update mip.SGEIP bit */
206
- riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
207
+ riscv_cpu_update_mip(env, MIP_SGEIP,
208
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
209
return RISCV_EXCP_NONE;
210
}
211
@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
212
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
213
target_ulong val)
214
{
215
- RISCVCPU *cpu = env_archcpu(env);
216
-
217
if (!env->rdtime_fn) {
218
return RISCV_EXCP_ILLEGAL_INST;
219
}
220
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
221
env->htimedelta = val;
222
}
223
224
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
225
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
226
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
227
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
228
env->htimedelta, MIP_VSTIP);
229
}
230
231
@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
232
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
233
target_ulong val)
234
{
235
- RISCVCPU *cpu = env_archcpu(env);
236
-
237
if (!env->rdtime_fn) {
238
return RISCV_EXCP_ILLEGAL_INST;
239
}
240
241
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
242
243
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
244
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
245
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
246
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
247
env->htimedelta, MIP_VSTIP);
248
}
249
250
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/target/riscv/pmu.c
253
+++ b/target/riscv/pmu.c
254
@@ -XXX,XX +XXX,XX @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
255
/* Generate interrupt only if OF bit is clear */
256
if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
257
env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
258
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
259
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
260
}
261
} else {
262
counter->mhpmcounterh_val++;
263
@@ -XXX,XX +XXX,XX @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
264
/* Generate interrupt only if OF bit is clear */
265
if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
266
env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
267
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
268
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
269
}
270
} else {
271
counter->mhpmcounter_val++;
272
@@ -XXX,XX +XXX,XX @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
273
/* Generate interrupt only if OF bit is clear */
274
if (!(*mhpmevent_val & of_bit_mask)) {
275
*mhpmevent_val |= of_bit_mask;
276
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
277
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
278
}
279
}
280
}
281
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
282
index XXXXXXX..XXXXXXX 100644
283
--- a/target/riscv/time_helper.c
284
+++ b/target/riscv/time_helper.c
285
@@ -XXX,XX +XXX,XX @@ static void riscv_vstimer_cb(void *opaque)
286
RISCVCPU *cpu = opaque;
287
CPURISCVState *env = &cpu->env;
288
env->vstime_irq = 1;
289
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
290
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
291
}
292
293
static void riscv_stimer_cb(void *opaque)
294
{
295
RISCVCPU *cpu = opaque;
296
- riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
297
+ riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
298
}
299
300
/*
301
* Called when timecmp is written to update the QEMU timer or immediately
302
* trigger timer interrupt if mtimecmp <= current timer value.
303
*/
304
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
305
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
306
uint64_t timecmp, uint64_t delta,
307
uint32_t timer_irq)
308
{
309
uint64_t diff, ns_diff, next;
310
- CPURISCVState *env = &cpu->env;
311
RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
312
uint32_t timebase_freq = mtimer->timebase_freq;
313
uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
314
@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
315
*/
316
if (timer_irq == MIP_VSTIP) {
317
env->vstime_irq = 1;
318
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
319
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
320
} else {
321
- riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
322
+ riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
323
}
324
return;
325
}
326
@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
327
/* Clear the [VS|S]TIP bit in mip */
328
if (timer_irq == MIP_VSTIP) {
329
env->vstime_irq = 0;
330
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
331
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
332
} else {
333
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
334
+ riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
335
}
336
337
/*
338
--
339
2.40.0
diff view generated by jsdifflib
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
[PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
3
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
4
directly.
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
13
---
8
target/riscv/csr.c | 7 ++++---
14
target/riscv/csr.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 3 deletions(-)
15
1 file changed, 4 insertions(+), 8 deletions(-)
10
16
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/csr.c
19
--- a/target/riscv/csr.c
14
+++ b/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
21
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
22
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
23
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
24
int csrno,
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
25
- bool write_mask,
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
26
- RISCVCPU *cpu)
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
27
+ bool write_mask)
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
23
24
static const char valid_vm_1_10_32[16] = {
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
26
target_ulong new_value, target_ulong write_mask)
27
{
28
{
28
int ret = rmw_mip(env, 0, ret_value, new_value,
29
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
29
- write_mask & hip_writable_mask);
30
bool read_only = get_field(csrno, 0xC00) == 3;
30
+ write_mask & hvip_writable_mask);
31
int csr_min_priv = csr_ops[csrno].min_priv_ver;
31
32
32
- *ret_value &= hip_writable_mask;
33
/* ensure the CSR extension is enabled */
33
+ *ret_value &= hvip_writable_mask;
34
- if (!cpu->cfg.ext_icsr) {
34
35
+ if (!riscv_cpu_cfg(env)->ext_icsr) {
35
return ret;
36
return RISCV_EXCP_ILLEGAL_INST;
36
}
37
}
38
39
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
40
target_ulong *ret_value,
41
target_ulong new_value, target_ulong write_mask)
42
{
43
- RISCVCPU *cpu = env_archcpu(env);
44
-
45
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
46
+ RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
47
if (ret != RISCV_EXCP_NONE) {
48
return ret;
49
}
50
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
51
Int128 new_value, Int128 write_mask)
52
{
53
RISCVException ret;
54
- RISCVCPU *cpu = env_archcpu(env);
55
56
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
57
+ ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
58
if (ret != RISCV_EXCP_NONE) {
59
return ret;
60
}
37
--
61
--
38
2.30.1
62
2.40.0
39
63
40
64
diff view generated by jsdifflib
New patch
[PULL 06/89] target/riscv: refactor Zicond support
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
1
2
3
After the original Zicond support was stuck/fell through the cracks on
4
the mailing list at v3 (and a different implementation was merged in
5
the meanwhile), we need to refactor Zicond to prepare it to be reused
6
by XVentanaCondOps.
7
8
This commit lifts the common logic out into gen_czero and uses this
9
via gen_logic and 2 helper functions (effectively partial closures).
10
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
13
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
14
Acked-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/insn_trans/trans_rvzicond.c.inc | 36 ++++++++++++--------
19
1 file changed, 21 insertions(+), 15 deletions(-)
20
21
diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/insn_trans/trans_rvzicond.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/insn_trans/trans_rvzicond.c.inc
24
+++ b/target/riscv/insn_trans/trans_rvzicond.c.inc
25
@@ -XXX,XX +XXX,XX @@
26
* RISC-V translation routines for the Zicond Standard Extension.
27
*
28
* Copyright (c) 2020-2023 PLCT Lab
29
+ * Copyright (c) 2022 VRULL GmbH.
30
*
31
* This program is free software; you can redistribute it and/or modify it
32
* under the terms and conditions of the GNU General Public License,
33
@@ -XXX,XX +XXX,XX @@
34
} \
35
} while (0)
36
37
-static bool trans_czero_eqz(DisasContext *ctx, arg_czero_eqz *a)
38
+/* Emits "$rd = ($rs2 <cond> $zero) ? $zero : $rs1" */
39
+static void gen_czero(TCGv dest, TCGv src1, TCGv src2, TCGCond cond)
40
{
41
- REQUIRE_ZICOND(ctx);
42
+ TCGv zero = tcg_constant_tl(0);
43
+ tcg_gen_movcond_tl(cond, dest, src2, zero, zero, src1);
44
+}
45
46
- TCGv dest = dest_gpr(ctx, a->rd);
47
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
48
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
49
+static void gen_czero_eqz(TCGv dest, TCGv src1, TCGv src2)
50
+{
51
+ gen_czero(dest, src1, src2, TCG_COND_EQ);
52
+}
53
54
- tcg_gen_movcond_tl(TCG_COND_EQ, dest, src2, ctx->zero, ctx->zero, src1);
55
- gen_set_gpr(ctx, a->rd, dest);
56
- return true;
57
+static void gen_czero_nez(TCGv dest, TCGv src1, TCGv src2)
58
+{
59
+ gen_czero(dest, src1, src2, TCG_COND_NE);
60
}
61
62
-static bool trans_czero_nez(DisasContext *ctx, arg_czero_nez *a)
63
+static bool trans_czero_eqz(DisasContext *ctx, arg_r *a)
64
{
65
REQUIRE_ZICOND(ctx);
66
67
- TCGv dest = dest_gpr(ctx, a->rd);
68
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
69
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
70
+ return gen_logic(ctx, a, gen_czero_eqz);
71
+}
72
+
73
+static bool trans_czero_nez(DisasContext *ctx, arg_r *a)
74
+{
75
+ REQUIRE_ZICOND(ctx);
76
77
- tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, ctx->zero, ctx->zero, src1);
78
- gen_set_gpr(ctx, a->rd, dest);
79
- return true;
80
+ return gen_logic(ctx, a, gen_czero_nez);
81
}
82
--
83
2.40.0
diff view generated by jsdifflib
New patch
[PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
1
2
3
The Zicond standard extension implements the same instruction
4
semantics as XVentanaCondOps, although using different mnemonics and
5
opcodes.
6
7
Point XVentanaCondOps to the (newly implemented) Zicond implementation
8
to reduce the future maintenance burden.
9
10
Also updating MAINTAINERS as trans_xventanacondops.c.inc.
11
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
14
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
15
Acked-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
MAINTAINERS | 2 +-
20
.../insn_trans/trans_xventanacondops.c.inc | 18 +++---------------
21
2 files changed, 4 insertions(+), 16 deletions(-)
22
23
diff --git a/MAINTAINERS b/MAINTAINERS
24
index XXXXXXX..XXXXXXX 100644
25
--- a/MAINTAINERS
26
+++ b/MAINTAINERS
27
@@ -XXX,XX +XXX,XX @@ F: target/riscv/xthead*.decode
28
RISC-V XVentanaCondOps extension
29
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
30
L: qemu-riscv@nongnu.org
31
-S: Supported
32
+S: Maintained
33
F: target/riscv/XVentanaCondOps.decode
34
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
35
36
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/insn_trans/trans_xventanacondops.c.inc
39
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
40
@@ -XXX,XX +XXX,XX @@
41
/*
42
* RISC-V translation routines for the XVentanaCondOps extension.
43
*
44
- * Copyright (c) 2021-2022 VRULL GmbH.
45
+ * Copyright (c) 2021-2023 VRULL GmbH.
46
*
47
* This program is free software; you can redistribute it and/or modify it
48
* under the terms and conditions of the GNU General Public License,
49
@@ -XXX,XX +XXX,XX @@
50
* this program. If not, see <http://www.gnu.org/licenses/>.
51
*/
52
53
-static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
54
-{
55
- TCGv dest = dest_gpr(ctx, a->rd);
56
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
57
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
58
-
59
- tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
60
-
61
- gen_set_gpr(ctx, a->rd, dest);
62
- return true;
63
-}
64
-
65
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
66
{
67
- return gen_vt_condmask(ctx, a, TCG_COND_NE);
68
+ return gen_logic(ctx, a, gen_czero_eqz);
69
}
70
71
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
72
{
73
- return gen_vt_condmask(ctx, a, TCG_COND_EQ);
74
+ return gen_logic(ctx, a, gen_czero_nez);
75
}
76
--
77
2.40.0
diff view generated by jsdifflib
New patch
[PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry
1
From: Conor Dooley <conor.dooley@microchip.com>
1
2
3
dt-validate complains:
4
> soc: pmu: {'riscv,event-to-mhpmcounters':
5
> [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280],
6
> [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]],
7
> pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short
8
9
There are bogus 0 entries added at the end, of which one is of
10
insufficient length. This happens because only 15 of
11
fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is
12
called using the size of the array.
13
Reduce the array to 15 elements to make the error go away.
14
15
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-Id: <20230404173333.35179-1-conor@kernel.org>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
target/riscv/pmu.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/pmu.c
26
+++ b/target/riscv/pmu.c
27
@@ -XXX,XX +XXX,XX @@
28
*/
29
void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
30
{
31
- uint32_t fdt_event_ctr_map[20] = {};
32
+ uint32_t fdt_event_ctr_map[15] = {};
33
uint32_t cmask;
34
35
/* All the programmable counters can map to any event */
36
--
37
2.40.0
diff view generated by jsdifflib
New patch
[PULL 09/89] target/riscv: add cfg properties for Zc* extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension.
4
Add check for these properties.
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu.h | 6 ++++++
14
target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
15
2 files changed, 49 insertions(+)
16
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.h
20
+++ b/target/riscv/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
bool ext_zbkc;
23
bool ext_zbkx;
24
bool ext_zbs;
25
+ bool ext_zca;
26
+ bool ext_zcb;
27
+ bool ext_zcd;
28
+ bool ext_zcf;
29
+ bool ext_zcmp;
30
+ bool ext_zcmt;
31
bool ext_zk;
32
bool ext_zkn;
33
bool ext_zknd;
34
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu.c
37
+++ b/target/riscv/cpu.c
38
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
39
}
40
}
41
42
+ if (cpu->cfg.ext_c) {
43
+ cpu->cfg.ext_zca = true;
44
+ if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
45
+ cpu->cfg.ext_zcf = true;
46
+ }
47
+ if (cpu->cfg.ext_d) {
48
+ cpu->cfg.ext_zcd = true;
49
+ }
50
+ }
51
+
52
+ if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
53
+ error_setg(errp, "Zcf extension is only relevant to RV32");
54
+ return;
55
+ }
56
+
57
+ if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
58
+ error_setg(errp, "Zcf extension requires F extension");
59
+ return;
60
+ }
61
+
62
+ if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
63
+ error_setg(errp, "Zcd extension requires D extension");
64
+ return;
65
+ }
66
+
67
+ if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
68
+ cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
69
+ error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
70
+ "extension");
71
+ return;
72
+ }
73
+
74
+ if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
75
+ error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
76
+ "Zcd extension");
77
+ return;
78
+ }
79
+
80
+ if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
81
+ error_setg(errp, "Zcmt extension requires Zicsr extension");
82
+ return;
83
+ }
84
+
85
if (cpu->cfg.ext_zk) {
86
cpu->cfg.ext_zkn = true;
87
cpu->cfg.ext_zkr = true;
88
--
89
2.40.0
diff view generated by jsdifflib
New patch
[PULL 10/89] target/riscv: add support for Zca extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Modify the check for C extension to Zca (C implies Zca).
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
10
Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/translate.c | 8 ++++++--
14
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
15
2 files changed, 8 insertions(+), 4 deletions(-)
16
17
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/translate.c
20
+++ b/target/riscv/translate.c
21
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
22
23
/* check misaligned: */
24
next_pc = ctx->base.pc_next + imm;
25
- if (!has_ext(ctx, RVC)) {
26
+ if (!ctx->cfg_ptr->ext_zca) {
27
if ((next_pc & 0x3) != 0) {
28
gen_exception_inst_addr_mis(ctx);
29
return;
30
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
31
if (insn_len(opcode) == 2) {
32
ctx->opcode = opcode;
33
ctx->pc_succ_insn = ctx->base.pc_next + 2;
34
- if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
35
+ /*
36
+ * The Zca extension is added as way to refer to instructions in the C
37
+ * extension that do not include the floating-point loads and stores
38
+ */
39
+ if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
40
return;
41
}
42
} else {
43
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/insn_trans/trans_rvi.c.inc
46
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
47
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
48
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
49
50
gen_set_pc(ctx, cpu_pc);
51
- if (!has_ext(ctx, RVC)) {
52
+ if (!ctx->cfg_ptr->ext_zca) {
53
TCGv t0 = tcg_temp_new();
54
55
misaligned = gen_new_label();
56
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
57
58
gen_set_label(l); /* branch taken */
59
60
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
61
+ if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
62
/* misaligned */
63
gen_exception_inst_addr_mis(ctx);
64
} else {
65
--
66
2.40.0
diff view generated by jsdifflib
New patch
[PULL 11/89] target/riscv: add support for Zcf extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn16.decode | 8 ++++----
13
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++
14
2 files changed, 22 insertions(+), 4 deletions(-)
15
16
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn16.decode
19
+++ b/target/riscv/insn16.decode
20
@@ -XXX,XX +XXX,XX @@ sw 110 ... ... .. ... 00 @cs_w
21
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
22
{
23
ld 011 ... ... .. ... 00 @cl_d
24
- flw 011 ... ... .. ... 00 @cl_w
25
+ c_flw 011 ... ... .. ... 00 @cl_w
26
}
27
{
28
sd 111 ... ... .. ... 00 @cs_d
29
- fsw 111 ... ... .. ... 00 @cs_w
30
+ c_fsw 111 ... ... .. ... 00 @cs_w
31
}
32
33
# *** RV32/64C Standard Extension (Quadrant 1) ***
34
@@ -XXX,XX +XXX,XX @@ sw 110 . ..... ..... 10 @c_swsp
35
{
36
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
37
ld 011 . ..... ..... 10 @c_ldsp
38
- flw 011 . ..... ..... 10 @c_lwsp
39
+ c_flw 011 . ..... ..... 10 @c_lwsp
40
}
41
{
42
sd 111 . ..... ..... 10 @c_sdsp
43
- fsw 111 . ..... ..... 10 @c_swsp
44
+ c_fsw 111 . ..... ..... 10 @c_swsp
45
}
46
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/insn_trans/trans_rvf.c.inc
49
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
50
@@ -XXX,XX +XXX,XX @@
51
} \
52
} while (0)
53
54
+#define REQUIRE_ZCF(ctx) do { \
55
+ if (!ctx->cfg_ptr->ext_zcf) { \
56
+ return false; \
57
+ } \
58
+} while (0)
59
+
60
static bool trans_flw(DisasContext *ctx, arg_flw *a)
61
{
62
TCGv_i64 dest;
63
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
64
return true;
65
}
66
67
+static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
68
+{
69
+ REQUIRE_ZCF(ctx);
70
+ return trans_flw(ctx, a);
71
+}
72
+
73
+static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
74
+{
75
+ REQUIRE_ZCF(ctx);
76
+ return trans_fsw(ctx, a);
77
+}
78
+
79
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
80
{
81
REQUIRE_FPU;
82
--
83
2.40.0
diff view generated by jsdifflib
New patch
[PULL 12/89] target/riscv: add support for Zcd extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Separate c_fld/c_fsd from fld/fsd to add additional check for
4
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
5
their encodings.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn16.decode | 8 ++++----
15
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++
16
2 files changed, 22 insertions(+), 4 deletions(-)
17
18
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn16.decode
21
+++ b/target/riscv/insn16.decode
22
@@ -XXX,XX +XXX,XX @@
23
}
24
{
25
lq 001 ... ... .. ... 00 @cl_q
26
- fld 001 ... ... .. ... 00 @cl_d
27
+ c_fld 001 ... ... .. ... 00 @cl_d
28
}
29
lw 010 ... ... .. ... 00 @cl_w
30
{
31
sq 101 ... ... .. ... 00 @cs_q
32
- fsd 101 ... ... .. ... 00 @cs_d
33
+ c_fsd 101 ... ... .. ... 00 @cs_d
34
}
35
sw 110 ... ... .. ... 00 @cs_w
36
37
@@ -XXX,XX +XXX,XX @@ addw 100 1 11 ... 01 ... 01 @cs_2
38
slli 000 . ..... ..... 10 @c_shift2
39
{
40
lq 001 ... ... .. ... 10 @c_lqsp
41
- fld 001 . ..... ..... 10 @c_ldsp
42
+ c_fld 001 . ..... ..... 10 @c_ldsp
43
}
44
{
45
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
46
@@ -XXX,XX +XXX,XX @@ slli 000 . ..... ..... 10 @c_shift2
47
}
48
{
49
sq 101 ... ... .. ... 10 @c_sqsp
50
- fsd 101 ...... ..... 10 @c_sdsp
51
+ c_fsd 101 ...... ..... 10 @c_sdsp
52
}
53
sw 110 . ..... ..... 10 @c_swsp
54
55
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/insn_trans/trans_rvd.c.inc
58
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
59
@@ -XXX,XX +XXX,XX @@
60
} \
61
} while (0)
62
63
+#define REQUIRE_ZCD(ctx) do { \
64
+ if (!ctx->cfg_ptr->ext_zcd) { \
65
+ return false; \
66
+ } \
67
+} while (0)
68
+
69
static bool trans_fld(DisasContext *ctx, arg_fld *a)
70
{
71
TCGv addr;
72
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
73
return true;
74
}
75
76
+static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
77
+{
78
+ REQUIRE_ZCD(ctx);
79
+ return trans_fld(ctx, a);
80
+}
81
+
82
+static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
83
+{
84
+ REQUIRE_ZCD(ctx);
85
+ return trans_fsd(ctx, a);
86
+}
87
+
88
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
89
{
90
REQUIRE_FPU;
91
--
92
2.40.0
diff view generated by jsdifflib
New patch
[PULL 13/89] target/riscv: add support for Zcb extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Add encode and trans* functions support for Zcb instructions.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn16.decode | 23 +++++
13
target/riscv/translate.c | 2 +
14
target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++
15
3 files changed, 125 insertions(+)
16
create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
17
18
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn16.decode
21
+++ b/target/riscv/insn16.decode
22
@@ -XXX,XX +XXX,XX @@
23
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
24
%imm_lui 12:s1 2:5 !function=ex_shift_12
25
26
+%uimm_cl_b 5:1 6:1
27
+%uimm_cl_h 5:1 !function=ex_shift_1
28
29
# Argument sets imported from insn32.decode:
30
&empty !extern
31
@@ -XXX,XX +XXX,XX @@
32
&b imm rs2 rs1 !extern
33
&u imm rd !extern
34
&shift shamt rs1 rd !extern
35
+&r2 rd rs1 !extern
36
37
38
# Formats 16:
39
@@ -XXX,XX +XXX,XX @@
40
41
@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
42
43
+@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
44
+@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
45
+@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
46
+@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
47
+@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
48
+
49
# *** RV32/64C Standard Extension (Quadrant 0) ***
50
{
51
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
52
@@ -XXX,XX +XXX,XX @@ sw 110 . ..... ..... 10 @c_swsp
53
sd 111 . ..... ..... 10 @c_sdsp
54
c_fsw 111 . ..... ..... 10 @c_swsp
55
}
56
+
57
+# *** RV64 and RV32 Zcb Extension ***
58
+c_zext_b 100 111 ... 11 000 01 @cu
59
+c_sext_b 100 111 ... 11 001 01 @cu
60
+c_zext_h 100 111 ... 11 010 01 @cu
61
+c_sext_h 100 111 ... 11 011 01 @cu
62
+c_zext_w 100 111 ... 11 100 01 @cu
63
+c_not 100 111 ... 11 101 01 @cu
64
+c_mul 100 111 ... 10 ... 01 @cs_2
65
+c_lbu 100 000 ... .. ... 00 @cl_b
66
+c_lhu 100 001 ... 0. ... 00 @cl_h
67
+c_lh 100 001 ... 1. ... 00 @cl_h
68
+c_sb 100 010 ... .. ... 00 @cs_b
69
+c_sh 100 011 ... 0. ... 00 @cs_h
70
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/riscv/translate.c
73
+++ b/target/riscv/translate.c
74
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
75
76
/* Include the auto-generated decoder for 16 bit insn */
77
#include "decode-insn16.c.inc"
78
+#include "insn_trans/trans_rvzce.c.inc"
79
+
80
/* Include decoders for factored-out extensions */
81
#include "decode-XVentanaCondOps.c.inc"
82
83
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
84
new file mode 100644
85
index XXXXXXX..XXXXXXX
86
--- /dev/null
87
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
88
@@ -XXX,XX +XXX,XX @@
89
+/*
90
+ * RISC-V translation routines for the Zcb Standard Extension.
91
+ *
92
+ * Copyright (c) 2021-2022 PLCT Lab
93
+ *
94
+ * This program is free software; you can redistribute it and/or modify it
95
+ * under the terms and conditions of the GNU General Public License,
96
+ * version 2 or later, as published by the Free Software Foundation.
97
+ *
98
+ * This program is distributed in the hope it will be useful, but WITHOUT
99
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
100
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
101
+ * more details.
102
+ *
103
+ * You should have received a copy of the GNU General Public License along with
104
+ * this program. If not, see <http://www.gnu.org/licenses/>.
105
+ */
106
+
107
+#define REQUIRE_ZCB(ctx) do { \
108
+ if (!ctx->cfg_ptr->ext_zcb) \
109
+ return false; \
110
+} while (0)
111
+
112
+static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
113
+{
114
+ REQUIRE_ZCB(ctx);
115
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl);
116
+}
117
+
118
+static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a)
119
+{
120
+ REQUIRE_ZCB(ctx);
121
+ REQUIRE_ZBB(ctx);
122
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
123
+}
124
+
125
+static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a)
126
+{
127
+ REQUIRE_ZCB(ctx);
128
+ REQUIRE_ZBB(ctx);
129
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
130
+}
131
+
132
+static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a)
133
+{
134
+ REQUIRE_ZCB(ctx);
135
+ REQUIRE_ZBB(ctx);
136
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
137
+}
138
+
139
+static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a)
140
+{
141
+ REQUIRE_64BIT(ctx);
142
+ REQUIRE_ZCB(ctx);
143
+ REQUIRE_ZBA(ctx);
144
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl);
145
+}
146
+
147
+static bool trans_c_not(DisasContext *ctx, arg_c_not *a)
148
+{
149
+ REQUIRE_ZCB(ctx);
150
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl);
151
+}
152
+
153
+static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a)
154
+{
155
+ REQUIRE_ZCB(ctx);
156
+ REQUIRE_M_OR_ZMMUL(ctx);
157
+ return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
158
+}
159
+
160
+static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
161
+{
162
+ REQUIRE_ZCB(ctx);
163
+ return gen_load(ctx, a, MO_UB);
164
+}
165
+
166
+static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
167
+{
168
+ REQUIRE_ZCB(ctx);
169
+ return gen_load(ctx, a, MO_UW);
170
+}
171
+
172
+static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
173
+{
174
+ REQUIRE_ZCB(ctx);
175
+ return gen_load(ctx, a, MO_SW);
176
+}
177
+
178
+static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
179
+{
180
+ REQUIRE_ZCB(ctx);
181
+ return gen_store(ctx, a, MO_UB);
182
+}
183
+
184
+static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
185
+{
186
+ REQUIRE_ZCB(ctx);
187
+ return gen_store(ctx, a, MO_UW);
188
+}
189
--
190
2.40.0
diff view generated by jsdifflib
New patch
[PULL 14/89] target/riscv: add support for Zcmp extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Add encode, trans* functions for Zcmp instructions.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn16.decode | 18 +++
13
target/riscv/translate.c | 5 +
14
target/riscv/insn_trans/trans_rvzce.c.inc | 187 +++++++++++++++++++++-
15
3 files changed, 209 insertions(+), 1 deletion(-)
16
17
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn16.decode
20
+++ b/target/riscv/insn16.decode
21
@@ -XXX,XX +XXX,XX @@
22
%rs1_3 7:3 !function=ex_rvc_register
23
%rs2_3 2:3 !function=ex_rvc_register
24
%rs2_5 2:5
25
+%r1s 7:3 !function=ex_sreg_register
26
+%r2s 2:3 !function=ex_sreg_register
27
28
# Immediates:
29
%imm_ci 12:s1 2:5
30
@@ -XXX,XX +XXX,XX @@
31
32
%uimm_cl_b 5:1 6:1
33
%uimm_cl_h 5:1 !function=ex_shift_1
34
+%spimm 2:2 !function=ex_shift_4
35
+%urlist 4:4
36
37
# Argument sets imported from insn32.decode:
38
&empty !extern
39
@@ -XXX,XX +XXX,XX @@
40
&u imm rd !extern
41
&shift shamt rs1 rd !extern
42
&r2 rd rs1 !extern
43
+&r2_s rs1 rs2 !extern
44
45
+&cmpp urlist spimm
46
47
# Formats 16:
48
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
49
@@ -XXX,XX +XXX,XX @@
50
@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
51
@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
52
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
53
+@cm_pp ... ... ........ .. &cmpp %urlist %spimm
54
+@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
55
56
# *** RV32/64C Standard Extension (Quadrant 0) ***
57
{
58
@@ -XXX,XX +XXX,XX @@ slli 000 . ..... ..... 10 @c_shift2
59
{
60
sq 101 ... ... .. ... 10 @c_sqsp
61
c_fsd 101 ...... ..... 10 @c_sdsp
62
+
63
+ # *** RV64 and RV32 Zcmp Extension ***
64
+ [
65
+ cm_push 101 11000 .... .. 10 @cm_pp
66
+ cm_pop 101 11010 .... .. 10 @cm_pp
67
+ cm_popret 101 11110 .... .. 10 @cm_pp
68
+ cm_popretz 101 11100 .... .. 10 @cm_pp
69
+ cm_mva01s 101 011 ... 11 ... 10 @cm_mv
70
+ cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
71
+ ]
72
}
73
sw 110 . ..... ..... 10 @c_swsp
74
75
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/riscv/translate.c
78
+++ b/target/riscv/translate.c
79
@@ -XXX,XX +XXX,XX @@ static int ex_rvc_register(DisasContext *ctx, int reg)
80
return 8 + reg;
81
}
82
83
+static int ex_sreg_register(DisasContext *ctx, int reg)
84
+{
85
+ return reg < 2 ? reg + 8 : reg + 16;
86
+}
87
+
88
static int ex_rvc_shiftli(DisasContext *ctx, int imm)
89
{
90
/* For RV128 a shamt of 0 means a shift by 64. */
91
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
94
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
95
@@ -XXX,XX +XXX,XX @@
96
/*
97
- * RISC-V translation routines for the Zcb Standard Extension.
98
+ * RISC-V translation routines for the Zc[b,mp] Standard Extensions.
99
*
100
* Copyright (c) 2021-2022 PLCT Lab
101
*
102
@@ -XXX,XX +XXX,XX @@
103
return false; \
104
} while (0)
105
106
+#define REQUIRE_ZCMP(ctx) do { \
107
+ if (!ctx->cfg_ptr->ext_zcmp) \
108
+ return false; \
109
+} while (0)
110
+
111
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
112
{
113
REQUIRE_ZCB(ctx);
114
@@ -XXX,XX +XXX,XX @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
115
REQUIRE_ZCB(ctx);
116
return gen_store(ctx, a, MO_UW);
117
}
118
+
119
+#define X_S0 8
120
+#define X_S1 9
121
+#define X_Sn 16
122
+
123
+static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
124
+{
125
+ uint32_t reg_bitmap = 0;
126
+
127
+ if (ctx->cfg_ptr->ext_e && rlist > 6) {
128
+ return 0;
129
+ }
130
+
131
+ switch (rlist) {
132
+ case 15:
133
+ reg_bitmap |= 1 << (X_Sn + 11) ;
134
+ reg_bitmap |= 1 << (X_Sn + 10) ;
135
+ /* FALL THROUGH */
136
+ case 14:
137
+ reg_bitmap |= 1 << (X_Sn + 9) ;
138
+ /* FALL THROUGH */
139
+ case 13:
140
+ reg_bitmap |= 1 << (X_Sn + 8) ;
141
+ /* FALL THROUGH */
142
+ case 12:
143
+ reg_bitmap |= 1 << (X_Sn + 7) ;
144
+ /* FALL THROUGH */
145
+ case 11:
146
+ reg_bitmap |= 1 << (X_Sn + 6) ;
147
+ /* FALL THROUGH */
148
+ case 10:
149
+ reg_bitmap |= 1 << (X_Sn + 5) ;
150
+ /* FALL THROUGH */
151
+ case 9:
152
+ reg_bitmap |= 1 << (X_Sn + 4) ;
153
+ /* FALL THROUGH */
154
+ case 8:
155
+ reg_bitmap |= 1 << (X_Sn + 3) ;
156
+ /* FALL THROUGH */
157
+ case 7:
158
+ reg_bitmap |= 1 << (X_Sn + 2) ;
159
+ /* FALL THROUGH */
160
+ case 6:
161
+ reg_bitmap |= 1 << X_S1 ;
162
+ /* FALL THROUGH */
163
+ case 5:
164
+ reg_bitmap |= 1 << X_S0;
165
+ /* FALL THROUGH */
166
+ case 4:
167
+ reg_bitmap |= 1 << xRA;
168
+ break;
169
+ default:
170
+ break;
171
+ }
172
+
173
+ return reg_bitmap;
174
+}
175
+
176
+static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
177
+{
178
+ REQUIRE_ZCMP(ctx);
179
+
180
+ uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist);
181
+ if (reg_bitmap == 0) {
182
+ return false;
183
+ }
184
+
185
+ MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
186
+ int reg_size = memop_size(memop);
187
+ target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) +
188
+ a->spimm;
189
+ TCGv sp = dest_gpr(ctx, xSP);
190
+ TCGv addr = tcg_temp_new();
191
+ int i;
192
+
193
+ tcg_gen_addi_tl(addr, sp, stack_adj - reg_size);
194
+
195
+ for (i = X_Sn + 11; i >= 0; i--) {
196
+ if (reg_bitmap & (1 << i)) {
197
+ TCGv dest = dest_gpr(ctx, i);
198
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
199
+ gen_set_gpr(ctx, i, dest);
200
+ tcg_gen_subi_tl(addr, addr, reg_size);
201
+ }
202
+ }
203
+
204
+ tcg_gen_addi_tl(sp, sp, stack_adj);
205
+ gen_set_gpr(ctx, xSP, sp);
206
+
207
+ if (ret_val) {
208
+ gen_set_gpr(ctx, xA0, ctx->zero);
209
+ }
210
+
211
+ if (ret) {
212
+ TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE);
213
+ gen_set_pc(ctx, ret_addr);
214
+ tcg_gen_lookup_and_goto_ptr();
215
+ ctx->base.is_jmp = DISAS_NORETURN;
216
+ }
217
+
218
+ return true;
219
+}
220
+
221
+static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a)
222
+{
223
+ REQUIRE_ZCMP(ctx);
224
+
225
+ uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist);
226
+ if (reg_bitmap == 0) {
227
+ return false;
228
+ }
229
+
230
+ MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
231
+ int reg_size = memop_size(memop);
232
+ target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) +
233
+ a->spimm;
234
+ TCGv sp = dest_gpr(ctx, xSP);
235
+ TCGv addr = tcg_temp_new();
236
+ int i;
237
+
238
+ tcg_gen_subi_tl(addr, sp, reg_size);
239
+
240
+ for (i = X_Sn + 11; i >= 0; i--) {
241
+ if (reg_bitmap & (1 << i)) {
242
+ TCGv val = get_gpr(ctx, i, EXT_NONE);
243
+ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, memop);
244
+ tcg_gen_subi_tl(addr, addr, reg_size);
245
+ }
246
+ }
247
+
248
+ tcg_gen_subi_tl(sp, sp, stack_adj);
249
+ gen_set_gpr(ctx, xSP, sp);
250
+
251
+ return true;
252
+}
253
+
254
+static bool trans_cm_pop(DisasContext *ctx, arg_cm_pop *a)
255
+{
256
+ return gen_pop(ctx, a, false, false);
257
+}
258
+
259
+static bool trans_cm_popret(DisasContext *ctx, arg_cm_popret *a)
260
+{
261
+ return gen_pop(ctx, a, true, false);
262
+}
263
+
264
+static bool trans_cm_popretz(DisasContext *ctx, arg_cm_popret *a)
265
+{
266
+ return gen_pop(ctx, a, true, true);
267
+}
268
+
269
+static bool trans_cm_mva01s(DisasContext *ctx, arg_cm_mva01s *a)
270
+{
271
+ REQUIRE_ZCMP(ctx);
272
+
273
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
274
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
275
+
276
+ gen_set_gpr(ctx, xA0, src1);
277
+ gen_set_gpr(ctx, xA1, src2);
278
+
279
+ return true;
280
+}
281
+
282
+static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a)
283
+{
284
+ REQUIRE_ZCMP(ctx);
285
+
286
+ if (a->rs1 == a->rs2) {
287
+ return false;
288
+ }
289
+
290
+ TCGv a0 = get_gpr(ctx, xA0, EXT_NONE);
291
+ TCGv a1 = get_gpr(ctx, xA1, EXT_NONE);
292
+
293
+ gen_set_gpr(ctx, a->rs1, a0);
294
+ gen_set_gpr(ctx, a->rs2, a1);
295
+
296
+ return true;
297
+}
298
--
299
2.40.0
diff view generated by jsdifflib
New patch
[PULL 15/89] target/riscv: add support for Zcmt extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Add encode, trans* functions and helper functions support for Zcmt
4
instrutions.
5
Add support for jvt csr.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu.h | 4 ++
15
target/riscv/cpu_bits.h | 7 +++
16
target/riscv/helper.h | 3 ++
17
target/riscv/insn16.decode | 7 ++-
18
target/riscv/csr.c | 36 ++++++++++++++-
19
target/riscv/machine.c | 19 ++++++++
20
target/riscv/zce_helper.c | 55 +++++++++++++++++++++++
21
target/riscv/insn_trans/trans_rvzce.c.inc | 28 +++++++++++-
22
target/riscv/meson.build | 3 +-
23
9 files changed, 157 insertions(+), 5 deletions(-)
24
create mode 100644 target/riscv/zce_helper.c
25
26
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.h
29
+++ b/target/riscv/cpu.h
30
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
31
/* 128-bit helpers upper part return value */
32
target_ulong retxh;
33
34
+ target_ulong jvt;
35
+
36
#ifdef CONFIG_USER_ONLY
37
uint32_t elf_flags;
38
#endif
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
40
target_ulong new_val,
41
target_ulong write_mask),
42
void *rmw_fn_arg);
43
+
44
+RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
45
#endif
46
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
47
48
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/cpu_bits.h
51
+++ b/target/riscv/cpu_bits.h
52
@@ -XXX,XX +XXX,XX @@
53
#define SMSTATEEN_MAX_COUNT 4
54
#define SMSTATEEN0_CS (1ULL << 0)
55
#define SMSTATEEN0_FCSR (1ULL << 1)
56
+#define SMSTATEEN0_JVT (1ULL << 2)
57
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
58
#define SMSTATEEN0_IMSIC (1ULL << 58)
59
#define SMSTATEEN0_AIA (1ULL << 59)
60
@@ -XXX,XX +XXX,XX @@
61
/* Crypto Extension */
62
#define CSR_SEED 0x015
63
64
+/* Zcmt Extension */
65
+#define CSR_JVT 0x017
66
+
67
/* mstatus CSR bits */
68
#define MSTATUS_UIE 0x00000001
69
#define MSTATUS_SIE 0x00000002
70
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
71
#define MHPMEVENT_IDX_MASK 0xFFFFF
72
#define MHPMEVENT_SSCOF_RESVD 16
73
74
+/* JVT CSR bits */
75
+#define JVT_MODE 0x3F
76
+#define JVT_BASE (~0x3F)
77
#endif
78
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/riscv/helper.h
81
+++ b/target/riscv/helper.h
82
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
83
84
DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
85
DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
86
+
87
+/* Zce helper */
88
+DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32)
89
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/riscv/insn16.decode
92
+++ b/target/riscv/insn16.decode
93
@@ -XXX,XX +XXX,XX @@
94
%uimm_cl_h 5:1 !function=ex_shift_1
95
%spimm 2:2 !function=ex_shift_4
96
%urlist 4:4
97
+%index 2:8
98
99
# Argument sets imported from insn32.decode:
100
&empty !extern
101
@@ -XXX,XX +XXX,XX @@
102
&r2_s rs1 rs2 !extern
103
104
&cmpp urlist spimm
105
+&cmjt index
106
107
# Formats 16:
108
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
109
@@ -XXX,XX +XXX,XX @@
110
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
111
@cm_pp ... ... ........ .. &cmpp %urlist %spimm
112
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
113
+@cm_jt ... ... ........ .. &cmjt %index
114
115
# *** RV32/64C Standard Extension (Quadrant 0) ***
116
{
117
@@ -XXX,XX +XXX,XX @@ slli 000 . ..... ..... 10 @c_shift2
118
sq 101 ... ... .. ... 10 @c_sqsp
119
c_fsd 101 ...... ..... 10 @c_sdsp
120
121
- # *** RV64 and RV32 Zcmp Extension ***
122
+ # *** RV64 and RV32 Zcmp/Zcmt Extension ***
123
[
124
cm_push 101 11000 .... .. 10 @cm_pp
125
cm_pop 101 11010 .... .. 10 @cm_pp
126
@@ -XXX,XX +XXX,XX @@ slli 000 . ..... ..... 10 @c_shift2
127
cm_popretz 101 11100 .... .. 10 @cm_pp
128
cm_mva01s 101 011 ... 11 ... 10 @cm_mv
129
cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
130
+
131
+ cm_jalt 101 000 ........ 10 @cm_jt
132
]
133
}
134
sw 110 . ..... ..... 10 @c_swsp
135
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/target/riscv/csr.c
138
+++ b/target/riscv/csr.c
139
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
140
141
/* Predicates */
142
#if !defined(CONFIG_USER_ONLY)
143
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
144
- uint64_t bit)
145
+RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
146
{
147
bool virt = riscv_cpu_virt_enabled(env);
148
149
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
150
return ctr(env, csrno);
151
}
152
153
+static RISCVException zcmt(CPURISCVState *env, int csrno)
154
+{
155
+ if (!riscv_cpu_cfg(env)->ext_zcmt) {
156
+ return RISCV_EXCP_ILLEGAL_INST;
157
+ }
158
+
159
+#if !defined(CONFIG_USER_ONLY)
160
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
161
+ if (ret != RISCV_EXCP_NONE) {
162
+ return ret;
163
+ }
164
+#endif
165
+
166
+ return RISCV_EXCP_NONE;
167
+}
168
+
169
#if !defined(CONFIG_USER_ONLY)
170
static RISCVException mctr(CPURISCVState *env, int csrno)
171
{
172
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
173
return ret;
174
}
175
176
+static RISCVException read_jvt(CPURISCVState *env, int csrno,
177
+ target_ulong *val)
178
+{
179
+ *val = env->jvt;
180
+ return RISCV_EXCP_NONE;
181
+}
182
+
183
+static RISCVException write_jvt(CPURISCVState *env, int csrno,
184
+ target_ulong val)
185
+{
186
+ env->jvt = val;
187
+ return RISCV_EXCP_NONE;
188
+}
189
+
190
/* Control and Status Register function table */
191
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
192
/* User Floating-Point CSRs */
193
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
194
/* Crypto Extension */
195
[CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
196
197
+ /* Zcmt Extension */
198
+ [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt},
199
+
200
#if !defined(CONFIG_USER_ONLY)
201
/* Machine Timers and Counters */
202
[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
203
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/target/riscv/machine.c
206
+++ b/target/riscv/machine.c
207
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = {
208
}
209
};
210
211
+static bool jvt_needed(void *opaque)
212
+{
213
+ RISCVCPU *cpu = opaque;
214
+
215
+ return cpu->cfg.ext_zcmt;
216
+}
217
+
218
+static const VMStateDescription vmstate_jvt = {
219
+ .name = "cpu/jvt",
220
+ .version_id = 1,
221
+ .minimum_version_id = 1,
222
+ .needed = jvt_needed,
223
+ .fields = (VMStateField[]) {
224
+ VMSTATE_UINTTL(env.jvt, RISCVCPU),
225
+ VMSTATE_END_OF_LIST()
226
+ }
227
+};
228
+
229
const VMStateDescription vmstate_riscv_cpu = {
230
.name = "cpu",
231
.version_id = 7,
232
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
233
&vmstate_envcfg,
234
&vmstate_debug,
235
&vmstate_smstateen,
236
+ &vmstate_jvt,
237
NULL
238
}
239
};
240
diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
241
new file mode 100644
242
index XXXXXXX..XXXXXXX
243
--- /dev/null
244
+++ b/target/riscv/zce_helper.c
245
@@ -XXX,XX +XXX,XX @@
246
+/*
247
+ * RISC-V Zcmt Extension Helper for QEMU.
248
+ *
249
+ * Copyright (c) 2021-2022 PLCT Lab
250
+ *
251
+ * This program is free software; you can redistribute it and/or modify it
252
+ * under the terms and conditions of the GNU General Public License,
253
+ * version 2 or later, as published by the Free Software Foundation.
254
+ *
255
+ * This program is distributed in the hope it will be useful, but WITHOUT
256
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
257
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
258
+ * more details.
259
+ *
260
+ * You should have received a copy of the GNU General Public License along with
261
+ * this program. If not, see <http://www.gnu.org/licenses/>.
262
+ */
263
+
264
+#include "qemu/osdep.h"
265
+#include "cpu.h"
266
+#include "exec/exec-all.h"
267
+#include "exec/helper-proto.h"
268
+#include "exec/cpu_ldst.h"
269
+
270
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
271
+{
272
+
273
+#if !defined(CONFIG_USER_ONLY)
274
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
275
+ if (ret != RISCV_EXCP_NONE) {
276
+ riscv_raise_exception(env, ret, 0);
277
+ }
278
+#endif
279
+
280
+ target_ulong target;
281
+ target_ulong val = env->jvt;
282
+ int xlen = riscv_cpu_xlen(env);
283
+ uint8_t mode = get_field(val, JVT_MODE);
284
+ target_ulong base = val & JVT_BASE;
285
+ target_ulong t0;
286
+
287
+ if (mode != 0) {
288
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0);
289
+ }
290
+
291
+ if (xlen == 32) {
292
+ t0 = base + (index << 2);
293
+ target = cpu_ldl_code(env, t0);
294
+ } else {
295
+ t0 = base + (index << 3);
296
+ target = cpu_ldq_code(env, t0);
297
+ }
298
+
299
+ return target & ~0x1;
300
+}
301
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
302
index XXXXXXX..XXXXXXX 100644
303
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
304
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
305
@@ -XXX,XX +XXX,XX @@
306
/*
307
- * RISC-V translation routines for the Zc[b,mp] Standard Extensions.
308
+ * RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions.
309
*
310
* Copyright (c) 2021-2022 PLCT Lab
311
*
312
@@ -XXX,XX +XXX,XX @@
313
return false; \
314
} while (0)
315
316
+#define REQUIRE_ZCMT(ctx) do { \
317
+ if (!ctx->cfg_ptr->ext_zcmt) \
318
+ return false; \
319
+} while (0)
320
+
321
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
322
{
323
REQUIRE_ZCB(ctx);
324
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a)
325
326
return true;
327
}
328
+
329
+static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
330
+{
331
+ REQUIRE_ZCMT(ctx);
332
+
333
+ /*
334
+ * Update pc to current for the non-unwinding exception
335
+ * that might come from cpu_ld*_code() in the helper.
336
+ */
337
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
338
+ gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
339
+
340
+ /* c.jt vs c.jalt depends on the index. */
341
+ if (a->index >= 32) {
342
+ gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
343
+ }
344
+
345
+ tcg_gen_lookup_and_goto_ptr();
346
+ ctx->base.is_jmp = DISAS_NORETURN;
347
+ return true;
348
+}
349
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
350
index XXXXXXX..XXXXXXX 100644
351
--- a/target/riscv/meson.build
352
+++ b/target/riscv/meson.build
353
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
354
'bitmanip_helper.c',
355
'translate.c',
356
'm128_helper.c',
357
- 'crypto_helper.c'
358
+ 'crypto_helper.c',
359
+ 'zce_helper.c'
360
))
361
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
362
363
--
364
2.40.0
diff view generated by jsdifflib
New patch
[PULL 16/89] target/riscv: expose properties for Zc* extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/cpu.c | 14 ++++++++++++++
12
1 file changed, 14 insertions(+)
13
14
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu.c
17
+++ b/target/riscv/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
19
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
20
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
21
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
22
+ ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
23
+ ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
24
+ ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
25
+ ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
26
+ ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
27
+ ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
28
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
29
ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
30
ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
31
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
32
/* These are experimental so mark with 'x-' */
33
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
34
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
35
+
36
+ DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
37
+ DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
38
+ DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
39
+ DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
40
+ DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
41
+ DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
42
+
43
/* ePMP 0.9.3 */
44
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
45
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
46
--
47
2.40.0
diff view generated by jsdifflib
New patch
[PULL 17/89] disas/riscv.c: add disasm support for Zc*
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
4
instructions currently.
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
disas/riscv.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++-
13
1 file changed, 227 insertions(+), 1 deletion(-)
14
15
diff --git a/disas/riscv.c b/disas/riscv.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/disas/riscv.c
18
+++ b/disas/riscv.c
19
@@ -XXX,XX +XXX,XX @@ typedef enum {
20
rv_codec_v_i,
21
rv_codec_vsetvli,
22
rv_codec_vsetivli,
23
+ rv_codec_zcb_ext,
24
+ rv_codec_zcb_mul,
25
+ rv_codec_zcb_lb,
26
+ rv_codec_zcb_lh,
27
+ rv_codec_zcmp_cm_pushpop,
28
+ rv_codec_zcmp_cm_mv,
29
+ rv_codec_zcmt_jt,
30
} rv_codec;
31
32
typedef enum {
33
@@ -XXX,XX +XXX,XX @@ typedef enum {
34
rv_op_vsetvli = 766,
35
rv_op_vsetivli = 767,
36
rv_op_vsetvl = 768,
37
+ rv_op_c_zext_b = 769,
38
+ rv_op_c_sext_b = 770,
39
+ rv_op_c_zext_h = 771,
40
+ rv_op_c_sext_h = 772,
41
+ rv_op_c_zext_w = 773,
42
+ rv_op_c_not = 774,
43
+ rv_op_c_mul = 775,
44
+ rv_op_c_lbu = 776,
45
+ rv_op_c_lhu = 777,
46
+ rv_op_c_lh = 778,
47
+ rv_op_c_sb = 779,
48
+ rv_op_c_sh = 780,
49
+ rv_op_cm_push = 781,
50
+ rv_op_cm_pop = 782,
51
+ rv_op_cm_popret = 783,
52
+ rv_op_cm_popretz = 784,
53
+ rv_op_cm_mva01s = 785,
54
+ rv_op_cm_mvsa01 = 786,
55
+ rv_op_cm_jt = 787,
56
+ rv_op_cm_jalt = 788,
57
} rv_op;
58
59
/* structures */
60
@@ -XXX,XX +XXX,XX @@ typedef struct {
61
uint8_t rnum;
62
uint8_t vm;
63
uint32_t vzimm;
64
+ uint8_t rlist;
65
} rv_decode;
66
67
typedef struct {
68
@@ -XXX,XX +XXX,XX @@ static const char rv_vreg_name_sym[32][4] = {
69
#define rv_fmt_vd_vm "O\tDm"
70
#define rv_fmt_vsetvli "O\t0,1,v"
71
#define rv_fmt_vsetivli "O\t0,u,v"
72
+#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
73
+#define rv_fmt_push_rlist "O\tx,-i"
74
+#define rv_fmt_pop_rlist "O\tx,i"
75
+#define rv_fmt_zcmt_index "O\ti"
76
77
/* pseudo-instruction constraints */
78
79
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
80
{ "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
81
{ "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
82
{ "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
83
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
84
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
85
+ { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
86
+ { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
87
+ { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
88
+ { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
89
+ { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
90
+ { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
91
+ { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
92
+ { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
93
+ { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
94
+ { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
95
+ { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
96
+ { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
97
+ { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
98
+ { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
99
+ { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
100
+ { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
101
+ { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
102
+ { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
103
+ { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
104
+ { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
105
};
106
107
/* CSR names */
108
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
109
case 0x000a: return "vxrm";
110
case 0x000f: return "vcsr";
111
case 0x0015: return "seed";
112
+ case 0x0017: return "jvt";
113
case 0x0040: return "uscratch";
114
case 0x0041: return "uepc";
115
case 0x0042: return "ucause";
116
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
117
op = rv_op_c_ld;
118
}
119
break;
120
+ case 4:
121
+ switch ((inst >> 10) & 0b111) {
122
+ case 0: op = rv_op_c_lbu; break;
123
+ case 1:
124
+ if (((inst >> 6) & 1) == 0) {
125
+ op = rv_op_c_lhu;
126
+ } else {
127
+ op = rv_op_c_lh;
128
+ }
129
+ break;
130
+ case 2: op = rv_op_c_sb; break;
131
+ case 3:
132
+ if (((inst >> 6) & 1) == 0) {
133
+ op = rv_op_c_sh;
134
+ }
135
+ break;
136
+ }
137
+ break;
138
case 5:
139
if (isa == rv128) {
140
op = rv_op_c_sq;
141
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
142
case 3: op = rv_op_c_and; break;
143
case 4: op = rv_op_c_subw; break;
144
case 5: op = rv_op_c_addw; break;
145
+ case 6: op = rv_op_c_mul; break;
146
+ case 7:
147
+ switch ((inst >> 2) & 0b111) {
148
+ case 0: op = rv_op_c_zext_b; break;
149
+ case 1: op = rv_op_c_sext_b; break;
150
+ case 2: op = rv_op_c_zext_h; break;
151
+ case 3: op = rv_op_c_sext_h; break;
152
+ case 4: op = rv_op_c_zext_w; break;
153
+ case 5: op = rv_op_c_not; break;
154
+ }
155
+ break;
156
}
157
break;
158
}
159
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
160
op = rv_op_c_sqsp;
161
} else {
162
op = rv_op_c_fsdsp;
163
+ if (((inst >> 12) & 0b01)) {
164
+ switch ((inst >> 8) & 0b01111) {
165
+ case 8:
166
+ if (((inst >> 4) & 0b01111) >= 4) {
167
+ op = rv_op_cm_push;
168
+ }
169
+ break;
170
+ case 10:
171
+ if (((inst >> 4) & 0b01111) >= 4) {
172
+ op = rv_op_cm_pop;
173
+ }
174
+ break;
175
+ case 12:
176
+ if (((inst >> 4) & 0b01111) >= 4) {
177
+ op = rv_op_cm_popretz;
178
+ }
179
+ break;
180
+ case 14:
181
+ if (((inst >> 4) & 0b01111) >= 4) {
182
+ op = rv_op_cm_popret;
183
+ }
184
+ break;
185
+ }
186
+ } else {
187
+ switch ((inst >> 10) & 0b011) {
188
+ case 0:
189
+ if (((inst >> 2) & 0xFF) >= 32) {
190
+ op = rv_op_cm_jalt;
191
+ } else {
192
+ op = rv_op_cm_jt;
193
+ }
194
+ break;
195
+ case 3:
196
+ switch ((inst >> 5) & 0b011) {
197
+ case 1: op = rv_op_cm_mvsa01; break;
198
+ case 3: op = rv_op_cm_mva01s; break;
199
+ }
200
+ break;
201
+ }
202
+ }
203
}
204
break;
205
case 6: op = rv_op_c_swsp; break;
206
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_crs2q(rv_inst inst)
207
return (inst << 59) >> 61;
208
}
209
210
+static uint32_t calculate_xreg(uint32_t sreg)
211
+{
212
+ return sreg < 2 ? sreg + 8 : sreg + 16;
213
+}
214
+
215
+static uint32_t operand_sreg1(rv_inst inst)
216
+{
217
+ return calculate_xreg((inst << 54) >> 61);
218
+}
219
+
220
+static uint32_t operand_sreg2(rv_inst inst)
221
+{
222
+ return calculate_xreg((inst << 59) >> 61);
223
+}
224
+
225
static uint32_t operand_crd(rv_inst inst)
226
{
227
return (inst << 52) >> 59;
228
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_vm(rv_inst inst)
229
return (inst << 38) >> 63;
230
}
231
232
+static uint32_t operand_uimm_c_lb(rv_inst inst)
233
+{
234
+ return (((inst << 58) >> 63) << 1) |
235
+ ((inst << 57) >> 63);
236
+}
237
+
238
+static uint32_t operand_uimm_c_lh(rv_inst inst)
239
+{
240
+ return (((inst << 58) >> 63) << 1);
241
+}
242
+
243
+static uint32_t operand_zcmp_spimm(rv_inst inst)
244
+{
245
+ return ((inst << 60) >> 62) << 4;
246
+}
247
+
248
+static uint32_t operand_zcmp_rlist(rv_inst inst)
249
+{
250
+ return ((inst << 56) >> 60);
251
+}
252
+
253
+static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
254
+{
255
+ int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
256
+ int regs = rlist == 15 ? 13 : rlist - 3;
257
+ uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
258
+ return stack_adj_base + spimm;
259
+}
260
+
261
+static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
262
+{
263
+ return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
264
+ operand_zcmp_spimm(inst));
265
+}
266
+
267
+static uint32_t operand_tbl_index(rv_inst inst)
268
+{
269
+ return ((inst << 54) >> 56);
270
+}
271
+
272
/* decode operands */
273
274
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
275
@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
276
dec->imm = operand_vimm(inst);
277
dec->vzimm = operand_vzimm10(inst);
278
break;
279
+ case rv_codec_zcb_lb:
280
+ dec->rs1 = operand_crs1q(inst) + 8;
281
+ dec->rs2 = operand_crs2q(inst) + 8;
282
+ dec->imm = operand_uimm_c_lb(inst);
283
+ break;
284
+ case rv_codec_zcb_lh:
285
+ dec->rs1 = operand_crs1q(inst) + 8;
286
+ dec->rs2 = operand_crs2q(inst) + 8;
287
+ dec->imm = operand_uimm_c_lh(inst);
288
+ break;
289
+ case rv_codec_zcb_ext:
290
+ dec->rd = operand_crs1q(inst) + 8;
291
+ break;
292
+ case rv_codec_zcb_mul:
293
+ dec->rd = operand_crs1rdq(inst) + 8;
294
+ dec->rs2 = operand_crs2q(inst) + 8;
295
+ break;
296
+ case rv_codec_zcmp_cm_pushpop:
297
+ dec->imm = operand_zcmp_stack_adj(inst, isa);
298
+ dec->rlist = operand_zcmp_rlist(inst);
299
+ break;
300
+ case rv_codec_zcmp_cm_mv:
301
+ dec->rd = operand_sreg1(inst);
302
+ dec->rs2 = operand_sreg2(inst);
303
+ break;
304
+ case rv_codec_zcmt_jt:
305
+ dec->imm = operand_tbl_index(inst);
306
+ break;
307
};
308
}
309
310
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
311
case ')':
312
append(buf, ")", buflen);
313
break;
314
+ case '-':
315
+ append(buf, "-", buflen);
316
+ break;
317
case 'b':
318
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
319
append(buf, tmp, buflen);
320
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
321
append(buf, vma, buflen);
322
break;
323
}
324
+ case 'x': {
325
+ switch (dec->rlist) {
326
+ case 4:
327
+ snprintf(tmp, sizeof(tmp), "{ra}");
328
+ break;
329
+ case 5:
330
+ snprintf(tmp, sizeof(tmp), "{ra, s0}");
331
+ break;
332
+ case 15:
333
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
334
+ break;
335
+ default:
336
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
337
+ break;
338
+ }
339
+ append(buf, tmp, buflen);
340
+ break;
341
+ }
342
default:
343
break;
344
}
345
--
346
2.40.0
diff view generated by jsdifflib
New patch
[PULL 18/89] target/riscv: Add support for Zce
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Add and expose property for Zce:
4
* Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt.
5
* Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu.h | 1 +
14
target/riscv/cpu.c | 12 ++++++++++++
15
2 files changed, 13 insertions(+)
16
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.h
20
+++ b/target/riscv/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
22
bool ext_zca;
23
bool ext_zcb;
24
bool ext_zcd;
25
+ bool ext_zce;
26
bool ext_zcf;
27
bool ext_zcmp;
28
bool ext_zcmt;
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/riscv/cpu.c
32
+++ b/target/riscv/cpu.c
33
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
34
ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
35
ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
36
ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
37
+ ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce),
38
ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
39
ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
40
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
41
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
42
}
43
}
44
45
+ if (cpu->cfg.ext_zce) {
46
+ cpu->cfg.ext_zca = true;
47
+ cpu->cfg.ext_zcb = true;
48
+ cpu->cfg.ext_zcmp = true;
49
+ cpu->cfg.ext_zcmt = true;
50
+ if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
51
+ cpu->cfg.ext_zcf = true;
52
+ }
53
+ }
54
+
55
if (cpu->cfg.ext_c) {
56
cpu->cfg.ext_zca = true;
57
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
58
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
59
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
60
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
61
DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
62
+ DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false),
63
DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
64
DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
65
DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
66
--
67
2.40.0
diff view generated by jsdifflib
New patch
[PULL 19/89] target/riscv: Fix itrigger when icount is used
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
4
The reason is that when execute helper_mret or helper_sret, it will
5
cause a call to icount_get_raw_locked (), which needs set can_do_io flag
6
on cpustate.
7
8
Thus we setting this flag when execute these two instructions.
9
10
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/insn_trans/trans_privileged.c.inc | 6 ++++++
17
1 file changed, 6 insertions(+)
18
19
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/insn_trans/trans_privileged.c.inc
22
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
23
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
24
#ifndef CONFIG_USER_ONLY
25
if (has_ext(ctx, RVS)) {
26
decode_save_opc(ctx);
27
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
28
+ gen_io_start();
29
+ }
30
gen_helper_sret(cpu_pc, cpu_env);
31
exit_tb(ctx); /* no chaining */
32
ctx->base.is_jmp = DISAS_NORETURN;
33
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
34
{
35
#ifndef CONFIG_USER_ONLY
36
decode_save_opc(ctx);
37
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
38
+ gen_io_start();
39
+ }
40
gen_helper_mret(cpu_pc, cpu_env);
41
exit_tb(ctx); /* no chaining */
42
ctx->base.is_jmp = DISAS_NORETURN;
43
--
44
2.40.0
diff view generated by jsdifflib
New patch
[PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
The assignment is done under the condition riscv_cpu_virt_enabled()=true.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu_helper.c | 4 +---
14
1 file changed, 1 insertion(+), 3 deletions(-)
15
16
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu_helper.c
19
+++ b/target/riscv/cpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
21
riscv_cpu_swap_hypervisor_regs(env);
22
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
23
env->priv);
24
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
25
- riscv_cpu_virt_enabled(env));
26
-
27
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
28
29
htval = env->guest_phys_fault_addr;
30
31
--
32
2.40.0
diff view generated by jsdifflib
New patch
[PULL 21/89] target/riscv: Remove redundant check on RVH
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Check on riscv_cpu_virt_enabled contains the check on RVH.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/op_helper.c | 3 +--
14
1 file changed, 1 insertion(+), 2 deletions(-)
15
16
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/op_helper.c
19
+++ b/target/riscv/op_helper.c
20
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
21
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
22
}
23
24
- if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
25
- get_field(env->hstatus, HSTATUS_VTSR)) {
26
+ if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) {
27
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
28
}
29
30
--
31
2.40.0
diff view generated by jsdifflib
New patch
[PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set
4
to true when RVH is disabled, so we can just return this bit(false) when
5
RVH is not disabled.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu_helper.c | 4 ----
16
1 file changed, 4 deletions(-)
17
18
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu_helper.c
21
+++ b/target/riscv/cpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
23
24
bool riscv_cpu_virt_enabled(CPURISCVState *env)
25
{
26
- if (!riscv_has_ext(env, RVH)) {
27
- return false;
28
- }
29
-
30
return get_field(env->virt, VIRT_ONOFF);
31
}
32
33
--
34
2.40.0
diff view generated by jsdifflib
New patch
[PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
In current implementation, riscv_cpu_set_virt_enabled is only called when
4
RVH is enabled.
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 5 +----
15
1 file changed, 1 insertion(+), 4 deletions(-)
16
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_virt_enabled(CPURISCVState *env)
22
return get_field(env->virt, VIRT_ONOFF);
23
}
24
25
+/* This function can only be called to set virt when RVH is enabled */
26
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
27
{
28
- if (!riscv_has_ext(env, RVH)) {
29
- return;
30
- }
31
-
32
/* Flush the TLB on all virt mode changes. */
33
if (get_field(env->virt, VIRT_ONOFF) != enable) {
34
tlb_flush(env_cpu(env));
35
--
36
2.40.0
diff view generated by jsdifflib
New patch
[PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
Currently we only use the env->virt to encode the virtual mode enabled
4
status. Let's make it a bool type.
5
6
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
7
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu.h | 2 +-
15
target/riscv/cpu_bits.h | 3 ---
16
target/riscv/cpu_helper.c | 6 +++---
17
target/riscv/machine.c | 6 +++---
18
target/riscv/translate.c | 4 ++--
19
5 files changed, 9 insertions(+), 12 deletions(-)
20
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
26
#ifndef CONFIG_USER_ONLY
27
target_ulong priv;
28
/* This contains QEMU specific information about the virt state. */
29
- target_ulong virt;
30
+ bool virt_enabled;
31
target_ulong geilen;
32
uint64_t resetvec;
33
34
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu_bits.h
37
+++ b/target/riscv/cpu_bits.h
38
@@ -XXX,XX +XXX,XX @@ typedef enum {
39
#define PRV_H 2 /* Reserved */
40
#define PRV_M 3
41
42
-/* Virtulisation Register Fields */
43
-#define VIRT_ONOFF 1
44
-
45
/* RV32 satp CSR field masks */
46
#define SATP32_MODE 0x80000000
47
#define SATP32_ASID 0x7fc00000
48
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/cpu_helper.c
51
+++ b/target/riscv/cpu_helper.c
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
53
54
bool riscv_cpu_virt_enabled(CPURISCVState *env)
55
{
56
- return get_field(env->virt, VIRT_ONOFF);
57
+ return env->virt_enabled;
58
}
59
60
/* This function can only be called to set virt when RVH is enabled */
61
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
62
{
63
/* Flush the TLB on all virt mode changes. */
64
- if (get_field(env->virt, VIRT_ONOFF) != enable) {
65
+ if (env->virt_enabled != enable) {
66
tlb_flush(env_cpu(env));
67
}
68
69
- env->virt = set_field(env->virt, VIRT_ONOFF, enable);
70
+ env->virt_enabled = enable;
71
72
if (enable) {
73
/*
74
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/machine.c
77
+++ b/target/riscv/machine.c
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_jvt = {
79
80
const VMStateDescription vmstate_riscv_cpu = {
81
.name = "cpu",
82
- .version_id = 7,
83
- .minimum_version_id = 7,
84
+ .version_id = 8,
85
+ .minimum_version_id = 8,
86
.post_load = riscv_cpu_post_load,
87
.fields = (VMStateField[]) {
88
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
89
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
90
VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
91
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
92
VMSTATE_UINTTL(env.priv, RISCVCPU),
93
- VMSTATE_UINTTL(env.virt, RISCVCPU),
94
+ VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
95
VMSTATE_UINT64(env.resetvec, RISCVCPU),
96
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
97
VMSTATE_UINT64(env.mstatus, RISCVCPU),
98
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/riscv/translate.c
101
+++ b/target/riscv/translate.c
102
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
103
104
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
105
#ifndef CONFIG_USER_ONLY
106
- fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
107
- env->priv, env->virt);
108
+ fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
109
+ env->priv, env->virt_enabled);
110
#endif
111
target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
112
}
113
--
114
2.40.0
diff view generated by jsdifflib
New patch
[PULL 25/89] target/riscv: Remove redundant parentheses
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Remove redundant parentheses in get_physical_address.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu_helper.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu_helper.c
19
+++ b/target/riscv/cpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ restart:
21
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
22
*prot |= PAGE_READ;
23
}
24
- if ((pte & PTE_X)) {
25
+ if (pte & PTE_X) {
26
*prot |= PAGE_EXEC;
27
}
28
/* add write permission on stores or if the page is already dirty,
29
--
30
2.40.0
diff view generated by jsdifflib
New patch
[PULL 26/89] target/riscv: Fix addr type for get_physical_address
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Function get_physical_address() translates both virtual address and
4
guest physical address, and the latter is 34-bits for Sv32x4. So we
5
should use vaddr type for 'addr' parameter.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
16
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
22
* @env: CPURISCVState
23
* @physical: This will be set to the calculated physical address
24
* @prot: The returned protection attributes
25
- * @addr: The virtual address to be translated
26
+ * @addr: The virtual address or guest physical address to be translated
27
* @fault_pte_addr: If not NULL, this will be set to fault pte address
28
* when a error occurs on pte address translation.
29
* This will already be shifted to match htval.
30
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
31
* @is_debug: Is this access from a debugger or the monitor?
32
*/
33
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
34
- int *prot, target_ulong addr,
35
+ int *prot, vaddr addr,
36
target_ulong *fault_pte_addr,
37
int access_type, int mmu_idx,
38
bool first_stage, bool two_stage,
39
--
40
2.40.0
diff view generated by jsdifflib
New patch
[PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
decode_save_opc() will not work for generate_exception(), since 0 is passed
4
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
5
not be restored in this case.
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
15
1 file changed, 2 insertions(+)
16
17
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn_trans/trans_rvh.c.inc
20
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
21
@@ -XXX,XX +XXX,XX @@
22
static bool check_access(DisasContext *ctx)
23
{
24
if (!ctx->hlsx) {
25
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
26
+ offsetof(CPURISCVState, bins));
27
if (ctx->virt_enabled) {
28
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
29
} else {
30
--
31
2.40.0
diff view generated by jsdifflib
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
[PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled()
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
3
Directly use env->virt_enabled instead.
4
short of its purpose, as all it checks is whether two-stage address
5
translation either via the hypervisor-load store instructions or the
6
MPRV feature would be allowed.
7
4
8
What we really need instead is whether two-stage address translation was
5
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
we do not have the information to reliably detect this. Therefore, when
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
11
we raise a memory fault exception we have to record whether two-stage
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
address translation is active.
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
14
---
19
target/riscv/cpu.h | 4 ++++
15
target/riscv/cpu.h | 1 -
20
target/riscv/cpu.c | 1 +
16
target/riscv/cpu.c | 2 +-
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
17
target/riscv/cpu_helper.c | 51 ++++++++++++++++++---------------------
22
3 files changed, 13 insertions(+), 13 deletions(-)
18
target/riscv/csr.c | 46 +++++++++++++++++------------------
19
target/riscv/debug.c | 10 ++++----
20
target/riscv/op_helper.c | 18 +++++++-------
21
target/riscv/pmu.c | 4 +--
22
target/riscv/translate.c | 2 +-
23
8 files changed, 64 insertions(+), 70 deletions(-)
23
24
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env);
29
target_ulong satp_hs;
30
target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
30
uint64_t mstatus_hs;
31
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
31
32
bool riscv_cpu_vector_enabled(CPURISCVState *env);
32
+ /* Signals whether the current exception occurred with two-stage address
33
-bool riscv_cpu_virt_enabled(CPURISCVState *env);
33
+ translation active. */
34
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
34
+ bool two_stage_lookup;
35
bool riscv_cpu_two_stage_lookup(int mmu_idx);
35
+
36
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
36
target_ulong scounteren;
37
target_ulong mcounteren;
38
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
37
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu.c
39
--- a/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
40
+++ b/target/riscv/cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
41
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
42
45
env->mcause = 0;
43
#if !defined(CONFIG_USER_ONLY)
46
env->pc = env->resetvec;
44
if (riscv_has_ext(env, RVH)) {
47
+ env->two_stage_lookup = false;
45
- qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
46
+ qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
47
}
48
#endif
48
#endif
49
cs->exception_index = EXCP_NONE;
49
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
50
env->load_res = -1;
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
50
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
52
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
52
--- a/target/riscv/cpu_helper.c
54
+++ b/target/riscv/cpu_helper.c
53
+++ b/target/riscv/cpu_helper.c
54
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
55
56
if (riscv_has_ext(env, RVH)) {
57
if (env->priv == PRV_M ||
58
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
59
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
60
+ (env->priv == PRV_S && !env->virt_enabled) ||
61
+ (env->priv == PRV_U && !env->virt_enabled &&
62
get_field(env->hstatus, HSTATUS_HU))) {
63
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
64
}
65
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
66
uint64_t irqs, pending, mie, hsie, vsie;
67
68
/* Determine interrupt enable state of all privilege modes */
69
- if (riscv_cpu_virt_enabled(env)) {
70
+ if (env->virt_enabled) {
71
mie = 1;
72
hsie = 1;
73
vsie = (env->priv < PRV_S) ||
74
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
75
bool riscv_cpu_fp_enabled(CPURISCVState *env)
76
{
77
if (env->mstatus & MSTATUS_FS) {
78
- if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
79
+ if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
80
return false;
81
}
82
return true;
83
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
84
bool riscv_cpu_vector_enabled(CPURISCVState *env)
85
{
86
if (env->mstatus & MSTATUS_VS) {
87
- if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
88
+ if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
89
return false;
90
}
91
return true;
92
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
93
if (riscv_has_ext(env, RVF)) {
94
mstatus_mask |= MSTATUS_FS;
95
}
96
- bool current_virt = riscv_cpu_virt_enabled(env);
97
+ bool current_virt = env->virt_enabled;
98
99
g_assert(riscv_has_ext(env, RVH));
100
101
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
102
env->geilen = geilen;
103
}
104
105
-bool riscv_cpu_virt_enabled(CPURISCVState *env)
106
-{
107
- return env->virt_enabled;
108
-}
109
-
110
/* This function can only be called to set virt when RVH is enabled */
111
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
112
{
113
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
114
CPUState *cs = env_cpu(env);
115
uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
116
117
- if (riscv_cpu_virt_enabled(env)) {
118
+ if (env->virt_enabled) {
119
gein = get_field(env->hstatus, HSTATUS_VGEIN);
120
vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
121
}
122
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
123
* was called. Background registers will be used if the guest has
124
* forced a two stage translation to be on (in HS or M mode).
125
*/
126
- if (!riscv_cpu_virt_enabled(env) && two_stage) {
127
+ if (!env->virt_enabled && two_stage) {
128
use_background = true;
129
}
130
131
@@ -XXX,XX +XXX,XX @@ restart:
132
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
133
bool hade = env->menvcfg & MENVCFG_HADE;
134
135
- if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
136
+ if (first_stage && two_stage && env->virt_enabled) {
137
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
138
hade = hade && (env->henvcfg & HENVCFG_HADE);
139
}
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
140
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
56
g_assert_not_reached();
141
57
}
142
switch (access_type) {
58
env->badaddr = address;
143
case MMU_INST_FETCH:
59
+ env->two_stage_lookup = two_stage;
144
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
60
}
145
+ if (env->virt_enabled && !first_stage) {
61
146
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
147
} else {
148
cs->exception_index = page_fault_exceptions ?
149
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
150
int mmu_idx = cpu_mmu_index(&cpu->env, false);
151
152
if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
153
- true, riscv_cpu_virt_enabled(env), true)) {
154
+ true, env->virt_enabled, true)) {
155
return -1;
156
}
157
158
- if (riscv_cpu_virt_enabled(env)) {
159
+ if (env->virt_enabled) {
160
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
161
0, mmu_idx, false, true, true)) {
162
return -1;
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
163
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
64
}
164
}
65
165
66
env->badaddr = addr;
166
env->badaddr = addr;
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
167
- env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
168
+ env->two_stage_lookup = env->virt_enabled ||
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
169
riscv_cpu_two_stage_lookup(mmu_idx);
70
}
170
env->two_stage_indirect_lookup = false;
71
171
cpu_loop_exit_restore(cs, retaddr);
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
172
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
73
g_assert_not_reached();
173
g_assert_not_reached();
74
}
174
}
75
env->badaddr = addr;
175
env->badaddr = addr;
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
176
- env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
177
+ env->two_stage_lookup = env->virt_enabled ||
78
riscv_raise_exception(env, cs->exception_index, retaddr);
178
riscv_cpu_two_stage_lookup(mmu_idx);
79
}
179
env->two_stage_indirect_lookup = false;
80
#endif /* !CONFIG_USER_ONLY */
180
cpu_loop_exit_restore(cs, retaddr);
181
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
182
}
183
184
pmu_tlb_fill_incr_ctr(cpu, access_type);
185
- if (riscv_cpu_virt_enabled(env) ||
186
+ if (env->virt_enabled ||
187
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
188
access_type != MMU_INST_FETCH)) {
189
/* Two stage lookup */
190
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
191
} else {
192
raise_mmu_exception(env, address, access_type, pmp_violation,
193
first_stage_error,
194
- riscv_cpu_virt_enabled(env) ||
195
+ env->virt_enabled ||
196
riscv_cpu_two_stage_lookup(mmu_idx),
197
two_stage_indirect_error);
198
cpu_loop_exit_restore(cs, retaddr);
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
199
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
82
/* handle the trap in S-mode */
200
201
if (env->priv == PRV_M) {
202
cause = RISCV_EXCP_M_ECALL;
203
- } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
204
+ } else if (env->priv == PRV_S && env->virt_enabled) {
205
cause = RISCV_EXCP_VS_ECALL;
206
- } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
207
+ } else if (env->priv == PRV_S && !env->virt_enabled) {
208
cause = RISCV_EXCP_S_ECALL;
209
} else if (env->priv == PRV_U) {
210
cause = RISCV_EXCP_U_ECALL;
211
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
83
if (riscv_has_ext(env, RVH)) {
212
if (riscv_has_ext(env, RVH)) {
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
213
uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
85
- bool two_stage_lookup = false;
214
86
215
- if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
87
- if (env->priv == PRV_M ||
216
+ if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
217
/* Trap to VS mode */
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
90
- get_field(env->hstatus, HSTATUS_HU))) {
91
- two_stage_lookup = true;
92
- }
93
-
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
95
+ if (env->two_stage_lookup && write_tval) {
96
/*
218
/*
97
* If we are writing a guest virtual address to stval, set
219
* See if we need to adjust cause. Yes if its VS mode interrupt
98
* this to 1. If we are trapping to VS we will set this to 0
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
220
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
100
riscv_cpu_set_force_hs_excep(env, 0);
221
cause = cause - 1;
101
} else {
222
}
102
/* Trap into HS mode */
223
write_gva = false;
103
- if (!two_stage_lookup) {
224
- } else if (riscv_cpu_virt_enabled(env)) {
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
225
+ } else if (env->virt_enabled) {
105
- riscv_cpu_virt_enabled(env));
226
/* Trap into HS mode, from virt */
106
- }
227
riscv_cpu_swap_hypervisor_regs(env);
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
228
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
108
htval = env->guest_phys_fault_addr;
229
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
230
} else {
231
/* handle the trap in M-mode */
232
if (riscv_has_ext(env, RVH)) {
233
- if (riscv_cpu_virt_enabled(env)) {
234
+ if (env->virt_enabled) {
235
riscv_cpu_swap_hypervisor_regs(env);
109
}
236
}
110
}
237
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
238
- riscv_cpu_virt_enabled(env));
112
* RISC-V ISA Specification.
239
- if (riscv_cpu_virt_enabled(env) && tval) {
240
+ env->virt_enabled);
241
+ if (env->virt_enabled && tval) {
242
env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
243
}
244
245
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
246
index XXXXXXX..XXXXXXX 100644
247
--- a/target/riscv/csr.c
248
+++ b/target/riscv/csr.c
249
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
250
#if !defined(CONFIG_USER_ONLY)
251
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
252
{
253
- bool virt = riscv_cpu_virt_enabled(env);
254
+ bool virt = env->virt_enabled;
255
256
if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
257
return RISCV_EXCP_NONE;
258
@@ -XXX,XX +XXX,XX @@ skip_ext_pmu_check:
259
return RISCV_EXCP_ILLEGAL_INST;
260
}
261
262
- if (riscv_cpu_virt_enabled(env)) {
263
+ if (env->virt_enabled) {
264
if (!get_field(env->hcounteren, ctr_mask) ||
265
(env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
266
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
267
@@ -XXX,XX +XXX,XX @@ static RISCVException hstateenh(CPURISCVState *env, int csrno)
268
269
static RISCVException sstateen(CPURISCVState *env, int csrno)
270
{
271
- bool virt = riscv_cpu_virt_enabled(env);
272
+ bool virt = env->virt_enabled;
273
int index = csrno - CSR_SSTATEEN0;
274
275
if (!riscv_cpu_cfg(env)->ext_smstateen) {
276
@@ -XXX,XX +XXX,XX @@ static RISCVException sstc(CPURISCVState *env, int csrno)
277
return RISCV_EXCP_ILLEGAL_INST;
278
}
279
280
- if (riscv_cpu_virt_enabled(env)) {
281
+ if (env->virt_enabled) {
282
if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
283
get_field(env->henvcfg, HENVCFG_STCE))) {
284
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
285
@@ -XXX,XX +XXX,XX @@ static RISCVException seed(CPURISCVState *env, int csrno)
113
*/
286
*/
114
287
if (env->priv == PRV_M) {
115
+ env->two_stage_lookup = false;
288
return RISCV_EXCP_NONE;
116
#endif
289
- } else if (riscv_cpu_virt_enabled(env)) {
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
290
+ } else if (env->virt_enabled) {
118
}
291
if (env->mseccfg & MSECCFG_SSEED) {
292
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
293
} else {
294
@@ -XXX,XX +XXX,XX @@ static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
295
static RISCVException read_time(CPURISCVState *env, int csrno,
296
target_ulong *val)
297
{
298
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
299
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
300
301
if (!env->rdtime_fn) {
302
return RISCV_EXCP_ILLEGAL_INST;
303
@@ -XXX,XX +XXX,XX @@ static RISCVException read_time(CPURISCVState *env, int csrno,
304
static RISCVException read_timeh(CPURISCVState *env, int csrno,
305
target_ulong *val)
306
{
307
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
308
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
309
310
if (!env->rdtime_fn) {
311
return RISCV_EXCP_ILLEGAL_INST;
312
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
313
static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
314
target_ulong *val)
315
{
316
- if (riscv_cpu_virt_enabled(env)) {
317
+ if (env->virt_enabled) {
318
*val = env->vstimecmp;
319
} else {
320
*val = env->stimecmp;
321
@@ -XXX,XX +XXX,XX @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
322
static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
323
target_ulong *val)
324
{
325
- if (riscv_cpu_virt_enabled(env)) {
326
+ if (env->virt_enabled) {
327
*val = env->vstimecmp >> 32;
328
} else {
329
*val = env->stimecmp >> 32;
330
@@ -XXX,XX +XXX,XX @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
331
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
332
target_ulong val)
333
{
334
- if (riscv_cpu_virt_enabled(env)) {
335
+ if (env->virt_enabled) {
336
if (env->hvictl & HVICTL_VTI) {
337
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
338
}
339
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
340
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
341
target_ulong val)
342
{
343
- if (riscv_cpu_virt_enabled(env)) {
344
+ if (env->virt_enabled) {
345
if (env->hvictl & HVICTL_VTI) {
346
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
347
}
348
@@ -XXX,XX +XXX,XX @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
349
350
static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
351
{
352
- if (!riscv_cpu_virt_enabled(env)) {
353
+ if (!env->virt_enabled) {
354
return csrno;
355
}
356
357
@@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
358
359
done:
360
if (ret) {
361
- return (riscv_cpu_virt_enabled(env) && virt) ?
362
+ return (env->virt_enabled && virt) ?
363
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
364
}
365
return RISCV_EXCP_NONE;
366
@@ -XXX,XX +XXX,XX @@ static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
367
368
done:
369
if (ret) {
370
- return (riscv_cpu_virt_enabled(env) && virt) ?
371
+ return (env->virt_enabled && virt) ?
372
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
373
}
374
return RISCV_EXCP_NONE;
375
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
376
static RISCVException read_sstateen(CPURISCVState *env, int csrno,
377
target_ulong *val)
378
{
379
- bool virt = riscv_cpu_virt_enabled(env);
380
+ bool virt = env->virt_enabled;
381
int index = csrno - CSR_SSTATEEN0;
382
383
*val = env->sstateen[index] & env->mstateen[index];
384
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstateen(CPURISCVState *env, int csrno,
385
static RISCVException write_sstateen(CPURISCVState *env, int csrno,
386
uint64_t mask, target_ulong new_val)
387
{
388
- bool virt = riscv_cpu_virt_enabled(env);
389
+ bool virt = env->virt_enabled;
390
int index = csrno - CSR_SSTATEEN0;
391
uint64_t wr_mask;
392
uint64_t *reg;
393
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
394
RISCVException ret;
395
uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
396
397
- if (riscv_cpu_virt_enabled(env)) {
398
+ if (env->virt_enabled) {
399
if (env->hvictl & HVICTL_VTI) {
400
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
401
}
402
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
403
RISCVException ret;
404
uint64_t mask = env->mideleg & sip_writable_mask;
405
406
- if (riscv_cpu_virt_enabled(env)) {
407
+ if (env->virt_enabled) {
408
if (env->hvictl & HVICTL_VTI) {
409
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
410
}
411
@@ -XXX,XX +XXX,XX @@ static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
412
int irq;
413
uint8_t iprio;
414
415
- if (riscv_cpu_virt_enabled(env)) {
416
+ if (env->virt_enabled) {
417
return read_vstopi(env, CSR_VSTOPI, val);
418
}
419
420
@@ -XXX,XX +XXX,XX @@ static int read_hvipriox(CPURISCVState *env, int first_index,
421
422
/* First index has to be a multiple of number of irqs per register */
423
if (first_index % num_irqs) {
424
- return (riscv_cpu_virt_enabled(env)) ?
425
+ return (env->virt_enabled) ?
426
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
427
}
428
429
@@ -XXX,XX +XXX,XX @@ static int write_hvipriox(CPURISCVState *env, int first_index,
430
431
/* First index has to be a multiple of number of irqs per register */
432
if (first_index % num_irqs) {
433
- return (riscv_cpu_virt_enabled(env)) ?
434
+ return (env->virt_enabled) ?
435
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
436
}
437
438
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
439
int csr_priv, effective_priv = env->priv;
440
441
if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
442
- !riscv_cpu_virt_enabled(env)) {
443
+ !env->virt_enabled) {
444
/*
445
* We are in HS mode. Add 1 to the effective privledge level to
446
* allow us to access the Hypervisor CSRs.
447
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
448
449
csr_priv = get_field(csrno, 0x300);
450
if (!env->debugger && (effective_priv < csr_priv)) {
451
- if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
452
+ if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
453
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
454
}
455
return RISCV_EXCP_ILLEGAL_INST;
456
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
457
index XXXXXXX..XXXXXXX 100644
458
--- a/target/riscv/debug.c
459
+++ b/target/riscv/debug.c
460
@@ -XXX,XX +XXX,XX @@ itrigger_set_count(CPURISCVState *env, int index, int value)
461
static bool check_itrigger_priv(CPURISCVState *env, int index)
462
{
463
target_ulong tdata1 = env->tdata1[index];
464
- if (riscv_cpu_virt_enabled(env)) {
465
+ if (env->virt_enabled) {
466
/* check VU/VS bit against current privilege level */
467
return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
468
(get_field(tdata1, ITRIGGER_VU) == env->priv);
469
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
470
switch (trigger_type) {
471
case TRIGGER_TYPE_AD_MATCH:
472
/* type 2 trigger cannot be fired in VU/VS mode */
473
- if (riscv_cpu_virt_enabled(env)) {
474
+ if (env->virt_enabled) {
475
return false;
476
}
477
478
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
479
pc = env->tdata2[i];
480
481
if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
482
- if (riscv_cpu_virt_enabled(env)) {
483
+ if (env->virt_enabled) {
484
/* check VU/VS bit against current privilege level */
485
if ((ctrl >> 23) & BIT(env->priv)) {
486
return true;
487
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
488
switch (trigger_type) {
489
case TRIGGER_TYPE_AD_MATCH:
490
/* type 2 trigger cannot be fired in VU/VS mode */
491
- if (riscv_cpu_virt_enabled(env)) {
492
+ if (env->virt_enabled) {
493
return false;
494
}
495
496
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
497
}
498
499
if ((wp->flags & flags) && (wp->vaddr == addr)) {
500
- if (riscv_cpu_virt_enabled(env)) {
501
+ if (env->virt_enabled) {
502
/* check VU/VS bit against current privilege level */
503
if ((ctrl >> 23) & BIT(env->priv)) {
504
return true;
505
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
506
index XXXXXXX..XXXXXXX 100644
507
--- a/target/riscv/op_helper.c
508
+++ b/target/riscv/op_helper.c
509
@@ -XXX,XX +XXX,XX @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
510
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
511
}
512
513
- if (riscv_cpu_virt_enabled(env) &&
514
+ if (env->virt_enabled &&
515
(((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
516
((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
517
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
518
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
519
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
520
}
521
522
- if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) {
523
+ if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) {
524
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
525
}
526
527
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
528
}
529
env->mstatus = mstatus;
530
531
- if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
532
+ if (riscv_has_ext(env, RVH) && !env->virt_enabled) {
533
/* We support Hypervisor extensions and virtulisation is disabled */
534
target_ulong hstatus = env->hstatus;
535
536
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
537
bool prv_s = env->priv == PRV_S;
538
539
if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
540
- (rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
541
+ (rvs && prv_u && !env->virt_enabled)) {
542
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
543
- } else if (riscv_cpu_virt_enabled(env) && (prv_u ||
544
+ } else if (env->virt_enabled && (prv_u ||
545
(prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
546
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
547
} else {
548
@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
549
(env->priv == PRV_S &&
550
get_field(env->mstatus, MSTATUS_TVM))) {
551
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
552
- } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
553
+ } else if (riscv_has_ext(env, RVH) && env->virt_enabled &&
554
get_field(env->hstatus, HSTATUS_VTVM)) {
555
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
556
} else {
557
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
558
{
559
CPUState *cs = env_cpu(env);
560
561
- if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
562
+ if (env->priv == PRV_S && env->virt_enabled) {
563
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
564
}
565
566
if (env->priv == PRV_M ||
567
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
568
+ (env->priv == PRV_S && !env->virt_enabled)) {
569
tlb_flush(cs);
570
return;
571
}
572
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
573
574
void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
575
{
576
- if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
577
+ if (env->priv == PRV_S && !env->virt_enabled &&
578
get_field(env->mstatus, MSTATUS_TVM)) {
579
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
580
}
581
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
582
index XXXXXXX..XXXXXXX 100644
583
--- a/target/riscv/pmu.c
584
+++ b/target/riscv/pmu.c
585
@@ -XXX,XX +XXX,XX @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
586
CPURISCVState *env = &cpu->env;
587
target_ulong max_val = UINT32_MAX;
588
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
589
- bool virt_on = riscv_cpu_virt_enabled(env);
590
+ bool virt_on = env->virt_enabled;
591
592
/* Privilege mode filtering */
593
if ((env->priv == PRV_M &&
594
@@ -XXX,XX +XXX,XX @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
595
CPURISCVState *env = &cpu->env;
596
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
597
uint64_t max_val = UINT64_MAX;
598
- bool virt_on = riscv_cpu_virt_enabled(env);
599
+ bool virt_on = env->virt_enabled;
600
601
/* Privilege mode filtering */
602
if ((env->priv == PRV_M &&
603
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
604
index XXXXXXX..XXXXXXX 100644
605
--- a/target/riscv/translate.c
606
+++ b/target/riscv/translate.c
607
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
608
ctx->priv_ver = env->priv_ver;
609
#if !defined(CONFIG_USER_ONLY)
610
if (riscv_has_ext(env, RVH)) {
611
- ctx->virt_enabled = riscv_cpu_virt_enabled(env);
612
+ ctx->virt_enabled = env->virt_enabled;
613
} else {
614
ctx->virt_enabled = false;
615
}
119
--
616
--
120
2.30.1
617
2.40.0
121
122
diff view generated by jsdifflib
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
[PULL 29/89] target/riscv: Fix format for indentation
1
From: Jim Shu <cwshu@andestech.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
3
Fix identation problems, and try to use the same indentation strategy
4
Fix it by propagating PMP permission to TLB page permission.
4
in the same file.
5
5
6
PMP permission checking also use MMU-style API to change TLB permission
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
and size.
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
11
Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
13
---
14
target/riscv/pmp.h | 4 +-
14
target/riscv/pmp.h | 9 +-
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
15
target/riscv/arch_dump.c | 4 +-
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
16
target/riscv/cpu.c | 40 +++---
17
3 files changed, 125 insertions(+), 43 deletions(-)
17
target/riscv/cpu_helper.c | 163 ++++++++++++------------
18
target/riscv/fpu_helper.c | 24 ++--
19
target/riscv/m128_helper.c | 16 +--
20
target/riscv/machine.c | 18 +--
21
target/riscv/op_helper.c | 4 +-
22
target/riscv/pmp.c | 19 +--
23
target/riscv/translate.c | 4 +-
24
target/riscv/vector_helper.c | 159 +++++++++++------------
25
target/riscv/insn_trans/trans_rvv.c.inc | 28 ++--
26
12 files changed, 247 insertions(+), 241 deletions(-)
18
27
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
28
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
20
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/pmp.h
30
--- a/target/riscv/pmp.h
22
+++ b/target/riscv/pmp.h
31
+++ b/target/riscv/pmp.h
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
32
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
target_ulong val);
33
} pmp_table_t;
34
35
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
36
- target_ulong val);
37
+ target_ulong val);
38
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
39
40
void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
41
target_ulong mseccfg_csr_read(CPURISCVState *env);
42
43
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
44
- target_ulong val);
45
+ target_ulong val);
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
46
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
47
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
48
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
49
- target_ulong mode);
29
+ target_ulong mode);
50
+ target_ulong size, pmp_priv_t privs,
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
51
+ pmp_priv_t *allowed_privs,
31
target_ulong *tlb_size);
52
+ target_ulong mode);
53
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
54
target_ulong tlb_sa, target_ulong tlb_ea);
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
55
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
33
void pmp_update_rule_nums(CPURISCVState *env);
56
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
57
index XXXXXXX..XXXXXXX 100644
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
58
--- a/target/riscv/arch_dump.c
36
59
+++ b/target/riscv/arch_dump.c
60
@@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info,
61
info->d_class = ELFCLASS32;
37
#endif
62
#endif
63
64
- info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
65
- ? ELFDATA2MSB : ELFDATA2LSB;
66
+ info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 ?
67
+ ELFDATA2MSB : ELFDATA2LSB;
68
69
return 0;
70
}
71
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/riscv/cpu.c
74
+++ b/target/riscv/cpu.c
75
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
76
};
77
78
#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
79
-{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
80
+ {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
81
82
/**
83
* Here are the ordering rules of extension naming defined by RISC-V
84
@@ -XXX,XX +XXX,XX @@ static void isa_ext_update_enabled(RISCVCPU *cpu,
85
}
86
87
const char * const riscv_int_regnames[] = {
88
- "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
89
- "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
90
- "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
91
- "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
92
- "x28/t3", "x29/t4", "x30/t5", "x31/t6"
93
+ "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
94
+ "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
95
+ "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
96
+ "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
97
+ "x28/t3", "x29/t4", "x30/t5", "x31/t6"
98
};
99
100
const char * const riscv_int_regnamesh[] = {
101
- "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
102
- "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
103
- "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
104
- "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
105
- "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
106
- "x30h/t5h", "x31h/t6h"
107
+ "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
108
+ "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
109
+ "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
110
+ "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
111
+ "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
112
+ "x30h/t5h", "x31h/t6h"
113
};
114
115
const char * const riscv_fpr_regnames[] = {
116
- "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
117
- "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
118
- "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
119
- "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
120
- "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
121
- "f30/ft10", "f31/ft11"
122
+ "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
123
+ "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
124
+ "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
125
+ "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
126
+ "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
127
+ "f30/ft10", "f31/ft11"
128
};
129
130
static const char * const riscv_excp_names[] = {
131
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
132
133
#ifndef CONFIG_USER_ONLY
134
set_satp_mode_max_supported(RISCV_CPU(obj),
135
- riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
136
- VM_1_10_SV32 : VM_1_10_SV57);
137
+ riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
138
+ VM_1_10_SV32 : VM_1_10_SV57);
139
#endif
140
141
set_priv_version(env, PRIV_VERSION_1_12_0);
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
142
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
143
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
144
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
145
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
146
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
43
env->load_res = -1;
147
flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
44
}
148
flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
45
149
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
46
+/*
150
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
47
+ * get_physical_address_pmp - check PMP permission for this physical address
151
+ FIELD_EX64(env->vtype, VTYPE, VLMUL));
48
+ *
152
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
49
+ * Match the PMP region and check permission for this physical address and it's
153
flags = FIELD_DP32(flags, TB_FLAGS, VTA,
50
+ * TLB page. Returns 0 if the permission checking was successful
154
- FIELD_EX64(env->vtype, VTYPE, VTA));
51
+ *
155
+ FIELD_EX64(env->vtype, VTYPE, VTA));
52
+ * @env: CPURISCVState
156
flags = FIELD_DP32(flags, TB_FLAGS, VMA,
53
+ * @prot: The returned protection attributes
157
- FIELD_EX64(env->vtype, VTYPE, VMA));
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
158
+ FIELD_EX64(env->vtype, VTYPE, VMA));
55
+ * permission checking. NULL if not set TLB page for addr.
159
} else {
56
+ * @addr: The physical address to be checked permission
160
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
57
+ * @access_type: The type of MMU access
161
}
58
+ * @mode: Indicates current privilege level.
162
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
59
+ */
163
if (env->priv == PRV_M ||
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
164
(env->priv == PRV_S && !env->virt_enabled) ||
61
+ target_ulong *tlb_size, hwaddr addr,
165
(env->priv == PRV_U && !env->virt_enabled &&
62
+ int size, MMUAccessType access_type,
166
- get_field(env->hstatus, HSTATUS_HU))) {
63
+ int mode)
167
+ get_field(env->hstatus, HSTATUS_HU))) {
64
+{
168
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
65
+ pmp_priv_t pmp_priv;
169
}
66
+ target_ulong tlb_size_pmp = 0;
170
171
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
172
* ----------------------------------------------------------------
173
*/
174
static const uint8_t default_iprio[64] = {
175
- /* Custom interrupts 48 to 63 */
176
- [63] = IPRIO_MMAXIPRIO,
177
- [62] = IPRIO_MMAXIPRIO,
178
- [61] = IPRIO_MMAXIPRIO,
179
- [60] = IPRIO_MMAXIPRIO,
180
- [59] = IPRIO_MMAXIPRIO,
181
- [58] = IPRIO_MMAXIPRIO,
182
- [57] = IPRIO_MMAXIPRIO,
183
- [56] = IPRIO_MMAXIPRIO,
184
- [55] = IPRIO_MMAXIPRIO,
185
- [54] = IPRIO_MMAXIPRIO,
186
- [53] = IPRIO_MMAXIPRIO,
187
- [52] = IPRIO_MMAXIPRIO,
188
- [51] = IPRIO_MMAXIPRIO,
189
- [50] = IPRIO_MMAXIPRIO,
190
- [49] = IPRIO_MMAXIPRIO,
191
- [48] = IPRIO_MMAXIPRIO,
192
-
193
- /* Custom interrupts 24 to 31 */
194
- [31] = IPRIO_MMAXIPRIO,
195
- [30] = IPRIO_MMAXIPRIO,
196
- [29] = IPRIO_MMAXIPRIO,
197
- [28] = IPRIO_MMAXIPRIO,
198
- [27] = IPRIO_MMAXIPRIO,
199
- [26] = IPRIO_MMAXIPRIO,
200
- [25] = IPRIO_MMAXIPRIO,
201
- [24] = IPRIO_MMAXIPRIO,
202
-
203
- [47] = IPRIO_DEFAULT_UPPER,
204
- [23] = IPRIO_DEFAULT_UPPER + 1,
205
- [46] = IPRIO_DEFAULT_UPPER + 2,
206
- [45] = IPRIO_DEFAULT_UPPER + 3,
207
- [22] = IPRIO_DEFAULT_UPPER + 4,
208
- [44] = IPRIO_DEFAULT_UPPER + 5,
209
-
210
- [43] = IPRIO_DEFAULT_UPPER + 6,
211
- [21] = IPRIO_DEFAULT_UPPER + 7,
212
- [42] = IPRIO_DEFAULT_UPPER + 8,
213
- [41] = IPRIO_DEFAULT_UPPER + 9,
214
- [20] = IPRIO_DEFAULT_UPPER + 10,
215
- [40] = IPRIO_DEFAULT_UPPER + 11,
216
-
217
- [11] = IPRIO_DEFAULT_M,
218
- [3] = IPRIO_DEFAULT_M + 1,
219
- [7] = IPRIO_DEFAULT_M + 2,
220
-
221
- [9] = IPRIO_DEFAULT_S,
222
- [1] = IPRIO_DEFAULT_S + 1,
223
- [5] = IPRIO_DEFAULT_S + 2,
224
-
225
- [12] = IPRIO_DEFAULT_SGEXT,
226
-
227
- [10] = IPRIO_DEFAULT_VS,
228
- [2] = IPRIO_DEFAULT_VS + 1,
229
- [6] = IPRIO_DEFAULT_VS + 2,
230
-
231
- [39] = IPRIO_DEFAULT_LOWER,
232
- [19] = IPRIO_DEFAULT_LOWER + 1,
233
- [38] = IPRIO_DEFAULT_LOWER + 2,
234
- [37] = IPRIO_DEFAULT_LOWER + 3,
235
- [18] = IPRIO_DEFAULT_LOWER + 4,
236
- [36] = IPRIO_DEFAULT_LOWER + 5,
237
-
238
- [35] = IPRIO_DEFAULT_LOWER + 6,
239
- [17] = IPRIO_DEFAULT_LOWER + 7,
240
- [34] = IPRIO_DEFAULT_LOWER + 8,
241
- [33] = IPRIO_DEFAULT_LOWER + 9,
242
- [16] = IPRIO_DEFAULT_LOWER + 10,
243
- [32] = IPRIO_DEFAULT_LOWER + 11,
244
+ /* Custom interrupts 48 to 63 */
245
+ [63] = IPRIO_MMAXIPRIO,
246
+ [62] = IPRIO_MMAXIPRIO,
247
+ [61] = IPRIO_MMAXIPRIO,
248
+ [60] = IPRIO_MMAXIPRIO,
249
+ [59] = IPRIO_MMAXIPRIO,
250
+ [58] = IPRIO_MMAXIPRIO,
251
+ [57] = IPRIO_MMAXIPRIO,
252
+ [56] = IPRIO_MMAXIPRIO,
253
+ [55] = IPRIO_MMAXIPRIO,
254
+ [54] = IPRIO_MMAXIPRIO,
255
+ [53] = IPRIO_MMAXIPRIO,
256
+ [52] = IPRIO_MMAXIPRIO,
257
+ [51] = IPRIO_MMAXIPRIO,
258
+ [50] = IPRIO_MMAXIPRIO,
259
+ [49] = IPRIO_MMAXIPRIO,
260
+ [48] = IPRIO_MMAXIPRIO,
67
+
261
+
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
262
+ /* Custom interrupts 24 to 31 */
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
263
+ [31] = IPRIO_MMAXIPRIO,
70
+ return TRANSLATE_SUCCESS;
264
+ [30] = IPRIO_MMAXIPRIO,
265
+ [29] = IPRIO_MMAXIPRIO,
266
+ [28] = IPRIO_MMAXIPRIO,
267
+ [27] = IPRIO_MMAXIPRIO,
268
+ [26] = IPRIO_MMAXIPRIO,
269
+ [25] = IPRIO_MMAXIPRIO,
270
+ [24] = IPRIO_MMAXIPRIO,
271
+
272
+ [47] = IPRIO_DEFAULT_UPPER,
273
+ [23] = IPRIO_DEFAULT_UPPER + 1,
274
+ [46] = IPRIO_DEFAULT_UPPER + 2,
275
+ [45] = IPRIO_DEFAULT_UPPER + 3,
276
+ [22] = IPRIO_DEFAULT_UPPER + 4,
277
+ [44] = IPRIO_DEFAULT_UPPER + 5,
278
+
279
+ [43] = IPRIO_DEFAULT_UPPER + 6,
280
+ [21] = IPRIO_DEFAULT_UPPER + 7,
281
+ [42] = IPRIO_DEFAULT_UPPER + 8,
282
+ [41] = IPRIO_DEFAULT_UPPER + 9,
283
+ [20] = IPRIO_DEFAULT_UPPER + 10,
284
+ [40] = IPRIO_DEFAULT_UPPER + 11,
285
+
286
+ [11] = IPRIO_DEFAULT_M,
287
+ [3] = IPRIO_DEFAULT_M + 1,
288
+ [7] = IPRIO_DEFAULT_M + 2,
289
+
290
+ [9] = IPRIO_DEFAULT_S,
291
+ [1] = IPRIO_DEFAULT_S + 1,
292
+ [5] = IPRIO_DEFAULT_S + 2,
293
+
294
+ [12] = IPRIO_DEFAULT_SGEXT,
295
+
296
+ [10] = IPRIO_DEFAULT_VS,
297
+ [2] = IPRIO_DEFAULT_VS + 1,
298
+ [6] = IPRIO_DEFAULT_VS + 2,
299
+
300
+ [39] = IPRIO_DEFAULT_LOWER,
301
+ [19] = IPRIO_DEFAULT_LOWER + 1,
302
+ [38] = IPRIO_DEFAULT_LOWER + 2,
303
+ [37] = IPRIO_DEFAULT_LOWER + 3,
304
+ [18] = IPRIO_DEFAULT_LOWER + 4,
305
+ [36] = IPRIO_DEFAULT_LOWER + 5,
306
+
307
+ [35] = IPRIO_DEFAULT_LOWER + 6,
308
+ [17] = IPRIO_DEFAULT_LOWER + 7,
309
+ [34] = IPRIO_DEFAULT_LOWER + 8,
310
+ [33] = IPRIO_DEFAULT_LOWER + 9,
311
+ [16] = IPRIO_DEFAULT_LOWER + 10,
312
+ [32] = IPRIO_DEFAULT_LOWER + 11,
313
};
314
315
uint8_t riscv_cpu_default_priority(int irq)
316
@@ -XXX,XX +XXX,XX @@ restart:
317
*/
318
MemoryRegion *mr;
319
hwaddr l = sizeof(target_ulong), addr1;
320
- mr = address_space_translate(cs->as, pte_addr,
321
- &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
322
+ mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
323
+ false, MEMTXATTRS_UNSPECIFIED);
324
if (memory_region_is_ram(mr)) {
325
target_ulong *pte_pa =
326
qemu_map_ram_ptr(mr->ram_block, addr1);
327
@@ -XXX,XX +XXX,XX @@ restart:
328
/* add write permission on stores or if the page is already dirty,
329
so that we TLB miss on later writes to update the dirty bit */
330
if ((pte & PTE_W) &&
331
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
332
+ (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
333
*prot |= PAGE_WRITE;
334
}
335
return TRANSLATE_SUCCESS;
336
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
337
false);
338
339
qemu_log_mask(CPU_LOG_MMU,
340
- "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
341
- HWADDR_FMT_plx " prot %d\n",
342
- __func__, im_address, ret, pa, prot2);
343
+ "%s 2nd-stage address=%" VADDR_PRIx
344
+ " ret %d physical "
345
+ HWADDR_FMT_plx " prot %d\n",
346
+ __func__, im_address, ret, pa, prot2);
347
348
prot &= prot2;
349
350
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
351
env->htval = htval;
352
env->htinst = tinst;
353
env->pc = (env->stvec >> 2 << 2) +
354
- ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
355
+ ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
356
riscv_cpu_set_mode(env, PRV_S);
357
} else {
358
/* handle the trap in M-mode */
359
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
360
env->mtval2 = mtval2;
361
env->mtinst = tinst;
362
env->pc = (env->mtvec >> 2 << 2) +
363
- ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
364
+ ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
365
riscv_cpu_set_mode(env, PRV_M);
366
}
367
368
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
369
index XXXXXXX..XXXXXXX 100644
370
--- a/target/riscv/fpu_helper.c
371
+++ b/target/riscv/fpu_helper.c
372
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
373
float32 frs1 = check_nanbox_s(env, rs1);
374
float32 frs2 = check_nanbox_s(env, rs2);
375
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
376
- float32_minnum(frs1, frs2, &env->fp_status) :
377
- float32_minimum_number(frs1, frs2, &env->fp_status));
378
+ float32_minnum(frs1, frs2, &env->fp_status) :
379
+ float32_minimum_number(frs1, frs2, &env->fp_status));
380
}
381
382
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
383
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
384
float32 frs1 = check_nanbox_s(env, rs1);
385
float32 frs2 = check_nanbox_s(env, rs2);
386
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
387
- float32_maxnum(frs1, frs2, &env->fp_status) :
388
- float32_maximum_number(frs1, frs2, &env->fp_status));
389
+ float32_maxnum(frs1, frs2, &env->fp_status) :
390
+ float32_maximum_number(frs1, frs2, &env->fp_status));
391
}
392
393
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
394
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
395
uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
396
{
397
return env->priv_ver < PRIV_VERSION_1_11_0 ?
398
- float64_minnum(frs1, frs2, &env->fp_status) :
399
- float64_minimum_number(frs1, frs2, &env->fp_status);
400
+ float64_minnum(frs1, frs2, &env->fp_status) :
401
+ float64_minimum_number(frs1, frs2, &env->fp_status);
402
}
403
404
uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
405
{
406
return env->priv_ver < PRIV_VERSION_1_11_0 ?
407
- float64_maxnum(frs1, frs2, &env->fp_status) :
408
- float64_maximum_number(frs1, frs2, &env->fp_status);
409
+ float64_maxnum(frs1, frs2, &env->fp_status) :
410
+ float64_maximum_number(frs1, frs2, &env->fp_status);
411
}
412
413
uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
414
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
415
float16 frs1 = check_nanbox_h(env, rs1);
416
float16 frs2 = check_nanbox_h(env, rs2);
417
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
418
- float16_minnum(frs1, frs2, &env->fp_status) :
419
- float16_minimum_number(frs1, frs2, &env->fp_status));
420
+ float16_minnum(frs1, frs2, &env->fp_status) :
421
+ float16_minimum_number(frs1, frs2, &env->fp_status));
422
}
423
424
uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
425
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
426
float16 frs1 = check_nanbox_h(env, rs1);
427
float16 frs2 = check_nanbox_h(env, rs2);
428
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
429
- float16_maxnum(frs1, frs2, &env->fp_status) :
430
- float16_maximum_number(frs1, frs2, &env->fp_status));
431
+ float16_maxnum(frs1, frs2, &env->fp_status) :
432
+ float16_maximum_number(frs1, frs2, &env->fp_status));
433
}
434
435
uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
436
diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c
437
index XXXXXXX..XXXXXXX 100644
438
--- a/target/riscv/m128_helper.c
439
+++ b/target/riscv/m128_helper.c
440
@@ -XXX,XX +XXX,XX @@
441
#include "exec/helper-proto.h"
442
443
target_ulong HELPER(divu_i128)(CPURISCVState *env,
444
- target_ulong ul, target_ulong uh,
445
- target_ulong vl, target_ulong vh)
446
+ target_ulong ul, target_ulong uh,
447
+ target_ulong vl, target_ulong vh)
448
{
449
target_ulong ql, qh;
450
Int128 q;
451
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(divu_i128)(CPURISCVState *env,
452
}
453
454
target_ulong HELPER(remu_i128)(CPURISCVState *env,
455
- target_ulong ul, target_ulong uh,
456
- target_ulong vl, target_ulong vh)
457
+ target_ulong ul, target_ulong uh,
458
+ target_ulong vl, target_ulong vh)
459
{
460
target_ulong rl, rh;
461
Int128 r;
462
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(remu_i128)(CPURISCVState *env,
463
}
464
465
target_ulong HELPER(divs_i128)(CPURISCVState *env,
466
- target_ulong ul, target_ulong uh,
467
- target_ulong vl, target_ulong vh)
468
+ target_ulong ul, target_ulong uh,
469
+ target_ulong vl, target_ulong vh)
470
{
471
target_ulong qh, ql;
472
Int128 q;
473
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(divs_i128)(CPURISCVState *env,
474
}
475
476
target_ulong HELPER(rems_i128)(CPURISCVState *env,
477
- target_ulong ul, target_ulong uh,
478
- target_ulong vl, target_ulong vh)
479
+ target_ulong ul, target_ulong uh,
480
+ target_ulong vl, target_ulong vh)
481
{
482
target_ulong rh, rl;
483
Int128 r;
484
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
485
index XXXXXXX..XXXXXXX 100644
486
--- a/target/riscv/machine.c
487
+++ b/target/riscv/machine.c
488
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
489
.minimum_version_id = 2,
490
.needed = vector_needed,
491
.fields = (VMStateField[]) {
492
- VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
493
- VMSTATE_UINTTL(env.vxrm, RISCVCPU),
494
- VMSTATE_UINTTL(env.vxsat, RISCVCPU),
495
- VMSTATE_UINTTL(env.vl, RISCVCPU),
496
- VMSTATE_UINTTL(env.vstart, RISCVCPU),
497
- VMSTATE_UINTTL(env.vtype, RISCVCPU),
498
- VMSTATE_BOOL(env.vill, RISCVCPU),
499
- VMSTATE_END_OF_LIST()
500
- }
501
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
502
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
503
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
504
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
505
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
506
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
507
+ VMSTATE_BOOL(env.vill, RISCVCPU),
508
+ VMSTATE_END_OF_LIST()
71
+ }
509
+ }
72
+
510
};
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
511
74
+ mode)) {
512
static bool pointermasking_needed(void *opaque)
75
+ *prot = 0;
513
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
76
+ return TRANSLATE_PMP_FAIL;
514
index XXXXXXX..XXXXXXX 100644
77
+ }
515
--- a/target/riscv/op_helper.c
78
+
516
+++ b/target/riscv/op_helper.c
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
517
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
80
+ if (tlb_size != NULL) {
518
if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
519
(rvs && prv_u && !env->virt_enabled)) {
82
+ *tlb_size = tlb_size_pmp;
520
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
83
+ }
521
- } else if (env->virt_enabled && (prv_u ||
84
+ }
522
- (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
85
+
523
+ } else if (env->virt_enabled &&
86
+ return TRANSLATE_SUCCESS;
524
+ (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
87
+}
525
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
88
+
526
} else {
89
/* get_physical_address - get the physical address for this virtual address
527
cs->halted = 1;
90
*
91
* Do a page table walk to obtain the physical address corresponding to a
92
@@ -XXX,XX +XXX,XX @@ restart:
93
pte_addr = base + idx * ptesize;
94
}
95
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
99
+ int pmp_prot;
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
101
+ sizeof(target_ulong),
102
+ MMU_DATA_LOAD, PRV_S);
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
104
return TRANSLATE_PMP_FAIL;
105
}
106
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
#ifndef CONFIG_USER_ONLY
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
154
}
155
+
156
if (ret == TRANSLATE_PMP_FAIL) {
157
pmp_violation = true;
158
}
159
160
if (ret == TRANSLATE_SUCCESS) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
163
- prot, mmu_idx, tlb_size);
164
- } else {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
528
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
174
index XXXXXXX..XXXXXXX 100644
529
index XXXXXXX..XXXXXXX 100644
175
--- a/target/riscv/pmp.c
530
--- a/target/riscv/pmp.c
176
+++ b/target/riscv/pmp.c
531
+++ b/target/riscv/pmp.c
532
@@ -XXX,XX +XXX,XX @@
533
#include "exec/exec-all.h"
534
535
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
536
- uint8_t val);
537
+ uint8_t val);
538
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
539
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
540
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
541
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
178
return result;
542
{
179
}
543
int result = 0;
180
544
181
+/*
545
- if ((addr >= env->pmp_state.addr[pmp_index].sa)
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
546
- && (addr <= env->pmp_state.addr[pmp_index].ea)) {
183
+ */
547
+ if ((addr >= env->pmp_state.addr[pmp_index].sa) &&
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
548
+ (addr <= env->pmp_state.addr[pmp_index].ea)) {
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
549
result = 1;
186
+ target_ulong mode)
550
} else {
187
+{
551
result = 0;
188
+ bool ret;
189
+
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
191
+ /*
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
194
+ */
195
+ ret = true;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
197
+ } else {
198
+ /*
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
200
+ * but there are rules. We've checked for no rule earlier in this
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
206
+
207
+ return ret;
208
+}
209
+
210
211
/*
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
552
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
553
* Check if the address has required RWX privs when no PMP entry is matched.
215
*/
554
*/
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
555
static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
556
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
557
- target_ulong mode)
219
+ target_ulong mode)
558
+ target_ulong size, pmp_priv_t privs,
559
+ pmp_priv_t *allowed_privs,
560
+ target_ulong mode)
561
{
562
bool ret;
563
564
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
565
* Return negtive value if no match
566
*/
567
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
568
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
569
- target_ulong mode)
570
+ target_ulong size, pmp_priv_t privs,
571
+ pmp_priv_t *allowed_privs, target_ulong mode)
220
{
572
{
221
int i = 0;
573
int i = 0;
222
int ret = -1;
574
int ret = -1;
223
int pmp_size = 0;
575
@@ -XXX,XX +XXX,XX @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
224
target_ulong s = 0;
576
* Handle a write to a pmpcfg CSR
225
target_ulong e = 0;
577
*/
226
- pmp_priv_t allowed_privs = 0;
578
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
227
579
- target_ulong val)
228
/* Short cut if no rules */
580
+ target_ulong val)
229
if (0 == pmp_get_num_rules(env)) {
581
{
230
- return (env->priv == PRV_M) ? true : false;
582
int i;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
583
uint8_t cfg_val;
232
+ allowed_privs, mode);
584
@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
233
}
585
* Handle a write to a pmpaddr CSR
234
586
*/
235
if (size == 0) {
587
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
588
- target_ulong val)
237
* check
589
+ target_ulong val)
238
*/
590
{
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
591
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
592
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
593
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
594
index XXXXXXX..XXXXXXX 100644
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
595
--- a/target/riscv/translate.c
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
596
+++ b/target/riscv/translate.c
245
}
597
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
246
598
} while (0)
247
- if ((privs & allowed_privs) == privs) {
599
248
- ret = 1;
600
#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
249
- break;
601
- if (!ctx->cfg_ptr->ext_##A && \
250
- } else {
602
- !ctx->cfg_ptr->ext_##B) { \
251
- ret = 0;
603
+ if (!ctx->cfg_ptr->ext_##A && \
252
- break;
604
+ !ctx->cfg_ptr->ext_##B) { \
253
- }
605
return false; \
254
+ ret = ((privs & *allowed_privs) == privs);
606
} \
255
+ break;
607
} while (0)
608
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
609
index XXXXXXX..XXXXXXX 100644
610
--- a/target/riscv/vector_helper.c
611
+++ b/target/riscv/vector_helper.c
612
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
256
}
613
}
257
}
614
}
258
615
259
/* No rule matched */
616
- if ((sew > cpu->cfg.elen)
260
if (ret == -1) {
617
- || vill
261
- if (mode == PRV_M) {
618
- || (ediv != 0)
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
619
- || (reserved != 0)) {
263
- * M-Mode access, the access succeeds */
620
+ if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
264
- } else {
621
/* only set vill bit. */
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
622
env->vill = 1;
266
- * match a rule, but there are rules. We've checked for
623
env->vtype = 0;
267
- * no rule earlier in this function. */
624
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
268
- }
625
\
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
626
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
270
+ allowed_privs, mode);
627
} \
628
- env->vstart = 0; \
629
+ env->vstart = 0; \
630
/* set tail elements to 1s */ \
631
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
632
}
633
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
634
/* generate the helpers for shift instructions with one vector and one scalar */
635
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
636
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
637
- void *vs2, CPURISCVState *env, uint32_t desc) \
638
+ void *vs2, CPURISCVState *env, \
639
+ uint32_t desc) \
640
{ \
641
uint32_t vm = vext_vm(desc); \
642
uint32_t vl = env->vl; \
643
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VX(vmulhsu_vx_d, 8)
644
/* Vector Integer Divide Instructions */
645
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
646
#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
647
-#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
648
+#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : \
649
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
650
-#define DO_REM(N, M) (unlikely(M == 0) ? N :\
651
+#define DO_REM(N, M) (unlikely(M == 0) ? N : \
652
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
653
654
RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
655
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VX(vwmulsu_vx_h, 4)
656
GEN_VEXT_VX(vwmulsu_vx_w, 8)
657
658
/* Vector Single-Width Integer Multiply-Add Instructions */
659
-#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
660
+#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
661
static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
662
{ \
663
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
664
@@ -XXX,XX +XXX,XX @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
665
/* generate helpers for fixed point instructions with OPIVX format */
666
#define GEN_VEXT_VX_RM(NAME, ESZ) \
667
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
668
- void *vs2, CPURISCVState *env, uint32_t desc) \
669
+ void *vs2, CPURISCVState *env, \
670
+ uint32_t desc) \
671
{ \
672
vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \
673
do_##NAME, ESZ); \
674
@@ -XXX,XX +XXX,XX @@ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
675
676
res = (int16_t)a * (int16_t)b;
677
round = get_round(vxrm, res, 7);
678
- res = (res >> 7) + round;
679
+ res = (res >> 7) + round;
680
681
if (res > INT8_MAX) {
682
env->vxsat = 0x1;
683
@@ -XXX,XX +XXX,XX @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
684
685
res = (int32_t)a * (int32_t)b;
686
round = get_round(vxrm, res, 15);
687
- res = (res >> 15) + round;
688
+ res = (res >> 15) + round;
689
690
if (res > INT16_MAX) {
691
env->vxsat = 0x1;
692
@@ -XXX,XX +XXX,XX @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
693
694
res = (int64_t)a * (int64_t)b;
695
round = get_round(vxrm, res, 31);
696
- res = (res >> 31) + round;
697
+ res = (res >> 31) + round;
698
699
if (res > INT32_MAX) {
700
env->vxsat = 0x1;
701
@@ -XXX,XX +XXX,XX @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
702
uint8_t res;
703
704
round = get_round(vxrm, a, shift);
705
- res = (a >> shift) + round;
706
+ res = (a >> shift) + round;
707
return res;
708
}
709
static inline uint16_t
710
@@ -XXX,XX +XXX,XX @@ vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b)
711
int16_t res;
712
713
round = get_round(vxrm, a, shift);
714
- res = (a >> shift) + round;
715
+ res = (a >> shift) + round;
716
if (res > INT8_MAX) {
717
env->vxsat = 0x1;
718
return INT8_MAX;
719
@@ -XXX,XX +XXX,XX @@ vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b)
720
int32_t res;
721
722
round = get_round(vxrm, a, shift);
723
- res = (a >> shift) + round;
724
+ res = (a >> shift) + round;
725
if (res > INT16_MAX) {
726
env->vxsat = 0x1;
727
return INT16_MAX;
728
@@ -XXX,XX +XXX,XX @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
729
int64_t res;
730
731
round = get_round(vxrm, a, shift);
732
- res = (a >> shift) + round;
733
+ res = (a >> shift) + round;
734
if (res > INT32_MAX) {
735
env->vxsat = 0x1;
736
return INT32_MAX;
737
@@ -XXX,XX +XXX,XX @@ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
738
uint16_t res;
739
740
round = get_round(vxrm, a, shift);
741
- res = (a >> shift) + round;
742
+ res = (a >> shift) + round;
743
if (res > UINT8_MAX) {
744
env->vxsat = 0x1;
745
return UINT8_MAX;
746
@@ -XXX,XX +XXX,XX @@ vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b)
747
uint32_t res;
748
749
round = get_round(vxrm, a, shift);
750
- res = (a >> shift) + round;
751
+ res = (a >> shift) + round;
752
if (res > UINT16_MAX) {
753
env->vxsat = 0x1;
754
return UINT16_MAX;
755
@@ -XXX,XX +XXX,XX @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
756
uint64_t res;
757
758
round = get_round(vxrm, a, shift);
759
- res = (a >> shift) + round;
760
+ res = (a >> shift) + round;
761
if (res > UINT32_MAX) {
762
env->vxsat = 0x1;
763
return UINT32_MAX;
764
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
765
uint32_t vm = vext_vm(desc); \
766
uint32_t vl = env->vl; \
767
uint32_t total_elems = \
768
- vext_get_total_elems(env, desc, ESZ); \
769
+ vext_get_total_elems(env, desc, ESZ); \
770
uint32_t vta = vext_vta(desc); \
771
uint32_t vma = vext_vma(desc); \
772
uint32_t i; \
773
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfrsub_vf_d, 8)
774
static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
775
{
776
return float32_add(float16_to_float32(a, true, s),
777
- float16_to_float32(b, true, s), s);
778
+ float16_to_float32(b, true, s), s);
779
}
780
781
static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
782
{
783
return float64_add(float32_to_float64(a, s),
784
- float32_to_float64(b, s), s);
785
+ float32_to_float64(b, s), s);
786
787
}
788
789
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwadd_vf_w, 8)
790
static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
791
{
792
return float32_sub(float16_to_float32(a, true, s),
793
- float16_to_float32(b, true, s), s);
794
+ float16_to_float32(b, true, s), s);
795
}
796
797
static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
798
{
799
return float64_sub(float32_to_float64(a, s),
800
- float32_to_float64(b, s), s);
801
+ float32_to_float64(b, s), s);
802
803
}
804
805
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfrdiv_vf_d, 8)
806
static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
807
{
808
return float32_mul(float16_to_float32(a, true, s),
809
- float16_to_float32(b, true, s), s);
810
+ float16_to_float32(b, true, s), s);
811
}
812
813
static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
814
{
815
return float64_mul(float32_to_float64(a, s),
816
- float32_to_float64(b, s), s);
817
+ float32_to_float64(b, s), s);
818
819
}
820
RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
821
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwmul_vf_w, 8)
822
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
823
#define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
824
static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
825
- CPURISCVState *env) \
826
+ CPURISCVState *env) \
827
{ \
828
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
829
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
830
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VV_ENV(vfmacc_vv_d, 8)
831
832
#define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
833
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
834
- CPURISCVState *env) \
835
+ CPURISCVState *env) \
836
{ \
837
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
838
TD d = *((TD *)vd + HD(i)); \
839
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfmacc_vf_d, 8)
840
841
static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
842
{
843
- return float16_muladd(a, b, d,
844
- float_muladd_negate_c | float_muladd_negate_product, s);
845
+ return float16_muladd(a, b, d, float_muladd_negate_c |
846
+ float_muladd_negate_product, s);
847
}
848
849
static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
850
{
851
- return float32_muladd(a, b, d,
852
- float_muladd_negate_c | float_muladd_negate_product, s);
853
+ return float32_muladd(a, b, d, float_muladd_negate_c |
854
+ float_muladd_negate_product, s);
855
}
856
857
static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
858
{
859
- return float64_muladd(a, b, d,
860
- float_muladd_negate_c | float_muladd_negate_product, s);
861
+ return float64_muladd(a, b, d, float_muladd_negate_c |
862
+ float_muladd_negate_product, s);
863
}
864
865
RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
866
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfmadd_vf_d, 8)
867
868
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
869
{
870
- return float16_muladd(d, b, a,
871
- float_muladd_negate_c | float_muladd_negate_product, s);
872
+ return float16_muladd(d, b, a, float_muladd_negate_c |
873
+ float_muladd_negate_product, s);
874
}
875
876
static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
877
{
878
- return float32_muladd(d, b, a,
879
- float_muladd_negate_c | float_muladd_negate_product, s);
880
+ return float32_muladd(d, b, a, float_muladd_negate_c |
881
+ float_muladd_negate_product, s);
882
}
883
884
static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
885
{
886
- return float64_muladd(d, b, a,
887
- float_muladd_negate_c | float_muladd_negate_product, s);
888
+ return float64_muladd(d, b, a, float_muladd_negate_c |
889
+ float_muladd_negate_product, s);
890
}
891
892
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
893
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfnmsub_vf_d, 8)
894
static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
895
{
896
return float32_muladd(float16_to_float32(a, true, s),
897
- float16_to_float32(b, true, s), d, 0, s);
898
+ float16_to_float32(b, true, s), d, 0, s);
899
}
900
901
static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
902
{
903
return float64_muladd(float32_to_float64(a, s),
904
- float32_to_float64(b, s), d, 0, s);
905
+ float32_to_float64(b, s), d, 0, s);
906
}
907
908
RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
909
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwmacc_vf_w, 8)
910
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
911
{
912
return float32_muladd(float16_to_float32(a, true, s),
913
- float16_to_float32(b, true, s), d,
914
- float_muladd_negate_c | float_muladd_negate_product, s);
915
+ float16_to_float32(b, true, s), d,
916
+ float_muladd_negate_c | float_muladd_negate_product,
917
+ s);
918
}
919
920
static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
921
{
922
- return float64_muladd(float32_to_float64(a, s),
923
- float32_to_float64(b, s), d,
924
- float_muladd_negate_c | float_muladd_negate_product, s);
925
+ return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, s),
926
+ d, float_muladd_negate_c |
927
+ float_muladd_negate_product, s);
928
}
929
930
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
931
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmacc_vf_w, 8)
932
static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
933
{
934
return float32_muladd(float16_to_float32(a, true, s),
935
- float16_to_float32(b, true, s), d,
936
- float_muladd_negate_c, s);
937
+ float16_to_float32(b, true, s), d,
938
+ float_muladd_negate_c, s);
939
}
940
941
static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
942
{
943
return float64_muladd(float32_to_float64(a, s),
944
- float32_to_float64(b, s), d,
945
- float_muladd_negate_c, s);
946
+ float32_to_float64(b, s), d,
947
+ float_muladd_negate_c, s);
948
}
949
950
RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
951
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwmsac_vf_w, 8)
952
static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
953
{
954
return float32_muladd(float16_to_float32(a, true, s),
955
- float16_to_float32(b, true, s), d,
956
- float_muladd_negate_product, s);
957
+ float16_to_float32(b, true, s), d,
958
+ float_muladd_negate_product, s);
959
}
960
961
static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
962
{
963
return float64_muladd(float32_to_float64(a, s),
964
- float32_to_float64(b, s), d,
965
- float_muladd_negate_product, s);
966
+ float32_to_float64(b, s), d,
967
+ float_muladd_negate_product, s);
968
}
969
970
RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
971
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmsac_vf_w, 8)
972
#define OP_UU_W uint32_t, uint32_t, uint32_t
973
#define OP_UU_D uint64_t, uint64_t, uint64_t
974
975
-#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
976
+#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
977
static void do_##NAME(void *vd, void *vs2, int i, \
978
- CPURISCVState *env) \
979
+ CPURISCVState *env) \
980
{ \
981
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
982
*((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \
983
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i, \
984
985
#define GEN_VEXT_V_ENV(NAME, ESZ) \
986
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
987
- CPURISCVState *env, uint32_t desc) \
988
+ CPURISCVState *env, uint32_t desc) \
989
{ \
990
uint32_t vm = vext_vm(desc); \
991
uint32_t vl = env->vl; \
992
@@ -XXX,XX +XXX,XX @@ static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size)
271
}
993
}
272
994
273
return ret == 1 ? true : false;
995
int idx = ((exp & 1) << (precision - 1)) |
274
}
996
- (frac >> (frac_size - precision + 1));
275
997
+ (frac >> (frac_size - precision + 1));
276
-
998
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
999
- (frac_size - precision);
1000
+ (frac_size - precision);
1001
uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2;
1002
1003
uint64_t val = 0;
1004
@@ -XXX,XX +XXX,XX @@ static float16 frsqrt7_h(float16 f, float_status *s)
1005
* frsqrt7(-subnormal) = canonical NaN
1006
*/
1007
if (float16_is_signaling_nan(f, s) ||
1008
- (float16_is_infinity(f) && sign) ||
1009
- (float16_is_normal(f) && sign) ||
1010
- (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
1011
+ (float16_is_infinity(f) && sign) ||
1012
+ (float16_is_normal(f) && sign) ||
1013
+ (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
1014
s->float_exception_flags |= float_flag_invalid;
1015
return float16_default_nan(s);
1016
}
1017
@@ -XXX,XX +XXX,XX @@ static float32 frsqrt7_s(float32 f, float_status *s)
1018
* frsqrt7(-subnormal) = canonical NaN
1019
*/
1020
if (float32_is_signaling_nan(f, s) ||
1021
- (float32_is_infinity(f) && sign) ||
1022
- (float32_is_normal(f) && sign) ||
1023
- (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
1024
+ (float32_is_infinity(f) && sign) ||
1025
+ (float32_is_normal(f) && sign) ||
1026
+ (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
1027
s->float_exception_flags |= float_flag_invalid;
1028
return float32_default_nan(s);
1029
}
1030
@@ -XXX,XX +XXX,XX @@ static float64 frsqrt7_d(float64 f, float_status *s)
1031
* frsqrt7(-subnormal) = canonical NaN
1032
*/
1033
if (float64_is_signaling_nan(f, s) ||
1034
- (float64_is_infinity(f) && sign) ||
1035
- (float64_is_normal(f) && sign) ||
1036
- (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
1037
+ (float64_is_infinity(f) && sign) ||
1038
+ (float64_is_normal(f) && sign) ||
1039
+ (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
1040
s->float_exception_flags |= float_flag_invalid;
1041
return float64_default_nan(s);
1042
}
1043
@@ -XXX,XX +XXX,XX @@ static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
1044
((s->float_rounding_mode == float_round_up) && sign)) {
1045
/* Return greatest/negative finite value. */
1046
return (sign << (exp_size + frac_size)) |
1047
- (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
1048
+ (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
1049
} else {
1050
/* Return +-inf. */
1051
return (sign << (exp_size + frac_size)) |
1052
- MAKE_64BIT_MASK(frac_size, exp_size);
1053
+ MAKE_64BIT_MASK(frac_size, exp_size);
1054
}
1055
}
1056
}
1057
1058
int idx = frac >> (frac_size - precision);
1059
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
1060
- (frac_size - precision);
1061
+ (frac_size - precision);
1062
uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
1063
1064
if (out_exp == 0 || out_exp == UINT64_MAX) {
1065
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
1066
\
1067
for (i = env->vstart; i < vl; i++) { \
1068
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1069
- *((ETYPE *)vd + H(i)) \
1070
- = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
1071
+ *((ETYPE *)vd + H(i)) = \
1072
+ (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
1073
} \
1074
env->vstart = 0; \
1075
/* set tail elements to 1s */ \
1076
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
1077
/* Vector Single-Width Integer Reduction Instructions */
1078
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
1079
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1080
- void *vs2, CPURISCVState *env, uint32_t desc) \
1081
+ void *vs2, CPURISCVState *env, \
1082
+ uint32_t desc) \
1083
{ \
1084
uint32_t vm = vext_vm(desc); \
1085
uint32_t vl = env->vl; \
1086
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
1087
1088
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
1089
static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
1090
- void *vs2, CPURISCVState *env, uint32_t desc) \
1091
+ void *vs2, CPURISCVState *env, \
1092
+ uint32_t desc) \
1093
{ \
1094
typedef uint##BITWIDTH##_t ETYPE; \
1095
uint32_t vm = vext_vm(desc); \
1096
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
1097
1098
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
1099
static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
1100
- void *vs2, CPURISCVState *env, uint32_t desc) \
1101
+ void *vs2, CPURISCVState *env, \
1102
+ uint32_t desc) \
1103
{ \
1104
typedef uint##BITWIDTH##_t ETYPE; \
1105
uint32_t vm = vext_vm(desc); \
1106
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
1107
index XXXXXXX..XXXXXXX 100644
1108
--- a/target/riscv/insn_trans/trans_rvv.c.inc
1109
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
1110
@@ -XXX,XX +XXX,XX @@ static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew)
1111
{
1112
int8_t emul = eew - s->sew + s->lmul;
1113
return (emul >= -3 && emul <= 3) &&
1114
- require_align(vd, emul) &&
1115
- require_nf(vd, nf, emul);
1116
+ require_align(vd, emul) &&
1117
+ require_nf(vd, nf, emul);
1118
}
1119
277
/*
1120
/*
278
* Handle a write to a pmpcfg CSP
1121
@@ -XXX,XX +XXX,XX @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
279
*/
1122
int8_t seg_vd;
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
1123
int8_t emul = eew - s->sew + s->lmul;
281
1124
bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
282
return false;
1125
- require_vm(vm, vd);
283
}
1126
+ require_vm(vm, vd);
284
+
1127
285
+/*
1128
/* Each segment register group has to follow overlap rules. */
286
+ * Convert PMP privilege to TLB page privilege.
1129
for (int i = 0; i < nf; ++i) {
287
+ */
1130
@@ -XXX,XX +XXX,XX @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
1131
static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
289
+{
1132
{
290
+ int prot = 0;
1133
return require_vm(vm, vd) &&
291
+
1134
- require_align(vd, s->lmul) &&
292
+ if (pmp_priv & PMP_READ) {
1135
- require_align(vs, s->lmul);
293
+ prot |= PAGE_READ;
1136
+ require_align(vd, s->lmul) &&
294
+ }
1137
+ require_align(vs, s->lmul);
295
+ if (pmp_priv & PMP_WRITE) {
1138
}
296
+ prot |= PAGE_WRITE;
1139
297
+ }
1140
/*
298
+ if (pmp_priv & PMP_EXEC) {
1141
@@ -XXX,XX +XXX,XX @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
299
+ prot |= PAGE_EXEC;
1142
static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
300
+ }
1143
{
301
+
1144
return vext_check_ss(s, vd, vs2, vm) &&
302
+ return prot;
1145
- require_align(vs1, s->lmul);
303
+}
1146
+ require_align(vs1, s->lmul);
1147
}
1148
1149
static bool vext_check_ms(DisasContext *s, int vd, int vs)
1150
@@ -XXX,XX +XXX,XX @@ static bool vext_check_ms(DisasContext *s, int vd, int vs)
1151
static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
1152
{
1153
bool ret = vext_check_ms(s, vd, vs2) &&
1154
- require_align(vs1, s->lmul);
1155
+ require_align(vs1, s->lmul);
1156
if (vd != vs1) {
1157
ret &= require_noover(vd, 0, vs1, s->lmul);
1158
}
1159
@@ -XXX,XX +XXX,XX @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
1160
static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
1161
{
1162
return vext_wide_check_common(s, vd, vm) &&
1163
- require_align(vs, s->lmul) &&
1164
- require_noover(vd, s->lmul + 1, vs, s->lmul);
1165
+ require_align(vs, s->lmul) &&
1166
+ require_noover(vd, s->lmul + 1, vs, s->lmul);
1167
}
1168
1169
static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
1170
{
1171
return vext_wide_check_common(s, vd, vm) &&
1172
- require_align(vs, s->lmul + 1);
1173
+ require_align(vs, s->lmul + 1);
1174
}
1175
1176
/*
1177
@@ -XXX,XX +XXX,XX @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
1178
static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
1179
{
1180
return vext_check_ds(s, vd, vs2, vm) &&
1181
- require_align(vs1, s->lmul) &&
1182
- require_noover(vd, s->lmul + 1, vs1, s->lmul);
1183
+ require_align(vs1, s->lmul) &&
1184
+ require_noover(vd, s->lmul + 1, vs1, s->lmul);
1185
}
1186
1187
/*
1188
@@ -XXX,XX +XXX,XX @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
1189
static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
1190
{
1191
return vext_check_ds(s, vd, vs1, vm) &&
1192
- require_align(vs2, s->lmul + 1);
1193
+ require_align(vs2, s->lmul + 1);
1194
}
1195
1196
static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
1197
@@ -XXX,XX +XXX,XX @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
1198
static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
1199
{
1200
return vext_check_sd(s, vd, vs2, vm) &&
1201
- require_align(vs1, s->lmul);
1202
+ require_align(vs1, s->lmul);
1203
}
1204
1205
/*
304
--
1206
--
305
2.30.1
1207
2.40.0
306
307
diff view generated by jsdifflib
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
[PULL 30/89] target/riscv: Fix format for comments
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
According to the specification the "field SPVP of hstatus controls the
3
Fix formats for multi-lines comments.
4
privilege level of the access" for the hypervisor virtual-machine load
4
Add spaces around single line comments(after "/*" and before "*/").
5
and store instructions HLV, HLVX and HSV.
6
5
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Acked-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
15
target/riscv/cpu.h | 26 ++++----
13
1 file changed, 14 insertions(+), 11 deletions(-)
16
target/riscv/cpu_bits.h | 2 +-
17
target/riscv/sbi_ecall_interface.h | 8 +--
18
target/riscv/arch_dump.c | 3 +-
19
target/riscv/cpu.c | 2 +-
20
target/riscv/cpu_helper.c | 57 +++++++++++------
21
target/riscv/csr.c | 6 +-
22
target/riscv/pmp.c | 41 +++++++------
23
target/riscv/translate.c | 20 +++---
24
target/riscv/vector_helper.c | 82 +++++++++++++++----------
25
target/riscv/insn_trans/trans_rvv.c.inc | 8 ++-
26
11 files changed, 151 insertions(+), 104 deletions(-)
14
27
28
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/riscv/cpu.h
31
+++ b/target/riscv/cpu.h
32
@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
33
typedef struct PMUCTRState {
34
/* Current value of a counter */
35
target_ulong mhpmcounter_val;
36
- /* Current value of a counter in RV32*/
37
+ /* Current value of a counter in RV32 */
38
target_ulong mhpmcounterh_val;
39
/* Snapshot values of counter */
40
target_ulong mhpmcounter_prev;
41
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
42
target_ulong satp_hs;
43
uint64_t mstatus_hs;
44
45
- /* Signals whether the current exception occurred with two-stage address
46
- translation active. */
47
+ /*
48
+ * Signals whether the current exception occurred with two-stage address
49
+ * translation active.
50
+ */
51
bool two_stage_lookup;
52
/*
53
* Signals whether the current exception occurred while doing two-stage
54
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
55
/* PMU counter state */
56
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
57
58
- /* PMU event selector configured values. First three are unused*/
59
+ /* PMU event selector configured values. First three are unused */
60
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
61
62
- /* PMU event selector configured values for RV32*/
63
+ /* PMU event selector configured values for RV32 */
64
target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
65
66
target_ulong sscratch;
67
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
68
69
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
70
71
-/**
72
+/*
73
* RISCVCPUClass:
74
* @parent_realize: The parent class' realize handler.
75
* @parent_phases: The parent class' reset phase handlers.
76
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
77
* A RISCV CPU model.
78
*/
79
struct RISCVCPUClass {
80
- /*< private >*/
81
+ /* < private > */
82
CPUClass parent_class;
83
- /*< public >*/
84
+ /* < public > */
85
DeviceRealize parent_realize;
86
ResettablePhases parent_phases;
87
};
88
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
89
90
typedef struct RISCVCPUConfig RISCVCPUConfig;
91
92
-/**
93
+/*
94
* RISCVCPU:
95
* @env: #CPURISCVState
96
*
97
* A RISCV CPU.
98
*/
99
struct ArchCPU {
100
- /*< private >*/
101
+ /* < private > */
102
CPUState parent_obj;
103
- /*< public >*/
104
+ /* < public > */
105
CPUNegativeOffsetState neg;
106
CPURISCVState env;
107
108
@@ -XXX,XX +XXX,XX @@ enum {
109
CSR_TABLE_SIZE = 0x1000
110
};
111
112
-/**
113
+/*
114
* The event id are encoded based on the encoding specified in the
115
* SBI specification v0.3
116
*/
117
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/riscv/cpu_bits.h
120
+++ b/target/riscv/cpu_bits.h
121
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
122
#define MIE_SSIE (1 << IRQ_S_SOFT)
123
#define MIE_USIE (1 << IRQ_U_SOFT)
124
125
-/* General PointerMasking CSR bits*/
126
+/* General PointerMasking CSR bits */
127
#define PM_ENABLE 0x00000001ULL
128
#define PM_CURRENT 0x00000002ULL
129
#define PM_INSN 0x00000004ULL
130
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/riscv/sbi_ecall_interface.h
133
+++ b/target/riscv/sbi_ecall_interface.h
134
@@ -XXX,XX +XXX,XX @@
135
#define SBI_EXT_RFENCE 0x52464E43
136
#define SBI_EXT_HSM 0x48534D
137
138
-/* SBI function IDs for BASE extension*/
139
+/* SBI function IDs for BASE extension */
140
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
141
#define SBI_EXT_BASE_GET_IMP_ID 0x1
142
#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
143
@@ -XXX,XX +XXX,XX @@
144
#define SBI_EXT_BASE_GET_MARCHID 0x5
145
#define SBI_EXT_BASE_GET_MIMPID 0x6
146
147
-/* SBI function IDs for TIME extension*/
148
+/* SBI function IDs for TIME extension */
149
#define SBI_EXT_TIME_SET_TIMER 0x0
150
151
-/* SBI function IDs for IPI extension*/
152
+/* SBI function IDs for IPI extension */
153
#define SBI_EXT_IPI_SEND_IPI 0x0
154
155
-/* SBI function IDs for RFENCE extension*/
156
+/* SBI function IDs for RFENCE extension */
157
#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
158
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
159
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
160
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/riscv/arch_dump.c
163
+++ b/target/riscv/arch_dump.c
164
@@ -XXX,XX +XXX,XX @@
165
-/* Support for writing ELF notes for RISC-V architectures
166
+/*
167
+ * Support for writing ELF notes for RISC-V architectures
168
*
169
* Copyright (C) 2021 Huawei Technologies Co., Ltd
170
*
171
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
172
index XXXXXXX..XXXXXXX 100644
173
--- a/target/riscv/cpu.c
174
+++ b/target/riscv/cpu.c
175
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
176
#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
177
{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
178
179
-/**
180
+/*
181
* Here are the ordering rules of extension naming defined by RISC-V
182
* specification :
183
* 1. All extensions should be separated from other multi-letter extensions
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
184
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
185
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
186
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
187
+++ b/target/riscv/cpu_helper.c
188
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
189
return TRANSLATE_SUCCESS;
190
}
191
192
-/* get_physical_address - get the physical address for this virtual address
193
+/*
194
+ * get_physical_address - get the physical address for this virtual address
195
*
196
* Do a page table walk to obtain the physical address corresponding to a
197
* virtual address. Returns 0 if the translation was successful
198
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
199
bool first_stage, bool two_stage,
200
bool is_debug)
201
{
202
- /* NOTE: the env->pc value visible here will not be
203
+ /*
204
+ * NOTE: the env->pc value visible here will not be
205
* correct, but the value visible to the exception handler
206
- * (riscv_cpu_do_interrupt) is correct */
207
+ * (riscv_cpu_do_interrupt) is correct
208
+ */
209
MemTxResult res;
210
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
211
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
212
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
20
use_background = true;
213
use_background = true;
21
}
214
}
22
215
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
216
- /* MPRV does not affect the virtual-machine load/store
24
+ /* MPRV does not affect the virtual-machine load/store
217
- instructions, HLV, HLVX, and HSV. */
25
+ instructions, HLV, HLVX, and HSV. */
218
+ /*
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
219
+ * MPRV does not affect the virtual-machine load/store
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
220
+ * instructions, HLV, HLVX, and HSV.
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
221
+ */
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
222
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
30
mode = get_field(env->mstatus, MSTATUS_MPP);
223
mode = get_field(env->hstatus, HSTATUS_SPVP);
31
}
224
} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
225
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
226
}
227
228
if (first_stage == false) {
229
- /* We are in stage 2 translation, this is similar to stage 1. */
230
- /* Stage 2 is always taken as U-mode */
231
+ /*
232
+ * We are in stage 2 translation, this is similar to stage 1.
233
+ * Stage 2 is always taken as U-mode
234
+ */
235
mode = PRV_U;
236
}
237
238
@@ -XXX,XX +XXX,XX @@ restart:
239
target_ulong *pte_pa =
240
qemu_map_ram_ptr(mr->ram_block, addr1);
241
#if TCG_OVERSIZED_GUEST
242
- /* MTTCG is not enabled on oversized TCG guests so
243
- * page table updates do not need to be atomic */
244
+ /*
245
+ * MTTCG is not enabled on oversized TCG guests so
246
+ * page table updates do not need to be atomic
247
+ */
248
*pte_pa = pte = updated_pte;
249
#else
250
target_ulong old_pte =
251
@@ -XXX,XX +XXX,XX @@ restart:
252
}
253
#endif
254
} else {
255
- /* misconfigured PTE in ROM (AD bits are not preset) or
256
- * PTE is in IO space and can't be updated atomically */
257
+ /*
258
+ * misconfigured PTE in ROM (AD bits are not preset) or
259
+ * PTE is in IO space and can't be updated atomically
260
+ */
261
return TRANSLATE_FAIL;
262
}
263
}
264
265
- /* for superpage mappings, make a fake leaf PTE for the TLB's
266
- benefit. */
267
+ /*
268
+ * for superpage mappings, make a fake leaf PTE for the TLB's
269
+ * benefit.
270
+ */
271
target_ulong vpn = addr >> PGSHIFT;
272
273
if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
274
@@ -XXX,XX +XXX,XX @@ restart:
275
if (pte & PTE_X) {
276
*prot |= PAGE_EXEC;
277
}
278
- /* add write permission on stores or if the page is already dirty,
279
- so that we TLB miss on later writes to update the dirty bit */
280
+ /*
281
+ * add write permission on stores or if the page is already dirty,
282
+ * so that we TLB miss on later writes to update the dirty bit
283
+ */
284
if ((pte & PTE_W) &&
285
(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
286
*prot |= PAGE_WRITE;
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
287
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
288
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
34
__func__, address, access_type, mmu_idx);
289
__func__, address, access_type, mmu_idx);
35
290
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
291
- /* MPRV does not affect the virtual-machine load/store
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
292
- instructions, HLV, HLVX, and HSV. */
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
293
+ /*
39
+ /* MPRV does not affect the virtual-machine load/store
294
+ * MPRV does not affect the virtual-machine load/store
40
+ instructions, HLV, HLVX, and HSV. */
295
+ * instructions, HLV, HLVX, and HSV.
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
296
+ */
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
297
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
298
mode = get_field(env->hstatus, HSTATUS_SPVP);
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
299
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
300
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
301
bool write_gva = false;
47
+ two_stage_lookup = true;
302
uint64_t s;
303
304
- /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
305
+ /*
306
+ * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
307
* so we mask off the MSB and separate into trap type and cause.
308
*/
309
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
310
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
311
riscv_cpu_set_mode(env, PRV_M);
312
}
313
314
- /* NOTE: it is not necessary to yield load reservations here. It is only
315
+ /*
316
+ * NOTE: it is not necessary to yield load reservations here. It is only
317
* necessary for an SC from "another hart" to cause a load reservation
318
* to be yielded. Refer to the memory consistency model section of the
319
* RISC-V ISA Specification.
320
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
321
index XXXXXXX..XXXXXXX 100644
322
--- a/target/riscv/csr.c
323
+++ b/target/riscv/csr.c
324
@@ -XXX,XX +XXX,XX @@ static RISCVException mctr(CPURISCVState *env, int csrno)
325
}
326
ctr_index = csrno - base_csrno;
327
if (!pmu_num || ctr_index >= pmu_num) {
328
- /* The PMU is not enabled or counter is out of range*/
329
+ /* The PMU is not enabled or counter is out of range */
330
return RISCV_EXCP_ILLEGAL_INST;
331
}
332
333
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
334
counter.mhpmcounter_val;
335
336
if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
337
- /**
338
+ /*
339
* Counter should not increment if inhibit bit is set. We can't really
340
* stop the icount counting. Just return the counter value written by
341
* the supervisor to indicate that counter was not incremented.
342
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
48
}
343
}
49
}
344
}
50
345
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
346
- /**
52
- access_type != MMU_INST_FETCH &&
347
+ /*
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
348
* The kernel computes the perf delta by subtracting the current value from
54
- get_field(env->mstatus, MSTATUS_MPV)) {
349
* the value it initialized previously (ctr_val).
55
- two_stage_lookup = true;
350
*/
56
- }
351
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
57
-
352
index XXXXXXX..XXXXXXX 100644
58
if (riscv_cpu_virt_enabled(env) ||
353
--- a/target/riscv/pmp.c
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
354
+++ b/target/riscv/pmp.c
60
access_type != MMU_INST_FETCH)) {
355
@@ -XXX,XX +XXX,XX @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
356
static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
357
{
358
/*
359
- aaaa...aaa0 8-byte NAPOT range
360
- aaaa...aa01 16-byte NAPOT range
361
- aaaa...a011 32-byte NAPOT range
362
- ...
363
- aa01...1111 2^XLEN-byte NAPOT range
364
- a011...1111 2^(XLEN+1)-byte NAPOT range
365
- 0111...1111 2^(XLEN+2)-byte NAPOT range
366
- 1111...1111 Reserved
367
- */
368
+ * aaaa...aaa0 8-byte NAPOT range
369
+ * aaaa...aa01 16-byte NAPOT range
370
+ * aaaa...a011 32-byte NAPOT range
371
+ * ...
372
+ * aa01...1111 2^XLEN-byte NAPOT range
373
+ * a011...1111 2^(XLEN+1)-byte NAPOT range
374
+ * 0111...1111 2^(XLEN+2)-byte NAPOT range
375
+ * 1111...1111 Reserved
376
+ */
377
a = (a << 2) | 0x3;
378
*sa = a & (a + 1);
379
*ea = a | (a + 1);
380
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env)
381
}
382
}
383
384
-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
385
+/*
386
+ * Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
387
* end address values.
388
* This function is called relatively infrequently whereas the check that
389
* an address is within a pmp rule is called often, so optimise that one
390
@@ -XXX,XX +XXX,XX @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
391
pmp_size = size;
392
}
393
394
- /* 1.10 draft priv spec states there is an implicit order
395
- from low to high */
396
+ /*
397
+ * 1.10 draft priv spec states there is an implicit order
398
+ * from low to high
399
+ */
400
for (i = 0; i < MAX_RISCV_PMPS; i++) {
401
s = pmp_is_in_range(env, i, addr);
402
e = pmp_is_in_range(env, i, addr + pmp_size - 1);
403
@@ -XXX,XX +XXX,XX @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
404
return TARGET_PAGE_SIZE;
405
} else {
406
/*
407
- * At this point we have a tlb_size that is the smallest possible size
408
- * That fits within a TARGET_PAGE_SIZE and the PMP region.
409
- *
410
- * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
411
- * This means the result isn't cached in the TLB and is only used for
412
- * a single translation.
413
- */
414
+ * At this point we have a tlb_size that is the smallest possible size
415
+ * That fits within a TARGET_PAGE_SIZE and the PMP region.
416
+ *
417
+ * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
418
+ * This means the result isn't cached in the TLB and is only used for
419
+ * a single translation.
420
+ */
421
return 1;
422
}
423
}
424
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
425
index XXXXXXX..XXXXXXX 100644
426
--- a/target/riscv/translate.c
427
+++ b/target/riscv/translate.c
428
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
429
uint32_t mstatus_hs_fs;
430
uint32_t mstatus_hs_vs;
431
uint32_t mem_idx;
432
- /* Remember the rounding mode encoded in the previous fp instruction,
433
- which we have already installed into env->fp_status. Or -1 for
434
- no previous fp instruction. Note that we exit the TB when writing
435
- to any system register, which includes CSR_FRM, so we do not have
436
- to reset this known value. */
437
+ /*
438
+ * Remember the rounding mode encoded in the previous fp instruction,
439
+ * which we have already installed into env->fp_status. Or -1 for
440
+ * no previous fp instruction. Note that we exit the TB when writing
441
+ * to any system register, which includes CSR_FRM, so we do not have
442
+ * to reset this known value.
443
+ */
444
int frm;
445
RISCVMXL ol;
446
bool virt_inst_excp;
447
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
448
}
449
}
450
451
-/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
452
+/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
453
static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
454
{
455
if (!ctx->cfg_ptr->ext_zfinx) {
456
@@ -XXX,XX +XXX,XX @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
457
}
458
459
#ifndef CONFIG_USER_ONLY
460
-/* The states of mstatus_fs are:
461
+/*
462
+ * The states of mstatus_fs are:
463
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
464
* We will have already diagnosed disabled state,
465
* and need to turn initial/clean into dirty.
466
@@ -XXX,XX +XXX,XX @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
467
#endif
468
469
#ifndef CONFIG_USER_ONLY
470
-/* The states of mstatus_vs are:
471
+/*
472
+ * The states of mstatus_vs are:
473
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
474
* We will have already diagnosed disabled state,
475
* and need to turn initial/clean into dirty.
476
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
477
index XXXXXXX..XXXXXXX 100644
478
--- a/target/riscv/vector_helper.c
479
+++ b/target/riscv/vector_helper.c
480
@@ -XXX,XX +XXX,XX @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
481
}
482
483
/*
484
- *** stride: access vector element from strided memory
485
+ * stride: access vector element from strided memory
486
*/
487
static void
488
vext_ldst_stride(void *vd, void *v0, target_ulong base,
489
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
490
GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
491
492
/*
493
- *** unit-stride: access elements stored contiguously in memory
494
+ * unit-stride: access elements stored contiguously in memory
495
*/
496
497
-/* unmasked unit-stride load and store operation*/
498
+/* unmasked unit-stride load and store operation */
499
static void
500
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
501
vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
502
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
503
GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
504
505
/*
506
- *** unit stride mask load and store, EEW = 1
507
+ * unit stride mask load and store, EEW = 1
508
*/
509
void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
510
CPURISCVState *env, uint32_t desc)
511
@@ -XXX,XX +XXX,XX @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
512
}
513
514
/*
515
- *** index: access vector element from indexed memory
516
+ * index: access vector element from indexed memory
517
*/
518
typedef target_ulong vext_get_index_addr(target_ulong base,
519
uint32_t idx, void *vs2);
520
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
521
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
522
523
/*
524
- *** unit-stride fault-only-fisrt load instructions
525
+ * unit-stride fault-only-fisrt load instructions
526
*/
527
static inline void
528
vext_ldff(void *vd, void *v0, target_ulong base,
529
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
530
uint32_t vma = vext_vma(desc);
531
target_ulong addr, offset, remain;
532
533
- /* probe every access*/
534
+ /* probe every access */
535
for (i = env->vstart; i < env->vl; i++) {
536
if (!vm && !vext_elem_mask(v0, i)) {
537
continue;
538
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
539
#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
540
541
/*
542
- *** load and store whole register instructions
543
+ * load and store whole register instructions
544
*/
545
static void
546
vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
547
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
548
GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
549
550
/*
551
- *** Vector Integer Arithmetic Instructions
552
+ * Vector Integer Arithmetic Instructions
553
*/
554
555
/* expand macro args before macro */
556
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
557
vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
558
} \
559
env->vstart = 0; \
560
- /* mask destination register are always tail-agnostic */ \
561
- /* set tail elements to 1s */ \
562
+ /*
563
+ * mask destination register are always tail-agnostic
564
+ * set tail elements to 1s
565
+ */ \
566
if (vta_all_1s) { \
567
for (; i < total_elems; i++) { \
568
vext_set_elem_mask(vd, i, 1); \
569
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
570
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
571
} \
572
env->vstart = 0; \
573
- /* mask destination register are always tail-agnostic */ \
574
- /* set tail elements to 1s */ \
575
+ /*
576
+ * mask destination register are always tail-agnostic
577
+ * set tail elements to 1s
578
+ */ \
579
if (vta_all_1s) { \
580
for (; i < total_elems; i++) { \
581
vext_set_elem_mask(vd, i, 1); \
582
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
583
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
584
} \
585
env->vstart = 0; \
586
- /* mask destination register are always tail-agnostic */ \
587
- /* set tail elements to 1s */ \
588
+ /*
589
+ * mask destination register are always tail-agnostic
590
+ * set tail elements to 1s
591
+ */ \
592
if (vta_all_1s) { \
593
for (; i < total_elems; i++) { \
594
vext_set_elem_mask(vd, i, 1); \
595
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
596
DO_OP(s2, (ETYPE)(target_long)s1)); \
597
} \
598
env->vstart = 0; \
599
- /* mask destination register are always tail-agnostic */ \
600
- /* set tail elements to 1s */ \
601
+ /*
602
+ * mask destination register are always tail-agnostic
603
+ * set tail elements to 1s
604
+ */ \
605
if (vta_all_1s) { \
606
for (; i < total_elems; i++) { \
607
vext_set_elem_mask(vd, i, 1); \
608
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4)
609
GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8)
610
611
/*
612
- *** Vector Fixed-Point Arithmetic Instructions
613
+ * Vector Fixed-Point Arithmetic Instructions
614
*/
615
616
/* Vector Single-Width Saturating Add and Subtract */
617
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VX_RM(vnclipu_wx_h, 2)
618
GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
619
620
/*
621
- *** Vector Float Point Arithmetic Instructions
622
+ * Vector Float Point Arithmetic Instructions
623
*/
624
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
625
#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
626
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
627
DO_OP(s2, s1, &env->fp_status)); \
628
} \
629
env->vstart = 0; \
630
- /* mask destination register are always tail-agnostic */ \
631
- /* set tail elements to 1s */ \
632
+ /*
633
+ * mask destination register are always tail-agnostic
634
+ * set tail elements to 1s
635
+ */ \
636
if (vta_all_1s) { \
637
for (; i < total_elems; i++) { \
638
vext_set_elem_mask(vd, i, 1); \
639
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
640
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
641
} \
642
env->vstart = 0; \
643
- /* mask destination register are always tail-agnostic */ \
644
- /* set tail elements to 1s */ \
645
+ /*
646
+ * mask destination register are always tail-agnostic
647
+ * set tail elements to 1s
648
+ */ \
649
if (vta_all_1s) { \
650
for (; i < total_elems; i++) { \
651
vext_set_elem_mask(vd, i, 1); \
652
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8)
653
#define WOP_UU_B uint16_t, uint8_t, uint8_t
654
#define WOP_UU_H uint32_t, uint16_t, uint16_t
655
#define WOP_UU_W uint64_t, uint32_t, uint32_t
656
-/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
657
+/*
658
+ * vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.
659
+ */
660
RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
661
RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
662
GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
663
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
664
GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
665
666
/*
667
- *** Vector Reduction Operations
668
+ * Vector Reduction Operations
669
*/
670
/* Vector Single-Width Integer Reduction Instructions */
671
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
672
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
673
GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
674
675
/*
676
- *** Vector Mask Operations
677
+ * Vector Mask Operations
678
*/
679
/* Vector Mask-Register Logical Instructions */
680
#define GEN_VEXT_MASK_VV(NAME, OP) \
681
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
682
vext_set_elem_mask(vd, i, OP(b, a)); \
683
} \
684
env->vstart = 0; \
685
- /* mask destination register are always tail- \
686
- * agnostic \
687
+ /*
688
+ * mask destination register are always tail-agnostic
689
+ * set tail elements to 1s
690
*/ \
691
- /* set tail elements to 1s */ \
692
if (vta_all_1s) { \
693
for (; i < total_elems; i++) { \
694
vext_set_elem_mask(vd, i, 1); \
695
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env,
696
return cnt;
697
}
698
699
-/* vfirst find-first-set mask bit*/
700
+/* vfirst find-first-set mask bit */
701
target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
702
uint32_t desc)
703
{
704
@@ -XXX,XX +XXX,XX @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
705
}
706
}
707
env->vstart = 0;
708
- /* mask destination register are always tail-agnostic */
709
- /* set tail elements to 1s */
710
+ /*
711
+ * mask destination register are always tail-agnostic
712
+ * set tail elements to 1s
713
+ */
714
if (vta_all_1s) {
715
for (; i < total_elems; i++) {
716
vext_set_elem_mask(vd, i, 1);
717
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VID_V(vid_v_w, uint32_t, H4)
718
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8)
719
720
/*
721
- *** Vector Permutation Instructions
722
+ * Vector Permutation Instructions
723
*/
724
725
/* Vector Slide Instructions */
726
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
727
index XXXXXXX..XXXXXXX 100644
728
--- a/target/riscv/insn_trans/trans_rvv.c.inc
729
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
730
@@ -XXX,XX +XXX,XX @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
731
return false;
732
}
733
734
-/* vmsbf.m set-before-first mask bit */
735
-/* vmsif.m set-includ-first mask bit */
736
-/* vmsof.m set-only-first mask bit */
737
+/*
738
+ * vmsbf.m set-before-first mask bit
739
+ * vmsif.m set-including-first mask bit
740
+ * vmsof.m set-only-first mask bit
741
+ */
742
#define GEN_M_TRANS(NAME) \
743
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
744
{ \
61
--
745
--
62
2.30.1
746
2.40.0
63
64
diff view generated by jsdifflib
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
[PULL 31/89] target/riscv: Fix lines with over 80 characters
1
From: Jim Shu <cwshu@andestech.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
If PMP permission of any address has been changed by updating PMP entry,
3
Fix lines with over 80 characters for both code and comments.
4
flush all TLB pages to prevent from getting old permission.
5
4
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
7
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
12
---
11
target/riscv/pmp.c | 4 ++++
13
target/riscv/cpu.h | 4 +-
12
1 file changed, 4 insertions(+)
14
target/riscv/cpu.c | 3 +-
15
target/riscv/cpu_helper.c | 3 +-
16
target/riscv/csr.c | 38 ++++++++++--------
17
target/riscv/debug.c | 11 +++---
18
target/riscv/gdbstub.c | 3 +-
19
target/riscv/pmp.c | 6 ++-
20
target/riscv/pmu.c | 3 +-
21
target/riscv/vector_helper.c | 76 ++++++++++++++++++++++++------------
22
9 files changed, 91 insertions(+), 56 deletions(-)
13
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
29
bool riscv_cpu_two_stage_lookup(int mmu_idx);
30
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
31
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
32
- MMUAccessType access_type, int mmu_idx,
33
- uintptr_t retaddr);
34
+ MMUAccessType access_type,
35
+ int mmu_idx, uintptr_t retaddr);
36
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
37
MMUAccessType access_type, int mmu_idx,
38
bool probe, uintptr_t retaddr);
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
44
device_class_set_props(dc, riscv_cpu_properties);
45
}
46
47
-static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
48
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
49
+ int max_str_len)
50
{
51
char *old = *isa_str;
52
char *new = *isa_str;
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
57
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
58
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
59
} else {
60
cs->exception_index = page_fault_exceptions ?
61
- RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
62
+ RISCV_EXCP_STORE_PAGE_FAULT :
63
+ RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
64
}
65
break;
66
default:
67
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/riscv/csr.c
70
+++ b/target/riscv/csr.c
71
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
72
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
73
SIP_LCOFIP;
74
static const target_ulong hip_writable_mask = MIP_VSSIP;
75
-static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
76
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
77
+ MIP_VSEIP;
78
static const target_ulong vsip_writable_mask = MIP_VSSIP;
79
80
const bool valid_vm_1_10_32[16] = {
81
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
82
static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
83
Int128 *val)
84
{
85
- *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
86
+ *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128,
87
+ env->mstatus));
88
return RISCV_EXCP_NONE;
89
}
90
91
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
92
{
93
env->hstatus = val;
94
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
95
- qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
96
+ qemu_log_mask(LOG_UNIMP,
97
+ "QEMU does not support mixed HSXLEN options.");
98
}
99
if (get_field(val, HSTATUS_VSBE) != 0) {
100
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
101
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
102
target_ulong wpri_val = val & MMTE_MASK;
103
104
if (val != wpri_val) {
105
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
106
- "MMTE: WPRI violation written 0x", val,
107
- "vs expected 0x", wpri_val);
108
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
109
+ TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
110
+ val, "vs expected 0x", wpri_val);
111
}
112
/* for machine mode pm.current is hardwired to 1 */
113
wpri_val |= MMTE_M_PM_CURRENT;
114
@@ -XXX,XX +XXX,XX @@ static RISCVException write_smte(CPURISCVState *env, int csrno,
115
target_ulong wpri_val = val & SMTE_MASK;
116
117
if (val != wpri_val) {
118
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
119
- "SMTE: WPRI violation written 0x", val,
120
- "vs expected 0x", wpri_val);
121
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
122
+ TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
123
+ val, "vs expected 0x", wpri_val);
124
}
125
126
/* if pm.current==0 we can't modify current PM CSRs */
127
@@ -XXX,XX +XXX,XX @@ static RISCVException write_umte(CPURISCVState *env, int csrno,
128
target_ulong wpri_val = val & UMTE_MASK;
129
130
if (val != wpri_val) {
131
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
132
- "UMTE: WPRI violation written 0x", val,
133
- "vs expected 0x", wpri_val);
134
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
135
+ TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
136
+ val, "vs expected 0x", wpri_val);
137
}
138
139
if (check_pm_current_disabled(env, csrno)) {
140
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
141
* Fall back to 64-bit version for now, if the 128-bit alternative isn't
142
* at all defined.
143
* Note, some CSRs don't need to extend to MXLEN (64 upper bits non
144
- * significant), for those, this fallback is correctly handling the accesses
145
+ * significant), for those, this fallback is correctly handling the
146
+ * accesses
147
*/
148
target_ulong old_value;
149
ret = riscv_csrrw_do64(env, csrno, &old_value,
150
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
151
152
/* Supervisor Trap Setup */
153
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
154
- NULL, read_sstatus_i128 },
155
- [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
156
- [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
157
+ NULL, read_sstatus_i128 },
158
+ [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
159
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
160
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
161
- write_scounteren },
162
+ write_scounteren },
163
164
/* Supervisor Trap Handling */
165
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
166
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/target/riscv/debug.c
169
+++ b/target/riscv/debug.c
170
@@ -XXX,XX +XXX,XX @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
171
/* validate size encoding */
172
size = type2_breakpoint_size(env, ctrl);
173
if (access_size[size] == -1) {
174
- qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
175
- size);
176
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
177
+ "SIZE_ANY\n", size);
178
} else {
179
val |= (ctrl & TYPE2_SIZELO);
180
if (riscv_cpu_mxl(env) == MXL_RV64) {
181
@@ -XXX,XX +XXX,XX @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
182
/* validate size encoding */
183
size = extract32(ctrl, 16, 4);
184
if (access_size[size] == -1) {
185
- qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
186
- size);
187
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
188
+ "SIZE_ANY\n", size);
189
} else {
190
val |= (ctrl & TYPE6_SIZE);
191
}
192
@@ -XXX,XX +XXX,XX @@ target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
193
int trigger_type;
194
switch (tdata_index) {
195
case TDATA1:
196
- trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
197
+ trigger_type = extract_trigger_type(env,
198
+ env->tdata1[env->trigger_cur]);
199
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
200
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
201
itrigger_get_adjust_count(env));
202
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
203
index XXXXXXX..XXXXXXX 100644
204
--- a/target/riscv/gdbstub.c
205
+++ b/target/riscv/gdbstub.c
206
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
207
}
208
if (env->misa_ext & RVV) {
209
int base_reg = cs->gdb_num_regs;
210
- gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
211
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector,
212
+ riscv_gdb_set_vector,
213
ricsv_gen_dynamic_vector_xml(cs, base_reg),
214
"riscv-vector.xml", 0);
215
}
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
216
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
15
index XXXXXXX..XXXXXXX 100644
217
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/pmp.c
218
--- a/target/riscv/pmp.c
17
+++ b/target/riscv/pmp.c
219
+++ b/target/riscv/pmp.c
18
@@ -XXX,XX +XXX,XX @@
220
@@ -XXX,XX +XXX,XX @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
19
#include "qapi/error.h"
221
}
20
#include "cpu.h"
222
}
21
#include "trace.h"
223
22
+#include "exec/exec-all.h"
224
-static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
23
225
+static void pmp_decode_napot(target_ulong a, target_ulong *sa,
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
226
+ target_ulong *ea)
25
uint8_t val);
227
{
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
228
/*
27
cfg_val = (val >> 8 * i) & 0xff;
229
* aaaa...aaa0 8-byte NAPOT range
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
230
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
29
}
231
pmp_update_rule_nums(env);
30
+
232
}
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
233
32
+ tlb_flush(env_cpu(env));
234
-static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
33
}
235
+static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
34
236
+ target_ulong addr)
35
237
{
238
int result = 0;
239
240
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
241
index XXXXXXX..XXXXXXX 100644
242
--- a/target/riscv/pmu.c
243
+++ b/target/riscv/pmu.c
244
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
245
} else {
246
return -1;
247
}
248
- overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
249
+ overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
250
+ overflow_ns;
251
252
if (overflow_at > INT64_MAX) {
253
overflow_left += overflow_at - INT64_MAX;
254
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/target/riscv/vector_helper.c
257
+++ b/target/riscv/vector_helper.c
258
@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
259
}
260
261
/*
262
- * masked unit-stride load and store operation will be a special case of stride,
263
- * stride = NF * sizeof (MTYPE)
264
+ * masked unit-stride load and store operation will be a special case of
265
+ * stride, stride = NF * sizeof (MTYPE)
266
*/
267
268
#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
269
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
270
/* load/store rest of elements of current segment pointed by vstart */
271
for (pos = off; pos < max_elems; pos++, env->vstart++) {
272
target_ulong addr = base + ((pos + k * max_elems) << log2_esz);
273
- ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
274
+ ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd,
275
+ ra);
276
}
277
k++;
278
}
279
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf)
280
GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f)
281
GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
282
283
-/* generate the helpers for shift instructions with one vector and one scalar */
284
+/*
285
+ * generate the helpers for shift instructions with one vector and one scalar
286
+ */
287
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
288
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
289
void *vs2, CPURISCVState *env, \
290
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
291
do_##NAME, ESZ); \
292
}
293
294
-static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
295
+static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a,
296
+ uint8_t b)
297
{
298
uint8_t res = a + b;
299
if (res < a) {
300
@@ -XXX,XX +XXX,XX @@ static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
301
return res;
302
}
303
304
-static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
305
+static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a,
306
+ int16_t b)
307
{
308
int16_t res = a + b;
309
if ((res ^ a) & (res ^ b) & INT16_MIN) {
310
@@ -XXX,XX +XXX,XX @@ static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
311
return res;
312
}
313
314
-static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
315
+static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a,
316
+ int32_t b)
317
{
318
int32_t res = a + b;
319
if ((res ^ a) & (res ^ b) & INT32_MIN) {
320
@@ -XXX,XX +XXX,XX @@ static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
321
return res;
322
}
323
324
-static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
325
+static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a,
326
+ int64_t b)
327
{
328
int64_t res = a + b;
329
if ((res ^ a) & (res ^ b) & INT64_MIN) {
330
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2)
331
GEN_VEXT_VX_RM(vsadd_vx_w, 4)
332
GEN_VEXT_VX_RM(vsadd_vx_d, 8)
333
334
-static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
335
+static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a,
336
+ uint8_t b)
337
{
338
uint8_t res = a - b;
339
if (res > a) {
340
@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
341
return res;
342
}
343
344
-static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
345
+static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a,
346
+ int16_t b)
347
{
348
int16_t res = a - b;
349
if ((res ^ a) & (a ^ b) & INT16_MIN) {
350
@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
351
return res;
352
}
353
354
-static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
355
+static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a,
356
+ int32_t b)
357
{
358
int32_t res = a - b;
359
if ((res ^ a) & (a ^ b) & INT32_MIN) {
360
@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
361
return res;
362
}
363
364
-static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
365
+static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a,
366
+ int64_t b)
367
{
368
int64_t res = a - b;
369
if ((res ^ a) & (a ^ b) & INT64_MIN) {
370
@@ -XXX,XX +XXX,XX @@ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
371
return 0; /* round-down (truncate) */
372
}
373
374
-static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
375
+static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a,
376
+ int32_t b)
377
{
378
int64_t res = (int64_t)a + b;
379
uint8_t round = get_round(vxrm, res, 1);
380
@@ -XXX,XX +XXX,XX @@ static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
381
return (res >> 1) + round;
382
}
383
384
-static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
385
+static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a,
386
+ int64_t b)
387
{
388
int64_t res = a + b;
389
uint8_t round = get_round(vxrm, res, 1);
390
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2)
391
GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
392
GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
393
394
-static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
395
+static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a,
396
+ int32_t b)
397
{
398
int64_t res = (int64_t)a - b;
399
uint8_t round = get_round(vxrm, res, 1);
400
@@ -XXX,XX +XXX,XX @@ static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
401
return (res >> 1) + round;
402
}
403
404
-static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
405
+static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a,
406
+ int64_t b)
407
{
408
int64_t res = (int64_t)a - b;
409
uint8_t round = get_round(vxrm, res, 1);
410
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
411
GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4)
412
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
413
414
-/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
415
+/*
416
+ * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.
417
+ */
418
RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
419
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
420
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
421
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4)
422
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
423
424
/*
425
- * vfwcvt.f.f.v vd, vs2, vm
426
- * Convert single-width float to double-width float.
427
+ * vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.
428
*/
429
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
430
{
431
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1)
432
GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
433
GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
434
435
-/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
436
+/*
437
+ * vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float.
438
+ */
439
RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
440
RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
441
GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2)
442
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
443
GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
444
445
/* Maximum value */
446
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number)
447
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_number)
448
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_number)
449
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2,
450
+ float16_maximum_number)
451
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4,
452
+ float32_maximum_number)
453
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8,
454
+ float64_maximum_number)
455
456
/* Minimum value */
457
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number)
458
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number)
459
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number)
460
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2,
461
+ float16_minimum_number)
462
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4,
463
+ float32_minimum_number)
464
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
465
+ float64_minimum_number)
466
467
/* Vector Widening Floating-Point Add Instructions */
468
static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
36
--
469
--
37
2.30.1
470
2.40.0
38
39
diff view generated by jsdifflib
[PULL 10/16] hw/riscv: allow ramfb on virt
[PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
Allow ramfb on virt. This lets `-device ramfb' work.
3
Add signature and signature-granularity properties in spike to specify the target
4
signatrue file and the line size for signature data.
4
5
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
6
Recgonize the signature section between begin_signature and end_signature symbols
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
when loading elf of ACT tests. Then dump signature data in signature section just
8
before the ACT tests exit.
9
10
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
14
Message-Id: <20230405095720.75848-2-liweiwei@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
hw/riscv/virt.c | 3 +++
17
include/hw/char/riscv_htif.h | 3 +++
12
1 file changed, 3 insertions(+)
18
hw/char/riscv_htif.c | 44 +++++++++++++++++++++++++++++++++++-
19
hw/riscv/spike.c | 13 +++++++++++
20
3 files changed, 59 insertions(+), 1 deletion(-)
13
21
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
22
diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
24
--- a/include/hw/char/riscv_htif.h
17
+++ b/hw/riscv/virt.c
25
+++ b/include/hw/char/riscv_htif.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
27
uint64_t pending_read;
28
} HTIFState;
29
30
+extern const char *sig_file;
31
+extern uint8_t line_size;
32
+
33
/* HTIF symbol callback */
34
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
35
uint64_t st_size);
36
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/riscv_htif.c
39
+++ b/hw/char/riscv_htif.c
18
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@
19
#include "sysemu/sysemu.h"
41
#include "chardev/char-fe.h"
20
#include "hw/pci/pci.h"
42
#include "qemu/timer.h"
21
#include "hw/pci-host/gpex.h"
43
#include "qemu/error-report.h"
22
+#include "hw/display/ramfb.h"
44
+#include "exec/address-spaces.h"
23
45
+#include "sysemu/dma.h"
24
static const MemMapEntry virt_memmap[] = {
46
25
[VIRT_DEBUG] = { 0x0, 0x100 },
47
#define RISCV_DEBUG_HTIF 0
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
48
#define HTIF_DEBUG(fmt, ...) \
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
49
@@ -XXX,XX +XXX,XX @@
50
/* PK system call number */
51
#define PK_SYS_WRITE 64
52
53
-static uint64_t fromhost_addr, tohost_addr;
54
+const char *sig_file;
55
+uint8_t line_size = 16;
56
+
57
+static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
58
59
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
60
uint64_t st_size)
61
@@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
62
error_report("HTIF tohost must be 8 bytes");
63
exit(1);
64
}
65
+ } else if (strcmp("begin_signature", st_name) == 0) {
66
+ begin_sig_addr = st_value;
67
+ } else if (strcmp("end_signature", st_name) == 0) {
68
+ end_sig_addr = st_value;
69
}
70
}
71
72
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
73
if (payload & 0x1) {
74
/* exit code */
75
int exit_code = payload >> 1;
76
+
77
+ /*
78
+ * Dump signature data if sig_file is specified and
79
+ * begin/end_signature symbols exist.
80
+ */
81
+ if (sig_file && begin_sig_addr && end_sig_addr) {
82
+ uint64_t sig_len = end_sig_addr - begin_sig_addr;
83
+ char *sig_data = g_malloc(sig_len);
84
+ dma_memory_read(&address_space_memory, begin_sig_addr,
85
+ sig_data, sig_len, MEMTXATTRS_UNSPECIFIED);
86
+ FILE *signature = fopen(sig_file, "w");
87
+ if (signature == NULL) {
88
+ error_report("Unable to open %s with error %s",
89
+ sig_file, strerror(errno));
90
+ exit(1);
91
+ }
92
+
93
+ for (int i = 0; i < sig_len; i += line_size) {
94
+ for (int j = line_size; j > 0; j--) {
95
+ if (i + j <= sig_len) {
96
+ fprintf(signature, "%02x",
97
+ sig_data[i + j - 1] & 0xff);
98
+ } else {
99
+ fprintf(signature, "%02x", 0);
100
+ }
101
+ }
102
+ fprintf(signature, "\n");
103
+ }
104
+
105
+ fclose(signature);
106
+ g_free(sig_data);
107
+ }
108
+
109
exit(exit_code);
110
} else {
111
uint64_t syscall[8];
112
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/hw/riscv/spike.c
115
+++ b/hw/riscv/spike.c
116
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
117
htif_custom_base);
118
}
119
120
+static void spike_set_signature(Object *obj, const char *val, Error **errp)
121
+{
122
+ sig_file = g_strdup(val);
123
+}
124
+
125
static void spike_machine_instance_init(Object *obj)
126
{
127
}
128
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
129
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
29
mc->numa_mem_supported = true;
130
mc->numa_mem_supported = true;
30
+
131
mc->default_ram_id = "riscv.spike.ram";
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
132
+ object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
133
+ object_class_property_set_description(oc, "signature",
134
+ "File to write ACT test signature");
135
+ object_class_property_add_uint8_ptr(oc, "signature-granularity",
136
+ &line_size, OBJ_PROP_FLAG_WRITE);
137
+ object_class_property_set_description(oc, "signature-granularity",
138
+ "Size of each line in ACT signature "
139
+ "file");
32
}
140
}
33
141
34
static const TypeInfo virt_machine_typeinfo = {
142
static const TypeInfo spike_machine_typeinfo = {
35
--
143
--
36
2.30.1
144
2.40.0
37
38
diff view generated by jsdifflib
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
[PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Provides fw_cfg for the virt machine on riscv. This enables
3
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
4
using e.g. ramfb later.
4
properties updated. The same can't be said about env->misa_ext*, since
5
the user might enable/disable MISA extensions in the command line, and
6
env->misa_ext* won't caught these changes. The current solution is to
7
sync everything at the end of validate_set_extensions(), checking every
8
cpu->cfg.ext_N value to do a set_misa() in the end.
5
9
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
10
The last change we're making in the MISA cfg flags are in the G
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise
12
we're not making any changes in MISA bits ever since realize() starts.
13
14
There's no reason to postpone misa_ext updates until the end of the
15
validation. Let's do it earlier, during realize(), in a new helper
16
called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it
17
again by updating env->misa_ext* directly.
18
19
This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to
20
use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA
21
extensions, which is our end goal here.
22
23
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
24
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
26
Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
28
---
12
include/hw/riscv/virt.h | 2 ++
29
target/riscv/cpu.c | 94 +++++++++++++++++++++++++++-------------------
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
30
1 file changed, 56 insertions(+), 38 deletions(-)
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 33 insertions(+)
16
31
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
32
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
34
--- a/target/riscv/cpu.c
20
+++ b/include/hw/riscv/virt.h
35
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
36
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
37
23
DeviceState *plic[VIRT_SOCKETS_MAX];
38
/*
24
PFlashCFI01 *flash[2];
39
* Check consistency between chosen extensions while setting
25
+ FWCfgState *fw_cfg;
40
- * cpu->cfg accordingly, doing a set_misa() in the end.
26
41
+ * cpu->cfg accordingly.
27
int fdt_size;
42
*/
28
};
43
static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
29
@@ -XXX,XX +XXX,XX @@ enum {
44
{
30
VIRT_PLIC,
45
CPURISCVState *env = &cpu->env;
31
VIRT_UART0,
46
- uint32_t ext = 0;
32
VIRT_VIRTIO,
47
33
+ VIRT_FW_CFG,
48
/* Do some ISA extension error checking */
34
VIRT_FLASH,
49
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
35
VIRT_DRAM,
50
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
VIRT_PCIE_MMIO,
51
cpu->cfg.ext_d = true;
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
52
cpu->cfg.ext_icsr = true;
38
index XXXXXXX..XXXXXXX 100644
53
cpu->cfg.ext_ifencei = true;
39
--- a/hw/riscv/virt.c
54
+
40
+++ b/hw/riscv/virt.c
55
+ env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
56
+ env->misa_ext_mask = env->misa_ext;
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
57
}
43
[VIRT_UART0] = { 0x10000000, 0x100 },
58
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
59
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
60
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
61
cpu->cfg.ext_zksh = true;
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
62
}
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
63
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
64
- if (cpu->cfg.ext_i) {
50
return dev;
65
- ext |= RVI;
66
- }
67
- if (cpu->cfg.ext_e) {
68
- ext |= RVE;
69
- }
70
- if (cpu->cfg.ext_m) {
71
- ext |= RVM;
72
- }
73
- if (cpu->cfg.ext_a) {
74
- ext |= RVA;
75
- }
76
- if (cpu->cfg.ext_f) {
77
- ext |= RVF;
78
- }
79
- if (cpu->cfg.ext_d) {
80
- ext |= RVD;
81
- }
82
- if (cpu->cfg.ext_c) {
83
- ext |= RVC;
84
- }
85
- if (cpu->cfg.ext_s) {
86
- ext |= RVS;
87
- }
88
- if (cpu->cfg.ext_u) {
89
- ext |= RVU;
90
- }
91
- if (cpu->cfg.ext_h) {
92
- ext |= RVH;
93
- }
94
if (cpu->cfg.ext_v) {
95
int vext_version = VEXT_VERSION_1_00_0;
96
- ext |= RVV;
97
if (!is_power_of_2(cpu->cfg.vlen)) {
98
error_setg(errp,
99
"Vector extension VLEN must be power of 2");
100
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
101
}
102
set_vext_version(env, vext_version);
103
}
104
- if (cpu->cfg.ext_j) {
105
- ext |= RVJ;
106
- }
107
-
108
- set_misa(env, env->misa_mxl, ext);
51
}
109
}
52
110
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
111
#ifndef CONFIG_USER_ONLY
112
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
113
#endif
114
}
115
116
+static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
54
+{
117
+{
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
118
+ uint32_t ext = 0;
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
57
+ FWCfgState *fw_cfg;
58
+ char *nodename;
59
+
119
+
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
120
+ if (riscv_cpu_cfg(env)->ext_i) {
61
+ &address_space_memory);
121
+ ext |= RVI;
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
122
+ }
123
+ if (riscv_cpu_cfg(env)->ext_e) {
124
+ ext |= RVE;
125
+ }
126
+ if (riscv_cpu_cfg(env)->ext_m) {
127
+ ext |= RVM;
128
+ }
129
+ if (riscv_cpu_cfg(env)->ext_a) {
130
+ ext |= RVA;
131
+ }
132
+ if (riscv_cpu_cfg(env)->ext_f) {
133
+ ext |= RVF;
134
+ }
135
+ if (riscv_cpu_cfg(env)->ext_d) {
136
+ ext |= RVD;
137
+ }
138
+ if (riscv_cpu_cfg(env)->ext_c) {
139
+ ext |= RVC;
140
+ }
141
+ if (riscv_cpu_cfg(env)->ext_s) {
142
+ ext |= RVS;
143
+ }
144
+ if (riscv_cpu_cfg(env)->ext_u) {
145
+ ext |= RVU;
146
+ }
147
+ if (riscv_cpu_cfg(env)->ext_h) {
148
+ ext |= RVH;
149
+ }
150
+ if (riscv_cpu_cfg(env)->ext_v) {
151
+ ext |= RVV;
152
+ }
153
+ if (riscv_cpu_cfg(env)->ext_j) {
154
+ ext |= RVJ;
155
+ }
63
+
156
+
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
157
+ env->misa_ext = env->misa_ext_mask = ext;
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
67
+ "compatible", "qemu,fw-cfg-mmio");
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
73
+}
158
+}
74
+
159
+
75
static void virt_machine_init(MachineState *machine)
160
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
76
{
161
{
77
const MemMapEntry *memmap = virt_memmap;
162
CPUState *cs = CPU(dev);
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
163
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
79
start_addr = virt_memmap[VIRT_FLASH].base;
164
set_priv_version(env, priv_version);
80
}
165
}
81
166
82
+ /*
167
+ /*
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
168
+ * We can't be sure of whether we set defaults during cpu_init()
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
169
+ * or whether the user enabled/disabled some bits via cpu->cfg
170
+ * flags. Sync env->misa_ext with cpu->cfg now to allow us to
171
+ * use just env->misa_ext later.
85
+ */
172
+ */
86
+ s->fw_cfg = create_fw_cfg(machine);
173
+ riscv_cpu_sync_misa_cfg(env);
87
+ rom_set_fw(s->fw_cfg);
88
+
174
+
89
/* Compute the fdt load address in dram */
175
/* Force disable extensions if priv spec version does not match */
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
176
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
91
machine->ram_size, machine->fdt);
177
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/riscv/Kconfig
95
+++ b/hw/riscv/Kconfig
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
97
select SIFIVE_PLIC
98
select SIFIVE_TEST
99
select VIRTIO_MMIO
100
+ select FW_CFG_DMA
101
102
config SIFIVE_E
103
bool
104
--
178
--
105
2.30.1
179
2.40.0
106
107
diff view generated by jsdifflib
New patch
[PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[]
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The code that disables extensions if there's a priv version mismatch
4
uses cpu->cfg.ext_N properties to do its job.
5
6
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
7
the MISA related verifications in a new function, removing it from
8
isa_edata_arr[].
9
10
We're also erroring it out instead of disabling, making the cpu_init()
11
function responsible for running an adequate priv spec for the MISA
12
extensions it wants to use.
13
14
Note that the RVV verification is being ignored since we're always have
15
at least PRIV_VERSION_1_10_0.
16
17
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
18
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
19
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
20
Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
23
target/riscv/cpu.c | 19 +++++++++++++++++--
24
1 file changed, 17 insertions(+), 2 deletions(-)
25
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.c
29
+++ b/target/riscv/cpu.c
30
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
31
* 4. Non-standard extensions (starts with 'X') must be listed after all
32
* standard extensions. They must be separated from other multi-letter
33
* extensions by an underscore.
34
+ *
35
+ * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
36
+ * instead.
37
*/
38
static const struct isa_ext_data isa_edata_arr[] = {
39
- ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
40
- ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
41
ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
42
ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
43
ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
44
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
45
env->misa_ext = env->misa_ext_mask = ext;
46
}
47
48
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
49
+{
50
+ if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
51
+ error_setg(errp, "H extension requires priv spec 1.12.0");
52
+ return;
53
+ }
54
+}
55
+
56
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
57
{
58
CPUState *cs = CPU(dev);
59
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
60
*/
61
riscv_cpu_sync_misa_cfg(env);
62
63
+ riscv_cpu_validate_misa_priv(env, &local_err);
64
+ if (local_err != NULL) {
65
+ error_propagate(errp, local_err);
66
+ return;
67
+ }
68
+
69
/* Force disable extensions if priv spec version does not match */
70
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
71
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
72
--
73
2.40.0
diff view generated by jsdifflib
New patch
[PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
4
redundant 'multi_letter' field from isa_ext_data.
5
6
Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu.c | 132 ++++++++++++++++++++++-----------------------
14
1 file changed, 65 insertions(+), 67 deletions(-)
15
16
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.c
19
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
21
22
struct isa_ext_data {
23
const char *name;
24
- bool multi_letter;
25
int min_version;
26
int ext_enable_offset;
27
};
28
29
-#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
30
- {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
31
+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
32
+ {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
33
34
/*
35
* Here are the ordering rules of extension naming defined by RISC-V
36
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
37
* instead.
38
*/
39
static const struct isa_ext_data isa_edata_arr[] = {
40
- ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
41
- ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
42
- ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
43
- ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
44
- ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
45
- ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
46
- ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
47
- ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
48
- ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
49
- ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
50
- ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
51
- ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
52
- ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
53
- ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
54
- ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
55
- ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce),
56
- ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
57
- ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
58
- ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
59
- ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
60
- ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
61
- ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
62
- ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
63
- ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
64
- ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
65
- ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
66
- ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
67
- ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
68
- ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
69
- ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
70
- ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
71
- ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
72
- ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
73
- ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
74
- ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
75
- ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f),
76
- ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f),
77
- ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d),
78
- ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
79
- ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
80
- ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
81
- ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
82
- ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
83
- ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
84
- ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
85
- ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
86
- ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
87
- ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
88
- ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
89
- ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
90
- ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
91
- ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
92
- ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
93
- ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
94
- ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
95
- ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
96
- ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
97
- ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
98
- ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
99
- ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
100
- ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
101
- ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
102
+ ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
103
+ ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
104
+ ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
105
+ ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
106
+ ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
107
+ ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
108
+ ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
109
+ ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
110
+ ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
111
+ ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
112
+ ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
113
+ ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
114
+ ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
115
+ ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
116
+ ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
117
+ ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
118
+ ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
119
+ ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
120
+ ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
121
+ ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
122
+ ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
123
+ ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
124
+ ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
125
+ ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
126
+ ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
127
+ ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
128
+ ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
129
+ ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
130
+ ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
131
+ ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
132
+ ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
133
+ ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
134
+ ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
135
+ ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
136
+ ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
137
+ ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
138
+ ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
139
+ ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
140
+ ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
141
+ ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
142
+ ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
143
+ ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
144
+ ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
145
+ ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
146
+ ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
147
+ ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
148
+ ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
149
+ ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
150
+ ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
151
+ ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
152
+ ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
153
+ ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
154
+ ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
155
+ ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
156
+ ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
157
+ ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
158
+ ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
159
+ ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
160
+ ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
161
+ ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
162
+ ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
163
+ ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
164
};
165
166
static bool isa_ext_is_enabled(RISCVCPU *cpu,
167
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
168
int i;
169
170
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
171
- if (isa_edata_arr[i].multi_letter &&
172
- isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
173
+ if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
174
new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
175
g_free(old);
176
old = new;
177
--
178
2.40.0
diff view generated by jsdifflib
New patch
[PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
4
in the command line. User settings are reflected in the cpu->cfg object
5
for later use. These properties are used in the target/riscv/cpu.c code,
6
most notably in riscv_cpu_validate_set_extensions(), where most of our
7
realize time validations are made.
8
9
And then there's env->misa_ext, the field where the MISA extensions are
10
set, that is read everywhere else. We need to keep env->misa_ext updated
11
with cpu->cfg settings, since our validations rely on it, forcing us to
12
make register_cpu_props() write cpu->cfg.ext_N flags to cover for named
13
CPUs that aren't used named properties but also needs to go through the
14
same validation steps. Failing to so will make those name CPUs fail
15
validation (see c66ffcd5358b for more info). Not only that, but we also
16
need to sync env->misa_ext with cpu->cfg again during realize() time to
17
catch any change the user might have done, since the rest of the code
18
relies on that.
19
20
Making cpu->cfg.ext_N and env->misa_ext reflect each other is not
21
needed. What we want is a way for users to enable/disable MISA extensions,
22
and there's nothing stopping us from letting the user write env->misa_ext
23
directly. Here are the artifacts that will enable us to do that:
24
25
- RISCVCPUMisaExtConfig will declare each MISA property;
26
27
- cpu_set_misa_ext_cfg() is the setter for each property. We'll write
28
env->misa_ext and env->misa_ext_mask with the appropriate misa_bit;
29
cutting off cpu->cfg.ext_N from the logic;
30
31
- cpu_get_misa_ext_cfg() is a getter that will retrieve the current val
32
of the property based on env->misa_ext;
33
34
- riscv_cpu_add_misa_properties() will be called in register_cpu_props()
35
to init all MISA properties from the misa_ext_cfgs[] array.
36
37
With this infrastructure we'll start to get rid of each cpu->cfg.ext_N
38
attribute in the next patches.
39
40
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
41
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
42
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
43
Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com>
44
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
45
---
46
target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++
47
1 file changed, 65 insertions(+)
48
49
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/riscv/cpu.c
52
+++ b/target/riscv/cpu.c
53
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
54
#endif /* CONFIG_USER_ONLY */
55
}
56
57
+typedef struct RISCVCPUMisaExtConfig {
58
+ const char *name;
59
+ const char *description;
60
+ target_ulong misa_bit;
61
+ bool enabled;
62
+} RISCVCPUMisaExtConfig;
63
+
64
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
65
+ void *opaque, Error **errp)
66
+{
67
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
68
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
69
+ RISCVCPU *cpu = RISCV_CPU(obj);
70
+ CPURISCVState *env = &cpu->env;
71
+ bool value;
72
+
73
+ if (!visit_type_bool(v, name, &value, errp)) {
74
+ return;
75
+ }
76
+
77
+ if (value) {
78
+ env->misa_ext |= misa_bit;
79
+ env->misa_ext_mask |= misa_bit;
80
+ } else {
81
+ env->misa_ext &= ~misa_bit;
82
+ env->misa_ext_mask &= ~misa_bit;
83
+ }
84
+}
85
+
86
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
87
+ void *opaque, Error **errp)
88
+{
89
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
90
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
91
+ RISCVCPU *cpu = RISCV_CPU(obj);
92
+ CPURISCVState *env = &cpu->env;
93
+ bool value;
94
+
95
+ value = env->misa_ext & misa_bit;
96
+
97
+ visit_type_bool(v, name, &value, errp);
98
+}
99
+
100
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
101
+
102
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
103
+{
104
+ int i;
105
+
106
+ for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
107
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
108
+
109
+ object_property_add(cpu_obj, misa_cfg->name, "bool",
110
+ cpu_get_misa_ext_cfg,
111
+ cpu_set_misa_ext_cfg,
112
+ NULL, (void *)misa_cfg);
113
+ object_property_set_description(cpu_obj, misa_cfg->name,
114
+ misa_cfg->description);
115
+ object_property_set_bool(cpu_obj, misa_cfg->name,
116
+ misa_cfg->enabled, NULL);
117
+ }
118
+}
119
+
120
static Property riscv_cpu_extensions[] = {
121
/* Defaults for standard extensions */
122
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
123
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
124
return;
125
}
126
127
+ riscv_cpu_add_misa_properties(obj);
128
+
129
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
130
qdev_property_add_static(dev, prop);
131
}
132
--
133
2.40.0
diff view generated by jsdifflib
New patch
[PULL 37/89] target/riscv: remove cpu->cfg.ext_a
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "a" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
5
replaced with riscv_has_ext(env, RVA).
6
7
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 16 ++++++++--------
17
2 files changed, 8 insertions(+), 9 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
bool ext_e;
25
bool ext_g;
26
bool ext_m;
27
- bool ext_a;
28
bool ext_f;
29
bool ext_d;
30
bool ext_c;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
37
/* Do some ISA extension error checking */
38
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
39
- cpu->cfg.ext_a && cpu->cfg.ext_f &&
40
- cpu->cfg.ext_d &&
41
+ riscv_has_ext(env, RVA) &&
42
+ cpu->cfg.ext_f && cpu->cfg.ext_d &&
43
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
44
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
45
cpu->cfg.ext_i = true;
46
cpu->cfg.ext_m = true;
47
- cpu->cfg.ext_a = true;
48
cpu->cfg.ext_f = true;
49
cpu->cfg.ext_d = true;
50
cpu->cfg.ext_icsr = true;
51
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
52
return;
53
}
54
55
- if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
56
+ if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
57
error_setg(errp, "Zawrs extension requires A extension");
58
return;
59
}
60
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
61
if (riscv_cpu_cfg(env)->ext_m) {
62
ext |= RVM;
63
}
64
- if (riscv_cpu_cfg(env)->ext_a) {
65
+ if (riscv_has_ext(env, RVA)) {
66
ext |= RVA;
67
}
68
if (riscv_cpu_cfg(env)->ext_f) {
69
@@ -XXX,XX +XXX,XX @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
70
visit_type_bool(v, name, &value, errp);
71
}
72
73
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
74
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
75
+ {.name = "a", .description = "Atomic instructions",
76
+ .misa_bit = RVA, .enabled = true},
77
+};
78
79
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
80
{
81
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
82
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
83
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
84
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
85
- DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
86
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
87
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
88
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
89
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
90
cpu->cfg.ext_i = misa_ext & RVI;
91
cpu->cfg.ext_e = misa_ext & RVE;
92
cpu->cfg.ext_m = misa_ext & RVM;
93
- cpu->cfg.ext_a = misa_ext & RVA;
94
cpu->cfg.ext_f = misa_ext & RVF;
95
cpu->cfg.ext_d = misa_ext & RVD;
96
cpu->cfg.ext_v = misa_ext & RVV;
97
--
98
2.40.0
diff view generated by jsdifflib
New patch
[PULL 38/89] target/riscv: remove cpu->cfg.ext_c
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "c" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
5
replaced with riscv_has_ext(env, RVC).
6
7
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 9 ++++-----
17
2 files changed, 4 insertions(+), 6 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
bool ext_m;
25
bool ext_f;
26
bool ext_d;
27
- bool ext_c;
28
bool ext_s;
29
bool ext_u;
30
bool ext_h;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
36
set_priv_version(env, PRIV_VERSION_1_11_0);
37
38
cpu->cfg.ext_g = true;
39
- cpu->cfg.ext_c = true;
40
cpu->cfg.ext_u = true;
41
cpu->cfg.ext_s = true;
42
cpu->cfg.ext_icsr = true;
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
44
}
45
}
46
47
- if (cpu->cfg.ext_c) {
48
+ if (riscv_has_ext(env, RVC)) {
49
cpu->cfg.ext_zca = true;
50
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
51
cpu->cfg.ext_zcf = true;
52
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
53
if (riscv_cpu_cfg(env)->ext_d) {
54
ext |= RVD;
55
}
56
- if (riscv_cpu_cfg(env)->ext_c) {
57
+ if (riscv_has_ext(env, RVC)) {
58
ext |= RVC;
59
}
60
if (riscv_cpu_cfg(env)->ext_s) {
61
@@ -XXX,XX +XXX,XX @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
62
static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
63
{.name = "a", .description = "Atomic instructions",
64
.misa_bit = RVA, .enabled = true},
65
+ {.name = "c", .description = "Compressed instructions",
66
+ .misa_bit = RVC, .enabled = true},
67
};
68
69
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
70
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
71
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
72
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
73
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
74
- DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
75
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
76
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
77
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
78
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
79
cpu->cfg.ext_f = misa_ext & RVF;
80
cpu->cfg.ext_d = misa_ext & RVD;
81
cpu->cfg.ext_v = misa_ext & RVV;
82
- cpu->cfg.ext_c = misa_ext & RVC;
83
cpu->cfg.ext_s = misa_ext & RVS;
84
cpu->cfg.ext_u = misa_ext & RVU;
85
cpu->cfg.ext_h = misa_ext & RVH;
86
--
87
2.40.0
diff view generated by jsdifflib
New patch
[PULL 39/89] target/riscv: remove cpu->cfg.ext_d
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "d" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
5
replaced with riscv_has_ext(env, RVD).
6
7
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 17 ++++++++---------
17
2 files changed, 8 insertions(+), 10 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
bool ext_g;
25
bool ext_m;
26
bool ext_f;
27
- bool ext_d;
28
bool ext_s;
29
bool ext_u;
30
bool ext_h;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
/* Do some ISA extension error checking */
37
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
38
riscv_has_ext(env, RVA) &&
39
- cpu->cfg.ext_f && cpu->cfg.ext_d &&
40
+ cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
41
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
42
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
43
cpu->cfg.ext_i = true;
44
cpu->cfg.ext_m = true;
45
cpu->cfg.ext_f = true;
46
- cpu->cfg.ext_d = true;
47
cpu->cfg.ext_icsr = true;
48
cpu->cfg.ext_ifencei = true;
49
50
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
51
return;
52
}
53
54
- if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
55
+ if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
56
error_setg(errp, "D extension requires F extension");
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
60
cpu->cfg.ext_zve32f = true;
61
}
62
63
- if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
64
+ if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
65
error_setg(errp, "Zve64d/V extensions require D extension");
66
return;
67
}
68
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
69
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
70
cpu->cfg.ext_zcf = true;
71
}
72
- if (cpu->cfg.ext_d) {
73
+ if (riscv_has_ext(env, RVD)) {
74
cpu->cfg.ext_zcd = true;
75
}
76
}
77
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
78
return;
79
}
80
81
- if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
82
+ if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
83
error_setg(errp, "Zcd extension requires D extension");
84
return;
85
}
86
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
87
if (riscv_cpu_cfg(env)->ext_f) {
88
ext |= RVF;
89
}
90
- if (riscv_cpu_cfg(env)->ext_d) {
91
+ if (riscv_has_ext(env, RVD)) {
92
ext |= RVD;
93
}
94
if (riscv_has_ext(env, RVC)) {
95
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
96
.misa_bit = RVA, .enabled = true},
97
{.name = "c", .description = "Compressed instructions",
98
.misa_bit = RVC, .enabled = true},
99
+ {.name = "d", .description = "Double-precision float point",
100
+ .misa_bit = RVD, .enabled = true},
101
};
102
103
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
104
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
105
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
106
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
107
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
108
- DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
109
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
110
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
111
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
112
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
113
cpu->cfg.ext_e = misa_ext & RVE;
114
cpu->cfg.ext_m = misa_ext & RVM;
115
cpu->cfg.ext_f = misa_ext & RVF;
116
- cpu->cfg.ext_d = misa_ext & RVD;
117
cpu->cfg.ext_v = misa_ext & RVV;
118
cpu->cfg.ext_s = misa_ext & RVS;
119
cpu->cfg.ext_u = misa_ext & RVU;
120
--
121
2.40.0
diff view generated by jsdifflib
New patch
[PULL 40/89] target/riscv: remove cpu->cfg.ext_f
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "f" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
5
replaced with riscv_has_ext(env, RVF).
6
7
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 26 +++++++++++++-------------
17
2 files changed, 13 insertions(+), 14 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
bool ext_e;
25
bool ext_g;
26
bool ext_m;
27
- bool ext_f;
28
bool ext_s;
29
bool ext_u;
30
bool ext_h;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
/* Do some ISA extension error checking */
37
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
38
riscv_has_ext(env, RVA) &&
39
- cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
40
+ riscv_has_ext(env, RVF) &&
41
+ riscv_has_ext(env, RVD) &&
42
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
43
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
44
cpu->cfg.ext_i = true;
45
cpu->cfg.ext_m = true;
46
- cpu->cfg.ext_f = true;
47
cpu->cfg.ext_icsr = true;
48
cpu->cfg.ext_ifencei = true;
49
50
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
51
return;
52
}
53
54
- if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
55
+ if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
56
error_setg(errp, "F extension requires Zicsr");
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
60
cpu->cfg.ext_zfhmin = true;
61
}
62
63
- if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
64
+ if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
65
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
66
return;
67
}
68
69
- if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
70
+ if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
71
error_setg(errp, "D extension requires F extension");
72
return;
73
}
74
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
75
return;
76
}
77
78
- if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
79
+ if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
80
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
81
return;
82
}
83
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
84
error_setg(errp, "Zfinx extension requires Zicsr");
85
return;
86
}
87
- if (cpu->cfg.ext_f) {
88
+ if (riscv_has_ext(env, RVF)) {
89
error_setg(errp,
90
"Zfinx cannot be supported together with F extension");
91
return;
92
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
93
cpu->cfg.ext_zcb = true;
94
cpu->cfg.ext_zcmp = true;
95
cpu->cfg.ext_zcmt = true;
96
- if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
97
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
98
cpu->cfg.ext_zcf = true;
99
}
100
}
101
102
if (riscv_has_ext(env, RVC)) {
103
cpu->cfg.ext_zca = true;
104
- if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
105
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
106
cpu->cfg.ext_zcf = true;
107
}
108
if (riscv_has_ext(env, RVD)) {
109
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
110
return;
111
}
112
113
- if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
114
+ if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
115
error_setg(errp, "Zcf extension requires F extension");
116
return;
117
}
118
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
119
if (riscv_has_ext(env, RVA)) {
120
ext |= RVA;
121
}
122
- if (riscv_cpu_cfg(env)->ext_f) {
123
+ if (riscv_has_ext(env, RVF)) {
124
ext |= RVF;
125
}
126
if (riscv_has_ext(env, RVD)) {
127
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
128
.misa_bit = RVC, .enabled = true},
129
{.name = "d", .description = "Double-precision float point",
130
.misa_bit = RVD, .enabled = true},
131
+ {.name = "f", .description = "Single-precision float point",
132
+ .misa_bit = RVF, .enabled = true},
133
};
134
135
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
136
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
137
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
138
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
139
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
140
- DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
141
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
142
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
143
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
144
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
145
cpu->cfg.ext_i = misa_ext & RVI;
146
cpu->cfg.ext_e = misa_ext & RVE;
147
cpu->cfg.ext_m = misa_ext & RVM;
148
- cpu->cfg.ext_f = misa_ext & RVF;
149
cpu->cfg.ext_v = misa_ext & RVV;
150
cpu->cfg.ext_s = misa_ext & RVS;
151
cpu->cfg.ext_u = misa_ext & RVU;
152
--
153
2.40.0
diff view generated by jsdifflib
New patch
[PULL 41/89] target/riscv: remove cpu->cfg.ext_i
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "i" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
5
replaced with riscv_has_ext(env, RVI).
6
7
Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 15 +++++++--------
17
2 files changed, 7 insertions(+), 9 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
} RISCVSATPMap;
25
26
struct RISCVCPUConfig {
27
- bool ext_i;
28
bool ext_e;
29
bool ext_g;
30
bool ext_m;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
CPURISCVState *env = &cpu->env;
37
38
/* Do some ISA extension error checking */
39
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
40
+ if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
41
riscv_has_ext(env, RVA) &&
42
riscv_has_ext(env, RVF) &&
43
riscv_has_ext(env, RVD) &&
44
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
45
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
46
- cpu->cfg.ext_i = true;
47
cpu->cfg.ext_m = true;
48
cpu->cfg.ext_icsr = true;
49
cpu->cfg.ext_ifencei = true;
50
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
51
env->misa_ext_mask = env->misa_ext;
52
}
53
54
- if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
55
+ if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
56
error_setg(errp,
57
"I and E extensions are incompatible");
58
return;
59
}
60
61
- if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
62
+ if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
63
error_setg(errp,
64
"Either I or E extension must be set");
65
return;
66
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
67
return;
68
}
69
70
- if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
71
+ if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
72
error_setg(errp,
73
"H depends on an I base integer ISA with 32 x registers");
74
return;
75
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
76
{
77
uint32_t ext = 0;
78
79
- if (riscv_cpu_cfg(env)->ext_i) {
80
+ if (riscv_has_ext(env, RVI)) {
81
ext |= RVI;
82
}
83
if (riscv_cpu_cfg(env)->ext_e) {
84
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
85
.misa_bit = RVD, .enabled = true},
86
{.name = "f", .description = "Single-precision float point",
87
.misa_bit = RVF, .enabled = true},
88
+ {.name = "i", .description = "Base integer instruction set",
89
+ .misa_bit = RVI, .enabled = true},
90
};
91
92
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
93
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
94
95
static Property riscv_cpu_extensions[] = {
96
/* Defaults for standard extensions */
97
- DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
98
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
99
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
100
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
101
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
102
* later on.
103
*/
104
if (cpu->env.misa_ext != 0) {
105
- cpu->cfg.ext_i = misa_ext & RVI;
106
cpu->cfg.ext_e = misa_ext & RVE;
107
cpu->cfg.ext_m = misa_ext & RVM;
108
cpu->cfg.ext_v = misa_ext & RVV;
109
--
110
2.40.0
diff view generated by jsdifflib
New patch
[PULL 42/89] target/riscv: remove cpu->cfg.ext_e
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "e" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
5
replaced with riscv_has_ext(env, RVE).
6
7
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 10 +++++-----
17
target/riscv/insn_trans/trans_rvzce.c.inc | 2 +-
18
3 files changed, 6 insertions(+), 7 deletions(-)
19
20
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/cpu.h
23
+++ b/target/riscv/cpu.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct {
25
} RISCVSATPMap;
26
27
struct RISCVCPUConfig {
28
- bool ext_e;
29
bool ext_g;
30
bool ext_m;
31
bool ext_s;
32
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/cpu.c
35
+++ b/target/riscv/cpu.c
36
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
37
env->misa_ext_mask = env->misa_ext;
38
}
39
40
- if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
41
+ if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
42
error_setg(errp,
43
"I and E extensions are incompatible");
44
return;
45
}
46
47
- if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
48
+ if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
49
error_setg(errp,
50
"Either I or E extension must be set");
51
return;
52
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
53
if (riscv_has_ext(env, RVI)) {
54
ext |= RVI;
55
}
56
- if (riscv_cpu_cfg(env)->ext_e) {
57
+ if (riscv_has_ext(env, RVE)) {
58
ext |= RVE;
59
}
60
if (riscv_cpu_cfg(env)->ext_m) {
61
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
62
.misa_bit = RVF, .enabled = true},
63
{.name = "i", .description = "Base integer instruction set",
64
.misa_bit = RVI, .enabled = true},
65
+ {.name = "e", .description = "Base integer instruction set (embedded)",
66
+ .misa_bit = RVE, .enabled = false},
67
};
68
69
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
70
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
71
72
static Property riscv_cpu_extensions[] = {
73
/* Defaults for standard extensions */
74
- DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
75
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
76
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
77
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
78
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
79
* later on.
80
*/
81
if (cpu->env.misa_ext != 0) {
82
- cpu->cfg.ext_e = misa_ext & RVE;
83
cpu->cfg.ext_m = misa_ext & RVM;
84
cpu->cfg.ext_v = misa_ext & RVV;
85
cpu->cfg.ext_s = misa_ext & RVS;
86
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
89
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
90
@@ -XXX,XX +XXX,XX @@ static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
91
{
92
uint32_t reg_bitmap = 0;
93
94
- if (ctx->cfg_ptr->ext_e && rlist > 6) {
95
+ if (has_ext(ctx, RVE) && rlist > 6) {
96
return 0;
97
}
98
99
--
100
2.40.0
diff view generated by jsdifflib
New patch
[PULL 43/89] target/riscv: remove cpu->cfg.ext_m
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "m" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
5
replaced with riscv_has_ext(env, RVM).
6
7
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 10 +++++-----
17
2 files changed, 5 insertions(+), 6 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_m;
28
bool ext_s;
29
bool ext_u;
30
bool ext_h;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
CPURISCVState *env = &cpu->env;
37
38
/* Do some ISA extension error checking */
39
- if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
40
+ if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
41
+ riscv_has_ext(env, RVM) &&
42
riscv_has_ext(env, RVA) &&
43
riscv_has_ext(env, RVF) &&
44
riscv_has_ext(env, RVD) &&
45
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
46
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
47
- cpu->cfg.ext_m = true;
48
cpu->cfg.ext_icsr = true;
49
cpu->cfg.ext_ifencei = true;
50
51
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
52
if (riscv_has_ext(env, RVE)) {
53
ext |= RVE;
54
}
55
- if (riscv_cpu_cfg(env)->ext_m) {
56
+ if (riscv_has_ext(env, RVM)) {
57
ext |= RVM;
58
}
59
if (riscv_has_ext(env, RVA)) {
60
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
61
.misa_bit = RVI, .enabled = true},
62
{.name = "e", .description = "Base integer instruction set (embedded)",
63
.misa_bit = RVE, .enabled = false},
64
+ {.name = "m", .description = "Integer multiplication and division",
65
+ .misa_bit = RVM, .enabled = true},
66
};
67
68
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
69
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
70
static Property riscv_cpu_extensions[] = {
71
/* Defaults for standard extensions */
72
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
73
- DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
74
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
75
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
76
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
77
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
78
* later on.
79
*/
80
if (cpu->env.misa_ext != 0) {
81
- cpu->cfg.ext_m = misa_ext & RVM;
82
cpu->cfg.ext_v = misa_ext & RVV;
83
cpu->cfg.ext_s = misa_ext & RVS;
84
cpu->cfg.ext_u = misa_ext & RVU;
85
--
86
2.40.0
diff view generated by jsdifflib
New patch
[PULL 44/89] target/riscv: remove cpu->cfg.ext_s
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "s" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
5
replaced with riscv_has_ext(env, RVS).
6
7
Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 11 +++++------
17
2 files changed, 5 insertions(+), 7 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_s;
28
bool ext_u;
29
bool ext_h;
30
bool ext_j;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
36
37
cpu->cfg.ext_g = true;
38
cpu->cfg.ext_u = true;
39
- cpu->cfg.ext_s = true;
40
cpu->cfg.ext_icsr = true;
41
cpu->cfg.ext_zfh = true;
42
cpu->cfg.mmu = true;
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
44
return;
45
}
46
47
- if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
48
+ if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
49
error_setg(errp,
50
"Setting S extension without U extension is illegal");
51
return;
52
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
53
return;
54
}
55
56
- if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
57
+ if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
58
error_setg(errp, "H extension implicitly requires S-mode");
59
return;
60
}
61
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
62
if (riscv_has_ext(env, RVC)) {
63
ext |= RVC;
64
}
65
- if (riscv_cpu_cfg(env)->ext_s) {
66
+ if (riscv_has_ext(env, RVS)) {
67
ext |= RVS;
68
}
69
if (riscv_cpu_cfg(env)->ext_u) {
70
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
71
.misa_bit = RVE, .enabled = false},
72
{.name = "m", .description = "Integer multiplication and division",
73
.misa_bit = RVM, .enabled = true},
74
+ {.name = "s", .description = "Supervisor-level instructions",
75
+ .misa_bit = RVS, .enabled = true},
76
};
77
78
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
79
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
80
static Property riscv_cpu_extensions[] = {
81
/* Defaults for standard extensions */
82
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
83
- DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
84
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
85
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
86
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
87
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
88
*/
89
if (cpu->env.misa_ext != 0) {
90
cpu->cfg.ext_v = misa_ext & RVV;
91
- cpu->cfg.ext_s = misa_ext & RVS;
92
cpu->cfg.ext_u = misa_ext & RVU;
93
cpu->cfg.ext_h = misa_ext & RVH;
94
cpu->cfg.ext_j = misa_ext & RVJ;
95
--
96
2.40.0
diff view generated by jsdifflib
New patch
[PULL 45/89] target/riscv: remove cpu->cfg.ext_u
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "u" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
5
replaced with riscv_has_ext(env, RVU).
6
7
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 9 ++++-----
17
2 files changed, 4 insertions(+), 6 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_u;
28
bool ext_h;
29
bool ext_j;
30
bool ext_v;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
36
set_priv_version(env, PRIV_VERSION_1_11_0);
37
38
cpu->cfg.ext_g = true;
39
- cpu->cfg.ext_u = true;
40
cpu->cfg.ext_icsr = true;
41
cpu->cfg.ext_zfh = true;
42
cpu->cfg.mmu = true;
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
44
return;
45
}
46
47
- if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
48
+ if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
49
error_setg(errp,
50
"Setting S extension without U extension is illegal");
51
return;
52
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
53
if (riscv_has_ext(env, RVS)) {
54
ext |= RVS;
55
}
56
- if (riscv_cpu_cfg(env)->ext_u) {
57
+ if (riscv_has_ext(env, RVU)) {
58
ext |= RVU;
59
}
60
if (riscv_cpu_cfg(env)->ext_h) {
61
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
62
.misa_bit = RVM, .enabled = true},
63
{.name = "s", .description = "Supervisor-level instructions",
64
.misa_bit = RVS, .enabled = true},
65
+ {.name = "u", .description = "User-level instructions",
66
+ .misa_bit = RVU, .enabled = true},
67
};
68
69
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
70
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
71
static Property riscv_cpu_extensions[] = {
72
/* Defaults for standard extensions */
73
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
74
- DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
75
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
76
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
77
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
78
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
79
*/
80
if (cpu->env.misa_ext != 0) {
81
cpu->cfg.ext_v = misa_ext & RVV;
82
- cpu->cfg.ext_u = misa_ext & RVU;
83
cpu->cfg.ext_h = misa_ext & RVH;
84
cpu->cfg.ext_j = misa_ext & RVJ;
85
86
--
87
2.40.0
diff view generated by jsdifflib
New patch
[PULL 46/89] target/riscv: remove cpu->cfg.ext_h
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "h" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
5
replaced with riscv_has_ext(env, RVH).
6
7
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 10 +++++-----
17
2 files changed, 5 insertions(+), 6 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_h;
28
bool ext_j;
29
bool ext_v;
30
bool ext_zba;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
return;
37
}
38
39
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
40
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
41
error_setg(errp,
42
"H depends on an I base integer ISA with 32 x registers");
43
return;
44
}
45
46
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
47
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
48
error_setg(errp, "H extension implicitly requires S-mode");
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
52
if (riscv_has_ext(env, RVU)) {
53
ext |= RVU;
54
}
55
- if (riscv_cpu_cfg(env)->ext_h) {
56
+ if (riscv_has_ext(env, RVH)) {
57
ext |= RVH;
58
}
59
if (riscv_cpu_cfg(env)->ext_v) {
60
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
61
.misa_bit = RVS, .enabled = true},
62
{.name = "u", .description = "User-level instructions",
63
.misa_bit = RVU, .enabled = true},
64
+ {.name = "h", .description = "Hypervisor",
65
+ .misa_bit = RVH, .enabled = true},
66
};
67
68
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
69
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
70
/* Defaults for standard extensions */
71
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
72
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
73
- DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
74
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
75
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
76
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
77
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
78
*/
79
if (cpu->env.misa_ext != 0) {
80
cpu->cfg.ext_v = misa_ext & RVV;
81
- cpu->cfg.ext_h = misa_ext & RVH;
82
cpu->cfg.ext_j = misa_ext & RVJ;
83
84
/*
85
--
86
2.40.0
diff view generated by jsdifflib
New patch
[PULL 47/89] target/riscv: remove cpu->cfg.ext_j
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "j" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
5
replaced with riscv_has_ext(env, RVJ).
6
7
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 6 +++---
17
2 files changed, 3 insertions(+), 4 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_j;
28
bool ext_v;
29
bool ext_zba;
30
bool ext_zbb;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
36
if (riscv_cpu_cfg(env)->ext_v) {
37
ext |= RVV;
38
}
39
- if (riscv_cpu_cfg(env)->ext_j) {
40
+ if (riscv_has_ext(env, RVJ)) {
41
ext |= RVJ;
42
}
43
44
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
45
.misa_bit = RVU, .enabled = true},
46
{.name = "h", .description = "Hypervisor",
47
.misa_bit = RVH, .enabled = true},
48
+ {.name = "x-j", .description = "Dynamic translated languages",
49
+ .misa_bit = RVJ, .enabled = false},
50
};
51
52
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
53
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
54
55
/* These are experimental so mark with 'x-' */
56
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
57
- DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
58
59
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
60
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
61
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
62
*/
63
if (cpu->env.misa_ext != 0) {
64
cpu->cfg.ext_v = misa_ext & RVV;
65
- cpu->cfg.ext_j = misa_ext & RVJ;
66
67
/*
68
* We don't want to set the default riscv_cpu_extensions
69
--
70
2.40.0
diff view generated by jsdifflib
New patch
[PULL 48/89] target/riscv: remove cpu->cfg.ext_v
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Create a new "v" RISCVCPUMisaExtConfig property that will update
4
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
5
replaced with riscv_has_ext(env, RVV).
6
7
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 1 -
16
target/riscv/cpu.c | 12 +++++-------
17
2 files changed, 5 insertions(+), 8 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
25
struct RISCVCPUConfig {
26
bool ext_g;
27
- bool ext_v;
28
bool ext_zba;
29
bool ext_zbb;
30
bool ext_zbc;
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
36
}
37
38
/* The V vector extension depends on the Zve64d extension */
39
- if (cpu->cfg.ext_v) {
40
+ if (riscv_has_ext(env, RVV)) {
41
cpu->cfg.ext_zve64d = true;
42
}
43
44
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
45
cpu->cfg.ext_zksh = true;
46
}
47
48
- if (cpu->cfg.ext_v) {
49
+ if (riscv_has_ext(env, RVV)) {
50
int vext_version = VEXT_VERSION_1_00_0;
51
if (!is_power_of_2(cpu->cfg.vlen)) {
52
error_setg(errp,
53
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
54
if (riscv_has_ext(env, RVH)) {
55
ext |= RVH;
56
}
57
- if (riscv_cpu_cfg(env)->ext_v) {
58
+ if (riscv_has_ext(env, RVV)) {
59
ext |= RVV;
60
}
61
if (riscv_has_ext(env, RVJ)) {
62
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
63
.misa_bit = RVH, .enabled = true},
64
{.name = "x-j", .description = "Dynamic translated languages",
65
.misa_bit = RVJ, .enabled = false},
66
+ {.name = "v", .description = "Vector operations",
67
+ .misa_bit = RVV, .enabled = false},
68
};
69
70
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
71
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
72
static Property riscv_cpu_extensions[] = {
73
/* Defaults for standard extensions */
74
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
75
- DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
76
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
77
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
78
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
79
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
80
static void register_cpu_props(Object *obj)
81
{
82
RISCVCPU *cpu = RISCV_CPU(obj);
83
- uint32_t misa_ext = cpu->env.misa_ext;
84
Property *prop;
85
DeviceState *dev = DEVICE(obj);
86
87
@@ -XXX,XX +XXX,XX @@ static void register_cpu_props(Object *obj)
88
* later on.
89
*/
90
if (cpu->env.misa_ext != 0) {
91
- cpu->cfg.ext_v = misa_ext & RVV;
92
-
93
/*
94
* We don't want to set the default riscv_cpu_extensions
95
* in this case.
96
--
97
2.40.0
diff view generated by jsdifflib
New patch
[PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
This function was created to move the sync between cpu->cfg.ext_N bit
4
changes to env->misa_ext* from the validation step to an ealier step,
5
giving us a guarantee that we could use either cpu->cfg.ext_N or
6
riscv_has_ext(env,N) in the validation.
7
8
We don't have any cpu->cfg.ext_N left that has an existing MISA bit
9
(cfg.ext_g will be handled shortly). The function is now a no-op, simply
10
copying the existing values of misa_ext* back to misa_ext*.
11
12
Remove it.
13
14
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
target/riscv/cpu.c | 52 ----------------------------------------------
21
1 file changed, 52 deletions(-)
22
23
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/cpu.c
26
+++ b/target/riscv/cpu.c
27
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
28
#endif
29
}
30
31
-static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
32
-{
33
- uint32_t ext = 0;
34
-
35
- if (riscv_has_ext(env, RVI)) {
36
- ext |= RVI;
37
- }
38
- if (riscv_has_ext(env, RVE)) {
39
- ext |= RVE;
40
- }
41
- if (riscv_has_ext(env, RVM)) {
42
- ext |= RVM;
43
- }
44
- if (riscv_has_ext(env, RVA)) {
45
- ext |= RVA;
46
- }
47
- if (riscv_has_ext(env, RVF)) {
48
- ext |= RVF;
49
- }
50
- if (riscv_has_ext(env, RVD)) {
51
- ext |= RVD;
52
- }
53
- if (riscv_has_ext(env, RVC)) {
54
- ext |= RVC;
55
- }
56
- if (riscv_has_ext(env, RVS)) {
57
- ext |= RVS;
58
- }
59
- if (riscv_has_ext(env, RVU)) {
60
- ext |= RVU;
61
- }
62
- if (riscv_has_ext(env, RVH)) {
63
- ext |= RVH;
64
- }
65
- if (riscv_has_ext(env, RVV)) {
66
- ext |= RVV;
67
- }
68
- if (riscv_has_ext(env, RVJ)) {
69
- ext |= RVJ;
70
- }
71
-
72
- env->misa_ext = env->misa_ext_mask = ext;
73
-}
74
-
75
static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
76
{
77
if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
78
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
79
set_priv_version(env, priv_version);
80
}
81
82
- /*
83
- * We can't be sure of whether we set defaults during cpu_init()
84
- * or whether the user enabled/disabled some bits via cpu->cfg
85
- * flags. Sync env->misa_ext with cpu->cfg now to allow us to
86
- * use just env->misa_ext later.
87
- */
88
- riscv_cpu_sync_misa_cfg(env);
89
-
90
riscv_cpu_validate_misa_priv(env, &local_err);
91
if (local_err != NULL) {
92
error_propagate(errp, local_err);
93
--
94
2.40.0
diff view generated by jsdifflib
New patch
[PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
This CPU is enabling G via cfg.ext_g and, at the same time, setting
4
IMAFD in set_misa() and cfg.ext_icsr.
5
6
riscv_cpu_validate_set_extensions() is already doing that, so there's no
7
need for cpu_init() setups to worry about setting G and its extensions.
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu.c
21
+++ b/target/riscv/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
23
CPURISCVState *env = &RISCV_CPU(obj)->env;
24
RISCVCPU *cpu = RISCV_CPU(obj);
25
26
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
27
+ set_misa(env, MXL_RV64, RVC | RVS | RVU);
28
set_priv_version(env, PRIV_VERSION_1_11_0);
29
30
cpu->cfg.ext_g = true;
31
- cpu->cfg.ext_icsr = true;
32
cpu->cfg.ext_zfh = true;
33
cpu->cfg.mmu = true;
34
cpu->cfg.ext_xtheadba = true;
35
--
36
2.40.0
diff view generated by jsdifflib
New patch
[PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
4
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
5
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
6
and use riscv_has_ext(env, RVG).
7
8
The caveat is that we don't have RVG, so add it. RVG will be used right
9
off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
10
enabling G via the now removed 'ext_g' flag.
11
12
After this patch, there are no more MISA extensions represented by flags
13
in RISCVCPUConfig.
14
15
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
16
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
21
target/riscv/cpu.h | 2 +-
22
target/riscv/cpu.c | 17 ++++++++---------
23
2 files changed, 9 insertions(+), 10 deletions(-)
24
25
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu.h
28
+++ b/target/riscv/cpu.h
29
@@ -XXX,XX +XXX,XX @@
30
#define RVU RV('U')
31
#define RVH RV('H')
32
#define RVJ RV('J')
33
+#define RVG RV('G')
34
35
36
/* Privileged specification version */
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
} RISCVSATPMap;
39
40
struct RISCVCPUConfig {
41
- bool ext_g;
42
bool ext_zba;
43
bool ext_zbb;
44
bool ext_zbc;
45
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/riscv/cpu.c
48
+++ b/target/riscv/cpu.c
49
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
50
CPURISCVState *env = &RISCV_CPU(obj)->env;
51
RISCVCPU *cpu = RISCV_CPU(obj);
52
53
- set_misa(env, MXL_RV64, RVC | RVS | RVU);
54
+ set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
55
set_priv_version(env, PRIV_VERSION_1_11_0);
56
57
- cpu->cfg.ext_g = true;
58
cpu->cfg.ext_zfh = true;
59
cpu->cfg.mmu = true;
60
cpu->cfg.ext_xtheadba = true;
61
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
62
CPURISCVState *env = &cpu->env;
63
64
/* Do some ISA extension error checking */
65
- if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
66
- riscv_has_ext(env, RVM) &&
67
- riscv_has_ext(env, RVA) &&
68
- riscv_has_ext(env, RVF) &&
69
- riscv_has_ext(env, RVD) &&
70
- cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
71
+ if (riscv_has_ext(env, RVG) &&
72
+ !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
73
+ riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
74
+ riscv_has_ext(env, RVD) &&
75
+ cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
76
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
77
cpu->cfg.ext_icsr = true;
78
cpu->cfg.ext_ifencei = true;
79
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
80
.misa_bit = RVJ, .enabled = false},
81
{.name = "v", .description = "Vector operations",
82
.misa_bit = RVV, .enabled = false},
83
+ {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)",
84
+ .misa_bit = RVG, .enabled = false},
85
};
86
87
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
88
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
89
90
static Property riscv_cpu_extensions[] = {
91
/* Defaults for standard extensions */
92
- DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
93
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
94
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
95
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
96
--
97
2.40.0
diff view generated by jsdifflib
New patch
[PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
The function is now a no-op for all cpu_init() callers that are setting
4
a non-zero misa value in set_misa(), since it's no longer used to sync
5
cpu->cfg props with env->misa_ext bits. Remove it in those cases.
6
7
While we're at it, rename the function to match what it's actually
8
doing: create user properties to set/remove CPU extensions. Make a note
9
that it will overwrite env->misa_ext with the defaults set by each user
10
property.
11
12
Update the MISA bits comment in cpu.h as well.
13
14
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
target/riscv/cpu.h | 5 +----
21
target/riscv/cpu.c | 41 ++++++++++-------------------------------
22
2 files changed, 11 insertions(+), 35 deletions(-)
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@
29
30
#define RV(x) ((target_ulong)1 << (x - 'A'))
31
32
-/*
33
- * Consider updating register_cpu_props() when adding
34
- * new MISA bits here.
35
- */
36
+/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
37
#define RVI RV('I')
38
#define RVE RV('E') /* E and I are mutually exclusive */
39
#define RVM RV('M')
40
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/riscv/cpu.c
43
+++ b/target/riscv/cpu.c
44
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
45
"reserved"
46
};
47
48
-static void register_cpu_props(Object *obj);
49
+static void riscv_cpu_add_user_properties(Object *obj);
50
51
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
52
{
53
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
54
#endif
55
56
set_priv_version(env, PRIV_VERSION_1_12_0);
57
- register_cpu_props(obj);
58
}
59
60
#if defined(TARGET_RISCV64)
61
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
62
CPURISCVState *env = &RISCV_CPU(obj)->env;
63
/* We set this in the realise function */
64
set_misa(env, MXL_RV64, 0);
65
- register_cpu_props(obj);
66
+ riscv_cpu_add_user_properties(obj);
67
/* Set latest version of privileged specification */
68
set_priv_version(env, PRIV_VERSION_1_12_0);
69
#ifndef CONFIG_USER_ONLY
70
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
71
{
72
CPURISCVState *env = &RISCV_CPU(obj)->env;
73
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
74
- register_cpu_props(obj);
75
set_priv_version(env, PRIV_VERSION_1_10_0);
76
#ifndef CONFIG_USER_ONLY
77
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
78
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
79
RISCVCPU *cpu = RISCV_CPU(obj);
80
81
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
82
- register_cpu_props(obj);
83
set_priv_version(env, PRIV_VERSION_1_10_0);
84
cpu->cfg.mmu = false;
85
#ifndef CONFIG_USER_ONLY
86
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
87
CPURISCVState *env = &RISCV_CPU(obj)->env;
88
/* We set this in the realise function */
89
set_misa(env, MXL_RV128, 0);
90
- register_cpu_props(obj);
91
+ riscv_cpu_add_user_properties(obj);
92
/* Set latest version of privileged specification */
93
set_priv_version(env, PRIV_VERSION_1_12_0);
94
#ifndef CONFIG_USER_ONLY
95
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
96
CPURISCVState *env = &RISCV_CPU(obj)->env;
97
/* We set this in the realise function */
98
set_misa(env, MXL_RV32, 0);
99
- register_cpu_props(obj);
100
+ riscv_cpu_add_user_properties(obj);
101
/* Set latest version of privileged specification */
102
set_priv_version(env, PRIV_VERSION_1_12_0);
103
#ifndef CONFIG_USER_ONLY
104
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
105
{
106
CPURISCVState *env = &RISCV_CPU(obj)->env;
107
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
108
- register_cpu_props(obj);
109
set_priv_version(env, PRIV_VERSION_1_10_0);
110
#ifndef CONFIG_USER_ONLY
111
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
112
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
113
RISCVCPU *cpu = RISCV_CPU(obj);
114
115
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
116
- register_cpu_props(obj);
117
set_priv_version(env, PRIV_VERSION_1_10_0);
118
cpu->cfg.mmu = false;
119
#ifndef CONFIG_USER_ONLY
120
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
121
RISCVCPU *cpu = RISCV_CPU(obj);
122
123
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
124
- register_cpu_props(obj);
125
set_priv_version(env, PRIV_VERSION_1_11_0);
126
cpu->cfg.mmu = false;
127
#ifndef CONFIG_USER_ONLY
128
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
129
RISCVCPU *cpu = RISCV_CPU(obj);
130
131
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
132
- register_cpu_props(obj);
133
set_priv_version(env, PRIV_VERSION_1_10_0);
134
cpu->cfg.mmu = false;
135
#ifndef CONFIG_USER_ONLY
136
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
137
#elif defined(TARGET_RISCV64)
138
set_misa(env, MXL_RV64, 0);
139
#endif
140
- register_cpu_props(obj);
141
+ riscv_cpu_add_user_properties(obj);
142
}
143
#endif
144
145
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
146
};
147
148
/*
149
- * Register CPU props based on env.misa_ext. If a non-zero
150
- * value was set, register only the required cpu->cfg.ext_*
151
- * properties and leave. env.misa_ext = 0 means that we want
152
- * all the default properties to be registered.
153
+ * Add CPU properties with user-facing flags.
154
+ *
155
+ * This will overwrite existing env->misa_ext values with the
156
+ * defaults set via riscv_cpu_add_misa_properties().
157
*/
158
-static void register_cpu_props(Object *obj)
159
+static void riscv_cpu_add_user_properties(Object *obj)
160
{
161
- RISCVCPU *cpu = RISCV_CPU(obj);
162
Property *prop;
163
DeviceState *dev = DEVICE(obj);
164
165
- /*
166
- * If misa_ext is not zero, set cfg properties now to
167
- * allow them to be read during riscv_cpu_realize()
168
- * later on.
169
- */
170
- if (cpu->env.misa_ext != 0) {
171
- /*
172
- * We don't want to set the default riscv_cpu_extensions
173
- * in this case.
174
- */
175
- return;
176
- }
177
-
178
riscv_cpu_add_misa_properties(obj);
179
180
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
181
--
182
2.40.0
diff view generated by jsdifflib
New patch
[PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
The MPP will be set to the least-privileged supported mode (U if
4
U-mode is implemented, else M).
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230407014743.18779-2-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/op_helper.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/op_helper.c
18
+++ b/target/riscv/op_helper.c
19
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env)
20
mstatus = set_field(mstatus, MSTATUS_MIE,
21
get_field(mstatus, MSTATUS_MPIE));
22
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
23
- mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
24
+ mstatus = set_field(mstatus, MSTATUS_MPP,
25
+ riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
26
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
27
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
28
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
29
--
30
2.40.0
diff view generated by jsdifflib
New patch
[PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
PRV_H has no real meaning, but just a reserved privilege mode currently.
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
10
[ Changes by AF:
11
- Convert one missing use of PRV_H
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu.h | 2 +-
16
target/riscv/cpu_bits.h | 2 +-
17
target/riscv/cpu_helper.c | 2 +-
18
target/riscv/gdbstub.c | 2 +-
19
target/riscv/op_helper.c | 2 +-
20
5 files changed, 5 insertions(+), 5 deletions(-)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
27
case PRV_U:
28
xl = get_field(env->mstatus, MSTATUS64_UXL);
29
break;
30
- default: /* PRV_S | PRV_H */
31
+ default: /* PRV_S */
32
xl = get_field(env->mstatus, MSTATUS64_SXL);
33
break;
34
}
35
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_bits.h
38
+++ b/target/riscv/cpu_bits.h
39
@@ -XXX,XX +XXX,XX @@ typedef enum {
40
/* Privilege modes */
41
#define PRV_U 0
42
#define PRV_S 1
43
-#define PRV_H 2 /* Reserved */
44
+#define PRV_RESERVED 2
45
#define PRV_M 3
46
47
/* RV32 satp CSR field masks */
48
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/cpu_helper.c
51
+++ b/target/riscv/cpu_helper.c
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
53
if (newpriv > PRV_M) {
54
g_assert_not_reached();
55
}
56
- if (newpriv == PRV_H) {
57
+ if (newpriv == PRV_RESERVED) {
58
newpriv = PRV_U;
59
}
60
if (icount_enabled() && newpriv != env->priv) {
61
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/gdbstub.c
64
+++ b/target/riscv/gdbstub.c
65
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
66
if (n == 0) {
67
#ifndef CONFIG_USER_ONLY
68
cs->priv = ldtul_p(mem_buf) & 0x3;
69
- if (cs->priv == PRV_H) {
70
+ if (cs->priv == PRV_RESERVED) {
71
cs->priv = PRV_S;
72
}
73
#endif
74
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/op_helper.c
77
+++ b/target/riscv/op_helper.c
78
@@ -XXX,XX +XXX,XX @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
79
}
80
81
if (env->virt_enabled &&
82
- (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
83
+ (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||
84
((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
85
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
86
}
87
--
88
2.40.0
diff view generated by jsdifflib
New patch
[PULL 55/89] target/riscv: Legalize MPP value in write_mstatus
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
mstatus.MPP field is a WARL field since priv version 1.11, so we
4
remain it unchanged if an invalid value is written into it. And
5
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
6
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 8 ++------
15
target/riscv/csr.c | 32 ++++++++++++++++++++++++++++++++
16
2 files changed, 34 insertions(+), 6 deletions(-)
17
18
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu_helper.c
21
+++ b/target/riscv/cpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
23
24
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
25
{
26
- if (newpriv > PRV_M) {
27
- g_assert_not_reached();
28
- }
29
- if (newpriv == PRV_RESERVED) {
30
- newpriv = PRV_U;
31
- }
32
+ g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
33
+
34
if (icount_enabled() && newpriv != env->priv) {
35
riscv_itrigger_update_priv(env);
36
}
37
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/csr.c
40
+++ b/target/riscv/csr.c
41
@@ -XXX,XX +XXX,XX @@ static bool validate_vm(CPURISCVState *env, target_ulong vm)
42
satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
43
}
44
45
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
46
+ target_ulong val)
47
+{
48
+ bool valid = false;
49
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
50
+
51
+ switch (new_mpp) {
52
+ case PRV_M:
53
+ valid = true;
54
+ break;
55
+ case PRV_S:
56
+ valid = riscv_has_ext(env, RVS);
57
+ break;
58
+ case PRV_U:
59
+ valid = riscv_has_ext(env, RVU);
60
+ break;
61
+ }
62
+
63
+ /* Remain field unchanged if new_mpp value is invalid */
64
+ if (!valid) {
65
+ val = set_field(val, MSTATUS_MPP, old_mpp);
66
+ }
67
+
68
+ return val;
69
+}
70
+
71
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
72
target_ulong val)
73
{
74
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
75
uint64_t mask = 0;
76
RISCVMXL xl = riscv_cpu_mxl(env);
77
78
+ /*
79
+ * MPP field have been made WARL since priv version 1.11. However,
80
+ * legalization for it will not break any software running on 1.10.
81
+ */
82
+ val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
83
+
84
/* flush tlb on mstatus fields that affect VM */
85
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
86
MSTATUS_MPRV | MSTATUS_SUM)) {
87
--
88
2.40.0
diff view generated by jsdifflib
New patch
[PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
4
by check currently.
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu.c | 5 +++--
13
1 file changed, 3 insertions(+), 2 deletions(-)
14
15
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.c
18
+++ b/target/riscv/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
20
cpu->cfg.ext_zhinxmin = true;
21
}
22
23
- if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
24
- cpu->cfg.ext_zfinx = true;
25
+ if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
26
+ error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
27
+ return;
28
}
29
30
if (cpu->cfg.ext_zfinx) {
31
--
32
2.40.0
diff view generated by jsdifflib
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
[PULL 57/89] target/riscv: fix H extension TVM trap
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Yi Chen <chenyi2000@zju.edu.cn>
2
2
3
The previous implementation was broken in many ways:
3
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
4
- Used mideleg instead of hideleg to mask accesses
4
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
5
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
6
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
7
SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with
8
HSTATUS.VTVM enabled.
9
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
10
HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA.
7
11
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
12
Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn>
13
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
16
Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
18
---
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
19
target/riscv/csr.c | 56 +++++++++++++++++++++++++---------------
14
1 file changed, 34 insertions(+), 34 deletions(-)
20
target/riscv/op_helper.c | 12 ++++-----
21
2 files changed, 41 insertions(+), 27 deletions(-)
15
22
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
23
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
25
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
26
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
27
@@ -XXX,XX +XXX,XX @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
21
return write_mstatus(env, CSR_MSTATUS, newval);
28
return sstc(env, csrno);
22
}
29
}
23
30
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
31
+static RISCVException satp(CPURISCVState *env, int csrno)
25
+{
32
+{
26
+ /* Shift the VS bits to their S bit location in vsie */
33
+ if (env->priv == PRV_S && !env->virt_enabled &&
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
34
+ get_field(env->mstatus, MSTATUS_TVM)) {
28
+ return 0;
35
+ return RISCV_EXCP_ILLEGAL_INST;
36
+ }
37
+ if (env->priv == PRV_S && env->virt_enabled &&
38
+ get_field(env->hstatus, HSTATUS_VTVM)) {
39
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
40
+ }
41
+
42
+ return smode(env, csrno);
29
+}
43
+}
30
+
44
+
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
45
+static RISCVException hgatp(CPURISCVState *env, int csrno)
32
{
33
if (riscv_cpu_virt_enabled(env)) {
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
36
+ read_vsie(env, CSR_VSIE, val);
37
} else {
38
*val = env->mie & env->mideleg;
39
}
40
return 0;
41
}
42
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
45
{
46
- target_ulong newval;
47
+ /* Shift the S bits to their VS bit location in mie */
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
50
+ return write_mie(env, CSR_MIE, newval);
51
+}
52
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
54
+{
46
+{
55
if (riscv_cpu_virt_enabled(env)) {
47
+ if (env->priv == PRV_S && !env->virt_enabled &&
56
- /* Shift the guests S bits to VS */
48
+ get_field(env->mstatus, MSTATUS_TVM)) {
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
49
+ return RISCV_EXCP_ILLEGAL_INST;
58
- ((val << 1) & VS_MODE_INTERRUPTS);
50
+ }
59
+ write_vsie(env, CSR_VSIE, val);
51
+
60
} else {
52
+ return hmode(env, csrno);
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
63
+ (val & S_MODE_INTERRUPTS);
64
+ write_mie(env, CSR_MIE, newval);
65
}
66
67
- return write_mie(env, CSR_MIE, newval);
68
+ return 0;
69
}
70
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
73
return 0;
74
}
75
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
77
+ target_ulong new_value, target_ulong write_mask)
78
+{
79
+ /* Shift the S bits to their VS bit location in mip */
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
86
+}
53
+}
87
+
54
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
55
/* Checks if PointerMasking registers could be accessed */
89
target_ulong new_value, target_ulong write_mask)
56
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
90
{
57
{
91
int ret;
58
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
92
59
*val = 0;
93
if (riscv_cpu_virt_enabled(env)) {
60
return RISCV_EXCP_NONE;
94
- /* Shift the new values to line up with the VS bits */
61
}
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
62
-
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
63
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
97
- ret &= vsip_writable_mask;
64
- return RISCV_EXCP_ILLEGAL_INST;
98
- ret >>= 1;
65
- } else {
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
66
- *val = env->satp;
67
- }
68
-
69
+ *val = env->satp;
70
return RISCV_EXCP_NONE;
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
74
}
75
76
if (vm && mask) {
77
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
78
- return RISCV_EXCP_ILLEGAL_INST;
79
- } else {
80
- /*
81
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
82
- * pass these through QEMU's TLB emulation as it improves
83
- * performance. Flushing the TLB on SATP writes with paging
84
- * enabled avoids leaking those invalid cached mappings.
85
- */
86
- tlb_flush(env_cpu(env));
87
- env->satp = val;
88
- }
89
+ /*
90
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
91
+ * pass these through QEMU's TLB emulation as it improves
92
+ * performance. Flushing the TLB on SATP writes with paging
93
+ * enabled avoids leaking those invalid cached mappings.
94
+ */
95
+ tlb_flush(env_cpu(env));
96
+ env->satp = val;
97
}
98
return RISCV_EXCP_NONE;
99
}
100
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
101
.min_priv_ver = PRIV_VERSION_1_12_0 },
102
103
/* Supervisor Protection and Translation */
104
- [CSR_SATP] = { "satp", smode, read_satp, write_satp },
105
+ [CSR_SATP] = { "satp", satp, read_satp, write_satp },
106
107
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
108
[CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
109
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
110
.min_priv_ver = PRIV_VERSION_1_12_0 },
111
[CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
112
.min_priv_ver = PRIV_VERSION_1_12_0 },
113
- [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
114
+ [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp,
115
.min_priv_ver = PRIV_VERSION_1_12_0 },
116
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
117
write_htimedelta,
118
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/op_helper.c
121
+++ b/target/riscv/op_helper.c
122
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
123
void helper_tlb_flush(CPURISCVState *env)
124
{
125
CPUState *cs = env_cpu(env);
126
- if (!(env->priv >= PRV_S) ||
127
- (env->priv == PRV_S &&
128
- get_field(env->mstatus, MSTATUS_TVM))) {
129
+ if (!env->virt_enabled &&
130
+ (env->priv == PRV_U ||
131
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) {
132
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
133
- } else if (riscv_has_ext(env, RVH) && env->virt_enabled &&
134
- get_field(env->hstatus, HSTATUS_VTVM)) {
135
+ } else if (env->virt_enabled &&
136
+ (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
137
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
100
} else {
138
} else {
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
139
tlb_flush(cs);
102
write_mask & env->mideleg & sip_writable_mask);
140
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
104
return 0;
105
}
106
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
108
- target_ulong new_value, target_ulong write_mask)
109
-{
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
111
- write_mask & env->mideleg & vsip_writable_mask);
112
- return ret;
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
141
{
129
*val = env->vstvec;
142
CPUState *cs = env_cpu(env);
143
144
- if (env->priv == PRV_S && env->virt_enabled) {
145
+ if (env->virt_enabled) {
146
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
147
}
148
130
--
149
--
131
2.30.1
150
2.40.0
132
133
diff view generated by jsdifflib
New patch
[PULL 58/89] target/riscv: Extract virt enabled state from tb flags
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
Virt enabled state is not a constant, so we should put it into tb flags.
4
Thus we can use it like a constant condition at translation phase.
5
6
Reported-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org>
14
Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu.h | 2 ++
18
target/riscv/cpu_helper.c | 1 +
19
target/riscv/translate.c | 10 +---------
20
3 files changed, 4 insertions(+), 9 deletions(-)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VTA, 24, 1)
27
FIELD(TB_FLAGS, VMA, 25, 1)
28
/* Native debug itrigger */
29
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
30
+/* Virtual mode enabled */
31
+FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
32
33
#ifdef TARGET_RISCV32
34
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_helper.c
38
+++ b/target/riscv/cpu_helper.c
39
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
40
41
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
42
get_field(env->mstatus_hs, MSTATUS_VS));
43
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled);
44
}
45
if (cpu->cfg.debug && !icount_enabled()) {
46
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
47
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/translate.c
50
+++ b/target/riscv/translate.c
51
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
52
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
53
ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
54
ctx->priv_ver = env->priv_ver;
55
-#if !defined(CONFIG_USER_ONLY)
56
- if (riscv_has_ext(env, RVH)) {
57
- ctx->virt_enabled = env->virt_enabled;
58
- } else {
59
- ctx->virt_enabled = false;
60
- }
61
-#else
62
- ctx->virt_enabled = false;
63
-#endif
64
+ ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
65
ctx->misa_ext = env->misa_ext;
66
ctx->frm = -1; /* unknown rounding mode */
67
ctx->cfg_ptr = &(cpu->cfg);
68
--
69
2.40.0
diff view generated by jsdifflib
New patch
[PULL 59/89] target/riscv: Add a general status enum for extensions
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
The pointer masking is the only extension that directly use status.
4
The vector or float extension uses the status in an indirect way.
5
6
Replace the pointer masking extension special status fields with
7
the general status.
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
12
[rth: Add a typedef for the enum]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
16
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
18
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
21
target/riscv/cpu.h | 8 ++++++++
22
target/riscv/cpu_bits.h | 12 ++++--------
23
target/riscv/cpu.c | 2 +-
24
target/riscv/csr.c | 14 +++++++-------
25
4 files changed, 20 insertions(+), 16 deletions(-)
26
27
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/cpu.h
30
+++ b/target/riscv/cpu.h
31
@@ -XXX,XX +XXX,XX @@ enum {
32
TRANSLATE_G_STAGE_FAIL
33
};
34
35
+/* Extension context status */
36
+typedef enum {
37
+ EXT_STATUS_DISABLED = 0,
38
+ EXT_STATUS_INITIAL,
39
+ EXT_STATUS_CLEAN,
40
+ EXT_STATUS_DIRTY,
41
+} RISCVExtStatus;
42
+
43
#define MMU_USER_IDX 3
44
45
#define MAX_RISCV_PMPS (16)
46
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/cpu_bits.h
49
+++ b/target/riscv/cpu_bits.h
50
@@ -XXX,XX +XXX,XX @@
51
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
52
(uint64_t)(mask)))
53
54
+/* Extension context status mask */
55
+#define EXT_STATUS_MASK 0x3ULL
56
+
57
/* Floating point round mode */
58
#define FSR_RD_SHIFT 5
59
#define FSR_RD (0x7 << FSR_RD_SHIFT)
60
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
61
#define PM_ENABLE 0x00000001ULL
62
#define PM_CURRENT 0x00000002ULL
63
#define PM_INSN 0x00000004ULL
64
-#define PM_XS_MASK 0x00000003ULL
65
-
66
-/* PointerMasking XS bits values */
67
-#define PM_EXT_DISABLE 0x00000000ULL
68
-#define PM_EXT_INITIAL 0x00000001ULL
69
-#define PM_EXT_CLEAN 0x00000002ULL
70
-#define PM_EXT_DIRTY 0x00000003ULL
71
72
/* Execution enviornment configuration bits */
73
#define MENVCFG_FIOM BIT(0)
74
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
75
#define S_OFFSET 5ULL
76
#define M_OFFSET 8ULL
77
78
-#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
79
+#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
80
#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
81
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
82
#define U_PM_INSN (PM_INSN << U_OFFSET)
83
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/riscv/cpu.c
86
+++ b/target/riscv/cpu.c
87
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
88
i++;
89
}
90
/* mmte is supposed to have pm.current hardwired to 1 */
91
- env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
92
+ env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
93
#endif
94
env->xl = riscv_cpu_mxl(env);
95
riscv_cpu_update_mask(env);
96
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/riscv/csr.c
99
+++ b/target/riscv/csr.c
100
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
101
102
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
103
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
104
- env->mmte = wpri_val | PM_EXT_DIRTY;
105
+ env->mmte = wpri_val | EXT_STATUS_DIRTY;
106
riscv_cpu_update_mask(env);
107
108
/* Set XS and SD bits, since PM CSRs are dirty */
109
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
110
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
111
env->cur_pmmask = val;
112
}
113
- env->mmte |= PM_EXT_DIRTY;
114
+ env->mmte |= EXT_STATUS_DIRTY;
115
116
/* Set XS and SD bits, since PM CSRs are dirty */
117
mstatus = env->mstatus | MSTATUS_XS;
118
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
119
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
120
env->cur_pmmask = val;
121
}
122
- env->mmte |= PM_EXT_DIRTY;
123
+ env->mmte |= EXT_STATUS_DIRTY;
124
125
/* Set XS and SD bits, since PM CSRs are dirty */
126
mstatus = env->mstatus | MSTATUS_XS;
127
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
128
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
129
env->cur_pmmask = val;
130
}
131
- env->mmte |= PM_EXT_DIRTY;
132
+ env->mmte |= EXT_STATUS_DIRTY;
133
134
/* Set XS and SD bits, since PM CSRs are dirty */
135
mstatus = env->mstatus | MSTATUS_XS;
136
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
137
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
138
env->cur_pmbase = val;
139
}
140
- env->mmte |= PM_EXT_DIRTY;
141
+ env->mmte |= EXT_STATUS_DIRTY;
142
143
/* Set XS and SD bits, since PM CSRs are dirty */
144
mstatus = env->mstatus | MSTATUS_XS;
145
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
146
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
147
env->cur_pmbase = val;
148
}
149
- env->mmte |= PM_EXT_DIRTY;
150
+ env->mmte |= EXT_STATUS_DIRTY;
151
152
/* Set XS and SD bits, since PM CSRs are dirty */
153
mstatus = env->mstatus | MSTATUS_XS;
154
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
155
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
156
env->cur_pmbase = val;
157
}
158
- env->mmte |= PM_EXT_DIRTY;
159
+ env->mmte |= EXT_STATUS_DIRTY;
160
161
/* Set XS and SD bits, since PM CSRs are dirty */
162
mstatus = env->mstatus | MSTATUS_XS;
163
--
164
2.40.0
diff view generated by jsdifflib
New patch
[PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags
1
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
2
3
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
4
normal way.
5
6
It will make it hard to change the tb flags layout. And even worse, if we
7
want to keep tb flags for a same extension togather without a hole.
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
13
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
18
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
21
target/riscv/cpu.h | 15 ++++++------
22
target/riscv/cpu_helper.c | 11 +++++----
23
target/riscv/translate.c | 32 +++++++++++--------------
24
target/riscv/insn_trans/trans_rvf.c.inc | 2 +-
25
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++----
26
5 files changed, 32 insertions(+), 36 deletions(-)
27
28
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/riscv/cpu.h
31
+++ b/target/riscv/cpu.h
32
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
33
34
#define TB_FLAGS_PRIV_MMU_MASK 3
35
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
36
-#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
37
-#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
38
39
#include "exec/cpu-all.h"
40
41
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
42
-FIELD(TB_FLAGS, LMUL, 3, 3)
43
-FIELD(TB_FLAGS, SEW, 6, 3)
44
-/* Skip MSTATUS_VS (0x600) bits */
45
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
46
-FIELD(TB_FLAGS, VILL, 12, 1)
47
-/* Skip MSTATUS_FS (0x6000) bits */
48
+FIELD(TB_FLAGS, FS, 3, 2)
49
+/* Vector flags */
50
+FIELD(TB_FLAGS, VS, 5, 2)
51
+FIELD(TB_FLAGS, LMUL, 7, 3)
52
+FIELD(TB_FLAGS, SEW, 10, 3)
53
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
54
+FIELD(TB_FLAGS, VILL, 14, 1)
55
/* Is a Hypervisor instruction load/store allowed? */
56
FIELD(TB_FLAGS, HLSX, 15, 1)
57
FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
58
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/cpu_helper.c
61
+++ b/target/riscv/cpu_helper.c
62
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
63
}
64
65
#ifdef CONFIG_USER_ONLY
66
- flags |= TB_FLAGS_MSTATUS_FS;
67
- flags |= TB_FLAGS_MSTATUS_VS;
68
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
69
+ flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
70
#else
71
flags |= cpu_mmu_index(env, 0);
72
if (riscv_cpu_fp_enabled(env)) {
73
- flags |= env->mstatus & MSTATUS_FS;
74
+ flags = FIELD_DP32(flags, TB_FLAGS, FS,
75
+ get_field(env->mstatus, MSTATUS_FS));
76
}
77
-
78
if (riscv_cpu_vector_enabled(env)) {
79
- flags |= env->mstatus & MSTATUS_VS;
80
+ flags = FIELD_DP32(flags, TB_FLAGS, VS,
81
+ get_field(env->mstatus, MSTATUS_VS));
82
}
83
84
if (riscv_has_ext(env, RVH)) {
85
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/target/riscv/translate.c
88
+++ b/target/riscv/translate.c
89
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
90
RISCVMXL xl;
91
uint32_t misa_ext;
92
uint32_t opcode;
93
- uint32_t mstatus_fs;
94
- uint32_t mstatus_vs;
95
- uint32_t mstatus_hs_fs;
96
- uint32_t mstatus_hs_vs;
97
+ RISCVExtStatus mstatus_fs;
98
+ RISCVExtStatus mstatus_vs;
99
+ RISCVExtStatus mstatus_hs_fs;
100
+ RISCVExtStatus mstatus_hs_vs;
101
uint32_t mem_idx;
102
/*
103
* Remember the rounding mode encoded in the previous fp instruction,
104
@@ -XXX,XX +XXX,XX @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
105
106
#ifndef CONFIG_USER_ONLY
107
/*
108
- * The states of mstatus_fs are:
109
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
110
* We will have already diagnosed disabled state,
111
* and need to turn initial/clean into dirty.
112
*/
113
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
114
return;
115
}
116
117
- if (ctx->mstatus_fs != MSTATUS_FS) {
118
+ if (ctx->mstatus_fs != EXT_STATUS_DIRTY) {
119
/* Remember the state change for the rest of the TB. */
120
- ctx->mstatus_fs = MSTATUS_FS;
121
+ ctx->mstatus_fs = EXT_STATUS_DIRTY;
122
123
tmp = tcg_temp_new();
124
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
125
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
126
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
127
}
128
129
- if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
130
+ if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {
131
/* Remember the stage change for the rest of the TB. */
132
- ctx->mstatus_hs_fs = MSTATUS_FS;
133
+ ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
134
135
tmp = tcg_temp_new();
136
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
137
@@ -XXX,XX +XXX,XX @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
138
139
#ifndef CONFIG_USER_ONLY
140
/*
141
- * The states of mstatus_vs are:
142
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
143
* We will have already diagnosed disabled state,
144
* and need to turn initial/clean into dirty.
145
*/
146
@@ -XXX,XX +XXX,XX @@ static void mark_vs_dirty(DisasContext *ctx)
147
{
148
TCGv tmp;
149
150
- if (ctx->mstatus_vs != MSTATUS_VS) {
151
+ if (ctx->mstatus_vs != EXT_STATUS_DIRTY) {
152
/* Remember the state change for the rest of the TB. */
153
- ctx->mstatus_vs = MSTATUS_VS;
154
+ ctx->mstatus_vs = EXT_STATUS_DIRTY;
155
156
tmp = tcg_temp_new();
157
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
158
@@ -XXX,XX +XXX,XX @@ static void mark_vs_dirty(DisasContext *ctx)
159
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
160
}
161
162
- if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
163
+ if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {
164
/* Remember the stage change for the rest of the TB. */
165
- ctx->mstatus_hs_vs = MSTATUS_VS;
166
+ ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
167
168
tmp = tcg_temp_new();
169
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
170
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
171
172
ctx->pc_succ_insn = ctx->base.pc_first;
173
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
174
- ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
175
- ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
176
+ ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
177
+ ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
178
ctx->priv_ver = env->priv_ver;
179
ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
180
ctx->misa_ext = env->misa_ext;
181
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/riscv/insn_trans/trans_rvf.c.inc
184
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
185
@@ -XXX,XX +XXX,XX @@
186
*/
187
188
#define REQUIRE_FPU do {\
189
- if (ctx->mstatus_fs == 0) \
190
+ if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \
191
if (!ctx->cfg_ptr->ext_zfinx) \
192
return false; \
193
} while (0)
194
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
195
index XXXXXXX..XXXXXXX 100644
196
--- a/target/riscv/insn_trans/trans_rvv.c.inc
197
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
198
@@ -XXX,XX +XXX,XX @@ static inline bool is_overlapped(const int8_t astart, int8_t asize,
199
200
static bool require_rvv(DisasContext *s)
201
{
202
- return s->mstatus_vs != 0;
203
+ return s->mstatus_vs != EXT_STATUS_DISABLED;
204
}
205
206
static bool require_rvf(DisasContext *s)
207
{
208
- if (s->mstatus_fs == 0) {
209
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
210
return false;
211
}
212
213
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
214
215
static bool require_scale_rvf(DisasContext *s)
216
{
217
- if (s->mstatus_fs == 0) {
218
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
219
return false;
220
}
221
222
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
223
224
static bool require_scale_rvfmin(DisasContext *s)
225
{
226
- if (s->mstatus_fs == 0) {
227
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
228
return false;
229
}
230
231
--
232
2.40.0
diff view generated by jsdifflib
New patch
[PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Merge with mstatus_{fs,vs}. We might perform a redundant
4
assignment to one or the other field, but it's a trivial
5
and saves 4 bits from TB_FLAGS.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org>
13
Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu.h | 16 +++++++---------
17
target/riscv/cpu_helper.c | 33 ++++++++++++++++-----------------
18
target/riscv/translate.c | 32 ++++++++++----------------------
19
3 files changed, 33 insertions(+), 48 deletions(-)
20
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
26
FIELD(TB_FLAGS, VILL, 14, 1)
27
/* Is a Hypervisor instruction load/store allowed? */
28
FIELD(TB_FLAGS, HLSX, 15, 1)
29
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
30
-FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
31
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
32
-FIELD(TB_FLAGS, XL, 20, 2)
33
+FIELD(TB_FLAGS, XL, 16, 2)
34
/* If PointerMasking should be applied */
35
-FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
36
-FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
37
-FIELD(TB_FLAGS, VTA, 24, 1)
38
-FIELD(TB_FLAGS, VMA, 25, 1)
39
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
40
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
41
+FIELD(TB_FLAGS, VTA, 20, 1)
42
+FIELD(TB_FLAGS, VMA, 21, 1)
43
/* Native debug itrigger */
44
-FIELD(TB_FLAGS, ITRIGGER, 26, 1)
45
+FIELD(TB_FLAGS, ITRIGGER, 22, 1)
46
/* Virtual mode enabled */
47
-FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
48
+FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
49
50
#ifdef TARGET_RISCV32
51
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
52
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/riscv/cpu_helper.c
55
+++ b/target/riscv/cpu_helper.c
56
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
57
{
58
CPUState *cs = env_cpu(env);
59
RISCVCPU *cpu = RISCV_CPU(cs);
60
-
61
+ RISCVExtStatus fs, vs;
62
uint32_t flags = 0;
63
64
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
65
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
66
}
67
68
#ifdef CONFIG_USER_ONLY
69
- flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
70
- flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
71
+ fs = EXT_STATUS_DIRTY;
72
+ vs = EXT_STATUS_DIRTY;
73
#else
74
flags |= cpu_mmu_index(env, 0);
75
- if (riscv_cpu_fp_enabled(env)) {
76
- flags = FIELD_DP32(flags, TB_FLAGS, FS,
77
- get_field(env->mstatus, MSTATUS_FS));
78
- }
79
- if (riscv_cpu_vector_enabled(env)) {
80
- flags = FIELD_DP32(flags, TB_FLAGS, VS,
81
- get_field(env->mstatus, MSTATUS_VS));
82
- }
83
+ fs = get_field(env->mstatus, MSTATUS_FS);
84
+ vs = get_field(env->mstatus, MSTATUS_VS);
85
86
if (riscv_has_ext(env, RVH)) {
87
if (env->priv == PRV_M ||
88
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
89
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
90
}
91
92
- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
93
- get_field(env->mstatus_hs, MSTATUS_FS));
94
-
95
- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
96
- get_field(env->mstatus_hs, MSTATUS_VS));
97
- flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled);
98
+ if (env->virt_enabled) {
99
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
100
+ /*
101
+ * Merge DISABLED and !DIRTY states using MIN.
102
+ * We will set both fields when dirtying.
103
+ */
104
+ fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
105
+ vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
106
+ }
107
}
108
if (cpu->cfg.debug && !icount_enabled()) {
109
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
110
}
111
#endif
112
113
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
114
+ flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
115
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
116
if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
117
flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
118
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/translate.c
121
+++ b/target/riscv/translate.c
122
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
123
uint32_t opcode;
124
RISCVExtStatus mstatus_fs;
125
RISCVExtStatus mstatus_vs;
126
- RISCVExtStatus mstatus_hs_fs;
127
- RISCVExtStatus mstatus_hs_vs;
128
uint32_t mem_idx;
129
/*
130
* Remember the rounding mode encoded in the previous fp instruction,
131
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
132
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
133
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
134
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
135
- }
136
-
137
- if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {
138
- /* Remember the stage change for the rest of the TB. */
139
- ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
140
141
- tmp = tcg_temp_new();
142
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
143
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
144
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
145
+ if (ctx->virt_enabled) {
146
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
147
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
148
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
149
+ }
150
}
151
}
152
#else
153
@@ -XXX,XX +XXX,XX @@ static void mark_vs_dirty(DisasContext *ctx)
154
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
155
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
156
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
157
- }
158
-
159
- if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {
160
- /* Remember the stage change for the rest of the TB. */
161
- ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
162
163
- tmp = tcg_temp_new();
164
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
165
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
166
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
167
+ if (ctx->virt_enabled) {
168
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
169
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
170
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
171
+ }
172
}
173
}
174
#else
175
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
176
ctx->misa_ext = env->misa_ext;
177
ctx->frm = -1; /* unknown rounding mode */
178
ctx->cfg_ptr = &(cpu->cfg);
179
- ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
180
- ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
181
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
182
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
183
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
184
--
185
2.40.0
diff view generated by jsdifflib
New patch
[PULL 62/89] target/riscv: Add a tb flags field for vstart
1
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
1
2
3
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
4
a constant, we should record it in the tb flags if we want to use
5
it in translation.
6
7
Reported-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org>
15
Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.h | 1 +
19
target/riscv/cpu_helper.c | 1 +
20
target/riscv/translate.c | 4 ++--
21
target/riscv/insn_trans/trans_rvv.c.inc | 14 +++++++-------
22
4 files changed, 11 insertions(+), 9 deletions(-)
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VMA, 21, 1)
29
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
30
/* Virtual mode enabled */
31
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
32
+FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
33
34
#ifdef TARGET_RISCV32
35
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
36
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu_helper.c
39
+++ b/target/riscv/cpu_helper.c
40
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
41
FIELD_EX64(env->vtype, VTYPE, VTA));
42
flags = FIELD_DP32(flags, TB_FLAGS, VMA,
43
FIELD_EX64(env->vtype, VTYPE, VMA));
44
+ flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
45
} else {
46
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
47
}
48
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/translate.c
51
+++ b/target/riscv/translate.c
52
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
53
uint8_t vta;
54
uint8_t vma;
55
bool cfg_vta_all_1s;
56
- target_ulong vstart;
57
+ bool vstart_eq_zero;
58
bool vl_eq_vlmax;
59
CPUState *cs;
60
TCGv zero;
61
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
62
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
63
ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
64
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
65
- ctx->vstart = env->vstart;
66
+ ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
67
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
68
ctx->misa_mxl_max = env->misa_mxl_max;
69
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
70
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/riscv/insn_trans/trans_rvv.c.inc
73
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
74
@@ -XXX,XX +XXX,XX @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
75
*/
76
static bool vext_check_reduction(DisasContext *s, int vs2)
77
{
78
- return require_align(vs2, s->lmul) && (s->vstart == 0);
79
+ return require_align(vs2, s->lmul) && s->vstart_eq_zero;
80
}
81
82
/*
83
@@ -XXX,XX +XXX,XX @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
84
{
85
if (require_rvv(s) &&
86
vext_check_isa_ill(s) &&
87
- s->vstart == 0) {
88
+ s->vstart_eq_zero) {
89
TCGv_ptr src2, mask;
90
TCGv dst;
91
TCGv_i32 desc;
92
@@ -XXX,XX +XXX,XX @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
93
{
94
if (require_rvv(s) &&
95
vext_check_isa_ill(s) &&
96
- s->vstart == 0) {
97
+ s->vstart_eq_zero) {
98
TCGv_ptr src2, mask;
99
TCGv dst;
100
TCGv_i32 desc;
101
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
102
vext_check_isa_ill(s) && \
103
require_vm(a->vm, a->rd) && \
104
(a->rd != a->rs2) && \
105
- (s->vstart == 0)) { \
106
+ s->vstart_eq_zero) { \
107
uint32_t data = 0; \
108
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
109
TCGLabel *over = gen_new_label(); \
110
@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
111
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
112
require_vm(a->vm, a->rd) &&
113
require_align(a->rd, s->lmul) &&
114
- (s->vstart == 0)) {
115
+ s->vstart_eq_zero) {
116
uint32_t data = 0;
117
TCGLabel *over = gen_new_label();
118
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
119
@@ -XXX,XX +XXX,XX @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a)
120
require_align(a->rs2, s->lmul) &&
121
(a->rd != a->rs2) &&
122
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) &&
123
- (s->vstart == 0);
124
+ s->vstart_eq_zero;
125
}
126
127
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
128
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
129
QEMU_IS_ALIGNED(a->rd, LEN) && \
130
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
131
uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
132
- if (s->vstart == 0) { \
133
+ if (s->vstart_eq_zero) { \
134
/* EEW = 8 */ \
135
tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
136
vreg_ofs(s, a->rs2), maxsz, maxsz); \
137
--
138
2.40.0
diff view generated by jsdifflib
New patch
[PULL 63/89] target/riscv: Separate priv from mmu_idx
1
From: Fei Wu <fei2.wu@intel.com>
1
2
3
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
4
this assumption won't last as we are about to add more mmu_idx. Here an
5
individual priv field is added into TB_FLAGS.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Fei Wu <fei2.wu@intel.com>
9
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
10
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
13
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
15
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.h | 2 +-
19
target/riscv/cpu_helper.c | 4 +++-
20
target/riscv/translate.c | 2 ++
21
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
22
target/riscv/insn_trans/trans_xthead.c.inc | 14 +-------------
23
5 files changed, 8 insertions(+), 16 deletions(-)
24
25
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu.h
28
+++ b/target/riscv/cpu.h
29
@@ -XXX,XX +XXX,XX @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
30
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
31
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
32
33
-#define TB_FLAGS_PRIV_MMU_MASK 3
34
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
35
36
#include "exec/cpu-all.h"
37
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1)
38
/* Virtual mode enabled */
39
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
40
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
41
+FIELD(TB_FLAGS, PRIV, 25, 2)
42
43
#ifdef TARGET_RISCV32
44
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
45
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/riscv/cpu_helper.c
48
+++ b/target/riscv/cpu_helper.c
49
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
50
fs = EXT_STATUS_DIRTY;
51
vs = EXT_STATUS_DIRTY;
52
#else
53
+ flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
54
+
55
flags |= cpu_mmu_index(env, 0);
56
fs = get_field(env->mstatus, MSTATUS_FS);
57
vs = get_field(env->mstatus, MSTATUS_VS);
58
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
59
*/
60
MemTxResult res;
61
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
62
- int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
63
+ int mode = env->priv;
64
bool use_background = false;
65
hwaddr ppn;
66
int napot_bits = 0;
67
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/riscv/translate.c
70
+++ b/target/riscv/translate.c
71
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
72
RISCVExtStatus mstatus_fs;
73
RISCVExtStatus mstatus_vs;
74
uint32_t mem_idx;
75
+ uint32_t priv;
76
/*
77
* Remember the rounding mode encoded in the previous fp instruction,
78
* which we have already installed into env->fp_status. Or -1 for
79
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
80
uint32_t tb_flags = ctx->base.tb->flags;
81
82
ctx->pc_succ_insn = ctx->base.pc_first;
83
+ ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
84
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
85
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
86
ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
87
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/riscv/insn_trans/trans_privileged.c.inc
90
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
91
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
92
* that no exception will be raised when fetching them.
93
*/
94
95
- if (semihosting_enabled(ctx->mem_idx < PRV_S) &&
96
+ if (semihosting_enabled(ctx->priv == PRV_U) &&
97
(pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
98
pre = opcode_at(&ctx->base, pre_addr);
99
ebreak = opcode_at(&ctx->base, ebreak_addr);
100
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/riscv/insn_trans/trans_xthead.c.inc
103
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
104
@@ -XXX,XX +XXX,XX @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
105
106
/* XTheadCmo */
107
108
-static inline int priv_level(DisasContext *ctx)
109
-{
110
-#ifdef CONFIG_USER_ONLY
111
- return PRV_U;
112
-#else
113
- /* Priv level is part of mem_idx. */
114
- return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
115
-#endif
116
-}
117
-
118
/* Test if priv level is M, S, or U (cannot fail). */
119
#define REQUIRE_PRIV_MSU(ctx)
120
121
/* Test if priv level is M or S. */
122
#define REQUIRE_PRIV_MS(ctx) \
123
do { \
124
- int priv = priv_level(ctx); \
125
- if (!(priv == PRV_M || \
126
- priv == PRV_S)) { \
127
+ if (ctx->priv == PRV_U) { \
128
return false; \
129
} \
130
} while (0)
131
--
132
2.40.0
diff view generated by jsdifflib
New patch
[PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change
1
From: Fei Wu <fei2.wu@intel.com>
1
2
3
Kernel needs to access user mode memory e.g. during syscalls, the window
4
is usually opened up for a very limited time through MSTATUS.SUM, the
5
overhead is too much if tlb_flush() gets called for every SUM change.
6
7
This patch creates a separate MMU index for S+SUM, so that it's not
8
necessary to flush tlb anymore when SUM changes. This is similar to how
9
ARM handles Privileged Access Never (PAN).
10
11
Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
12
other syscalls benefit a lot from this too.
13
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Fei Wu <fei2.wu@intel.com>
16
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com>
17
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
18
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
19
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
20
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org>
22
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org>
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
25
target/riscv/cpu.h | 2 --
26
target/riscv/internals.h | 14 ++++++++++++++
27
target/riscv/cpu_helper.c | 17 +++++++++++++++--
28
target/riscv/csr.c | 3 +--
29
target/riscv/op_helper.c | 5 +++--
30
target/riscv/insn_trans/trans_rvh.c.inc | 4 ++--
31
6 files changed, 35 insertions(+), 10 deletions(-)
32
33
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.h
36
+++ b/target/riscv/cpu.h
37
@@ -XXX,XX +XXX,XX @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
38
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
39
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
40
41
-#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
42
-
43
#include "exec/cpu-all.h"
44
45
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
46
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/internals.h
49
+++ b/target/riscv/internals.h
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "hw/registerfields.h"
53
54
+/*
55
+ * The current MMU Modes are:
56
+ * - U 0b000
57
+ * - S 0b001
58
+ * - S+SUM 0b010
59
+ * - M 0b011
60
+ * - HLV/HLVX/HSV adds 0b100
61
+ */
62
+#define MMUIdx_U 0
63
+#define MMUIdx_S 1
64
+#define MMUIdx_S_SUM 2
65
+#define MMUIdx_M 3
66
+#define MMU_HYP_ACCESS_BIT (1 << 2)
67
+
68
/* share data between vector helpers and decode code */
69
FIELD(VDATA, VM, 0, 1)
70
FIELD(VDATA, LMUL, 1, 3)
71
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/riscv/cpu_helper.c
74
+++ b/target/riscv/cpu_helper.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu/log.h"
77
#include "qemu/main-loop.h"
78
#include "cpu.h"
79
+#include "internals.h"
80
#include "pmu.h"
81
#include "exec/exec-all.h"
82
#include "instmap.h"
83
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
84
#ifdef CONFIG_USER_ONLY
85
return 0;
86
#else
87
- return env->priv;
88
+ if (ifetch) {
89
+ return env->priv;
90
+ }
91
+
92
+ /* All priv -> mmu_idx mapping are here */
93
+ int mode = env->priv;
94
+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
95
+ mode = get_field(env->mstatus, MSTATUS_MPP);
96
+ }
97
+ if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
98
+ return MMUIdx_S_SUM;
99
+ }
100
+ return mode;
101
#endif
102
}
103
104
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
105
106
bool riscv_cpu_two_stage_lookup(int mmu_idx)
107
{
108
- return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
109
+ return mmu_idx & MMU_HYP_ACCESS_BIT;
110
}
111
112
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
113
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/riscv/csr.c
116
+++ b/target/riscv/csr.c
117
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
118
val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
119
120
/* flush tlb on mstatus fields that affect VM */
121
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
122
- MSTATUS_MPRV | MSTATUS_SUM)) {
123
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
124
tlb_flush(env_cpu(env));
125
}
126
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
127
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/riscv/op_helper.c
130
+++ b/target/riscv/op_helper.c
131
@@ -XXX,XX +XXX,XX @@
132
133
#include "qemu/osdep.h"
134
#include "cpu.h"
135
+#include "internals.h"
136
#include "qemu/main-loop.h"
137
#include "exec/exec-all.h"
138
#include "exec/helper-proto.h"
139
@@ -XXX,XX +XXX,XX @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
140
141
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
142
{
143
- int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
144
+ int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
145
146
return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
147
}
148
149
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
150
{
151
- int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
152
+ int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
153
154
return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
155
}
156
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
157
index XXXXXXX..XXXXXXX 100644
158
--- a/target/riscv/insn_trans/trans_rvh.c.inc
159
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
160
@@ -XXX,XX +XXX,XX @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
161
if (check_access(ctx)) {
162
TCGv dest = dest_gpr(ctx, a->rd);
163
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
164
- int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
165
+ int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
166
tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
167
gen_set_gpr(ctx, a->rd, dest);
168
}
169
@@ -XXX,XX +XXX,XX @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
170
if (check_access(ctx)) {
171
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
172
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
173
- int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
174
+ int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
175
tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
176
}
177
return true;
178
--
179
2.40.0
diff view generated by jsdifflib
New patch
[PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use the new functions to properly check execute permission
4
for the read rather than read permission.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/op_helper.c | 13 +++++++++++--
15
1 file changed, 11 insertions(+), 2 deletions(-)
16
17
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/op_helper.c
20
+++ b/target/riscv/op_helper.c
21
@@ -XXX,XX +XXX,XX @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
22
helper_hyp_tlb_flush(env);
23
}
24
25
+/*
26
+ * TODO: These implementations are not quite correct. They perform the
27
+ * access using execute permission just fine, but the final PMP check
28
+ * is supposed to have read permission as well. Without replicating
29
+ * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
30
+ * which would imply that exact check in tlb_fill.
31
+ */
32
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
33
{
34
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
35
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
36
37
- return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
38
+ return cpu_ldw_code_mmu(env, address, oi, GETPC());
39
}
40
41
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
42
{
43
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
44
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
45
46
- return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
47
+ return cpu_ldl_code_mmu(env, address, oi, GETPC());
48
}
49
50
#endif /* !CONFIG_USER_ONLY */
51
--
52
2.40.0
diff view generated by jsdifflib
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
[PULL 66/89] target/riscv: Handle HLV, HSV via helpers
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
3
Implement these instructions via helpers, in expectation
4
further compressed instruction decoding. However, prior to this change,
4
of determining the mmu_idx to use at runtime. This allows
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
5
the permission check to also be moved out of line, which
6
fails to decode the instruction. This means that we skipped illegal
6
allows HLSX to be removed from TB_FLAGS.
7
compressed instructions instead of raising an illegal instruction
8
exception.
9
7
10
Instead of patching decode_RV32_64C(), we can just remove it,
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
as it is dead code since f330433b363 anyway.
12
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
11
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org>
13
Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
15
---
19
target/riscv/translate.c | 179 +--------------------------------------
16
target/riscv/cpu.h | 6 +-
20
1 file changed, 1 insertion(+), 178 deletions(-)
17
target/riscv/helper.h | 12 ++-
18
target/riscv/cpu_helper.c | 26 ++---
19
target/riscv/op_helper.c | 99 ++++++++++++++++--
20
target/riscv/translate.c | 2 -
21
target/riscv/insn_trans/trans_rvh.c.inc | 129 ++++++++++--------------
22
6 files changed, 165 insertions(+), 109 deletions(-)
21
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, LMUL, 7, 3)
29
FIELD(TB_FLAGS, SEW, 10, 3)
30
FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
31
FIELD(TB_FLAGS, VILL, 14, 1)
32
-/* Is a Hypervisor instruction load/store allowed? */
33
-FIELD(TB_FLAGS, HLSX, 15, 1)
34
+FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
35
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
36
FIELD(TB_FLAGS, XL, 16, 2)
37
/* If PointerMasking should be applied */
38
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VMA, 21, 1)
39
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
40
/* Virtual mode enabled */
41
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
42
-FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
43
-FIELD(TB_FLAGS, PRIV, 25, 2)
44
+FIELD(TB_FLAGS, PRIV, 24, 2)
45
46
#ifdef TARGET_RISCV32
47
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
48
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/helper.h
51
+++ b/target/riscv/helper.h
52
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(itrigger_match, void, env)
53
#ifndef CONFIG_USER_ONLY
54
DEF_HELPER_1(hyp_tlb_flush, void, env)
55
DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
56
-DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl)
57
-DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
58
+DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl)
59
+DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl)
60
+DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl)
61
+DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl)
62
+DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl)
63
+DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl)
64
+DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl)
65
+DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl)
66
+DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl)
67
+DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl)
68
#endif
69
70
/* Vector functions */
71
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/riscv/cpu_helper.c
74
+++ b/target/riscv/cpu_helper.c
75
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
76
fs = get_field(env->mstatus, MSTATUS_FS);
77
vs = get_field(env->mstatus, MSTATUS_VS);
78
79
- if (riscv_has_ext(env, RVH)) {
80
- if (env->priv == PRV_M ||
81
- (env->priv == PRV_S && !env->virt_enabled) ||
82
- (env->priv == PRV_U && !env->virt_enabled &&
83
- get_field(env->hstatus, HSTATUS_HU))) {
84
- flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
85
- }
86
-
87
- if (env->virt_enabled) {
88
- flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
89
- /*
90
- * Merge DISABLED and !DIRTY states using MIN.
91
- * We will set both fields when dirtying.
92
- */
93
- fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
94
- vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
95
- }
96
+ if (env->virt_enabled) {
97
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
98
+ /*
99
+ * Merge DISABLED and !DIRTY states using MIN.
100
+ * We will set both fields when dirtying.
101
+ */
102
+ fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
103
+ vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
104
}
105
+
106
if (cpu->cfg.debug && !icount_enabled()) {
107
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
108
}
109
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/riscv/op_helper.c
112
+++ b/target/riscv/op_helper.c
113
@@ -XXX,XX +XXX,XX @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
114
helper_hyp_tlb_flush(env);
115
}
116
117
+static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
118
+{
119
+ if (env->priv == PRV_M) {
120
+ /* always allowed */
121
+ } else if (env->virt_enabled) {
122
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
123
+ } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) {
124
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
125
+ }
126
+
127
+ return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
128
+}
129
+
130
+target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
131
+{
132
+ uintptr_t ra = GETPC();
133
+ int mmu_idx = check_access_hlsv(env, false, ra);
134
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
135
+
136
+ return cpu_ldb_mmu(env, addr, oi, ra);
137
+}
138
+
139
+target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr)
140
+{
141
+ uintptr_t ra = GETPC();
142
+ int mmu_idx = check_access_hlsv(env, false, ra);
143
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
144
+
145
+ return cpu_ldw_mmu(env, addr, oi, ra);
146
+}
147
+
148
+target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr)
149
+{
150
+ uintptr_t ra = GETPC();
151
+ int mmu_idx = check_access_hlsv(env, false, ra);
152
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
153
+
154
+ return cpu_ldl_mmu(env, addr, oi, ra);
155
+}
156
+
157
+target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr)
158
+{
159
+ uintptr_t ra = GETPC();
160
+ int mmu_idx = check_access_hlsv(env, false, ra);
161
+ MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx);
162
+
163
+ return cpu_ldq_mmu(env, addr, oi, ra);
164
+}
165
+
166
+void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val)
167
+{
168
+ uintptr_t ra = GETPC();
169
+ int mmu_idx = check_access_hlsv(env, false, ra);
170
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
171
+
172
+ cpu_stb_mmu(env, addr, val, oi, ra);
173
+}
174
+
175
+void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val)
176
+{
177
+ uintptr_t ra = GETPC();
178
+ int mmu_idx = check_access_hlsv(env, false, ra);
179
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
180
+
181
+ cpu_stw_mmu(env, addr, val, oi, ra);
182
+}
183
+
184
+void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val)
185
+{
186
+ uintptr_t ra = GETPC();
187
+ int mmu_idx = check_access_hlsv(env, false, ra);
188
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
189
+
190
+ cpu_stl_mmu(env, addr, val, oi, ra);
191
+}
192
+
193
+void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val)
194
+{
195
+ uintptr_t ra = GETPC();
196
+ int mmu_idx = check_access_hlsv(env, false, ra);
197
+ MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx);
198
+
199
+ cpu_stq_mmu(env, addr, val, oi, ra);
200
+}
201
+
202
/*
203
* TODO: These implementations are not quite correct. They perform the
204
* access using execute permission just fine, but the final PMP check
205
@@ -XXX,XX +XXX,XX @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
206
* a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
207
* which would imply that exact check in tlb_fill.
208
*/
209
-target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
210
+target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr)
211
{
212
- int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
213
+ uintptr_t ra = GETPC();
214
+ int mmu_idx = check_access_hlsv(env, true, ra);
215
MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
216
217
- return cpu_ldw_code_mmu(env, address, oi, GETPC());
218
+ return cpu_ldw_code_mmu(env, addr, oi, GETPC());
219
}
220
221
-target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
222
+target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr)
223
{
224
- int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
225
+ uintptr_t ra = GETPC();
226
+ int mmu_idx = check_access_hlsv(env, true, ra);
227
MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
228
229
- return cpu_ldl_code_mmu(env, address, oi, GETPC());
230
+ return cpu_ldl_code_mmu(env, addr, oi, ra);
231
}
232
233
#endif /* !CONFIG_USER_ONLY */
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
234
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
23
index XXXXXXX..XXXXXXX 100644
235
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
236
--- a/target/riscv/translate.c
25
+++ b/target/riscv/translate.c
237
+++ b/target/riscv/translate.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
238
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
27
CPUState *cs;
239
bool virt_inst_excp;
28
} DisasContext;
240
bool virt_enabled;
29
241
const RISCVCPUConfig *cfg_ptr;
30
-#ifdef TARGET_RISCV64
242
- bool hlsx;
31
-/* convert riscv funct3 to qemu memop for load/store */
243
/* vector extension */
32
-static const int tcg_memop_lookup[8] = {
244
bool vill;
33
- [0 ... 7] = -1,
245
/*
34
- [0] = MO_SB,
246
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
35
- [1] = MO_TESW,
247
ctx->misa_ext = env->misa_ext;
36
- [2] = MO_TESL,
248
ctx->frm = -1; /* unknown rounding mode */
37
- [3] = MO_TEQ,
249
ctx->cfg_ptr = &(cpu->cfg);
38
- [4] = MO_UB,
250
- ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
39
- [5] = MO_TEUW,
251
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
40
- [6] = MO_TEUL,
252
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
41
-};
253
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
42
-#endif
254
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
43
-
255
index XXXXXXX..XXXXXXX 100644
44
#ifdef TARGET_RISCV64
256
--- a/target/riscv/insn_trans/trans_rvh.c.inc
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
257
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
46
#else
258
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
259
* this program. If not, see <http://www.gnu.org/licenses/>.
48
ctx->base.is_jmp = DISAS_NORETURN;
260
*/
49
}
261
50
262
-#ifndef CONFIG_USER_ONLY
51
-#ifdef TARGET_RISCV64
263
-static bool check_access(DisasContext *ctx)
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
53
- target_long imm)
54
-{
264
-{
55
- TCGv t0 = tcg_temp_new();
265
- if (!ctx->hlsx) {
56
- TCGv t1 = tcg_temp_new();
266
- tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
57
- gen_get_gpr(t0, rs1);
267
- offsetof(CPURISCVState, bins));
58
- tcg_gen_addi_tl(t0, t0, imm);
268
- if (ctx->virt_enabled) {
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
269
- generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
60
-
270
- } else {
61
- if (memop < 0) {
271
- generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
62
- gen_exception_illegal(ctx);
272
- }
63
- return;
273
- return false;
64
- }
274
- }
65
-
275
+#ifdef CONFIG_USER_ONLY
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
276
+#define do_hlv(ctx, a, func) false
67
- gen_set_gpr(rd, t1);
277
+#define do_hsv(ctx, a, func) false
68
- tcg_temp_free(t0);
278
+#else
69
- tcg_temp_free(t1);
279
+static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a)
280
+{
281
+ gen_helper_hyp_hlv_bu(r, e, a);
282
+ tcg_gen_ext8s_tl(r, r);
283
+}
284
+
285
+static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a)
286
+{
287
+ gen_helper_hyp_hlv_hu(r, e, a);
288
+ tcg_gen_ext16s_tl(r, r);
289
+}
290
+
291
+static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a)
292
+{
293
+ gen_helper_hyp_hlv_wu(r, e, a);
294
+ tcg_gen_ext32s_tl(r, r);
295
+}
296
+
297
+static bool do_hlv(DisasContext *ctx, arg_r2 *a,
298
+ void (*func)(TCGv, TCGv_env, TCGv))
299
+{
300
+ TCGv dest = dest_gpr(ctx, a->rd);
301
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
302
+
303
+ decode_save_opc(ctx);
304
+ func(dest, cpu_env, addr);
305
+ gen_set_gpr(ctx, a->rd, dest);
306
return true;
307
}
308
-#endif
309
310
-static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
311
+static bool do_hsv(DisasContext *ctx, arg_r2_s *a,
312
+ void (*func)(TCGv_env, TCGv, TCGv))
313
{
314
-#ifdef CONFIG_USER_ONLY
315
- return false;
316
-#else
317
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
318
+ TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
319
+
320
decode_save_opc(ctx);
321
- if (check_access(ctx)) {
322
- TCGv dest = dest_gpr(ctx, a->rd);
323
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
324
- int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
325
- tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
326
- gen_set_gpr(ctx, a->rd, dest);
327
- }
328
+ func(cpu_env, addr, data);
329
return true;
330
-#endif
331
}
332
+#endif /* CONFIG_USER_ONLY */
333
334
static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
335
{
336
REQUIRE_EXT(ctx, RVH);
337
- return do_hlv(ctx, a, MO_SB);
338
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_b);
339
}
340
341
static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
342
{
343
REQUIRE_EXT(ctx, RVH);
344
- return do_hlv(ctx, a, MO_TESW);
345
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_h);
346
}
347
348
static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
349
{
350
REQUIRE_EXT(ctx, RVH);
351
- return do_hlv(ctx, a, MO_TESL);
352
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_w);
353
}
354
355
static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
356
{
357
REQUIRE_EXT(ctx, RVH);
358
- return do_hlv(ctx, a, MO_UB);
359
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_bu);
360
}
361
362
static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
363
{
364
REQUIRE_EXT(ctx, RVH);
365
- return do_hlv(ctx, a, MO_TEUW);
70
-}
366
-}
71
-
367
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
368
-static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
73
- target_long imm)
74
-{
369
-{
75
- TCGv t0 = tcg_temp_new();
370
-#ifdef CONFIG_USER_ONLY
76
- TCGv dat = tcg_temp_new();
371
- return false;
77
- gen_get_gpr(t0, rs1);
372
-#else
78
- tcg_gen_addi_tl(t0, t0, imm);
373
- decode_save_opc(ctx);
79
- gen_get_gpr(dat, rs2);
374
- if (check_access(ctx)) {
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
375
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
81
-
376
- TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
82
- if (memop < 0) {
377
- int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
83
- gen_exception_illegal(ctx);
378
- tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
84
- return;
85
- }
379
- }
86
-
380
- return true;
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
381
-#endif
88
- tcg_temp_free(t0);
382
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_hu);
89
- tcg_temp_free(dat);
383
}
90
-}
384
91
-#endif
385
static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
92
-
386
{
93
#ifndef CONFIG_USER_ONLY
387
REQUIRE_EXT(ctx, RVH);
94
/* The states of mstatus_fs are:
388
- return do_hsv(ctx, a, MO_SB);
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
389
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_b);
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
390
}
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
391
98
#endif
392
static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
99
393
{
100
-#if !defined(TARGET_RISCV64)
394
REQUIRE_EXT(ctx, RVH);
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
395
- return do_hsv(ctx, a, MO_TESW);
102
- int rs1, target_long imm)
396
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_h);
103
-{
397
}
104
- TCGv t0;
398
105
-
399
static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
106
- if (ctx->mstatus_fs == 0) {
400
{
107
- gen_exception_illegal(ctx);
401
REQUIRE_EXT(ctx, RVH);
108
- return;
402
- return do_hsv(ctx, a, MO_TESL);
109
- }
403
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_w);
110
-
404
}
111
- t0 = tcg_temp_new();
405
112
- gen_get_gpr(t0, rs1);
406
static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
113
- tcg_gen_addi_tl(t0, t0, imm);
407
{
114
-
408
REQUIRE_64BIT(ctx);
115
- switch (opc) {
409
REQUIRE_EXT(ctx, RVH);
116
- case OPC_RISC_FLW:
410
- return do_hlv(ctx, a, MO_TEUL);
117
- if (!has_ext(ctx, RVF)) {
411
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_wu);
118
- goto do_illegal;
412
}
119
- }
413
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
414
static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
415
{
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
416
REQUIRE_64BIT(ctx);
123
- break;
417
REQUIRE_EXT(ctx, RVH);
124
- case OPC_RISC_FLD:
418
- return do_hlv(ctx, a, MO_TEUQ);
125
- if (!has_ext(ctx, RVD)) {
419
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_d);
126
- goto do_illegal;
420
}
127
- }
421
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
422
static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
129
- break;
423
{
130
- do_illegal:
424
REQUIRE_64BIT(ctx);
131
- default:
425
REQUIRE_EXT(ctx, RVH);
132
- gen_exception_illegal(ctx);
426
- return do_hsv(ctx, a, MO_TEUQ);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
427
-}
139
-
428
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
429
-#ifndef CONFIG_USER_ONLY
141
- int rs2, target_long imm)
430
-static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
431
- void (*func)(TCGv, TCGv_env, TCGv))
142
-{
432
-{
143
- TCGv t0;
433
- decode_save_opc(ctx);
144
-
434
- if (check_access(ctx)) {
145
- if (ctx->mstatus_fs == 0) {
435
- TCGv dest = dest_gpr(ctx, a->rd);
146
- gen_exception_illegal(ctx);
436
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
147
- return;
437
- func(dest, cpu_env, addr);
438
- gen_set_gpr(ctx, a->rd, dest);
148
- }
439
- }
149
-
440
- return true;
150
- t0 = tcg_temp_new();
441
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_d);
151
- gen_get_gpr(t0, rs1);
442
}
152
- tcg_gen_addi_tl(t0, t0, imm);
443
-#endif
153
-
444
154
- switch (opc) {
445
static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
155
- case OPC_RISC_FSW:
446
{
156
- if (!has_ext(ctx, RVF)) {
447
REQUIRE_EXT(ctx, RVH);
157
- goto do_illegal;
448
-#ifndef CONFIG_USER_ONLY
158
- }
449
- return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu);
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
179
TCGv_i32 t0;
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
181
tcg_temp_free_i32(t0);
182
}
183
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
185
-{
186
- uint8_t funct3 = extract16(opcode, 13, 3);
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
188
- uint8_t rs1s = GET_C_RS1S(opcode);
189
-
190
- switch (funct3) {
191
- case 3:
192
-#if defined(TARGET_RISCV64)
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
195
- GET_C_LD_IMM(opcode));
196
-#else
450
-#else
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
451
- return false;
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
452
-#endif
199
- GET_C_LW_IMM(opcode));
453
+ return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu);
200
-#endif
454
}
201
- break;
455
202
- case 7:
456
static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
203
-#if defined(TARGET_RISCV64)
457
{
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
458
REQUIRE_EXT(ctx, RVH);
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
459
-#ifndef CONFIG_USER_ONLY
206
- GET_C_LD_IMM(opcode));
460
- return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu);
207
-#else
461
-#else
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
462
- return false;
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
463
-#endif
210
- GET_C_LW_IMM(opcode));
464
+ return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu);
211
-#endif
465
}
212
- break;
466
213
- }
467
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
214
-}
215
-
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
229
return nf + 1;
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
231
} else {
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
233
if (!decode_insn16(ctx, opcode)) {
234
- /* fall back to old decoder */
235
- decode_RV32_64C(ctx, opcode);
236
+ gen_exception_illegal(ctx);
237
}
238
}
239
} else {
240
--
468
--
241
2.30.1
469
2.40.0
242
243
diff view generated by jsdifflib
New patch
[PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We will enable more uses of this bit in the future.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org>
10
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/internals.h | 6 ++++--
14
target/riscv/cpu_helper.c | 2 +-
15
target/riscv/op_helper.c | 2 +-
16
3 files changed, 6 insertions(+), 4 deletions(-)
17
18
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/internals.h
21
+++ b/target/riscv/internals.h
22
@@ -XXX,XX +XXX,XX @@
23
* - S 0b001
24
* - S+SUM 0b010
25
* - M 0b011
26
- * - HLV/HLVX/HSV adds 0b100
27
+ * - U+2STAGE 0b100
28
+ * - S+2STAGE 0b101
29
+ * - S+SUM+2STAGE 0b110
30
*/
31
#define MMUIdx_U 0
32
#define MMUIdx_S 1
33
#define MMUIdx_S_SUM 2
34
#define MMUIdx_M 3
35
-#define MMU_HYP_ACCESS_BIT (1 << 2)
36
+#define MMU_2STAGE_BIT (1 << 2)
37
38
/* share data between vector helpers and decode code */
39
FIELD(VDATA, VM, 0, 1)
40
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/riscv/cpu_helper.c
43
+++ b/target/riscv/cpu_helper.c
44
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
45
46
bool riscv_cpu_two_stage_lookup(int mmu_idx)
47
{
48
- return mmu_idx & MMU_HYP_ACCESS_BIT;
49
+ return mmu_idx & MMU_2STAGE_BIT;
50
}
51
52
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
53
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/op_helper.c
56
+++ b/target/riscv/op_helper.c
57
@@ -XXX,XX +XXX,XX @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
58
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
59
}
60
61
- return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
62
+ return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
63
}
64
65
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
66
--
67
2.40.0
diff view generated by jsdifflib
New patch
[PULL 68/89] target/riscv: Introduce mmuidx_sum
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In get_physical_address, we should use the setting passed
4
via mmu_idx rather than checking env->mstatus directly.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/internals.h | 5 +++++
15
target/riscv/cpu_helper.c | 2 +-
16
2 files changed, 6 insertions(+), 1 deletion(-)
17
18
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/internals.h
21
+++ b/target/riscv/internals.h
22
@@ -XXX,XX +XXX,XX @@
23
#define MMUIdx_M 3
24
#define MMU_2STAGE_BIT (1 << 2)
25
26
+static inline bool mmuidx_sum(int mmu_idx)
27
+{
28
+ return (mmu_idx & 3) == MMUIdx_S_SUM;
29
+}
30
+
31
/* share data between vector helpers and decode code */
32
FIELD(VDATA, VM, 0, 1)
33
FIELD(VDATA, LMUL, 1, 3)
34
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu_helper.c
37
+++ b/target/riscv/cpu_helper.c
38
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
39
widened = 2;
40
}
41
/* status.SUM will be ignored if execute on background */
42
- sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
43
+ sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
44
switch (vm) {
45
case VM_1_10_SV32:
46
levels = 2; ptidxbits = 10; ptesize = 4; break;
47
--
48
2.40.0
diff view generated by jsdifflib
New patch
[PULL 69/89] target/riscv: Introduce mmuidx_priv
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use the priv level encoded into the mmu_idx, rather than
4
starting from env->priv. We have already checked MPRV+MPP
5
in riscv_cpu_mmu_index -- no need to repeat that.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org>
12
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/internals.h | 9 +++++++++
16
target/riscv/cpu_helper.c | 6 +-----
17
2 files changed, 10 insertions(+), 5 deletions(-)
18
19
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/internals.h
22
+++ b/target/riscv/internals.h
23
@@ -XXX,XX +XXX,XX @@
24
#define MMUIdx_M 3
25
#define MMU_2STAGE_BIT (1 << 2)
26
27
+static inline int mmuidx_priv(int mmu_idx)
28
+{
29
+ int ret = mmu_idx & 3;
30
+ if (ret == MMUIdx_S_SUM) {
31
+ ret = PRV_S;
32
+ }
33
+ return ret;
34
+}
35
+
36
static inline bool mmuidx_sum(int mmu_idx)
37
{
38
return (mmu_idx & 3) == MMUIdx_S_SUM;
39
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu_helper.c
42
+++ b/target/riscv/cpu_helper.c
43
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
44
*/
45
MemTxResult res;
46
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
47
- int mode = env->priv;
48
+ int mode = mmuidx_priv(mmu_idx);
49
bool use_background = false;
50
hwaddr ppn;
51
int napot_bits = 0;
52
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
53
*/
54
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
55
mode = get_field(env->hstatus, HSTATUS_SPVP);
56
- } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
57
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
58
- mode = get_field(env->mstatus, MSTATUS_MPP);
59
- }
60
}
61
62
if (first_stage == false) {
63
--
64
2.40.0
diff view generated by jsdifflib
New patch
[PULL 70/89] target/riscv: Introduce mmuidx_2stage
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Move and rename riscv_cpu_two_stage_lookup, to match
4
the other mmuidx_* functions.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu.h | 1 -
15
target/riscv/internals.h | 5 +++++
16
target/riscv/cpu_helper.c | 20 ++++++--------------
17
3 files changed, 11 insertions(+), 15 deletions(-)
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
24
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
25
bool riscv_cpu_vector_enabled(CPURISCVState *env);
26
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
27
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
28
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
29
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
30
MMUAccessType access_type,
31
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/internals.h
34
+++ b/target/riscv/internals.h
35
@@ -XXX,XX +XXX,XX @@ static inline bool mmuidx_sum(int mmu_idx)
36
return (mmu_idx & 3) == MMUIdx_S_SUM;
37
}
38
39
+static inline bool mmuidx_2stage(int mmu_idx)
40
+{
41
+ return mmu_idx & MMU_2STAGE_BIT;
42
+}
43
+
44
/* share data between vector helpers and decode code */
45
FIELD(VDATA, VM, 0, 1)
46
FIELD(VDATA, LMUL, 1, 3)
47
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/cpu_helper.c
50
+++ b/target/riscv/cpu_helper.c
51
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
52
}
53
}
54
55
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
56
-{
57
- return mmu_idx & MMU_2STAGE_BIT;
58
-}
59
-
60
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
61
{
62
CPURISCVState *env = &cpu->env;
63
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
64
* MPRV does not affect the virtual-machine load/store
65
* instructions, HLV, HLVX, and HSV.
66
*/
67
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
68
+ if (mmuidx_2stage(mmu_idx)) {
69
mode = get_field(env->hstatus, HSTATUS_SPVP);
70
}
71
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
73
}
74
75
env->badaddr = addr;
76
- env->two_stage_lookup = env->virt_enabled ||
77
- riscv_cpu_two_stage_lookup(mmu_idx);
78
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
79
env->two_stage_indirect_lookup = false;
80
cpu_loop_exit_restore(cs, retaddr);
81
}
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
83
g_assert_not_reached();
84
}
85
env->badaddr = addr;
86
- env->two_stage_lookup = env->virt_enabled ||
87
- riscv_cpu_two_stage_lookup(mmu_idx);
88
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
89
env->two_stage_indirect_lookup = false;
90
cpu_loop_exit_restore(cs, retaddr);
91
}
92
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
93
* MPRV does not affect the virtual-machine load/store
94
* instructions, HLV, HLVX, and HSV.
95
*/
96
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
97
+ if (mmuidx_2stage(mmu_idx)) {
98
mode = get_field(env->hstatus, HSTATUS_SPVP);
99
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
100
get_field(env->mstatus, MSTATUS_MPRV)) {
101
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
102
103
pmu_tlb_fill_incr_ctr(cpu, access_type);
104
if (env->virt_enabled ||
105
- ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
106
+ ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
107
access_type != MMU_INST_FETCH)) {
108
/* Two stage lookup */
109
ret = get_physical_address(env, &pa, &prot, address,
110
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
111
} else {
112
raise_mmu_exception(env, address, access_type, pmp_violation,
113
first_stage_error,
114
- env->virt_enabled ||
115
- riscv_cpu_two_stage_lookup(mmu_idx),
116
+ env->virt_enabled || mmuidx_2stage(mmu_idx),
117
two_stage_indirect_error);
118
cpu_loop_exit_restore(cs, retaddr);
119
}
120
--
121
2.40.0
diff view generated by jsdifflib
New patch
[PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The current cpu_mmu_index value is really irrelevant to
4
the HLV/HSV lookup. Provide the correct priv level directly.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 10 +---------
15
target/riscv/op_helper.c | 2 +-
16
2 files changed, 2 insertions(+), 10 deletions(-)
17
18
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu_helper.c
21
+++ b/target/riscv/cpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
23
use_background = true;
24
}
25
26
- /*
27
- * MPRV does not affect the virtual-machine load/store
28
- * instructions, HLV, HLVX, and HSV.
29
- */
30
- if (mmuidx_2stage(mmu_idx)) {
31
- mode = get_field(env->hstatus, HSTATUS_SPVP);
32
- }
33
-
34
if (first_stage == false) {
35
/*
36
* We are in stage 2 translation, this is similar to stage 1.
37
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
38
* instructions, HLV, HLVX, and HSV.
39
*/
40
if (mmuidx_2stage(mmu_idx)) {
41
- mode = get_field(env->hstatus, HSTATUS_SPVP);
42
+ ;
43
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
44
get_field(env->mstatus, MSTATUS_MPRV)) {
45
mode = get_field(env->mstatus, MSTATUS_MPP);
46
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/op_helper.c
49
+++ b/target/riscv/op_helper.c
50
@@ -XXX,XX +XXX,XX @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
51
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
52
}
53
54
- return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
55
+ return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT;
56
}
57
58
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
59
--
60
2.40.0
diff view generated by jsdifflib
New patch
[PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
4
function, so we don't have to keep doing it within tlb_fill and
5
subroutines. This also elides a flush on changes to MPV.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org>
12
Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/cpu_helper.c | 49 ++++++++++++++-------------------------
16
target/riscv/csr.c | 6 +----
17
2 files changed, 18 insertions(+), 37 deletions(-)
18
19
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu_helper.c
22
+++ b/target/riscv/cpu_helper.c
23
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
24
#ifdef CONFIG_USER_ONLY
25
return 0;
26
#else
27
- if (ifetch) {
28
- return env->priv;
29
- }
30
+ bool virt = env->virt_enabled;
31
+ int mode = env->priv;
32
33
/* All priv -> mmu_idx mapping are here */
34
- int mode = env->priv;
35
- if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
36
- mode = get_field(env->mstatus, MSTATUS_MPP);
37
- }
38
- if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
39
- return MMUIdx_S_SUM;
40
+ if (!ifetch) {
41
+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
42
+ mode = get_field(env->mstatus, MSTATUS_MPP);
43
+ virt = get_field(env->mstatus, MSTATUS_MPV);
44
+ }
45
+ if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
46
+ mode = MMUIdx_S_SUM;
47
+ }
48
}
49
- return mode;
50
+
51
+ return mode | (virt ? MMU_2STAGE_BIT : 0);
52
#endif
53
}
54
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
56
}
57
58
env->badaddr = addr;
59
- env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
60
+ env->two_stage_lookup = mmuidx_2stage(mmu_idx);
61
env->two_stage_indirect_lookup = false;
62
cpu_loop_exit_restore(cs, retaddr);
63
}
64
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
65
g_assert_not_reached();
66
}
67
env->badaddr = addr;
68
- env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
69
+ env->two_stage_lookup = mmuidx_2stage(mmu_idx);
70
env->two_stage_indirect_lookup = false;
71
cpu_loop_exit_restore(cs, retaddr);
72
}
73
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
74
int prot, prot2, prot_pmp;
75
bool pmp_violation = false;
76
bool first_stage_error = true;
77
- bool two_stage_lookup = false;
78
+ bool two_stage_lookup = mmuidx_2stage(mmu_idx);
79
bool two_stage_indirect_error = false;
80
int ret = TRANSLATE_FAIL;
81
int mode = mmu_idx;
82
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
83
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
84
__func__, address, access_type, mmu_idx);
85
86
- /*
87
- * MPRV does not affect the virtual-machine load/store
88
- * instructions, HLV, HLVX, and HSV.
89
- */
90
- if (mmuidx_2stage(mmu_idx)) {
91
- ;
92
- } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
93
- get_field(env->mstatus, MSTATUS_MPRV)) {
94
- mode = get_field(env->mstatus, MSTATUS_MPP);
95
- if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
96
- two_stage_lookup = true;
97
- }
98
- }
99
-
100
pmu_tlb_fill_incr_ctr(cpu, access_type);
101
- if (env->virt_enabled ||
102
- ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
103
- access_type != MMU_INST_FETCH)) {
104
+ if (two_stage_lookup) {
105
/* Two stage lookup */
106
ret = get_physical_address(env, &pa, &prot, address,
107
&env->guest_phys_fault_addr, access_type,
108
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
109
return false;
110
} else {
111
raise_mmu_exception(env, address, access_type, pmp_violation,
112
- first_stage_error,
113
- env->virt_enabled || mmuidx_2stage(mmu_idx),
114
+ first_stage_error, two_stage_lookup,
115
two_stage_indirect_error);
116
cpu_loop_exit_restore(cs, retaddr);
117
}
118
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/csr.c
121
+++ b/target/riscv/csr.c
122
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
123
val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
124
125
/* flush tlb on mstatus fields that affect VM */
126
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
127
+ if ((val ^ mstatus) & MSTATUS_MXR) {
128
tlb_flush(env_cpu(env));
129
}
130
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
131
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
132
uint64_t valh = (uint64_t)val << 32;
133
uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
134
135
- if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
136
- tlb_flush(env_cpu(env));
137
- }
138
-
139
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
140
141
return RISCV_EXCP_NONE;
142
--
143
2.40.0
diff view generated by jsdifflib
New patch
[PULL 73/89] target/riscv: Check SUM in the correct register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
4
vsstatus.SUM instead of HS-level sstatus.SUM.
5
6
For HLV/HSV instructions, the HS-level register does not apply, but
7
the VS-level register presumably does, though this is not mentioned
8
explicitly in the manual. However, it matches the behavior for MPV.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
13
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org>
15
Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu_helper.c | 12 ++++++++----
19
target/riscv/op_helper.c | 6 +++++-
20
2 files changed, 13 insertions(+), 5 deletions(-)
21
22
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu_helper.c
25
+++ b/target/riscv/cpu_helper.c
26
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
27
28
/* All priv -> mmu_idx mapping are here */
29
if (!ifetch) {
30
- if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
31
+ uint64_t status = env->mstatus;
32
+
33
+ if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
34
mode = get_field(env->mstatus, MSTATUS_MPP);
35
virt = get_field(env->mstatus, MSTATUS_MPV);
36
+ if (virt) {
37
+ status = env->vsstatus;
38
+ }
39
}
40
- if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
41
+ if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {
42
mode = MMUIdx_S_SUM;
43
}
44
}
45
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
46
}
47
widened = 2;
48
}
49
- /* status.SUM will be ignored if execute on background */
50
- sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
51
+ sum = mmuidx_sum(mmu_idx) || is_debug;
52
switch (vm) {
53
case VM_1_10_SV32:
54
levels = 2; ptidxbits = 10; ptesize = 4; break;
55
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/op_helper.c
58
+++ b/target/riscv/op_helper.c
59
@@ -XXX,XX +XXX,XX @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
60
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
61
}
62
63
- return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT;
64
+ int mode = get_field(env->hstatus, HSTATUS_SPVP);
65
+ if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) {
66
+ mode = MMUIdx_S_SUM;
67
+ }
68
+ return mode | MMU_2STAGE_BIT;
69
}
70
71
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
72
--
73
2.40.0
diff view generated by jsdifflib
New patch
[PULL 74/89] target/riscv: Hoist second stage mode change to callers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Move the check from the top of get_physical_address to
4
the two callers, where passing mmu_idx makes no sense.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 12 ++----------
15
1 file changed, 2 insertions(+), 10 deletions(-)
16
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
22
use_background = true;
23
}
24
25
- if (first_stage == false) {
26
- /*
27
- * We are in stage 2 translation, this is similar to stage 1.
28
- * Stage 2 is always taken as U-mode
29
- */
30
- mode = PRV_U;
31
- }
32
-
33
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
34
*physical = addr;
35
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
36
@@ -XXX,XX +XXX,XX @@ restart:
37
/* Do the second stage translation on the base PTE address. */
38
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
39
base, NULL, MMU_DATA_LOAD,
40
- mmu_idx, false, true,
41
+ MMUIdx_U, false, true,
42
is_debug);
43
44
if (vbase_ret != TRANSLATE_SUCCESS) {
45
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
46
im_address = pa;
47
48
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
49
- access_type, mmu_idx, false, true,
50
+ access_type, MMUIdx_U, false, true,
51
false);
52
53
qemu_log_mask(CPU_LOG_MMU,
54
--
55
2.40.0
diff view generated by jsdifflib
New patch
[PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These values are constant for every level of pte lookup.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org>
10
Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu_helper.c | 16 ++++++++--------
14
1 file changed, 8 insertions(+), 8 deletions(-)
15
16
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu_helper.c
19
+++ b/target/riscv/cpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
21
return TRANSLATE_FAIL;
22
}
23
24
+ bool pbmte = env->menvcfg & MENVCFG_PBMTE;
25
+ bool hade = env->menvcfg & MENVCFG_HADE;
26
+
27
+ if (first_stage && two_stage && env->virt_enabled) {
28
+ pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
29
+ hade = hade && (env->henvcfg & HENVCFG_HADE);
30
+ }
31
+
32
int ptshift = (levels - 1) * ptidxbits;
33
int i;
34
35
@@ -XXX,XX +XXX,XX @@ restart:
36
return TRANSLATE_FAIL;
37
}
38
39
- bool pbmte = env->menvcfg & MENVCFG_PBMTE;
40
- bool hade = env->menvcfg & MENVCFG_HADE;
41
-
42
- if (first_stage && two_stage && env->virt_enabled) {
43
- pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
44
- hade = hade && (env->henvcfg & HENVCFG_HADE);
45
- }
46
-
47
if (riscv_cpu_sxl(env) == MXL_RV32) {
48
ppn = pte >> PTE_PPN_SHIFT;
49
} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
50
--
51
2.40.0
diff view generated by jsdifflib
New patch
[PULL 76/89] target/riscv: Move leaf pte processing out of level loop
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Move the code that never loops outside of the loop.
4
Unchain the if-return-else statements.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org>
11
Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_helper.c | 234 ++++++++++++++++++++------------------
15
1 file changed, 123 insertions(+), 111 deletions(-)
16
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
22
}
23
24
int ptshift = (levels - 1) * ptidxbits;
25
+ target_ulong pte;
26
+ hwaddr pte_addr;
27
int i;
28
29
#if !TCG_OVERSIZED_GUEST
30
@@ -XXX,XX +XXX,XX @@ restart:
31
}
32
33
/* check that physical address of PTE is legal */
34
- hwaddr pte_addr;
35
36
if (two_stage && first_stage) {
37
int vbase_prot;
38
@@ -XXX,XX +XXX,XX @@ restart:
39
return TRANSLATE_PMP_FAIL;
40
}
41
42
- target_ulong pte;
43
if (riscv_cpu_mxl(env) == MXL_RV32) {
44
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
45
} else {
46
@@ -XXX,XX +XXX,XX @@ restart:
47
if (!(pte & PTE_V)) {
48
/* Invalid PTE */
49
return TRANSLATE_FAIL;
50
- } else if (!pbmte && (pte & PTE_PBMT)) {
51
- return TRANSLATE_FAIL;
52
- } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
53
- /* Inner PTE, continue walking */
54
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
55
- return TRANSLATE_FAIL;
56
- }
57
- base = ppn << PGSHIFT;
58
- } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
59
- /* Reserved leaf PTE flags: PTE_W */
60
- return TRANSLATE_FAIL;
61
- } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
62
- /* Reserved leaf PTE flags: PTE_W + PTE_X */
63
- return TRANSLATE_FAIL;
64
- } else if ((pte & PTE_U) && ((mode != PRV_U) &&
65
- (!sum || access_type == MMU_INST_FETCH))) {
66
- /* User PTE flags when not U mode and mstatus.SUM is not set,
67
- or the access type is an instruction fetch */
68
- return TRANSLATE_FAIL;
69
- } else if (!(pte & PTE_U) && (mode != PRV_S)) {
70
- /* Supervisor PTE flags when not S mode */
71
- return TRANSLATE_FAIL;
72
- } else if (ppn & ((1ULL << ptshift) - 1)) {
73
- /* Misaligned PPN */
74
- return TRANSLATE_FAIL;
75
- } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
76
- ((pte & PTE_X) && mxr))) {
77
- /* Read access check failed */
78
- return TRANSLATE_FAIL;
79
- } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
80
- /* Write access check failed */
81
- return TRANSLATE_FAIL;
82
- } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
83
- /* Fetch access check failed */
84
+ }
85
+ if (pte & (PTE_R | PTE_W | PTE_X)) {
86
+ goto leaf;
87
+ }
88
+
89
+ /* Inner PTE, continue walking */
90
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
91
return TRANSLATE_FAIL;
92
- } else {
93
- /* if necessary, set accessed and dirty bits. */
94
- target_ulong updated_pte = pte | PTE_A |
95
+ }
96
+ base = ppn << PGSHIFT;
97
+ }
98
+
99
+ /* No leaf pte at any translation level. */
100
+ return TRANSLATE_FAIL;
101
+
102
+ leaf:
103
+ if (ppn & ((1ULL << ptshift) - 1)) {
104
+ /* Misaligned PPN */
105
+ return TRANSLATE_FAIL;
106
+ }
107
+ if (!pbmte && (pte & PTE_PBMT)) {
108
+ /* Reserved without Svpbmt. */
109
+ return TRANSLATE_FAIL;
110
+ }
111
+ if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
112
+ /* Reserved leaf PTE flags: PTE_W */
113
+ return TRANSLATE_FAIL;
114
+ }
115
+ if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
116
+ /* Reserved leaf PTE flags: PTE_W + PTE_X */
117
+ return TRANSLATE_FAIL;
118
+ }
119
+ if ((pte & PTE_U) &&
120
+ ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
121
+ /*
122
+ * User PTE flags when not U mode and mstatus.SUM is not set,
123
+ * or the access type is an instruction fetch.
124
+ */
125
+ return TRANSLATE_FAIL;
126
+ }
127
+ if (!(pte & PTE_U) && (mode != PRV_S)) {
128
+ /* Supervisor PTE flags when not S mode */
129
+ return TRANSLATE_FAIL;
130
+ }
131
+ if (access_type == MMU_DATA_LOAD &&
132
+ !((pte & PTE_R) || ((pte & PTE_X) && mxr))) {
133
+ /* Read access check failed */
134
+ return TRANSLATE_FAIL;
135
+ }
136
+ if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
137
+ /* Write access check failed */
138
+ return TRANSLATE_FAIL;
139
+ }
140
+ if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
141
+ /* Fetch access check failed */
142
+ return TRANSLATE_FAIL;
143
+ }
144
+
145
+ /* If necessary, set accessed and dirty bits. */
146
+ target_ulong updated_pte = pte | PTE_A |
147
(access_type == MMU_DATA_STORE ? PTE_D : 0);
148
149
- /* Page table updates need to be atomic with MTTCG enabled */
150
- if (updated_pte != pte) {
151
- if (!hade) {
152
- return TRANSLATE_FAIL;
153
- }
154
+ /* Page table updates need to be atomic with MTTCG enabled */
155
+ if (updated_pte != pte) {
156
+ if (!hade) {
157
+ return TRANSLATE_FAIL;
158
+ }
159
160
- /*
161
- * - if accessed or dirty bits need updating, and the PTE is
162
- * in RAM, then we do so atomically with a compare and swap.
163
- * - if the PTE is in IO space or ROM, then it can't be updated
164
- * and we return TRANSLATE_FAIL.
165
- * - if the PTE changed by the time we went to update it, then
166
- * it is no longer valid and we must re-walk the page table.
167
- */
168
- MemoryRegion *mr;
169
- hwaddr l = sizeof(target_ulong), addr1;
170
- mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
171
- false, MEMTXATTRS_UNSPECIFIED);
172
- if (memory_region_is_ram(mr)) {
173
- target_ulong *pte_pa =
174
- qemu_map_ram_ptr(mr->ram_block, addr1);
175
+ /*
176
+ * - if accessed or dirty bits need updating, and the PTE is
177
+ * in RAM, then we do so atomically with a compare and swap.
178
+ * - if the PTE is in IO space or ROM, then it can't be updated
179
+ * and we return TRANSLATE_FAIL.
180
+ * - if the PTE changed by the time we went to update it, then
181
+ * it is no longer valid and we must re-walk the page table.
182
+ */
183
+ MemoryRegion *mr;
184
+ hwaddr l = sizeof(target_ulong), addr1;
185
+ mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
186
+ false, MEMTXATTRS_UNSPECIFIED);
187
+ if (memory_region_is_ram(mr)) {
188
+ target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
189
#if TCG_OVERSIZED_GUEST
190
- /*
191
- * MTTCG is not enabled on oversized TCG guests so
192
- * page table updates do not need to be atomic
193
- */
194
- *pte_pa = pte = updated_pte;
195
+ /*
196
+ * MTTCG is not enabled on oversized TCG guests so
197
+ * page table updates do not need to be atomic
198
+ */
199
+ *pte_pa = pte = updated_pte;
200
#else
201
- target_ulong old_pte =
202
- qatomic_cmpxchg(pte_pa, pte, updated_pte);
203
- if (old_pte != pte) {
204
- goto restart;
205
- } else {
206
- pte = updated_pte;
207
- }
208
-#endif
209
- } else {
210
- /*
211
- * misconfigured PTE in ROM (AD bits are not preset) or
212
- * PTE is in IO space and can't be updated atomically
213
- */
214
- return TRANSLATE_FAIL;
215
- }
216
+ target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
217
+ if (old_pte != pte) {
218
+ goto restart;
219
}
220
-
221
+ pte = updated_pte;
222
+#endif
223
+ } else {
224
/*
225
- * for superpage mappings, make a fake leaf PTE for the TLB's
226
- * benefit.
227
+ * Misconfigured PTE in ROM (AD bits are not preset) or
228
+ * PTE is in IO space and can't be updated atomically.
229
*/
230
- target_ulong vpn = addr >> PGSHIFT;
231
-
232
- if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
233
- napot_bits = ctzl(ppn) + 1;
234
- if ((i != (levels - 1)) || (napot_bits != 4)) {
235
- return TRANSLATE_FAIL;
236
- }
237
- }
238
+ return TRANSLATE_FAIL;
239
+ }
240
+ }
241
242
- napot_mask = (1 << napot_bits) - 1;
243
- *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
244
- (vpn & (((target_ulong)1 << ptshift) - 1))
245
- ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
246
+ /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
247
+ target_ulong vpn = addr >> PGSHIFT;
248
249
- /* set permissions on the TLB entry */
250
- if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
251
- *prot |= PAGE_READ;
252
- }
253
- if (pte & PTE_X) {
254
- *prot |= PAGE_EXEC;
255
- }
256
- /*
257
- * add write permission on stores or if the page is already dirty,
258
- * so that we TLB miss on later writes to update the dirty bit
259
- */
260
- if ((pte & PTE_W) &&
261
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
262
- *prot |= PAGE_WRITE;
263
- }
264
- return TRANSLATE_SUCCESS;
265
+ if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
266
+ napot_bits = ctzl(ppn) + 1;
267
+ if ((i != (levels - 1)) || (napot_bits != 4)) {
268
+ return TRANSLATE_FAIL;
269
}
270
}
271
- return TRANSLATE_FAIL;
272
+
273
+ napot_mask = (1 << napot_bits) - 1;
274
+ *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
275
+ (vpn & (((target_ulong)1 << ptshift) - 1))
276
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
277
+
278
+ /* set permissions on the TLB entry */
279
+ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
280
+ *prot |= PAGE_READ;
281
+ }
282
+ if (pte & PTE_X) {
283
+ *prot |= PAGE_EXEC;
284
+ }
285
+ /*
286
+ * Add write permission on stores or if the page is already dirty,
287
+ * so that we TLB miss on later writes to update the dirty bit.
288
+ */
289
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
290
+ *prot |= PAGE_WRITE;
291
+ }
292
+ return TRANSLATE_SUCCESS;
293
}
294
295
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
296
--
297
2.40.0
diff view generated by jsdifflib
New patch
[PULL 77/89] target/riscv: Suppress pte update with is_debug
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The debugger should not modify PTE_A or PTE_D.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org>
10
Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu_helper.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu_helper.c
19
+++ b/target/riscv/cpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ restart:
21
(access_type == MMU_DATA_STORE ? PTE_D : 0);
22
23
/* Page table updates need to be atomic with MTTCG enabled */
24
- if (updated_pte != pte) {
25
+ if (updated_pte != pte && !is_debug) {
26
if (!hade) {
27
return TRANSLATE_FAIL;
28
}
29
--
30
2.40.0
diff view generated by jsdifflib
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
[PULL 78/89] target/riscv: Don't modify SUM with is_debug
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The current condition for the use of background registers only
3
If we want to give the debugger a greater view of memory than
4
considers the hypervisor load and store instructions,
4
the cpu, we should simply disable the access check entirely,
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
5
not simply for this one corner case.
6
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
9
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
10
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org>
12
Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
target/riscv/cpu_helper.c | 2 +-
15
target/riscv/cpu_helper.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
16
1 file changed, 1 insertion(+), 1 deletion(-)
14
17
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
20
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
21
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
22
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
20
* was called. Background registers will be used if the guest has
23
}
21
* forced a two stage translation to be on (in HS or M mode).
24
widened = 2;
22
*/
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
25
use_background = true;
26
}
25
}
27
26
- sum = mmuidx_sum(mmu_idx) || is_debug;
27
+ sum = mmuidx_sum(mmu_idx);
28
switch (vm) {
29
case VM_1_10_SV32:
30
levels = 2; ptidxbits = 10; ptesize = 4; break;
28
--
31
--
29
2.30.1
32
2.40.0
30
31
diff view generated by jsdifflib
New patch
[PULL 79/89] target/riscv: Merge checks for reserved pte flags
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org>
8
Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/cpu_helper.c | 12 ++++++------
12
1 file changed, 6 insertions(+), 6 deletions(-)
13
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ restart:
19
/* Reserved without Svpbmt. */
20
return TRANSLATE_FAIL;
21
}
22
- if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
23
- /* Reserved leaf PTE flags: PTE_W */
24
- return TRANSLATE_FAIL;
25
- }
26
- if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
27
- /* Reserved leaf PTE flags: PTE_W + PTE_X */
28
+
29
+ /* Check for reserved combinations of RWX flags. */
30
+ switch (pte & (PTE_R | PTE_W | PTE_X)) {
31
+ case PTE_W:
32
+ case PTE_W | PTE_X:
33
return TRANSLATE_FAIL;
34
}
35
+
36
if ((pte & PTE_U) &&
37
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
38
/*
39
--
40
2.40.0
diff view generated by jsdifflib
New patch
[PULL 80/89] target/riscv: Reorg access check in get_physical_address
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We were effectively computing the protection bits twice,
4
once while performing access checks and once while returning
5
the valid bits to the caller. Reorg so we do this once.
6
7
Move the computation of mxr close to its single use.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org>
14
Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/cpu_helper.c | 69 ++++++++++++++++++++-------------------
18
1 file changed, 36 insertions(+), 33 deletions(-)
19
20
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/cpu_helper.c
23
+++ b/target/riscv/cpu_helper.c
24
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
25
* @is_debug: Is this access from a debugger or the monitor?
26
*/
27
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
28
- int *prot, vaddr addr,
29
+ int *ret_prot, vaddr addr,
30
target_ulong *fault_pte_addr,
31
int access_type, int mmu_idx,
32
bool first_stage, bool two_stage,
33
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
34
35
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
36
*physical = addr;
37
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
38
+ *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
39
return TRANSLATE_SUCCESS;
40
}
41
42
- *prot = 0;
43
+ *ret_prot = 0;
44
45
hwaddr base;
46
- int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
47
-
48
- if (first_stage == true) {
49
- mxr = get_field(env->mstatus, MSTATUS_MXR);
50
- } else {
51
- mxr = get_field(env->vsstatus, MSTATUS_MXR);
52
- }
53
+ int levels, ptidxbits, ptesize, vm, sum, widened;
54
55
if (first_stage == true) {
56
if (use_background) {
57
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
58
levels = 5; ptidxbits = 9; ptesize = 8; break;
59
case VM_1_10_MBARE:
60
*physical = addr;
61
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
62
+ *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
63
return TRANSLATE_SUCCESS;
64
default:
65
g_assert_not_reached();
66
@@ -XXX,XX +XXX,XX @@ restart:
67
return TRANSLATE_FAIL;
68
}
69
70
+ int prot = 0;
71
+ if (pte & PTE_R) {
72
+ prot |= PAGE_READ;
73
+ }
74
+ if (pte & PTE_W) {
75
+ prot |= PAGE_WRITE;
76
+ }
77
+ if (pte & PTE_X) {
78
+ bool mxr;
79
+
80
+ if (first_stage == true) {
81
+ mxr = get_field(env->mstatus, MSTATUS_MXR);
82
+ } else {
83
+ mxr = get_field(env->vsstatus, MSTATUS_MXR);
84
+ }
85
+ if (mxr) {
86
+ prot |= PAGE_READ;
87
+ }
88
+ prot |= PAGE_EXEC;
89
+ }
90
+
91
if ((pte & PTE_U) &&
92
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
93
/*
94
@@ -XXX,XX +XXX,XX @@ restart:
95
/* Supervisor PTE flags when not S mode */
96
return TRANSLATE_FAIL;
97
}
98
- if (access_type == MMU_DATA_LOAD &&
99
- !((pte & PTE_R) || ((pte & PTE_X) && mxr))) {
100
- /* Read access check failed */
101
- return TRANSLATE_FAIL;
102
- }
103
- if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
104
- /* Write access check failed */
105
- return TRANSLATE_FAIL;
106
- }
107
- if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
108
- /* Fetch access check failed */
109
+
110
+ if (!((prot >> access_type) & 1)) {
111
+ /* Access check failed */
112
return TRANSLATE_FAIL;
113
}
114
115
@@ -XXX,XX +XXX,XX @@ restart:
116
(vpn & (((target_ulong)1 << ptshift) - 1))
117
) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
118
119
- /* set permissions on the TLB entry */
120
- if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
121
- *prot |= PAGE_READ;
122
- }
123
- if (pte & PTE_X) {
124
- *prot |= PAGE_EXEC;
125
- }
126
/*
127
- * Add write permission on stores or if the page is already dirty,
128
- * so that we TLB miss on later writes to update the dirty bit.
129
+ * Remove write permission unless this is a store, or the page is
130
+ * already dirty, so that we TLB miss on later writes to update
131
+ * the dirty bit.
132
*/
133
- if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
134
- *prot |= PAGE_WRITE;
135
+ if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) {
136
+ prot &= ~PAGE_WRITE;
137
}
138
+ *ret_prot = prot;
139
+
140
return TRANSLATE_SUCCESS;
141
}
142
143
--
144
2.40.0
diff view generated by jsdifflib
[PULL 04/16] target/riscv: add log of PMP permission checking
[PULL 81/89] target/riscv: Reorg sum check in get_physical_address
1
From: Jim Shu <cwshu@andestech.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Like MMU translation, add qemu log of PMP permission checking for
3
Implement this by adjusting prot, which reduces the set of
4
debugging.
4
checks required. This prevents exec to be set for U pages
5
in MMUIdx_S_SUM. While it had been technically incorrect,
6
it did not manifest as a bug, because we will never attempt
7
to execute from MMUIdx_S_SUM.
5
8
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
11
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org>
14
Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
17
target/riscv/cpu_helper.c | 22 +++++++++++-----------
12
1 file changed, 12 insertions(+)
18
1 file changed, 11 insertions(+), 11 deletions(-)
13
19
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
20
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
22
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
23
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
24
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
19
if (ret == TRANSLATE_SUCCESS) {
25
*ret_prot = 0;
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
26
21
size, access_type, mode);
27
hwaddr base;
28
- int levels, ptidxbits, ptesize, vm, sum, widened;
29
+ int levels, ptidxbits, ptesize, vm, widened;
30
31
if (first_stage == true) {
32
if (use_background) {
33
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
34
}
35
widened = 2;
36
}
37
- sum = mmuidx_sum(mmu_idx);
22
+
38
+
23
+ qemu_log_mask(CPU_LOG_MMU,
39
switch (vm) {
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
40
case VM_1_10_SV32:
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
41
levels = 2; ptidxbits = 10; ptesize = 4; break;
26
+ __func__, pa, ret, prot_pmp, tlb_size);
42
@@ -XXX,XX +XXX,XX @@ restart:
27
+
43
prot |= PAGE_EXEC;
28
prot &= prot_pmp;
44
}
29
}
45
30
46
- if ((pte & PTE_U) &&
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
47
- ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
32
if (ret == TRANSLATE_SUCCESS) {
48
- /*
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
49
- * User PTE flags when not U mode and mstatus.SUM is not set,
34
size, access_type, mode);
50
- * or the access type is an instruction fetch.
35
+
51
- */
36
+ qemu_log_mask(CPU_LOG_MMU,
52
- return TRANSLATE_FAIL;
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
53
- }
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
54
- if (!(pte & PTE_U) && (mode != PRV_S)) {
39
+ __func__, pa, ret, prot_pmp, tlb_size);
55
+ if (pte & PTE_U) {
40
+
56
+ if (mode != PRV_U) {
41
prot &= prot_pmp;
57
+ if (!mmuidx_sum(mmu_idx)) {
42
}
58
+ return TRANSLATE_FAIL;
59
+ }
60
+ /* SUM allows only read+write, not execute. */
61
+ prot &= PAGE_READ | PAGE_WRITE;
62
+ }
63
+ } else if (mode != PRV_S) {
64
/* Supervisor PTE flags when not S mode */
65
return TRANSLATE_FAIL;
43
}
66
}
44
--
67
--
45
2.30.1
68
2.40.0
46
47
diff view generated by jsdifflib
New patch
[PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state
1
From: Ivan Klokov <ivan.klokov@syntacore.com>
1
2
3
Since g_new is used to initialize the RISCVAPLICState->state structure,
4
in some case we get behavior that is not as expected. This patch
5
changes this to g_new0, which allows to initialize the APLIC in the correct state.
6
7
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Anup Patel <anup@brainfault.org>
10
Message-Id: <20230413133432.53771-1-ivan.klokov@syntacore.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/intc/riscv_aplic.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/riscv_aplic.c
19
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
21
22
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
23
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
24
- aplic->state = g_new(uint32_t, aplic->num_irqs);
25
+ aplic->state = g_new0(uint32_t, aplic->num_irqs);
26
aplic->target = g_new0(uint32_t, aplic->num_irqs);
27
if (!aplic->msimode) {
28
for (i = 0; i < aplic->num_irqs; i++) {
29
--
30
2.40.0
diff view generated by jsdifflib
New patch
[PULL 83/89] target/riscv: add CPU QOM header
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
QMP CPU commands are usually implemented by a separated file,
4
<arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
5
This file uses a CPU QOM header with basic QOM declarations for the
6
arch.
7
8
We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
9
but first we need a cpu-qom.h header with the definitions of
10
TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
11
cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
12
13
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++
20
target/riscv/cpu.h | 46 +--------------------------
21
2 files changed, 71 insertions(+), 45 deletions(-)
22
create mode 100644 target/riscv/cpu-qom.h
23
24
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
25
new file mode 100644
26
index XXXXXXX..XXXXXXX
27
--- /dev/null
28
+++ b/target/riscv/cpu-qom.h
29
@@ -XXX,XX +XXX,XX @@
30
+/*
31
+ * QEMU RISC-V CPU QOM header
32
+ *
33
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
34
+ *
35
+ * This program is free software; you can redistribute it and/or modify it
36
+ * under the terms and conditions of the GNU General Public License,
37
+ * version 2 or later, as published by the Free Software Foundation.
38
+ *
39
+ * This program is distributed in the hope it will be useful, but WITHOUT
40
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
41
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
42
+ * more details.
43
+ *
44
+ * You should have received a copy of the GNU General Public License along with
45
+ * this program. If not, see <http://www.gnu.org/licenses/>.
46
+ */
47
+
48
+#ifndef RISCV_CPU_QOM_H
49
+#define RISCV_CPU_QOM_H
50
+
51
+#include "hw/core/cpu.h"
52
+#include "qom/object.h"
53
+
54
+#define TYPE_RISCV_CPU "riscv-cpu"
55
+
56
+#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
57
+#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
58
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
59
+
60
+#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
61
+#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
62
+#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
63
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
64
+#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
65
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
66
+#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
67
+#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
68
+#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
69
+#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
70
+#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
71
+#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
72
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
73
+
74
+#if defined(TARGET_RISCV32)
75
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
76
+#elif defined(TARGET_RISCV64)
77
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
78
+#endif
79
+
80
+typedef struct CPUArchState CPURISCVState;
81
+
82
+OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
83
+
84
+/**
85
+ * RISCVCPUClass:
86
+ * @parent_realize: The parent class' realize handler.
87
+ * @parent_phases: The parent class' reset phase handlers.
88
+ *
89
+ * A RISCV CPU model.
90
+ */
91
+struct RISCVCPUClass {
92
+ /*< private >*/
93
+ CPUClass parent_class;
94
+ /*< public >*/
95
+ DeviceRealize parent_realize;
96
+ ResettablePhases parent_phases;
97
+};
98
+
99
+#endif /* RISCV_CPU_QOM_H */
100
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/riscv/cpu.h
103
+++ b/target/riscv/cpu.h
104
@@ -XXX,XX +XXX,XX @@
105
#include "qemu/int128.h"
106
#include "cpu_bits.h"
107
#include "qapi/qapi-types-common.h"
108
+#include "cpu-qom.h"
109
110
#define TCG_GUEST_DEFAULT_MO 0
111
112
@@ -XXX,XX +XXX,XX @@
113
*/
114
#define TARGET_INSN_START_EXTRA_WORDS 1
115
116
-#define TYPE_RISCV_CPU "riscv-cpu"
117
-
118
-#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
119
-#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
120
-#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
121
-
122
-#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
123
-#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
124
-#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
125
-#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
126
-#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
127
-#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
128
-#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
129
-#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
130
-#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
131
-#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
132
-#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
133
-#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
134
-#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
135
-
136
-#if defined(TARGET_RISCV32)
137
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
138
-#elif defined(TARGET_RISCV64)
139
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
140
-#endif
141
-
142
#define RV(x) ((target_ulong)1 << (x - 'A'))
143
144
/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
145
@@ -XXX,XX +XXX,XX @@ typedef enum {
146
147
#define MAX_RISCV_PMPS (16)
148
149
-typedef struct CPUArchState CPURISCVState;
150
-
151
#if !defined(CONFIG_USER_ONLY)
152
#include "pmp.h"
153
#include "debug.h"
154
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
155
uint64_t kvm_timer_frequency;
156
};
157
158
-OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
159
-
160
-/*
161
- * RISCVCPUClass:
162
- * @parent_realize: The parent class' realize handler.
163
- * @parent_phases: The parent class' reset phase handlers.
164
- *
165
- * A RISCV CPU model.
166
- */
167
-struct RISCVCPUClass {
168
- /* < private > */
169
- CPUClass parent_class;
170
- /* < public > */
171
- DeviceRealize parent_realize;
172
- ResettablePhases parent_phases;
173
-};
174
-
175
/*
176
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
177
* satp mode that is supported. It may be chosen by the user and must respect
178
--
179
2.40.0
diff view generated by jsdifflib
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PULL 84/89] target/riscv: add query-cpy-definitions support
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
This adds the documentation to describe what is supported for the
3
This command is used by tooling like libvirt to retrieve a list of
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
4
supported CPUs. Each entry returns a CpuDefinitionInfo object that
5
contains more information about each CPU.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
This initial support includes only the name of the CPU and its typename.
8
Here's what the command produces for the riscv64 target:
9
10
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
11
{"QMP": {"version": (...)}
12
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
13
{"return": {}}
14
{"execute": "query-cpu-definitions"}
15
{"return": [
16
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
17
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false},
18
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
19
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
20
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false},
21
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false},
22
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}]
23
}
24
25
Next patch will introduce a way to tell whether a given CPU is static or
26
not.
27
28
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
31
Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
33
---
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
34
qapi/machine-target.json | 6 ++--
12
docs/system/target-riscv.rst | 1 +
35
target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++
13
2 files changed, 90 insertions(+)
36
target/riscv/meson.build | 3 +-
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
37
3 files changed, 59 insertions(+), 3 deletions(-)
38
create mode 100644 target/riscv/riscv-qmp-cmds.c
15
39
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
40
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
41
index XXXXXXX..XXXXXXX 100644
42
--- a/qapi/machine-target.json
43
+++ b/qapi/machine-target.json
44
@@ -XXX,XX +XXX,XX @@
45
'TARGET_I386',
46
'TARGET_S390X',
47
'TARGET_MIPS',
48
- 'TARGET_LOONGARCH64' ] } }
49
+ 'TARGET_LOONGARCH64',
50
+ 'TARGET_RISCV' ] } }
51
52
##
53
# @query-cpu-definitions:
54
@@ -XXX,XX +XXX,XX @@
55
'TARGET_I386',
56
'TARGET_S390X',
57
'TARGET_MIPS',
58
- 'TARGET_LOONGARCH64' ] } }
59
+ 'TARGET_LOONGARCH64',
60
+ 'TARGET_RISCV' ] } }
61
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
17
new file mode 100644
62
new file mode 100644
18
index XXXXXXX..XXXXXXX
63
index XXXXXXX..XXXXXXX
19
--- /dev/null
64
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
65
+++ b/target/riscv/riscv-qmp-cmds.c
21
@@ -XXX,XX +XXX,XX @@
66
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
67
+/*
23
+=============================================================
68
+ * QEMU CPU QMP commands for RISC-V
69
+ *
70
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
71
+ *
72
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
73
+ * of this software and associated documentation files (the "Software"), to deal
74
+ * in the Software without restriction, including without limitation the rights
75
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
76
+ * copies of the Software, and to permit persons to whom the Software is
77
+ * furnished to do so, subject to the following conditions:
78
+ *
79
+ * The above copyright notice and this permission notice shall be included in
80
+ * all copies or substantial portions of the Software.
81
+ *
82
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
83
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
84
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
86
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
87
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
88
+ * THE SOFTWARE.
89
+ */
24
+
90
+
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
91
+#include "qemu/osdep.h"
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
27
+
92
+
28
+For more details about Microchip PolarFire SoC, please see:
93
+#include "qapi/qapi-commands-machine-target.h"
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
94
+#include "cpu-qom.h"
30
+
95
+
31
+The Icicle Kit board information can be found here:
96
+static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
32
+https://www.microsemi.com/existing-parts/parts/152514
97
+{
98
+ ObjectClass *oc = data;
99
+ CpuDefinitionInfoList **cpu_list = user_data;
100
+ CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
101
+ const char *typename = object_class_get_name(oc);
33
+
102
+
34
+Supported devices
103
+ info->name = g_strndup(typename,
35
+-----------------
104
+ strlen(typename) - strlen("-" TYPE_RISCV_CPU));
105
+ info->q_typename = g_strdup(typename);
36
+
106
+
37
+The ``microchip-icicle-kit`` machine supports the following devices:
107
+ QAPI_LIST_PREPEND(*cpu_list, info);
108
+}
38
+
109
+
39
+ * 1 E51 core
110
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
40
+ * 4 U54 cores
111
+{
41
+ * Core Level Interruptor (CLINT)
112
+ CpuDefinitionInfoList *cpu_list = NULL;
42
+ * Platform-Level Interrupt Controller (PLIC)
113
+ GSList *list = object_class_get_list(TYPE_RISCV_CPU, false);
43
+ * L2 Loosely Integrated Memory (L2-LIM)
44
+ * DDR memory controller
45
+ * 5 MMUARTs
46
+ * 1 DMA controller
47
+ * 2 GEM Ethernet controllers
48
+ * 1 SDHC storage controller
49
+
114
+
50
+Boot options
115
+ g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list);
51
+------------
116
+ g_slist_free(list);
52
+
117
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
118
+ return cpu_list;
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
119
+}
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
120
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
56
+support direct kernel loading via the -kernel option. One has to load kernel
57
+from U-Boot.
58
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
60
+memory size by HSS. A sanity check on ram size is performed in the machine
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
62
+than 1537 MiB ram is detected.
63
+
64
+Boot the machine
65
+----------------
66
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
69
+in the HSS source tree:
70
+
71
+.. code-block:: bash
72
+
73
+ $ export CROSS_COMPILE=riscv64-linux-
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
75
+ $ make BOARD=mpfs-icicle-kit-es
76
+
77
+Download the official SD card image released by Microchip and prepare it for
78
+QEMU usage:
79
+
80
+.. code-block:: bash
81
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
86
+Then we can boot the machine by:
87
+
88
+.. code-block:: bash
89
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
92
+ -nic user,model=cadence_gem \
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
94
+ -display none -serial stdio \
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
96
+ -serial chardev:serial1
97
+
98
+With above command line, current terminal session will be used for the first
99
+serial port. Open another terminal window, and use `minicom` to connect the
100
+second serial port.
101
+
102
+.. code-block:: bash
103
+
104
+ $ minicom -D unix\#serial1.sock
105
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
107
+second serial port. U-Boot will automatically load the Linux kernel from
108
+the SD card image.
109
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
112
index XXXXXXX..XXXXXXX 100644
121
index XXXXXXX..XXXXXXX 100644
113
--- a/docs/system/target-riscv.rst
122
--- a/target/riscv/meson.build
114
+++ b/docs/system/target-riscv.rst
123
+++ b/target/riscv/meson.build
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
124
@@ -XXX,XX +XXX,XX @@ riscv_softmmu_ss.add(files(
116
.. toctree::
125
'monitor.c',
117
:maxdepth: 1
126
'machine.c',
118
127
'pmu.c',
119
+ riscv/microchip-icicle-kit
128
- 'time_helper.c'
120
riscv/sifive_u
129
+ 'time_helper.c',
121
130
+ 'riscv-qmp-cmds.c',
122
RISC-V CPU features
131
))
132
133
target_arch += {'riscv': riscv_ss}
123
--
134
--
124
2.30.1
135
2.40.0
125
126
diff view generated by jsdifflib
New patch
[PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
This new abstract type will be used to differentiate between static and
4
non-static CPUs in query-cpu-definitions.
5
6
All generic CPUs were changed to be of this type. Named CPUs are kept as
7
TYPE_RISCV_CPU and will still be considered static.
8
9
This is the output of query-cpu-definitions after this change for the
10
riscv64 target:
11
12
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
13
{"QMP": {"version": (...)}
14
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
15
{"return": {}}
16
{"execute": "query-cpu-definitions"}
17
{"return": [
18
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
19
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false},
20
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
21
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
22
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false},
23
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false},
24
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false}
25
]}
26
27
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
28
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
---
34
target/riscv/cpu-qom.h | 2 +-
35
target/riscv/cpu.c | 20 ++++++++++++++++----
36
target/riscv/riscv-qmp-cmds.c | 4 ++++
37
3 files changed, 21 insertions(+), 5 deletions(-)
38
39
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu-qom.h
42
+++ b/target/riscv/cpu-qom.h
43
@@ -XXX,XX +XXX,XX @@
44
#include "qom/object.h"
45
46
#define TYPE_RISCV_CPU "riscv-cpu"
47
+#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
48
49
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
50
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
51
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUClass {
52
DeviceRealize parent_realize;
53
ResettablePhases parent_phases;
54
};
55
-
56
#endif /* RISCV_CPU_QOM_H */
57
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/cpu.c
60
+++ b/target/riscv/cpu.c
61
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_list(void)
62
.instance_init = initfn \
63
}
64
65
+#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
66
+ { \
67
+ .name = type_name, \
68
+ .parent = TYPE_RISCV_DYNAMIC_CPU, \
69
+ .instance_init = initfn \
70
+ }
71
+
72
static const TypeInfo riscv_cpu_type_infos[] = {
73
{
74
.name = TYPE_RISCV_CPU,
75
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
76
.class_size = sizeof(RISCVCPUClass),
77
.class_init = riscv_cpu_class_init,
78
},
79
- DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
80
+ {
81
+ .name = TYPE_RISCV_DYNAMIC_CPU,
82
+ .parent = TYPE_RISCV_CPU,
83
+ .abstract = true,
84
+ },
85
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
86
#if defined(CONFIG_KVM)
87
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
88
#endif
89
#if defined(TARGET_RISCV32)
90
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
91
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
92
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
93
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
94
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
95
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
96
#elif defined(TARGET_RISCV64)
97
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
98
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
99
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
100
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
101
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
102
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
103
- DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
104
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
105
#endif
106
};
107
108
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/riscv/riscv-qmp-cmds.c
111
+++ b/target/riscv/riscv-qmp-cmds.c
112
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
113
CpuDefinitionInfoList **cpu_list = user_data;
114
CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
115
const char *typename = object_class_get_name(oc);
116
+ ObjectClass *dyn_class;
117
118
info->name = g_strndup(typename,
119
strlen(typename) - strlen("-" TYPE_RISCV_CPU));
120
info->q_typename = g_strdup(typename);
121
122
+ dyn_class = object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU);
123
+ info->q_static = dyn_class == NULL;
124
+
125
QAPI_LIST_PREPEND(*cpu_list, info);
126
}
127
128
--
129
2.40.0
diff view generated by jsdifflib
[PULL 01/16] target/riscv: fix vs() to return proper error code
[PULL 86/89] target/riscv: Restore the predicate() NULL check behavior
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Bin Meng <bmeng@tinylab.org>
2
2
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
3
When reading a non-existent CSR QEMU should raise illegal instruction
4
is not enabled.
4
exception, but currently it just exits due to the g_assert() check.
5
5
6
If -1 is returned, exception will be raised and cs->exception_index will
6
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
7
be set to the negative return value. The exception will then be treated
7
Some comments are also added to indicate that predicate() must be
8
as an instruction access fault instead of illegal instruction fault.
8
provided for an implemented CSR.
9
9
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
10
Reported-by: Fei Wu <fei2.wu@intel.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Bin Meng <bmeng@tinylab.org>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
15
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
16
Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
18
---
16
target/riscv/csr.c | 2 +-
19
target/riscv/csr.c | 11 +++++++++--
17
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 9 insertions(+), 2 deletions(-)
18
21
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
22
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
24
--- a/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
25
+++ b/target/riscv/csr.c
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
26
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
24
if (env->misa & RVV) {
27
return RISCV_EXCP_ILLEGAL_INST;
25
return 0;
26
}
28
}
27
- return -1;
29
28
+ return -RISCV_EXCP_ILLEGAL_INST;
30
+ /* ensure CSR is implemented by checking predicate */
31
+ if (!csr_ops[csrno].predicate) {
32
+ return RISCV_EXCP_ILLEGAL_INST;
33
+ }
34
+
35
/* privileged spec version check */
36
if (env->priv_ver < csr_min_priv) {
37
return RISCV_EXCP_ILLEGAL_INST;
38
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
39
* illegal instruction exception should be triggered instead of virtual
40
* instruction exception. Hence this comes after the read / write check.
41
*/
42
- g_assert(csr_ops[csrno].predicate != NULL);
43
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
44
if (ret != RISCV_EXCP_NONE) {
45
return ret;
46
@@ -XXX,XX +XXX,XX @@ static RISCVException write_jvt(CPURISCVState *env, int csrno,
47
return RISCV_EXCP_NONE;
29
}
48
}
30
49
31
static int ctr(CPURISCVState *env, int csrno)
50
-/* Control and Status Register function table */
51
+/*
52
+ * Control and Status Register function table
53
+ * riscv_csr_operations::predicate() must be provided for an implemented CSR
54
+ */
55
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
56
/* User Floating-Point CSRs */
57
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
32
--
58
--
33
2.30.1
59
2.40.0
34
35
diff view generated by jsdifflib
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
[PULL 87/89] target/riscv: Fix Guest Physical Address Translation
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
2
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
3
Before changing the flow check for sv39/48/57.
4
the newest received byte. The rx_level variable is added to allow the use of
5
the existing OpenTitan driver libraries.
6
4
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
5
According to specification (for Supervisor mode):
6
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
7
pages.
8
Instruction fetch addresses and load and store effective addresses, which are
9
64 bits,
10
must have bits 63–39 all equal to bit 38, or else a page-fault exception will
11
occur.
12
Likewise for Sv48 and Sv57.
13
14
So the high bits are equal to bit 38 for sv39.
15
16
According to specification (for Hypervisor mode):
17
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
18
or else a
19
guest-page-fault exception occurs.
20
21
Likewise for Sv48x4 and Sv57x4.
22
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault
23
exception occurs.
24
For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault
25
exception occurs.
26
27
For example we are trying to access address 0xffff_ffff_ff01_0000 with only
28
G-translation enabled.
29
So expected behavior is to generate exception. But qemu doesn't generate such
30
exception.
31
32
For the old check, we get
33
va_bits == 41, mask == (1 << 24) - 1, masked_msbs == (0xffff_ffff_ff01_0000 >>
34
40) & mask == mask.
35
Accordingly, the condition masked_msbs != 0 && masked_msbs != mask is not
36
fulfilled
37
and the check passes.
38
39
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
40
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
41
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
42
Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
43
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
44
---
12
include/hw/char/ibex_uart.h | 4 ++++
45
target/riscv/cpu_helper.c | 25 ++++++++++++++++---------
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
46
1 file changed, 16 insertions(+), 9 deletions(-)
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
47
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
48
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
50
--- a/target/riscv/cpu_helper.c
19
+++ b/include/hw/char/ibex_uart.h
51
+++ b/target/riscv/cpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
52
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
53
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
54
CPUState *cs = env_cpu(env);
23
REG32(FIFO_STATUS, 0x20)
55
int va_bits = PGSHIFT + levels * ptidxbits + widened;
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
56
- target_ulong mask, masked_msbs;
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
57
26
REG32(OVRD, 0x24)
58
- if (TARGET_LONG_BITS > (va_bits - 1)) {
27
REG32(VAL, 0x28)
59
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
28
REG32(TIMEOUT_CTRL, 0x2c)
60
- } else {
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
61
- mask = 0;
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
62
- }
31
uint32_t tx_level;
63
- masked_msbs = (addr >> (va_bits - 1)) & mask;
32
64
+ if (first_stage == true) {
33
+ uint32_t rx_level;
65
+ target_ulong mask, masked_msbs;
66
67
- if (masked_msbs != 0 && masked_msbs != mask) {
68
- return TRANSLATE_FAIL;
69
+ if (TARGET_LONG_BITS > (va_bits - 1)) {
70
+ mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
71
+ } else {
72
+ mask = 0;
73
+ }
74
+ masked_msbs = (addr >> (va_bits - 1)) & mask;
34
+
75
+
35
QEMUTimer *fifo_trigger_handle;
76
+ if (masked_msbs != 0 && masked_msbs != mask) {
36
uint64_t char_tx_time;
77
+ return TRANSLATE_FAIL;
37
78
+ }
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
79
+ } else {
39
index XXXXXXX..XXXXXXX 100644
80
+ if (vm != VM_1_10_SV32 && addr >> va_bits != 0) {
40
--- a/hw/char/ibex_uart.c
81
+ return TRANSLATE_FAIL;
41
+++ b/hw/char/ibex_uart.c
82
+ }
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
43
{
44
IbexUartState *s = opaque;
45
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
49
return 1;
50
}
83
}
51
84
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
85
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
53
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
+ /* The RXFULL is set after receiving a single byte
57
+ * as the FIFO buffers are not yet implemented.
58
+ */
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
+ s->rx_level += 1;
61
62
if (size > rx_fifo_level) {
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
s->uart_timeout_ctrl = 0x00000000;
66
67
s->tx_level = 0;
68
+ s->rx_level = 0;
69
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
74
case R_RDATA:
75
retvalue = s->uart_rdata;
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
qemu_chr_fe_accept_input(&s->chr);
79
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ s->rx_level -= 1;
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ if (s->rx_level == 0) {
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
+ }
88
}
89
break;
90
case R_WDATA:
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
86
--
110
2.30.1
87
2.40.0
111
88
112
89
diff view generated by jsdifflib
New patch
[PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed
1
From: Alexandre Ghiti <alexghiti@rivosinc.com>
1
2
3
As per the specification, in 64-bit, if any of the pte reserved bits
4
60-54 is set an exception should be triggered (see 4.4.1, "Addressing and
5
Memory Protection"). In addition, we must check the napot/pbmt bits are
6
not set if those extensions are not active.
7
8
Reported-by: Andrea Parri <andrea@rivosinc.com>
9
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/cpu_bits.h | 1 +
15
target/riscv/cpu_helper.c | 15 +++++++++++----
16
2 files changed, 12 insertions(+), 4 deletions(-)
17
18
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/cpu_bits.h
21
+++ b/target/riscv/cpu_bits.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
23
#define PTE_SOFT 0x300 /* Reserved for Software */
24
#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
25
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
26
+#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
27
#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
28
29
/* Page table PPN shift amount */
30
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/cpu_helper.c
33
+++ b/target/riscv/cpu_helper.c
34
@@ -XXX,XX +XXX,XX @@ restart:
35
36
if (riscv_cpu_sxl(env) == MXL_RV32) {
37
ppn = pte >> PTE_PPN_SHIFT;
38
- } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
39
- ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
40
} else {
41
- ppn = pte >> PTE_PPN_SHIFT;
42
- if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
43
+ if (pte & PTE_RESERVED) {
44
+ return TRANSLATE_FAIL;
45
+ }
46
+
47
+ if (!pbmte && (pte & PTE_PBMT)) {
48
return TRANSLATE_FAIL;
49
}
50
+
51
+ if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
52
+ return TRANSLATE_FAIL;
53
+ }
54
+
55
+ ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
56
}
57
58
if (!(pte & PTE_V)) {
59
--
60
2.40.0
diff view generated by jsdifflib
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
[PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Rahul Pathak <rpathak@ventanamicro.com>
2
2
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
3
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
4
the address bytes. Note only SPI mode is supported by SST flashes.
4
exclusively for the rv64 target. It's tested with the 'virt' board.
5
5
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
6
CPU specs and general information can be found here:
7
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
9
10
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
11
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
12
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
14
Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
16
---
13
hw/block/m25p80.c | 3 +++
17
target/riscv/cpu-qom.h | 1 +
14
1 file changed, 3 insertions(+)
18
target/riscv/cpu_vendorid.h | 4 ++++
19
target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++
20
3 files changed, 43 insertions(+)
15
21
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
22
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
24
--- a/target/riscv/cpu-qom.h
19
+++ b/hw/block/m25p80.c
25
+++ b/target/riscv/cpu-qom.h
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
26
@@ -XXX,XX +XXX,XX @@
21
s->needed_bytes = get_addr_length(s);
27
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
22
switch (get_man(s)) {
28
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
23
/* Dummy cycles - modeled with bytes writes instead of bits */
29
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
24
+ case MAN_SST:
30
+#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
25
+ s->needed_bytes += 1;
31
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
26
+ break;
32
27
case MAN_WINBOND:
33
#if defined(TARGET_RISCV32)
28
s->needed_bytes += 8;
34
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
29
break;
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu_vendorid.h
37
+++ b/target/riscv/cpu_vendorid.h
38
@@ -XXX,XX +XXX,XX @@
39
40
#define THEAD_VENDOR_ID 0x5b7
41
42
+#define VEYRON_V1_MARCHID 0x8000000000010000
43
+#define VEYRON_V1_MIMPID 0x111
44
+#define VEYRON_V1_MVENDORID 0x61f
45
+
46
#endif /* TARGET_RISCV_CPU_VENDORID_H */
47
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/cpu.c
50
+++ b/target/riscv/cpu.c
51
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
52
#endif
53
}
54
55
+static void rv64_veyron_v1_cpu_init(Object *obj)
56
+{
57
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
58
+ RISCVCPU *cpu = RISCV_CPU(obj);
59
+
60
+ set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
61
+ env->priv_ver = PRIV_VERSION_1_12_0;
62
+
63
+ /* Enable ISA extensions */
64
+ cpu->cfg.mmu = true;
65
+ cpu->cfg.ext_icbom = true;
66
+ cpu->cfg.cbom_blocksize = 64;
67
+ cpu->cfg.cboz_blocksize = 64;
68
+ cpu->cfg.ext_icboz = true;
69
+ cpu->cfg.ext_smaia = true;
70
+ cpu->cfg.ext_ssaia = true;
71
+ cpu->cfg.ext_sscofpmf = true;
72
+ cpu->cfg.ext_sstc = true;
73
+ cpu->cfg.ext_svinval = true;
74
+ cpu->cfg.ext_svnapot = true;
75
+ cpu->cfg.ext_svpbmt = true;
76
+ cpu->cfg.ext_smstateen = true;
77
+ cpu->cfg.ext_zba = true;
78
+ cpu->cfg.ext_zbb = true;
79
+ cpu->cfg.ext_zbc = true;
80
+ cpu->cfg.ext_zbs = true;
81
+ cpu->cfg.ext_XVentanaCondOps = true;
82
+
83
+ cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
84
+ cpu->cfg.marchid = VEYRON_V1_MARCHID;
85
+ cpu->cfg.mimpid = VEYRON_V1_MIMPID;
86
+
87
+#ifndef CONFIG_USER_ONLY
88
+ set_satp_mode_max_supported(cpu, VM_1_10_SV48);
89
+#endif
90
+}
91
+
92
static void rv128_base_cpu_init(Object *obj)
93
{
94
if (qemu_tcg_mttcg_enabled()) {
95
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
96
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
97
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
98
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
99
+ DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
100
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
101
#endif
102
};
30
--
103
--
31
2.30.1
104
2.40.0
32
33
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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