[PULL 00/16] riscv-to-apply queue
[PULL v2 00/19] riscv-to-apply queue
1
The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
3
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
4
5
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging (2022-06-30 22:04:12 +0530)
4
6
5
are available in the Git repository at:
7
are available in the Git repository at:
6
8
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220703-1
8
10
9
for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
11
for you to fetch changes up to 435774992e82d2d16f025afbb20b4f7be9b242b0:
10
12
11
target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
13
target/riscv: Update default priority table for local interrupts (2022-07-03 10:03:20 +1000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
RISC-V PR for 6.0
16
Fifth RISC-V PR for QEMU 7.1
15
17
16
This PR includes:
18
* Fix register zero guarding for auipc and lui
17
- Fix for vector CSR access
19
* Ensure bins (mtval) is set correctly
18
- Improvements to the Ibex UART device
20
* Minimize the calls to decode_save_opc
19
- PMP improvements and bug fixes
21
* Guard against PMP ranges with a negative size
20
- Hypervisor extension bug fixes
22
* Implement mcountinhibit CSR
21
- ramfb support for the virt machine
23
* Add support for hpmcounters/hpmevents
22
- Fast read support for SST flash
24
* Improve PMU implenentation
23
- Improvements to the microchip_pfsoc machine
25
* Support mcycle/minstret write operation
26
* Fixup MSECCFG minimum priv check
27
* Ibex (OpenTitan) fixup priv version
28
* Fix bug resulting in always using latest priv spec
29
* Reduce FDT address alignment constraints
30
* Set minumum priv spec version for mcountinhibit
31
* AIA update to v0.3 of the spec
24
32
25
----------------------------------------------------------------
33
----------------------------------------------------------------
26
Alexander Wagner (1):
34
Alistair Francis (3):
27
hw/char: disable ibex uart receive if the buffer is full
35
target/riscv: Fixup MSECCFG minimum priv check
36
target/riscv: Ibex: Support priv version 1.11
37
hw/riscv: boot: Reduce FDT address alignment constraints
28
38
29
Asherah Connor (2):
39
Anup Patel (4):
30
hw/riscv: Add fw_cfg support to virt
40
target/riscv: Don't force update priv spec version to latest
31
hw/riscv: allow ramfb on virt
41
target/riscv: Set minumum priv spec version for mcountinhibit
42
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
43
target/riscv: Update default priority table for local interrupts
32
44
33
Bin Meng (3):
45
Atish Patra (7):
34
hw/block: m25p80: Support fast read for SST flashes
46
target/riscv: Fix PMU CSR predicate function
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
47
target/riscv: Implement PMU CSR predicate function for S-mode
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
48
target/riscv: pmu: Rename the counters extension to pmu
49
target/riscv: pmu: Make number of counters configurable
50
target/riscv: Implement mcountinhibit CSR
51
target/riscv: Add support for hpmcounters/hpmevents
52
target/riscv: Support mcycle/minstret write operation
37
53
38
Frank Chang (1):
54
Nicolas Pitre (1):
39
target/riscv: fix vs() to return proper error code
55
target/riscv/pmp: guard against PMP ranges with a negative size
40
56
41
Georg Kotheimer (6):
57
Richard Henderson (3):
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
58
target/riscv: Set env->bins in gen_exception_illegal
43
target/riscv: Make VSTIP and VSEIP read-only in hip
59
target/riscv: Remove generate_exception_mtval
44
target/riscv: Use background registers also for MSTATUS_MPV
60
target/riscv: Minimize the calls to decode_save_opc
45
target/riscv: Fix read and write accesses to vsip and vsie
46
target/riscv: Add proper two-stage lookup exception detection
47
target/riscv: Prevent lost illegal instruction exceptions
48
61
49
Jim Shu (3):
62
Víctor Colombo (1):
50
target/riscv: propagate PMP permission to TLB page
63
target/riscv: Remove condition guarding register zero for auipc and lui
51
target/riscv: add log of PMP permission checking
52
target/riscv: flush TLB pages if PMP permission has been changed
53
64
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
65
target/riscv/cpu.h | 24 +-
55
docs/system/target-riscv.rst | 1 +
66
target/riscv/cpu_bits.h | 30 +-
56
include/hw/char/ibex_uart.h | 4 +
67
target/riscv/pmu.h | 28 +
57
include/hw/riscv/microchip_pfsoc.h | 1 +
68
hw/riscv/boot.c | 4 +-
58
include/hw/riscv/virt.h | 2 +
69
target/riscv/cpu.c | 17 +-
59
target/riscv/cpu.h | 4 +
70
target/riscv/cpu_helper.c | 134 ++--
60
target/riscv/pmp.h | 4 +-
71
target/riscv/csr.c | 857 +++++++++++++++----------
61
hw/block/m25p80.c | 3 +
72
target/riscv/machine.c | 25 +
62
hw/char/ibex_uart.c | 23 +++-
73
target/riscv/pmp.c | 3 +
63
hw/riscv/microchip_pfsoc.c | 6 +
74
target/riscv/pmu.c | 32 +
64
hw/riscv/virt.c | 33 ++++++
75
target/riscv/translate.c | 31 +-
65
target/riscv/cpu.c | 1 +
76
target/riscv/insn_trans/trans_privileged.c.inc | 4 +
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
77
target/riscv/insn_trans/trans_rvh.c.inc | 2 +
67
target/riscv/csr.c | 77 +++++++------
78
target/riscv/insn_trans/trans_rvi.c.inc | 10 +-
68
target/riscv/pmp.c | 84 ++++++++++----
79
target/riscv/meson.build | 3 +-
69
target/riscv/translate.c | 179 +----------------------------
80
tests/tcg/riscv64/Makefile.softmmu-target | 21 +
70
hw/riscv/Kconfig | 1 +
81
tests/tcg/riscv64/issue1060.S | 53 ++
71
17 files changed, 367 insertions(+), 289 deletions(-)
82
tests/tcg/riscv64/semihost.ld | 21 +
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
83
18 files changed, 843 insertions(+), 456 deletions(-)
73
84
create mode 100644 target/riscv/pmu.h
85
create mode 100644 target/riscv/pmu.c
86
create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
87
create mode 100644 tests/tcg/riscv64/issue1060.S
88
create mode 100644 tests/tcg/riscv64/semihost.ld
diff view generated by jsdifflib
New patch
[PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui
1
From: Víctor Colombo <victor.colombo@eldorado.org.br>
1
2
3
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
4
a check for if the destination register is 'zero'. The check in auipc
5
and lui are then redundant. This patch removes those checks.
6
7
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
14
1 file changed, 2 insertions(+), 6 deletions(-)
15
16
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn_trans/trans_rvi.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
21
22
static bool trans_lui(DisasContext *ctx, arg_lui *a)
23
{
24
- if (a->rd != 0) {
25
- gen_set_gpri(ctx, a->rd, a->imm);
26
- }
27
+ gen_set_gpri(ctx, a->rd, a->imm);
28
return true;
29
}
30
31
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
32
{
33
- if (a->rd != 0) {
34
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
35
- }
36
+ gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
37
return true;
38
}
39
40
--
41
2.36.1
diff view generated by jsdifflib
New patch
[PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
While we set env->bins when unwinding for ILLEGAL_INST,
4
from e.g. csrrw, we weren't setting it for immediately
5
illegal instructions.
6
7
Add a testcase for mtval via both exception paths.
8
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/translate.c | 2 +
16
tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++
17
tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++++++
18
tests/tcg/riscv64/semihost.ld | 21 +++++++++
19
4 files changed, 97 insertions(+)
20
create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
21
create mode 100644 tests/tcg/riscv64/issue1060.S
22
create mode 100644 tests/tcg/riscv64/semihost.ld
23
24
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/translate.c
27
+++ b/target/riscv/translate.c
28
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
29
30
static void gen_exception_illegal(DisasContext *ctx)
31
{
32
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
33
+ offsetof(CPURISCVState, bins));
34
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
35
}
36
37
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
38
new file mode 100644
39
index XXXXXXX..XXXXXXX
40
--- /dev/null
41
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
42
@@ -XXX,XX +XXX,XX @@
43
+#
44
+# RISC-V system tests
45
+#
46
+
47
+TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
48
+VPATH += $(TEST_SRC)
49
+
50
+LINK_SCRIPT = $(TEST_SRC)/semihost.ld
51
+LDFLAGS = -T $(LINK_SCRIPT)
52
+CFLAGS += -g -Og
53
+
54
+%.o: %.S
55
+    $(CC) $(CFLAGS) $< -c -o $@
56
+%: %.o $(LINK_SCRIPT)
57
+    $(LD) $(LDFLAGS) $< -o $@
58
+
59
+QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
60
+
61
+EXTRA_RUNS += run-issue1060
62
+run-issue1060: issue1060
63
+    $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
64
diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/tests/tcg/riscv64/issue1060.S
69
@@ -XXX,XX +XXX,XX @@
70
+    .option    norvc
71
+
72
+    .text
73
+    .global _start
74
+_start:
75
+    lla    t0, trap
76
+    csrw    mtvec, t0
77
+
78
+    # These are all illegal instructions
79
+    csrw    time, x0
80
+    .insn    i CUSTOM_0, 0, x0, x0, 0x321
81
+    csrw    time, x0
82
+    .insn    i CUSTOM_0, 0, x0, x0, 0x123
83
+    csrw    cycle, x0
84
+
85
+    # Success!
86
+    li    a0, 0
87
+    j    _exit
88
+
89
+trap:
90
+    # When an instruction traps, compare it to the insn in memory.
91
+    csrr    t0, mepc
92
+    csrr    t1, mtval
93
+    lwu    t2, 0(t0)
94
+    bne    t1, t2, fail
95
+
96
+    # Skip the insn and continue.
97
+    addi    t0, t0, 4
98
+    csrw    mepc, t0
99
+    mret
100
+
101
+fail:
102
+    li    a0, 1
103
+
104
+# Exit code in a0
105
+_exit:
106
+    lla    a1, semiargs
107
+    li    t0, 0x20026    # ADP_Stopped_ApplicationExit
108
+    sd    t0, 0(a1)
109
+    sd    a0, 8(a1)
110
+    li    a0, 0x20    # TARGET_SYS_EXIT_EXTENDED
111
+
112
+    # Semihosting call sequence
113
+    .balign    16
114
+    slli    zero, zero, 0x1f
115
+    ebreak
116
+    srai    zero, zero, 0x7
117
+    j    .
118
+
119
+    .data
120
+    .balign    16
121
+semiargs:
122
+    .space    16
123
diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld
124
new file mode 100644
125
index XXXXXXX..XXXXXXX
126
--- /dev/null
127
+++ b/tests/tcg/riscv64/semihost.ld
128
@@ -XXX,XX +XXX,XX @@
129
+ENTRY(_start)
130
+
131
+SECTIONS
132
+{
133
+ /* virt machine, RAM starts at 2gb */
134
+ . = 0x80000000;
135
+ .text : {
136
+ *(.text)
137
+ }
138
+ .rodata : {
139
+ *(.rodata)
140
+ }
141
+ /* align r/w section to next 2mb */
142
+ . = ALIGN(1 << 21);
143
+ .data : {
144
+ *(.data)
145
+ }
146
+ .bss : {
147
+ *(.bss)
148
+ }
149
+}
150
--
151
2.36.1
diff view generated by jsdifflib
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
[PULL v2 03/19] target/riscv: Remove generate_exception_mtval
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
3
The function doesn't set mtval, it sets badaddr. Move the set
4
further compressed instruction decoding. However, prior to this change,
4
of badaddr directly into gen_exception_inst_addr_mis and use
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
5
generate_exception.
6
fails to decode the instruction. This means that we skipped illegal
7
compressed instructions instead of raising an illegal instruction
8
exception.
9
6
10
Instead of patching decode_RV32_64C(), we can just remove it,
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
as it is dead code since f330433b363 anyway.
12
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
11
---
19
target/riscv/translate.c | 179 +--------------------------------------
12
target/riscv/translate.c | 11 ++---------
20
1 file changed, 1 insertion(+), 178 deletions(-)
13
1 file changed, 2 insertions(+), 9 deletions(-)
21
14
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
15
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
17
--- a/target/riscv/translate.c
25
+++ b/target/riscv/translate.c
18
+++ b/target/riscv/translate.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
19
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
27
CPUState *cs;
28
} DisasContext;
29
30
-#ifdef TARGET_RISCV64
31
-/* convert riscv funct3 to qemu memop for load/store */
32
-static const int tcg_memop_lookup[8] = {
33
- [0 ... 7] = -1,
34
- [0] = MO_SB,
35
- [1] = MO_TESW,
36
- [2] = MO_TESL,
37
- [3] = MO_TEQ,
38
- [4] = MO_UB,
39
- [5] = MO_TEUW,
40
- [6] = MO_TEUL,
41
-};
42
-#endif
43
-
44
#ifdef TARGET_RISCV64
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
46
#else
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
48
ctx->base.is_jmp = DISAS_NORETURN;
20
ctx->base.is_jmp = DISAS_NORETURN;
49
}
21
}
50
22
51
-#ifdef TARGET_RISCV64
23
-static void generate_exception_mtval(DisasContext *ctx, int excp)
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
53
- target_long imm)
54
-{
24
-{
55
- TCGv t0 = tcg_temp_new();
25
- gen_set_pc_imm(ctx, ctx->base.pc_next);
56
- TCGv t1 = tcg_temp_new();
26
- tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
57
- gen_get_gpr(t0, rs1);
27
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
58
- tcg_gen_addi_tl(t0, t0, imm);
28
- ctx->base.is_jmp = DISAS_NORETURN;
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
60
-
61
- if (memop < 0) {
62
- gen_exception_illegal(ctx);
63
- return;
64
- }
65
-
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
67
- gen_set_gpr(rd, t1);
68
- tcg_temp_free(t0);
69
- tcg_temp_free(t1);
70
-}
29
-}
71
-
30
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
31
static void gen_exception_illegal(DisasContext *ctx)
73
- target_long imm)
74
-{
75
- TCGv t0 = tcg_temp_new();
76
- TCGv dat = tcg_temp_new();
77
- gen_get_gpr(t0, rs1);
78
- tcg_gen_addi_tl(t0, t0, imm);
79
- gen_get_gpr(dat, rs2);
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
81
-
82
- if (memop < 0) {
83
- gen_exception_illegal(ctx);
84
- return;
85
- }
86
-
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
88
- tcg_temp_free(t0);
89
- tcg_temp_free(dat);
90
-}
91
-#endif
92
-
93
#ifndef CONFIG_USER_ONLY
94
/* The states of mstatus_fs are:
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
98
#endif
99
100
-#if !defined(TARGET_RISCV64)
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
102
- int rs1, target_long imm)
103
-{
104
- TCGv t0;
105
-
106
- if (ctx->mstatus_fs == 0) {
107
- gen_exception_illegal(ctx);
108
- return;
109
- }
110
-
111
- t0 = tcg_temp_new();
112
- gen_get_gpr(t0, rs1);
113
- tcg_gen_addi_tl(t0, t0, imm);
114
-
115
- switch (opc) {
116
- case OPC_RISC_FLW:
117
- if (!has_ext(ctx, RVF)) {
118
- goto do_illegal;
119
- }
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
123
- break;
124
- case OPC_RISC_FLD:
125
- if (!has_ext(ctx, RVD)) {
126
- goto do_illegal;
127
- }
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
129
- break;
130
- do_illegal:
131
- default:
132
- gen_exception_illegal(ctx);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
139
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
141
- int rs2, target_long imm)
142
-{
143
- TCGv t0;
144
-
145
- if (ctx->mstatus_fs == 0) {
146
- gen_exception_illegal(ctx);
147
- return;
148
- }
149
-
150
- t0 = tcg_temp_new();
151
- gen_get_gpr(t0, rs1);
152
- tcg_gen_addi_tl(t0, t0, imm);
153
-
154
- switch (opc) {
155
- case OPC_RISC_FSW:
156
- if (!has_ext(ctx, RVF)) {
157
- goto do_illegal;
158
- }
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
32
{
179
TCGv_i32 t0;
33
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
34
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
181
tcg_temp_free_i32(t0);
35
36
static void gen_exception_inst_addr_mis(DisasContext *ctx)
37
{
38
- generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
39
+ tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
40
+ generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
182
}
41
}
183
42
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
43
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
185
-{
186
- uint8_t funct3 = extract16(opcode, 13, 3);
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
188
- uint8_t rs1s = GET_C_RS1S(opcode);
189
-
190
- switch (funct3) {
191
- case 3:
192
-#if defined(TARGET_RISCV64)
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
195
- GET_C_LD_IMM(opcode));
196
-#else
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
199
- GET_C_LW_IMM(opcode));
200
-#endif
201
- break;
202
- case 7:
203
-#if defined(TARGET_RISCV64)
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
206
- GET_C_LD_IMM(opcode));
207
-#else
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
210
- GET_C_LW_IMM(opcode));
211
-#endif
212
- break;
213
- }
214
-}
215
-
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
229
return nf + 1;
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
231
} else {
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
233
if (!decode_insn16(ctx, opcode)) {
234
- /* fall back to old decoder */
235
- decode_RV32_64C(ctx, opcode);
236
+ gen_exception_illegal(ctx);
237
}
238
}
239
} else {
240
--
44
--
241
2.30.1
45
2.36.1
242
243
diff view generated by jsdifflib
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
[PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Provides fw_cfg for the virt machine on riscv. This enables
3
The set of instructions that require decode_save_opc for
4
using e.g. ramfb later.
4
unwinding is really fairly small -- only insns that can
5
raise ILLEGAL_INSN at runtime. This includes CSR, anything
6
that uses a *new* fp rounding mode, and many privileged insns.
5
7
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
8
Since unwind info is stored as the difference from the
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
previous insn, storing a 0 for most insns minimizes the
10
size of the unwind info.
11
12
Booting a debian kernel image to the missing rootfs panic yields
13
14
- gen code size 22226819/1026886656
15
+ gen code size 21601907/1026886656
16
17
on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.
18
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
20
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
21
Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
23
---
12
include/hw/riscv/virt.h | 2 ++
24
target/riscv/translate.c | 18 +++++++++---------
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
25
target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
14
hw/riscv/Kconfig | 1 +
26
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
15
3 files changed, 33 insertions(+)
27
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
28
4 files changed, 17 insertions(+), 9 deletions(-)
16
29
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
30
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
18
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
32
--- a/target/riscv/translate.c
20
+++ b/include/hw/riscv/virt.h
33
+++ b/target/riscv/translate.c
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
34
@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
35
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
23
DeviceState *plic[VIRT_SOCKETS_MAX];
24
PFlashCFI01 *flash[2];
25
+ FWCfgState *fw_cfg;
26
27
int fdt_size;
28
};
29
@@ -XXX,XX +XXX,XX @@ enum {
30
VIRT_PLIC,
31
VIRT_UART0,
32
VIRT_VIRTIO,
33
+ VIRT_FW_CFG,
34
VIRT_FLASH,
35
VIRT_DRAM,
36
VIRT_PCIE_MMIO,
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/riscv/virt.c
40
+++ b/hw/riscv/virt.c
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
43
[VIRT_UART0] = { 0x10000000, 0x100 },
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
50
return dev;
51
}
36
}
52
37
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
38
+static void decode_save_opc(DisasContext *ctx)
54
+{
39
+{
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
40
+ assert(ctx->insn_start != NULL);
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
41
+ tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
57
+ FWCfgState *fw_cfg;
42
+ ctx->insn_start = NULL;
58
+ char *nodename;
59
+
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
61
+ &address_space_memory);
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
63
+
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
67
+ "compatible", "qemu,fw-cfg-mmio");
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
73
+}
43
+}
74
+
44
+
75
static void virt_machine_init(MachineState *machine)
45
static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
76
{
46
{
77
const MemMapEntry *memmap = virt_memmap;
47
if (get_xl(ctx) == MXL_RV32) {
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
48
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
79
start_addr = virt_memmap[VIRT_FLASH].base;
49
return;
80
}
50
}
81
51
82
+ /*
52
+ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
53
+ decode_save_opc(ctx);
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
54
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
85
+ */
55
}
86
+ s->fw_cfg = create_fw_cfg(machine);
56
87
+ rom_set_fw(s->fw_cfg);
57
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
88
+
58
/* Include decoders for factored-out extensions */
89
/* Compute the fdt load address in dram */
59
#include "decode-XVentanaCondOps.c.inc"
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
60
91
machine->ram_size, machine->fdt);
61
-static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
62
-{
63
- assert(ctx->insn_start != NULL);
64
- tcg_set_insn_start_param(ctx->insn_start, 1, opc);
65
- ctx->insn_start = NULL;
66
-}
67
-
68
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
69
{
70
/*
71
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
72
73
/* Check for compressed insn */
74
if (extract16(opcode, 0, 2) != 3) {
75
- decode_save_opc(ctx, opcode);
76
if (!has_ext(ctx, RVC)) {
77
gen_exception_illegal(ctx);
78
} else {
79
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
80
opcode32 = deposit32(opcode32, 16, 16,
81
translator_lduw(env, &ctx->base,
82
ctx->base.pc_next + 2));
83
- decode_save_opc(ctx, opcode32);
84
ctx->opcode = opcode32;
85
ctx->pc_succ_insn = ctx->base.pc_next + 4;
86
87
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
93
index XXXXXXX..XXXXXXX 100644
88
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/riscv/Kconfig
89
--- a/target/riscv/insn_trans/trans_privileged.c.inc
95
+++ b/hw/riscv/Kconfig
90
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
91
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
97
select SIFIVE_PLIC
92
{
98
select SIFIVE_TEST
93
#ifndef CONFIG_USER_ONLY
99
select VIRTIO_MMIO
94
if (has_ext(ctx, RVS)) {
100
+ select FW_CFG_DMA
95
+ decode_save_opc(ctx);
101
96
gen_helper_sret(cpu_pc, cpu_env);
102
config SIFIVE_E
97
tcg_gen_exit_tb(NULL, 0); /* no chaining */
103
bool
98
ctx->base.is_jmp = DISAS_NORETURN;
99
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
100
static bool trans_mret(DisasContext *ctx, arg_mret *a)
101
{
102
#ifndef CONFIG_USER_ONLY
103
+ decode_save_opc(ctx);
104
gen_helper_mret(cpu_pc, cpu_env);
105
tcg_gen_exit_tb(NULL, 0); /* no chaining */
106
ctx->base.is_jmp = DISAS_NORETURN;
107
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
108
static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
109
{
110
#ifndef CONFIG_USER_ONLY
111
+ decode_save_opc(ctx);
112
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
113
gen_helper_wfi(cpu_env);
114
return true;
115
@@ -XXX,XX +XXX,XX @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
116
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
117
{
118
#ifndef CONFIG_USER_ONLY
119
+ decode_save_opc(ctx);
120
gen_helper_tlb_flush(cpu_env);
121
return true;
122
#endif
123
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
124
index XXXXXXX..XXXXXXX 100644
125
--- a/target/riscv/insn_trans/trans_rvh.c.inc
126
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
127
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
128
{
129
REQUIRE_EXT(ctx, RVH);
130
#ifndef CONFIG_USER_ONLY
131
+ decode_save_opc(ctx);
132
gen_helper_hyp_gvma_tlb_flush(cpu_env);
133
return true;
134
#endif
135
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
136
{
137
REQUIRE_EXT(ctx, RVH);
138
#ifndef CONFIG_USER_ONLY
139
+ decode_save_opc(ctx);
140
gen_helper_hyp_tlb_flush(cpu_env);
141
return true;
142
#endif
143
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
144
index XXXXXXX..XXXXXXX 100644
145
--- a/target/riscv/insn_trans/trans_rvi.c.inc
146
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
147
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
148
149
static bool do_csr_post(DisasContext *ctx)
150
{
151
+ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
152
+ decode_save_opc(ctx);
153
/* We may have changed important cpu state -- exit to main loop. */
154
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
155
tcg_gen_exit_tb(NULL, 0);
104
--
156
--
105
2.30.1
157
2.36.1
106
107
diff view generated by jsdifflib
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
[PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size
1
From: Jim Shu <cwshu@andestech.com>
1
From: Nicolas Pitre <nico@fluxnic.net>
2
2
3
If PMP permission of any address has been changed by updating PMP entry,
3
For a TOR entry to match, the stard address must be lower than the end
4
flush all TLB pages to prevent from getting old permission.
4
address. Normally this is always the case, but correct code might still
5
run into the following scenario:
5
6
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
7
Initial state:
8
9
    pmpaddr3 = 0x2000    pmp3cfg = OFF
10
    pmpaddr4 = 0x3000    pmp4cfg = TOR
11
12
Execution:
13
14
    1. write 0x40ff to pmpaddr3
15
    2. write 0x32ff to pmpaddr4
16
    3. set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0
17
    4. set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1
18
19
When (2) is emulated, a call to pmp_update_rule() creates a negative
20
range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated,
21
a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return
22
a very creatively large TLB size for pmp4. This, in turn, may result in
23
accesses to non-existent/unitialized memory regions and a fault, so that
24
(4) ends up never being executed.
25
26
This is in m-mode with MPRV unset, meaning that unlocked PMP entries
27
should have no effect. Therefore such a behavior based on PMP content
28
is very unexpected.
29
30
Make sure no negative PMP range can be created, whether explicitly by
31
the emulated code or implicitly like the above.
32
33
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
35
Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
36
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
37
---
11
target/riscv/pmp.c | 4 ++++
38
target/riscv/pmp.c | 3 +++
12
1 file changed, 4 insertions(+)
39
1 file changed, 3 insertions(+)
13
40
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
41
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
15
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/pmp.c
43
--- a/target/riscv/pmp.c
17
+++ b/target/riscv/pmp.c
44
+++ b/target/riscv/pmp.c
18
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
19
#include "qapi/error.h"
46
case PMP_AMATCH_TOR:
20
#include "cpu.h"
47
sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
21
#include "trace.h"
48
ea = (this_addr << 2) - 1u;
22
+#include "exec/exec-all.h"
49
+ if (sa > ea) {
23
50
+ sa = ea = 0u;
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
51
+ }
25
uint8_t val);
52
break;
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
53
27
cfg_val = (val >> 8 * i) & 0xff;
54
case PMP_AMATCH_NA4:
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
29
}
30
+
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
32
+ tlb_flush(env_cpu(env));
33
}
34
35
36
--
55
--
37
2.30.1
56
2.36.1
38
39
diff view generated by jsdifflib
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
[PULL v2 06/19] target/riscv: Fix PMU CSR predicate function
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
3
The predicate function calculates the counter index incorrectly for
4
hpmcounterx. Fix the counter index to reflect correct CSR number.
5
6
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Signed-off-by: Atish Patra <atish.patra@wdc.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
13
---
8
target/riscv/csr.c | 7 ++++---
14
target/riscv/csr.c | 11 +++++++----
9
1 file changed, 4 insertions(+), 3 deletions(-)
15
1 file changed, 7 insertions(+), 4 deletions(-)
10
16
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/csr.c
19
--- a/target/riscv/csr.c
14
+++ b/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
21
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
22
#if !defined(CONFIG_USER_ONLY)
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
23
CPUState *cs = env_cpu(env);
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
24
RISCVCPU *cpu = RISCV_CPU(cs);
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
25
+ int ctr_index;
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
26
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
27
if (!cpu->cfg.ext_counters) {
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
28
/* The Counters extensions is not enabled */
23
29
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
24
static const char valid_vm_1_10_32[16] = {
30
}
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
31
break;
26
target_ulong new_value, target_ulong write_mask)
32
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
27
{
33
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
28
int ret = rmw_mip(env, 0, ret_value, new_value,
34
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
29
- write_mask & hip_writable_mask);
35
+ ctr_index = csrno - CSR_CYCLE;
30
+ write_mask & hvip_writable_mask);
36
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
31
37
+ get_field(env->mcounteren, 1 << ctr_index)) {
32
- *ret_value &= hip_writable_mask;
38
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
33
+ *ret_value &= hvip_writable_mask;
39
}
34
40
break;
35
return ret;
41
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
36
}
42
}
43
break;
44
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
45
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
46
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
47
+ ctr_index = csrno - CSR_CYCLEH;
48
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
49
+ get_field(env->mcounteren, 1 << ctr_index)) {
50
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
51
}
52
break;
37
--
53
--
38
2.30.1
54
2.36.1
39
40
diff view generated by jsdifflib
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
[PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
According to the specification the "field SPVP of hstatus controls the
3
Currently, the predicate function for PMU related CSRs only works if
4
privilege level of the access" for the hypervisor virtual-machine load
4
virtualization is enabled. It also does not check mcounteren bits before
5
and store instructions HLV, HLVX and HSV.
5
before cycle/minstret/hpmcounterx access.
6
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
Support supervisor mode access in the predicate function as well.
8
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Signed-off-by: Atish Patra <atish.patra@wdc.com>
12
Signed-off-by: Atish Patra <atishp@rivosinc.com>
13
Message-Id: <20220620231603.2547260-3-atishp@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
16
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 14 insertions(+), 11 deletions(-)
17
1 file changed, 51 insertions(+)
14
18
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
21
--- a/target/riscv/csr.c
18
+++ b/target/riscv/cpu_helper.c
22
+++ b/target/riscv/csr.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
23
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
20
use_background = true;
24
return RISCV_EXCP_ILLEGAL_INST;
21
}
25
}
22
26
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
27
+ if (env->priv == PRV_S) {
24
+ /* MPRV does not affect the virtual-machine load/store
28
+ switch (csrno) {
25
+ instructions, HLV, HLVX, and HSV. */
29
+ case CSR_CYCLE:
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
30
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
31
+ return RISCV_EXCP_ILLEGAL_INST;
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
32
+ }
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
33
+ break;
30
mode = get_field(env->mstatus, MSTATUS_MPP);
34
+ case CSR_TIME:
31
}
35
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
36
+ return RISCV_EXCP_ILLEGAL_INST;
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
37
+ }
34
__func__, address, access_type, mmu_idx);
38
+ break;
35
39
+ case CSR_INSTRET:
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
40
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
41
+ return RISCV_EXCP_ILLEGAL_INST;
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
42
+ }
39
+ /* MPRV does not affect the virtual-machine load/store
43
+ break;
40
+ instructions, HLV, HLVX, and HSV. */
44
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
45
+ ctr_index = csrno - CSR_CYCLE;
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
46
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
47
+ return RISCV_EXCP_ILLEGAL_INST;
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
48
+ }
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
49
+ break;
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
50
+ }
47
+ two_stage_lookup = true;
51
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
48
}
52
+ switch (csrno) {
49
}
53
+ case CSR_CYCLEH:
50
54
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
55
+ return RISCV_EXCP_ILLEGAL_INST;
52
- access_type != MMU_INST_FETCH &&
56
+ }
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
57
+ break;
54
- get_field(env->mstatus, MSTATUS_MPV)) {
58
+ case CSR_TIMEH:
55
- two_stage_lookup = true;
59
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
56
- }
60
+ return RISCV_EXCP_ILLEGAL_INST;
57
-
61
+ }
58
if (riscv_cpu_virt_enabled(env) ||
62
+ break;
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
63
+ case CSR_INSTRETH:
60
access_type != MMU_INST_FETCH)) {
64
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
65
+ return RISCV_EXCP_ILLEGAL_INST;
66
+ }
67
+ break;
68
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
69
+ ctr_index = csrno - CSR_CYCLEH;
70
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
71
+ return RISCV_EXCP_ILLEGAL_INST;
72
+ }
73
+ break;
74
+ }
75
+ }
76
+ }
77
+
78
if (riscv_cpu_virt_enabled(env)) {
79
switch (csrno) {
80
case CSR_CYCLE:
61
--
81
--
62
2.30.1
82
2.36.1
63
64
diff view generated by jsdifflib
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
[PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
The current condition for the use of background registers only
3
The PMU counters are supported via cpu config "Counters" which doesn't
4
considers the hypervisor load and store instructions,
4
indicate the correct purpose of those counters.
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
6
5
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
6
Rename the config property to pmu to indicate that these counters
7
are performance monitoring counters. This aligns with cpu options for
8
ARM architecture as well.
9
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
12
Signed-off-by: Atish Patra <atish.patra@wdc.com>
13
Signed-off-by: Atish Patra <atishp@rivosinc.com>
14
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
target/riscv/cpu_helper.c | 2 +-
17
target/riscv/cpu.h | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
18
target/riscv/cpu.c | 4 ++--
19
target/riscv/csr.c | 4 ++--
20
3 files changed, 5 insertions(+), 5 deletions(-)
14
21
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
24
--- a/target/riscv/cpu.h
18
+++ b/target/riscv/cpu_helper.c
25
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
20
* was called. Background registers will be used if the guest has
27
bool ext_zksed;
21
* forced a two stage translation to be on (in HS or M mode).
28
bool ext_zksh;
22
*/
29
bool ext_zkt;
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
30
- bool ext_counters;
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
31
+ bool ext_pmu;
25
use_background = true;
32
bool ext_ifencei;
33
bool ext_icsr;
34
bool ext_svinval;
35
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu.c
38
+++ b/target/riscv/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
40
{
41
RISCVCPU *cpu = RISCV_CPU(obj);
42
43
- cpu->cfg.ext_counters = true;
44
+ cpu->cfg.ext_pmu = true;
45
cpu->cfg.ext_ifencei = true;
46
cpu->cfg.ext_icsr = true;
47
cpu->cfg.mmu = true;
48
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
49
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
50
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
51
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
52
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
53
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
54
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
55
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
56
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
57
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/csr.c
60
+++ b/target/riscv/csr.c
61
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
62
RISCVCPU *cpu = RISCV_CPU(cs);
63
int ctr_index;
64
65
- if (!cpu->cfg.ext_counters) {
66
- /* The Counters extensions is not enabled */
67
+ if (!cpu->cfg.ext_pmu) {
68
+ /* The PMU extension is not enabled */
69
return RISCV_EXCP_ILLEGAL_INST;
26
}
70
}
27
71
28
--
72
--
29
2.30.1
73
2.36.1
30
31
diff view generated by jsdifflib
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
[PULL v2 09/19] target/riscv: pmu: Make number of counters configurable
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
3
The RISC-V privilege specification provides flexibility to implement
4
short of its purpose, as all it checks is whether two-stage address
4
any number of counters from 29 programmable counters. However, the QEMU
5
translation either via the hypervisor-load store instructions or the
5
implements all the counters.
6
MPRV feature would be allowed.
7
6
8
What we really need instead is whether two-stage address translation was
7
Make it configurable through pmu config parameter which now will indicate
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
8
how many programmable counters should be implemented by the cpu.
10
we do not have the information to reliably detect this. Therefore, when
11
we raise a memory fault exception we have to record whether two-stage
12
address translation is active.
13
9
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
12
Signed-off-by: Atish Patra <atish.patra@wdc.com>
13
Signed-off-by: Atish Patra <atishp@rivosinc.com>
14
Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
16
---
19
target/riscv/cpu.h | 4 ++++
17
target/riscv/cpu.h | 2 +-
20
target/riscv/cpu.c | 1 +
18
target/riscv/cpu.c | 3 +-
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
19
target/riscv/csr.c | 94 ++++++++++++++++++++++++++++++----------------
22
3 files changed, 13 insertions(+), 13 deletions(-)
20
3 files changed, 63 insertions(+), 36 deletions(-)
23
21
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
24
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
29
target_ulong satp_hs;
27
bool ext_zksed;
30
uint64_t mstatus_hs;
28
bool ext_zksh;
31
29
bool ext_zkt;
32
+ /* Signals whether the current exception occurred with two-stage address
30
- bool ext_pmu;
33
+ translation active. */
31
bool ext_ifencei;
34
+ bool two_stage_lookup;
32
bool ext_icsr;
35
+
33
bool ext_svinval;
36
target_ulong scounteren;
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
37
target_ulong mcounteren;
35
/* Vendor-specific custom extensions */
38
36
bool ext_XVentanaCondOps;
37
38
+ uint8_t pmu_num;
39
char *priv_spec;
40
char *user_spec;
41
char *bext_spec;
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
42
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
40
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu.c
44
--- a/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
45
+++ b/target/riscv/cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
46
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
47
{
45
env->mcause = 0;
48
RISCVCPU *cpu = RISCV_CPU(obj);
46
env->pc = env->resetvec;
49
47
+ env->two_stage_lookup = false;
50
- cpu->cfg.ext_pmu = true;
48
#endif
51
cpu->cfg.ext_ifencei = true;
49
cs->exception_index = EXCP_NONE;
52
cpu->cfg.ext_icsr = true;
50
env->load_res = -1;
53
cpu->cfg.mmu = true;
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
55
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
56
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
57
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
58
- DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
59
+ DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
60
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
61
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
62
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
63
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
52
index XXXXXXX..XXXXXXX 100644
64
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
65
--- a/target/riscv/csr.c
54
+++ b/target/riscv/cpu_helper.c
66
+++ b/target/riscv/csr.c
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
67
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
56
g_assert_not_reached();
68
CPUState *cs = env_cpu(env);
69
RISCVCPU *cpu = RISCV_CPU(cs);
70
int ctr_index;
71
+ int base_csrno = CSR_HPMCOUNTER3;
72
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
73
74
- if (!cpu->cfg.ext_pmu) {
75
- /* The PMU extension is not enabled */
76
+ if (rv32 && csrno >= CSR_CYCLEH) {
77
+ /* Offset for RV32 hpmcounternh counters */
78
+ base_csrno += 0x80;
79
+ }
80
+ ctr_index = csrno - base_csrno;
81
+
82
+ if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num)) {
83
+ /* No counter is enabled in PMU or the counter is out of range */
84
return RISCV_EXCP_ILLEGAL_INST;
57
}
85
}
58
env->badaddr = address;
86
59
+ env->two_stage_lookup = two_stage;
87
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
88
}
89
break;
90
}
91
- if (riscv_cpu_mxl(env) == MXL_RV32) {
92
+ if (rv32) {
93
switch (csrno) {
94
case CSR_CYCLEH:
95
if (!get_field(env->mcounteren, COUNTEREN_CY)) {
96
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
97
}
98
break;
99
}
100
- if (riscv_cpu_mxl(env) == MXL_RV32) {
101
+ if (rv32) {
102
switch (csrno) {
103
case CSR_CYCLEH:
104
if (!get_field(env->hcounteren, COUNTEREN_CY) &&
105
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
60
}
106
}
61
107
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
108
#if !defined(CONFIG_USER_ONLY)
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
109
+static RISCVException mctr(CPURISCVState *env, int csrno)
64
}
110
+{
65
111
+ CPUState *cs = env_cpu(env);
66
env->badaddr = addr;
112
+ RISCVCPU *cpu = RISCV_CPU(cs);
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
113
+ int ctr_index;
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
114
+ int base_csrno = CSR_MHPMCOUNTER3;
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
115
+
70
}
116
+ if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) {
71
117
+ /* Offset for RV32 mhpmcounternh counters */
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
118
+ base_csrno += 0x80;
73
g_assert_not_reached();
119
+ }
74
}
120
+ ctr_index = csrno - base_csrno;
75
env->badaddr = addr;
121
+ if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
122
+ /* The PMU is not enabled or counter is out of range*/
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
123
+ return RISCV_EXCP_ILLEGAL_INST;
78
riscv_raise_exception(env, cs->exception_index, retaddr);
124
+ }
79
}
125
+
80
#endif /* !CONFIG_USER_ONLY */
126
+ return RISCV_EXCP_NONE;
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
127
+}
82
/* handle the trap in S-mode */
128
+
83
if (riscv_has_ext(env, RVH)) {
129
static RISCVException any(CPURISCVState *env, int csrno)
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
130
{
85
- bool two_stage_lookup = false;
131
return RISCV_EXCP_NONE;
86
132
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
87
- if (env->priv == PRV_M ||
133
[CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
134
[CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
135
90
- get_field(env->hstatus, HSTATUS_HU))) {
136
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
91
- two_stage_lookup = true;
137
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
92
- }
138
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
93
-
139
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
140
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
95
+ if (env->two_stage_lookup && write_tval) {
141
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
96
/*
142
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
97
* If we are writing a guest virtual address to stval, set
143
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
98
* this to 1. If we are trapping to VS we will set this to 0
144
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
145
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
100
riscv_cpu_set_force_hs_excep(env, 0);
146
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
101
} else {
147
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
102
/* Trap into HS mode */
148
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
103
- if (!two_stage_lookup) {
149
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
150
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
105
- riscv_cpu_virt_enabled(env));
151
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
106
- }
152
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
153
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
108
htval = env->guest_phys_fault_addr;
154
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
109
}
155
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
110
}
156
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
157
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
112
* RISC-V ISA Specification.
158
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
113
*/
159
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
114
160
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
115
+ env->two_stage_lookup = false;
161
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
116
#endif
162
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
163
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
118
}
164
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
165
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
166
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
167
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
168
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
169
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
170
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
171
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
172
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
173
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
174
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
175
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
176
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
177
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
178
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
179
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
180
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
181
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
182
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
183
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
184
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
185
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
186
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
187
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
188
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
189
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
190
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
191
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
192
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
193
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
194
195
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
196
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
119
--
197
--
120
2.30.1
198
2.36.1
121
122
diff view generated by jsdifflib
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
[PULL v2 10/19] target/riscv: Implement mcountinhibit CSR
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
The previous implementation was broken in many ways:
3
As per the privilege specification v1.11, mcountinhibit allows to start/stop
4
- Used mideleg instead of hideleg to mask accesses
4
a pmu counter selectively.
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
7
5
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
8
Signed-off-by: Atish Patra <atish.patra@wdc.com>
9
Signed-off-by: Atish Patra <atishp@rivosinc.com>
10
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
13
target/riscv/cpu.h | 2 ++
14
1 file changed, 34 insertions(+), 34 deletions(-)
14
target/riscv/cpu_bits.h | 4 ++++
15
target/riscv/csr.c | 25 +++++++++++++++++++++++++
16
target/riscv/machine.c | 1 +
17
4 files changed, 32 insertions(+)
15
18
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/cpu.h
22
+++ b/target/riscv/cpu.h
23
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
24
target_ulong scounteren;
25
target_ulong mcounteren;
26
27
+ target_ulong mcountinhibit;
28
+
29
target_ulong sscratch;
30
target_ulong mscratch;
31
32
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/cpu_bits.h
35
+++ b/target/riscv/cpu_bits.h
36
@@ -XXX,XX +XXX,XX @@
37
#define CSR_MHPMCOUNTER29 0xb1d
38
#define CSR_MHPMCOUNTER30 0xb1e
39
#define CSR_MHPMCOUNTER31 0xb1f
40
+
41
+/* Machine counter-inhibit register */
42
+#define CSR_MCOUNTINHIBIT 0x320
43
+
44
#define CSR_MHPMEVENT3 0x323
45
#define CSR_MHPMEVENT4 0x324
46
#define CSR_MHPMEVENT5 0x325
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
47
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
49
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
50
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
51
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
21
return write_mstatus(env, CSR_MSTATUS, newval);
52
return RISCV_EXCP_NONE;
22
}
53
}
23
54
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
55
+static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
56
+ target_ulong *val)
25
+{
57
+{
26
+ /* Shift the VS bits to their S bit location in vsie */
58
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
59
+ return RISCV_EXCP_ILLEGAL_INST;
28
+ return 0;
60
+ }
61
+
62
+ *val = env->mcountinhibit;
63
+ return RISCV_EXCP_NONE;
29
+}
64
+}
30
+
65
+
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
66
+static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
32
{
67
+ target_ulong val)
33
if (riscv_cpu_virt_enabled(env)) {
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
36
+ read_vsie(env, CSR_VSIE, val);
37
} else {
38
*val = env->mie & env->mideleg;
39
}
40
return 0;
41
}
42
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
45
{
46
- target_ulong newval;
47
+ /* Shift the S bits to their VS bit location in mie */
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
50
+ return write_mie(env, CSR_MIE, newval);
51
+}
52
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
54
+{
68
+{
55
if (riscv_cpu_virt_enabled(env)) {
69
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
56
- /* Shift the guests S bits to VS */
70
+ return RISCV_EXCP_ILLEGAL_INST;
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
71
+ }
58
- ((val << 1) & VS_MODE_INTERRUPTS);
72
+
59
+ write_vsie(env, CSR_VSIE, val);
73
+ env->mcountinhibit = val;
60
} else {
74
+ return RISCV_EXCP_NONE;
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
63
+ (val & S_MODE_INTERRUPTS);
64
+ write_mie(env, CSR_MIE, newval);
65
}
66
67
- return write_mie(env, CSR_MIE, newval);
68
+ return 0;
69
}
70
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
73
return 0;
74
}
75
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
77
+ target_ulong new_value, target_ulong write_mask)
78
+{
79
+ /* Shift the S bits to their VS bit location in mip */
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
86
+}
75
+}
87
+
76
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
77
static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
89
target_ulong new_value, target_ulong write_mask)
78
target_ulong *val)
90
{
79
{
91
int ret;
80
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
92
81
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
93
if (riscv_cpu_virt_enabled(env)) {
82
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
94
- /* Shift the new values to line up with the VS bits */
83
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
84
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
85
+ write_mcountinhibit },
97
- ret &= vsip_writable_mask;
86
+
98
- ret >>= 1;
87
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
88
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
100
} else {
89
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
90
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
102
write_mask & env->mideleg & sip_writable_mask);
91
index XXXXXXX..XXXXXXX 100644
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
92
--- a/target/riscv/machine.c
104
return 0;
93
+++ b/target/riscv/machine.c
105
}
94
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
106
95
VMSTATE_UINTTL(env.siselect, RISCVCPU),
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
96
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
108
- target_ulong new_value, target_ulong write_mask)
97
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
109
-{
98
+ VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
99
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
111
- write_mask & env->mideleg & vsip_writable_mask);
100
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
112
- return ret;
101
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
129
*val = env->vstvec;
130
--
102
--
131
2.30.1
103
2.36.1
132
133
diff view generated by jsdifflib
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
[PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
3
With SBI PMU extension, user can use any of the available hpmcounters to
4
been updated to use a register mapped at 0x4f000000 instead of a
4
track any perf events based on the value written to mhpmevent csr.
5
GPIO to control whether eMMC or SD card is to be used. With this
5
Add read/write functionality for these csrs.
6
support the same HSS image can be used for both eMMC and SD card
7
boot flow, while previously two different board configurations were
8
used. This is undocumented but one can take a look at the HSS code
9
HSS_MMCInit() in services/mmc/mmc_api.c.
10
6
11
With this commit, HSS image built from 2020.12 release boots again.
12
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Signed-off-by: Atish Patra <atish.patra@wdc.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
13
---
18
include/hw/riscv/microchip_pfsoc.h | 1 +
14
target/riscv/cpu.h | 11 +
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
15
target/riscv/csr.c | 469 ++++++++++++++++++++++++++++-------------
20
2 files changed, 7 insertions(+)
16
target/riscv/machine.c | 3 +
17
3 files changed, 331 insertions(+), 152 deletions(-)
21
18
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
19
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/riscv/microchip_pfsoc.h
21
--- a/target/riscv/cpu.h
25
+++ b/include/hw/riscv/microchip_pfsoc.h
22
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ enum {
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState CPURISCVState;
27
MICROCHIP_PFSOC_ENVM_DATA,
24
#endif
28
MICROCHIP_PFSOC_QSPI_XIP,
25
29
MICROCHIP_PFSOC_IOSCB,
26
#define RV_VLEN_MAX 1024
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
27
+#define RV_MAX_MHPMEVENTS 29
31
MICROCHIP_PFSOC_DRAM_LO,
28
+#define RV_MAX_MHPMCOUNTERS 32
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
29
33
MICROCHIP_PFSOC_DRAM_HI,
30
FIELD(VTYPE, VLMUL, 0, 3)
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
31
FIELD(VTYPE, VSEW, 3, 3)
32
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
33
34
target_ulong mcountinhibit;
35
36
+ /* PMU counter configured values */
37
+ target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
38
+
39
+ /* for RV32 */
40
+ target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
41
+
42
+ /* PMU event selector configured values */
43
+ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
44
+
45
target_ulong sscratch;
46
target_ulong mscratch;
47
48
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
35
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/riscv/microchip_pfsoc.c
50
--- a/target/riscv/csr.c
37
+++ b/hw/riscv/microchip_pfsoc.c
51
+++ b/target/riscv/csr.c
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
52
@@ -XXX,XX +XXX,XX @@ static RISCVException mctr(CPURISCVState *env, int csrno)
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
53
return RISCV_EXCP_NONE;
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
54
}
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
55
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
56
+static RISCVException mctr32(CPURISCVState *env, int csrno)
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
57
+{
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
58
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
59
+ return RISCV_EXCP_ILLEGAL_INST;
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
60
+ }
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
61
+
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
62
+ return mctr(env, csrno);
49
63
+}
50
+ /* eMMC/SD mux */
64
+
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
65
static RISCVException any(CPURISCVState *env, int csrno)
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
66
{
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
67
return RISCV_EXCP_NONE;
54
+
68
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
55
/* QSPI Flash */
69
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
70
#else /* CONFIG_USER_ONLY */
57
"microchip.pfsoc.qspi_xip",
71
72
+static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
73
+{
74
+ int evt_index = csrno - CSR_MHPMEVENT3;
75
+
76
+ *val = env->mhpmevent_val[evt_index];
77
+
78
+ return RISCV_EXCP_NONE;
79
+}
80
+
81
+static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
82
+{
83
+ int evt_index = csrno - CSR_MHPMEVENT3;
84
+
85
+ env->mhpmevent_val[evt_index] = val;
86
+
87
+ return RISCV_EXCP_NONE;
88
+}
89
+
90
+static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
91
+{
92
+ int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
93
+
94
+ env->mhpmcounter_val[ctr_index] = val;
95
+
96
+ return RISCV_EXCP_NONE;
97
+}
98
+
99
+static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
100
+{
101
+ int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
102
+
103
+ env->mhpmcounterh_val[ctr_index] = val;
104
+
105
+ return RISCV_EXCP_NONE;
106
+}
107
+
108
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
109
+{
110
+ int ctr_index;
111
+
112
+ if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
113
+ ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
114
+ } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
115
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
116
+ } else {
117
+ return RISCV_EXCP_ILLEGAL_INST;
118
+ }
119
+ *val = env->mhpmcounter_val[ctr_index];
120
+
121
+ return RISCV_EXCP_NONE;
122
+}
123
+
124
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
125
+{
126
+ int ctr_index;
127
+
128
+ if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
129
+ ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
130
+ } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
131
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
132
+ } else {
133
+ return RISCV_EXCP_ILLEGAL_INST;
134
+ }
135
+ *val = env->mhpmcounterh_val[ctr_index];
136
+
137
+ return RISCV_EXCP_NONE;
138
+}
139
+
140
+
141
static RISCVException read_time(CPURISCVState *env, int csrno,
142
target_ulong *val)
143
{
144
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
145
[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
146
147
/* Performance Counters */
148
- [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
149
- [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
150
- [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
151
- [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
152
- [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
153
- [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
154
- [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
155
- [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
156
- [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
157
- [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
158
- [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
159
- [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
160
- [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
161
- [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
162
- [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
163
- [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
164
- [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
165
- [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
166
- [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
167
- [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
168
- [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
169
- [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
170
- [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
171
- [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
172
- [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
173
- [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
174
- [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
175
- [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
176
- [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
177
-
178
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
179
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
180
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
181
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
182
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
183
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
184
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
185
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
186
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
187
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
188
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
189
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
190
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
191
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
192
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
193
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
194
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
195
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
196
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
197
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
198
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
199
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
200
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
201
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
202
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
203
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
204
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
205
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
206
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
207
-
208
- [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
209
- write_mcountinhibit },
210
-
211
- [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
212
- [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
213
- [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
214
- [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
215
- [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
216
- [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
217
- [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
218
- [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
219
- [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
220
- [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
221
- [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
222
- [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
223
- [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
224
- [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
225
- [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
226
- [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
227
- [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
228
- [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
229
- [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
230
- [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
231
- [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
232
- [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
233
- [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
234
- [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
235
- [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
236
- [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
237
- [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
238
- [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
239
- [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
240
-
241
- [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
242
- [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
243
- [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
244
- [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
245
- [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
246
- [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
247
- [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
248
- [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
249
- [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
250
- [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
251
- [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
252
- [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
253
- [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
254
- [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
255
- [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
256
- [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
257
- [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
258
- [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
259
- [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
260
- [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
261
- [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
262
- [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
263
- [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
264
- [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
265
- [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
266
- [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
267
- [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
268
- [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
269
- [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
270
-
271
- [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
272
- [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
273
- [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
274
- [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
275
- [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
276
- [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
277
- [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
278
- [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
279
- [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
280
- [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
281
- [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
282
- [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
283
- [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
284
- [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
285
- [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
286
- [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
287
- [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
288
- [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
289
- [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
290
- [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
291
- [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
292
- [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
293
- [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
294
- [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
295
- [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
296
- [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
297
- [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
298
- [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
299
- [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
300
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
301
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
302
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter },
303
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter },
304
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter },
305
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter },
306
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter },
307
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter },
308
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter },
309
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter },
310
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter },
311
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter },
312
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter },
313
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter },
314
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter },
315
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter },
316
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter },
317
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter },
318
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter },
319
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter },
320
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter },
321
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter },
322
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter },
323
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter },
324
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter },
325
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter },
326
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter },
327
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter },
328
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter },
329
+
330
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter,
331
+ write_mhpmcounter },
332
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter,
333
+ write_mhpmcounter },
334
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter,
335
+ write_mhpmcounter },
336
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter,
337
+ write_mhpmcounter },
338
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter,
339
+ write_mhpmcounter },
340
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter,
341
+ write_mhpmcounter },
342
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter,
343
+ write_mhpmcounter },
344
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter,
345
+ write_mhpmcounter },
346
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter,
347
+ write_mhpmcounter },
348
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter,
349
+ write_mhpmcounter },
350
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter,
351
+ write_mhpmcounter },
352
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter,
353
+ write_mhpmcounter },
354
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter,
355
+ write_mhpmcounter },
356
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter,
357
+ write_mhpmcounter },
358
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter,
359
+ write_mhpmcounter },
360
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter,
361
+ write_mhpmcounter },
362
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter,
363
+ write_mhpmcounter },
364
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter,
365
+ write_mhpmcounter },
366
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter,
367
+ write_mhpmcounter },
368
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter,
369
+ write_mhpmcounter },
370
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter,
371
+ write_mhpmcounter },
372
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter,
373
+ write_mhpmcounter },
374
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter,
375
+ write_mhpmcounter },
376
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter,
377
+ write_mhpmcounter },
378
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter,
379
+ write_mhpmcounter },
380
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter,
381
+ write_mhpmcounter },
382
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter,
383
+ write_mhpmcounter },
384
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter,
385
+ write_mhpmcounter },
386
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter,
387
+ write_mhpmcounter },
388
+
389
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
390
+ write_mcountinhibit },
391
+
392
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
393
+ write_mhpmevent },
394
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent,
395
+ write_mhpmevent },
396
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,
397
+ write_mhpmevent },
398
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent,
399
+ write_mhpmevent },
400
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent,
401
+ write_mhpmevent },
402
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent,
403
+ write_mhpmevent },
404
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent,
405
+ write_mhpmevent },
406
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent,
407
+ write_mhpmevent },
408
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent,
409
+ write_mhpmevent },
410
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent,
411
+ write_mhpmevent },
412
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent,
413
+ write_mhpmevent },
414
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent,
415
+ write_mhpmevent },
416
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent,
417
+ write_mhpmevent },
418
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent,
419
+ write_mhpmevent },
420
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent,
421
+ write_mhpmevent },
422
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent,
423
+ write_mhpmevent },
424
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent,
425
+ write_mhpmevent },
426
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent,
427
+ write_mhpmevent },
428
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent,
429
+ write_mhpmevent },
430
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent,
431
+ write_mhpmevent },
432
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent,
433
+ write_mhpmevent },
434
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent,
435
+ write_mhpmevent },
436
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent,
437
+ write_mhpmevent },
438
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent,
439
+ write_mhpmevent },
440
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent,
441
+ write_mhpmevent },
442
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,
443
+ write_mhpmevent },
444
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent,
445
+ write_mhpmevent },
446
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent,
447
+ write_mhpmevent },
448
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
449
+ write_mhpmevent },
450
+
451
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
452
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
453
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
454
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh },
455
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh },
456
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh },
457
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh },
458
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh },
459
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh },
460
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh },
461
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh },
462
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh },
463
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh },
464
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh },
465
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh },
466
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh },
467
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh },
468
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh },
469
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh },
470
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh },
471
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh },
472
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh },
473
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh },
474
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh },
475
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh },
476
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh },
477
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh },
478
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh },
479
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh },
480
+
481
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh,
482
+ write_mhpmcounterh },
483
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh,
484
+ write_mhpmcounterh },
485
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh,
486
+ write_mhpmcounterh },
487
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh,
488
+ write_mhpmcounterh },
489
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh,
490
+ write_mhpmcounterh },
491
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh,
492
+ write_mhpmcounterh },
493
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh,
494
+ write_mhpmcounterh },
495
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh,
496
+ write_mhpmcounterh },
497
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh,
498
+ write_mhpmcounterh },
499
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh,
500
+ write_mhpmcounterh },
501
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh,
502
+ write_mhpmcounterh },
503
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh,
504
+ write_mhpmcounterh },
505
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
506
+ write_mhpmcounterh },
507
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
508
+ write_mhpmcounterh },
509
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
510
+ write_mhpmcounterh },
511
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
512
+ write_mhpmcounterh },
513
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
514
+ write_mhpmcounterh },
515
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
516
+ write_mhpmcounterh },
517
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
518
+ write_mhpmcounterh },
519
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
520
+ write_mhpmcounterh },
521
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
522
+ write_mhpmcounterh },
523
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
524
+ write_mhpmcounterh },
525
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
526
+ write_mhpmcounterh },
527
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
528
+ write_mhpmcounterh },
529
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
530
+ write_mhpmcounterh },
531
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
532
+ write_mhpmcounterh },
533
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
534
+ write_mhpmcounterh },
535
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
536
+ write_mhpmcounterh },
537
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
538
+ write_mhpmcounterh },
539
#endif /* !CONFIG_USER_ONLY */
540
};
541
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
542
index XXXXXXX..XXXXXXX 100644
543
--- a/target/riscv/machine.c
544
+++ b/target/riscv/machine.c
545
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
546
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
547
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
548
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
549
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
550
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
551
+ VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
552
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
553
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
554
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
58
--
555
--
59
2.30.1
556
2.36.1
60
61
diff view generated by jsdifflib
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PULL v2 12/19] target/riscv: Support mcycle/minstret write operation
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atish.patra@wdc.com>
2
2
3
This adds the documentation to describe what is supported for the
3
mcycle/minstret are actually WARL registers and can be written with any
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
4
given value. With SBI PMU extension, it will be used to store a initial
5
value provided from supervisor OS. The Qemu also need prohibit the counter
6
increment if mcountinhibit is set.
5
7
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Support mcycle/minstret through generic counter infrastructure.
9
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
11
Signed-off-by: Atish Patra <atish.patra@wdc.com>
12
Signed-off-by: Atish Patra <atishp@rivosinc.com>
13
Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
15
---
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
16
target/riscv/cpu.h | 23 ++++--
12
docs/system/target-riscv.rst | 1 +
17
target/riscv/pmu.h | 28 +++++++
13
2 files changed, 90 insertions(+)
18
target/riscv/csr.c | 155 ++++++++++++++++++++++++++++-----------
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
19
target/riscv/machine.c | 25 ++++++-
20
target/riscv/pmu.c | 32 ++++++++
21
target/riscv/meson.build | 3 +-
22
6 files changed, 213 insertions(+), 53 deletions(-)
23
create mode 100644 target/riscv/pmu.h
24
create mode 100644 target/riscv/pmu.c
15
25
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
26
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.h
29
+++ b/target/riscv/cpu.h
30
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState CPURISCVState;
31
#endif
32
33
#define RV_VLEN_MAX 1024
34
-#define RV_MAX_MHPMEVENTS 29
35
+#define RV_MAX_MHPMEVENTS 32
36
#define RV_MAX_MHPMCOUNTERS 32
37
38
FIELD(VTYPE, VLMUL, 0, 3)
39
@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, VMA, 7, 1)
40
FIELD(VTYPE, VEDIV, 8, 2)
41
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
42
43
+typedef struct PMUCTRState {
44
+ /* Current value of a counter */
45
+ target_ulong mhpmcounter_val;
46
+ /* Current value of a counter in RV32*/
47
+ target_ulong mhpmcounterh_val;
48
+ /* Snapshot values of counter */
49
+ target_ulong mhpmcounter_prev;
50
+ /* Snapshort value of a counter in RV32 */
51
+ target_ulong mhpmcounterh_prev;
52
+ bool started;
53
+} PMUCTRState;
54
+
55
struct CPUArchState {
56
target_ulong gpr[32];
57
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
58
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
59
60
target_ulong mcountinhibit;
61
62
- /* PMU counter configured values */
63
- target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
64
-
65
- /* for RV32 */
66
- target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
67
+ /* PMU counter state */
68
+ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
69
70
- /* PMU event selector configured values */
71
+ /* PMU event selector configured values. First three are unused*/
72
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
73
74
target_ulong sscratch;
75
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
17
new file mode 100644
76
new file mode 100644
18
index XXXXXXX..XXXXXXX
77
index XXXXXXX..XXXXXXX
19
--- /dev/null
78
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
79
+++ b/target/riscv/pmu.h
21
@@ -XXX,XX +XXX,XX @@
80
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
81
+/*
23
+=============================================================
82
+ * RISC-V PMU header file.
24
+
83
+ *
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
84
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
85
+ *
27
+
86
+ * This program is free software; you can redistribute it and/or modify it
28
+For more details about Microchip PolarFire SoC, please see:
87
+ * under the terms and conditions of the GNU General Public License,
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
88
+ * version 2 or later, as published by the Free Software Foundation.
30
+
89
+ *
31
+The Icicle Kit board information can be found here:
90
+ * This program is distributed in the hope it will be useful, but WITHOUT
32
+https://www.microsemi.com/existing-parts/parts/152514
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
33
+
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
34
+Supported devices
93
+ * more details.
35
+-----------------
94
+ *
36
+
95
+ * You should have received a copy of the GNU General Public License along with
37
+The ``microchip-icicle-kit`` machine supports the following devices:
96
+ * this program. If not, see <http://www.gnu.org/licenses/>.
38
+
97
+ */
39
+ * 1 E51 core
98
+
40
+ * 4 U54 cores
99
+#include "qemu/osdep.h"
41
+ * Core Level Interruptor (CLINT)
100
+#include "qemu/log.h"
42
+ * Platform-Level Interrupt Controller (PLIC)
101
+#include "cpu.h"
43
+ * L2 Loosely Integrated Memory (L2-LIM)
102
+#include "qemu/main-loop.h"
44
+ * DDR memory controller
103
+#include "exec/exec-all.h"
45
+ * 5 MMUARTs
104
+
46
+ * 1 DMA controller
105
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
47
+ * 2 GEM Ethernet controllers
106
+ uint32_t target_ctr);
48
+ * 1 SDHC storage controller
107
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
49
+
108
+ uint32_t target_ctr);
50
+Boot options
109
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
51
+------------
52
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
56
+support direct kernel loading via the -kernel option. One has to load kernel
57
+from U-Boot.
58
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
60
+memory size by HSS. A sanity check on ram size is performed in the machine
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
62
+than 1537 MiB ram is detected.
63
+
64
+Boot the machine
65
+----------------
66
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
69
+in the HSS source tree:
70
+
71
+.. code-block:: bash
72
+
73
+ $ export CROSS_COMPILE=riscv64-linux-
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
75
+ $ make BOARD=mpfs-icicle-kit-es
76
+
77
+Download the official SD card image released by Microchip and prepare it for
78
+QEMU usage:
79
+
80
+.. code-block:: bash
81
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
86
+Then we can boot the machine by:
87
+
88
+.. code-block:: bash
89
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
92
+ -nic user,model=cadence_gem \
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
94
+ -display none -serial stdio \
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
96
+ -serial chardev:serial1
97
+
98
+With above command line, current terminal session will be used for the first
99
+serial port. Open another terminal window, and use `minicom` to connect the
100
+second serial port.
101
+
102
+.. code-block:: bash
103
+
104
+ $ minicom -D unix\#serial1.sock
105
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
107
+second serial port. U-Boot will automatically load the Linux kernel from
108
+the SD card image.
109
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
112
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
113
--- a/docs/system/target-riscv.rst
111
--- a/target/riscv/csr.c
114
+++ b/docs/system/target-riscv.rst
112
+++ b/target/riscv/csr.c
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
113
@@ -XXX,XX +XXX,XX @@
116
.. toctree::
114
#include "qemu/log.h"
117
:maxdepth: 1
115
#include "qemu/timer.h"
118
116
#include "cpu.h"
119
+ riscv/microchip-icicle-kit
117
+#include "pmu.h"
120
riscv/sifive_u
118
#include "qemu/main-loop.h"
121
119
#include "exec/exec-all.h"
122
RISC-V CPU features
120
#include "sysemu/cpu-timers.h"
121
@@ -XXX,XX +XXX,XX @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
122
}
123
124
/* User Timers and Counters */
125
-static RISCVException read_instret(CPURISCVState *env, int csrno,
126
- target_ulong *val)
127
+static target_ulong get_ticks(bool shift)
128
{
129
+ int64_t val;
130
+ target_ulong result;
131
+
132
#if !defined(CONFIG_USER_ONLY)
133
if (icount_enabled()) {
134
- *val = icount_get();
135
+ val = icount_get();
136
} else {
137
- *val = cpu_get_host_ticks();
138
+ val = cpu_get_host_ticks();
139
}
140
#else
141
- *val = cpu_get_host_ticks();
142
+ val = cpu_get_host_ticks();
143
#endif
144
- return RISCV_EXCP_NONE;
145
-}
146
147
-static RISCVException read_instreth(CPURISCVState *env, int csrno,
148
- target_ulong *val)
149
-{
150
-#if !defined(CONFIG_USER_ONLY)
151
- if (icount_enabled()) {
152
- *val = icount_get() >> 32;
153
+ if (shift) {
154
+ result = val >> 32;
155
} else {
156
- *val = cpu_get_host_ticks() >> 32;
157
+ result = val;
158
}
159
-#else
160
- *val = cpu_get_host_ticks() >> 32;
161
-#endif
162
- return RISCV_EXCP_NONE;
163
+
164
+ return result;
165
}
166
167
#if defined(CONFIG_USER_ONLY)
168
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
169
return RISCV_EXCP_NONE;
170
}
171
172
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
173
+{
174
+ *val = get_ticks(false);
175
+ return RISCV_EXCP_NONE;
176
+}
177
+
178
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
179
+{
180
+ *val = get_ticks(true);
181
+ return RISCV_EXCP_NONE;
182
+}
183
+
184
#else /* CONFIG_USER_ONLY */
185
186
static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
187
{
188
- int evt_index = csrno - CSR_MHPMEVENT3;
189
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
190
191
*val = env->mhpmevent_val[evt_index];
192
193
@@ -XXX,XX +XXX,XX @@ static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
194
195
static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
196
{
197
- int evt_index = csrno - CSR_MHPMEVENT3;
198
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
199
200
env->mhpmevent_val[evt_index] = val;
201
202
@@ -XXX,XX +XXX,XX @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
203
204
static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
205
{
206
- int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
207
+ int ctr_idx = csrno - CSR_MCYCLE;
208
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
209
210
- env->mhpmcounter_val[ctr_index] = val;
211
+ counter->mhpmcounter_val = val;
212
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
213
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
214
+ counter->mhpmcounter_prev = get_ticks(false);
215
+ } else {
216
+ /* Other counters can keep incrementing from the given value */
217
+ counter->mhpmcounter_prev = val;
218
+ }
219
220
return RISCV_EXCP_NONE;
221
}
222
223
static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
224
{
225
- int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
226
+ int ctr_idx = csrno - CSR_MCYCLEH;
227
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
228
229
- env->mhpmcounterh_val[ctr_index] = val;
230
+ counter->mhpmcounterh_val = val;
231
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
232
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
233
+ counter->mhpmcounterh_prev = get_ticks(true);
234
+ } else {
235
+ counter->mhpmcounterh_prev = val;
236
+ }
237
+
238
+ return RISCV_EXCP_NONE;
239
+}
240
+
241
+static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
242
+ bool upper_half, uint32_t ctr_idx)
243
+{
244
+ PMUCTRState counter = env->pmu_ctrs[ctr_idx];
245
+ target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev :
246
+ counter.mhpmcounter_prev;
247
+ target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val :
248
+ counter.mhpmcounter_val;
249
+
250
+ if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
251
+ /**
252
+ * Counter should not increment if inhibit bit is set. We can't really
253
+ * stop the icount counting. Just return the counter value written by
254
+ * the supervisor to indicate that counter was not incremented.
255
+ */
256
+ if (!counter.started) {
257
+ *val = ctr_val;
258
+ return RISCV_EXCP_NONE;
259
+ } else {
260
+ /* Mark that the counter has been stopped */
261
+ counter.started = false;
262
+ }
263
+ }
264
+
265
+ /**
266
+ * The kernel computes the perf delta by subtracting the current value from
267
+ * the value it initialized previously (ctr_val).
268
+ */
269
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
270
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
271
+ *val = get_ticks(upper_half) - ctr_prev + ctr_val;
272
+ } else {
273
+ *val = ctr_val;
274
+ }
275
276
return RISCV_EXCP_NONE;
277
}
278
279
static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
280
{
281
- int ctr_index;
282
+ uint16_t ctr_index;
283
284
if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
285
- ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
286
+ ctr_index = csrno - CSR_MCYCLE;
287
} else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
288
- ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
289
+ ctr_index = csrno - CSR_CYCLE;
290
} else {
291
return RISCV_EXCP_ILLEGAL_INST;
292
}
293
- *val = env->mhpmcounter_val[ctr_index];
294
295
- return RISCV_EXCP_NONE;
296
+ return riscv_pmu_read_ctr(env, val, false, ctr_index);
297
}
298
299
static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
300
{
301
- int ctr_index;
302
+ uint16_t ctr_index;
303
304
if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
305
- ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
306
+ ctr_index = csrno - CSR_MCYCLEH;
307
} else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
308
- ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
309
+ ctr_index = csrno - CSR_CYCLEH;
310
} else {
311
return RISCV_EXCP_ILLEGAL_INST;
312
}
313
- *val = env->mhpmcounterh_val[ctr_index];
314
315
- return RISCV_EXCP_NONE;
316
+ return riscv_pmu_read_ctr(env, val, true, ctr_index);
317
}
318
319
-
320
static RISCVException read_time(CPURISCVState *env, int csrno,
321
target_ulong *val)
322
{
323
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
324
static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
325
target_ulong val)
326
{
327
+ int cidx;
328
+ PMUCTRState *counter;
329
+
330
if (env->priv_ver < PRIV_VERSION_1_11_0) {
331
return RISCV_EXCP_ILLEGAL_INST;
332
}
333
334
env->mcountinhibit = val;
335
+
336
+ /* Check if any other counter is also monitoring cycles/instructions */
337
+ for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
338
+ if (!get_field(env->mcountinhibit, BIT(cidx))) {
339
+ counter = &env->pmu_ctrs[cidx];
340
+ counter->started = true;
341
+ }
342
+ }
343
+
344
return RISCV_EXCP_NONE;
345
}
346
347
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
348
[CSR_VLENB] = { "vlenb", vs, read_vlenb,
349
.min_priv_ver = PRIV_VERSION_1_12_0 },
350
/* User Timers and Counters */
351
- [CSR_CYCLE] = { "cycle", ctr, read_instret },
352
- [CSR_INSTRET] = { "instret", ctr, read_instret },
353
- [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
354
- [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
355
+ [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
356
+ [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
357
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh },
358
+ [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh },
359
360
/*
361
* In privileged mode, the monitor will have to emulate TIME CSRs only if
362
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
363
364
#if !defined(CONFIG_USER_ONLY)
365
/* Machine Timers and Counters */
366
- [CSR_MCYCLE] = { "mcycle", any, read_instret },
367
- [CSR_MINSTRET] = { "minstret", any, read_instret },
368
- [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
369
- [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
370
+ [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
371
+ [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
372
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
373
+ [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
374
375
/* Machine Information Registers */
376
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
377
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
378
index XXXXXXX..XXXXXXX 100644
379
--- a/target/riscv/machine.c
380
+++ b/target/riscv/machine.c
381
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_envcfg = {
382
VMSTATE_UINT64(env.menvcfg, RISCVCPU),
383
VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
384
VMSTATE_UINT64(env.henvcfg, RISCVCPU),
385
+ VMSTATE_END_OF_LIST()
386
+ }
387
+};
388
+
389
+static bool pmu_needed(void *opaque)
390
+{
391
+ RISCVCPU *cpu = opaque;
392
393
+ return cpu->cfg.pmu_num;
394
+}
395
+
396
+static const VMStateDescription vmstate_pmu_ctr_state = {
397
+ .name = "cpu/pmu",
398
+ .version_id = 1,
399
+ .minimum_version_id = 1,
400
+ .needed = pmu_needed,
401
+ .fields = (VMStateField[]) {
402
+ VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
403
+ VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
404
+ VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
405
+ VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
406
+ VMSTATE_BOOL(started, PMUCTRState),
407
VMSTATE_END_OF_LIST()
408
}
409
};
410
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
411
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
412
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
413
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
414
- VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
415
- VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
416
+ VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
417
+ vmstate_pmu_ctr_state, PMUCTRState),
418
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
419
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
420
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
421
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
422
new file mode 100644
423
index XXXXXXX..XXXXXXX
424
--- /dev/null
425
+++ b/target/riscv/pmu.c
426
@@ -XXX,XX +XXX,XX @@
427
+/*
428
+ * RISC-V PMU file.
429
+ *
430
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
431
+ *
432
+ * This program is free software; you can redistribute it and/or modify it
433
+ * under the terms and conditions of the GNU General Public License,
434
+ * version 2 or later, as published by the Free Software Foundation.
435
+ *
436
+ * This program is distributed in the hope it will be useful, but WITHOUT
437
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
438
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
439
+ * more details.
440
+ *
441
+ * You should have received a copy of the GNU General Public License along with
442
+ * this program. If not, see <http://www.gnu.org/licenses/>.
443
+ */
444
+
445
+#include "qemu/osdep.h"
446
+#include "cpu.h"
447
+#include "pmu.h"
448
+
449
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
450
+ uint32_t target_ctr)
451
+{
452
+ return (target_ctr == 0) ? true : false;
453
+}
454
+
455
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
456
+{
457
+ return (target_ctr == 2) ? true : false;
458
+}
459
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
460
index XXXXXXX..XXXXXXX 100644
461
--- a/target/riscv/meson.build
462
+++ b/target/riscv/meson.build
463
@@ -XXX,XX +XXX,XX @@ riscv_softmmu_ss.add(files(
464
'pmp.c',
465
'debug.c',
466
'monitor.c',
467
- 'machine.c'
468
+ 'machine.c',
469
+ 'pmu.c'
470
))
471
472
target_arch += {'riscv': riscv_ss}
123
--
473
--
124
2.30.1
474
2.36.1
125
126
diff view generated by jsdifflib
New patch
[PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
There is nothing in the RISC-V spec that mandates version 1.12 is
4
required for ePMP and there is currently hardware [1] that implements
5
ePMP (a draft version though) with the 1.11 priv spec.
6
7
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
8
9
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.")
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>
13
---
14
target/riscv/csr.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/csr.c
20
+++ b/target/riscv/csr.c
21
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
22
23
/* Physical Memory Protection */
24
[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
25
- .min_priv_ver = PRIV_VERSION_1_12_0 },
26
+ .min_priv_ver = PRIV_VERSION_1_11_0 },
27
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
28
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
29
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
30
--
31
2.36.1
diff view generated by jsdifflib
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
[PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
3
The Ibex CPU supports version 1.11 of the priv spec [1], so let's
4
the address bytes. Note only SPI mode is supported by SST flashes.
4
correct that in QEMU as well.
5
5
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
6
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
7
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
10
Message-Id: <20220629233102.275181-3-alistair.francis@opensource.wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
hw/block/m25p80.c | 3 +++
13
target/riscv/cpu.c | 2 +-
14
1 file changed, 3 insertions(+)
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
15
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
16
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
18
--- a/target/riscv/cpu.c
19
+++ b/hw/block/m25p80.c
19
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
20
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
21
s->needed_bytes = get_addr_length(s);
21
RISCVCPU *cpu = RISCV_CPU(obj);
22
switch (get_man(s)) {
22
23
/* Dummy cycles - modeled with bytes writes instead of bits */
23
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
24
+ case MAN_SST:
24
- set_priv_version(env, PRIV_VERSION_1_10_0);
25
+ s->needed_bytes += 1;
25
+ set_priv_version(env, PRIV_VERSION_1_11_0);
26
+ break;
26
cpu->cfg.mmu = false;
27
case MAN_WINBOND:
27
cpu->cfg.epmp = true;
28
s->needed_bytes += 8;
28
}
29
break;
30
--
29
--
31
2.30.1
30
2.36.1
32
33
diff view generated by jsdifflib
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
[PULL v2 15/19] target/riscv: Don't force update priv spec version to latest
1
From: Jim Shu <cwshu@andestech.com>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
3
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
4
Fix it by propagating PMP permission to TLB page permission.
4
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
5
value of priv spec v1.10 is zero.
5
6
6
PMP permission checking also use MMU-style API to change TLB permission
7
Due to above issue, the sifive_u machine will see priv spec v1.12
7
and size.
8
instead of priv spec v1.10.
8
9
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
10
To fix this issue, we set latest priv spec version (i.e. v1.12)
11
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
12
spec version only when "cpu->cfg.priv_spec != NULL".
13
14
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
15
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
16
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
18
Reviewed-by: Atish Patra <atishp@rivosinc.com>
19
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
20
Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
22
---
14
target/riscv/pmp.h | 4 +-
23
target/riscv/cpu.c | 12 ++++++++----
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
24
1 file changed, 8 insertions(+), 4 deletions(-)
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
17
3 files changed, 125 insertions(+), 43 deletions(-)
18
25
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
20
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/pmp.h
28
--- a/target/riscv/cpu.c
22
+++ b/target/riscv/pmp.h
29
+++ b/target/riscv/cpu.c
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
30
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
24
target_ulong val);
31
/* We set this in the realise function */
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
32
set_misa(env, MXL_RV64, 0);
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
33
register_cpu_props(DEVICE(obj));
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
34
+ /* Set latest version of privileged specification */
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
35
+ set_priv_version(env, PRIV_VERSION_1_12_0);
29
+ target_ulong mode);
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
31
target_ulong *tlb_size);
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
33
void pmp_update_rule_nums(CPURISCVState *env);
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
36
37
#endif
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
43
env->load_res = -1;
44
}
36
}
45
37
46
+/*
38
static void rv64_sifive_u_cpu_init(Object *obj)
47
+ * get_physical_address_pmp - check PMP permission for this physical address
39
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
48
+ *
40
/* We set this in the realise function */
49
+ * Match the PMP region and check permission for this physical address and it's
41
set_misa(env, MXL_RV128, 0);
50
+ * TLB page. Returns 0 if the permission checking was successful
42
register_cpu_props(DEVICE(obj));
51
+ *
43
+ /* Set latest version of privileged specification */
52
+ * @env: CPURISCVState
44
+ set_priv_version(env, PRIV_VERSION_1_12_0);
53
+ * @prot: The returned protection attributes
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
55
+ * permission checking. NULL if not set TLB page for addr.
56
+ * @addr: The physical address to be checked permission
57
+ * @access_type: The type of MMU access
58
+ * @mode: Indicates current privilege level.
59
+ */
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
61
+ target_ulong *tlb_size, hwaddr addr,
62
+ int size, MMUAccessType access_type,
63
+ int mode)
64
+{
65
+ pmp_priv_t pmp_priv;
66
+ target_ulong tlb_size_pmp = 0;
67
+
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
70
+ return TRANSLATE_SUCCESS;
71
+ }
72
+
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
74
+ mode)) {
75
+ *prot = 0;
76
+ return TRANSLATE_PMP_FAIL;
77
+ }
78
+
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
80
+ if (tlb_size != NULL) {
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
82
+ *tlb_size = tlb_size_pmp;
83
+ }
84
+ }
85
+
86
+ return TRANSLATE_SUCCESS;
87
+}
88
+
89
/* get_physical_address - get the physical address for this virtual address
90
*
91
* Do a page table walk to obtain the physical address corresponding to a
92
@@ -XXX,XX +XXX,XX @@ restart:
93
pte_addr = base + idx * ptesize;
94
}
95
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
99
+ int pmp_prot;
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
101
+ sizeof(target_ulong),
102
+ MMU_DATA_LOAD, PRV_S);
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
104
return TRANSLATE_PMP_FAIL;
105
}
106
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
#ifndef CONFIG_USER_ONLY
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
154
}
155
+
156
if (ret == TRANSLATE_PMP_FAIL) {
157
pmp_violation = true;
158
}
159
160
if (ret == TRANSLATE_SUCCESS) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
163
- prot, mmu_idx, tlb_size);
164
- } else {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/target/riscv/pmp.c
176
+++ b/target/riscv/pmp.c
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
178
return result;
179
}
45
}
180
46
#else
181
+/*
47
static void rv32_base_cpu_init(Object *obj)
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
48
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
183
+ */
49
/* We set this in the realise function */
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
50
set_misa(env, MXL_RV32, 0);
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
51
register_cpu_props(DEVICE(obj));
186
+ target_ulong mode)
52
+ /* Set latest version of privileged specification */
187
+{
53
+ set_priv_version(env, PRIV_VERSION_1_12_0);
188
+ bool ret;
54
}
189
+
55
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
56
static void rv32_sifive_u_cpu_init(Object *obj)
191
+ /*
57
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
58
CPURISCVState *env = &cpu->env;
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
59
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
194
+ */
60
CPUClass *cc = CPU_CLASS(mcc);
195
+ ret = true;
61
- int priv_version = 0;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
62
+ int priv_version = -1;
197
+ } else {
63
Error *local_err = NULL;
198
+ /*
64
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
65
cpu_exec_realizefn(cs, &local_err);
200
+ * but there are rules. We've checked for no rule earlier in this
66
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
206
+
207
+ return ret;
208
+}
209
+
210
211
/*
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
215
*/
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
219
+ target_ulong mode)
220
{
221
int i = 0;
222
int ret = -1;
223
int pmp_size = 0;
224
target_ulong s = 0;
225
target_ulong e = 0;
226
- pmp_priv_t allowed_privs = 0;
227
228
/* Short cut if no rules */
229
if (0 == pmp_get_num_rules(env)) {
230
- return (env->priv == PRV_M) ? true : false;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
232
+ allowed_privs, mode);
233
}
234
235
if (size == 0) {
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
237
* check
238
*/
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
245
}
246
247
- if ((privs & allowed_privs) == privs) {
248
- ret = 1;
249
- break;
250
- } else {
251
- ret = 0;
252
- break;
253
- }
254
+ ret = ((privs & *allowed_privs) == privs);
255
+ break;
256
}
67
}
257
}
68
}
258
69
259
/* No rule matched */
70
- if (priv_version) {
260
if (ret == -1) {
71
+ if (priv_version >= PRIV_VERSION_1_10_0) {
261
- if (mode == PRV_M) {
72
set_priv_version(env, priv_version);
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
73
- } else if (!env->priv_ver) {
263
- * M-Mode access, the access succeeds */
74
- set_priv_version(env, PRIV_VERSION_1_12_0);
264
- } else {
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
266
- * match a rule, but there are rules. We've checked for
267
- * no rule earlier in this function. */
268
- }
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
270
+ allowed_privs, mode);
271
}
75
}
272
76
273
return ret == 1 ? true : false;
77
if (cpu->cfg.mmu) {
274
}
275
276
-
277
/*
278
* Handle a write to a pmpcfg CSP
279
*/
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
281
282
return false;
283
}
284
+
285
+/*
286
+ * Convert PMP privilege to TLB page privilege.
287
+ */
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
289
+{
290
+ int prot = 0;
291
+
292
+ if (pmp_priv & PMP_READ) {
293
+ prot |= PAGE_READ;
294
+ }
295
+ if (pmp_priv & PMP_WRITE) {
296
+ prot |= PAGE_WRITE;
297
+ }
298
+ if (pmp_priv & PMP_EXEC) {
299
+ prot |= PAGE_EXEC;
300
+ }
301
+
302
+ return prot;
303
+}
304
--
78
--
305
2.30.1
79
2.36.1
306
307
diff view generated by jsdifflib
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
[PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
3
We previously stored the device tree at a 16MB alignment from the end of
4
the newest received byte. The rx_level variable is added to allow the use of
4
memory (or 3GB). This means we need at least 16MB of memory to be able
5
the existing OpenTitan driver libraries.
5
to do this. We don't actually need the FDT to be 16MB aligned, so let's
6
drop it down to 2MB so that we can support systems with less memory,
7
while also allowing FDT size expansion.
6
8
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
11
Reviewed-by: Atish Patra <atishp@rivosinc.com>
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
13
Tested-by: Bin Meng <bin.meng@windriver.com>
14
Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
include/hw/char/ibex_uart.h | 4 ++++
17
hw/riscv/boot.c | 4 ++--
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
18
1 file changed, 2 insertions(+), 2 deletions(-)
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
19
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
20
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
22
--- a/hw/riscv/boot.c
19
+++ b/include/hw/char/ibex_uart.h
23
+++ b/hw/riscv/boot.c
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
24
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
25
/*
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
26
* We should put fdt as far as possible to avoid kernel/initrd overwriting
23
REG32(FIFO_STATUS, 0x20)
27
* its content. But it should be addressable by 32 bit system as well.
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
28
- * Thus, put it at an 16MB aligned address that less than fdt size from the
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
29
+ * Thus, put it at an 2MB aligned address that less than fdt size from the
26
REG32(OVRD, 0x24)
30
* end of dram or 3GB whichever is lesser.
27
REG32(VAL, 0x28)
31
*/
28
REG32(TIMEOUT_CTRL, 0x2c)
32
temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
33
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
34
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
31
uint32_t tx_level;
35
32
36
ret = fdt_pack(fdt);
33
+ uint32_t rx_level;
37
/* Should only fail if we've built a corrupted tree */
34
+
35
QEMUTimer *fifo_trigger_handle;
36
uint64_t char_tx_time;
37
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/char/ibex_uart.c
41
+++ b/hw/char/ibex_uart.c
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
43
{
44
IbexUartState *s = opaque;
45
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
49
return 1;
50
}
51
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
53
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
+ /* The RXFULL is set after receiving a single byte
57
+ * as the FIFO buffers are not yet implemented.
58
+ */
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
+ s->rx_level += 1;
61
62
if (size > rx_fifo_level) {
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
s->uart_timeout_ctrl = 0x00000000;
66
67
s->tx_level = 0;
68
+ s->rx_level = 0;
69
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
74
case R_RDATA:
75
retvalue = s->uart_rdata;
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
qemu_chr_fe_accept_input(&s->chr);
79
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ s->rx_level -= 1;
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ if (s->rx_level == 0) {
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
+ }
88
}
89
break;
90
case R_WDATA:
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
38
--
110
2.30.1
39
2.36.1
111
112
diff view generated by jsdifflib
[PULL 01/16] target/riscv: fix vs() to return proper error code
[PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
3
The minimum priv spec versino for mcountinhibit to v1.11 so that it
4
is not enabled.
4
is not available for v1.10 (or lower).
5
5
6
If -1 is returned, exception will be raised and cs->exception_index will
6
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
7
be set to the negative return value. The exception will then be treated
7
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
8
as an instruction access fault instead of illegal instruction fault.
9
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
9
Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
11
---
16
target/riscv/csr.c | 2 +-
12
target/riscv/csr.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
18
14
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
15
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/csr.c
17
--- a/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
18
+++ b/target/riscv/csr.c
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
19
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
24
if (env->misa & RVV) {
20
write_mhpmcounter },
25
return 0;
21
26
}
22
[CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
27
- return -1;
23
- write_mcountinhibit },
28
+ return -RISCV_EXCP_ILLEGAL_INST;
24
+ write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 },
29
}
25
30
26
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
31
static int ctr(CPURISCVState *env, int csrno)
27
write_mhpmevent },
32
--
28
--
33
2.30.1
29
2.36.1
34
35
diff view generated by jsdifflib
[PULL 10/16] hw/riscv: allow ramfb on virt
[PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
1
From: Asherah Connor <ashe@kivikakk.ee>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
Allow ramfb on virt. This lets `-device ramfb' work.
3
Based on architecture review committee feedback, the [m|s|vs]seteienum,
4
4
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
5
removed in the latest AIA draft v0.3.0 specification.
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
7
8
These CSRs were mostly for software convenience and software can always
9
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
10
file bits.
11
12
We update the IMSIC CSR emulation as-per above to match the latest AIA
13
draft specification.
14
15
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
17
Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
19
---
11
hw/riscv/virt.c | 3 +++
20
target/riscv/cpu_bits.h | 24 +------
12
1 file changed, 3 insertions(+)
21
target/riscv/csr.c | 150 +---------------------------------------
13
22
2 files changed, 6 insertions(+), 168 deletions(-)
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
23
24
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
26
--- a/target/riscv/cpu_bits.h
17
+++ b/hw/riscv/virt.c
27
+++ b/target/riscv/cpu_bits.h
18
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
19
#include "sysemu/sysemu.h"
29
#define CSR_MIREG 0x351
20
#include "hw/pci/pci.h"
30
21
#include "hw/pci-host/gpex.h"
31
/* Machine-Level Interrupts (AIA) */
22
+#include "hw/display/ramfb.h"
32
-#define CSR_MTOPI 0xfb0
23
33
-
24
static const MemMapEntry virt_memmap[] = {
34
-/* Machine-Level IMSIC Interface (AIA) */
25
[VIRT_DEBUG] = { 0x0, 0x100 },
35
-#define CSR_MSETEIPNUM 0x358
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
36
-#define CSR_MCLREIPNUM 0x359
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
37
-#define CSR_MSETEIENUM 0x35a
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
38
-#define CSR_MCLREIENUM 0x35b
29
mc->numa_mem_supported = true;
39
#define CSR_MTOPEI 0x35c
30
+
40
+#define CSR_MTOPI 0xfb0
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
41
42
/* Virtual Interrupts for Supervisor Level (AIA) */
43
#define CSR_MVIEN 0x308
44
@@ -XXX,XX +XXX,XX @@
45
#define CSR_SIREG 0x151
46
47
/* Supervisor-Level Interrupts (AIA) */
48
-#define CSR_STOPI 0xdb0
49
-
50
-/* Supervisor-Level IMSIC Interface (AIA) */
51
-#define CSR_SSETEIPNUM 0x158
52
-#define CSR_SCLREIPNUM 0x159
53
-#define CSR_SSETEIENUM 0x15a
54
-#define CSR_SCLREIENUM 0x15b
55
#define CSR_STOPEI 0x15c
56
+#define CSR_STOPI 0xdb0
57
58
/* Supervisor-Level High-Half CSRs (AIA) */
59
#define CSR_SIEH 0x114
60
@@ -XXX,XX +XXX,XX @@
61
#define CSR_VSIREG 0x251
62
63
/* VS-Level Interrupts (H-extension with AIA) */
64
-#define CSR_VSTOPI 0xeb0
65
-
66
-/* VS-Level IMSIC Interface (H-extension with AIA) */
67
-#define CSR_VSSETEIPNUM 0x258
68
-#define CSR_VSCLREIPNUM 0x259
69
-#define CSR_VSSETEIENUM 0x25a
70
-#define CSR_VSCLREIENUM 0x25b
71
#define CSR_VSTOPEI 0x25c
72
+#define CSR_VSTOPI 0xeb0
73
74
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
75
#define CSR_HIDELEGH 0x613
76
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/riscv/csr.c
79
+++ b/target/riscv/csr.c
80
@@ -XXX,XX +XXX,XX @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
81
return CSR_VSISELECT;
82
case CSR_SIREG:
83
return CSR_VSIREG;
84
- case CSR_SSETEIPNUM:
85
- return CSR_VSSETEIPNUM;
86
- case CSR_SCLREIPNUM:
87
- return CSR_VSCLREIPNUM;
88
- case CSR_SSETEIENUM:
89
- return CSR_VSSETEIENUM;
90
- case CSR_SCLREIENUM:
91
- return CSR_VSCLREIENUM;
92
case CSR_STOPEI:
93
return CSR_VSTOPEI;
94
default:
95
@@ -XXX,XX +XXX,XX @@ done:
96
return RISCV_EXCP_NONE;
32
}
97
}
33
98
34
static const TypeInfo virt_machine_typeinfo = {
99
-static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
100
- target_ulong new_val, target_ulong wr_mask)
101
-{
102
- int ret = -EINVAL;
103
- bool set, pend, virt;
104
- target_ulong priv, isel, vgein, xlen, nval, wmask;
105
-
106
- /* Translate CSR number for VS-mode */
107
- csrno = aia_xlate_vs_csrno(env, csrno);
108
-
109
- /* Decode register details from CSR number */
110
- virt = set = pend = false;
111
- switch (csrno) {
112
- case CSR_MSETEIPNUM:
113
- priv = PRV_M;
114
- set = true;
115
- pend = true;
116
- break;
117
- case CSR_MCLREIPNUM:
118
- priv = PRV_M;
119
- pend = true;
120
- break;
121
- case CSR_MSETEIENUM:
122
- priv = PRV_M;
123
- set = true;
124
- break;
125
- case CSR_MCLREIENUM:
126
- priv = PRV_M;
127
- break;
128
- case CSR_SSETEIPNUM:
129
- priv = PRV_S;
130
- set = true;
131
- pend = true;
132
- break;
133
- case CSR_SCLREIPNUM:
134
- priv = PRV_S;
135
- pend = true;
136
- break;
137
- case CSR_SSETEIENUM:
138
- priv = PRV_S;
139
- set = true;
140
- break;
141
- case CSR_SCLREIENUM:
142
- priv = PRV_S;
143
- break;
144
- case CSR_VSSETEIPNUM:
145
- priv = PRV_S;
146
- virt = true;
147
- set = true;
148
- pend = true;
149
- break;
150
- case CSR_VSCLREIPNUM:
151
- priv = PRV_S;
152
- virt = true;
153
- pend = true;
154
- break;
155
- case CSR_VSSETEIENUM:
156
- priv = PRV_S;
157
- virt = true;
158
- set = true;
159
- break;
160
- case CSR_VSCLREIENUM:
161
- priv = PRV_S;
162
- virt = true;
163
- break;
164
- default:
165
- goto done;
166
- };
167
-
168
- /* IMSIC CSRs only available when machine implements IMSIC. */
169
- if (!env->aia_ireg_rmw_fn[priv]) {
170
- goto done;
171
- }
172
-
173
- /* Find the selected guest interrupt file */
174
- vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
175
-
176
- /* Selected guest interrupt file should be valid */
177
- if (virt && (!vgein || env->geilen < vgein)) {
178
- goto done;
179
- }
180
-
181
- /* Set/Clear CSRs always read zero */
182
- if (val) {
183
- *val = 0;
184
- }
185
-
186
- if (wr_mask) {
187
- /* Get interrupt number */
188
- new_val &= wr_mask;
189
-
190
- /* Find target interrupt pending/enable register */
191
- xlen = riscv_cpu_mxl_bits(env);
192
- isel = (new_val / xlen);
193
- isel *= (xlen / IMSIC_EIPx_BITS);
194
- isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
195
-
196
- /* Find the interrupt bit to be set/clear */
197
- wmask = ((target_ulong)1) << (new_val % xlen);
198
- nval = (set) ? wmask : 0;
199
-
200
- /* Call machine specific IMSIC register emulation */
201
- ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
202
- AIA_MAKE_IREG(isel, priv, virt,
203
- vgein, xlen),
204
- NULL, nval, wmask);
205
- } else {
206
- ret = 0;
207
- }
208
-
209
-done:
210
- if (ret) {
211
- return (riscv_cpu_virt_enabled(env) && virt) ?
212
- RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
213
- }
214
- return RISCV_EXCP_NONE;
215
-}
216
-
217
static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
218
target_ulong new_val, target_ulong wr_mask)
219
{
220
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
221
[CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
222
223
/* Machine-Level Interrupts (AIA) */
224
- [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
225
-
226
- /* Machine-Level IMSIC Interface (AIA) */
227
- [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
228
- [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
229
- [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
230
- [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
231
[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
232
+ [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
233
234
/* Virtual Interrupts for Supervisor Level (AIA) */
235
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
236
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
237
[CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
238
239
/* Supervisor-Level Interrupts (AIA) */
240
- [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
241
-
242
- /* Supervisor-Level IMSIC Interface (AIA) */
243
- [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
244
- [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
245
- [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
246
- [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
247
[CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
248
+ [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
249
250
/* Supervisor-Level High-Half CSRs (AIA) */
251
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
252
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
253
[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
254
255
/* VS-Level Interrupts (H-extension with AIA) */
256
- [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
257
-
258
- /* VS-Level IMSIC Interface (H-extension with AIA) */
259
- [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
260
- [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
261
- [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
262
- [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
263
[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
264
+ [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
265
266
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
267
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
35
--
268
--
36
2.30.1
269
2.36.1
37
38
diff view generated by jsdifflib
[PULL 04/16] target/riscv: add log of PMP permission checking
[PULL v2 19/19] target/riscv: Update default priority table for local interrupts
1
From: Jim Shu <cwshu@andestech.com>
1
From: Anup Patel <apatel@ventanamicro.com>
2
2
3
Like MMU translation, add qemu log of PMP permission checking for
3
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
4
debugging.
4
default priority assignments where:
5
5
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
6
and have implementation specific default priority.
7
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
8
(not mandatory) priority assignments.
9
10
We update the default priority table and hviprio mapping as-per above.
11
12
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
14
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
17
target/riscv/cpu_bits.h | 2 +-
12
1 file changed, 12 insertions(+)
18
target/riscv/cpu_helper.c | 134 ++++++++++++++++++--------------------
13
19
2 files changed, 66 insertions(+), 70 deletions(-)
20
21
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_bits.h
24
+++ b/target/riscv/cpu_bits.h
25
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
26
#define IPRIO_IRQ_BITS 8
27
#define IPRIO_MMAXIPRIO 255
28
#define IPRIO_DEFAULT_UPPER 4
29
-#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24)
30
+#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12)
31
#define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE
32
#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3)
33
#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3)
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
34
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
36
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
37
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
38
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_update_mask(CPURISCVState *env)
19
if (ret == TRANSLATE_SUCCESS) {
39
* 14 "
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
40
* 15 "
21
size, access_type, mode);
41
* 16 "
22
+
42
- * 18 Debug/trace interrupt
23
+ qemu_log_mask(CPU_LOG_MMU,
43
- * 20 (Reserved interrupt)
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
44
+ * 17 "
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
45
+ * 18 "
26
+ __func__, pa, ret, prot_pmp, tlb_size);
46
+ * 19 "
27
+
47
+ * 20 "
28
prot &= prot_pmp;
48
+ * 21 "
29
}
49
* 22 "
30
50
- * 24 "
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
51
- * 26 "
32
if (ret == TRANSLATE_SUCCESS) {
52
- * 28 "
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
53
- * 30 (Reserved for standard reporting of bus or system errors)
34
size, access_type, mode);
54
+ * 23 "
35
+
55
*/
36
+ qemu_log_mask(CPU_LOG_MMU,
56
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
57
static const int hviprio_index2irq[] = {
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
58
- 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
39
+ __func__, pa, ret, prot_pmp, tlb_size);
59
+ 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
40
+
60
static const int hviprio_index2rdzero[] = {
41
prot &= prot_pmp;
61
1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
42
}
62
43
}
63
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
64
* Default |
65
* Priority | Major Interrupt Numbers
66
* ----------------------------------------------------------------
67
- * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c),
68
- * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38),
69
- * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34),
70
- * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30)
71
+ * Highest | 47, 23, 46, 45, 22, 44,
72
+ * | 43, 21, 42, 41, 20, 40
73
* |
74
* | 11 (0b), 3 (03), 7 (07)
75
* | 9 (09), 1 (01), 5 (05)
76
* | 12 (0c)
77
* | 10 (0a), 2 (02), 6 (06)
78
* |
79
- * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c),
80
- * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28),
81
- * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24),
82
- * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20)
83
+ * | 39, 19, 38, 37, 18, 36,
84
+ * Lowest | 35, 17, 34, 33, 16, 32
85
* ----------------------------------------------------------------
86
*/
87
static const uint8_t default_iprio[64] = {
88
- [63] = IPRIO_DEFAULT_UPPER,
89
- [62] = IPRIO_DEFAULT_UPPER + 1,
90
- [31] = IPRIO_DEFAULT_UPPER + 2,
91
- [30] = IPRIO_DEFAULT_UPPER + 3,
92
- [61] = IPRIO_DEFAULT_UPPER + 4,
93
- [60] = IPRIO_DEFAULT_UPPER + 5,
94
-
95
- [59] = IPRIO_DEFAULT_UPPER + 6,
96
- [58] = IPRIO_DEFAULT_UPPER + 7,
97
- [29] = IPRIO_DEFAULT_UPPER + 8,
98
- [28] = IPRIO_DEFAULT_UPPER + 9,
99
- [57] = IPRIO_DEFAULT_UPPER + 10,
100
- [56] = IPRIO_DEFAULT_UPPER + 11,
101
-
102
- [55] = IPRIO_DEFAULT_UPPER + 12,
103
- [54] = IPRIO_DEFAULT_UPPER + 13,
104
- [27] = IPRIO_DEFAULT_UPPER + 14,
105
- [26] = IPRIO_DEFAULT_UPPER + 15,
106
- [53] = IPRIO_DEFAULT_UPPER + 16,
107
- [52] = IPRIO_DEFAULT_UPPER + 17,
108
-
109
- [51] = IPRIO_DEFAULT_UPPER + 18,
110
- [50] = IPRIO_DEFAULT_UPPER + 19,
111
- [25] = IPRIO_DEFAULT_UPPER + 20,
112
- [24] = IPRIO_DEFAULT_UPPER + 21,
113
- [49] = IPRIO_DEFAULT_UPPER + 22,
114
- [48] = IPRIO_DEFAULT_UPPER + 23,
115
+ /* Custom interrupts 48 to 63 */
116
+ [63] = IPRIO_MMAXIPRIO,
117
+ [62] = IPRIO_MMAXIPRIO,
118
+ [61] = IPRIO_MMAXIPRIO,
119
+ [60] = IPRIO_MMAXIPRIO,
120
+ [59] = IPRIO_MMAXIPRIO,
121
+ [58] = IPRIO_MMAXIPRIO,
122
+ [57] = IPRIO_MMAXIPRIO,
123
+ [56] = IPRIO_MMAXIPRIO,
124
+ [55] = IPRIO_MMAXIPRIO,
125
+ [54] = IPRIO_MMAXIPRIO,
126
+ [53] = IPRIO_MMAXIPRIO,
127
+ [52] = IPRIO_MMAXIPRIO,
128
+ [51] = IPRIO_MMAXIPRIO,
129
+ [50] = IPRIO_MMAXIPRIO,
130
+ [49] = IPRIO_MMAXIPRIO,
131
+ [48] = IPRIO_MMAXIPRIO,
132
+
133
+ /* Custom interrupts 24 to 31 */
134
+ [31] = IPRIO_MMAXIPRIO,
135
+ [30] = IPRIO_MMAXIPRIO,
136
+ [29] = IPRIO_MMAXIPRIO,
137
+ [28] = IPRIO_MMAXIPRIO,
138
+ [27] = IPRIO_MMAXIPRIO,
139
+ [26] = IPRIO_MMAXIPRIO,
140
+ [25] = IPRIO_MMAXIPRIO,
141
+ [24] = IPRIO_MMAXIPRIO,
142
+
143
+ [47] = IPRIO_DEFAULT_UPPER,
144
+ [23] = IPRIO_DEFAULT_UPPER + 1,
145
+ [46] = IPRIO_DEFAULT_UPPER + 2,
146
+ [45] = IPRIO_DEFAULT_UPPER + 3,
147
+ [22] = IPRIO_DEFAULT_UPPER + 4,
148
+ [44] = IPRIO_DEFAULT_UPPER + 5,
149
+
150
+ [43] = IPRIO_DEFAULT_UPPER + 6,
151
+ [21] = IPRIO_DEFAULT_UPPER + 7,
152
+ [42] = IPRIO_DEFAULT_UPPER + 8,
153
+ [41] = IPRIO_DEFAULT_UPPER + 9,
154
+ [20] = IPRIO_DEFAULT_UPPER + 10,
155
+ [40] = IPRIO_DEFAULT_UPPER + 11,
156
157
[11] = IPRIO_DEFAULT_M,
158
[3] = IPRIO_DEFAULT_M + 1,
159
@@ -XXX,XX +XXX,XX @@ static const uint8_t default_iprio[64] = {
160
[2] = IPRIO_DEFAULT_VS + 1,
161
[6] = IPRIO_DEFAULT_VS + 2,
162
163
- [47] = IPRIO_DEFAULT_LOWER,
164
- [46] = IPRIO_DEFAULT_LOWER + 1,
165
- [23] = IPRIO_DEFAULT_LOWER + 2,
166
- [22] = IPRIO_DEFAULT_LOWER + 3,
167
- [45] = IPRIO_DEFAULT_LOWER + 4,
168
- [44] = IPRIO_DEFAULT_LOWER + 5,
169
-
170
- [43] = IPRIO_DEFAULT_LOWER + 6,
171
- [42] = IPRIO_DEFAULT_LOWER + 7,
172
- [21] = IPRIO_DEFAULT_LOWER + 8,
173
- [20] = IPRIO_DEFAULT_LOWER + 9,
174
- [41] = IPRIO_DEFAULT_LOWER + 10,
175
- [40] = IPRIO_DEFAULT_LOWER + 11,
176
-
177
- [39] = IPRIO_DEFAULT_LOWER + 12,
178
- [38] = IPRIO_DEFAULT_LOWER + 13,
179
- [19] = IPRIO_DEFAULT_LOWER + 14,
180
- [18] = IPRIO_DEFAULT_LOWER + 15,
181
- [37] = IPRIO_DEFAULT_LOWER + 16,
182
- [36] = IPRIO_DEFAULT_LOWER + 17,
183
-
184
- [35] = IPRIO_DEFAULT_LOWER + 18,
185
- [34] = IPRIO_DEFAULT_LOWER + 19,
186
- [17] = IPRIO_DEFAULT_LOWER + 20,
187
- [16] = IPRIO_DEFAULT_LOWER + 21,
188
- [33] = IPRIO_DEFAULT_LOWER + 22,
189
- [32] = IPRIO_DEFAULT_LOWER + 23,
190
+ [39] = IPRIO_DEFAULT_LOWER,
191
+ [19] = IPRIO_DEFAULT_LOWER + 1,
192
+ [38] = IPRIO_DEFAULT_LOWER + 2,
193
+ [37] = IPRIO_DEFAULT_LOWER + 3,
194
+ [18] = IPRIO_DEFAULT_LOWER + 4,
195
+ [36] = IPRIO_DEFAULT_LOWER + 5,
196
+
197
+ [35] = IPRIO_DEFAULT_LOWER + 6,
198
+ [17] = IPRIO_DEFAULT_LOWER + 7,
199
+ [34] = IPRIO_DEFAULT_LOWER + 8,
200
+ [33] = IPRIO_DEFAULT_LOWER + 9,
201
+ [16] = IPRIO_DEFAULT_LOWER + 10,
202
+ [32] = IPRIO_DEFAULT_LOWER + 11,
203
};
204
205
uint8_t riscv_cpu_default_priority(int irq)
44
--
206
--
45
2.30.1
207
2.36.1
46
47
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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