Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/19] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+From: Alistair Francis <alistair@alistair23.me>
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
   Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging (2022-06-30 22:04:12 +0530)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220703
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 435774992e82d2d16f025afbb20b4f7be9b242b0:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  target/riscv: Update default priority table for local interrupts (2022-07-03 10:03:20 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Fifth RISC-V PR for QEMU 7.1
-This PR includes:
+* Fix register zero guarding for auipc and lui
- - Fix for vector CSR access
+* Ensure bins (mtval) is set correctly
- - Improvements to the Ibex UART device
+* Minimize the calls to decode_save_opc
- - PMP improvements and bug fixes
+* Guard against PMP ranges with a negative size
- - Hypervisor extension bug fixes
+* Implement mcountinhibit CSR
- - ramfb support for the virt machine
+* Add support for hpmcounters/hpmevents
- - Fast read support for SST flash
+* Improve PMU implenentation
- - Improvements to the microchip_pfsoc machine
+* Support mcycle/minstret write operation
 * Fixup MSECCFG minimum priv check
 * Ibex (OpenTitan) fixup priv version
 * Fix bug resulting in always using latest priv spec
 * Reduce FDT address alignment constraints
 * Set minumum priv spec version for mcountinhibit
 * AIA update to v0.3 of the spec
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Alistair Francis (3):
-      hw/char: disable ibex uart receive if the buffer is full
+      target/riscv: Fixup MSECCFG minimum priv check
       target/riscv: Ibex: Support priv version 1.11
       hw/riscv: boot: Reduce FDT address alignment constraints
-Asherah Connor (2):
+Anup Patel (4):
-      hw/riscv: Add fw_cfg support to virt
+      target/riscv: Don't force update priv spec version to latest
-      hw/riscv: allow ramfb on virt
+      target/riscv: Set minumum priv spec version for mcountinhibit
       target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
       target/riscv: Update default priority table for local interrupts
-Bin Meng (3):
+Atish Patra (7):
-      hw/block: m25p80: Support fast read for SST flashes
+      target/riscv: Fix PMU CSR predicate function
-      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+      target/riscv: Implement PMU CSR predicate function for S-mode
-      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+      target/riscv: pmu: Rename the counters extension to pmu
       target/riscv: pmu: Make number of counters configurable
       target/riscv: Implement mcountinhibit CSR
       target/riscv: Add support for hpmcounters/hpmevents
       target/riscv: Support mcycle/minstret write operation
-Frank Chang (1):
+Nicolas Pitre (1):
-      target/riscv: fix vs() to return proper error code
+      target/riscv/pmp: guard against PMP ranges with a negative size
-Georg Kotheimer (6):
+Richard Henderson (3):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+      target/riscv: Set env->bins in gen_exception_illegal
-      target/riscv: Make VSTIP and VSEIP read-only in hip
+      target/riscv: Remove generate_exception_mtval
-      target/riscv: Use background registers also for MSTATUS_MPV
+      target/riscv: Minimize the calls to decode_save_opc
       target/riscv: Fix read and write accesses to vsip and vsie
       target/riscv: Add proper two-stage lookup exception detection
       target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
+Víctor Colombo (1):
-      target/riscv: propagate PMP permission to TLB page
+      target/riscv: Remove condition guarding register zero for auipc and lui
       target/riscv: add log of PMP permission checking
       target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
+ target/riscv/cpu.h                             |  24 +-
- docs/system/target-riscv.rst               |   1 +
+ target/riscv/cpu_bits.h                        |  30 +-
- include/hw/char/ibex_uart.h                |   4 +
+ target/riscv/pmu.h                             |  28 +
- include/hw/riscv/microchip_pfsoc.h         |   1 +
+ hw/riscv/boot.c                                |   4 +-
- include/hw/riscv/virt.h                    |   2 +
+ target/riscv/cpu.c                             |  17 +-
- target/riscv/cpu.h                         |   4 +
+ target/riscv/cpu_helper.c                      | 134 ++--
- target/riscv/pmp.h                         |   4 +-
+ target/riscv/csr.c                             | 857 +++++++++++++++----------
- hw/block/m25p80.c                          |   3 +
+ target/riscv/machine.c                         |  25 +
- hw/char/ibex_uart.c                        |  23 +++-
+ target/riscv/pmp.c                             |   3 +
- hw/riscv/microchip_pfsoc.c                 |   6 +
+ target/riscv/pmu.c                             |  32 +
- hw/riscv/virt.c                            |  33 ++++++
+ target/riscv/translate.c                       |  31 +-
- target/riscv/cpu.c                         |   1 +
+ target/riscv/insn_trans/trans_privileged.c.inc |   4 +
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
+ target/riscv/insn_trans/trans_rvh.c.inc        |   2 +
- target/riscv/csr.c                         |  77 +++++++------
+ target/riscv/insn_trans/trans_rvi.c.inc        |  10 +-
- target/riscv/pmp.c                         |  84 ++++++++++----
+ target/riscv/meson.build                       |   3 +-
- target/riscv/translate.c                   | 179 +----------------------------
+ tests/tcg/riscv64/Makefile.softmmu-target      |  21 +
- hw/riscv/Kconfig                           |   1 +
+ tests/tcg/riscv64/issue1060.S                  |  53 ++
-files changed, 367 insertions(+), 289 deletions(-)
+ tests/tcg/riscv64/semihost.ld                  |  21 +
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+files changed, 843 insertions(+), 456 deletions(-)
+ create mode 100644 target/riscv/pmu.h
  create mode 100644 target/riscv/pmu.c
  create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
  create mode 100644 tests/tcg/riscv64/issue1060.S
  create mode 100644 tests/tcg/riscv64/semihost.ld

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 01/19] target/riscv: Remove condition guarding register zero for auipc and lui
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Víctor Colombo <victor.colombo@eldorado.org.br>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Commit 57c108b8646 introduced gen_set_gpri(), which already contains
-short of its purpose, as all it checks is whether two-stage address
+a check for if the destination register is 'zero'. The check in auipc
-translation either via the hypervisor-load store instructions or the
+and lui are then redundant. This patch removes those checks.
 MPRV feature would be allowed.
-What we really need instead is whether two-stage address translation was
+Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
-active when the exception was raised. However, in riscv_cpu_do_interrupt
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 we do not have the information to reliably detect this. Therefore, when
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
- target/riscv/cpu.c        |  1 +
+file changed, 2 insertions(+), 6 deletions(-)
  target/riscv/cpu_helper.c | 21 ++++++++-------------
 files changed, 13 insertions(+), 13 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
-     target_ulong satp_hs;
-     uint64_t mstatus_hs;
+ static bool trans_lui(DisasContext *ctx, arg_lui *a)
+ {
-+    /* Signals whether the current exception occurred with two-stage address
+-    if (a->rd != 0) {
-+       translation active. */
+-        gen_set_gpri(ctx, a->rd, a->imm);
-+    bool two_stage_lookup;
+-    }
-+
++    gen_set_gpri(ctx, a->rd, a->imm);
-     target_ulong scounteren;
+     return true;
      target_ulong mcounteren;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
      env->mcause = 0;
      env->pc = env->resetvec;
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE;
      env->load_res = -1;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
          g_assert_not_reached();
      }
      env->badaddr = address;
 +    env->two_stage_lookup = two_stage;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ {
-     }
+-    if (a->rd != 0) {
+-        gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
-     env->badaddr = addr;
+-    }
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
++    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
+     return true;
      riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
  }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
-         g_assert_not_reached();
-     }
-     env->badaddr = addr;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
-     riscv_raise_exception(env, cs->exception_index, retaddr);
- }
- #endif /* !CONFIG_USER_ONLY */
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         /* handle the trap in S-mode */
-         if (riscv_has_ext(env, RVH)) {
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
--            bool two_stage_lookup = false;
--            if (env->priv == PRV_M ||
--                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
--                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
--                    get_field(env->hstatus, HSTATUS_HU))) {
--                    two_stage_lookup = true;
--            }
--
--            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
-+            if (env->two_stage_lookup && write_tval) {
-                 /*
-                  * If we are writing a guest virtual address to stval, set
-                  * this to 1. If we are trapping to VS we will set this to 0
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-                 riscv_cpu_set_force_hs_excep(env, 0);
-             } else {
-                 /* Trap into HS mode */
--                if (!two_stage_lookup) {
--                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
--                                             riscv_cpu_virt_enabled(env));
--                }
-+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
-                 htval = env->guest_phys_fault_addr;
-             }
-         }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-      * RISC-V ISA Specification.
-      */
-+    env->two_stage_lookup = false;
- #endif
-     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
- }
 --
-.30.1
+.36.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 02/19] target/riscv: Set env->bins in gen_exception_illegal
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-This adds the documentation to describe what is supported for the
+While we set env->bins when unwinding for ILLEGAL_INST,
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+from e.g. csrrw, we weren't setting it for immediately
 illegal instructions.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Add a testcase for mtval via both exception paths.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ target/riscv/translate.c                  |  2 +
- docs/system/target-riscv.rst               |  1 +
+ tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++
-files changed, 90 insertions(+)
+ tests/tcg/riscv64/issue1060.S             | 53 +++++++++++++++++++++++
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ tests/tcg/riscv64/semihost.ld             | 21 +++++++++
 files changed, 97 insertions(+)
  create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
  create mode 100644 tests/tcg/riscv64/issue1060.S
  create mode 100644 tests/tcg/riscv64/semihost.ld
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
  static void gen_exception_illegal(DisasContext *ctx)
  {
 +    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
 +                   offsetof(CPURISCVState, bins));
      generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
  }
 diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
++++ b/tests/tcg/riscv64/Makefile.softmmu-target
 @@ -XXX,XX +XXX,XX @@
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
++#
-+=============================================================
++# RISC-V system tests
 +#
 +
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
++TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
++VPATH += $(TEST_SRC)
 +
-+For more details about Microchip PolarFire SoC, please see:
++LINK_SCRIPT = $(TEST_SRC)/semihost.ld
-+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
++LDFLAGS = -T $(LINK_SCRIPT)
 +CFLAGS += -g -Og
 +
-+The Icicle Kit board information can be found here:
++%.o: %.S
-+https://www.microsemi.com/existing-parts/parts/152514
++    $(CC) $(CFLAGS) $< -c -o $@
 +%: %.o $(LINK_SCRIPT)
 +    $(LD) $(LDFLAGS) $< -o $@
 +
-+Supported devices
++QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
 +-----------------
 +
-+The ``microchip-icicle-kit`` machine supports the following devices:
++EXTRA_RUNS += run-issue1060
 +run-issue1060: issue1060
 +    $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
 diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/tcg/riscv64/issue1060.S
@@ -XXX,XX +XXX,XX @@
 +    .option    norvc
 +
-+ * 1 E51 core
++    .text
-+ * 4 U54 cores
++    .global _start
-+ * Core Level Interruptor (CLINT)
++_start:
-+ * Platform-Level Interrupt Controller (PLIC)
++    lla    t0, trap
-+ * L2 Loosely Integrated Memory (L2-LIM)
++    csrw    mtvec, t0
 + * DDR memory controller
 + * 5 MMUARTs
 + * 1 DMA controller
 + * 2 GEM Ethernet controllers
 + * 1 SDHC storage controller
 +
-+Boot options
++    # These are all illegal instructions
-+------------
++    csrw    time, x0
 +    .insn    i CUSTOM_0, 0, x0, x0, 0x321
 +    csrw    time, x0
 +    .insn    i CUSTOM_0, 0, x0, x0, 0x123
 +    csrw    cycle, x0
 +
-+The ``microchip-icicle-kit`` machine can start using the standard -bios
++    # Success!
-+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
++    li    a0, 0
-+HSS loads the second stage bootloader U-Boot from an SD card. It does not
++    j    _exit
 +support direct kernel loading via the -kernel option. One has to load kernel
 +from U-Boot.
 +
-+The memory is set to 1537 MiB by default which is the minimum required high
++trap:
-+memory size by HSS. A sanity check on ram size is performed in the machine
++    # When an instruction traps, compare it to the insn in memory.
-+init routine to prompt user to increase the RAM size to > 1537 MiB when less
++    csrr    t0, mepc
-+than 1537 MiB ram is detected.
++    csrr    t1, mtval
 +    lwu    t2, 0(t0)
 +    bne    t1, t2, fail
 +
-+Boot the machine
++    # Skip the insn and continue.
-+----------------
++    addi    t0, t0, 4
 +    csrw    mepc, t0
 +    mret
 +
-+HSS 2020.12 release is tested at the time of writing. To build an HSS image
++fail:
-+that can be booted by the ``microchip-icicle-kit`` machine, type the following
++    li    a0, 1
 +in the HSS source tree:
 +
-+.. code-block:: bash
++# Exit code in a0
 +_exit:
 +    lla    a1, semiargs
 +    li    t0, 0x20026    # ADP_Stopped_ApplicationExit
 +    sd    t0, 0(a1)
 +    sd    a0, 8(a1)
 +    li    a0, 0x20    # TARGET_SYS_EXIT_EXTENDED
 +
-+  $ export CROSS_COMPILE=riscv64-linux-
++    # Semihosting call sequence
-+  $ cp boards/mpfs-icicle-kit-es/def_config .config
++    .balign    16
-+  $ make BOARD=mpfs-icicle-kit-es
++    slli    zero, zero, 0x1f
 +    ebreak
 +    srai    zero, zero, 0x7
 +    j    .
 +
-+Download the official SD card image released by Microchip and prepare it for
++    .data
-+QEMU usage:
++    .balign    16
 +semiargs:
 +    .space    16
 diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/tcg/riscv64/semihost.ld
@@ -XXX,XX +XXX,XX @@
 +ENTRY(_start)
 +
-+.. code-block:: bash
++SECTIONS
-+
++{
-+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++    /* virt machine, RAM starts at 2gb */
-+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++    . = 0x80000000;
-+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
++    .text : {
-+
++        *(.text)
-+Then we can boot the machine by:
++    }
-+
++    .rodata : {
-+.. code-block:: bash
++        *(.rodata)
-+
++    }
-+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
++    /* align r/w section to next 2mb */
-+      -bios path/to/hss.bin -sd path/to/sdcard.img \
++    . = ALIGN(1 << 21);
-+      -nic user,model=cadence_gem \
++    .data : {
-+      -nic tap,ifname=tap,model=cadence_gem,script=no \
++        *(.data)
-+      -display none -serial stdio \
++    }
-+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
++    .bss : {
-+      -serial chardev:serial1
++        *(.bss)
-+
++    }
-+With above command line, current terminal session will be used for the first
++}
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
 +  $ minicom -D unix\#serial1.sock
 +
 +HSS output is on the first serial port (stdio) and U-Boot outputs on the
 +second serial port. U-Boot will automatically load the Linux kernel from
 +the SD card image.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/target-riscv.rst
 +++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
  .. toctree::
     :maxdepth: 1
 +   riscv/microchip-icicle-kit
     riscv/sifive_u
  RISC-V CPU features
 --
-.30.1
+.36.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 03/19] target/riscv: Remove generate_exception_mtval
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+The function doesn't set mtval, it sets badaddr. Move the set
-further compressed instruction decoding. However, prior to this change,
+of badaddr directly into gen_exception_inst_addr_mis and use
-we did not raise an illegal instruction exception, if decode_RV32_64C()
+generate_exception.
 fails to decode the instruction. This means that we skipped illegal
 compressed instructions instead of raising an illegal instruction
 exception.
-Instead of patching decode_RV32_64C(), we can just remove it,
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 as it is dead code since f330433b363 anyway.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ target/riscv/translate.c | 11 ++---------
-file changed, 1 insertion(+), 178 deletions(-)
+file changed, 2 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
      CPUState *cs;
  } DisasContext;
 -#ifdef TARGET_RISCV64
 -/* convert riscv funct3 to qemu memop for load/store */
 -static const int tcg_memop_lookup[8] = {
 -    [0 ... 7] = -1,
 -    [0] = MO_SB,
 -    [1] = MO_TESW,
 -    [2] = MO_TESL,
 -    [3] = MO_TEQ,
 -    [4] = MO_UB,
 -    [5] = MO_TEUW,
 -    [6] = MO_TEUL,
 -};
 -#endif
 -
  #ifdef TARGET_RISCV64
  #define CASE_OP_32_64(X) case X: case glue(X, W)
  #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
--#ifdef TARGET_RISCV64
+-static void generate_exception_mtval(DisasContext *ctx, int excp)
 -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 -        target_long imm)
 -{
--    TCGv t0 = tcg_temp_new();
+-    gen_set_pc_imm(ctx, ctx->base.pc_next);
--    TCGv t1 = tcg_temp_new();
+-    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
--    gen_get_gpr(t0, rs1);
+-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
--    tcg_gen_addi_tl(t0, t0, imm);
+-    ctx->base.is_jmp = DISAS_NORETURN;
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
--static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+ static void gen_exception_illegal(DisasContext *ctx)
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
 -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
-     TCGv_i32 t0;
+     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
-     tcg_temp_free_i32(t0);
  static void gen_exception_inst_addr_mis(DisasContext *ctx)
  {
 -    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 +    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 +    generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
  }
--static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
+ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 -{
 -    uint8_t funct3 = extract16(opcode, 13, 3);
 -    uint8_t rd_rs2 = GET_C_RS2S(opcode);
 -    uint8_t rs1s = GET_C_RS1S(opcode);
 -
 -    switch (funct3) {
 -    case 3:
 -#if defined(TARGET_RISCV64)
 -        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 -        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 -                 GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 -        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 -                    GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    case 7:
 -#if defined(TARGET_RISCV64)
 -        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 -        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 -                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.36.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 04/19] target/riscv: Minimize the calls to decode_save_opc
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The previous implementation was broken in many ways:
+The set of instructions that require decode_save_opc for
- - Used mideleg instead of hideleg to mask accesses
+unwinding is really fairly small -- only insns that can
- - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
+raise ILLEGAL_INSN at runtime.  This includes CSR, anything
- - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
+that uses a *new* fp rounding mode, and many privileged insns.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Since unwind info is stored as the difference from the
 previous insn, storing a 0 for most insns minimizes the
 size of the unwind info.
 Booting a debian kernel image to the missing rootfs panic yields
 - gen code size       22226819/1026886656
 + gen code size       21601907/1026886656
 on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/translate.c                       | 18 +++++++++---------
-file changed, 34 insertions(+), 34 deletions(-)
+ target/riscv/insn_trans/trans_privileged.c.inc |  4 ++++
  target/riscv/insn_trans/trans_rvh.c.inc        |  2 ++
  target/riscv/insn_trans/trans_rvi.c.inc        |  2 ++
 files changed, 17 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/translate.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
-     return write_mstatus(env, CSR_MSTATUS, newval);
+     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static void decode_save_opc(DisasContext *ctx)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    assert(ctx->insn_start != NULL);
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
-+    return 0;
++    ctx->insn_start = NULL;
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+ static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
  {
-     if (riscv_cpu_virt_enabled(env)) {
+     if (get_xl(ctx) == MXL_RV32) {
--        /* Tell the guest the VS bits, shifted to the S bit locations */
+@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+         return;
 +        read_vsie(env, CSR_VSIE, val);
      } else {
          *val = env->mie & env->mideleg;
      }
-     return 0;
 +    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
 +    decode_save_opc(ctx);
      gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
  }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
-+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+ /* Include decoders for factored-out extensions */
- {
+ #include "decode-XVentanaCondOps.c.inc"
--    target_ulong newval;
-+    /* Shift the S bits to their VS bit location in mie */
+-static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
 +    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 +                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 +    return write_mie(env, CSR_MIE, newval);
 +}
 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +{
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the guests S bits to VS */
 -        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 -                 ((val << 1) & VS_MODE_INTERRUPTS);
 +        write_vsie(env, CSR_VSIE, val);
      } else {
 -        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 +        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 +                              (val & S_MODE_INTERRUPTS);
 +        write_mie(env, CSR_MIE, newval);
      }
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
  static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +                    target_ulong new_value, target_ulong write_mask)
 +{
 +    /* Shift the S bits to their VS bit location in mip */
 +    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
  static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
      int ret;
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the new values to line up with the VS bits */
 -        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 -                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
 -        ret &= vsip_writable_mask;
 -        ret >>= 1;
 +        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
      } else {
          ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                        write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                    target_ulong new_value, target_ulong write_mask)
 -{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
+-    assert(ctx->insn_start != NULL);
--                      write_mask & env->mideleg & vsip_writable_mask);
+-    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
--    return ret;
+-    ctx->insn_start = NULL;
 -}
 -
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 -{
 -    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
 -    return 0;
 -}
 -
 -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 -{
 -    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
 -    return write_mie(env, CSR_MIE, newval);
 -}
 -
  static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
  {
-     *val = env->vstvec;
+     /*
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
      /* Check for compressed insn */
      if (extract16(opcode, 0, 2) != 3) {
 -        decode_save_opc(ctx, opcode);
          if (!has_ext(ctx, RVC)) {
              gen_exception_illegal(ctx);
          } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          opcode32 = deposit32(opcode32, 16, 16,
                               translator_lduw(env, &ctx->base,
                                               ctx->base.pc_next + 2));
 -        decode_save_opc(ctx, opcode32);
          ctx->opcode = opcode32;
          ctx->pc_succ_insn = ctx->base.pc_next + 4;
 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_privileged.c.inc
 +++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
  {
  #ifndef CONFIG_USER_ONLY
      if (has_ext(ctx, RVS)) {
 +        decode_save_opc(ctx);
          gen_helper_sret(cpu_pc, cpu_env);
          tcg_gen_exit_tb(NULL, 0); /* no chaining */
          ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
  static bool trans_mret(DisasContext *ctx, arg_mret *a)
  {
  #ifndef CONFIG_USER_ONLY
 +    decode_save_opc(ctx);
      gen_helper_mret(cpu_pc, cpu_env);
      tcg_gen_exit_tb(NULL, 0); /* no chaining */
      ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
  static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
  {
  #ifndef CONFIG_USER_ONLY
 +    decode_save_opc(ctx);
      gen_set_pc_imm(ctx, ctx->pc_succ_insn);
      gen_helper_wfi(cpu_env);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
  static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
  {
  #ifndef CONFIG_USER_ONLY
 +    decode_save_opc(ctx);
      gen_helper_tlb_flush(cpu_env);
      return true;
  #endif
 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvh.c.inc
 +++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
  {
      REQUIRE_EXT(ctx, RVH);
  #ifndef CONFIG_USER_ONLY
 +    decode_save_opc(ctx);
      gen_helper_hyp_gvma_tlb_flush(cpu_env);
      return true;
  #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
  {
      REQUIRE_EXT(ctx, RVH);
  #ifndef CONFIG_USER_ONLY
 +    decode_save_opc(ctx);
      gen_helper_hyp_tlb_flush(cpu_env);
      return true;
  #endif
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
  static bool do_csr_post(DisasContext *ctx)
  {
 +    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
 +    decode_save_opc(ctx);
      /* We may have changed important cpu state -- exit to main loop. */
      gen_set_pc_imm(ctx, ctx->pc_succ_insn);
      tcg_gen_exit_tb(NULL, 0);
 --
-.30.1
+.36.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL 05/19] target/riscv/pmp: guard against PMP ranges with a negative size
-From: Jim Shu <cwshu@andestech.com>
+From: Nicolas Pitre <nico@fluxnic.net>
-If PMP permission of any address has been changed by updating PMP entry,
+For a TOR entry to match, the stard address must be lower than the end
-flush all TLB pages to prevent from getting old permission.
+address. Normally this is always the case, but correct code might still
 run into the following scenario:
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Initial state:
     pmpaddr3 = 0x2000    pmp3cfg = OFF
     pmpaddr4 = 0x3000    pmp4cfg = TOR
 Execution:
 . write 0x40ff to pmpaddr3
 . write 0x32ff to pmpaddr4
 . set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0
 . set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1
 When (2) is emulated, a call to pmp_update_rule() creates a negative
 range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated,
 a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return
 a very creatively large TLB size for pmp4. This, in turn, may result in
 accesses to non-existent/unitialized memory regions and a fault, so that
 (4) ends up never being executed.
 This is in m-mode with MPRV unset, meaning that unlocked PMP entries
 should have no effect. Therefore such a behavior based on PMP content
 is very unexpected.
 Make sure no negative PMP range can be created, whether explicitly by
 the emulated code or implicitly like the above.
 Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
+Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ target/riscv/pmp.c | 3 +++
-file changed, 4 insertions(+)
+file changed, 3 insertions(+)
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
- #include "qapi/error.h"
+     case PMP_AMATCH_TOR:
- #include "cpu.h"
+         sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
- #include "trace.h"
+         ea = (this_addr << 2) - 1u;
-+#include "exec/exec-all.h"
++        if (sa > ea) {
++            sa = ea = 0u;
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
++        }
-     uint8_t val);
+         break;
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
-         cfg_val = (val >> 8 * i)  & 0xff;
+     case PMP_AMATCH_NA4:
          pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
      }
 +
 +    /* If PMP permission of any addr has been changed, flush TLB pages. */
 +    tlb_flush(env_cpu(env));
  }
 --
-.30.1
+.36.1

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL 06/19] target/riscv: Fix PMU CSR predicate function
-From: Frank Chang <frank.chang@sifive.com>
+From: Atish Patra <atish.patra@wdc.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+The predicate function calculates the counter index incorrectly for
-is not enabled.
+hpmcounterx. Fix the counter index to reflect correct CSR number.
-If -1 is returned, exception will be raised and cs->exception_index will
+Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
 be set to the negative return value. The exception will then be treated
 as an instruction access fault instead of illegal instruction fault.
 Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Signed-off-by: Atish Patra <atish.patra@wdc.com>
 Signed-off-by: Atish Patra <atishp@rivosinc.com>
 Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/csr.c | 11 +++++++----
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 7 insertions(+), 4 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
-     if (env->misa & RVV) {
+ #if !defined(CONFIG_USER_ONLY)
-         return 0;
+     CPUState *cs = env_cpu(env);
-     }
+     RISCVCPU *cpu = RISCV_CPU(cs);
--    return -1;
++    int ctr_index;
-+    return -RISCV_EXCP_ILLEGAL_INST;
- }
+     if (!cpu->cfg.ext_counters) {
+         /* The Counters extensions is not enabled */
- static int ctr(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
              }
              break;
          case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
 -            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
 -                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
 +            ctr_index = csrno - CSR_CYCLE;
 +            if (!get_field(env->hcounteren, 1 << ctr_index) &&
 +                 get_field(env->mcounteren, 1 << ctr_index)) {
                  return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
              }
              break;
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                  }
                  break;
              case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 -                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 -                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 +                ctr_index = csrno - CSR_CYCLEH;
 +                if (!get_field(env->hcounteren, 1 << ctr_index) &&
 +                     get_field(env->mcounteren, 1 << ctr_index)) {
                      return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                  }
                  break;
 --
-.30.1
+.36.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+Deleted patch
-From: Alexander Wagner <alexander.wagner@ulal.de>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
-the newest received byte. The rx_level variable is added to allow the use of
-the existing OpenTitan driver libraries.
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/ibex_uart.h |  4 ++++
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
-files changed, 22 insertions(+), 5 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
-+++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
- REG32(OVRD, 0x24)
- REG32(VAL, 0x28)
- REG32(TIMEOUT_CTRL, 0x2c)
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
-     uint32_t tx_level;
-+    uint32_t rx_level;
-+
-     QEMUTimer *fifo_trigger_handle;
-     uint64_t char_tx_time;
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/ibex_uart.c
-+++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
- {
-     IbexUartState *s = opaque;
--    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
-+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
-         return 1;
-     }
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
-     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
-     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
-+    /* The RXFULL is set after receiving a single byte
-+     * as the FIFO buffers are not yet implemented.
-+     */
-+    s->uart_status |= R_STATUS_RXFULL_MASK;
-+    s->rx_level += 1;
-     if (size > rx_fifo_level) {
-         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
-     s->uart_timeout_ctrl = 0x00000000;
-     s->tx_level = 0;
-+    s->rx_level = 0;
-     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-     case R_RDATA:
-         retvalue = s->uart_rdata;
--        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
-             qemu_chr_fe_accept_input(&s->chr);
--            s->uart_status |= R_STATUS_RXIDLE_MASK;
--            s->uart_status |= R_STATUS_RXEMPTY_MASK;
-+            s->rx_level -= 1;
-+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
-+            if (s->rx_level == 0) {
-+                s->uart_status |= R_STATUS_RXIDLE_MASK;
-+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
-+            }
-         }
-         break;
-     case R_WDATA:
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-     case R_FIFO_STATUS:
-         retvalue = s->uart_fifo_status;
--        retvalue |= s->tx_level & 0x1F;
-+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
-+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: RX fifos are not supported\n", __func__);
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
-         s->uart_fifo_ctrl = value;
-         if (value & R_FIFO_CTRL_RXRST_MASK) {
-+            s->rx_level = 0;
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: RX fifos are not supported\n", __func__);
-         }
---
-.30.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
-Fix it by propagating PMP permission to TLB page permission.
-PMP permission checking also use MMU-style API to change TLB permission
-and size.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/pmp.h        |  4 +-
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
- target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
-files changed, 125 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
-+++ b/target/riscv/pmp.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
-     target_ulong val);
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode);
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-                          target_ulong *tlb_size);
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
- void pmp_update_rule_nums(CPURISCVState *env);
- uint32_t pmp_get_num_rules(CPURISCVState *env);
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
- #endif
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
-     env->load_res = -1;
- }
-+/*
-+ * get_physical_address_pmp - check PMP permission for this physical address
-+ *
-+ * Match the PMP region and check permission for this physical address and it's
-+ * TLB page. Returns 0 if the permission checking was successful
-+ *
-+ * @env: CPURISCVState
-+ * @prot: The returned protection attributes
-+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
-+ *            permission checking. NULL if not set TLB page for addr.
-+ * @addr: The physical address to be checked permission
-+ * @access_type: The type of MMU access
-+ * @mode: Indicates current privilege level.
-+ */
-+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
-+                                    target_ulong *tlb_size, hwaddr addr,
-+                                    int size, MMUAccessType access_type,
-+                                    int mode)
-+{
-+    pmp_priv_t pmp_priv;
-+    target_ulong tlb_size_pmp = 0;
-+
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
-+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-+        return TRANSLATE_SUCCESS;
-+    }
-+
-+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
-+                            mode)) {
-+        *prot = 0;
-+        return TRANSLATE_PMP_FAIL;
-+    }
-+
-+    *prot = pmp_priv_to_page_prot(pmp_priv);
-+    if (tlb_size != NULL) {
-+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
-+            *tlb_size = tlb_size_pmp;
-+        }
-+    }
-+
-+    return TRANSLATE_SUCCESS;
-+}
-+
- /* get_physical_address - get the physical address for this virtual address
-  *
-  * Do a page table walk to obtain the physical address corresponding to a
-@@ -XXX,XX +XXX,XX @@ restart:
-             pte_addr = base + idx * ptesize;
-         }
--        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
--            1 << MMU_DATA_LOAD, PRV_S)) {
-+        int pmp_prot;
-+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
-+                                               sizeof(target_ulong),
-+                                               MMU_DATA_LOAD, PRV_S);
-+        if (pmp_ret != TRANSLATE_SUCCESS) {
-             return TRANSLATE_PMP_FAIL;
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- #ifndef CONFIG_USER_ONLY
-     vaddr im_address;
-     hwaddr pa = 0;
--    int prot, prot2;
-+    int prot, prot2, prot_pmp;
-     bool pmp_violation = false;
-     bool first_stage_error = true;
-     bool two_stage_lookup = false;
-     int ret = TRANSLATE_FAIL;
-     int mode = mmu_idx;
--    target_ulong tlb_size = 0;
-+    /* default TLB page size */
-+    target_ulong tlb_size = TARGET_PAGE_SIZE;
-     env->guest_phys_fault_addr = 0;
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             prot &= prot2;
--            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--                (ret == TRANSLATE_SUCCESS) &&
--                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--                ret = TRANSLATE_PMP_FAIL;
-+            if (ret == TRANSLATE_SUCCESS) {
-+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                               size, access_type, mode);
-+                prot &= prot_pmp;
-             }
-             if (ret != TRANSLATE_SUCCESS) {
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                       "%s address=%" VADDR_PRIx " ret %d physical "
-                       TARGET_FMT_plx " prot %d\n",
-                       __func__, address, ret, pa, prot);
--    }
--    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--        (ret == TRANSLATE_SUCCESS) &&
--        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--        ret = TRANSLATE_PMP_FAIL;
-+        if (ret == TRANSLATE_SUCCESS) {
-+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                           size, access_type, mode);
-+            prot &= prot_pmp;
-+        }
-     }
-+
-     if (ret == TRANSLATE_PMP_FAIL) {
-         pmp_violation = true;
-     }
-     if (ret == TRANSLATE_SUCCESS) {
--        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
--            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
--                         prot, mmu_idx, tlb_size);
--        } else {
--            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--                         prot, mmu_idx, TARGET_PAGE_SIZE);
--        }
-+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-+                     prot, mmu_idx, tlb_size);
-         return true;
-     } else if (probe) {
-         return false;
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
-     return result;
- }
-+/*
-+ * Check if the address has required RWX privs when no PMP entry is matched.
-+ */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode)
-+{
-+    bool ret;
-+
-+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-+        /*
-+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
-+         * or no PMP entry matches an M-Mode access, the access succeeds.
-+         */
-+        ret = true;
-+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-+    } else {
-+        /*
-+         * Other modes are not allowed to succeed if they don't * match a rule,
-+         * but there are rules. We've checked for no rule earlier in this
-+         * function.
-+         */
-+        ret = false;
-+        *allowed_privs = 0;
-+    }
-+
-+    return ret;
-+}
-+
- /*
-  * Public Interface
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
-  * Check if the address has required RWX privs to complete desired operation
-  */
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
--    target_ulong size, pmp_priv_t privs, target_ulong mode)
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode)
- {
-     int i = 0;
-     int ret = -1;
-     int pmp_size = 0;
-     target_ulong s = 0;
-     target_ulong e = 0;
--    pmp_priv_t allowed_privs = 0;
-     /* Short cut if no rules */
-     if (0 == pmp_get_num_rules(env)) {
--        return (env->priv == PRV_M) ? true : false;
-+        return pmp_hart_has_privs_default(env, addr, size, privs,
-+                                          allowed_privs, mode);
-     }
-     if (size == 0) {
-@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-          * check
-          */
-         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
--            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
--                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
-+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
-             }
--            if ((privs & allowed_privs) == privs) {
--                ret = 1;
--                break;
--            } else {
--                ret = 0;
--                break;
--            }
-+            ret = ((privs & *allowed_privs) == privs);
-+            break;
-         }
-     }
-     /* No rule matched */
-     if (ret == -1) {
--        if (mode == PRV_M) {
--            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
--                      * M-Mode access, the access succeeds */
--        } else {
--            ret = 0; /* Other modes are not allowed to succeed if they don't
--                      * match a rule, but there are rules.  We've checked for
--                      * no rule earlier in this function. */
--        }
-+        return pmp_hart_has_privs_default(env, addr, size, privs,
-+                                          allowed_privs, mode);
-     }
-     return ret == 1 ? true : false;
- }
--
- /*
-  * Handle a write to a pmpcfg CSP
-  */
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-     return false;
- }
-+
-+/*
-+ * Convert PMP privilege to TLB page privilege.
-+ */
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
-+{
-+    int prot = 0;
-+
-+    if (pmp_priv & PMP_READ) {
-+        prot |= PAGE_READ;
-+    }
-+    if (pmp_priv & PMP_WRITE) {
-+        prot |= PAGE_WRITE;
-+    }
-+    if (pmp_priv & PMP_EXEC) {
-+        prot |= PAGE_EXEC;
-+    }
-+
-+    return prot;
-+}
---
-.30.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-Like MMU translation, add qemu log of PMP permission checking for
-debugging.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 12 ++++++++++++
-file changed, 12 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             if (ret == TRANSLATE_SUCCESS) {
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                                size, access_type, mode);
-+
-+                qemu_log_mask(CPU_LOG_MMU,
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
-+                              __func__, pa, ret, prot_pmp, tlb_size);
-+
-                 prot &= prot_pmp;
-             }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-         if (ret == TRANSLATE_SUCCESS) {
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                            size, access_type, mode);
-+
-+            qemu_log_mask(CPU_LOG_MMU,
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
-+                          __func__, pa, ret, prot_pmp, tlb_size);
-+
-             prot &= prot_pmp;
-         }
-     }
---
-.30.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-According to the specification the "field SPVP of hstatus controls the
-privilege level of the access" for the hypervisor virtual-machine load
-and store instructions HLV, HLVX and HSV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
-file changed, 14 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-         use_background = true;
-     }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
-             mode = get_field(env->mstatus, MSTATUS_MPP);
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
-                   __func__, address, access_type, mmu_idx);
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
--        if (get_field(env->mstatus, MSTATUS_MPRV)) {
--            mode = get_field(env->mstatus, MSTATUS_MPP);
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
-+               get_field(env->mstatus, MSTATUS_MPRV)) {
-+        mode = get_field(env->mstatus, MSTATUS_MPP);
-+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
-+            two_stage_lookup = true;
-         }
-     }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
--        access_type != MMU_INST_FETCH &&
--        get_field(env->mstatus, MSTATUS_MPRV) &&
--        get_field(env->mstatus, MSTATUS_MPV)) {
--        two_stage_lookup = true;
--    }
--
-     if (riscv_cpu_virt_enabled(env) ||
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-          access_type != MMU_INST_FETCH)) {
---
-.30.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 7 ++++---
-file changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
- static const char valid_vm_1_10_32[16] = {
-@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
- {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & hip_writable_mask);
-+                      write_mask & hvip_writable_mask);
--    *ret_value &= hip_writable_mask;
-+    *ret_value &= hvip_writable_mask;
-     return ret;
- }
---
-.30.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-The current condition for the use of background registers only
-considers the hypervisor load and store instructions,
-but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
-      */
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
-         use_background = true;
-     }
---
-.30.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+Deleted patch
-From: Asherah Connor <ashe@kivikakk.ee>
-Provides fw_cfg for the virt machine on riscv.  This enables
-using e.g.  ramfb later.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/virt.h |  2 ++
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
- hw/riscv/Kconfig        |  1 +
-files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
-     DeviceState *plic[VIRT_SOCKETS_MAX];
-     PFlashCFI01 *flash[2];
-+    FWCfgState *fw_cfg;
-     int fdt_size;
- };
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_PLIC,
-     VIRT_UART0,
-     VIRT_VIRTIO,
-+    VIRT_FW_CFG,
-     VIRT_FLASH,
-     VIRT_DRAM,
-     VIRT_PCIE_MMIO,
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
-+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
-     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
-     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
-     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
-@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-     return dev;
- }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
-+{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
-+    FWCfgState *fw_cfg;
-+    char *nodename;
-+
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
-+                                  &address_space_memory);
-+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-+
-+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-+    qemu_fdt_add_subnode(mc->fdt, nodename);
-+    qemu_fdt_setprop_string(mc->fdt, nodename,
-+                            "compatible", "qemu,fw-cfg-mmio");
-+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
-+                                 2, base, 2, size);
-+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
-+    g_free(nodename);
-+    return fw_cfg;
-+}
-+
- static void virt_machine_init(MachineState *machine)
- {
-     const MemMapEntry *memmap = virt_memmap;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-         start_addr = virt_memmap[VIRT_FLASH].base;
-     }
-+    /*
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-+     */
-+    s->fw_cfg = create_fw_cfg(machine);
-+    rom_set_fw(s->fw_cfg);
-+
-     /* Compute the fdt load address in dram */
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
-                                    machine->ram_size, machine->fdt);
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
-+++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
-     select SIFIVE_PLIC
-     select SIFIVE_TEST
-     select VIRTIO_MMIO
-+    select FW_CFG_DMA
- config SIFIVE_E
-     bool
---
-.30.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+Deleted patch
-From: Asherah Connor <ashe@kivikakk.ee>
-Allow ramfb on virt.  This lets `-device ramfb' work.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/sysemu.h"
- #include "hw/pci/pci.h"
- #include "hw/pci-host/gpex.h"
-+#include "hw/display/ramfb.h"
- static const MemMapEntry virt_memmap[] = {
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
-     mc->numa_mem_supported = true;
-+
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
- }
- static const TypeInfo virt_machine_typeinfo = {
---
-.30.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
-the address bytes. Note only SPI mode is supported by SST flashes.
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/block/m25p80.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
-     s->needed_bytes = get_addr_length(s);
-     switch (get_man(s)) {
-     /* Dummy cycles - modeled with bytes writes instead of bits */
-+    case MAN_SST:
-+        s->needed_bytes += 1;
-+        break;
-     case MAN_WINBOND:
-         s->needed_bytes += 8;
-         break;
---
-.30.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
-been updated to use a register mapped at 0x4f000000 instead of a
-GPIO to control whether eMMC or SD card is to be used. With this
-support the same HSS image can be used for both eMMC and SD card
-boot flow, while previously two different board configurations were
-used. This is undocumented but one can take a look at the HSS code
-HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/microchip_pfsoc.h | 1 +
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
-files changed, 7 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ enum {
-     MICROCHIP_PFSOC_ENVM_DATA,
-     MICROCHIP_PFSOC_QSPI_XIP,
-     MICROCHIP_PFSOC_IOSCB,
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
-     MICROCHIP_PFSOC_DRAM_LO,
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
-     MICROCHIP_PFSOC_DRAM_HI,
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
-+++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
-     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
-     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
-     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
-                     memmap[MICROCHIP_PFSOC_IOSCB].base);
-+    /* eMMC/SD mux */
-+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
-+
-     /* QSPI Flash */
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
-                            "microchip.pfsoc.qspi_xip",
---
-.30.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

From: Alistair Francis <alistair@alistair23.me>

The following changes since commit d495e432c04a6394126c35cf96517749708b410f:

Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging (2022-06-30 22:04:12 +0530)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220703

for you to fetch changes up to 435774992e82d2d16f025afbb20b4f7be9b242b0:

target/riscv: Update default priority table for local interrupts (2022-07-03 10:03:20 +1000)

----------------------------------------------------------------
Fifth RISC-V PR for QEMU 7.1

* Fix register zero guarding for auipc and lui
* Ensure bins (mtval) is set correctly
* Minimize the calls to decode_save_opc
* Guard against PMP ranges with a negative size
* Implement mcountinhibit CSR
* Add support for hpmcounters/hpmevents
* Improve PMU implenentation
* Support mcycle/minstret write operation
* Fixup MSECCFG minimum priv check
* Ibex (OpenTitan) fixup priv version
* Fix bug resulting in always using latest priv spec
* Reduce FDT address alignment constraints
* Set minumum priv spec version for mcountinhibit
* AIA update to v0.3 of the spec

----------------------------------------------------------------
Alistair Francis (3):
      target/riscv: Fixup MSECCFG minimum priv check
      target/riscv: Ibex: Support priv version 1.11
      hw/riscv: boot: Reduce FDT address alignment constraints

Anup Patel (4):
      target/riscv: Don't force update priv spec version to latest
      target/riscv: Set minumum priv spec version for mcountinhibit
      target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
      target/riscv: Update default priority table for local interrupts

Atish Patra (7):
      target/riscv: Fix PMU CSR predicate function
      target/riscv: Implement PMU CSR predicate function for S-mode
      target/riscv: pmu: Rename the counters extension to pmu
      target/riscv: pmu: Make number of counters configurable
      target/riscv: Implement mcountinhibit CSR
      target/riscv: Add support for hpmcounters/hpmevents
      target/riscv: Support mcycle/minstret write operation

Nicolas Pitre (1):
      target/riscv/pmp: guard against PMP ranges with a negative size

Richard Henderson (3):
      target/riscv: Set env->bins in gen_exception_illegal
      target/riscv: Remove generate_exception_mtval
      target/riscv: Minimize the calls to decode_save_opc

Víctor Colombo (1):
      target/riscv: Remove condition guarding register zero for auipc and lui

target/riscv/cpu.h                             |  24 +-
 target/riscv/cpu_bits.h                        |  30 +-
 target/riscv/pmu.h                             |  28 +
 hw/riscv/boot.c                                |   4 +-
 target/riscv/cpu.c                             |  17 +-
 target/riscv/cpu_helper.c                      | 134 ++--
 target/riscv/csr.c                             | 857 +++++++++++++++----------
 target/riscv/machine.c                         |  25 +
 target/riscv/pmp.c                             |   3 +
 target/riscv/pmu.c                             |  32 +
 target/riscv/translate.c                       |  31 +-
 target/riscv/insn_trans/trans_privileged.c.inc |   4 +
 target/riscv/insn_trans/trans_rvh.c.inc        |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc        |  10 +-
 target/riscv/meson.build                       |   3 +-
 tests/tcg/riscv64/Makefile.softmmu-target      |  21 +
 tests/tcg/riscv64/issue1060.S                  |  53 ++
 tests/tcg/riscv64/semihost.ld                  |  21 +
 18 files changed, 843 insertions(+), 456 deletions(-)
 create mode 100644 target/riscv/pmu.h
 create mode 100644 target/riscv/pmu.c
 create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
 create mode 100644 tests/tcg/riscv64/issue1060.S
 create mode 100644 tests/tcg/riscv64/semihost.ld

From: Víctor Colombo <victor.colombo@eldorado.org.br>

Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
 
 static bool trans_lui(DisasContext *ctx, arg_lui *a)
 {
-    if (a->rd != 0) {
-        gen_set_gpri(ctx, a->rd, a->imm);
-    }
+    gen_set_gpri(ctx, a->rd, a->imm);
     return true;
 }
 
 static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
 {
-    if (a->rd != 0) {
-        gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
-    }
+    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
     return true;
 }
 
-- 
2.36.1

From: Richard Henderson <richard.henderson@linaro.org>

While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.

Add a testcase for mtval via both exception paths.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                  |  2 +
 tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++
 tests/tcg/riscv64/issue1060.S             | 53 +++++++++++++++++++++++
 tests/tcg/riscv64/semihost.ld             | 21 +++++++++
 4 files changed, 97 insertions(+)
 create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
 create mode 100644 tests/tcg/riscv64/issue1060.S
 create mode 100644 tests/tcg/riscv64/semihost.ld

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
 
 static void gen_exception_illegal(DisasContext *ctx)
 {
+    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+                   offsetof(CPURISCVState, bins));
     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 }
 
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -XXX,XX +XXX,XX @@
+#
+# RISC-V system tests
+#
+
+TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
+VPATH += $(TEST_SRC)
+
+LINK_SCRIPT = $(TEST_SRC)/semihost.ld
+LDFLAGS = -T $(LINK_SCRIPT)
+CFLAGS += -g -Og
+
+%.o: %.S
+	$(CC) $(CFLAGS) $< -c -o $@
+%: %.o $(LINK_SCRIPT)
+	$(LD) $(LDFLAGS) $< -o $@
+
+QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
+
+EXTRA_RUNS += run-issue1060
+run-issue1060: issue1060
+	$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/issue1060.S
@@ -XXX,XX +XXX,XX @@
+	.option	norvc
+
+	.text
+	.global _start
+_start:
+	lla	t0, trap
+	csrw	mtvec, t0
+
+	# These are all illegal instructions
+	csrw	time, x0
+	.insn	i CUSTOM_0, 0, x0, x0, 0x321
+	csrw	time, x0
+	.insn	i CUSTOM_0, 0, x0, x0, 0x123
+	csrw	cycle, x0
+
+	# Success!
+	li	a0, 0
+	j	_exit
+
+trap:
+	# When an instruction traps, compare it to the insn in memory.
+	csrr	t0, mepc
+	csrr	t1, mtval
+	lwu	t2, 0(t0)
+	bne	t1, t2, fail
+
+	# Skip the insn and continue.
+	addi	t0, t0, 4
+	csrw	mepc, t0
+	mret
+
+fail:
+	li	a0, 1
+
+# Exit code in a0
+_exit:
+	lla	a1, semiargs
+	li	t0, 0x20026	# ADP_Stopped_ApplicationExit
+	sd	t0, 0(a1)
+	sd	a0, 8(a1)
+	li	a0, 0x20	# TARGET_SYS_EXIT_EXTENDED
+
+	# Semihosting call sequence
+	.balign	16
+	slli	zero, zero, 0x1f
+	ebreak
+	srai	zero, zero, 0x7
+	j	.
+
+	.data
+	.balign	16
+semiargs:
+	.space	16
diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/semihost.ld
@@ -XXX,XX +XXX,XX @@
+ENTRY(_start)
+
+SECTIONS
+{
+    /* virt machine, RAM starts at 2gb */
+    . = 0x80000000;
+    .text : {
+        *(.text)
+    }
+    .rodata : {
+        *(.rodata)
+    }
+    /* align r/w section to next 2mb */
+    . = ALIGN(1 << 21);
+    .data : {
+        *(.data)
+    }
+    .bss : {
+        *(.bss)
+    }
+}
-- 
2.36.1

From: Richard Henderson <richard.henderson@linaro.org>

The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void generate_exception_mtval(DisasContext *ctx, int excp)
-{
-    gen_set_pc_imm(ctx, ctx->base.pc_next);
-    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_exception_illegal(DisasContext *ctx)
 {
     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 {
-    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
+    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+    generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
-- 
2.36.1

From: Richard Henderson <richard.henderson@linaro.org>

The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime.  This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.

Since unwind info is stored as the difference from the
previous insn, storing a 0 for most insns minimizes the
size of the unwind info.

Booting a debian kernel image to the missing rootfs panic yields

- gen code size       22226819/1026886656
+ gen code size       21601907/1026886656

on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                       | 18 +++++++++---------
 target/riscv/insn_trans/trans_privileged.c.inc |  4 ++++
 target/riscv/insn_trans/trans_rvh.c.inc        |  2 ++
 target/riscv/insn_trans/trans_rvi.c.inc        |  2 ++
 4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void decode_save_opc(DisasContext *ctx)
+{
+    assert(ctx->insn_start != NULL);
+    tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
+    ctx->insn_start = NULL;
+}
+
 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
 {
     if (get_xl(ctx) == MXL_RV32) {
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
         return;
     }
 
+    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
+    decode_save_opc(ctx);
     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 }
 
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 /* Include decoders for factored-out extensions */
 #include "decode-XVentanaCondOps.c.inc"
 
-static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
-{
-    assert(ctx->insn_start != NULL);
-    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
-    ctx->insn_start = NULL;
-}
-
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 
     /* Check for compressed insn */
     if (extract16(opcode, 0, 2) != 3) {
-        decode_save_opc(ctx, opcode);
         if (!has_ext(ctx, RVC)) {
             gen_exception_illegal(ctx);
         } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         opcode32 = deposit32(opcode32, 16, 16,
                              translator_lduw(env, &ctx->base,
                                              ctx->base.pc_next + 2));
-        decode_save_opc(ctx, opcode32);
         ctx->opcode = opcode32;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
     if (has_ext(ctx, RVS)) {
+        decode_save_opc(ctx);
         gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     gen_helper_wfi(cpu_env);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 {
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_tlb_flush(cpu_env);
     return true;
 #endif
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
 {
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_hyp_gvma_tlb_flush(cpu_env);
     return true;
 #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
 {
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_hyp_tlb_flush(cpu_env);
     return true;
 #endif
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 
 static bool do_csr_post(DisasContext *ctx)
 {
+    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
+    decode_save_opc(ctx);
     /* We may have changed important cpu state -- exit to main loop. */
     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
-- 
2.36.1

From: Nicolas Pitre <nico@fluxnic.net>

For a TOR entry to match, the stard address must be lower than the end
address. Normally this is always the case, but correct code might still
run into the following scenario:

Initial state:

pmpaddr3 = 0x2000	pmp3cfg = OFF
	pmpaddr4 = 0x3000	pmp4cfg = TOR

Execution:

1. write 0x40ff to pmpaddr3
	2. write 0x32ff to pmpaddr4
	3. set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0
	4. set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1

When (2) is emulated, a call to pmp_update_rule() creates a negative
range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated,
a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return
a very creatively large TLB size for pmp4. This, in turn, may result in
accesses to non-existent/unitialized memory regions and a fault, so that
(4) ends up never being executed.

This is in m-mode with MPRV unset, meaning that unlocked PMP entries
should have no effect. Therefore such a behavior based on PMP content
is very unexpected.

Make sure no negative PMP range can be created, whether explicitly by
the emulated code or implicitly like the above.

Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
     case PMP_AMATCH_TOR:
         sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
         ea = (this_addr << 2) - 1u;
+        if (sa > ea) {
+            sa = ea = 0u;
+        }
         break;
 
     case PMP_AMATCH_NA4:
-- 
2.36.1

From: Atish Patra <atish.patra@wdc.com>

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 #if !defined(CONFIG_USER_ONLY)
     CPUState *cs = env_cpu(env);
     RISCVCPU *cpu = RISCV_CPU(cs);
+    int ctr_index;
 
     if (!cpu->cfg.ext_counters) {
         /* The Counters extensions is not enabled */
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
-                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+            ctr_index = csrno - CSR_CYCLE;
+            if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                 get_field(env->mcounteren, 1 << ctr_index)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                 }
                 break;
             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
-                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                ctr_index = csrno - CSR_CYCLEH;
+                if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                     get_field(env->mcounteren, 1 << ctr_index)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.36.1