Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/25] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:
   Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging (2022-06-09 08:25:17 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Fourth RISC-V PR for QEMU 7.1
-This PR includes:
+* Update MAINTAINERS
- - Fix for vector CSR access
+* Add support for Zmmul extension
- - Improvements to the Ibex UART device
+* Fixup FDT errors when supplying device tree from the command line for virt machine
- - PMP improvements and bug fixes
+* Avoid overflowing the addr_config buffer in the SiFive PLIC
- - Hypervisor extension bug fixes
+* Support -device loader addresses above 2GB
- - ramfb support for the virt machine
+* Correctly wake from WFI on VS-level external interrupts
- - Fast read support for SST flash
+* Fixes for RV128 support
- - Improvements to the microchip_pfsoc machine
+* Support Vector extension tail agnostic setting elements' bits to all 1s
 * Don't expose the CPU properties on named CPUs
 * Fix vector extension assert for RV32
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Alistair Francis (4):
-      hw/char: disable ibex uart receive if the buffer is full
+      MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section
       hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
       target/riscv: Don't expose the CPU properties on names CPUs
       target/riscv: trans_rvv: Avoid assert for RV32 and e64
-Asherah Connor (2):
+Andrew Bresticker (1):
-      hw/riscv: Add fw_cfg support to virt
+      target/riscv: Wake on VS-level external interrupts
       hw/riscv: allow ramfb on virt
-Bin Meng (3):
+Atish Patra (1):
-      hw/block: m25p80: Support fast read for SST flashes
+      hw/riscv: virt: Generate fw_cfg DT node correctly
       hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
       docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
-Frank Chang (1):
+Frédéric Pétrot (1):
-      target/riscv: fix vs() to return proper error code
+      target/riscv/debug.c: keep experimental rv128 support working
-Georg Kotheimer (6):
+Jamie Iles (1):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+      hw/core/loader: return image sizes as ssize_t
       target/riscv: Make VSTIP and VSEIP read-only in hip
       target/riscv: Use background registers also for MSTATUS_MPV
       target/riscv: Fix read and write accesses to vsip and vsie
       target/riscv: Add proper two-stage lookup exception detection
       target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
+Weiwei Li (1):
-      target/riscv: propagate PMP permission to TLB page
+      target/riscv: add support for zmmul extension v0.1
       target/riscv: add log of PMP permission checking
       target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
+eopXD (16):
- docs/system/target-riscv.rst               |   1 +
+      target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
- include/hw/char/ibex_uart.h                |   4 +
+      target/riscv: rvv: Prune redundant access_type parameter passed
- include/hw/riscv/microchip_pfsoc.h         |   1 +
+      target/riscv: rvv: Rename ambiguous esz
- include/hw/riscv/virt.h                    |   2 +
+      target/riscv: rvv: Early exit when vstart >= vl
- target/riscv/cpu.h                         |   4 +
+      target/riscv: rvv: Add tail agnostic for vv instructions
- target/riscv/pmp.h                         |   4 +-
+      target/riscv: rvv: Add tail agnostic for vector load / store instructions
- hw/block/m25p80.c                          |   3 +
+      target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
- hw/char/ibex_uart.c                        |  23 +++-
+      target/riscv: rvv: Add tail agnostic for vector integer shift instructions
- hw/riscv/microchip_pfsoc.c                 |   6 +
+      target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
- hw/riscv/virt.c                            |  33 ++++++
+      target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
- target/riscv/cpu.c                         |   1 +
+      target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
+      target/riscv: rvv: Add tail agnostic for vector floating-point instructions
- target/riscv/csr.c                         |  77 +++++++------
+      target/riscv: rvv: Add tail agnostic for vector reduction instructions
- target/riscv/pmp.c                         |  84 ++++++++++----
+      target/riscv: rvv: Add tail agnostic for vector mask instructions
- target/riscv/translate.c                   | 179 +----------------------------
+      target/riscv: rvv: Add tail agnostic for vector permutation instructions
- hw/riscv/Kconfig                           |   1 +
+      target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
 files changed, 367 insertions(+), 289 deletions(-)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ include/hw/loader.h                     |   55 +-
+ target/riscv/cpu.h                      |    4 +
+ target/riscv/internals.h                |    6 +-
+ hw/arm/armv7m.c                         |    2 +-
+ hw/arm/boot.c                           |    8 +-
+ hw/core/generic-loader.c                |    2 +-
+ hw/core/loader.c                        |   81 +-
+ hw/i386/x86.c                           |    2 +-
+ hw/intc/sifive_plic.c                   |   19 +-
+ hw/riscv/boot.c                         |    5 +-
+ hw/riscv/virt.c                         |   28 +-
+ target/riscv/cpu.c                      |   68 +-
+ target/riscv/cpu_helper.c               |    4 +-
+ target/riscv/debug.c                    |    2 +
+ target/riscv/translate.c                |    4 +
+ target/riscv/vector_helper.c            | 1588 +++++++++++++++++++------------
+ target/riscv/insn_trans/trans_rvm.c.inc |   18 +-
+ target/riscv/insn_trans/trans_rvv.c.inc |  106 ++-
+ MAINTAINERS                             |    1 +
+files changed, 1244 insertions(+), 759 deletions(-)

-New patch
+[PULL 01/25] MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section
+From: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-Id: <20220509091339.26016-1-alistair.francis@wdc.com>
+---
+ MAINTAINERS | 1 +
+file changed, 1 insertion(+)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ Generic Loader
+ M: Alistair Francis <alistair@alistair23.me>
+ S: Maintained
+ F: hw/core/generic-loader.c
++F: hw/core/uboot_image.h
+ F: include/hw/core/generic-loader.h
+ F: docs/system/generic-loader.rst
+--
+.36.1

-New patch
+[PULL 02/25] target/riscv: add support for zmmul extension v0.1
+From: Weiwei Li <liweiwei@iscas.ac.cn>
+Add support for the zmmul extension v0.1. This extension includes all
+multiplication operations from the M extension but not the divide ops.
+Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h                      |  1 +
+ target/riscv/cpu.c                      |  7 +++++++
+ target/riscv/insn_trans/trans_rvm.c.inc | 18 ++++++++++++------
+files changed, 20 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zhinxmin;
+     bool ext_zve32f;
+     bool ext_zve64f;
++    bool ext_zmmul;
+     uint32_t mvendorid;
+     uint64_t marchid;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_ifencei = true;
+         }
++        if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
++            warn_report("Zmmul will override M");
++            cpu->cfg.ext_m = false;
++        }
++
+         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+             error_setg(errp,
+                        "I and E extensions are incompatible");
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     /* These are experimental so mark with 'x-' */
+     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
++    DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false),
+     /* ePMP 0.9.3 */
+     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+     struct isa_ext_data isa_edata_arr[] = {
+         ISA_EDATA_ENTRY(zicsr, ext_icsr),
+         ISA_EDATA_ENTRY(zifencei, ext_ifencei),
++        ISA_EDATA_ENTRY(zmmul, ext_zmmul),
+         ISA_EDATA_ENTRY(zfh, ext_zfh),
+         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvm.c.inc
++++ b/target/riscv/insn_trans/trans_rvm.c.inc
+@@ -XXX,XX +XXX,XX @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
++#define REQUIRE_M_OR_ZMMUL(ctx) do {                      \
++    if (!ctx->cfg_ptr->ext_zmmul && !has_ext(ctx, RVM)) { \
++        return false;                                     \
++    }                                                     \
++} while (0)
++
+ static void gen_mulhu_i128(TCGv r2, TCGv r3, TCGv al, TCGv ah, TCGv bl, TCGv bh)
+ {
+     TCGv tmpl = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static void gen_mul_i128(TCGv rl, TCGv rh,
+ static bool trans_mul(DisasContext *ctx, arg_mul *a)
+ {
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, gen_mul_i128);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
+ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+ {
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w,
+                             gen_mulh_i128);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
+ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+ {
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w,
+                             gen_mulhsu_i128);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
+ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+ {
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     /* gen_mulh_w works for either sign as input. */
+     return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w,
+                             gen_mulhu_i128);
+@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
+ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+ {
+     REQUIRE_64_OR_128BIT(ctx);
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     ctx->ol = MXL_RV32;
+     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+ static bool trans_muld(DisasContext *ctx, arg_muld *a)
+ {
+     REQUIRE_128BIT(ctx);
+-    REQUIRE_EXT(ctx, RVM);
++    REQUIRE_M_OR_ZMMUL(ctx);
+     ctx->ol = MXL_RV64;
+     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_mul_tl, NULL);
+ }
+--
+.36.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL 03/25] hw/riscv: virt: Generate fw_cfg DT node correctly
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Atish Patra <atishp@rivosinc.com>
-Provides fw_cfg for the virt machine on riscv.  This enables
+fw_cfg DT node is generated after the create_fdt without any check
-using e.g.  ramfb later.
+if the DT is being loaded from the commandline. This results in
 FDT_ERR_EXISTS error if dtb is loaded from the commandline.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Generate fw_cfg node only if the DT is not loaded from the commandline.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Signed-off-by: Atish Patra <atishp@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-Id: <20220526203500.847165-1-atishp@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ hw/riscv/virt.c | 28 ++++++++++++++++++----------
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+file changed, 18 insertions(+), 10 deletions(-)
  hw/riscv/Kconfig        |  1 +
 files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
-     DeviceState *plic[VIRT_SOCKETS_MAX];
-     PFlashCFI01 *flash[2];
-+    FWCfgState *fw_cfg;
-     int fdt_size;
- };
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_PLIC,
-     VIRT_UART0,
-     VIRT_VIRTIO,
-+    VIRT_FW_CFG,
-     VIRT_FLASH,
-     VIRT_DRAM,
-     VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+     g_free(name);
      [VIRT_UART0] =       { 0x10000000,         0x100 },
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
 +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
      return dev;
  }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
++static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
 +{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
-+    FWCfgState *fw_cfg;
 +    char *nodename;
-+
++    MachineState *mc = MACHINE(s);
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
++    hwaddr base = memmap[VIRT_FW_CFG].base;
-+                                  &address_space_memory);
++    hwaddr size = memmap[VIRT_FW_CFG].size;
 +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
 +
 +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
 +    qemu_fdt_add_subnode(mc->fdt, nodename);
 +    qemu_fdt_setprop_string(mc->fdt, nodename,
 +                            "compatible", "qemu,fw-cfg-mmio");
 +    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
 +                                 2, base, 2, size);
 +    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 +    g_free(nodename);
-+    return fw_cfg;
 +}
 +
- static void virt_machine_init(MachineState *machine)
+ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
                         uint64_t mem_size, const char *cmdline, bool is_32_bit)
  {
-     const MemMapEntry *memmap = virt_memmap;
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+     create_fdt_rtc(s, memmap, irq_mmio_phandle);
-         start_addr = virt_memmap[VIRT_FLASH].base;
-     }
+     create_fdt_flash(s, memmap);
++    create_fdt_fw_cfg(s, memmap);
-+    /*
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+ update_bootargs:
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     if (cmdline && *cmdline) {
-+     */
+@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-+    s->fw_cfg = create_fw_cfg(machine);
+ static FWCfgState *create_fw_cfg(const MachineState *mc)
-+    rom_set_fw(s->fw_cfg);
+ {
-+
+     hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-     /* Compute the fdt load address in dram */
+-    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+     FWCfgState *fw_cfg;
-                                    machine->ram_size, machine->fdt);
+-    char *nodename;
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
-index XXXXXXX..XXXXXXX 100644
+     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
---- a/hw/riscv/Kconfig
+                                   &address_space_memory);
-+++ b/hw/riscv/Kconfig
+     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
-     select SIFIVE_PLIC
+-    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-     select SIFIVE_TEST
+-    qemu_fdt_add_subnode(mc->fdt, nodename);
-     select VIRTIO_MMIO
+-    qemu_fdt_setprop_string(mc->fdt, nodename,
-+    select FW_CFG_DMA
+-                            "compatible", "qemu,fw-cfg-mmio");
+-    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
- config SIFIVE_E
+-                                 2, base, 2, size);
-     bool
+-    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 -    g_free(nodename);
      return fw_cfg;
  }
 --
-.30.1
+.36.1

-New patch
+[PULL 04/25] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
+From: Alistair Francis <alistair.francis@wdc.com>
+Since commit ad40be27 "target/riscv: Support start kernel directly by
+KVM" we have been overflowing the addr_config on "M,MS..."
+configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.
+This commit changes the loop in sifive_plic_create() from iterating over
+the number of harts to just iterating over the addr_config. The
+addr_config is based on the hart_config, and will contain interrup details
+for all harts. This way we can't iterate past the end of addr_config.
+Fixes: ad40be27084536 ("target/riscv: Support start kernel directly by KVM")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1050
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-Id: <20220601013631.196854-1-alistair.francis@opensource.wdc.com>
+---
+ hw/intc/sifive_plic.c | 19 +++++++++----------
+file changed, 9 insertions(+), 10 deletions(-)
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/sifive_plic.c
++++ b/hw/intc/sifive_plic.c
+@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
+     uint32_t context_stride, uint32_t aperture_size)
+ {
+     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
+-    int i, j = 0;
++    int i;
+     SiFivePLICState *plic;
+     assert(enable_stride == (enable_stride & -enable_stride));
+@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
+     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+     plic = SIFIVE_PLIC(dev);
+-    for (i = 0; i < num_harts; i++) {
+-        CPUState *cpu = qemu_get_cpu(hartid_base + i);
+-        if (plic->addr_config[j].mode == PLICMode_M) {
+-            j++;
+-            qdev_connect_gpio_out(dev, num_harts + i,
++    for (i = 0; i < plic->num_addrs; i++) {
++        int cpu_num = plic->addr_config[i].hartid;
++        CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num);
++
++        if (plic->addr_config[i].mode == PLICMode_M) {
++            qdev_connect_gpio_out(dev, num_harts + cpu_num,
+                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+         }
+-
+-        if (plic->addr_config[j].mode == PLICMode_S) {
+-            j++;
+-            qdev_connect_gpio_out(dev, i,
++        if (plic->addr_config[i].mode == PLICMode_S) {
++            qdev_connect_gpio_out(dev, cpu_num,
+                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
+         }
+     }
+--
+.36.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL 05/25] hw/core/loader: return image sizes as ssize_t
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Jamie Iles <jamie@nuviainc.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Various loader functions return an int which limits images to 2GB which
 is fine for things like a BIOS/kernel image, but if we want to be able
 to load memory images or large ramdisks then any file over 2GB would
 silently fail to load.
 Cc: Luc Michel <lmichel@kalray.eu>
 Signed-off-by: Jamie Iles <jamie@nuviainc.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Luc Michel <lmichel@kalray.eu>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20211111141141.3295094-2-jamie@nuviainc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ include/hw/loader.h      | 55 +++++++++++++--------------
-file changed, 4 insertions(+), 3 deletions(-)
+ hw/arm/armv7m.c          |  2 +-
  hw/arm/boot.c            |  8 ++--
  hw/core/generic-loader.c |  2 +-
  hw/core/loader.c         | 81 +++++++++++++++++++++-------------------
  hw/i386/x86.c            |  2 +-
  hw/riscv/boot.c          |  5 ++-
 files changed, 80 insertions(+), 75 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/include/hw/loader.h b/include/hw/loader.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/include/hw/loader.h
-+++ b/target/riscv/csr.c
++++ b/include/hw/loader.h
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+  *
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+  * Returns the size of the loaded image on success, -1 otherwise.
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+  */
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+-int load_image_targphys_as(const char *filename,
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
+-                           hwaddr addr, uint64_t max_sz, AddressSpace *as);
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
++ssize_t load_image_targphys_as(const char *filename,
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
++                               hwaddr addr, uint64_t max_sz, AddressSpace *as);
- static const char valid_vm_1_10_32[16] = {
+ /**load_targphys_hex_as:
-@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+  * @filename: Path to the .hex file
-                    target_ulong new_value, target_ulong write_mask)
+@@ -XXX,XX +XXX,XX @@ int load_image_targphys_as(const char *filename,
- {
+  *
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+  * Returns the size of the loaded .hex file on success, -1 otherwise.
--                      write_mask & hip_writable_mask);
+  */
-+                      write_mask & hvip_writable_mask);
+-int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as);
++ssize_t load_targphys_hex_as(const char *filename, hwaddr *entry,
--    *ret_value &= hip_writable_mask;
++                             AddressSpace *as);
-+    *ret_value &= hvip_writable_mask;
+ /** load_image_targphys:
   * Same as load_image_targphys_as(), but doesn't allow the caller to specify
   * an AddressSpace.
   */
 -int load_image_targphys(const char *filename, hwaddr,
 -                        uint64_t max_sz);
 +ssize_t load_image_targphys(const char *filename, hwaddr,
 +                            uint64_t max_sz);
  /**
   * load_image_mr: load an image into a memory region
@@ -XXX,XX +XXX,XX @@ int load_image_targphys(const char *filename, hwaddr,
   * If the file is larger than the memory region's size the call will fail.
   * Returns -1 on failure, or the size of the file.
   */
 -int load_image_mr(const char *filename, MemoryRegion *mr);
 +ssize_t load_image_mr(const char *filename, MemoryRegion *mr);
  /* This is the limit on the maximum uncompressed image size that
   * load_image_gzipped_buffer() and load_image_gzipped() will read. It prevents
@@ -XXX,XX +XXX,XX @@ int load_image_mr(const char *filename, MemoryRegion *mr);
   */
  #define LOAD_IMAGE_MAX_GUNZIP_BYTES (256 << 20)
 -int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
 -                              uint8_t **buffer);
 -int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
 +ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
 +                                  uint8_t **buffer);
 +ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
  #define ELF_LOAD_FAILED       -1
  #define ELF_LOAD_NOT_ELF      -2
@@ -XXX,XX +XXX,XX @@ ssize_t load_elf(const char *filename,
   */
  void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp);
 -int load_aout(const char *filename, hwaddr addr, int max_sz,
 -              int bswap_needed, hwaddr target_page_size);
 +ssize_t load_aout(const char *filename, hwaddr addr, int max_sz,
 +                  int bswap_needed, hwaddr target_page_size);
  #define LOAD_UIMAGE_LOADADDR_INVALID (-1)
@@ -XXX,XX +XXX,XX @@ int load_aout(const char *filename, hwaddr addr, int max_sz,
   *
   * Returns the size of the loaded image on success, -1 otherwise.
   */
 -int load_uimage_as(const char *filename, hwaddr *ep,
 -                   hwaddr *loadaddr, int *is_linux,
 -                   uint64_t (*translate_fn)(void *, uint64_t),
 -                   void *translate_opaque, AddressSpace *as);
 +ssize_t load_uimage_as(const char *filename, hwaddr *ep,
 +                       hwaddr *loadaddr, int *is_linux,
 +                       uint64_t (*translate_fn)(void *, uint64_t),
 +                       void *translate_opaque, AddressSpace *as);
  /** load_uimage:
   * Same as load_uimage_as(), but doesn't allow the caller to specify an
   * AddressSpace.
   */
 -int load_uimage(const char *filename, hwaddr *ep,
 -                hwaddr *loadaddr, int *is_linux,
 -                uint64_t (*translate_fn)(void *, uint64_t),
 -                void *translate_opaque);
 +ssize_t load_uimage(const char *filename, hwaddr *ep,
 +                    hwaddr *loadaddr, int *is_linux,
 +                    uint64_t (*translate_fn)(void *, uint64_t),
 +                    void *translate_opaque);
  /**
   * load_ramdisk_as:
@@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep,
   *
   * Returns the size of the loaded image on success, -1 otherwise.
   */
 -int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
 -                    AddressSpace *as);
 +ssize_t load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
 +                        AddressSpace *as);
  /**
   * load_ramdisk:
   * Same as load_ramdisk_as(), but doesn't allow the caller to specify
   * an AddressSpace.
   */
 -int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz);
 +ssize_t load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz);
  ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen);
@@ -XXX,XX +XXX,XX @@ void pstrcpy_targphys(const char *name,
  extern bool option_rom_has_mr;
  extern bool rom_file_has_mr;
 -int rom_add_file(const char *file, const char *fw_dir,
 -                 hwaddr addr, int32_t bootindex,
 -                 bool option_rom, MemoryRegion *mr, AddressSpace *as);
 +ssize_t rom_add_file(const char *file, const char *fw_dir,
 +                     hwaddr addr, int32_t bootindex,
 +                     bool option_rom, MemoryRegion *mr, AddressSpace *as);
  MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
                             size_t max_len, hwaddr addr,
                             const char *fw_file_name,
@@ -XXX,XX +XXX,XX @@ void hmp_info_roms(Monitor *mon, const QDict *qdict);
  #define rom_add_blob_fixed_as(_f, _b, _l, _a, _as)      \
      rom_add_blob(_f, _b, _l, _l, _a, NULL, NULL, NULL, _as, true)
 -int rom_add_vga(const char *file);
 -int rom_add_option(const char *file, int32_t bootindex);
 +ssize_t rom_add_vga(const char *file);
 +ssize_t rom_add_option(const char *file, int32_t bootindex);
  /* This is the usual maximum in uboot, so if a uImage overflows this, it would
   * overflow on real hardware too. */
 diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armv7m.c
 +++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
  void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
  {
 -    int image_size;
 +    ssize_t image_size;
      uint64_t entry;
      int big_endian;
      AddressSpace *as;
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/boot.c
 +++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque)
      return 0;
  }
 -static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
 +static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
                              uint64_t *lowaddr, uint64_t *highaddr,
                              int elf_machine, AddressSpace *as)
  {
@@ -XXX,XX +XXX,XX @@ static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
      } elf_header;
      int data_swab = 0;
      bool big_endian;
 -    int64_t ret = -1;
 +    ssize_t ret = -1;
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
      /* Set up for a direct boot of a kernel image file. */
      CPUState *cs;
      AddressSpace *as = arm_boot_address_space(cpu, info);
 -    int kernel_size;
 +    ssize_t kernel_size;
      int initrd_size;
      int is_linux = 0;
      uint64_t elf_entry;
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
      if (kernel_size > info->ram_size) {
          error_report("kernel '%s' is too large to fit in RAM "
 -                     "(kernel size %d, RAM size %" PRId64 ")",
 +                     "(kernel size %zd, RAM size %" PRId64 ")",
                       info->kernel_filename, kernel_size, info->ram_size);
          exit(1);
      }
 diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/generic-loader.c
 +++ b/hw/core/generic-loader.c
@@ -XXX,XX +XXX,XX @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
      GenericLoaderState *s = GENERIC_LOADER(dev);
      hwaddr entry;
      int big_endian;
 -    int size = 0;
 +    ssize_t size = 0;
      s->set_pc = false;
 diff --git a/hw/core/loader.c b/hw/core/loader.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/loader.c
 +++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t read_targphys(const char *name,
      return did;
  }
 -int load_image_targphys(const char *filename,
 -                        hwaddr addr, uint64_t max_sz)
 +ssize_t load_image_targphys(const char *filename,
 +                            hwaddr addr, uint64_t max_sz)
  {
      return load_image_targphys_as(filename, addr, max_sz, NULL);
  }
  /* return the size or -1 if error */
 -int load_image_targphys_as(const char *filename,
 -                           hwaddr addr, uint64_t max_sz, AddressSpace *as)
 +ssize_t load_image_targphys_as(const char *filename,
 +                               hwaddr addr, uint64_t max_sz, AddressSpace *as)
  {
 -    int size;
 +    ssize_t size;
      size = get_image_size(filename);
      if (size < 0 || size > max_sz) {
@@ -XXX,XX +XXX,XX @@ int load_image_targphys_as(const char *filename,
      return size;
  }
 -int load_image_mr(const char *filename, MemoryRegion *mr)
 +ssize_t load_image_mr(const char *filename, MemoryRegion *mr)
  {
 -    int size;
 +    ssize_t size;
      if (!memory_access_is_direct(mr, false)) {
          /* Can only load an image into RAM or ROM */
@@ -XXX,XX +XXX,XX @@ static void bswap_ahdr(struct exec *e)
       : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
 -int load_aout(const char *filename, hwaddr addr, int max_sz,
 -              int bswap_needed, hwaddr target_page_size)
 +ssize_t load_aout(const char *filename, hwaddr addr, int max_sz,
 +                  int bswap_needed, hwaddr target_page_size)
  {
      int fd;
      ssize_t size, ret;
@@ -XXX,XX +XXX,XX @@ toosmall:
  }
  /* Load a U-Boot image.  */
 -static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
 -                            int *is_linux, uint8_t image_type,
 -                            uint64_t (*translate_fn)(void *, uint64_t),
 -                            void *translate_opaque, AddressSpace *as)
 +static ssize_t load_uboot_image(const char *filename, hwaddr *ep,
 +                                hwaddr *loadaddr, int *is_linux,
 +                                uint8_t image_type,
 +                                uint64_t (*translate_fn)(void *, uint64_t),
 +                                void *translate_opaque, AddressSpace *as)
  {
      int fd;
 -    int size;
 +    ssize_t size;
      hwaddr address;
      uboot_image_header_t h;
      uboot_image_header_t *hdr = &h;
@@ -XXX,XX +XXX,XX @@ out:
      return ret;
  }
+-int load_uimage(const char *filename, hwaddr *ep, hwaddr *loadaddr,
+-                int *is_linux,
+-                uint64_t (*translate_fn)(void *, uint64_t),
+-                void *translate_opaque)
++ssize_t load_uimage(const char *filename, hwaddr *ep, hwaddr *loadaddr,
++                    int *is_linux,
++                    uint64_t (*translate_fn)(void *, uint64_t),
++                    void *translate_opaque)
+ {
+     return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL,
+                             translate_fn, translate_opaque, NULL);
+ }
+-int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr,
+-                   int *is_linux,
+-                   uint64_t (*translate_fn)(void *, uint64_t),
+-                   void *translate_opaque, AddressSpace *as)
++ssize_t load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr,
++                       int *is_linux,
++                       uint64_t (*translate_fn)(void *, uint64_t),
++                       void *translate_opaque, AddressSpace *as)
+ {
+     return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL,
+                             translate_fn, translate_opaque, as);
+ }
+ /* Load a ramdisk.  */
+-int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz)
++ssize_t load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz)
+ {
+     return load_ramdisk_as(filename, addr, max_sz, NULL);
+ }
+-int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
+-                    AddressSpace *as)
++ssize_t load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
++                        AddressSpace *as)
+ {
+     return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK,
+                             NULL, NULL, as);
+ }
+ /* Load a gzip-compressed kernel to a dynamically allocated buffer. */
+-int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
+-                              uint8_t **buffer)
++ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
++                                  uint8_t **buffer)
+ {
+     uint8_t *compressed_data = NULL;
+     uint8_t *data = NULL;
+@@ -XXX,XX +XXX,XX @@ int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
+ }
+ /* Load a gzip-compressed kernel. */
+-int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
++ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
+ {
+-    int bytes;
++    ssize_t bytes;
+     uint8_t *data;
+     bytes = load_image_gzipped_buffer(filename, max_sz, &data);
+@@ -XXX,XX +XXX,XX @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro)
+     return data;
+ }
+-int rom_add_file(const char *file, const char *fw_dir,
+-                 hwaddr addr, int32_t bootindex,
+-                 bool option_rom, MemoryRegion *mr,
+-                 AddressSpace *as)
++ssize_t rom_add_file(const char *file, const char *fw_dir,
++                     hwaddr addr, int32_t bootindex,
++                     bool option_rom, MemoryRegion *mr,
++                     AddressSpace *as)
+ {
+     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
+     Rom *rom;
+-    int rc, fd = -1;
++    ssize_t rc;
++    int fd = -1;
+     char devpath[100];
+     if (as && mr) {
+@@ -XXX,XX +XXX,XX @@ int rom_add_file(const char *file, const char *fw_dir,
+     lseek(fd, 0, SEEK_SET);
+     rc = read(fd, rom->data, rom->datasize);
+     if (rc != rom->datasize) {
+-        fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n",
++        fprintf(stderr, "rom: file %-20s: read error: rc=%zd (expected %zd)\n",
+                 rom->name, rc, rom->datasize);
+         goto err;
+     }
+@@ -XXX,XX +XXX,XX @@ int rom_add_elf_program(const char *name, GMappedFile *mapped_file, void *data,
+     return 0;
+ }
+-int rom_add_vga(const char *file)
++ssize_t rom_add_vga(const char *file)
+ {
+     return rom_add_file(file, "vgaroms", 0, -1, true, NULL, NULL);
+ }
+-int rom_add_option(const char *file, int32_t bootindex)
++ssize_t rom_add_option(const char *file, int32_t bootindex)
+ {
+     return rom_add_file(file, "genroms", 0, bootindex, true, NULL, NULL);
+ }
+@@ -XXX,XX +XXX,XX @@ out:
+ }
+ /* return size or -1 if error */
+-int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as)
++ssize_t load_targphys_hex_as(const char *filename, hwaddr *entry,
++                             AddressSpace *as)
+ {
+     gsize hex_blob_size;
+     gchar *hex_blob;
+-    int total_size = 0;
++    ssize_t total_size = 0;
+     if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) {
+         return -1;
+diff --git a/hw/i386/x86.c b/hw/i386/x86.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/i386/x86.c
++++ b/hw/i386/x86.c
+@@ -XXX,XX +XXX,XX @@ void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
+     char *filename;
+     MemoryRegion *bios, *isa_bios;
+     int bios_size, isa_bios_size;
+-    int ret;
++    ssize_t ret;
+     /* BIOS load */
+     bios_name = ms->firmware ?: default_firmware;
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/boot.c
++++ b/hw/riscv/boot.c
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
+                                  hwaddr firmware_load_addr,
+                                  symbol_fn_t sym_cb)
+ {
+-    uint64_t firmware_entry, firmware_size, firmware_end;
++    uint64_t firmware_entry, firmware_end;
++    ssize_t firmware_size;
+     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
+                          &firmware_entry, NULL, &firmware_end, NULL,
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
+ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
+                          uint64_t kernel_entry, hwaddr *start)
+ {
+-    int size;
++    ssize_t size;
+     /*
+      * We want to put the initrd far enough into RAM that when the
 --
-.30.1
+.36.1

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 06/25] target/riscv: Wake on VS-level external interrupts
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Andrew Bresticker <abrestic@rivosinc.com>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Whether or not VSEIP is pending isn't reflected in env->mip and must
-short of its purpose, as all it checks is whether two-stage address
+instead be determined from hstatus.vgein and hgeip. As a result a
-translation either via the hypervisor-load store instructions or the
+CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
-MPRV feature would be allowed.
+specified in the privileged ISA. Just use riscv_cpu_all_pending()
 instead, which already accounts for VSEIP.
-What we really need instead is whether two-stage address translation was
+Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
 active when the exception was raised. However, in riscv_cpu_do_interrupt
 we do not have the information to reliably detect this. Therefore, when
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/cpu.h        | 1 +
- target/riscv/cpu.c        |  1 +
+ target/riscv/cpu.c        | 2 +-
- target/riscv/cpu_helper.c | 21 ++++++++-------------
+ target/riscv/cpu_helper.c | 2 +-
-files changed, 13 insertions(+), 13 deletions(-)
+files changed, 3 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-     target_ulong satp_hs;
+ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-     uint64_t mstatus_hs;
+ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
+ uint8_t riscv_cpu_default_priority(int irq);
-+    /* Signals whether the current exception occurred with two-stage address
++uint64_t riscv_cpu_all_pending(CPURISCVState *env);
-+       translation active. */
+ int riscv_cpu_mirq_pending(CPURISCVState *env);
-+    bool two_stage_lookup;
+ int riscv_cpu_sirq_pending(CPURISCVState *env);
-+
+ int riscv_cpu_vsirq_pending(CPURISCVState *env);
      target_ulong scounteren;
      target_ulong mcounteren;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+      * Definition of the WFI instruction requires it to ignore the privilege
-     env->mcause = 0;
+      * mode and delegation registers, but respect individual enables
-     env->pc = env->resetvec;
+      */
-+    env->two_stage_lookup = false;
+-    return (env->mip & env->mie) != 0;
 +    return riscv_cpu_all_pending(env) != 0;
  #else
      return true;
  #endif
-     cs->exception_index = EXCP_NONE;
-     env->load_res = -1;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
-         g_assert_not_reached();
+     return best_irq;
      }
      env->badaddr = address;
 +    env->two_stage_lookup = two_stage;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+-static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
++uint64_t riscv_cpu_all_pending(CPURISCVState *env)
-     }
+ {
+     uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
-     env->badaddr = addr;
+     uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
 +    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
 +                            riscv_cpu_two_stage_lookup(mmu_idx);
      riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
  }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
          g_assert_not_reached();
      }
      env->badaddr = addr;
 +    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
 +                            riscv_cpu_two_stage_lookup(mmu_idx);
      riscv_raise_exception(env, cs->exception_index, retaddr);
  }
  #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          /* handle the trap in S-mode */
          if (riscv_has_ext(env, RVH)) {
              target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 -            bool two_stage_lookup = false;
 -            if (env->priv == PRV_M ||
 -                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                    get_field(env->hstatus, HSTATUS_HU))) {
 -                    two_stage_lookup = true;
 -            }
 -
 -            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
 +            if (env->two_stage_lookup && write_tval) {
                  /*
                   * If we are writing a guest virtual address to stval, set
                   * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  riscv_cpu_set_force_hs_excep(env, 0);
              } else {
                  /* Trap into HS mode */
 -                if (!two_stage_lookup) {
 -                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 -                                             riscv_cpu_virt_enabled(env));
 -                }
 +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                  htval = env->guest_phys_fault_addr;
              }
          }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
       * RISC-V ISA Specification.
       */
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.36.1

-New patch
+[PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working
+From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+Add an MXL_RV128 case in two switches so that no error is triggered when
+using the -cpu x-rv128 option.
+Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/debug.c | 2 ++
+file changed, 2 insertions(+)
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/debug.c
++++ b/target/riscv/debug.c
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong trigger_type(CPURISCVState *env,
+         tdata1 = RV32_TYPE(type);
+         break;
+     case MXL_RV64:
++    case MXL_RV128:
+         tdata1 = RV64_TYPE(type);
+         break;
+     default:
+@@ -XXX,XX +XXX,XX @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
+         tdata1 = RV32_TYPE(t);
+         break;
+     case MXL_RV64:
++    case MXL_RV128:
+         type = extract64(val, 60, 4);
+         dmode = extract64(val, 59, 1);
+         tdata1 = RV64_TYPE(t);
+--
+.36.1

-New patch
+[PULL 08/25] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
+From: eopXD <yueh.ting.chen@gmail.com>
+No functional change intended in this commit.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-1@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 1132 +++++++++++++++++-----------------
+file changed, 565 insertions(+), 567 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
+ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
+                        CPURISCVState *env, uint32_t desc,
+-                       uint32_t esz, uint32_t dsz,
+                        opivv2_fn *fn)
+ {
+     uint32_t vm = vext_vm(desc);
+@@ -XXX,XX +XXX,XX @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
+ }
+ /* generate the helpers for OPIVV */
+-#define GEN_VEXT_VV(NAME, ESZ, DSZ)                       \
++#define GEN_VEXT_VV(NAME)                                 \
+ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
+                   void *vs2, CPURISCVState *env,          \
+                   uint32_t desc)                          \
+ {                                                         \
+-    do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ,     \
++    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
+                do_##NAME);                                \
+ }
+-GEN_VEXT_VV(vadd_vv_b, 1, 1)
+-GEN_VEXT_VV(vadd_vv_h, 2, 2)
+-GEN_VEXT_VV(vadd_vv_w, 4, 4)
+-GEN_VEXT_VV(vadd_vv_d, 8, 8)
+-GEN_VEXT_VV(vsub_vv_b, 1, 1)
+-GEN_VEXT_VV(vsub_vv_h, 2, 2)
+-GEN_VEXT_VV(vsub_vv_w, 4, 4)
+-GEN_VEXT_VV(vsub_vv_d, 8, 8)
++GEN_VEXT_VV(vadd_vv_b)
++GEN_VEXT_VV(vadd_vv_h)
++GEN_VEXT_VV(vadd_vv_w)
++GEN_VEXT_VV(vadd_vv_d)
++GEN_VEXT_VV(vsub_vv_b)
++GEN_VEXT_VV(vsub_vv_h)
++GEN_VEXT_VV(vsub_vv_w)
++GEN_VEXT_VV(vsub_vv_d)
+ typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
+ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
+                        CPURISCVState *env, uint32_t desc,
+-                       uint32_t esz, uint32_t dsz,
+                        opivx2_fn fn)
+ {
+     uint32_t vm = vext_vm(desc);
+@@ -XXX,XX +XXX,XX @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
+ }
+ /* generate the helpers for OPIVX */
+-#define GEN_VEXT_VX(NAME, ESZ, DSZ)                       \
++#define GEN_VEXT_VX(NAME)                                 \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
+                   void *vs2, CPURISCVState *env,          \
+                   uint32_t desc)                          \
+ {                                                         \
+-    do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ,      \
++    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
+                do_##NAME);                                \
+ }
+-GEN_VEXT_VX(vadd_vx_b, 1, 1)
+-GEN_VEXT_VX(vadd_vx_h, 2, 2)
+-GEN_VEXT_VX(vadd_vx_w, 4, 4)
+-GEN_VEXT_VX(vadd_vx_d, 8, 8)
+-GEN_VEXT_VX(vsub_vx_b, 1, 1)
+-GEN_VEXT_VX(vsub_vx_h, 2, 2)
+-GEN_VEXT_VX(vsub_vx_w, 4, 4)
+-GEN_VEXT_VX(vsub_vx_d, 8, 8)
+-GEN_VEXT_VX(vrsub_vx_b, 1, 1)
+-GEN_VEXT_VX(vrsub_vx_h, 2, 2)
+-GEN_VEXT_VX(vrsub_vx_w, 4, 4)
+-GEN_VEXT_VX(vrsub_vx_d, 8, 8)
++GEN_VEXT_VX(vadd_vx_b)
++GEN_VEXT_VX(vadd_vx_h)
++GEN_VEXT_VX(vadd_vx_w)
++GEN_VEXT_VX(vadd_vx_d)
++GEN_VEXT_VX(vsub_vx_b)
++GEN_VEXT_VX(vsub_vx_h)
++GEN_VEXT_VX(vsub_vx_w)
++GEN_VEXT_VX(vsub_vx_d)
++GEN_VEXT_VX(vrsub_vx_b)
++GEN_VEXT_VX(vrsub_vx_h)
++GEN_VEXT_VX(vrsub_vx_w)
++GEN_VEXT_VX(vrsub_vx_d)
+ void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
+ RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
+ RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
+ RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
+-GEN_VEXT_VV(vwaddu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwaddu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwaddu_vv_w, 4, 8)
+-GEN_VEXT_VV(vwsubu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwsubu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwsubu_vv_w, 4, 8)
+-GEN_VEXT_VV(vwadd_vv_b, 1, 2)
+-GEN_VEXT_VV(vwadd_vv_h, 2, 4)
+-GEN_VEXT_VV(vwadd_vv_w, 4, 8)
+-GEN_VEXT_VV(vwsub_vv_b, 1, 2)
+-GEN_VEXT_VV(vwsub_vv_h, 2, 4)
+-GEN_VEXT_VV(vwsub_vv_w, 4, 8)
+-GEN_VEXT_VV(vwaddu_wv_b, 1, 2)
+-GEN_VEXT_VV(vwaddu_wv_h, 2, 4)
+-GEN_VEXT_VV(vwaddu_wv_w, 4, 8)
+-GEN_VEXT_VV(vwsubu_wv_b, 1, 2)
+-GEN_VEXT_VV(vwsubu_wv_h, 2, 4)
+-GEN_VEXT_VV(vwsubu_wv_w, 4, 8)
+-GEN_VEXT_VV(vwadd_wv_b, 1, 2)
+-GEN_VEXT_VV(vwadd_wv_h, 2, 4)
+-GEN_VEXT_VV(vwadd_wv_w, 4, 8)
+-GEN_VEXT_VV(vwsub_wv_b, 1, 2)
+-GEN_VEXT_VV(vwsub_wv_h, 2, 4)
+-GEN_VEXT_VV(vwsub_wv_w, 4, 8)
++GEN_VEXT_VV(vwaddu_vv_b)
++GEN_VEXT_VV(vwaddu_vv_h)
++GEN_VEXT_VV(vwaddu_vv_w)
++GEN_VEXT_VV(vwsubu_vv_b)
++GEN_VEXT_VV(vwsubu_vv_h)
++GEN_VEXT_VV(vwsubu_vv_w)
++GEN_VEXT_VV(vwadd_vv_b)
++GEN_VEXT_VV(vwadd_vv_h)
++GEN_VEXT_VV(vwadd_vv_w)
++GEN_VEXT_VV(vwsub_vv_b)
++GEN_VEXT_VV(vwsub_vv_h)
++GEN_VEXT_VV(vwsub_vv_w)
++GEN_VEXT_VV(vwaddu_wv_b)
++GEN_VEXT_VV(vwaddu_wv_h)
++GEN_VEXT_VV(vwaddu_wv_w)
++GEN_VEXT_VV(vwsubu_wv_b)
++GEN_VEXT_VV(vwsubu_wv_h)
++GEN_VEXT_VV(vwsubu_wv_w)
++GEN_VEXT_VV(vwadd_wv_b)
++GEN_VEXT_VV(vwadd_wv_h)
++GEN_VEXT_VV(vwadd_wv_w)
++GEN_VEXT_VV(vwsub_wv_b)
++GEN_VEXT_VV(vwsub_wv_h)
++GEN_VEXT_VV(vwsub_wv_w)
+ RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
+ RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
+ RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
+ RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
+ RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
+-GEN_VEXT_VX(vwaddu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwaddu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwaddu_vx_w, 4, 8)
+-GEN_VEXT_VX(vwsubu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwsubu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwsubu_vx_w, 4, 8)
+-GEN_VEXT_VX(vwadd_vx_b, 1, 2)
+-GEN_VEXT_VX(vwadd_vx_h, 2, 4)
+-GEN_VEXT_VX(vwadd_vx_w, 4, 8)
+-GEN_VEXT_VX(vwsub_vx_b, 1, 2)
+-GEN_VEXT_VX(vwsub_vx_h, 2, 4)
+-GEN_VEXT_VX(vwsub_vx_w, 4, 8)
+-GEN_VEXT_VX(vwaddu_wx_b, 1, 2)
+-GEN_VEXT_VX(vwaddu_wx_h, 2, 4)
+-GEN_VEXT_VX(vwaddu_wx_w, 4, 8)
+-GEN_VEXT_VX(vwsubu_wx_b, 1, 2)
+-GEN_VEXT_VX(vwsubu_wx_h, 2, 4)
+-GEN_VEXT_VX(vwsubu_wx_w, 4, 8)
+-GEN_VEXT_VX(vwadd_wx_b, 1, 2)
+-GEN_VEXT_VX(vwadd_wx_h, 2, 4)
+-GEN_VEXT_VX(vwadd_wx_w, 4, 8)
+-GEN_VEXT_VX(vwsub_wx_b, 1, 2)
+-GEN_VEXT_VX(vwsub_wx_h, 2, 4)
+-GEN_VEXT_VX(vwsub_wx_w, 4, 8)
++GEN_VEXT_VX(vwaddu_vx_b)
++GEN_VEXT_VX(vwaddu_vx_h)
++GEN_VEXT_VX(vwaddu_vx_w)
++GEN_VEXT_VX(vwsubu_vx_b)
++GEN_VEXT_VX(vwsubu_vx_h)
++GEN_VEXT_VX(vwsubu_vx_w)
++GEN_VEXT_VX(vwadd_vx_b)
++GEN_VEXT_VX(vwadd_vx_h)
++GEN_VEXT_VX(vwadd_vx_w)
++GEN_VEXT_VX(vwsub_vx_b)
++GEN_VEXT_VX(vwsub_vx_h)
++GEN_VEXT_VX(vwsub_vx_w)
++GEN_VEXT_VX(vwaddu_wx_b)
++GEN_VEXT_VX(vwaddu_wx_h)
++GEN_VEXT_VX(vwaddu_wx_w)
++GEN_VEXT_VX(vwsubu_wx_b)
++GEN_VEXT_VX(vwsubu_wx_h)
++GEN_VEXT_VX(vwsubu_wx_w)
++GEN_VEXT_VX(vwadd_wx_b)
++GEN_VEXT_VX(vwadd_wx_h)
++GEN_VEXT_VX(vwadd_wx_w)
++GEN_VEXT_VX(vwsub_wx_b)
++GEN_VEXT_VX(vwsub_wx_h)
++GEN_VEXT_VX(vwsub_wx_w)
+ /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
+ #define DO_VADC(N, M, C) (N + M + C)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
+ RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
+ RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
+ RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
+-GEN_VEXT_VV(vand_vv_b, 1, 1)
+-GEN_VEXT_VV(vand_vv_h, 2, 2)
+-GEN_VEXT_VV(vand_vv_w, 4, 4)
+-GEN_VEXT_VV(vand_vv_d, 8, 8)
+-GEN_VEXT_VV(vor_vv_b, 1, 1)
+-GEN_VEXT_VV(vor_vv_h, 2, 2)
+-GEN_VEXT_VV(vor_vv_w, 4, 4)
+-GEN_VEXT_VV(vor_vv_d, 8, 8)
+-GEN_VEXT_VV(vxor_vv_b, 1, 1)
+-GEN_VEXT_VV(vxor_vv_h, 2, 2)
+-GEN_VEXT_VV(vxor_vv_w, 4, 4)
+-GEN_VEXT_VV(vxor_vv_d, 8, 8)
++GEN_VEXT_VV(vand_vv_b)
++GEN_VEXT_VV(vand_vv_h)
++GEN_VEXT_VV(vand_vv_w)
++GEN_VEXT_VV(vand_vv_d)
++GEN_VEXT_VV(vor_vv_b)
++GEN_VEXT_VV(vor_vv_h)
++GEN_VEXT_VV(vor_vv_w)
++GEN_VEXT_VV(vor_vv_d)
++GEN_VEXT_VV(vxor_vv_b)
++GEN_VEXT_VV(vxor_vv_h)
++GEN_VEXT_VV(vxor_vv_w)
++GEN_VEXT_VV(vxor_vv_d)
+ RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
+ RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
+ RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
+ RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
+ RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
+-GEN_VEXT_VX(vand_vx_b, 1, 1)
+-GEN_VEXT_VX(vand_vx_h, 2, 2)
+-GEN_VEXT_VX(vand_vx_w, 4, 4)
+-GEN_VEXT_VX(vand_vx_d, 8, 8)
+-GEN_VEXT_VX(vor_vx_b, 1, 1)
+-GEN_VEXT_VX(vor_vx_h, 2, 2)
+-GEN_VEXT_VX(vor_vx_w, 4, 4)
+-GEN_VEXT_VX(vor_vx_d, 8, 8)
+-GEN_VEXT_VX(vxor_vx_b, 1, 1)
+-GEN_VEXT_VX(vxor_vx_h, 2, 2)
+-GEN_VEXT_VX(vxor_vx_w, 4, 4)
+-GEN_VEXT_VX(vxor_vx_d, 8, 8)
++GEN_VEXT_VX(vand_vx_b)
++GEN_VEXT_VX(vand_vx_h)
++GEN_VEXT_VX(vand_vx_w)
++GEN_VEXT_VX(vand_vx_d)
++GEN_VEXT_VX(vor_vx_b)
++GEN_VEXT_VX(vor_vx_h)
++GEN_VEXT_VX(vor_vx_w)
++GEN_VEXT_VX(vor_vx_d)
++GEN_VEXT_VX(vxor_vx_b)
++GEN_VEXT_VX(vxor_vx_h)
++GEN_VEXT_VX(vxor_vx_w)
++GEN_VEXT_VX(vxor_vx_d)
+ /* Vector Single-Width Bit Shift Instructions */
+ #define DO_SLL(N, M)  (N << (M))
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
+ RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
+ RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
+ RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
+-GEN_VEXT_VV(vminu_vv_b, 1, 1)
+-GEN_VEXT_VV(vminu_vv_h, 2, 2)
+-GEN_VEXT_VV(vminu_vv_w, 4, 4)
+-GEN_VEXT_VV(vminu_vv_d, 8, 8)
+-GEN_VEXT_VV(vmin_vv_b, 1, 1)
+-GEN_VEXT_VV(vmin_vv_h, 2, 2)
+-GEN_VEXT_VV(vmin_vv_w, 4, 4)
+-GEN_VEXT_VV(vmin_vv_d, 8, 8)
+-GEN_VEXT_VV(vmaxu_vv_b, 1, 1)
+-GEN_VEXT_VV(vmaxu_vv_h, 2, 2)
+-GEN_VEXT_VV(vmaxu_vv_w, 4, 4)
+-GEN_VEXT_VV(vmaxu_vv_d, 8, 8)
+-GEN_VEXT_VV(vmax_vv_b, 1, 1)
+-GEN_VEXT_VV(vmax_vv_h, 2, 2)
+-GEN_VEXT_VV(vmax_vv_w, 4, 4)
+-GEN_VEXT_VV(vmax_vv_d, 8, 8)
++GEN_VEXT_VV(vminu_vv_b)
++GEN_VEXT_VV(vminu_vv_h)
++GEN_VEXT_VV(vminu_vv_w)
++GEN_VEXT_VV(vminu_vv_d)
++GEN_VEXT_VV(vmin_vv_b)
++GEN_VEXT_VV(vmin_vv_h)
++GEN_VEXT_VV(vmin_vv_w)
++GEN_VEXT_VV(vmin_vv_d)
++GEN_VEXT_VV(vmaxu_vv_b)
++GEN_VEXT_VV(vmaxu_vv_h)
++GEN_VEXT_VV(vmaxu_vv_w)
++GEN_VEXT_VV(vmaxu_vv_d)
++GEN_VEXT_VV(vmax_vv_b)
++GEN_VEXT_VV(vmax_vv_h)
++GEN_VEXT_VV(vmax_vv_w)
++GEN_VEXT_VV(vmax_vv_d)
+ RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
+ RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
+ RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
+ RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
+ RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
+-GEN_VEXT_VX(vminu_vx_b, 1, 1)
+-GEN_VEXT_VX(vminu_vx_h, 2, 2)
+-GEN_VEXT_VX(vminu_vx_w, 4, 4)
+-GEN_VEXT_VX(vminu_vx_d, 8, 8)
+-GEN_VEXT_VX(vmin_vx_b, 1, 1)
+-GEN_VEXT_VX(vmin_vx_h, 2, 2)
+-GEN_VEXT_VX(vmin_vx_w, 4, 4)
+-GEN_VEXT_VX(vmin_vx_d, 8, 8)
+-GEN_VEXT_VX(vmaxu_vx_b, 1, 1)
+-GEN_VEXT_VX(vmaxu_vx_h, 2, 2)
+-GEN_VEXT_VX(vmaxu_vx_w, 4, 4)
+-GEN_VEXT_VX(vmaxu_vx_d, 8, 8)
+-GEN_VEXT_VX(vmax_vx_b, 1, 1)
+-GEN_VEXT_VX(vmax_vx_h, 2, 2)
+-GEN_VEXT_VX(vmax_vx_w, 4, 4)
+-GEN_VEXT_VX(vmax_vx_d, 8, 8)
++GEN_VEXT_VX(vminu_vx_b)
++GEN_VEXT_VX(vminu_vx_h)
++GEN_VEXT_VX(vminu_vx_w)
++GEN_VEXT_VX(vminu_vx_d)
++GEN_VEXT_VX(vmin_vx_b)
++GEN_VEXT_VX(vmin_vx_h)
++GEN_VEXT_VX(vmin_vx_w)
++GEN_VEXT_VX(vmin_vx_d)
++GEN_VEXT_VX(vmaxu_vx_b)
++GEN_VEXT_VX(vmaxu_vx_h)
++GEN_VEXT_VX(vmaxu_vx_w)
++GEN_VEXT_VX(vmaxu_vx_d)
++GEN_VEXT_VX(vmax_vx_b)
++GEN_VEXT_VX(vmax_vx_h)
++GEN_VEXT_VX(vmax_vx_w)
++GEN_VEXT_VX(vmax_vx_d)
+ /* Vector Single-Width Integer Multiply Instructions */
+ #define DO_MUL(N, M) (N * M)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
+ RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
+ RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
+ RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
+-GEN_VEXT_VV(vmul_vv_b, 1, 1)
+-GEN_VEXT_VV(vmul_vv_h, 2, 2)
+-GEN_VEXT_VV(vmul_vv_w, 4, 4)
+-GEN_VEXT_VV(vmul_vv_d, 8, 8)
++GEN_VEXT_VV(vmul_vv_b)
++GEN_VEXT_VV(vmul_vv_h)
++GEN_VEXT_VV(vmul_vv_w)
++GEN_VEXT_VV(vmul_vv_d)
+ static int8_t do_mulh_b(int8_t s2, int8_t s1)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
+ RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
+ RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
+ RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
+-GEN_VEXT_VV(vmulh_vv_b, 1, 1)
+-GEN_VEXT_VV(vmulh_vv_h, 2, 2)
+-GEN_VEXT_VV(vmulh_vv_w, 4, 4)
+-GEN_VEXT_VV(vmulh_vv_d, 8, 8)
+-GEN_VEXT_VV(vmulhu_vv_b, 1, 1)
+-GEN_VEXT_VV(vmulhu_vv_h, 2, 2)
+-GEN_VEXT_VV(vmulhu_vv_w, 4, 4)
+-GEN_VEXT_VV(vmulhu_vv_d, 8, 8)
+-GEN_VEXT_VV(vmulhsu_vv_b, 1, 1)
+-GEN_VEXT_VV(vmulhsu_vv_h, 2, 2)
+-GEN_VEXT_VV(vmulhsu_vv_w, 4, 4)
+-GEN_VEXT_VV(vmulhsu_vv_d, 8, 8)
++GEN_VEXT_VV(vmulh_vv_b)
++GEN_VEXT_VV(vmulh_vv_h)
++GEN_VEXT_VV(vmulh_vv_w)
++GEN_VEXT_VV(vmulh_vv_d)
++GEN_VEXT_VV(vmulhu_vv_b)
++GEN_VEXT_VV(vmulhu_vv_h)
++GEN_VEXT_VV(vmulhu_vv_w)
++GEN_VEXT_VV(vmulhu_vv_d)
++GEN_VEXT_VV(vmulhsu_vv_b)
++GEN_VEXT_VV(vmulhsu_vv_h)
++GEN_VEXT_VV(vmulhsu_vv_w)
++GEN_VEXT_VV(vmulhsu_vv_d)
+ RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
+ RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
+ RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
+ RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
+ RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
+-GEN_VEXT_VX(vmul_vx_b, 1, 1)
+-GEN_VEXT_VX(vmul_vx_h, 2, 2)
+-GEN_VEXT_VX(vmul_vx_w, 4, 4)
+-GEN_VEXT_VX(vmul_vx_d, 8, 8)
+-GEN_VEXT_VX(vmulh_vx_b, 1, 1)
+-GEN_VEXT_VX(vmulh_vx_h, 2, 2)
+-GEN_VEXT_VX(vmulh_vx_w, 4, 4)
+-GEN_VEXT_VX(vmulh_vx_d, 8, 8)
+-GEN_VEXT_VX(vmulhu_vx_b, 1, 1)
+-GEN_VEXT_VX(vmulhu_vx_h, 2, 2)
+-GEN_VEXT_VX(vmulhu_vx_w, 4, 4)
+-GEN_VEXT_VX(vmulhu_vx_d, 8, 8)
+-GEN_VEXT_VX(vmulhsu_vx_b, 1, 1)
+-GEN_VEXT_VX(vmulhsu_vx_h, 2, 2)
+-GEN_VEXT_VX(vmulhsu_vx_w, 4, 4)
+-GEN_VEXT_VX(vmulhsu_vx_d, 8, 8)
++GEN_VEXT_VX(vmul_vx_b)
++GEN_VEXT_VX(vmul_vx_h)
++GEN_VEXT_VX(vmul_vx_w)
++GEN_VEXT_VX(vmul_vx_d)
++GEN_VEXT_VX(vmulh_vx_b)
++GEN_VEXT_VX(vmulh_vx_h)
++GEN_VEXT_VX(vmulh_vx_w)
++GEN_VEXT_VX(vmulh_vx_d)
++GEN_VEXT_VX(vmulhu_vx_b)
++GEN_VEXT_VX(vmulhu_vx_h)
++GEN_VEXT_VX(vmulhu_vx_w)
++GEN_VEXT_VX(vmulhu_vx_d)
++GEN_VEXT_VX(vmulhsu_vx_b)
++GEN_VEXT_VX(vmulhsu_vx_h)
++GEN_VEXT_VX(vmulhsu_vx_w)
++GEN_VEXT_VX(vmulhsu_vx_d)
+ /* Vector Integer Divide Instructions */
+ #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
+ RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
+ RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
+ RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
+-GEN_VEXT_VV(vdivu_vv_b, 1, 1)
+-GEN_VEXT_VV(vdivu_vv_h, 2, 2)
+-GEN_VEXT_VV(vdivu_vv_w, 4, 4)
+-GEN_VEXT_VV(vdivu_vv_d, 8, 8)
+-GEN_VEXT_VV(vdiv_vv_b, 1, 1)
+-GEN_VEXT_VV(vdiv_vv_h, 2, 2)
+-GEN_VEXT_VV(vdiv_vv_w, 4, 4)
+-GEN_VEXT_VV(vdiv_vv_d, 8, 8)
+-GEN_VEXT_VV(vremu_vv_b, 1, 1)
+-GEN_VEXT_VV(vremu_vv_h, 2, 2)
+-GEN_VEXT_VV(vremu_vv_w, 4, 4)
+-GEN_VEXT_VV(vremu_vv_d, 8, 8)
+-GEN_VEXT_VV(vrem_vv_b, 1, 1)
+-GEN_VEXT_VV(vrem_vv_h, 2, 2)
+-GEN_VEXT_VV(vrem_vv_w, 4, 4)
+-GEN_VEXT_VV(vrem_vv_d, 8, 8)
++GEN_VEXT_VV(vdivu_vv_b)
++GEN_VEXT_VV(vdivu_vv_h)
++GEN_VEXT_VV(vdivu_vv_w)
++GEN_VEXT_VV(vdivu_vv_d)
++GEN_VEXT_VV(vdiv_vv_b)
++GEN_VEXT_VV(vdiv_vv_h)
++GEN_VEXT_VV(vdiv_vv_w)
++GEN_VEXT_VV(vdiv_vv_d)
++GEN_VEXT_VV(vremu_vv_b)
++GEN_VEXT_VV(vremu_vv_h)
++GEN_VEXT_VV(vremu_vv_w)
++GEN_VEXT_VV(vremu_vv_d)
++GEN_VEXT_VV(vrem_vv_b)
++GEN_VEXT_VV(vrem_vv_h)
++GEN_VEXT_VV(vrem_vv_w)
++GEN_VEXT_VV(vrem_vv_d)
+ RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
+ RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
+ RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
+ RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
+ RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
+-GEN_VEXT_VX(vdivu_vx_b, 1, 1)
+-GEN_VEXT_VX(vdivu_vx_h, 2, 2)
+-GEN_VEXT_VX(vdivu_vx_w, 4, 4)
+-GEN_VEXT_VX(vdivu_vx_d, 8, 8)
+-GEN_VEXT_VX(vdiv_vx_b, 1, 1)
+-GEN_VEXT_VX(vdiv_vx_h, 2, 2)
+-GEN_VEXT_VX(vdiv_vx_w, 4, 4)
+-GEN_VEXT_VX(vdiv_vx_d, 8, 8)
+-GEN_VEXT_VX(vremu_vx_b, 1, 1)
+-GEN_VEXT_VX(vremu_vx_h, 2, 2)
+-GEN_VEXT_VX(vremu_vx_w, 4, 4)
+-GEN_VEXT_VX(vremu_vx_d, 8, 8)
+-GEN_VEXT_VX(vrem_vx_b, 1, 1)
+-GEN_VEXT_VX(vrem_vx_h, 2, 2)
+-GEN_VEXT_VX(vrem_vx_w, 4, 4)
+-GEN_VEXT_VX(vrem_vx_d, 8, 8)
++GEN_VEXT_VX(vdivu_vx_b)
++GEN_VEXT_VX(vdivu_vx_h)
++GEN_VEXT_VX(vdivu_vx_w)
++GEN_VEXT_VX(vdivu_vx_d)
++GEN_VEXT_VX(vdiv_vx_b)
++GEN_VEXT_VX(vdiv_vx_h)
++GEN_VEXT_VX(vdiv_vx_w)
++GEN_VEXT_VX(vdiv_vx_d)
++GEN_VEXT_VX(vremu_vx_b)
++GEN_VEXT_VX(vremu_vx_h)
++GEN_VEXT_VX(vremu_vx_w)
++GEN_VEXT_VX(vremu_vx_d)
++GEN_VEXT_VX(vrem_vx_b)
++GEN_VEXT_VX(vrem_vx_h)
++GEN_VEXT_VX(vrem_vx_w)
++GEN_VEXT_VX(vrem_vx_d)
+ /* Vector Widening Integer Multiply Instructions */
+ RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
+ RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
+ RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
+ RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
+-GEN_VEXT_VV(vwmul_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmul_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmul_vv_w, 4, 8)
+-GEN_VEXT_VV(vwmulu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmulu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmulu_vv_w, 4, 8)
+-GEN_VEXT_VV(vwmulsu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmulsu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmulsu_vv_w, 4, 8)
++GEN_VEXT_VV(vwmul_vv_b)
++GEN_VEXT_VV(vwmul_vv_h)
++GEN_VEXT_VV(vwmul_vv_w)
++GEN_VEXT_VV(vwmulu_vv_b)
++GEN_VEXT_VV(vwmulu_vv_h)
++GEN_VEXT_VV(vwmulu_vv_w)
++GEN_VEXT_VV(vwmulsu_vv_b)
++GEN_VEXT_VV(vwmulsu_vv_h)
++GEN_VEXT_VV(vwmulsu_vv_w)
+ RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
+ RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
+ RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
+ RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
+ RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
+-GEN_VEXT_VX(vwmul_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmul_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmul_vx_w, 4, 8)
+-GEN_VEXT_VX(vwmulu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmulu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmulu_vx_w, 4, 8)
+-GEN_VEXT_VX(vwmulsu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmulsu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmulsu_vx_w, 4, 8)
++GEN_VEXT_VX(vwmul_vx_b)
++GEN_VEXT_VX(vwmul_vx_h)
++GEN_VEXT_VX(vwmul_vx_w)
++GEN_VEXT_VX(vwmulu_vx_b)
++GEN_VEXT_VX(vwmulu_vx_h)
++GEN_VEXT_VX(vwmulu_vx_w)
++GEN_VEXT_VX(vwmulsu_vx_b)
++GEN_VEXT_VX(vwmulsu_vx_h)
++GEN_VEXT_VX(vwmulsu_vx_w)
+ /* Vector Single-Width Integer Multiply-Add Instructions */
+ #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
+ RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
+ RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
+ RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
+-GEN_VEXT_VV(vmacc_vv_b, 1, 1)
+-GEN_VEXT_VV(vmacc_vv_h, 2, 2)
+-GEN_VEXT_VV(vmacc_vv_w, 4, 4)
+-GEN_VEXT_VV(vmacc_vv_d, 8, 8)
+-GEN_VEXT_VV(vnmsac_vv_b, 1, 1)
+-GEN_VEXT_VV(vnmsac_vv_h, 2, 2)
+-GEN_VEXT_VV(vnmsac_vv_w, 4, 4)
+-GEN_VEXT_VV(vnmsac_vv_d, 8, 8)
+-GEN_VEXT_VV(vmadd_vv_b, 1, 1)
+-GEN_VEXT_VV(vmadd_vv_h, 2, 2)
+-GEN_VEXT_VV(vmadd_vv_w, 4, 4)
+-GEN_VEXT_VV(vmadd_vv_d, 8, 8)
+-GEN_VEXT_VV(vnmsub_vv_b, 1, 1)
+-GEN_VEXT_VV(vnmsub_vv_h, 2, 2)
+-GEN_VEXT_VV(vnmsub_vv_w, 4, 4)
+-GEN_VEXT_VV(vnmsub_vv_d, 8, 8)
++GEN_VEXT_VV(vmacc_vv_b)
++GEN_VEXT_VV(vmacc_vv_h)
++GEN_VEXT_VV(vmacc_vv_w)
++GEN_VEXT_VV(vmacc_vv_d)
++GEN_VEXT_VV(vnmsac_vv_b)
++GEN_VEXT_VV(vnmsac_vv_h)
++GEN_VEXT_VV(vnmsac_vv_w)
++GEN_VEXT_VV(vnmsac_vv_d)
++GEN_VEXT_VV(vmadd_vv_b)
++GEN_VEXT_VV(vmadd_vv_h)
++GEN_VEXT_VV(vmadd_vv_w)
++GEN_VEXT_VV(vmadd_vv_d)
++GEN_VEXT_VV(vnmsub_vv_b)
++GEN_VEXT_VV(vnmsub_vv_h)
++GEN_VEXT_VV(vnmsub_vv_w)
++GEN_VEXT_VV(vnmsub_vv_d)
+ #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
+ static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
+ RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
+ RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
+ RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
+-GEN_VEXT_VX(vmacc_vx_b, 1, 1)
+-GEN_VEXT_VX(vmacc_vx_h, 2, 2)
+-GEN_VEXT_VX(vmacc_vx_w, 4, 4)
+-GEN_VEXT_VX(vmacc_vx_d, 8, 8)
+-GEN_VEXT_VX(vnmsac_vx_b, 1, 1)
+-GEN_VEXT_VX(vnmsac_vx_h, 2, 2)
+-GEN_VEXT_VX(vnmsac_vx_w, 4, 4)
+-GEN_VEXT_VX(vnmsac_vx_d, 8, 8)
+-GEN_VEXT_VX(vmadd_vx_b, 1, 1)
+-GEN_VEXT_VX(vmadd_vx_h, 2, 2)
+-GEN_VEXT_VX(vmadd_vx_w, 4, 4)
+-GEN_VEXT_VX(vmadd_vx_d, 8, 8)
+-GEN_VEXT_VX(vnmsub_vx_b, 1, 1)
+-GEN_VEXT_VX(vnmsub_vx_h, 2, 2)
+-GEN_VEXT_VX(vnmsub_vx_w, 4, 4)
+-GEN_VEXT_VX(vnmsub_vx_d, 8, 8)
++GEN_VEXT_VX(vmacc_vx_b)
++GEN_VEXT_VX(vmacc_vx_h)
++GEN_VEXT_VX(vmacc_vx_w)
++GEN_VEXT_VX(vmacc_vx_d)
++GEN_VEXT_VX(vnmsac_vx_b)
++GEN_VEXT_VX(vnmsac_vx_h)
++GEN_VEXT_VX(vnmsac_vx_w)
++GEN_VEXT_VX(vnmsac_vx_d)
++GEN_VEXT_VX(vmadd_vx_b)
++GEN_VEXT_VX(vmadd_vx_h)
++GEN_VEXT_VX(vmadd_vx_w)
++GEN_VEXT_VX(vmadd_vx_d)
++GEN_VEXT_VX(vnmsub_vx_b)
++GEN_VEXT_VX(vnmsub_vx_h)
++GEN_VEXT_VX(vnmsub_vx_w)
++GEN_VEXT_VX(vnmsub_vx_d)
+ /* Vector Widening Integer Multiply-Add Instructions */
+ RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
+ RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
+ RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
+ RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
+-GEN_VEXT_VV(vwmaccu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmaccu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmaccu_vv_w, 4, 8)
+-GEN_VEXT_VV(vwmacc_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmacc_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmacc_vv_w, 4, 8)
+-GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2)
+-GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4)
+-GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8)
++GEN_VEXT_VV(vwmaccu_vv_b)
++GEN_VEXT_VV(vwmaccu_vv_h)
++GEN_VEXT_VV(vwmaccu_vv_w)
++GEN_VEXT_VV(vwmacc_vv_b)
++GEN_VEXT_VV(vwmacc_vv_h)
++GEN_VEXT_VV(vwmacc_vv_w)
++GEN_VEXT_VV(vwmaccsu_vv_b)
++GEN_VEXT_VV(vwmaccsu_vv_h)
++GEN_VEXT_VV(vwmaccsu_vv_w)
+ RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
+ RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
+ RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
+ RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
+ RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
+-GEN_VEXT_VX(vwmaccu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmaccu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmaccu_vx_w, 4, 8)
+-GEN_VEXT_VX(vwmacc_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmacc_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmacc_vx_w, 4, 8)
+-GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8)
+-GEN_VEXT_VX(vwmaccus_vx_b, 1, 2)
+-GEN_VEXT_VX(vwmaccus_vx_h, 2, 4)
+-GEN_VEXT_VX(vwmaccus_vx_w, 4, 8)
++GEN_VEXT_VX(vwmaccu_vx_b)
++GEN_VEXT_VX(vwmaccu_vx_h)
++GEN_VEXT_VX(vwmaccu_vx_w)
++GEN_VEXT_VX(vwmacc_vx_b)
++GEN_VEXT_VX(vwmacc_vx_h)
++GEN_VEXT_VX(vwmacc_vx_w)
++GEN_VEXT_VX(vwmaccsu_vx_b)
++GEN_VEXT_VX(vwmaccsu_vx_h)
++GEN_VEXT_VX(vwmaccsu_vx_w)
++GEN_VEXT_VX(vwmaccus_vx_b)
++GEN_VEXT_VX(vwmaccus_vx_h)
++GEN_VEXT_VX(vwmaccus_vx_w)
+ /* Vector Integer Merge and Move Instructions */
+ #define GEN_VEXT_VMV_VV(NAME, ETYPE, H)                              \
+@@ -XXX,XX +XXX,XX @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
+ static inline void
+ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
+              CPURISCVState *env,
+-             uint32_t desc, uint32_t esz, uint32_t dsz,
++             uint32_t desc,
+              opivv2_rm_fn *fn)
+ {
+     uint32_t vm = vext_vm(desc);
+@@ -XXX,XX +XXX,XX @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
+ }
+ /* generate helpers for fixed point instructions with OPIVV format */
+-#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ)                          \
++#define GEN_VEXT_VV_RM(NAME)                                    \
+ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,     \
+                   CPURISCVState *env, uint32_t desc)            \
+ {                                                               \
+-    vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ,         \
++    vext_vv_rm_2(vd, v0, vs1, vs2, env, desc,                   \
+                  do_##NAME);                                    \
+ }
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
+ RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
+ RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
+ RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
+-GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vsaddu_vv_b)
++GEN_VEXT_VV_RM(vsaddu_vv_h)
++GEN_VEXT_VV_RM(vsaddu_vv_w)
++GEN_VEXT_VV_RM(vsaddu_vv_d)
+ typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
+                           CPURISCVState *env, int vxrm);
+@@ -XXX,XX +XXX,XX @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
+ static inline void
+ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
+              CPURISCVState *env,
+-             uint32_t desc, uint32_t esz, uint32_t dsz,
++             uint32_t desc,
+              opivx2_rm_fn *fn)
+ {
+     uint32_t vm = vext_vm(desc);
+@@ -XXX,XX +XXX,XX @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
+ }
+ /* generate helpers for fixed point instructions with OPIVX format */
+-#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ)                    \
++#define GEN_VEXT_VX_RM(NAME)                              \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
+         void *vs2, CPURISCVState *env, uint32_t desc)     \
+ {                                                         \
+-    vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ,    \
++    vext_vx_rm_2(vd, v0, s1, vs2, env, desc,              \
+                  do_##NAME);                              \
+ }
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
+ RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
+ RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
+ RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
+-GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vsaddu_vx_b)
++GEN_VEXT_VX_RM(vsaddu_vx_h)
++GEN_VEXT_VX_RM(vsaddu_vx_w)
++GEN_VEXT_VX_RM(vsaddu_vx_d)
+ static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
+ RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
+ RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
+ RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
+-GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vsadd_vv_b)
++GEN_VEXT_VV_RM(vsadd_vv_h)
++GEN_VEXT_VV_RM(vsadd_vv_w)
++GEN_VEXT_VV_RM(vsadd_vv_d)
+ RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
+ RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
+ RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
+ RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
+-GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vsadd_vx_b)
++GEN_VEXT_VX_RM(vsadd_vx_h)
++GEN_VEXT_VX_RM(vsadd_vx_w)
++GEN_VEXT_VX_RM(vsadd_vx_d)
+ static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
+ RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
+ RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
+ RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
+-GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vssubu_vv_b)
++GEN_VEXT_VV_RM(vssubu_vv_h)
++GEN_VEXT_VV_RM(vssubu_vv_w)
++GEN_VEXT_VV_RM(vssubu_vv_d)
+ RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
+ RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
+ RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
+ RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
+-GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vssubu_vx_b)
++GEN_VEXT_VX_RM(vssubu_vx_h)
++GEN_VEXT_VX_RM(vssubu_vx_w)
++GEN_VEXT_VX_RM(vssubu_vx_d)
+ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
+ RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
+ RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
+ RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
+-GEN_VEXT_VV_RM(vssub_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vssub_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vssub_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vssub_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vssub_vv_b)
++GEN_VEXT_VV_RM(vssub_vv_h)
++GEN_VEXT_VV_RM(vssub_vv_w)
++GEN_VEXT_VV_RM(vssub_vv_d)
+ RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
+ RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
+ RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
+ RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
+-GEN_VEXT_VX_RM(vssub_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vssub_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vssub_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vssub_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vssub_vx_b)
++GEN_VEXT_VX_RM(vssub_vx_h)
++GEN_VEXT_VX_RM(vssub_vx_w)
++GEN_VEXT_VX_RM(vssub_vx_d)
+ /* Vector Single-Width Averaging Add and Subtract */
+ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
+ RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
+ RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
+ RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
+-GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vaadd_vv_b)
++GEN_VEXT_VV_RM(vaadd_vv_h)
++GEN_VEXT_VV_RM(vaadd_vv_w)
++GEN_VEXT_VV_RM(vaadd_vv_d)
+ RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
+ RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
+ RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
+ RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
+-GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vaadd_vx_b)
++GEN_VEXT_VX_RM(vaadd_vx_h)
++GEN_VEXT_VX_RM(vaadd_vx_w)
++GEN_VEXT_VX_RM(vaadd_vx_d)
+ static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
+                                uint32_t a, uint32_t b)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
+ RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
+ RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
+ RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
+-GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vaaddu_vv_b)
++GEN_VEXT_VV_RM(vaaddu_vv_h)
++GEN_VEXT_VV_RM(vaaddu_vv_w)
++GEN_VEXT_VV_RM(vaaddu_vv_d)
+ RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
+ RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
+ RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
+ RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
+-GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vaaddu_vx_b)
++GEN_VEXT_VX_RM(vaaddu_vx_h)
++GEN_VEXT_VX_RM(vaaddu_vx_w)
++GEN_VEXT_VX_RM(vaaddu_vx_d)
+ static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+ {
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
+ RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
+ RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
+ RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
+-GEN_VEXT_VV_RM(vasub_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vasub_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vasub_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vasub_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vasub_vv_b)
++GEN_VEXT_VV_RM(vasub_vv_h)
++GEN_VEXT_VV_RM(vasub_vv_w)
++GEN_VEXT_VV_RM(vasub_vv_d)
+ RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
+ RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
+ RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
+ RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
+-GEN_VEXT_VX_RM(vasub_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vasub_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vasub_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vasub_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vasub_vx_b)
++GEN_VEXT_VX_RM(vasub_vx_h)
++GEN_VEXT_VX_RM(vasub_vx_w)
++GEN_VEXT_VX_RM(vasub_vx_d)
+ static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
+                                uint32_t a, uint32_t b)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
+ RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
+ RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
+ RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
+-GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vasubu_vv_b)
++GEN_VEXT_VV_RM(vasubu_vv_h)
++GEN_VEXT_VV_RM(vasubu_vv_w)
++GEN_VEXT_VV_RM(vasubu_vv_d)
+ RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
+ RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
+ RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
+ RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
+-GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vasubu_vx_b)
++GEN_VEXT_VX_RM(vasubu_vx_h)
++GEN_VEXT_VX_RM(vasubu_vx_w)
++GEN_VEXT_VX_RM(vasubu_vx_d)
+ /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
+ RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
+ RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
+ RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
+-GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vsmul_vv_b)
++GEN_VEXT_VV_RM(vsmul_vv_h)
++GEN_VEXT_VV_RM(vsmul_vv_w)
++GEN_VEXT_VV_RM(vsmul_vv_d)
+ RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
+ RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
+ RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
+ RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
+-GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vsmul_vx_b)
++GEN_VEXT_VX_RM(vsmul_vx_h)
++GEN_VEXT_VX_RM(vsmul_vx_w)
++GEN_VEXT_VX_RM(vsmul_vx_d)
+ /* Vector Single-Width Scaling Shift Instructions */
+ static inline uint8_t
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
+ RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
+ RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
+ RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
+-GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vssrl_vv_b)
++GEN_VEXT_VV_RM(vssrl_vv_h)
++GEN_VEXT_VV_RM(vssrl_vv_w)
++GEN_VEXT_VV_RM(vssrl_vv_d)
+ RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
+ RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
+ RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
+ RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
+-GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vssrl_vx_b)
++GEN_VEXT_VX_RM(vssrl_vx_h)
++GEN_VEXT_VX_RM(vssrl_vx_w)
++GEN_VEXT_VX_RM(vssrl_vx_d)
+ static inline int8_t
+ vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
+ RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
+ RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
+ RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
+-GEN_VEXT_VV_RM(vssra_vv_b, 1, 1)
+-GEN_VEXT_VV_RM(vssra_vv_h, 2, 2)
+-GEN_VEXT_VV_RM(vssra_vv_w, 4, 4)
+-GEN_VEXT_VV_RM(vssra_vv_d, 8, 8)
++GEN_VEXT_VV_RM(vssra_vv_b)
++GEN_VEXT_VV_RM(vssra_vv_h)
++GEN_VEXT_VV_RM(vssra_vv_w)
++GEN_VEXT_VV_RM(vssra_vv_d)
+ RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
+ RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
+ RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
+ RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
+-GEN_VEXT_VX_RM(vssra_vx_b, 1, 1)
+-GEN_VEXT_VX_RM(vssra_vx_h, 2, 2)
+-GEN_VEXT_VX_RM(vssra_vx_w, 4, 4)
+-GEN_VEXT_VX_RM(vssra_vx_d, 8, 8)
++GEN_VEXT_VX_RM(vssra_vx_b)
++GEN_VEXT_VX_RM(vssra_vx_h)
++GEN_VEXT_VX_RM(vssra_vx_w)
++GEN_VEXT_VX_RM(vssra_vx_d)
+ /* Vector Narrowing Fixed-Point Clip Instructions */
+ static inline int8_t
+@@ -XXX,XX +XXX,XX @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
+ RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
+ RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
+ RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
+-GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1)
+-GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2)
+-GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4)
++GEN_VEXT_VV_RM(vnclip_wv_b)
++GEN_VEXT_VV_RM(vnclip_wv_h)
++GEN_VEXT_VV_RM(vnclip_wv_w)
+ RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
+ RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
+ RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
+-GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1)
+-GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2)
+-GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4)
++GEN_VEXT_VX_RM(vnclip_wx_b)
++GEN_VEXT_VX_RM(vnclip_wx_h)
++GEN_VEXT_VX_RM(vnclip_wx_w)
+ static inline uint8_t
+ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
+@@ -XXX,XX +XXX,XX @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
+ RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
+ RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
+ RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
+-GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1)
+-GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2)
+-GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4)
++GEN_VEXT_VV_RM(vnclipu_wv_b)
++GEN_VEXT_VV_RM(vnclipu_wv_h)
++GEN_VEXT_VV_RM(vnclipu_wv_w)
+ RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
+ RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
+ RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
+-GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1)
+-GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2)
+-GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4)
++GEN_VEXT_VX_RM(vnclipu_wx_b)
++GEN_VEXT_VX_RM(vnclipu_wx_h)
++GEN_VEXT_VX_RM(vnclipu_wx_w)
+ /*
+  *** Vector Float Point Arithmetic Instructions
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \
+     *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status);         \
+ }
+-#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ)                   \
++#define GEN_VEXT_VV_ENV(NAME)                             \
+ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
+                   void *vs2, CPURISCVState *env,          \
+                   uint32_t desc)                          \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
+ RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
+ RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
+ RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
+-GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfadd_vv_h)
++GEN_VEXT_VV_ENV(vfadd_vv_w)
++GEN_VEXT_VV_ENV(vfadd_vv_d)
+ #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)        \
+ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
+     *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
+ }
+-#define GEN_VEXT_VF(NAME, ESZ, DSZ)                       \
++#define GEN_VEXT_VF(NAME)                                 \
+ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
+                   void *vs2, CPURISCVState *env,          \
+                   uint32_t desc)                          \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
+ RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
+ RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
+ RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
+-GEN_VEXT_VF(vfadd_vf_h, 2, 2)
+-GEN_VEXT_VF(vfadd_vf_w, 4, 4)
+-GEN_VEXT_VF(vfadd_vf_d, 8, 8)
++GEN_VEXT_VF(vfadd_vf_h)
++GEN_VEXT_VF(vfadd_vf_w)
++GEN_VEXT_VF(vfadd_vf_d)
+ RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
+ RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
+ RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
+-GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfsub_vv_h)
++GEN_VEXT_VV_ENV(vfsub_vv_w)
++GEN_VEXT_VV_ENV(vfsub_vv_d)
+ RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
+ RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
+ RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
+-GEN_VEXT_VF(vfsub_vf_h, 2, 2)
+-GEN_VEXT_VF(vfsub_vf_w, 4, 4)
+-GEN_VEXT_VF(vfsub_vf_d, 8, 8)
++GEN_VEXT_VF(vfsub_vf_h)
++GEN_VEXT_VF(vfsub_vf_w)
++GEN_VEXT_VF(vfsub_vf_d)
+ static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
+ RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
+ RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
+ RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
+-GEN_VEXT_VF(vfrsub_vf_h, 2, 2)
+-GEN_VEXT_VF(vfrsub_vf_w, 4, 4)
+-GEN_VEXT_VF(vfrsub_vf_d, 8, 8)
++GEN_VEXT_VF(vfrsub_vf_h)
++GEN_VEXT_VF(vfrsub_vf_w)
++GEN_VEXT_VF(vfrsub_vf_d)
+ /* Vector Widening Floating-Point Add/Subtract Instructions */
+ static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
+@@ -XXX,XX +XXX,XX @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
+ RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
+ RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
+-GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwadd_vv_h)
++GEN_VEXT_VV_ENV(vfwadd_vv_w)
+ RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
+ RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
+-GEN_VEXT_VF(vfwadd_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwadd_vf_w, 4, 8)
++GEN_VEXT_VF(vfwadd_vf_h)
++GEN_VEXT_VF(vfwadd_vf_w)
+ static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
+ RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
+ RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
+-GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwsub_vv_h)
++GEN_VEXT_VV_ENV(vfwsub_vv_w)
+ RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
+ RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
+-GEN_VEXT_VF(vfwsub_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwsub_vf_w, 4, 8)
++GEN_VEXT_VF(vfwsub_vf_h)
++GEN_VEXT_VF(vfwsub_vf_w)
+ static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
+ RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
+ RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
+-GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwadd_wv_h)
++GEN_VEXT_VV_ENV(vfwadd_wv_w)
+ RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
+ RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
+-GEN_VEXT_VF(vfwadd_wf_h, 2, 4)
+-GEN_VEXT_VF(vfwadd_wf_w, 4, 8)
++GEN_VEXT_VF(vfwadd_wf_h)
++GEN_VEXT_VF(vfwadd_wf_w)
+ static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
+ RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
+ RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
+-GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwsub_wv_h)
++GEN_VEXT_VV_ENV(vfwsub_wv_w)
+ RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
+ RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
+-GEN_VEXT_VF(vfwsub_wf_h, 2, 4)
+-GEN_VEXT_VF(vfwsub_wf_w, 4, 8)
++GEN_VEXT_VF(vfwsub_wf_h)
++GEN_VEXT_VF(vfwsub_wf_w)
+ /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
+ RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
+ RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
+ RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
+-GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmul_vv_h)
++GEN_VEXT_VV_ENV(vfmul_vv_w)
++GEN_VEXT_VV_ENV(vfmul_vv_d)
+ RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
+ RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
+ RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
+-GEN_VEXT_VF(vfmul_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmul_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmul_vf_d, 8, 8)
++GEN_VEXT_VF(vfmul_vf_h)
++GEN_VEXT_VF(vfmul_vf_w)
++GEN_VEXT_VF(vfmul_vf_d)
+ RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
+ RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
+ RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
+-GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfdiv_vv_h)
++GEN_VEXT_VV_ENV(vfdiv_vv_w)
++GEN_VEXT_VV_ENV(vfdiv_vv_d)
+ RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
+ RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
+ RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
+-GEN_VEXT_VF(vfdiv_vf_h, 2, 2)
+-GEN_VEXT_VF(vfdiv_vf_w, 4, 4)
+-GEN_VEXT_VF(vfdiv_vf_d, 8, 8)
++GEN_VEXT_VF(vfdiv_vf_h)
++GEN_VEXT_VF(vfdiv_vf_w)
++GEN_VEXT_VF(vfdiv_vf_d)
+ static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
+ RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
+ RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
+ RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
+-GEN_VEXT_VF(vfrdiv_vf_h, 2, 2)
+-GEN_VEXT_VF(vfrdiv_vf_w, 4, 4)
+-GEN_VEXT_VF(vfrdiv_vf_d, 8, 8)
++GEN_VEXT_VF(vfrdiv_vf_h)
++GEN_VEXT_VF(vfrdiv_vf_w)
++GEN_VEXT_VF(vfrdiv_vf_d)
+ /* Vector Widening Floating-Point Multiply */
+ static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
+@@ -XXX,XX +XXX,XX @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
+ }
+ RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
+ RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
+-GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwmul_vv_h)
++GEN_VEXT_VV_ENV(vfwmul_vv_w)
+ RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
+ RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
+-GEN_VEXT_VF(vfwmul_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwmul_vf_w, 4, 8)
++GEN_VEXT_VF(vfwmul_vf_h)
++GEN_VEXT_VF(vfwmul_vf_w)
+ /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
+ #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)       \
+@@ -XXX,XX +XXX,XX @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
+ RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
+ RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
+-GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmacc_vv_h)
++GEN_VEXT_VV_ENV(vfmacc_vv_w)
++GEN_VEXT_VV_ENV(vfmacc_vv_d)
+ #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)           \
+ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
+ RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
+ RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
+ RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
+-GEN_VEXT_VF(vfmacc_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmacc_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmacc_vf_d, 8, 8)
++GEN_VEXT_VF(vfmacc_vf_h)
++GEN_VEXT_VF(vfmacc_vf_w)
++GEN_VEXT_VF(vfmacc_vf_d)
+ static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
+ RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
+ RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
+-GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfnmacc_vv_h)
++GEN_VEXT_VV_ENV(vfnmacc_vv_w)
++GEN_VEXT_VV_ENV(vfnmacc_vv_d)
+ RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
+ RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
+ RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
+-GEN_VEXT_VF(vfnmacc_vf_h, 2, 2)
+-GEN_VEXT_VF(vfnmacc_vf_w, 4, 4)
+-GEN_VEXT_VF(vfnmacc_vf_d, 8, 8)
++GEN_VEXT_VF(vfnmacc_vf_h)
++GEN_VEXT_VF(vfnmacc_vf_w)
++GEN_VEXT_VF(vfnmacc_vf_d)
+ static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
+ RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
+ RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
+-GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmsac_vv_h)
++GEN_VEXT_VV_ENV(vfmsac_vv_w)
++GEN_VEXT_VV_ENV(vfmsac_vv_d)
+ RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
+ RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
+ RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
+-GEN_VEXT_VF(vfmsac_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmsac_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmsac_vf_d, 8, 8)
++GEN_VEXT_VF(vfmsac_vf_h)
++GEN_VEXT_VF(vfmsac_vf_w)
++GEN_VEXT_VF(vfmsac_vf_d)
+ static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
+ RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
+ RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
+-GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfnmsac_vv_h)
++GEN_VEXT_VV_ENV(vfnmsac_vv_w)
++GEN_VEXT_VV_ENV(vfnmsac_vv_d)
+ RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
+ RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
+ RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
+-GEN_VEXT_VF(vfnmsac_vf_h, 2, 2)
+-GEN_VEXT_VF(vfnmsac_vf_w, 4, 4)
+-GEN_VEXT_VF(vfnmsac_vf_d, 8, 8)
++GEN_VEXT_VF(vfnmsac_vf_h)
++GEN_VEXT_VF(vfnmsac_vf_w)
++GEN_VEXT_VF(vfnmsac_vf_d)
+ static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
+ RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
+ RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
+-GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmadd_vv_h)
++GEN_VEXT_VV_ENV(vfmadd_vv_w)
++GEN_VEXT_VV_ENV(vfmadd_vv_d)
+ RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
+ RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
+ RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
+-GEN_VEXT_VF(vfmadd_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmadd_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmadd_vf_d, 8, 8)
++GEN_VEXT_VF(vfmadd_vf_h)
++GEN_VEXT_VF(vfmadd_vf_w)
++GEN_VEXT_VF(vfmadd_vf_d)
+ static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
+ RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
+ RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
+-GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfnmadd_vv_h)
++GEN_VEXT_VV_ENV(vfnmadd_vv_w)
++GEN_VEXT_VV_ENV(vfnmadd_vv_d)
+ RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
+ RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
+ RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
+-GEN_VEXT_VF(vfnmadd_vf_h, 2, 2)
+-GEN_VEXT_VF(vfnmadd_vf_w, 4, 4)
+-GEN_VEXT_VF(vfnmadd_vf_d, 8, 8)
++GEN_VEXT_VF(vfnmadd_vf_h)
++GEN_VEXT_VF(vfnmadd_vf_w)
++GEN_VEXT_VF(vfnmadd_vf_d)
+ static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
+ RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
+ RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
+-GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmsub_vv_h)
++GEN_VEXT_VV_ENV(vfmsub_vv_w)
++GEN_VEXT_VV_ENV(vfmsub_vv_d)
+ RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
+ RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
+ RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
+-GEN_VEXT_VF(vfmsub_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmsub_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmsub_vf_d, 8, 8)
++GEN_VEXT_VF(vfmsub_vf_h)
++GEN_VEXT_VF(vfmsub_vf_w)
++GEN_VEXT_VF(vfmsub_vf_d)
+ static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
+ RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
+ RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
+-GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfnmsub_vv_h)
++GEN_VEXT_VV_ENV(vfnmsub_vv_w)
++GEN_VEXT_VV_ENV(vfnmsub_vv_d)
+ RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
+ RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
+ RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
+-GEN_VEXT_VF(vfnmsub_vf_h, 2, 2)
+-GEN_VEXT_VF(vfnmsub_vf_w, 4, 4)
+-GEN_VEXT_VF(vfnmsub_vf_d, 8, 8)
++GEN_VEXT_VF(vfnmsub_vf_h)
++GEN_VEXT_VF(vfnmsub_vf_w)
++GEN_VEXT_VF(vfnmsub_vf_d)
+ /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
+ static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+@@ -XXX,XX +XXX,XX @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
+ RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
+-GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwmacc_vv_h)
++GEN_VEXT_VV_ENV(vfwmacc_vv_w)
+ RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
+ RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
+-GEN_VEXT_VF(vfwmacc_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwmacc_vf_w, 4, 8)
++GEN_VEXT_VF(vfwmacc_vf_h)
++GEN_VEXT_VF(vfwmacc_vf_w)
+ static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
+ RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
+-GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwnmacc_vv_h)
++GEN_VEXT_VV_ENV(vfwnmacc_vv_w)
+ RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
+ RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
+-GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8)
++GEN_VEXT_VF(vfwnmacc_vf_h)
++GEN_VEXT_VF(vfwnmacc_vf_w)
+ static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
+ RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
+-GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwmsac_vv_h)
++GEN_VEXT_VV_ENV(vfwmsac_vv_w)
+ RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
+ RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
+-GEN_VEXT_VF(vfwmsac_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwmsac_vf_w, 4, 8)
++GEN_VEXT_VF(vfwmsac_vf_h)
++GEN_VEXT_VF(vfwmsac_vf_w)
+ static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
+ RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
+ RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
+-GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4)
+-GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8)
++GEN_VEXT_VV_ENV(vfwnmsac_vv_h)
++GEN_VEXT_VV_ENV(vfwnmsac_vv_w)
+ RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
+ RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
+-GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4)
+-GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8)
++GEN_VEXT_VF(vfwnmsac_vf_h)
++GEN_VEXT_VF(vfwnmsac_vf_w)
+ /* Vector Floating-Point Square-Root Instruction */
+ /* (TD, T2, TX2) */
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i,      \
+     *((TD *)vd + HD(i)) = OP(s2, &env->fp_status);     \
+ }
+-#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ)                 \
++#define GEN_VEXT_V_ENV(NAME)                           \
+ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+         CPURISCVState *env, uint32_t desc)             \
+ {                                                      \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+ RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
+ RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
+ RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
+-GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfsqrt_v_h)
++GEN_VEXT_V_ENV(vfsqrt_v_w)
++GEN_VEXT_V_ENV(vfsqrt_v_d)
+ /*
+  * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+@@ -XXX,XX +XXX,XX @@ static float64 frsqrt7_d(float64 f, float_status *s)
+ RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
+ RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
+ RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
+-GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfrsqrt7_v_h)
++GEN_VEXT_V_ENV(vfrsqrt7_v_w)
++GEN_VEXT_V_ENV(vfrsqrt7_v_d)
+ /*
+  * Vector Floating-Point Reciprocal Estimate Instruction
+@@ -XXX,XX +XXX,XX @@ static float64 frec7_d(float64 f, float_status *s)
+ RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
+ RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
+ RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
+-GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfrec7_v_h)
++GEN_VEXT_V_ENV(vfrec7_v_w)
++GEN_VEXT_V_ENV(vfrec7_v_d)
+ /* Vector Floating-Point MIN/MAX Instructions */
+ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
+ RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
+ RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
+-GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmin_vv_h)
++GEN_VEXT_VV_ENV(vfmin_vv_w)
++GEN_VEXT_VV_ENV(vfmin_vv_d)
+ RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
+ RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
+ RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
+-GEN_VEXT_VF(vfmin_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmin_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmin_vf_d, 8, 8)
++GEN_VEXT_VF(vfmin_vf_h)
++GEN_VEXT_VF(vfmin_vf_w)
++GEN_VEXT_VF(vfmin_vf_d)
+ RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
+ RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
+ RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
+-GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfmax_vv_h)
++GEN_VEXT_VV_ENV(vfmax_vv_w)
++GEN_VEXT_VV_ENV(vfmax_vv_d)
+ RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
+ RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
+ RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
+-GEN_VEXT_VF(vfmax_vf_h, 2, 2)
+-GEN_VEXT_VF(vfmax_vf_w, 4, 4)
+-GEN_VEXT_VF(vfmax_vf_d, 8, 8)
++GEN_VEXT_VF(vfmax_vf_h)
++GEN_VEXT_VF(vfmax_vf_w)
++GEN_VEXT_VF(vfmax_vf_d)
+ /* Vector Floating-Point Sign-Injection Instructions */
+ static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
+@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
+ RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
+ RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
+ RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
+-GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfsgnj_vv_h)
++GEN_VEXT_VV_ENV(vfsgnj_vv_w)
++GEN_VEXT_VV_ENV(vfsgnj_vv_d)
+ RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
+ RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
+ RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
+-GEN_VEXT_VF(vfsgnj_vf_h, 2, 2)
+-GEN_VEXT_VF(vfsgnj_vf_w, 4, 4)
+-GEN_VEXT_VF(vfsgnj_vf_d, 8, 8)
++GEN_VEXT_VF(vfsgnj_vf_h)
++GEN_VEXT_VF(vfsgnj_vf_w)
++GEN_VEXT_VF(vfsgnj_vf_d)
+ static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
+ RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
+ RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
+ RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
+-GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfsgnjn_vv_h)
++GEN_VEXT_VV_ENV(vfsgnjn_vv_w)
++GEN_VEXT_VV_ENV(vfsgnjn_vv_d)
+ RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
+ RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
+ RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
+-GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2)
+-GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4)
+-GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8)
++GEN_VEXT_VF(vfsgnjn_vf_h)
++GEN_VEXT_VF(vfsgnjn_vf_w)
++GEN_VEXT_VF(vfsgnjn_vf_d)
+ static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
+ RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
+ RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
+ RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
+-GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2)
+-GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4)
+-GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8)
++GEN_VEXT_VV_ENV(vfsgnjx_vv_h)
++GEN_VEXT_VV_ENV(vfsgnjx_vv_w)
++GEN_VEXT_VV_ENV(vfsgnjx_vv_d)
+ RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
+ RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
+ RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
+-GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2)
+-GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4)
+-GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8)
++GEN_VEXT_VF(vfsgnjx_vf_h)
++GEN_VEXT_VF(vfsgnjx_vf_w)
++GEN_VEXT_VF(vfsgnjx_vf_d)
+ /* Vector Floating-Point Compare Instructions */
+ #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP)            \
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i)      \
+     *((TD *)vd + HD(i)) = OP(s2);                      \
+ }
+-#define GEN_VEXT_V(NAME, ESZ, DSZ)                     \
++#define GEN_VEXT_V(NAME)                               \
+ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+                   CPURISCVState *env, uint32_t desc)   \
+ {                                                      \
+@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1)
+ RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
+ RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
+ RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
+-GEN_VEXT_V(vfclass_v_h, 2, 2)
+-GEN_VEXT_V(vfclass_v_w, 4, 4)
+-GEN_VEXT_V(vfclass_v_d, 8, 8)
++GEN_VEXT_V(vfclass_v_h)
++GEN_VEXT_V(vfclass_v_w)
++GEN_VEXT_V(vfclass_v_d)
+ /* Vector Floating-Point Merge Instruction */
+ #define GEN_VFMERGE_VF(NAME, ETYPE, H)                        \
+@@ -XXX,XX +XXX,XX @@ GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8)
+ RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
+ RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
+ RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
+-GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfcvt_xu_f_v_h)
++GEN_VEXT_V_ENV(vfcvt_xu_f_v_w)
++GEN_VEXT_V_ENV(vfcvt_xu_f_v_d)
+ /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
+ RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
+ RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
+ RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
+-GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfcvt_x_f_v_h)
++GEN_VEXT_V_ENV(vfcvt_x_f_v_w)
++GEN_VEXT_V_ENV(vfcvt_x_f_v_d)
+ /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
+ RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
+ RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
+ RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
+-GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfcvt_f_xu_v_h)
++GEN_VEXT_V_ENV(vfcvt_f_xu_v_w)
++GEN_VEXT_V_ENV(vfcvt_f_xu_v_d)
+ /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
+ RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
+ RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
+ RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
+-GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2)
+-GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4)
+-GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
++GEN_VEXT_V_ENV(vfcvt_f_x_v_h)
++GEN_VEXT_V_ENV(vfcvt_f_x_v_w)
++GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
+ /* Widening Floating-Point/Integer Type-Convert Instructions */
+ /* (TD, T2, TX2) */
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
+ /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
+ RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
+ RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
+-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4)
+-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8)
++GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h)
++GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w)
+ /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */
+ RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32)
+ RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
+-GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
+-GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
++GEN_VEXT_V_ENV(vfwcvt_x_f_v_h)
++GEN_VEXT_V_ENV(vfwcvt_x_f_v_w)
+ /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+ RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
+ RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
+ RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
+-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2)
+-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
+-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
++GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b)
++GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h)
++GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w)
+ /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
+ RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
+ RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
+ RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
+-GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2)
+-GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
+-GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
++GEN_VEXT_V_ENV(vfwcvt_f_x_v_b)
++GEN_VEXT_V_ENV(vfwcvt_f_x_v_h)
++GEN_VEXT_V_ENV(vfwcvt_f_x_v_w)
+ /*
+  * vfwcvt.f.f.v vd, vs2, vm
+@@ -XXX,XX +XXX,XX @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
+ RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16)
+ RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
+-GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4)
+-GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
++GEN_VEXT_V_ENV(vfwcvt_f_f_v_h)
++GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
+ /* Narrowing Floating-Point/Integer Type-Convert Instructions */
+ /* (TD, T2, TX2) */
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
+ RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+ RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+ RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+-GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
+-GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
+-GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
++GEN_VEXT_V_ENV(vfncvt_xu_f_w_b)
++GEN_VEXT_V_ENV(vfncvt_xu_f_w_h)
++GEN_VEXT_V_ENV(vfncvt_xu_f_w_w)
+ /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
+ RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+ RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+ RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+-GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
+-GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
+-GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
++GEN_VEXT_V_ENV(vfncvt_x_f_w_b)
++GEN_VEXT_V_ENV(vfncvt_x_f_w_h)
++GEN_VEXT_V_ENV(vfncvt_x_f_w_w)
+ /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
+ RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+ RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+-GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
+-GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
++GEN_VEXT_V_ENV(vfncvt_f_xu_w_h)
++GEN_VEXT_V_ENV(vfncvt_f_xu_w_w)
+ /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
+ RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+ RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+-GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
+-GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
++GEN_VEXT_V_ENV(vfncvt_f_x_w_h)
++GEN_VEXT_V_ENV(vfncvt_f_x_w_w)
+ /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
+ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
+@@ -XXX,XX +XXX,XX @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
+ RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+ RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+-GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
+-GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
++GEN_VEXT_V_ENV(vfncvt_f_f_w_h)
++GEN_VEXT_V_ENV(vfncvt_f_f_w_w)
+ /*
+  *** Vector Reduction Operations
+--
+.36.1

-New patch
+[PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed
+From: eopXD <yueh.ting.chen@gmail.com>
+No functional change intended in this commit.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-2@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 35 ++++++++++++++++-------------------
+file changed, 16 insertions(+), 19 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
+                  target_ulong stride, CPURISCVState *env,
+                  uint32_t desc, uint32_t vm,
+                  vext_ldst_elem_fn *ldst_elem,
+-                 uint32_t esz, uintptr_t ra, MMUAccessType access_type)
++                 uint32_t esz, uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base,               \
+ {                                                                       \
+     uint32_t vm = vext_vm(desc);                                        \
+     vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN,      \
+-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD);      \
++                     ctzl(sizeof(ETYPE)), GETPC());                     \
+ }
+ GEN_VEXT_LD_STRIDE(vlse8_v,  int8_t,  lde_b)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                \
+ {                                                                       \
+     uint32_t vm = vext_vm(desc);                                        \
+     vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN,     \
+-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE);     \
++                     ctzl(sizeof(ETYPE)), GETPC());                     \
+ }
+ GEN_VEXT_ST_STRIDE(vsse8_v,  int8_t,  ste_b)
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
+ static void
+ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+              vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
+-             uintptr_t ra, MMUAccessType access_type)
++             uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base,         \
+ {                                                                       \
+     uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE));             \
+     vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN,   \
+-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD);      \
++                     ctzl(sizeof(ETYPE)), GETPC());                     \
+ }                                                                       \
+                                                                         \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                \
+                   CPURISCVState *env, uint32_t desc)                    \
+ {                                                                       \
+     vext_ldst_us(vd, base, env, desc, LOAD_FN,                          \
+-                 ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \
++                 ctzl(sizeof(ETYPE)), env->vl, GETPC());                \
+ }
+ GEN_VEXT_LD_US(vle8_v,  int8_t,  lde_b)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base,          \
+ {                                                                        \
+     uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE));              \
+     vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN,   \
+-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE);      \
++                     ctzl(sizeof(ETYPE)), GETPC());                      \
+ }                                                                        \
+                                                                          \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                 \
+                   CPURISCVState *env, uint32_t desc)                     \
+ {                                                                        \
+     vext_ldst_us(vd, base, env, desc, STORE_FN,                          \
+-                 ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \
++                 ctzl(sizeof(ETYPE)), env->vl, GETPC());                 \
+ }
+ GEN_VEXT_ST_US(vse8_v,  int8_t,  ste_b)
+@@ -XXX,XX +XXX,XX @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
+     /* evl = ceil(vl/8) */
+     uint8_t evl = (env->vl + 7) >> 3;
+     vext_ldst_us(vd, base, env, desc, lde_b,
+-                 0, evl, GETPC(), MMU_DATA_LOAD);
++                 0, evl, GETPC());
+ }
+ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
+@@ -XXX,XX +XXX,XX @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
+     /* evl = ceil(vl/8) */
+     uint8_t evl = (env->vl + 7) >> 3;
+     vext_ldst_us(vd, base, env, desc, ste_b,
+-                 0, evl, GETPC(), MMU_DATA_STORE);
++                 0, evl, GETPC());
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
+                 void *vs2, CPURISCVState *env, uint32_t desc,
+                 vext_get_index_addr get_index_addr,
+                 vext_ldst_elem_fn *ldst_elem,
+-                uint32_t esz, uintptr_t ra, MMUAccessType access_type)
++                uint32_t esz, uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                   \
+                   void *vs2, CPURISCVState *env, uint32_t desc)            \
+ {                                                                          \
+     vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN,                \
+-                    LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
++                    LOAD_FN, ctzl(sizeof(ETYPE)), GETPC());                \
+ }
+ GEN_VEXT_LD_INDEX(vlxei8_8_v,   int8_t,  idx_b, lde_b)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,         \
+ {                                                                \
+     vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN,      \
+                     STORE_FN, ctzl(sizeof(ETYPE)),               \
+-                    GETPC(), MMU_DATA_STORE);                    \
++                    GETPC());                                    \
+ }
+ GEN_VEXT_ST_INDEX(vsxei8_8_v,   int8_t,  idx_b, ste_b)
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
+  */
+ static void
+ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+-                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
+-                MMUAccessType access_type)
++                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra)
+ {
+     uint32_t i, k, off, pos;
+     uint32_t nf = vext_nf(desc);
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, target_ulong base,       \
+                   CPURISCVState *env, uint32_t desc) \
+ {                                                    \
+     vext_ldst_whole(vd, base, env, desc, LOAD_FN,    \
+-                    ctzl(sizeof(ETYPE)), GETPC(),    \
+-                    MMU_DATA_LOAD);                  \
++                    ctzl(sizeof(ETYPE)), GETPC());   \
+ }
+ GEN_VEXT_LD_WHOLE(vl1re8_v,  int8_t,  lde_b)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, target_ulong base,       \
+                   CPURISCVState *env, uint32_t desc) \
+ {                                                    \
+     vext_ldst_whole(vd, base, env, desc, STORE_FN,   \
+-                    ctzl(sizeof(ETYPE)), GETPC(),    \
+-                    MMU_DATA_STORE);                 \
++                    ctzl(sizeof(ETYPE)), GETPC());   \
+ }
+ GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
+--
+.36.1

-New patch
+[PULL 10/25] target/riscv: rvv: Rename ambiguous esz
+From: eopXD <yueh.ting.chen@gmail.com>
+No functional change intended in this commit.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-3@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 76 ++++++++++++++++++------------------
+file changed, 38 insertions(+), 38 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ static inline int32_t vext_lmul(uint32_t desc)
+ /*
+  * Get the maximum number of elements can be operated.
+  *
+- * esz: log2 of element size in bytes.
++ * log2_esz: log2 of element size in bytes.
+  */
+-static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
++static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
+ {
+     /*
+      * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
+     uint32_t vlenb = simd_maxsz(desc);
+     /* Return VLMAX */
+-    int scale = vext_lmul(desc) - esz;
++    int scale = vext_lmul(desc) - log2_esz;
+     return scale < 0 ? vlenb >> -scale : vlenb << scale;
+ }
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
+                  target_ulong stride, CPURISCVState *env,
+                  uint32_t desc, uint32_t vm,
+                  vext_ldst_elem_fn *ldst_elem,
+-                 uint32_t esz, uintptr_t ra)
++                 uint32_t log2_esz, uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+-    uint32_t max_elems = vext_max_elems(desc, esz);
++    uint32_t max_elems = vext_max_elems(desc, log2_esz);
+     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
+         if (!vm && !vext_elem_mask(v0, i)) {
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
+         k = 0;
+         while (k < nf) {
+-            target_ulong addr = base + stride * i + (k << esz);
++            target_ulong addr = base + stride * i + (k << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
+             k++;
+         }
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
+ /* unmasked unit-stride load and store operation*/
+ static void
+ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+-             vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
++             vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
+              uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+-    uint32_t max_elems = vext_max_elems(desc, esz);
++    uint32_t max_elems = vext_max_elems(desc, log2_esz);
+     /* load bytes from guest memory */
+     for (i = env->vstart; i < evl; i++, env->vstart++) {
+         k = 0;
+         while (k < nf) {
+-            target_ulong addr = base + ((i * nf + k) << esz);
++            target_ulong addr = base + ((i * nf + k) << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
+             k++;
+         }
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
+                 void *vs2, CPURISCVState *env, uint32_t desc,
+                 vext_get_index_addr get_index_addr,
+                 vext_ldst_elem_fn *ldst_elem,
+-                uint32_t esz, uintptr_t ra)
++                uint32_t log2_esz, uintptr_t ra)
+ {
+     uint32_t i, k;
+     uint32_t nf = vext_nf(desc);
+     uint32_t vm = vext_vm(desc);
+-    uint32_t max_elems = vext_max_elems(desc, esz);
++    uint32_t max_elems = vext_max_elems(desc, log2_esz);
+     /* load bytes from guest memory */
+     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
+         k = 0;
+         while (k < nf) {
+-            abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
++            abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
+             k++;
+         }
+@@ -XXX,XX +XXX,XX @@ static inline void
+ vext_ldff(void *vd, void *v0, target_ulong base,
+           CPURISCVState *env, uint32_t desc,
+           vext_ldst_elem_fn *ldst_elem,
+-          uint32_t esz, uintptr_t ra)
++          uint32_t log2_esz, uintptr_t ra)
+ {
+     void *host;
+     uint32_t i, k, vl = 0;
+     uint32_t nf = vext_nf(desc);
+     uint32_t vm = vext_vm(desc);
+-    uint32_t max_elems = vext_max_elems(desc, esz);
++    uint32_t max_elems = vext_max_elems(desc, log2_esz);
+     target_ulong addr, offset, remain;
+     /* probe every access*/
+@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
+         if (!vm && !vext_elem_mask(v0, i)) {
+             continue;
+         }
+-        addr = adjust_addr(env, base + i * (nf << esz));
++        addr = adjust_addr(env, base + i * (nf << log2_esz));
+         if (i == 0) {
+-            probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
++            probe_pages(env, addr, nf << log2_esz, ra, MMU_DATA_LOAD);
+         } else {
+             /* if it triggers an exception, no need to check watchpoint */
+-            remain = nf << esz;
++            remain = nf << log2_esz;
+             while (remain > 0) {
+                 offset = -(addr | TARGET_PAGE_MASK);
+                 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
+@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
+             continue;
+         }
+         while (k < nf) {
+-            target_ulong addr = base + ((i * nf + k) << esz);
++            target_ulong addr = base + ((i * nf + k) << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
+             k++;
+         }
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
+  */
+ static void
+ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+-                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra)
++                vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uintptr_t ra)
+ {
+     uint32_t i, k, off, pos;
+     uint32_t nf = vext_nf(desc);
+     uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+-    uint32_t max_elems = vlenb >> esz;
++    uint32_t max_elems = vlenb >> log2_esz;
+     k = env->vstart / max_elems;
+     off = env->vstart % max_elems;
+@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+     if (off) {
+         /* load/store rest of elements of current segment pointed by vstart */
+         for (pos = off; pos < max_elems; pos++, env->vstart++) {
+-            target_ulong addr = base + ((pos + k * max_elems) << esz);
++            target_ulong addr = base + ((pos + k * max_elems) << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
+         }
+         k++;
+@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+     /* load/store elements for rest of segments */
+     for (; k < nf; k++) {
+         for (i = 0; i < max_elems; i++, env->vstart++) {
+-            target_ulong addr = base + ((i + k * max_elems) << esz);
++            target_ulong addr = base + ((i + k * max_elems) << log2_esz);
+             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
+ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
+ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
+-#define GEN_VEXT_VSLIE1UP(ESZ, H)                                           \
+-static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
+-                     CPURISCVState *env, uint32_t desc)                     \
++#define GEN_VEXT_VSLIE1UP(BITWIDTH, H)                                      \
++static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
++                     void *vs2, CPURISCVState *env, uint32_t desc)          \
+ {                                                                           \
+-    typedef uint##ESZ##_t ETYPE;                                            \
++    typedef uint##BITWIDTH##_t ETYPE;                                       \
+     uint32_t vm = vext_vm(desc);                                            \
+     uint32_t vl = env->vl;                                                  \
+     uint32_t i;                                                             \
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIE1UP(16, H2)
+ GEN_VEXT_VSLIE1UP(32, H4)
+ GEN_VEXT_VSLIE1UP(64, H8)
+-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ)                          \
++#define GEN_VEXT_VSLIDE1UP_VX(NAME, BITWIDTH)                     \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+                   CPURISCVState *env, uint32_t desc)              \
+ {                                                                 \
+-    vslide1up_##ESZ(vd, v0, s1, vs2, env, desc);                  \
++    vslide1up_##BITWIDTH(vd, v0, s1, vs2, env, desc);             \
+ }
+ /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16)
+ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
+ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
+-#define GEN_VEXT_VSLIDE1DOWN(ESZ, H)                                          \
+-static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
+-                       CPURISCVState *env, uint32_t desc)                     \
++#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H)                                     \
++static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
++                       void *vs2, CPURISCVState *env, uint32_t desc)          \
+ {                                                                             \
+-    typedef uint##ESZ##_t ETYPE;                                              \
++    typedef uint##BITWIDTH##_t ETYPE;                                         \
+     uint32_t vm = vext_vm(desc);                                              \
+     uint32_t vl = env->vl;                                                    \
+     uint32_t i;                                                               \
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1DOWN(16, H2)
+ GEN_VEXT_VSLIDE1DOWN(32, H4)
+ GEN_VEXT_VSLIDE1DOWN(64, H8)
+-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ)                        \
++#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, BITWIDTH)                   \
+ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+                   CPURISCVState *env, uint32_t desc)              \
+ {                                                                 \
+-    vslide1down_##ESZ(vd, v0, s1, vs2, env, desc);                \
++    vslide1down_##BITWIDTH(vd, v0, s1, vs2, env, desc);           \
+ }
+ /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32)
+ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64)
+ /* Vector Floating-Point Slide Instructions */
+-#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ)                     \
++#define GEN_VEXT_VFSLIDE1UP_VF(NAME, BITWIDTH)                \
+ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+                   CPURISCVState *env, uint32_t desc)          \
+ {                                                             \
+-    vslide1up_##ESZ(vd, v0, s1, vs2, env, desc);              \
++    vslide1up_##BITWIDTH(vd, v0, s1, vs2, env, desc);         \
+ }
+ /* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16)
+ GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32)
+ GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64)
+-#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ)                   \
++#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, BITWIDTH)              \
+ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+                   CPURISCVState *env, uint32_t desc)          \
+ {                                                             \
+-    vslide1down_##ESZ(vd, v0, s1, vs2, env, desc);            \
++    vslide1down_##BITWIDTH(vd, v0, s1, vs2, env, desc);       \
+ }
+ /* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */
+--
+.36.1

-New patch
+[PULL 11/25] target/riscv: rvv: Early exit when vstart >= vl
+From: eopXD <yueh.ting.chen@gmail.com>
 According to v-spec (section 5.4):
 When vstart ≥ vl, there are no body elements, and no elements are
 updated in any destination vector register group, including that
 no tail elements are updated with agnostic values.
 vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselves
 require vstart to be zero. So they don't need the early exit.
 Signed-off-by: eop Chen <eop.chen@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <165449614532.19704.7000832880482980398-4@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++++
 file changed, 27 insertions(+)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
      }
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      if (a->vm && s->vl_eq_vlmax) {
          gvec_fn(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
              };
              TCGLabel *over = gen_new_label();
              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
              tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
                                 cpu_env, s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          TCGv s1;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          s1 = get_gpr(s, a->rs1, EXT_SIGN);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
              };
              TCGLabel *over = gen_new_label();
              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
              s1 = tcg_constant_i64(simm);
              dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
          TCGLabel *over = gen_new_label();                        \
          gen_set_rm(s, RISCV_FRM_DYN);                            \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
                                                                   \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
          TCGLabel *over = gen_new_label();
          gen_set_rm(s, rm);
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
              };
              TCGLabel *over = gen_new_label();
              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
              t1 = tcg_temp_new_i64();
              /* NaN-box f[rs1] */
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, FRM);                                        \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, FRM);                                        \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, FRM);                                        \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
          gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
      gen_helper_gvec_3_ptr *fn;
      TCGLabel *over = gen_new_label();
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 +    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
      static gen_helper_gvec_3_ptr * const fns[6][4] = {
          {
 --
 .36.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions
-From: Jim Shu <cwshu@andestech.com>
+From: eopXD <eop.chen@sifive.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+According to v-spec, tail agnostic behavior can be either kept as
-Fix it by propagating PMP permission to TLB page permission.
+undisturbed or set elements' bits to all 1s. To distinguish the
 difference of tail policies, QEMU should be able to simulate the tail
 agnostic behavior as "set tail elements' bits to all 1s".
-PMP permission checking also use MMU-style API to change TLB permission
+There are multiple possibility for agnostic elements according to
-and size.
+v-spec. The main intent of this patch-set tries to add option that
 can distinguish between tail policies. Setting agnostic elements to
 all 1s allows QEMU to express this.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+This is the first commit regarding the optional tail agnostic
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+behavior. Follow-up commits will add this optional behavior
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+for all rvv instructions.
 Signed-off-by: eop Chen <eop.chen@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/cpu.h                      |   2 +
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+ target/riscv/internals.h                |   5 +-
- target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
+ target/riscv/cpu_helper.c               |   2 +
-files changed, 125 insertions(+), 43 deletions(-)
+ target/riscv/translate.c                |   2 +
  target/riscv/vector_helper.c            | 296 +++++++++++++-----------
  target/riscv/insn_trans/trans_rvv.c.inc |   3 +-
 files changed, 178 insertions(+), 132 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/pmp.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     target_ulong val);
+     bool ext_zve32f;
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+     bool ext_zve64f;
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+     bool ext_zmmul;
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
++    bool rvv_ta_all_1s;
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode);
+     uint32_t mvendorid;
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+     uint64_t marchid;
-                          target_ulong *tlb_size);
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, XL, 20, 2)
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+ /* If PointerMasking should be applied */
- void pmp_update_rule_nums(CPURISCVState *env);
+ FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
- uint32_t pmp_get_num_rules(CPURISCVState *env);
+ FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
++FIELD(TB_FLAGS, VTA, 24, 1)
- #endif
+ #ifdef TARGET_RISCV32
  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 diff --git a/target/riscv/internals.h b/target/riscv/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/internals.h
 +++ b/target/riscv/internals.h
@@ -XXX,XX +XXX,XX @@
  /* share data between vector helpers and decode code */
  FIELD(VDATA, VM, 0, 1)
  FIELD(VDATA, LMUL, 1, 3)
 -FIELD(VDATA, NF, 4, 4)
 -FIELD(VDATA, WD, 4, 1)
 +FIELD(VDATA, VTA, 4, 1)
 +FIELD(VDATA, NF, 5, 4)
 +FIELD(VDATA, WD, 5, 1)
  /* float point classify helpers */
  target_ulong fclass_h(uint64_t frs1);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-     env->load_res = -1;
+         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                      FIELD_EX64(env->vtype, VTYPE, VLMUL));
          flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
 +        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
 +                    FIELD_EX64(env->vtype, VTYPE, VTA));
      } else {
          flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
      }
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
       */
      int8_t lmul;
      uint8_t sew;
 +    uint8_t vta;
      target_ulong vstart;
      bool vl_eq_vlmax;
      uint8_t ntemp;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
      ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
      ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
 +    ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
      ctx->vstart = env->vstart;
      ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
      ctx->misa_mxl_max = env->misa_mxl_max;
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline int32_t vext_lmul(uint32_t desc)
      return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
  }
-+/*
++static inline uint32_t vext_vta(uint32_t desc)
 + * get_physical_address_pmp - check PMP permission for this physical address
 + *
 + * Match the PMP region and check permission for this physical address and it's
 + * TLB page. Returns 0 if the permission checking was successful
 + *
 + * @env: CPURISCVState
 + * @prot: The returned protection attributes
 + * @tlb_size: TLB page size containing addr. It could be modified after PMP
 + *            permission checking. NULL if not set TLB page for addr.
 + * @addr: The physical address to be checked permission
 + * @access_type: The type of MMU access
 + * @mode: Indicates current privilege level.
 + */
 +static int get_physical_address_pmp(CPURISCVState *env, int *prot,
 +                                    target_ulong *tlb_size, hwaddr addr,
 +                                    int size, MMUAccessType access_type,
 +                                    int mode)
 +{
-+    pmp_priv_t pmp_priv;
++    return FIELD_EX32(simd_data(desc), VDATA, VTA);
 +    target_ulong tlb_size_pmp = 0;
 +
 +    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
 +        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +        return TRANSLATE_SUCCESS;
 +    }
 +
 +    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 +                            mode)) {
 +        *prot = 0;
 +        return TRANSLATE_PMP_FAIL;
 +    }
 +
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
 +    }
 +
 +    return TRANSLATE_SUCCESS;
 +}
 +
- /* get_physical_address - get the physical address for this virtual address
+ /*
   * Get the maximum number of elements can be operated.
   *
-  * Do a page table walk to obtain the physical address corresponding to a
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
-@@ -XXX,XX +XXX,XX @@ restart:
+     return scale < 0 ? vlenb >> -scale : vlenb << scale;
              pte_addr = base + idx * ptesize;
          }
 -        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 -            1 << MMU_DATA_LOAD, PRV_S)) {
 +        int pmp_prot;
 +        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
 +                                               sizeof(target_ulong),
 +                                               MMU_DATA_LOAD, PRV_S);
 +        if (pmp_ret != TRANSLATE_SUCCESS) {
              return TRANSLATE_PMP_FAIL;
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
  #ifndef CONFIG_USER_ONLY
      vaddr im_address;
      hwaddr pa = 0;
 -    int prot, prot2;
 +    int prot, prot2, prot_pmp;
      bool pmp_violation = false;
      bool first_stage_error = true;
      bool two_stage_lookup = false;
      int ret = TRANSLATE_FAIL;
      int mode = mmu_idx;
 -    target_ulong tlb_size = 0;
 +    /* default TLB page size */
 +    target_ulong tlb_size = TARGET_PAGE_SIZE;
      env->guest_phys_fault_addr = 0;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
              prot &= prot2;
 -            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -                (ret == TRANSLATE_SUCCESS) &&
 -                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -                ret = TRANSLATE_PMP_FAIL;
 +            if (ret == TRANSLATE_SUCCESS) {
 +                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                               size, access_type, mode);
 +                prot &= prot_pmp;
              }
              if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        "%s address=%" VADDR_PRIx " ret %d physical "
                        TARGET_FMT_plx " prot %d\n",
                        __func__, address, ret, pa, prot);
 -    }
 -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -        (ret == TRANSLATE_SUCCESS) &&
 -        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -        ret = TRANSLATE_PMP_FAIL;
 +        if (ret == TRANSLATE_SUCCESS) {
 +            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                           size, access_type, mode);
 +            prot &= prot_pmp;
 +        }
      }
 +
      if (ret == TRANSLATE_PMP_FAIL) {
          pmp_violation = true;
      }
      if (ret == TRANSLATE_SUCCESS) {
 -        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
 -            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 -                         prot, mmu_idx, tlb_size);
 -        } else {
 -            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 -                         prot, mmu_idx, TARGET_PAGE_SIZE);
 -        }
 +        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 +                     prot, mmu_idx, tlb_size);
          return true;
      } else if (probe) {
          return false;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
      return result;
  }
 +/*
-+ * Check if the address has required RWX privs when no PMP entry is matched.
++ * Get number of total elements, including prestart, body and tail elements.
 + * Note that when LMUL < 1, the tail includes the elements past VLMAX that
 + * are held in the same vector register.
 + */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
++static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
++                                            uint32_t esz)
 +    target_ulong mode)
 +{
-+    bool ret;
++    uint32_t vlenb = simd_maxsz(desc);
-+
++    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
-+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
++    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
-+        /*
++                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
-+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
++    return (vlenb << emul) / esz;
 +         * or no PMP entry matches an M-Mode access, the access succeeds.
 +         */
 +        ret = true;
 +        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +    } else {
 +        /*
 +         * Other modes are not allowed to succeed if they don't * match a rule,
 +         * but there are rules. We've checked for no rule earlier in this
 +         * function.
 +         */
 +        ret = false;
 +        *allowed_privs = 0;
 +    }
 +
 +    return ret;
 +}
 +
+ static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
  /*
   * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
   * Check if the address has required RWX privs to complete desired operation
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
-     int i = 0;
+     return (addr & env->cur_pmmask) | env->cur_pmbase;
-     int ret = -1;
+@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
      int pmp_size = 0;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
+ }
-     if (size == 0) {
-@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
++/* set agnostic elements to 1s */
-          * check
++static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-          */
++                              uint32_t tot)
-         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
++{
--            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
++    if (is_agnostic == 0) {
-+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
++        /* policy undisturbed */
-             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
++        return;
--                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
++    }
-+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
++    if (tot - cnt == 0) {
-             }
++        return ;
++    }
--            if ((privs & allowed_privs) == privs) {
++    memset(base + cnt, -1, tot - cnt);
--                ret = 1;
++}
--                break;
++
--            } else {
+ static inline void vext_set_elem_mask(void *v0, int index,
--                ret = 0;
+                                       uint8_t value)
--                break;
+ {
--            }
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
-+            ret = ((privs & *allowed_privs) == privs);
-+            break;
+ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
-         }
+                        CPURISCVState *env, uint32_t desc,
 -                       opivv2_fn *fn)
 +                       opivv2_fn *fn, uint32_t esz)
  {
      uint32_t vm = vext_vm(desc);
      uint32_t vl = env->vl;
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +    uint32_t vta = vext_vta(desc);
      uint32_t i;
      for (i = env->vstart; i < vl; i++) {
@@ -XXX,XX +XXX,XX @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
          fn(vd, vs1, vs2, i);
      }
+     env->vstart = 0;
-     /* No rule matched */
++    /* set tail elements to 1s */
-     if (ret == -1) {
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
--
+ /* generate the helpers for OPIVV */
- /*
+-#define GEN_VEXT_VV(NAME)                                 \
-  * Handle a write to a pmpcfg CSP
++#define GEN_VEXT_VV(NAME, ESZ)                            \
-  */
+ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+                   void *vs2, CPURISCVState *env,          \
+                   uint32_t desc)                          \
-     return false;
+ {                                                         \
      do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
 -               do_##NAME);                                \
 +               do_##NAME, ESZ);                           \
  }
-+
-+/*
+-GEN_VEXT_VV(vadd_vv_b)
-+ * Convert PMP privilege to TLB page privilege.
+-GEN_VEXT_VV(vadd_vv_h)
-+ */
+-GEN_VEXT_VV(vadd_vv_w)
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+-GEN_VEXT_VV(vadd_vv_d)
-+{
+-GEN_VEXT_VV(vsub_vv_b)
-+    int prot = 0;
+-GEN_VEXT_VV(vsub_vv_h)
-+
+-GEN_VEXT_VV(vsub_vv_w)
-+    if (pmp_priv & PMP_READ) {
+-GEN_VEXT_VV(vsub_vv_d)
-+        prot |= PAGE_READ;
++GEN_VEXT_VV(vadd_vv_b, 1)
-+    }
++GEN_VEXT_VV(vadd_vv_h, 2)
-+    if (pmp_priv & PMP_WRITE) {
++GEN_VEXT_VV(vadd_vv_w, 4)
-+        prot |= PAGE_WRITE;
++GEN_VEXT_VV(vadd_vv_d, 8)
-+    }
++GEN_VEXT_VV(vsub_vv_b, 1)
-+    if (pmp_priv & PMP_EXEC) {
++GEN_VEXT_VV(vsub_vv_h, 2)
-+        prot |= PAGE_EXEC;
++GEN_VEXT_VV(vsub_vv_w, 4)
-+    }
++GEN_VEXT_VV(vsub_vv_d, 8)
-+
-+    return prot;
+ typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
-+}
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
  RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
  RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
  RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
 -GEN_VEXT_VV(vwaddu_vv_b)
 -GEN_VEXT_VV(vwaddu_vv_h)
 -GEN_VEXT_VV(vwaddu_vv_w)
 -GEN_VEXT_VV(vwsubu_vv_b)
 -GEN_VEXT_VV(vwsubu_vv_h)
 -GEN_VEXT_VV(vwsubu_vv_w)
 -GEN_VEXT_VV(vwadd_vv_b)
 -GEN_VEXT_VV(vwadd_vv_h)
 -GEN_VEXT_VV(vwadd_vv_w)
 -GEN_VEXT_VV(vwsub_vv_b)
 -GEN_VEXT_VV(vwsub_vv_h)
 -GEN_VEXT_VV(vwsub_vv_w)
 -GEN_VEXT_VV(vwaddu_wv_b)
 -GEN_VEXT_VV(vwaddu_wv_h)
 -GEN_VEXT_VV(vwaddu_wv_w)
 -GEN_VEXT_VV(vwsubu_wv_b)
 -GEN_VEXT_VV(vwsubu_wv_h)
 -GEN_VEXT_VV(vwsubu_wv_w)
 -GEN_VEXT_VV(vwadd_wv_b)
 -GEN_VEXT_VV(vwadd_wv_h)
 -GEN_VEXT_VV(vwadd_wv_w)
 -GEN_VEXT_VV(vwsub_wv_b)
 -GEN_VEXT_VV(vwsub_wv_h)
 -GEN_VEXT_VV(vwsub_wv_w)
 +GEN_VEXT_VV(vwaddu_vv_b, 2)
 +GEN_VEXT_VV(vwaddu_vv_h, 4)
 +GEN_VEXT_VV(vwaddu_vv_w, 8)
 +GEN_VEXT_VV(vwsubu_vv_b, 2)
 +GEN_VEXT_VV(vwsubu_vv_h, 4)
 +GEN_VEXT_VV(vwsubu_vv_w, 8)
 +GEN_VEXT_VV(vwadd_vv_b, 2)
 +GEN_VEXT_VV(vwadd_vv_h, 4)
 +GEN_VEXT_VV(vwadd_vv_w, 8)
 +GEN_VEXT_VV(vwsub_vv_b, 2)
 +GEN_VEXT_VV(vwsub_vv_h, 4)
 +GEN_VEXT_VV(vwsub_vv_w, 8)
 +GEN_VEXT_VV(vwaddu_wv_b, 2)
 +GEN_VEXT_VV(vwaddu_wv_h, 4)
 +GEN_VEXT_VV(vwaddu_wv_w, 8)
 +GEN_VEXT_VV(vwsubu_wv_b, 2)
 +GEN_VEXT_VV(vwsubu_wv_h, 4)
 +GEN_VEXT_VV(vwsubu_wv_w, 8)
 +GEN_VEXT_VV(vwadd_wv_b, 2)
 +GEN_VEXT_VV(vwadd_wv_h, 4)
 +GEN_VEXT_VV(vwadd_wv_w, 8)
 +GEN_VEXT_VV(vwsub_wv_b, 2)
 +GEN_VEXT_VV(vwsub_wv_h, 4)
 +GEN_VEXT_VV(vwsub_wv_w, 8)
  RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
  RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
  RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
  RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
  RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
 -GEN_VEXT_VV(vand_vv_b)
 -GEN_VEXT_VV(vand_vv_h)
 -GEN_VEXT_VV(vand_vv_w)
 -GEN_VEXT_VV(vand_vv_d)
 -GEN_VEXT_VV(vor_vv_b)
 -GEN_VEXT_VV(vor_vv_h)
 -GEN_VEXT_VV(vor_vv_w)
 -GEN_VEXT_VV(vor_vv_d)
 -GEN_VEXT_VV(vxor_vv_b)
 -GEN_VEXT_VV(vxor_vv_h)
 -GEN_VEXT_VV(vxor_vv_w)
 -GEN_VEXT_VV(vxor_vv_d)
 +GEN_VEXT_VV(vand_vv_b, 1)
 +GEN_VEXT_VV(vand_vv_h, 2)
 +GEN_VEXT_VV(vand_vv_w, 4)
 +GEN_VEXT_VV(vand_vv_d, 8)
 +GEN_VEXT_VV(vor_vv_b, 1)
 +GEN_VEXT_VV(vor_vv_h, 2)
 +GEN_VEXT_VV(vor_vv_w, 4)
 +GEN_VEXT_VV(vor_vv_d, 8)
 +GEN_VEXT_VV(vxor_vv_b, 1)
 +GEN_VEXT_VV(vxor_vv_h, 2)
 +GEN_VEXT_VV(vxor_vv_w, 4)
 +GEN_VEXT_VV(vxor_vv_d, 8)
  RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
  RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
  RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
  RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
  RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
 -GEN_VEXT_VV(vminu_vv_b)
 -GEN_VEXT_VV(vminu_vv_h)
 -GEN_VEXT_VV(vminu_vv_w)
 -GEN_VEXT_VV(vminu_vv_d)
 -GEN_VEXT_VV(vmin_vv_b)
 -GEN_VEXT_VV(vmin_vv_h)
 -GEN_VEXT_VV(vmin_vv_w)
 -GEN_VEXT_VV(vmin_vv_d)
 -GEN_VEXT_VV(vmaxu_vv_b)
 -GEN_VEXT_VV(vmaxu_vv_h)
 -GEN_VEXT_VV(vmaxu_vv_w)
 -GEN_VEXT_VV(vmaxu_vv_d)
 -GEN_VEXT_VV(vmax_vv_b)
 -GEN_VEXT_VV(vmax_vv_h)
 -GEN_VEXT_VV(vmax_vv_w)
 -GEN_VEXT_VV(vmax_vv_d)
 +GEN_VEXT_VV(vminu_vv_b, 1)
 +GEN_VEXT_VV(vminu_vv_h, 2)
 +GEN_VEXT_VV(vminu_vv_w, 4)
 +GEN_VEXT_VV(vminu_vv_d, 8)
 +GEN_VEXT_VV(vmin_vv_b, 1)
 +GEN_VEXT_VV(vmin_vv_h, 2)
 +GEN_VEXT_VV(vmin_vv_w, 4)
 +GEN_VEXT_VV(vmin_vv_d, 8)
 +GEN_VEXT_VV(vmaxu_vv_b, 1)
 +GEN_VEXT_VV(vmaxu_vv_h, 2)
 +GEN_VEXT_VV(vmaxu_vv_w, 4)
 +GEN_VEXT_VV(vmaxu_vv_d, 8)
 +GEN_VEXT_VV(vmax_vv_b, 1)
 +GEN_VEXT_VV(vmax_vv_h, 2)
 +GEN_VEXT_VV(vmax_vv_w, 4)
 +GEN_VEXT_VV(vmax_vv_d, 8)
  RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
  RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
  RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
  RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
  RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
 -GEN_VEXT_VV(vmul_vv_b)
 -GEN_VEXT_VV(vmul_vv_h)
 -GEN_VEXT_VV(vmul_vv_w)
 -GEN_VEXT_VV(vmul_vv_d)
 +GEN_VEXT_VV(vmul_vv_b, 1)
 +GEN_VEXT_VV(vmul_vv_h, 2)
 +GEN_VEXT_VV(vmul_vv_w, 4)
 +GEN_VEXT_VV(vmul_vv_d, 8)
  static int8_t do_mulh_b(int8_t s2, int8_t s1)
  {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
  RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
  RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
  RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
 -GEN_VEXT_VV(vmulh_vv_b)
 -GEN_VEXT_VV(vmulh_vv_h)
 -GEN_VEXT_VV(vmulh_vv_w)
 -GEN_VEXT_VV(vmulh_vv_d)
 -GEN_VEXT_VV(vmulhu_vv_b)
 -GEN_VEXT_VV(vmulhu_vv_h)
 -GEN_VEXT_VV(vmulhu_vv_w)
 -GEN_VEXT_VV(vmulhu_vv_d)
 -GEN_VEXT_VV(vmulhsu_vv_b)
 -GEN_VEXT_VV(vmulhsu_vv_h)
 -GEN_VEXT_VV(vmulhsu_vv_w)
 -GEN_VEXT_VV(vmulhsu_vv_d)
 +GEN_VEXT_VV(vmulh_vv_b, 1)
 +GEN_VEXT_VV(vmulh_vv_h, 2)
 +GEN_VEXT_VV(vmulh_vv_w, 4)
 +GEN_VEXT_VV(vmulh_vv_d, 8)
 +GEN_VEXT_VV(vmulhu_vv_b, 1)
 +GEN_VEXT_VV(vmulhu_vv_h, 2)
 +GEN_VEXT_VV(vmulhu_vv_w, 4)
 +GEN_VEXT_VV(vmulhu_vv_d, 8)
 +GEN_VEXT_VV(vmulhsu_vv_b, 1)
 +GEN_VEXT_VV(vmulhsu_vv_h, 2)
 +GEN_VEXT_VV(vmulhsu_vv_w, 4)
 +GEN_VEXT_VV(vmulhsu_vv_d, 8)
  RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
  RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
  RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
  RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
  RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
 -GEN_VEXT_VV(vdivu_vv_b)
 -GEN_VEXT_VV(vdivu_vv_h)
 -GEN_VEXT_VV(vdivu_vv_w)
 -GEN_VEXT_VV(vdivu_vv_d)
 -GEN_VEXT_VV(vdiv_vv_b)
 -GEN_VEXT_VV(vdiv_vv_h)
 -GEN_VEXT_VV(vdiv_vv_w)
 -GEN_VEXT_VV(vdiv_vv_d)
 -GEN_VEXT_VV(vremu_vv_b)
 -GEN_VEXT_VV(vremu_vv_h)
 -GEN_VEXT_VV(vremu_vv_w)
 -GEN_VEXT_VV(vremu_vv_d)
 -GEN_VEXT_VV(vrem_vv_b)
 -GEN_VEXT_VV(vrem_vv_h)
 -GEN_VEXT_VV(vrem_vv_w)
 -GEN_VEXT_VV(vrem_vv_d)
 +GEN_VEXT_VV(vdivu_vv_b, 1)
 +GEN_VEXT_VV(vdivu_vv_h, 2)
 +GEN_VEXT_VV(vdivu_vv_w, 4)
 +GEN_VEXT_VV(vdivu_vv_d, 8)
 +GEN_VEXT_VV(vdiv_vv_b, 1)
 +GEN_VEXT_VV(vdiv_vv_h, 2)
 +GEN_VEXT_VV(vdiv_vv_w, 4)
 +GEN_VEXT_VV(vdiv_vv_d, 8)
 +GEN_VEXT_VV(vremu_vv_b, 1)
 +GEN_VEXT_VV(vremu_vv_h, 2)
 +GEN_VEXT_VV(vremu_vv_w, 4)
 +GEN_VEXT_VV(vremu_vv_d, 8)
 +GEN_VEXT_VV(vrem_vv_b, 1)
 +GEN_VEXT_VV(vrem_vv_h, 2)
 +GEN_VEXT_VV(vrem_vv_w, 4)
 +GEN_VEXT_VV(vrem_vv_d, 8)
  RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
  RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
  RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
  RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
  RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
 -GEN_VEXT_VV(vwmul_vv_b)
 -GEN_VEXT_VV(vwmul_vv_h)
 -GEN_VEXT_VV(vwmul_vv_w)
 -GEN_VEXT_VV(vwmulu_vv_b)
 -GEN_VEXT_VV(vwmulu_vv_h)
 -GEN_VEXT_VV(vwmulu_vv_w)
 -GEN_VEXT_VV(vwmulsu_vv_b)
 -GEN_VEXT_VV(vwmulsu_vv_h)
 -GEN_VEXT_VV(vwmulsu_vv_w)
 +GEN_VEXT_VV(vwmul_vv_b, 2)
 +GEN_VEXT_VV(vwmul_vv_h, 4)
 +GEN_VEXT_VV(vwmul_vv_w, 8)
 +GEN_VEXT_VV(vwmulu_vv_b, 2)
 +GEN_VEXT_VV(vwmulu_vv_h, 4)
 +GEN_VEXT_VV(vwmulu_vv_w, 8)
 +GEN_VEXT_VV(vwmulsu_vv_b, 2)
 +GEN_VEXT_VV(vwmulsu_vv_h, 4)
 +GEN_VEXT_VV(vwmulsu_vv_w, 8)
  RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
  RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
  RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
  RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
  RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
 -GEN_VEXT_VV(vmacc_vv_b)
 -GEN_VEXT_VV(vmacc_vv_h)
 -GEN_VEXT_VV(vmacc_vv_w)
 -GEN_VEXT_VV(vmacc_vv_d)
 -GEN_VEXT_VV(vnmsac_vv_b)
 -GEN_VEXT_VV(vnmsac_vv_h)
 -GEN_VEXT_VV(vnmsac_vv_w)
 -GEN_VEXT_VV(vnmsac_vv_d)
 -GEN_VEXT_VV(vmadd_vv_b)
 -GEN_VEXT_VV(vmadd_vv_h)
 -GEN_VEXT_VV(vmadd_vv_w)
 -GEN_VEXT_VV(vmadd_vv_d)
 -GEN_VEXT_VV(vnmsub_vv_b)
 -GEN_VEXT_VV(vnmsub_vv_h)
 -GEN_VEXT_VV(vnmsub_vv_w)
 -GEN_VEXT_VV(vnmsub_vv_d)
 +GEN_VEXT_VV(vmacc_vv_b, 1)
 +GEN_VEXT_VV(vmacc_vv_h, 2)
 +GEN_VEXT_VV(vmacc_vv_w, 4)
 +GEN_VEXT_VV(vmacc_vv_d, 8)
 +GEN_VEXT_VV(vnmsac_vv_b, 1)
 +GEN_VEXT_VV(vnmsac_vv_h, 2)
 +GEN_VEXT_VV(vnmsac_vv_w, 4)
 +GEN_VEXT_VV(vnmsac_vv_d, 8)
 +GEN_VEXT_VV(vmadd_vv_b, 1)
 +GEN_VEXT_VV(vmadd_vv_h, 2)
 +GEN_VEXT_VV(vmadd_vv_w, 4)
 +GEN_VEXT_VV(vmadd_vv_d, 8)
 +GEN_VEXT_VV(vnmsub_vv_b, 1)
 +GEN_VEXT_VV(vnmsub_vv_h, 2)
 +GEN_VEXT_VV(vnmsub_vv_w, 4)
 +GEN_VEXT_VV(vnmsub_vv_d, 8)
  #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
  static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
  RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
  RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
  RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
 -GEN_VEXT_VV(vwmaccu_vv_b)
 -GEN_VEXT_VV(vwmaccu_vv_h)
 -GEN_VEXT_VV(vwmaccu_vv_w)
 -GEN_VEXT_VV(vwmacc_vv_b)
 -GEN_VEXT_VV(vwmacc_vv_h)
 -GEN_VEXT_VV(vwmacc_vv_w)
 -GEN_VEXT_VV(vwmaccsu_vv_b)
 -GEN_VEXT_VV(vwmaccsu_vv_h)
 -GEN_VEXT_VV(vwmaccsu_vv_w)
 +GEN_VEXT_VV(vwmaccu_vv_b, 2)
 +GEN_VEXT_VV(vwmaccu_vv_h, 4)
 +GEN_VEXT_VV(vwmaccu_vv_w, 8)
 +GEN_VEXT_VV(vwmacc_vv_b, 2)
 +GEN_VEXT_VV(vwmacc_vv_h, 4)
 +GEN_VEXT_VV(vwmacc_vv_w, 8)
 +GEN_VEXT_VV(vwmaccsu_vv_b, 2)
 +GEN_VEXT_VV(vwmaccsu_vv_h, 4)
 +GEN_VEXT_VV(vwmaccsu_vv_w, 8)
  RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
  RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 -    if (a->vm && s->vl_eq_vlmax) {
 +    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
          gvec_fn(s->sew, vreg_ofs(s, a->rd),
                  vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
                  MAXSZ(s), MAXSZ(s));
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
                             cpu_env, s->cfg_ptr->vlen / 8,
 --
-.30.1
+.36.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 13/25] target/riscv: rvv: Add tail agnostic for vector load / store instructions
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+Destination register of unit-stride mask load and store instructions are
-further compressed instruction decoding. However, prior to this change,
+always written with a tail-agnostic policy.
-we did not raise an illegal instruction exception, if decode_RV32_64C()
-fails to decode the instruction. This means that we skipped illegal
+A vector segment load / store instruction may contain fractional lmul
-compressed instructions instead of raising an illegal instruction
+with nf * lmul > 1. The rest of the elements in the last register should
-exception.
+be treated as tail elements.
-Instead of patching decode_RV32_64C(), we can just remove it,
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-as it is dead code since f330433b363 anyway.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ target/riscv/translate.c                |  2 +
-file changed, 1 insertion(+), 178 deletions(-)
+ target/riscv/vector_helper.c            | 60 +++++++++++++++++++++++++
  target/riscv/insn_trans/trans_rvv.c.inc |  6 +++
 files changed, 68 insertions(+)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     CPUState *cs;
+     int8_t lmul;
- } DisasContext;
+     uint8_t sew;
+     uint8_t vta;
--#ifdef TARGET_RISCV64
++    bool cfg_vta_all_1s;
--/* convert riscv funct3 to qemu memop for load/store */
+     target_ulong vstart;
--static const int tcg_memop_lookup[8] = {
+     bool vl_eq_vlmax;
--    [0 ... 7] = -1,
+     uint8_t ntemp;
--    [0] = MO_SB,
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--    [1] = MO_TESW,
+     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
--    [2] = MO_TESL,
+     ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
--    [3] = MO_TEQ,
+     ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
--    [4] = MO_UB,
++    ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
--    [5] = MO_TEUW,
+     ctx->vstart = env->vstart;
--    [6] = MO_TEUL,
+     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
--};
+     ctx->misa_mxl_max = env->misa_mxl_max;
--#endif
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
--
+index XXXXXXX..XXXXXXX 100644
- #ifdef TARGET_RISCV64
+--- a/target/riscv/vector_helper.c
- #define CASE_OP_32_64(X) case X: case glue(X, W)
++++ b/target/riscv/vector_helper.c
- #else
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+     uint32_t i, k;
-     ctx->base.is_jmp = DISAS_NORETURN;
+     uint32_t nf = vext_nf(desc);
- }
+     uint32_t max_elems = vext_max_elems(desc, log2_esz);
++    uint32_t esz = 1 << log2_esz;
--#ifdef TARGET_RISCV64
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
--static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
++    uint32_t vta = vext_vta(desc);
--        target_long imm)
--{
+     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
--    TCGv t0 = tcg_temp_new();
+         if (!vm && !vext_elem_mask(v0, i)) {
--    TCGv t1 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
--    gen_get_gpr(t0, rs1);
+         }
--    tcg_gen_addi_tl(t0, t0, imm);
+     }
--    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
+     env->vstart = 0;
--
++    /* set tail elements to 1s */
--    if (memop < 0) {
++    for (k = 0; k < nf; ++k) {
--        gen_exception_illegal(ctx);
++        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
--        return;
++                          (k * max_elems + max_elems) * esz);
--    }
++    }
--
++    if (nf * max_elems % total_elems != 0) {
--    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
++        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
--    gen_set_gpr(rd, t1);
++        uint32_t registers_used =
--    tcg_temp_free(t0);
++            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
--    tcg_temp_free(t1);
++        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
--}
++                          registers_used * vlenb);
--
++    }
--static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+ }
--        target_long imm)
--{
+ #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)                        \
--    TCGv t0 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
--    TCGv dat = tcg_temp_new();
+     uint32_t i, k;
--    gen_get_gpr(t0, rs1);
+     uint32_t nf = vext_nf(desc);
--    tcg_gen_addi_tl(t0, t0, imm);
+     uint32_t max_elems = vext_max_elems(desc, log2_esz);
--    gen_get_gpr(dat, rs2);
++    uint32_t esz = 1 << log2_esz;
--    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
--
++    uint32_t vta = vext_vta(desc);
--    if (memop < 0) {
--        gen_exception_illegal(ctx);
+     /* load bytes from guest memory */
--        return;
+     for (i = env->vstart; i < evl; i++, env->vstart++) {
--    }
+@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
--
+         }
--    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+     }
--    tcg_temp_free(t0);
+     env->vstart = 0;
--    tcg_temp_free(dat);
++    /* set tail elements to 1s */
--}
++    for (k = 0; k < nf; ++k) {
--#endif
++        vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz,
--
++                          (k * max_elems + max_elems) * esz);
- #ifndef CONFIG_USER_ONLY
++    }
- /* The states of mstatus_fs are:
++    if (nf * max_elems % total_elems != 0) {
-  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
++        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
-@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
++        uint32_t registers_used =
- static inline void mark_fs_dirty(DisasContext *ctx) { }
++            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- #endif
++        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
++                          registers_used * vlenb);
--#if !defined(TARGET_RISCV64)
++    }
--static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
+ }
--        int rs1, target_long imm)
--{
+ /*
--    TCGv t0;
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
--
+     uint32_t nf = vext_nf(desc);
--    if (ctx->mstatus_fs == 0) {
+     uint32_t vm = vext_vm(desc);
--        gen_exception_illegal(ctx);
+     uint32_t max_elems = vext_max_elems(desc, log2_esz);
--        return;
++    uint32_t esz = 1 << log2_esz;
--    }
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
--
++    uint32_t vta = vext_vta(desc);
--    t0 = tcg_temp_new();
--    gen_get_gpr(t0, rs1);
+     /* load bytes from guest memory */
--    tcg_gen_addi_tl(t0, t0, imm);
+     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
--
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
--    switch (opc) {
+         }
--    case OPC_RISC_FLW:
+     }
--        if (!has_ext(ctx, RVF)) {
+     env->vstart = 0;
--            goto do_illegal;
++    /* set tail elements to 1s */
--        }
++    for (k = 0; k < nf; ++k) {
--        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
++        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
--        /* RISC-V requires NaN-boxing of narrower width floating point values */
++                          (k * max_elems + max_elems) * esz);
--        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
++    }
--        break;
++    if (nf * max_elems % total_elems != 0) {
--    case OPC_RISC_FLD:
++        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
--        if (!has_ext(ctx, RVD)) {
++        uint32_t registers_used =
--            goto do_illegal;
++            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
--        }
++        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
--        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
++                          registers_used * vlenb);
--        break;
++    }
--    do_illegal:
+ }
--    default:
--        gen_exception_illegal(ctx);
+ #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN)                  \
--        break;
+@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
--    }
+     uint32_t nf = vext_nf(desc);
--    tcg_temp_free(t0);
+     uint32_t vm = vext_vm(desc);
--
+     uint32_t max_elems = vext_max_elems(desc, log2_esz);
--    mark_fs_dirty(ctx);
++    uint32_t esz = 1 << log2_esz;
--}
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
--
++    uint32_t vta = vext_vta(desc);
--static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
+     target_ulong addr, offset, remain;
--        int rs2, target_long imm)
--{
+     /* probe every access*/
--    TCGv t0;
+@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
--
+         }
--    if (ctx->mstatus_fs == 0) {
+     }
--        gen_exception_illegal(ctx);
+     env->vstart = 0;
--        return;
++    /* set tail elements to 1s */
--    }
++    for (k = 0; k < nf; ++k) {
--
++        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
--    t0 = tcg_temp_new();
++                          (k * max_elems + max_elems) * esz);
--    gen_get_gpr(t0, rs1);
++    }
--    tcg_gen_addi_tl(t0, t0, imm);
++    if (nf * max_elems % total_elems != 0) {
--
++        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
--    switch (opc) {
++        uint32_t registers_used =
--    case OPC_RISC_FSW:
++            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
--        if (!has_ext(ctx, RVF)) {
++        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
--            goto do_illegal;
++                          registers_used * vlenb);
--        }
++    }
--        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
+ }
--        break;
--    case OPC_RISC_FSD:
+ #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN)               \
--        if (!has_ext(ctx, RVD)) {
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
--            goto do_illegal;
+index XXXXXXX..XXXXXXX 100644
--        }
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
--        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
--        break;
+@@ -XXX,XX +XXX,XX @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
--    do_illegal:
+     data = FIELD_DP32(data, VDATA, VM, a->vm);
--    default:
+     data = FIELD_DP32(data, VDATA, LMUL, emul);
--        gen_exception_illegal(ctx);
+     data = FIELD_DP32(data, VDATA, NF, a->nf);
--        break;
++    data = FIELD_DP32(data, VDATA, VTA, s->vta);
--    }
+     return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
--
+ }
--    tcg_temp_free(t0);
--}
+@@ -XXX,XX +XXX,XX @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
--#endif
+     /* EMUL = 1, NFIELDS = 1 */
--
+     data = FIELD_DP32(data, VDATA, LMUL, 0);
- static void gen_set_rm(DisasContext *ctx, int rm)
+     data = FIELD_DP32(data, VDATA, NF, 1);
- {
++    /* Mask destination register are always tail-agnostic */
-     TCGv_i32 t0;
++    data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
+     return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
-     tcg_temp_free_i32(t0);
+ }
- }
+@@ -XXX,XX +XXX,XX @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
--static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
+     data = FIELD_DP32(data, VDATA, VM, a->vm);
--{
+     data = FIELD_DP32(data, VDATA, LMUL, emul);
--    uint8_t funct3 = extract16(opcode, 13, 3);
+     data = FIELD_DP32(data, VDATA, NF, a->nf);
--    uint8_t rd_rs2 = GET_C_RS2S(opcode);
++    data = FIELD_DP32(data, VDATA, VTA, s->vta);
--    uint8_t rs1s = GET_C_RS1S(opcode);
+     return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
--
+ }
--    switch (funct3) {
--    case 3:
+@@ -XXX,XX +XXX,XX @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
--#if defined(TARGET_RISCV64)
+     data = FIELD_DP32(data, VDATA, VM, a->vm);
--        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
+     data = FIELD_DP32(data, VDATA, LMUL, emul);
--        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+     data = FIELD_DP32(data, VDATA, NF, a->nf);
--                 GET_C_LD_IMM(opcode));
++    data = FIELD_DP32(data, VDATA, VTA, s->vta);
--#else
+     return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
--        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
+ }
--        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
--                    GET_C_LW_IMM(opcode));
+@@ -XXX,XX +XXX,XX @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
--#endif
+     data = FIELD_DP32(data, VDATA, VM, a->vm);
--        break;
+     data = FIELD_DP32(data, VDATA, LMUL, emul);
--    case 7:
+     data = FIELD_DP32(data, VDATA, NF, a->nf);
--#if defined(TARGET_RISCV64)
++    data = FIELD_DP32(data, VDATA, VTA, s->vta);
--        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
+     return ldff_trans(a->rd, a->rs1, data, fn, s);
--        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+ }
--                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.36.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-The previous implementation was broken in many ways:
+`vmadc` and `vmsbc` produces a mask value, they always operate with
- - Used mideleg instead of hideleg to mask accesses
+a tail agnostic policy.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/internals.h                |   5 +-
-file changed, 34 insertions(+), 34 deletions(-)
+ target/riscv/vector_helper.c            | 314 +++++++++++++-----------
  target/riscv/insn_trans/trans_rvv.c.inc |  13 +-
 files changed, 190 insertions(+), 142 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/internals.h b/target/riscv/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/internals.h
-+++ b/target/riscv/csr.c
++++ b/target/riscv/internals.h
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@
-     return write_mstatus(env, CSR_MSTATUS, newval);
+ FIELD(VDATA, VM, 0, 1)
  FIELD(VDATA, LMUL, 1, 3)
  FIELD(VDATA, VTA, 4, 1)
 -FIELD(VDATA, NF, 5, 4)
 -FIELD(VDATA, WD, 5, 1)
 +FIELD(VDATA, VTA_ALL_1S, 5, 1)
 +FIELD(VDATA, NF, 6, 4)
 +FIELD(VDATA, WD, 6, 1)
  /* float point classify helpers */
  target_ulong fclass_h(uint64_t frs1);
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_vta(uint32_t desc)
      return FIELD_EX32(simd_data(desc), VDATA, VTA);
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static inline uint32_t vext_vta_all_1s(uint32_t desc)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
 +    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 +    return 0;
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+ /*
   * Get the maximum number of elements can be operated.
   *
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
  static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
                         CPURISCVState *env, uint32_t desc,
 -                       opivx2_fn fn)
 +                       opivx2_fn fn, uint32_t esz)
  {
-     if (riscv_cpu_virt_enabled(env)) {
+     uint32_t vm = vext_vm(desc);
--        /* Tell the guest the VS bits, shifted to the S bit locations */
+     uint32_t vl = env->vl;
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-+        read_vsie(env, CSR_VSIE, val);
++    uint32_t vta = vext_vta(desc);
-     } else {
+     uint32_t i;
-         *val = env->mie & env->mideleg;
      for (i = env->vstart; i < vl; i++) {
@@ -XXX,XX +XXX,XX @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
          fn(vd, s1, vs2, i);
      }
-     return 0;
+     env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
  }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+ /* generate the helpers for OPIVX */
-+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+-#define GEN_VEXT_VX(NAME)                                 \
- {
++#define GEN_VEXT_VX(NAME, ESZ)                            \
--    target_ulong newval;
+ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
-+    /* Shift the S bits to their VS bit location in mie */
+                   void *vs2, CPURISCVState *env,          \
-+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                   uint32_t desc)                          \
-+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+ {                                                         \
-+    return write_mie(env, CSR_MIE, newval);
+     do_vext_vx(vd, v0, s1, vs2, env, desc,                \
-+}
+-               do_##NAME);                                \
+-}
-+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+-
-+{
+-GEN_VEXT_VX(vadd_vx_b)
-     if (riscv_cpu_virt_enabled(env)) {
+-GEN_VEXT_VX(vadd_vx_h)
--        /* Shift the guests S bits to VS */
+-GEN_VEXT_VX(vadd_vx_w)
--        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+-GEN_VEXT_VX(vadd_vx_d)
--                 ((val << 1) & VS_MODE_INTERRUPTS);
+-GEN_VEXT_VX(vsub_vx_b)
-+        write_vsie(env, CSR_VSIE, val);
+-GEN_VEXT_VX(vsub_vx_h)
-     } else {
+-GEN_VEXT_VX(vsub_vx_w)
--        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+-GEN_VEXT_VX(vsub_vx_d)
-+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+-GEN_VEXT_VX(vrsub_vx_b)
-+                              (val & S_MODE_INTERRUPTS);
+-GEN_VEXT_VX(vrsub_vx_h)
-+        write_mie(env, CSR_MIE, newval);
+-GEN_VEXT_VX(vrsub_vx_w)
-     }
+-GEN_VEXT_VX(vrsub_vx_d)
++               do_##NAME, ESZ);                           \
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
  static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +                    target_ulong new_value, target_ulong write_mask)
 +{
 +    /* Shift the S bits to their VS bit location in mip */
 +    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
- static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
++GEN_VEXT_VX(vadd_vx_b, 1)
-                    target_ulong new_value, target_ulong write_mask)
++GEN_VEXT_VX(vadd_vx_h, 2)
 +GEN_VEXT_VX(vadd_vx_w, 4)
 +GEN_VEXT_VX(vadd_vx_d, 8)
 +GEN_VEXT_VX(vsub_vx_b, 1)
 +GEN_VEXT_VX(vsub_vx_h, 2)
 +GEN_VEXT_VX(vsub_vx_w, 4)
 +GEN_VEXT_VX(vsub_vx_d, 8)
 +GEN_VEXT_VX(vrsub_vx_b, 1)
 +GEN_VEXT_VX(vrsub_vx_h, 2)
 +GEN_VEXT_VX(vrsub_vx_w, 4)
 +GEN_VEXT_VX(vrsub_vx_d, 8)
  void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
  {
-     int ret;
+@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
+ RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
-     if (riscv_cpu_virt_enabled(env)) {
+ RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
--        /* Shift the new values to line up with the VS bits */
+ RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
--        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
+-GEN_VEXT_VX(vwaddu_vx_b)
--                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
+-GEN_VEXT_VX(vwaddu_vx_h)
--        ret &= vsip_writable_mask;
+-GEN_VEXT_VX(vwaddu_vx_w)
--        ret >>= 1;
+-GEN_VEXT_VX(vwsubu_vx_b)
-+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
+-GEN_VEXT_VX(vwsubu_vx_h)
-     } else {
+-GEN_VEXT_VX(vwsubu_vx_w)
-         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+-GEN_VEXT_VX(vwadd_vx_b)
-                       write_mask & env->mideleg & sip_writable_mask);
+-GEN_VEXT_VX(vwadd_vx_h)
-@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
+-GEN_VEXT_VX(vwadd_vx_w)
-     return 0;
+-GEN_VEXT_VX(vwsub_vx_b)
 -GEN_VEXT_VX(vwsub_vx_h)
 -GEN_VEXT_VX(vwsub_vx_w)
 -GEN_VEXT_VX(vwaddu_wx_b)
 -GEN_VEXT_VX(vwaddu_wx_h)
 -GEN_VEXT_VX(vwaddu_wx_w)
 -GEN_VEXT_VX(vwsubu_wx_b)
 -GEN_VEXT_VX(vwsubu_wx_h)
 -GEN_VEXT_VX(vwsubu_wx_w)
 -GEN_VEXT_VX(vwadd_wx_b)
 -GEN_VEXT_VX(vwadd_wx_h)
 -GEN_VEXT_VX(vwadd_wx_w)
 -GEN_VEXT_VX(vwsub_wx_b)
 -GEN_VEXT_VX(vwsub_wx_h)
 -GEN_VEXT_VX(vwsub_wx_w)
 +GEN_VEXT_VX(vwaddu_vx_b, 2)
 +GEN_VEXT_VX(vwaddu_vx_h, 4)
 +GEN_VEXT_VX(vwaddu_vx_w, 8)
 +GEN_VEXT_VX(vwsubu_vx_b, 2)
 +GEN_VEXT_VX(vwsubu_vx_h, 4)
 +GEN_VEXT_VX(vwsubu_vx_w, 8)
 +GEN_VEXT_VX(vwadd_vx_b, 2)
 +GEN_VEXT_VX(vwadd_vx_h, 4)
 +GEN_VEXT_VX(vwadd_vx_w, 8)
 +GEN_VEXT_VX(vwsub_vx_b, 2)
 +GEN_VEXT_VX(vwsub_vx_h, 4)
 +GEN_VEXT_VX(vwsub_vx_w, 8)
 +GEN_VEXT_VX(vwaddu_wx_b, 2)
 +GEN_VEXT_VX(vwaddu_wx_h, 4)
 +GEN_VEXT_VX(vwaddu_wx_w, 8)
 +GEN_VEXT_VX(vwsubu_wx_b, 2)
 +GEN_VEXT_VX(vwsubu_wx_h, 4)
 +GEN_VEXT_VX(vwsubu_wx_w, 8)
 +GEN_VEXT_VX(vwadd_wx_b, 2)
 +GEN_VEXT_VX(vwadd_wx_h, 4)
 +GEN_VEXT_VX(vwadd_wx_w, 8)
 +GEN_VEXT_VX(vwsub_wx_b, 2)
 +GEN_VEXT_VX(vwsub_wx_h, 4)
 +GEN_VEXT_VX(vwsub_wx_w, 8)
  /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
  #define DO_VADC(N, M, C) (N + M + C)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
                    CPURISCVState *env, uint32_t desc)          \
  {                                                             \
      uint32_t vl = env->vl;                                    \
 +    uint32_t esz = sizeof(ETYPE);                             \
 +    uint32_t total_elems =                                    \
 +        vext_get_total_elems(env, desc, esz);                 \
 +    uint32_t vta = vext_vta(desc);                            \
      uint32_t i;                                               \
                                                                \
      for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
          *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry);         \
      }                                                         \
      env->vstart = 0;                                          \
 +    /* set tail elements to 1s */                             \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);  \
  }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t,  H1, DO_VADC)
--                    target_ulong new_value, target_ulong write_mask)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,        \
--{
+                   CPURISCVState *env, uint32_t desc)                     \
--    int ret = rmw_mip(env, 0, ret_value, new_value,
+ {                                                                        \
--                      write_mask & env->mideleg & vsip_writable_mask);
+     uint32_t vl = env->vl;                                               \
--    return ret;
++    uint32_t esz = sizeof(ETYPE);                                        \
--}
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);         \
--
++    uint32_t vta = vext_vta(desc);                                       \
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+     uint32_t i;                                                          \
--{
+                                                                          \
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
+     for (i = env->vstart; i < vl; i++) {                                 \
--    return 0;
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,        \
--}
+         *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
--
+     }                                                                    \
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+     env->vstart = 0;                                          \
--{
++    /* set tail elements to 1s */                                        \
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);             \
--    return write_mie(env, CSR_MIE, newval);
+ }
--}
--
+ GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t,  H1, DO_VADC)
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
- {
+ {                                                             \
-     *val = env->vstvec;
+     uint32_t vl = env->vl;                                    \
      uint32_t vm = vext_vm(desc);                              \
 +    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
 +    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
      uint32_t i;                                               \
                                                                \
      for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
          vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry));      \
      }                                                         \
      env->vstart = 0;                                          \
 +    /* mask destination register are always tail-agnostic */  \
 +    /* set tail elements to 1s */                             \
 +    if (vta_all_1s) {                                         \
 +        for (; i < total_elems; i++) {                        \
 +            vext_set_elem_mask(vd, i, 1);                     \
 +        }                                                     \
 +    }                                                         \
  }
  GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t,  H1, DO_MADC)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,          \
  {                                                               \
      uint32_t vl = env->vl;                                      \
      uint32_t vm = vext_vm(desc);                                \
 +    uint32_t total_elems = env_archcpu(env)->cfg.vlen;          \
 +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                \
      uint32_t i;                                                 \
                                                                  \
      for (i = env->vstart; i < vl; i++) {                        \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,          \
                  DO_OP(s2, (ETYPE)(target_long)s1, carry));      \
      }                                                           \
      env->vstart = 0;                                            \
 +    /* mask destination register are always tail-agnostic */    \
 +    /* set tail elements to 1s */                               \
 +    if (vta_all_1s) {                                           \
 +        for (; i < total_elems; i++) {                          \
 +            vext_set_elem_mask(vd, i, 1);                       \
 +        }                                                       \
 +    }                                                           \
  }
  GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t,  H1, DO_MADC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
  RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
  RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
  RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
 -GEN_VEXT_VX(vand_vx_b)
 -GEN_VEXT_VX(vand_vx_h)
 -GEN_VEXT_VX(vand_vx_w)
 -GEN_VEXT_VX(vand_vx_d)
 -GEN_VEXT_VX(vor_vx_b)
 -GEN_VEXT_VX(vor_vx_h)
 -GEN_VEXT_VX(vor_vx_w)
 -GEN_VEXT_VX(vor_vx_d)
 -GEN_VEXT_VX(vxor_vx_b)
 -GEN_VEXT_VX(vxor_vx_h)
 -GEN_VEXT_VX(vxor_vx_w)
 -GEN_VEXT_VX(vxor_vx_d)
 +GEN_VEXT_VX(vand_vx_b, 1)
 +GEN_VEXT_VX(vand_vx_h, 2)
 +GEN_VEXT_VX(vand_vx_w, 4)
 +GEN_VEXT_VX(vand_vx_d, 8)
 +GEN_VEXT_VX(vor_vx_b, 1)
 +GEN_VEXT_VX(vor_vx_h, 2)
 +GEN_VEXT_VX(vor_vx_w, 4)
 +GEN_VEXT_VX(vor_vx_d, 8)
 +GEN_VEXT_VX(vxor_vx_b, 1)
 +GEN_VEXT_VX(vxor_vx_h, 2)
 +GEN_VEXT_VX(vxor_vx_w, 4)
 +GEN_VEXT_VX(vxor_vx_d, 8)
  /* Vector Single-Width Bit Shift Instructions */
  #define DO_SLL(N, M)  (N << (M))
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
  RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
  RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
  RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
 -GEN_VEXT_VX(vminu_vx_b)
 -GEN_VEXT_VX(vminu_vx_h)
 -GEN_VEXT_VX(vminu_vx_w)
 -GEN_VEXT_VX(vminu_vx_d)
 -GEN_VEXT_VX(vmin_vx_b)
 -GEN_VEXT_VX(vmin_vx_h)
 -GEN_VEXT_VX(vmin_vx_w)
 -GEN_VEXT_VX(vmin_vx_d)
 -GEN_VEXT_VX(vmaxu_vx_b)
 -GEN_VEXT_VX(vmaxu_vx_h)
 -GEN_VEXT_VX(vmaxu_vx_w)
 -GEN_VEXT_VX(vmaxu_vx_d)
 -GEN_VEXT_VX(vmax_vx_b)
 -GEN_VEXT_VX(vmax_vx_h)
 -GEN_VEXT_VX(vmax_vx_w)
 -GEN_VEXT_VX(vmax_vx_d)
 +GEN_VEXT_VX(vminu_vx_b, 1)
 +GEN_VEXT_VX(vminu_vx_h, 2)
 +GEN_VEXT_VX(vminu_vx_w, 4)
 +GEN_VEXT_VX(vminu_vx_d, 8)
 +GEN_VEXT_VX(vmin_vx_b, 1)
 +GEN_VEXT_VX(vmin_vx_h, 2)
 +GEN_VEXT_VX(vmin_vx_w, 4)
 +GEN_VEXT_VX(vmin_vx_d, 8)
 +GEN_VEXT_VX(vmaxu_vx_b, 1)
 +GEN_VEXT_VX(vmaxu_vx_h, 2)
 +GEN_VEXT_VX(vmaxu_vx_w, 4)
 +GEN_VEXT_VX(vmaxu_vx_d, 8)
 +GEN_VEXT_VX(vmax_vx_b, 1)
 +GEN_VEXT_VX(vmax_vx_h, 2)
 +GEN_VEXT_VX(vmax_vx_w, 4)
 +GEN_VEXT_VX(vmax_vx_d, 8)
  /* Vector Single-Width Integer Multiply Instructions */
  #define DO_MUL(N, M) (N * M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
  RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
  RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
  RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
 -GEN_VEXT_VX(vmul_vx_b)
 -GEN_VEXT_VX(vmul_vx_h)
 -GEN_VEXT_VX(vmul_vx_w)
 -GEN_VEXT_VX(vmul_vx_d)
 -GEN_VEXT_VX(vmulh_vx_b)
 -GEN_VEXT_VX(vmulh_vx_h)
 -GEN_VEXT_VX(vmulh_vx_w)
 -GEN_VEXT_VX(vmulh_vx_d)
 -GEN_VEXT_VX(vmulhu_vx_b)
 -GEN_VEXT_VX(vmulhu_vx_h)
 -GEN_VEXT_VX(vmulhu_vx_w)
 -GEN_VEXT_VX(vmulhu_vx_d)
 -GEN_VEXT_VX(vmulhsu_vx_b)
 -GEN_VEXT_VX(vmulhsu_vx_h)
 -GEN_VEXT_VX(vmulhsu_vx_w)
 -GEN_VEXT_VX(vmulhsu_vx_d)
 +GEN_VEXT_VX(vmul_vx_b, 1)
 +GEN_VEXT_VX(vmul_vx_h, 2)
 +GEN_VEXT_VX(vmul_vx_w, 4)
 +GEN_VEXT_VX(vmul_vx_d, 8)
 +GEN_VEXT_VX(vmulh_vx_b, 1)
 +GEN_VEXT_VX(vmulh_vx_h, 2)
 +GEN_VEXT_VX(vmulh_vx_w, 4)
 +GEN_VEXT_VX(vmulh_vx_d, 8)
 +GEN_VEXT_VX(vmulhu_vx_b, 1)
 +GEN_VEXT_VX(vmulhu_vx_h, 2)
 +GEN_VEXT_VX(vmulhu_vx_w, 4)
 +GEN_VEXT_VX(vmulhu_vx_d, 8)
 +GEN_VEXT_VX(vmulhsu_vx_b, 1)
 +GEN_VEXT_VX(vmulhsu_vx_h, 2)
 +GEN_VEXT_VX(vmulhsu_vx_w, 4)
 +GEN_VEXT_VX(vmulhsu_vx_d, 8)
  /* Vector Integer Divide Instructions */
  #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
  RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
  RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
  RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
 -GEN_VEXT_VX(vdivu_vx_b)
 -GEN_VEXT_VX(vdivu_vx_h)
 -GEN_VEXT_VX(vdivu_vx_w)
 -GEN_VEXT_VX(vdivu_vx_d)
 -GEN_VEXT_VX(vdiv_vx_b)
 -GEN_VEXT_VX(vdiv_vx_h)
 -GEN_VEXT_VX(vdiv_vx_w)
 -GEN_VEXT_VX(vdiv_vx_d)
 -GEN_VEXT_VX(vremu_vx_b)
 -GEN_VEXT_VX(vremu_vx_h)
 -GEN_VEXT_VX(vremu_vx_w)
 -GEN_VEXT_VX(vremu_vx_d)
 -GEN_VEXT_VX(vrem_vx_b)
 -GEN_VEXT_VX(vrem_vx_h)
 -GEN_VEXT_VX(vrem_vx_w)
 -GEN_VEXT_VX(vrem_vx_d)
 +GEN_VEXT_VX(vdivu_vx_b, 1)
 +GEN_VEXT_VX(vdivu_vx_h, 2)
 +GEN_VEXT_VX(vdivu_vx_w, 4)
 +GEN_VEXT_VX(vdivu_vx_d, 8)
 +GEN_VEXT_VX(vdiv_vx_b, 1)
 +GEN_VEXT_VX(vdiv_vx_h, 2)
 +GEN_VEXT_VX(vdiv_vx_w, 4)
 +GEN_VEXT_VX(vdiv_vx_d, 8)
 +GEN_VEXT_VX(vremu_vx_b, 1)
 +GEN_VEXT_VX(vremu_vx_h, 2)
 +GEN_VEXT_VX(vremu_vx_w, 4)
 +GEN_VEXT_VX(vremu_vx_d, 8)
 +GEN_VEXT_VX(vrem_vx_b, 1)
 +GEN_VEXT_VX(vrem_vx_h, 2)
 +GEN_VEXT_VX(vrem_vx_w, 4)
 +GEN_VEXT_VX(vrem_vx_d, 8)
  /* Vector Widening Integer Multiply Instructions */
  RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
  RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
  RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
  RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
 -GEN_VEXT_VX(vwmul_vx_b)
 -GEN_VEXT_VX(vwmul_vx_h)
 -GEN_VEXT_VX(vwmul_vx_w)
 -GEN_VEXT_VX(vwmulu_vx_b)
 -GEN_VEXT_VX(vwmulu_vx_h)
 -GEN_VEXT_VX(vwmulu_vx_w)
 -GEN_VEXT_VX(vwmulsu_vx_b)
 -GEN_VEXT_VX(vwmulsu_vx_h)
 -GEN_VEXT_VX(vwmulsu_vx_w)
 +GEN_VEXT_VX(vwmul_vx_b, 2)
 +GEN_VEXT_VX(vwmul_vx_h, 4)
 +GEN_VEXT_VX(vwmul_vx_w, 8)
 +GEN_VEXT_VX(vwmulu_vx_b, 2)
 +GEN_VEXT_VX(vwmulu_vx_h, 4)
 +GEN_VEXT_VX(vwmulu_vx_w, 8)
 +GEN_VEXT_VX(vwmulsu_vx_b, 2)
 +GEN_VEXT_VX(vwmulsu_vx_h, 4)
 +GEN_VEXT_VX(vwmulsu_vx_w, 8)
  /* Vector Single-Width Integer Multiply-Add Instructions */
  #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
  RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
  RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
  RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
 -GEN_VEXT_VX(vmacc_vx_b)
 -GEN_VEXT_VX(vmacc_vx_h)
 -GEN_VEXT_VX(vmacc_vx_w)
 -GEN_VEXT_VX(vmacc_vx_d)
 -GEN_VEXT_VX(vnmsac_vx_b)
 -GEN_VEXT_VX(vnmsac_vx_h)
 -GEN_VEXT_VX(vnmsac_vx_w)
 -GEN_VEXT_VX(vnmsac_vx_d)
 -GEN_VEXT_VX(vmadd_vx_b)
 -GEN_VEXT_VX(vmadd_vx_h)
 -GEN_VEXT_VX(vmadd_vx_w)
 -GEN_VEXT_VX(vmadd_vx_d)
 -GEN_VEXT_VX(vnmsub_vx_b)
 -GEN_VEXT_VX(vnmsub_vx_h)
 -GEN_VEXT_VX(vnmsub_vx_w)
 -GEN_VEXT_VX(vnmsub_vx_d)
 +GEN_VEXT_VX(vmacc_vx_b, 1)
 +GEN_VEXT_VX(vmacc_vx_h, 2)
 +GEN_VEXT_VX(vmacc_vx_w, 4)
 +GEN_VEXT_VX(vmacc_vx_d, 8)
 +GEN_VEXT_VX(vnmsac_vx_b, 1)
 +GEN_VEXT_VX(vnmsac_vx_h, 2)
 +GEN_VEXT_VX(vnmsac_vx_w, 4)
 +GEN_VEXT_VX(vnmsac_vx_d, 8)
 +GEN_VEXT_VX(vmadd_vx_b, 1)
 +GEN_VEXT_VX(vmadd_vx_h, 2)
 +GEN_VEXT_VX(vmadd_vx_w, 4)
 +GEN_VEXT_VX(vmadd_vx_d, 8)
 +GEN_VEXT_VX(vnmsub_vx_b, 1)
 +GEN_VEXT_VX(vnmsub_vx_h, 2)
 +GEN_VEXT_VX(vnmsub_vx_w, 4)
 +GEN_VEXT_VX(vnmsub_vx_d, 8)
  /* Vector Widening Integer Multiply-Add Instructions */
  RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
  RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
  RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
  RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
 -GEN_VEXT_VX(vwmaccu_vx_b)
 -GEN_VEXT_VX(vwmaccu_vx_h)
 -GEN_VEXT_VX(vwmaccu_vx_w)
 -GEN_VEXT_VX(vwmacc_vx_b)
 -GEN_VEXT_VX(vwmacc_vx_h)
 -GEN_VEXT_VX(vwmacc_vx_w)
 -GEN_VEXT_VX(vwmaccsu_vx_b)
 -GEN_VEXT_VX(vwmaccsu_vx_h)
 -GEN_VEXT_VX(vwmaccsu_vx_w)
 -GEN_VEXT_VX(vwmaccus_vx_b)
 -GEN_VEXT_VX(vwmaccus_vx_h)
 -GEN_VEXT_VX(vwmaccus_vx_w)
 +GEN_VEXT_VX(vwmaccu_vx_b, 2)
 +GEN_VEXT_VX(vwmaccu_vx_h, 4)
 +GEN_VEXT_VX(vwmaccu_vx_w, 8)
 +GEN_VEXT_VX(vwmacc_vx_b, 2)
 +GEN_VEXT_VX(vwmacc_vx_h, 4)
 +GEN_VEXT_VX(vwmacc_vx_w, 8)
 +GEN_VEXT_VX(vwmaccsu_vx_b, 2)
 +GEN_VEXT_VX(vwmaccsu_vx_h, 4)
 +GEN_VEXT_VX(vwmaccsu_vx_w, 8)
 +GEN_VEXT_VX(vwmaccus_vx_b, 2)
 +GEN_VEXT_VX(vwmaccus_vx_h, 4)
 +GEN_VEXT_VX(vwmaccus_vx_w, 8)
  /* Vector Integer Merge and Move Instructions */
  #define GEN_VEXT_VMV_VV(NAME, ETYPE, H)                              \
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      data = FIELD_DP32(data, VDATA, VM, vm);
      data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +    data = FIELD_DP32(data, VDATA, VTA, s->vta);
 +    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
      desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
                                        s->cfg_ptr->vlen / 8, data));
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
          return false;
      }
 -    if (a->vm && s->vl_eq_vlmax) {
 +    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
          TCGv_i64 src1 = tcg_temp_new_i64();
          tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN));
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
      data = FIELD_DP32(data, VDATA, VM, vm);
      data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +    data = FIELD_DP32(data, VDATA, VTA, s->vta);
 +    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
      desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
                                        s->cfg_ptr->vlen / 8, data));
@@ -XXX,XX +XXX,XX @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
          return false;
      }
 -    if (a->vm && s->vl_eq_vlmax) {
 +    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
          gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                  extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
          mark_vs_dirty(s);
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1),
                             vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1),
                             vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
 +        data =                                                     \
 +            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs1),                    \
                             vreg_ofs(s, a->rs2), cpu_env,           \
 --
-.30.1
+.36.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
-From: Alexander Wagner <alexander.wagner@ulal.de>
+From: eopXD <yueh.ting.chen@gmail.com>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-the newest received byte. The rx_level variable is added to allow the use of
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-the existing OpenTitan driver libraries.
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
+Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ target/riscv/vector_helper.c            | 11 +++++++++++
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+ target/riscv/insn_trans/trans_rvv.c.inc |  3 ++-
-files changed, 22 insertions(+), 5 deletions(-)
+files changed, 13 insertions(+), 1 deletion(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
+--- a/target/riscv/vector_helper.c
-+++ b/include/hw/char/ibex_uart.h
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,                          \
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
+ {                                                                         \
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
+     uint32_t vm = vext_vm(desc);                                          \
- REG32(FIFO_STATUS, 0x20)
+     uint32_t vl = env->vl;                                                \
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
++    uint32_t esz = sizeof(TS1);                                           \
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
- REG32(OVRD, 0x24)
++    uint32_t vta = vext_vta(desc);                                        \
- REG32(VAL, 0x28)
+     uint32_t i;                                                           \
- REG32(TIMEOUT_CTRL, 0x2c)
+                                                                           \
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
+     for (i = env->vstart; i < vl; i++) {                                  \
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,                          \
-     uint32_t tx_level;
+         *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK);                        \
+     }                                                                     \
-+    uint32_t rx_level;
+     env->vstart = 0;                                                      \
-+
++    /* set tail elements to 1s */                                         \
-     QEMUTimer *fifo_trigger_handle;
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
-     uint64_t char_tx_time;
+ }
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
+ GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t,  uint8_t, H1, H1, DO_SLL, 0x7)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,      \
  {                                                           \
      uint32_t vm = vext_vm(desc);                            \
      uint32_t vl = env->vl;                                  \
 +    uint32_t esz = sizeof(TD);                              \
 +    uint32_t total_elems =                                  \
 +        vext_get_total_elems(env, desc, esz);               \
 +    uint32_t vta = vext_vta(desc);                          \
      uint32_t i;                                             \
                                                              \
      for (i = env->vstart; i < vl; i++) {                    \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,      \
          *((TD *)vd + HD(i)) = OP(s2, s1 & MASK);            \
      }                                                       \
      env->vstart = 0;                                        \
 +    /* set tail elements to 1s */                           \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);\
  }
  GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/ibex_uart.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/char/ibex_uart.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
+@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
- {
+         return false;
      IbexUartState *s = opaque;
 -    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
 +           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
          return 1;
      }
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
+-    if (a->vm && s->vl_eq_vlmax) {
++    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
-     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
+         TCGv_i32 src1 = tcg_temp_new_i32();
-     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
-+    /* The RXFULL is set after receiving a single byte
+         tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
-+     * as the FIFO buffers are not yet implemented.
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-+     */
+                                                                    \
-+    s->uart_status |= R_STATUS_RXFULL_MASK;
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-+    s->rx_level += 1;
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
-     if (size > rx_fifo_level) {
+         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
+                            vreg_ofs(s, a->rs1),                    \
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
+                            vreg_ofs(s, a->rs2), cpu_env,           \
      s->uart_timeout_ctrl = 0x00000000;
      s->tx_level = 0;
 +    s->rx_level = 0;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
          break;
      case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_FIFO_STATUS:
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
 --
-.30.1
+.36.1

-New patch
+[PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
+From: eopXD <yueh.ting.chen@gmail.com>
+Compares write mask registers, and so always operate under a tail-
+agnostic policy.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-9@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 18 ++++++++++++++++++
+file changed, 18 insertions(+)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
+ {                                                             \
+     uint32_t vm = vext_vm(desc);                              \
+     uint32_t vl = env->vl;                                    \
++    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
++    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
+     uint32_t i;                                               \
+                                                               \
+     for (i = env->vstart; i < vl; i++) {                      \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
+         vext_set_elem_mask(vd, i, DO_OP(s2, s1));             \
+     }                                                         \
+     env->vstart = 0;                                          \
++    /* mask destination register are always tail-agnostic */  \
++    /* set tail elements to 1s */                             \
++    if (vta_all_1s) {                                         \
++        for (; i < total_elems; i++) {                        \
++            vext_set_elem_mask(vd, i, 1);                     \
++        }                                                     \
++    }                                                         \
+ }
+ GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t,  H1, DO_MSEQ)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,   \
+ {                                                                   \
+     uint32_t vm = vext_vm(desc);                                    \
+     uint32_t vl = env->vl;                                          \
++    uint32_t total_elems = env_archcpu(env)->cfg.vlen;              \
++    uint32_t vta_all_1s = vext_vta_all_1s(desc);                    \
+     uint32_t i;                                                     \
+                                                                     \
+     for (i = env->vstart; i < vl; i++) {                            \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,   \
+                 DO_OP(s2, (ETYPE)(target_long)s1));                 \
+     }                                                               \
+     env->vstart = 0;                                                \
++    /* mask destination register are always tail-agnostic */        \
++    /* set tail elements to 1s */                                   \
++    if (vta_all_1s) {                                               \
++        for (; i < total_elems; i++) {                              \
++            vext_set_elem_mask(vd, i, 1);                           \
++        }                                                           \
++    }                                                               \
+ }
+ GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t,  H1, DO_MSEQ)
+--
+.36.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
-From: Bin Meng <bin.meng@windriver.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-This adds the documentation to describe what is supported for the
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht>
 Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ target/riscv/vector_helper.c            | 20 ++++++++++++++++++++
- docs/system/target-riscv.rst               |  1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++----
-files changed, 90 insertions(+)
+files changed, 28 insertions(+), 4 deletions(-)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
 +Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
 +=============================================================
 +
 +Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
 +SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
 +
 +For more details about Microchip PolarFire SoC, please see:
 +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
 +
 +The Icicle Kit board information can be found here:
 +https://www.microsemi.com/existing-parts/parts/152514
 +
 +Supported devices
 +-----------------
 +
 +The ``microchip-icicle-kit`` machine supports the following devices:
 +
 + * 1 E51 core
 + * 4 U54 cores
 + * Core Level Interruptor (CLINT)
 + * Platform-Level Interrupt Controller (PLIC)
 + * L2 Loosely Integrated Memory (L2-LIM)
 + * DDR memory controller
 + * 5 MMUARTs
 + * 1 DMA controller
 + * 2 GEM Ethernet controllers
 + * 1 SDHC storage controller
 +
 +Boot options
 +------------
 +
 +The ``microchip-icicle-kit`` machine can start using the standard -bios
 +functionality for loading its BIOS image, aka Hart Software Services (HSS_).
 +HSS loads the second stage bootloader U-Boot from an SD card. It does not
 +support direct kernel loading via the -kernel option. One has to load kernel
 +from U-Boot.
 +
 +The memory is set to 1537 MiB by default which is the minimum required high
 +memory size by HSS. A sanity check on ram size is performed in the machine
 +init routine to prompt user to increase the RAM size to > 1537 MiB when less
 +than 1537 MiB ram is detected.
 +
 +Boot the machine
 +----------------
 +
 +HSS 2020.12 release is tested at the time of writing. To build an HSS image
 +that can be booted by the ``microchip-icicle-kit`` machine, type the following
 +in the HSS source tree:
 +
 +.. code-block:: bash
 +
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ cp boards/mpfs-icicle-kit-es/def_config .config
 +  $ make BOARD=mpfs-icicle-kit-es
 +
 +Download the official SD card image released by Microchip and prepare it for
 +QEMU usage:
 +
 +.. code-block:: bash
 +
 +  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
 +
 +Then we can boot the machine by:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
 +      -bios path/to/hss.bin -sd path/to/sdcard.img \
 +      -nic user,model=cadence_gem \
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
 +      -serial chardev:serial1
 +
 +With above command line, current terminal session will be used for the first
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
 +  $ minicom -D unix\#serial1.sock
 +
 +HSS output is on the first serial port (stdio) and U-Boot outputs on the
 +second serial port. U-Boot will automatically load the Linux kernel from
 +the SD card image.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-riscv.rst
+--- a/target/riscv/vector_helper.c
-+++ b/docs/system/target-riscv.rst
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env,           \
- .. toctree::
+                   uint32_t desc)                                     \
-    :maxdepth: 1
+ {                                                                    \
+     uint32_t vl = env->vl;                                           \
-+   riscv/microchip-icicle-kit
++    uint32_t esz = sizeof(ETYPE);                                    \
-    riscv/sifive_u
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
++    uint32_t vta = vext_vta(desc);                                   \
- RISC-V CPU features
+     uint32_t i;                                                      \
                                                                       \
      for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env,           \
          *((ETYPE *)vd + H(i)) = s1;                                  \
      }                                                                \
      env->vstart = 0;                                                 \
 +    /* set tail elements to 1s */                                    \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
  }
  GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env,         \
                    uint32_t desc)                                     \
  {                                                                    \
      uint32_t vl = env->vl;                                           \
 +    uint32_t esz = sizeof(ETYPE);                                    \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
 +    uint32_t vta = vext_vta(desc);                                   \
      uint32_t i;                                                      \
                                                                       \
      for (i = env->vstart; i < vl; i++) {                             \
          *((ETYPE *)vd + H(i)) = (ETYPE)s1;                           \
      }                                                                \
      env->vstart = 0;                                                 \
 +    /* set tail elements to 1s */                                    \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
  }
  GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,          \
                    CPURISCVState *env, uint32_t desc)                 \
  {                                                                    \
      uint32_t vl = env->vl;                                           \
 +    uint32_t esz = sizeof(ETYPE);                                    \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
 +    uint32_t vta = vext_vta(desc);                                   \
      uint32_t i;                                                      \
                                                                       \
      for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,          \
          *((ETYPE *)vd + H(i)) = *(vt + H(i));                        \
      }                                                                \
      env->vstart = 0;                                                 \
 +    /* set tail elements to 1s */                                    \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
  }
  GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,               \
                    void *vs2, CPURISCVState *env, uint32_t desc)      \
  {                                                                    \
      uint32_t vl = env->vl;                                           \
 +    uint32_t esz = sizeof(ETYPE);                                    \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
 +    uint32_t vta = vext_vta(desc);                                   \
      uint32_t i;                                                      \
                                                                       \
      for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,               \
          *((ETYPE *)vd + H(i)) = d;                                   \
      }                                                                \
      env->vstart = 0;                                                 \
 +    /* set tail elements to 1s */                                    \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
  }
  GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t,  H1)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
          vext_check_isa_ill(s) &&
          /* vmv.v.v has rs2 = 0 and vm = 1 */
          vext_check_sss(s, a->rd, a->rs1, 0, 1)) {
 -        if (s->vl_eq_vlmax) {
 +        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
              tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
                               vreg_ofs(s, a->rs1),
                               MAXSZ(s), MAXSZ(s));
          } else {
              uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);
              static gen_helper_gvec_2_ptr * const fns[4] = {
                  gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
                  gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          s1 = get_gpr(s, a->rs1, EXT_SIGN);
 -        if (s->vl_eq_vlmax) {
 +        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
              tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
                                  MAXSZ(s), MAXSZ(s), s1);
          } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
              TCGv_i64 s1_i64 = tcg_temp_new_i64();
              TCGv_ptr dest = tcg_temp_new_ptr();
              uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);
              static gen_helper_vmv_vx * const fns[4] = {
                  gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
                  gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
          /* vmv.v.i has rs2 = 0 and vm = 1 */
          vext_check_ss(s, a->rd, 0, 1)) {
          int64_t simm = sextract64(a->rs1, 0, 5);
 -        if (s->vl_eq_vlmax) {
 +        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
              tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
                                   MAXSZ(s), MAXSZ(s), simm);
              mark_vs_dirty(s);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
              TCGv_i64 s1;
              TCGv_ptr dest;
              uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);
              static gen_helper_vmv_vx * const fns[4] = {
                  gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
                  gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
          TCGv_i64 t1;
 -        if (s->vl_eq_vlmax) {
 +        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
              t1 = tcg_temp_new_i64();
              /* NaN-box f[rs1] */
              do_nanbox(s, t1, cpu_fpr[a->rs1]);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
              TCGv_ptr dest;
              TCGv_i32 desc;
              uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
 +            data = FIELD_DP32(data, VDATA, VTA, s->vta);
              static gen_helper_vmv_vx * const fns[3] = {
                  gen_helper_vmv_v_x_h,
                  gen_helper_vmv_v_x_w,
 --
-.30.1
+.36.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL 18/25] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
-From: Jim Shu <cwshu@andestech.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-If PMP permission of any address has been changed by updating PMP entry,
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-flush all TLB pages to prevent from getting old permission.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-11@git.sr.ht>
 Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ target/riscv/vector_helper.c | 220 ++++++++++++++++++-----------------
-file changed, 4 insertions(+)
+file changed, 114 insertions(+), 106 deletions(-)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/target/riscv/vector_helper.c
-+++ b/target/riscv/pmp.c
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline void
- #include "qapi/error.h"
+ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
- #include "cpu.h"
+              CPURISCVState *env,
- #include "trace.h"
+              uint32_t desc,
-+#include "exec/exec-all.h"
+-             opivv2_rm_fn *fn)
++             opivv2_rm_fn *fn, uint32_t esz)
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
+ {
-     uint8_t val);
+     uint32_t vm = vext_vm(desc);
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
+     uint32_t vl = env->vl;
-         cfg_val = (val >> 8 * i)  & 0xff;
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
++    uint32_t vta = vext_vta(desc);
      switch (env->vxrm) {
      case 0: /* rnu */
@@ -XXX,XX +XXX,XX @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
                       env, vl, vm, 3, fn);
          break;
      }
-+
++    /* set tail elements to 1s */
-+    /* If PMP permission of any addr has been changed, flush TLB pages. */
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 +    tlb_flush(env_cpu(env));
  }
+ /* generate helpers for fixed point instructions with OPIVV format */
 -#define GEN_VEXT_VV_RM(NAME)                                    \
 +#define GEN_VEXT_VV_RM(NAME, ESZ)                               \
  void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,     \
                    CPURISCVState *env, uint32_t desc)            \
  {                                                               \
      vext_vv_rm_2(vd, v0, vs1, vs2, env, desc,                   \
 -                 do_##NAME);                                    \
 +                 do_##NAME, ESZ);                               \
  }
  static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
  RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
  RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
  RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
 -GEN_VEXT_VV_RM(vsaddu_vv_b)
 -GEN_VEXT_VV_RM(vsaddu_vv_h)
 -GEN_VEXT_VV_RM(vsaddu_vv_w)
 -GEN_VEXT_VV_RM(vsaddu_vv_d)
 +GEN_VEXT_VV_RM(vsaddu_vv_b, 1)
 +GEN_VEXT_VV_RM(vsaddu_vv_h, 2)
 +GEN_VEXT_VV_RM(vsaddu_vv_w, 4)
 +GEN_VEXT_VV_RM(vsaddu_vv_d, 8)
  typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
                            CPURISCVState *env, int vxrm);
@@ -XXX,XX +XXX,XX @@ static inline void
  vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
               CPURISCVState *env,
               uint32_t desc,
 -             opivx2_rm_fn *fn)
 +             opivx2_rm_fn *fn, uint32_t esz)
  {
      uint32_t vm = vext_vm(desc);
      uint32_t vl = env->vl;
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
 +    uint32_t vta = vext_vta(desc);
      switch (env->vxrm) {
      case 0: /* rnu */
@@ -XXX,XX +XXX,XX @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
                       env, vl, vm, 3, fn);
          break;
      }
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
  }
  /* generate helpers for fixed point instructions with OPIVX format */
 -#define GEN_VEXT_VX_RM(NAME)                              \
 +#define GEN_VEXT_VX_RM(NAME, ESZ)                         \
  void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
          void *vs2, CPURISCVState *env, uint32_t desc)     \
  {                                                         \
      vext_vx_rm_2(vd, v0, s1, vs2, env, desc,              \
 -                 do_##NAME);                              \
 +                 do_##NAME, ESZ);                         \
  }
  RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
  RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
  RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
  RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
 -GEN_VEXT_VX_RM(vsaddu_vx_b)
 -GEN_VEXT_VX_RM(vsaddu_vx_h)
 -GEN_VEXT_VX_RM(vsaddu_vx_w)
 -GEN_VEXT_VX_RM(vsaddu_vx_d)
 +GEN_VEXT_VX_RM(vsaddu_vx_b, 1)
 +GEN_VEXT_VX_RM(vsaddu_vx_h, 2)
 +GEN_VEXT_VX_RM(vsaddu_vx_w, 4)
 +GEN_VEXT_VX_RM(vsaddu_vx_d, 8)
  static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
  {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
  RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
  RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
  RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
 -GEN_VEXT_VV_RM(vsadd_vv_b)
 -GEN_VEXT_VV_RM(vsadd_vv_h)
 -GEN_VEXT_VV_RM(vsadd_vv_w)
 -GEN_VEXT_VV_RM(vsadd_vv_d)
 +GEN_VEXT_VV_RM(vsadd_vv_b, 1)
 +GEN_VEXT_VV_RM(vsadd_vv_h, 2)
 +GEN_VEXT_VV_RM(vsadd_vv_w, 4)
 +GEN_VEXT_VV_RM(vsadd_vv_d, 8)
  RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
  RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
  RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
  RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
 -GEN_VEXT_VX_RM(vsadd_vx_b)
 -GEN_VEXT_VX_RM(vsadd_vx_h)
 -GEN_VEXT_VX_RM(vsadd_vx_w)
 -GEN_VEXT_VX_RM(vsadd_vx_d)
 +GEN_VEXT_VX_RM(vsadd_vx_b, 1)
 +GEN_VEXT_VX_RM(vsadd_vx_h, 2)
 +GEN_VEXT_VX_RM(vsadd_vx_w, 4)
 +GEN_VEXT_VX_RM(vsadd_vx_d, 8)
  static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
  {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
  RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
  RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
  RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
 -GEN_VEXT_VV_RM(vssubu_vv_b)
 -GEN_VEXT_VV_RM(vssubu_vv_h)
 -GEN_VEXT_VV_RM(vssubu_vv_w)
 -GEN_VEXT_VV_RM(vssubu_vv_d)
 +GEN_VEXT_VV_RM(vssubu_vv_b, 1)
 +GEN_VEXT_VV_RM(vssubu_vv_h, 2)
 +GEN_VEXT_VV_RM(vssubu_vv_w, 4)
 +GEN_VEXT_VV_RM(vssubu_vv_d, 8)
  RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
  RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
  RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
  RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
 -GEN_VEXT_VX_RM(vssubu_vx_b)
 -GEN_VEXT_VX_RM(vssubu_vx_h)
 -GEN_VEXT_VX_RM(vssubu_vx_w)
 -GEN_VEXT_VX_RM(vssubu_vx_d)
 +GEN_VEXT_VX_RM(vssubu_vx_b, 1)
 +GEN_VEXT_VX_RM(vssubu_vx_h, 2)
 +GEN_VEXT_VX_RM(vssubu_vx_w, 4)
 +GEN_VEXT_VX_RM(vssubu_vx_d, 8)
  static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
  {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
  RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
  RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
  RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
 -GEN_VEXT_VV_RM(vssub_vv_b)
 -GEN_VEXT_VV_RM(vssub_vv_h)
 -GEN_VEXT_VV_RM(vssub_vv_w)
 -GEN_VEXT_VV_RM(vssub_vv_d)
 +GEN_VEXT_VV_RM(vssub_vv_b, 1)
 +GEN_VEXT_VV_RM(vssub_vv_h, 2)
 +GEN_VEXT_VV_RM(vssub_vv_w, 4)
 +GEN_VEXT_VV_RM(vssub_vv_d, 8)
  RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
  RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
  RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
  RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
 -GEN_VEXT_VX_RM(vssub_vx_b)
 -GEN_VEXT_VX_RM(vssub_vx_h)
 -GEN_VEXT_VX_RM(vssub_vx_w)
 -GEN_VEXT_VX_RM(vssub_vx_d)
 +GEN_VEXT_VX_RM(vssub_vx_b, 1)
 +GEN_VEXT_VX_RM(vssub_vx_h, 2)
 +GEN_VEXT_VX_RM(vssub_vx_w, 4)
 +GEN_VEXT_VX_RM(vssub_vx_d, 8)
  /* Vector Single-Width Averaging Add and Subtract */
  static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
  RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
  RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
  RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
 -GEN_VEXT_VV_RM(vaadd_vv_b)
 -GEN_VEXT_VV_RM(vaadd_vv_h)
 -GEN_VEXT_VV_RM(vaadd_vv_w)
 -GEN_VEXT_VV_RM(vaadd_vv_d)
 +GEN_VEXT_VV_RM(vaadd_vv_b, 1)
 +GEN_VEXT_VV_RM(vaadd_vv_h, 2)
 +GEN_VEXT_VV_RM(vaadd_vv_w, 4)
 +GEN_VEXT_VV_RM(vaadd_vv_d, 8)
  RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
  RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
  RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
  RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
 -GEN_VEXT_VX_RM(vaadd_vx_b)
 -GEN_VEXT_VX_RM(vaadd_vx_h)
 -GEN_VEXT_VX_RM(vaadd_vx_w)
 -GEN_VEXT_VX_RM(vaadd_vx_d)
 +GEN_VEXT_VX_RM(vaadd_vx_b, 1)
 +GEN_VEXT_VX_RM(vaadd_vx_h, 2)
 +GEN_VEXT_VX_RM(vaadd_vx_w, 4)
 +GEN_VEXT_VX_RM(vaadd_vx_d, 8)
  static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
                                 uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
  RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
  RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
  RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
 -GEN_VEXT_VV_RM(vaaddu_vv_b)
 -GEN_VEXT_VV_RM(vaaddu_vv_h)
 -GEN_VEXT_VV_RM(vaaddu_vv_w)
 -GEN_VEXT_VV_RM(vaaddu_vv_d)
 +GEN_VEXT_VV_RM(vaaddu_vv_b, 1)
 +GEN_VEXT_VV_RM(vaaddu_vv_h, 2)
 +GEN_VEXT_VV_RM(vaaddu_vv_w, 4)
 +GEN_VEXT_VV_RM(vaaddu_vv_d, 8)
  RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
  RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
  RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
  RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
 -GEN_VEXT_VX_RM(vaaddu_vx_b)
 -GEN_VEXT_VX_RM(vaaddu_vx_h)
 -GEN_VEXT_VX_RM(vaaddu_vx_w)
 -GEN_VEXT_VX_RM(vaaddu_vx_d)
 +GEN_VEXT_VX_RM(vaaddu_vx_b, 1)
 +GEN_VEXT_VX_RM(vaaddu_vx_h, 2)
 +GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
 +GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
  static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
  {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
  RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
  RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
  RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
 -GEN_VEXT_VV_RM(vasub_vv_b)
 -GEN_VEXT_VV_RM(vasub_vv_h)
 -GEN_VEXT_VV_RM(vasub_vv_w)
 -GEN_VEXT_VV_RM(vasub_vv_d)
 +GEN_VEXT_VV_RM(vasub_vv_b, 1)
 +GEN_VEXT_VV_RM(vasub_vv_h, 2)
 +GEN_VEXT_VV_RM(vasub_vv_w, 4)
 +GEN_VEXT_VV_RM(vasub_vv_d, 8)
  RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
  RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
  RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
  RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
 -GEN_VEXT_VX_RM(vasub_vx_b)
 -GEN_VEXT_VX_RM(vasub_vx_h)
 -GEN_VEXT_VX_RM(vasub_vx_w)
 -GEN_VEXT_VX_RM(vasub_vx_d)
 +GEN_VEXT_VX_RM(vasub_vx_b, 1)
 +GEN_VEXT_VX_RM(vasub_vx_h, 2)
 +GEN_VEXT_VX_RM(vasub_vx_w, 4)
 +GEN_VEXT_VX_RM(vasub_vx_d, 8)
  static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
                                 uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
  RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
  RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
  RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
 -GEN_VEXT_VV_RM(vasubu_vv_b)
 -GEN_VEXT_VV_RM(vasubu_vv_h)
 -GEN_VEXT_VV_RM(vasubu_vv_w)
 -GEN_VEXT_VV_RM(vasubu_vv_d)
 +GEN_VEXT_VV_RM(vasubu_vv_b, 1)
 +GEN_VEXT_VV_RM(vasubu_vv_h, 2)
 +GEN_VEXT_VV_RM(vasubu_vv_w, 4)
 +GEN_VEXT_VV_RM(vasubu_vv_d, 8)
  RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
  RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
  RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
  RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
 -GEN_VEXT_VX_RM(vasubu_vx_b)
 -GEN_VEXT_VX_RM(vasubu_vx_h)
 -GEN_VEXT_VX_RM(vasubu_vx_w)
 -GEN_VEXT_VX_RM(vasubu_vx_d)
 +GEN_VEXT_VX_RM(vasubu_vx_b, 1)
 +GEN_VEXT_VX_RM(vasubu_vx_h, 2)
 +GEN_VEXT_VX_RM(vasubu_vx_w, 4)
 +GEN_VEXT_VX_RM(vasubu_vx_d, 8)
  /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
  static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
  RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
  RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
  RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
 -GEN_VEXT_VV_RM(vsmul_vv_b)
 -GEN_VEXT_VV_RM(vsmul_vv_h)
 -GEN_VEXT_VV_RM(vsmul_vv_w)
 -GEN_VEXT_VV_RM(vsmul_vv_d)
 +GEN_VEXT_VV_RM(vsmul_vv_b, 1)
 +GEN_VEXT_VV_RM(vsmul_vv_h, 2)
 +GEN_VEXT_VV_RM(vsmul_vv_w, 4)
 +GEN_VEXT_VV_RM(vsmul_vv_d, 8)
  RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
  RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
  RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
  RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
 -GEN_VEXT_VX_RM(vsmul_vx_b)
 -GEN_VEXT_VX_RM(vsmul_vx_h)
 -GEN_VEXT_VX_RM(vsmul_vx_w)
 -GEN_VEXT_VX_RM(vsmul_vx_d)
 +GEN_VEXT_VX_RM(vsmul_vx_b, 1)
 +GEN_VEXT_VX_RM(vsmul_vx_h, 2)
 +GEN_VEXT_VX_RM(vsmul_vx_w, 4)
 +GEN_VEXT_VX_RM(vsmul_vx_d, 8)
  /* Vector Single-Width Scaling Shift Instructions */
  static inline uint8_t
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
  RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
  RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
  RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
 -GEN_VEXT_VV_RM(vssrl_vv_b)
 -GEN_VEXT_VV_RM(vssrl_vv_h)
 -GEN_VEXT_VV_RM(vssrl_vv_w)
 -GEN_VEXT_VV_RM(vssrl_vv_d)
 +GEN_VEXT_VV_RM(vssrl_vv_b, 1)
 +GEN_VEXT_VV_RM(vssrl_vv_h, 2)
 +GEN_VEXT_VV_RM(vssrl_vv_w, 4)
 +GEN_VEXT_VV_RM(vssrl_vv_d, 8)
  RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
  RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
  RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
  RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
 -GEN_VEXT_VX_RM(vssrl_vx_b)
 -GEN_VEXT_VX_RM(vssrl_vx_h)
 -GEN_VEXT_VX_RM(vssrl_vx_w)
 -GEN_VEXT_VX_RM(vssrl_vx_d)
 +GEN_VEXT_VX_RM(vssrl_vx_b, 1)
 +GEN_VEXT_VX_RM(vssrl_vx_h, 2)
 +GEN_VEXT_VX_RM(vssrl_vx_w, 4)
 +GEN_VEXT_VX_RM(vssrl_vx_d, 8)
  static inline int8_t
  vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
  RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
  RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
  RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
 -GEN_VEXT_VV_RM(vssra_vv_b)
 -GEN_VEXT_VV_RM(vssra_vv_h)
 -GEN_VEXT_VV_RM(vssra_vv_w)
 -GEN_VEXT_VV_RM(vssra_vv_d)
 +GEN_VEXT_VV_RM(vssra_vv_b, 1)
 +GEN_VEXT_VV_RM(vssra_vv_h, 2)
 +GEN_VEXT_VV_RM(vssra_vv_w, 4)
 +GEN_VEXT_VV_RM(vssra_vv_d, 8)
  RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
  RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
  RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
  RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
 -GEN_VEXT_VX_RM(vssra_vx_b)
 -GEN_VEXT_VX_RM(vssra_vx_h)
 -GEN_VEXT_VX_RM(vssra_vx_w)
 -GEN_VEXT_VX_RM(vssra_vx_d)
 +GEN_VEXT_VX_RM(vssra_vx_b, 1)
 +GEN_VEXT_VX_RM(vssra_vx_h, 2)
 +GEN_VEXT_VX_RM(vssra_vx_w, 4)
 +GEN_VEXT_VX_RM(vssra_vx_d, 8)
  /* Vector Narrowing Fixed-Point Clip Instructions */
  static inline int8_t
@@ -XXX,XX +XXX,XX @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
  RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
  RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
  RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
 -GEN_VEXT_VV_RM(vnclip_wv_b)
 -GEN_VEXT_VV_RM(vnclip_wv_h)
 -GEN_VEXT_VV_RM(vnclip_wv_w)
 +GEN_VEXT_VV_RM(vnclip_wv_b, 1)
 +GEN_VEXT_VV_RM(vnclip_wv_h, 2)
 +GEN_VEXT_VV_RM(vnclip_wv_w, 4)
  RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
  RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
  RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
 -GEN_VEXT_VX_RM(vnclip_wx_b)
 -GEN_VEXT_VX_RM(vnclip_wx_h)
 -GEN_VEXT_VX_RM(vnclip_wx_w)
 +GEN_VEXT_VX_RM(vnclip_wx_b, 1)
 +GEN_VEXT_VX_RM(vnclip_wx_h, 2)
 +GEN_VEXT_VX_RM(vnclip_wx_w, 4)
  static inline uint8_t
  vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -XXX,XX +XXX,XX @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
  RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
  RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
  RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
 -GEN_VEXT_VV_RM(vnclipu_wv_b)
 -GEN_VEXT_VV_RM(vnclipu_wv_h)
 -GEN_VEXT_VV_RM(vnclipu_wv_w)
 +GEN_VEXT_VV_RM(vnclipu_wv_b, 1)
 +GEN_VEXT_VV_RM(vnclipu_wv_h, 2)
 +GEN_VEXT_VV_RM(vnclipu_wv_w, 4)
  RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
  RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
  RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
 -GEN_VEXT_VX_RM(vnclipu_wx_b)
 -GEN_VEXT_VX_RM(vnclipu_wx_h)
 -GEN_VEXT_VX_RM(vnclipu_wx_w)
 +GEN_VEXT_VX_RM(vnclipu_wx_b, 1)
 +GEN_VEXT_VX_RM(vnclipu_wx_h, 2)
 +GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
  /*
   *** Vector Float Point Arithmetic Instructions
 --
-.30.1
+.36.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 19/25] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
-From: Bin Meng <bin.meng@windriver.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+Compares write mask registers, and so always operate under a tail-
-been updated to use a register mapped at 0x4f000000 instead of a
+agnostic policy.
 GPIO to control whether eMMC or SD card is to be used. With this
 support the same HSS image can be used for both eMMC and SD card
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-Id: <165449614532.19704.7000832880482980398-12@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ target/riscv/vector_helper.c            | 440 +++++++++++++-----------
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+ target/riscv/insn_trans/trans_rvv.c.inc |  17 +
-files changed, 7 insertions(+)
+files changed, 261 insertions(+), 196 deletions(-)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/vector_helper.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \
-     MICROCHIP_PFSOC_ENVM_DATA,
+     *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status);         \
-     MICROCHIP_PFSOC_QSPI_XIP,
+ }
-     MICROCHIP_PFSOC_IOSCB,
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
+-#define GEN_VEXT_VV_ENV(NAME)                             \
-     MICROCHIP_PFSOC_DRAM_LO,
++#define GEN_VEXT_VV_ENV(NAME, ESZ)                        \
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-     MICROCHIP_PFSOC_DRAM_HI,
+                   void *vs2, CPURISCVState *env,          \
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+                   uint32_t desc)                          \
  {                                                         \
      uint32_t vm = vext_vm(desc);                          \
      uint32_t vl = env->vl;                                \
 +    uint32_t total_elems =                                \
 +        vext_get_total_elems(env, desc, ESZ);             \
 +    uint32_t vta = vext_vta(desc);                        \
      uint32_t i;                                           \
                                                            \
      for (i = env->vstart; i < vl; i++) {                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
          do_##NAME(vd, vs1, vs2, i, env);                  \
      }                                                     \
      env->vstart = 0;                                      \
 +    /* set tail elements to 1s */                         \
 +    vext_set_elems_1s(vd, vta, vl * ESZ,                  \
 +                      total_elems * ESZ);                 \
  }
  RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
  RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
  RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
 -GEN_VEXT_VV_ENV(vfadd_vv_h)
 -GEN_VEXT_VV_ENV(vfadd_vv_w)
 -GEN_VEXT_VV_ENV(vfadd_vv_d)
 +GEN_VEXT_VV_ENV(vfadd_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfadd_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfadd_vv_d, 8)
  #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)        \
  static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
      *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
  }
 -#define GEN_VEXT_VF(NAME)                                 \
 +#define GEN_VEXT_VF(NAME, ESZ)                            \
  void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
                    void *vs2, CPURISCVState *env,          \
                    uint32_t desc)                          \
  {                                                         \
      uint32_t vm = vext_vm(desc);                          \
      uint32_t vl = env->vl;                                \
 +    uint32_t total_elems =                                \
 +        vext_get_total_elems(env, desc, ESZ);              \
 +    uint32_t vta = vext_vta(desc);                        \
      uint32_t i;                                           \
                                                            \
      for (i = env->vstart; i < vl; i++) {                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
          do_##NAME(vd, s1, vs2, i, env);                   \
      }                                                     \
      env->vstart = 0;                                      \
 +    /* set tail elements to 1s */                         \
 +    vext_set_elems_1s(vd, vta, vl * ESZ,                  \
 +                      total_elems * ESZ);                 \
  }
  RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
  RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
  RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
 -GEN_VEXT_VF(vfadd_vf_h)
 -GEN_VEXT_VF(vfadd_vf_w)
 -GEN_VEXT_VF(vfadd_vf_d)
 +GEN_VEXT_VF(vfadd_vf_h, 2)
 +GEN_VEXT_VF(vfadd_vf_w, 4)
 +GEN_VEXT_VF(vfadd_vf_d, 8)
  RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
  RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
  RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
 -GEN_VEXT_VV_ENV(vfsub_vv_h)
 -GEN_VEXT_VV_ENV(vfsub_vv_w)
 -GEN_VEXT_VV_ENV(vfsub_vv_d)
 +GEN_VEXT_VV_ENV(vfsub_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfsub_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfsub_vv_d, 8)
  RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
  RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
  RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
 -GEN_VEXT_VF(vfsub_vf_h)
 -GEN_VEXT_VF(vfsub_vf_w)
 -GEN_VEXT_VF(vfsub_vf_d)
 +GEN_VEXT_VF(vfsub_vf_h, 2)
 +GEN_VEXT_VF(vfsub_vf_w, 4)
 +GEN_VEXT_VF(vfsub_vf_d, 8)
  static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
  RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
  RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
  RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
 -GEN_VEXT_VF(vfrsub_vf_h)
 -GEN_VEXT_VF(vfrsub_vf_w)
 -GEN_VEXT_VF(vfrsub_vf_d)
 +GEN_VEXT_VF(vfrsub_vf_h, 2)
 +GEN_VEXT_VF(vfrsub_vf_w, 4)
 +GEN_VEXT_VF(vfrsub_vf_d, 8)
  /* Vector Widening Floating-Point Add/Subtract Instructions */
  static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
  RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
  RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
 -GEN_VEXT_VV_ENV(vfwadd_vv_h)
 -GEN_VEXT_VV_ENV(vfwadd_vv_w)
 +GEN_VEXT_VV_ENV(vfwadd_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwadd_vv_w, 8)
  RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
  RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
 -GEN_VEXT_VF(vfwadd_vf_h)
 -GEN_VEXT_VF(vfwadd_vf_w)
 +GEN_VEXT_VF(vfwadd_vf_h, 4)
 +GEN_VEXT_VF(vfwadd_vf_w, 8)
  static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
  RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
  RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
 -GEN_VEXT_VV_ENV(vfwsub_vv_h)
 -GEN_VEXT_VV_ENV(vfwsub_vv_w)
 +GEN_VEXT_VV_ENV(vfwsub_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwsub_vv_w, 8)
  RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
  RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
 -GEN_VEXT_VF(vfwsub_vf_h)
 -GEN_VEXT_VF(vfwsub_vf_w)
 +GEN_VEXT_VF(vfwsub_vf_h, 4)
 +GEN_VEXT_VF(vfwsub_vf_w, 8)
  static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
  RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
  RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
 -GEN_VEXT_VV_ENV(vfwadd_wv_h)
 -GEN_VEXT_VV_ENV(vfwadd_wv_w)
 +GEN_VEXT_VV_ENV(vfwadd_wv_h, 4)
 +GEN_VEXT_VV_ENV(vfwadd_wv_w, 8)
  RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
  RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
 -GEN_VEXT_VF(vfwadd_wf_h)
 -GEN_VEXT_VF(vfwadd_wf_w)
 +GEN_VEXT_VF(vfwadd_wf_h, 4)
 +GEN_VEXT_VF(vfwadd_wf_w, 8)
  static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
  RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
  RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
 -GEN_VEXT_VV_ENV(vfwsub_wv_h)
 -GEN_VEXT_VV_ENV(vfwsub_wv_w)
 +GEN_VEXT_VV_ENV(vfwsub_wv_h, 4)
 +GEN_VEXT_VV_ENV(vfwsub_wv_w, 8)
  RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
  RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
 -GEN_VEXT_VF(vfwsub_wf_h)
 -GEN_VEXT_VF(vfwsub_wf_w)
 +GEN_VEXT_VF(vfwsub_wf_h, 4)
 +GEN_VEXT_VF(vfwsub_wf_w, 8)
  /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
  RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
  RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
  RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
 -GEN_VEXT_VV_ENV(vfmul_vv_h)
 -GEN_VEXT_VV_ENV(vfmul_vv_w)
 -GEN_VEXT_VV_ENV(vfmul_vv_d)
 +GEN_VEXT_VV_ENV(vfmul_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmul_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmul_vv_d, 8)
  RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
  RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
  RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
 -GEN_VEXT_VF(vfmul_vf_h)
 -GEN_VEXT_VF(vfmul_vf_w)
 -GEN_VEXT_VF(vfmul_vf_d)
 +GEN_VEXT_VF(vfmul_vf_h, 2)
 +GEN_VEXT_VF(vfmul_vf_w, 4)
 +GEN_VEXT_VF(vfmul_vf_d, 8)
  RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
  RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
  RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
 -GEN_VEXT_VV_ENV(vfdiv_vv_h)
 -GEN_VEXT_VV_ENV(vfdiv_vv_w)
 -GEN_VEXT_VV_ENV(vfdiv_vv_d)
 +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8)
  RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
  RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
  RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
 -GEN_VEXT_VF(vfdiv_vf_h)
 -GEN_VEXT_VF(vfdiv_vf_w)
 -GEN_VEXT_VF(vfdiv_vf_d)
 +GEN_VEXT_VF(vfdiv_vf_h, 2)
 +GEN_VEXT_VF(vfdiv_vf_w, 4)
 +GEN_VEXT_VF(vfdiv_vf_d, 8)
  static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
  RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
  RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
  RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
 -GEN_VEXT_VF(vfrdiv_vf_h)
 -GEN_VEXT_VF(vfrdiv_vf_w)
 -GEN_VEXT_VF(vfrdiv_vf_d)
 +GEN_VEXT_VF(vfrdiv_vf_h, 2)
 +GEN_VEXT_VF(vfrdiv_vf_w, 4)
 +GEN_VEXT_VF(vfrdiv_vf_d, 8)
  /* Vector Widening Floating-Point Multiply */
  static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
  }
  RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
  RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
 -GEN_VEXT_VV_ENV(vfwmul_vv_h)
 -GEN_VEXT_VV_ENV(vfwmul_vv_w)
 +GEN_VEXT_VV_ENV(vfwmul_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwmul_vv_w, 8)
  RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
  RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
 -GEN_VEXT_VF(vfwmul_vf_h)
 -GEN_VEXT_VF(vfwmul_vf_w)
 +GEN_VEXT_VF(vfwmul_vf_h, 4)
 +GEN_VEXT_VF(vfwmul_vf_w, 8)
  /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
  #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)       \
@@ -XXX,XX +XXX,XX @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
  RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
  RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
 -GEN_VEXT_VV_ENV(vfmacc_vv_h)
 -GEN_VEXT_VV_ENV(vfmacc_vv_w)
 -GEN_VEXT_VV_ENV(vfmacc_vv_d)
 +GEN_VEXT_VV_ENV(vfmacc_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmacc_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmacc_vv_d, 8)
  #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)           \
  static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
  RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
  RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
  RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
 -GEN_VEXT_VF(vfmacc_vf_h)
 -GEN_VEXT_VF(vfmacc_vf_w)
 -GEN_VEXT_VF(vfmacc_vf_d)
 +GEN_VEXT_VF(vfmacc_vf_h, 2)
 +GEN_VEXT_VF(vfmacc_vf_w, 4)
 +GEN_VEXT_VF(vfmacc_vf_d, 8)
  static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
  RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
  RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
 -GEN_VEXT_VV_ENV(vfnmacc_vv_h)
 -GEN_VEXT_VV_ENV(vfnmacc_vv_w)
 -GEN_VEXT_VV_ENV(vfnmacc_vv_d)
 +GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8)
  RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
  RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
  RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
 -GEN_VEXT_VF(vfnmacc_vf_h)
 -GEN_VEXT_VF(vfnmacc_vf_w)
 -GEN_VEXT_VF(vfnmacc_vf_d)
 +GEN_VEXT_VF(vfnmacc_vf_h, 2)
 +GEN_VEXT_VF(vfnmacc_vf_w, 4)
 +GEN_VEXT_VF(vfnmacc_vf_d, 8)
  static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
  RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
  RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
 -GEN_VEXT_VV_ENV(vfmsac_vv_h)
 -GEN_VEXT_VV_ENV(vfmsac_vv_w)
 -GEN_VEXT_VV_ENV(vfmsac_vv_d)
 +GEN_VEXT_VV_ENV(vfmsac_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmsac_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmsac_vv_d, 8)
  RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
  RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
  RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
 -GEN_VEXT_VF(vfmsac_vf_h)
 -GEN_VEXT_VF(vfmsac_vf_w)
 -GEN_VEXT_VF(vfmsac_vf_d)
 +GEN_VEXT_VF(vfmsac_vf_h, 2)
 +GEN_VEXT_VF(vfmsac_vf_w, 4)
 +GEN_VEXT_VF(vfmsac_vf_d, 8)
  static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
  RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
  RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
 -GEN_VEXT_VV_ENV(vfnmsac_vv_h)
 -GEN_VEXT_VV_ENV(vfnmsac_vv_w)
 -GEN_VEXT_VV_ENV(vfnmsac_vv_d)
 +GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8)
  RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
  RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
  RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
 -GEN_VEXT_VF(vfnmsac_vf_h)
 -GEN_VEXT_VF(vfnmsac_vf_w)
 -GEN_VEXT_VF(vfnmsac_vf_d)
 +GEN_VEXT_VF(vfnmsac_vf_h, 2)
 +GEN_VEXT_VF(vfnmsac_vf_w, 4)
 +GEN_VEXT_VF(vfnmsac_vf_d, 8)
  static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
  RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
  RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
 -GEN_VEXT_VV_ENV(vfmadd_vv_h)
 -GEN_VEXT_VV_ENV(vfmadd_vv_w)
 -GEN_VEXT_VV_ENV(vfmadd_vv_d)
 +GEN_VEXT_VV_ENV(vfmadd_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmadd_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmadd_vv_d, 8)
  RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
  RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
  RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
 -GEN_VEXT_VF(vfmadd_vf_h)
 -GEN_VEXT_VF(vfmadd_vf_w)
 -GEN_VEXT_VF(vfmadd_vf_d)
 +GEN_VEXT_VF(vfmadd_vf_h, 2)
 +GEN_VEXT_VF(vfmadd_vf_w, 4)
 +GEN_VEXT_VF(vfmadd_vf_d, 8)
  static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
  RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
  RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
 -GEN_VEXT_VV_ENV(vfnmadd_vv_h)
 -GEN_VEXT_VV_ENV(vfnmadd_vv_w)
 -GEN_VEXT_VV_ENV(vfnmadd_vv_d)
 +GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8)
  RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
  RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
  RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
 -GEN_VEXT_VF(vfnmadd_vf_h)
 -GEN_VEXT_VF(vfnmadd_vf_w)
 -GEN_VEXT_VF(vfnmadd_vf_d)
 +GEN_VEXT_VF(vfnmadd_vf_h, 2)
 +GEN_VEXT_VF(vfnmadd_vf_w, 4)
 +GEN_VEXT_VF(vfnmadd_vf_d, 8)
  static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
  RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
  RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
 -GEN_VEXT_VV_ENV(vfmsub_vv_h)
 -GEN_VEXT_VV_ENV(vfmsub_vv_w)
 -GEN_VEXT_VV_ENV(vfmsub_vv_d)
 +GEN_VEXT_VV_ENV(vfmsub_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmsub_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmsub_vv_d, 8)
  RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
  RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
  RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
 -GEN_VEXT_VF(vfmsub_vf_h)
 -GEN_VEXT_VF(vfmsub_vf_w)
 -GEN_VEXT_VF(vfmsub_vf_d)
 +GEN_VEXT_VF(vfmsub_vf_h, 2)
 +GEN_VEXT_VF(vfmsub_vf_w, 4)
 +GEN_VEXT_VF(vfmsub_vf_d, 8)
  static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
  RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
  RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
 -GEN_VEXT_VV_ENV(vfnmsub_vv_h)
 -GEN_VEXT_VV_ENV(vfnmsub_vv_w)
 -GEN_VEXT_VV_ENV(vfnmsub_vv_d)
 +GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8)
  RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
  RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
  RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
 -GEN_VEXT_VF(vfnmsub_vf_h)
 -GEN_VEXT_VF(vfnmsub_vf_w)
 -GEN_VEXT_VF(vfnmsub_vf_d)
 +GEN_VEXT_VF(vfnmsub_vf_h, 2)
 +GEN_VEXT_VF(vfnmsub_vf_w, 4)
 +GEN_VEXT_VF(vfnmsub_vf_d, 8)
  /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
  static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
  RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
 -GEN_VEXT_VV_ENV(vfwmacc_vv_h)
 -GEN_VEXT_VV_ENV(vfwmacc_vv_w)
 +GEN_VEXT_VV_ENV(vfwmacc_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwmacc_vv_w, 8)
  RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
  RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
 -GEN_VEXT_VF(vfwmacc_vf_h)
 -GEN_VEXT_VF(vfwmacc_vf_w)
 +GEN_VEXT_VF(vfwmacc_vf_h, 4)
 +GEN_VEXT_VF(vfwmacc_vf_w, 8)
  static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
  RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
 -GEN_VEXT_VV_ENV(vfwnmacc_vv_h)
 -GEN_VEXT_VV_ENV(vfwnmacc_vv_w)
 +GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 8)
  RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
  RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
 -GEN_VEXT_VF(vfwnmacc_vf_h)
 -GEN_VEXT_VF(vfwnmacc_vf_w)
 +GEN_VEXT_VF(vfwnmacc_vf_h, 4)
 +GEN_VEXT_VF(vfwnmacc_vf_w, 8)
  static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
  RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
 -GEN_VEXT_VV_ENV(vfwmsac_vv_h)
 -GEN_VEXT_VV_ENV(vfwmsac_vv_w)
 +GEN_VEXT_VV_ENV(vfwmsac_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwmsac_vv_w, 8)
  RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
  RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
 -GEN_VEXT_VF(vfwmsac_vf_h)
 -GEN_VEXT_VF(vfwmsac_vf_w)
 +GEN_VEXT_VF(vfwmsac_vf_h, 4)
 +GEN_VEXT_VF(vfwmsac_vf_w, 8)
  static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
  RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
  RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
 -GEN_VEXT_VV_ENV(vfwnmsac_vv_h)
 -GEN_VEXT_VV_ENV(vfwnmsac_vv_w)
 +GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 4)
 +GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 8)
  RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
  RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
 -GEN_VEXT_VF(vfwnmsac_vf_h)
 -GEN_VEXT_VF(vfwnmsac_vf_w)
 +GEN_VEXT_VF(vfwnmsac_vf_h, 4)
 +GEN_VEXT_VF(vfwnmsac_vf_w, 8)
  /* Vector Floating-Point Square-Root Instruction */
  /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i,      \
      *((TD *)vd + HD(i)) = OP(s2, &env->fp_status);     \
  }
 -#define GEN_VEXT_V_ENV(NAME)                           \
 +#define GEN_VEXT_V_ENV(NAME, ESZ)                      \
  void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
          CPURISCVState *env, uint32_t desc)             \
  {                                                      \
      uint32_t vm = vext_vm(desc);                       \
      uint32_t vl = env->vl;                             \
 +    uint32_t total_elems =                             \
 +        vext_get_total_elems(env, desc, ESZ);          \
 +    uint32_t vta = vext_vta(desc);                     \
      uint32_t i;                                        \
                                                         \
      if (vl == 0) {                                     \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
          do_##NAME(vd, vs2, i, env);                    \
      }                                                  \
      env->vstart = 0;                                   \
 +    vext_set_elems_1s(vd, vta, vl * ESZ,               \
 +                      total_elems * ESZ);              \
  }
  RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
  RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
  RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
 -GEN_VEXT_V_ENV(vfsqrt_v_h)
 -GEN_VEXT_V_ENV(vfsqrt_v_w)
 -GEN_VEXT_V_ENV(vfsqrt_v_d)
 +GEN_VEXT_V_ENV(vfsqrt_v_h, 2)
 +GEN_VEXT_V_ENV(vfsqrt_v_w, 4)
 +GEN_VEXT_V_ENV(vfsqrt_v_d, 8)
  /*
   * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frsqrt7_d(float64 f, float_status *s)
  RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
  RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
  RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
 -GEN_VEXT_V_ENV(vfrsqrt7_v_h)
 -GEN_VEXT_V_ENV(vfrsqrt7_v_w)
 -GEN_VEXT_V_ENV(vfrsqrt7_v_d)
 +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2)
 +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4)
 +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8)
  /*
   * Vector Floating-Point Reciprocal Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frec7_d(float64 f, float_status *s)
  RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
  RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
  RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
 -GEN_VEXT_V_ENV(vfrec7_v_h)
 -GEN_VEXT_V_ENV(vfrec7_v_w)
 -GEN_VEXT_V_ENV(vfrec7_v_d)
 +GEN_VEXT_V_ENV(vfrec7_v_h, 2)
 +GEN_VEXT_V_ENV(vfrec7_v_w, 4)
 +GEN_VEXT_V_ENV(vfrec7_v_d, 8)
  /* Vector Floating-Point MIN/MAX Instructions */
  RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
  RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
  RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
 -GEN_VEXT_VV_ENV(vfmin_vv_h)
 -GEN_VEXT_VV_ENV(vfmin_vv_w)
 -GEN_VEXT_VV_ENV(vfmin_vv_d)
 +GEN_VEXT_VV_ENV(vfmin_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmin_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmin_vv_d, 8)
  RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
  RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
  RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
 -GEN_VEXT_VF(vfmin_vf_h)
 -GEN_VEXT_VF(vfmin_vf_w)
 -GEN_VEXT_VF(vfmin_vf_d)
 +GEN_VEXT_VF(vfmin_vf_h, 2)
 +GEN_VEXT_VF(vfmin_vf_w, 4)
 +GEN_VEXT_VF(vfmin_vf_d, 8)
  RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
  RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
  RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
 -GEN_VEXT_VV_ENV(vfmax_vv_h)
 -GEN_VEXT_VV_ENV(vfmax_vv_w)
 -GEN_VEXT_VV_ENV(vfmax_vv_d)
 +GEN_VEXT_VV_ENV(vfmax_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfmax_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfmax_vv_d, 8)
  RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
  RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
  RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
 -GEN_VEXT_VF(vfmax_vf_h)
 -GEN_VEXT_VF(vfmax_vf_w)
 -GEN_VEXT_VF(vfmax_vf_d)
 +GEN_VEXT_VF(vfmax_vf_h, 2)
 +GEN_VEXT_VF(vfmax_vf_w, 4)
 +GEN_VEXT_VF(vfmax_vf_d, 8)
  /* Vector Floating-Point Sign-Injection Instructions */
  static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
  RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
  RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
  RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
 -GEN_VEXT_VV_ENV(vfsgnj_vv_h)
 -GEN_VEXT_VV_ENV(vfsgnj_vv_w)
 -GEN_VEXT_VV_ENV(vfsgnj_vv_d)
 +GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8)
  RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
  RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
  RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
 -GEN_VEXT_VF(vfsgnj_vf_h)
 -GEN_VEXT_VF(vfsgnj_vf_w)
 -GEN_VEXT_VF(vfsgnj_vf_d)
 +GEN_VEXT_VF(vfsgnj_vf_h, 2)
 +GEN_VEXT_VF(vfsgnj_vf_w, 4)
 +GEN_VEXT_VF(vfsgnj_vf_d, 8)
  static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
  RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
  RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
  RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
 -GEN_VEXT_VV_ENV(vfsgnjn_vv_h)
 -GEN_VEXT_VV_ENV(vfsgnjn_vv_w)
 -GEN_VEXT_VV_ENV(vfsgnjn_vv_d)
 +GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8)
  RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
  RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
  RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
 -GEN_VEXT_VF(vfsgnjn_vf_h)
 -GEN_VEXT_VF(vfsgnjn_vf_w)
 -GEN_VEXT_VF(vfsgnjn_vf_d)
 +GEN_VEXT_VF(vfsgnjn_vf_h, 2)
 +GEN_VEXT_VF(vfsgnjn_vf_w, 4)
 +GEN_VEXT_VF(vfsgnjn_vf_d, 8)
  static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
  {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
  RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
  RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
  RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
 -GEN_VEXT_VV_ENV(vfsgnjx_vv_h)
 -GEN_VEXT_VV_ENV(vfsgnjx_vv_w)
 -GEN_VEXT_VV_ENV(vfsgnjx_vv_d)
 +GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2)
 +GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4)
 +GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8)
  RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
  RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
  RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
 -GEN_VEXT_VF(vfsgnjx_vf_h)
 -GEN_VEXT_VF(vfsgnjx_vf_w)
 -GEN_VEXT_VF(vfsgnjx_vf_d)
 +GEN_VEXT_VF(vfsgnjx_vf_h, 2)
 +GEN_VEXT_VF(vfsgnjx_vf_w, 4)
 +GEN_VEXT_VF(vfsgnjx_vf_d, 8)
  /* Vector Floating-Point Compare Instructions */
  #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP)            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
  {                                                             \
      uint32_t vm = vext_vm(desc);                              \
      uint32_t vl = env->vl;                                    \
 +    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
 +    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
      uint32_t i;                                               \
                                                                \
      for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
                             DO_OP(s2, s1, &env->fp_status));   \
      }                                                         \
      env->vstart = 0;                                          \
 +    /* mask destination register are always tail-agnostic */  \
 +    /* set tail elements to 1s */                             \
 +    if (vta_all_1s) {                                         \
 +        for (; i < total_elems; i++) {                        \
 +            vext_set_elem_mask(vd, i, 1);                     \
 +        }                                                     \
 +    }                                                         \
  }
  GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2,       \
  {                                                                   \
      uint32_t vm = vext_vm(desc);                                    \
      uint32_t vl = env->vl;                                          \
 +    uint32_t total_elems = env_archcpu(env)->cfg.vlen;              \
 +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                    \
      uint32_t i;                                                     \
                                                                      \
      for (i = env->vstart; i < vl; i++) {                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2,       \
                             DO_OP(s2, (ETYPE)s1, &env->fp_status));  \
      }                                                               \
      env->vstart = 0;                                                \
 +    /* mask destination register are always tail-agnostic */        \
 +    /* set tail elements to 1s */                                   \
 +    if (vta_all_1s) {                                               \
 +        for (; i < total_elems; i++) {                              \
 +            vext_set_elem_mask(vd, i, 1);                           \
 +        }                                                           \
 +    }                                                               \
  }
  GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i)      \
      *((TD *)vd + HD(i)) = OP(s2);                      \
  }
 -#define GEN_VEXT_V(NAME)                               \
 +#define GEN_VEXT_V(NAME, ESZ)                          \
  void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
                    CPURISCVState *env, uint32_t desc)   \
  {                                                      \
      uint32_t vm = vext_vm(desc);                       \
      uint32_t vl = env->vl;                             \
 +    uint32_t total_elems =                             \
 +        vext_get_total_elems(env, desc, ESZ);          \
 +    uint32_t vta = vext_vta(desc);                     \
      uint32_t i;                                        \
                                                         \
      for (i = env->vstart; i < vl; i++) {               \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
          do_##NAME(vd, vs2, i);                         \
      }                                                  \
      env->vstart = 0;                                   \
 +    /* set tail elements to 1s */                      \
 +    vext_set_elems_1s(vd, vta, vl * ESZ,               \
 +                      total_elems * ESZ);              \
  }
  target_ulong fclass_h(uint64_t frs1)
@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1)
  RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
  RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
  RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
 -GEN_VEXT_V(vfclass_v_h)
 -GEN_VEXT_V(vfclass_v_w)
 -GEN_VEXT_V(vfclass_v_d)
 +GEN_VEXT_V(vfclass_v_h, 2)
 +GEN_VEXT_V(vfclass_v_w, 4)
 +GEN_VEXT_V(vfclass_v_d, 8)
  /* Vector Floating-Point Merge Instruction */
 +
  #define GEN_VFMERGE_VF(NAME, ETYPE, H)                        \
  void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
                    CPURISCVState *env, uint32_t desc)          \
  {                                                             \
      uint32_t vm = vext_vm(desc);                              \
      uint32_t vl = env->vl;                                    \
 +    uint32_t esz = sizeof(ETYPE);                             \
 +    uint32_t total_elems =                                    \
 +        vext_get_total_elems(env, desc, esz);                 \
 +    uint32_t vta = vext_vta(desc);                            \
      uint32_t i;                                               \
                                                                \
      for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
            = (!vm && !vext_elem_mask(v0, i) ? s2 : s1);        \
      }                                                         \
      env->vstart = 0;                                          \
 +    /* set tail elements to 1s */                             \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);  \
  }
  GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2)
@@ -XXX,XX +XXX,XX @@ GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8)
  RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
  RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
  RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
 -GEN_VEXT_V_ENV(vfcvt_xu_f_v_h)
 -GEN_VEXT_V_ENV(vfcvt_xu_f_v_w)
 -GEN_VEXT_V_ENV(vfcvt_xu_f_v_d)
 +GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2)
 +GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4)
 +GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8)
  /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
  RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
  RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
  RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
 -GEN_VEXT_V_ENV(vfcvt_x_f_v_h)
 -GEN_VEXT_V_ENV(vfcvt_x_f_v_w)
 -GEN_VEXT_V_ENV(vfcvt_x_f_v_d)
 +GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2)
 +GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4)
 +GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8)
  /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
  RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
  RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
  RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
 -GEN_VEXT_V_ENV(vfcvt_f_xu_v_h)
 -GEN_VEXT_V_ENV(vfcvt_f_xu_v_w)
 -GEN_VEXT_V_ENV(vfcvt_f_xu_v_d)
 +GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2)
 +GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4)
 +GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8)
  /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
  RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
  RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
  RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
 -GEN_VEXT_V_ENV(vfcvt_f_x_v_h)
 -GEN_VEXT_V_ENV(vfcvt_f_x_v_w)
 -GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
 +GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2)
 +GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4)
 +GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8)
  /* Widening Floating-Point/Integer Type-Convert Instructions */
  /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
  /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
  RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
  RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
 -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h)
 -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w)
 +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
 +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 8)
  /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */
  RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32)
  RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
 -GEN_VEXT_V_ENV(vfwcvt_x_f_v_h)
 -GEN_VEXT_V_ENV(vfwcvt_x_f_v_w)
 +GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4)
 +GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
  /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
  RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
  RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
  RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
 -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b)
 -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h)
 -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w)
 +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 2)
 +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 4)
 +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 8)
  /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
  RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
  RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
  RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
 -GEN_VEXT_V_ENV(vfwcvt_f_x_v_b)
 -GEN_VEXT_V_ENV(vfwcvt_f_x_v_h)
 -GEN_VEXT_V_ENV(vfwcvt_f_x_v_w)
 +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 2)
 +GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4)
 +GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
  /*
   * vfwcvt.f.f.v vd, vs2, vm
@@ -XXX,XX +XXX,XX @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
  RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16)
  RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
 -GEN_VEXT_V_ENV(vfwcvt_f_f_v_h)
 -GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
 +GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4)
 +GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8)
  /* Narrowing Floating-Point/Integer Type-Convert Instructions */
  /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
  RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
  RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
  RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
 -GEN_VEXT_V_ENV(vfncvt_xu_f_w_b)
 -GEN_VEXT_V_ENV(vfncvt_xu_f_w_h)
 -GEN_VEXT_V_ENV(vfncvt_xu_f_w_w)
 +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1)
 +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2)
 +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4)
  /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
  RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
  RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
  RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
 -GEN_VEXT_V_ENV(vfncvt_x_f_w_b)
 -GEN_VEXT_V_ENV(vfncvt_x_f_w_h)
 -GEN_VEXT_V_ENV(vfncvt_x_f_w_w)
 +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1)
 +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
 +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
  /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
  RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
  RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
 -GEN_VEXT_V_ENV(vfncvt_f_xu_w_h)
 -GEN_VEXT_V_ENV(vfncvt_f_xu_w_w)
 +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2)
 +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4)
  /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
  RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
  RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
 -GEN_VEXT_V_ENV(vfncvt_f_x_w_h)
 -GEN_VEXT_V_ENV(vfncvt_f_x_w_w)
 +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2)
 +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4)
  /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
  static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
  RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
  RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
 -GEN_VEXT_V_ENV(vfncvt_f_f_w_h)
 -GEN_VEXT_V_ENV(vfncvt_f_f_w_w)
 +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
 +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
  /*
   *** Vector Reduction Operations
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+                                                                    \
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
-     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
++        data =                                                     \
-     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
++            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
-     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+                            vreg_ofs(s, a->rs1),                    \
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+                            vreg_ofs(s, a->rs2), cpu_env,           \
-                     memmap[MICROCHIP_PFSOC_IOSCB].base);
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)            \
+         gen_set_rm(s, RISCV_FRM_DYN);                             \
-+    /* eMMC/SD mux */
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                \
-+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);            \
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);              \
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
++        data = FIELD_DP32(data, VDATA, VTA_ALL_1S,                \
-+
++                          s->cfg_vta_all_1s);                     \
-     /* QSPI Flash */
+         return opfvf_trans(a->rd, a->rs1, a->rs2, data,           \
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
+                            fns[s->sew - 1], s);                   \
-                            "microchip.pfsoc.qspi_xip",
+     }                                                             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
                                                                   \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                             vreg_ofs(s, a->rs1),                  \
                             vreg_ofs(s, a->rs2), cpu_env,         \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
          gen_set_rm(s, RISCV_FRM_DYN);                            \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
          return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                             fns[s->sew - 1], s);                  \
      }                                                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs1),                    \
                             vreg_ofs(s, a->rs2), cpu_env,           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
          gen_set_rm(s, RISCV_FRM_DYN);                            \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
          return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                             fns[s->sew - 1], s);                  \
      }                                                            \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs2), cpu_env,
                             s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
 +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
 +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
 +        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
 --
-.30.1
+.36.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+[PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions
-From: Asherah Connor <ashe@kivikakk.ee>
+From: eopXD <yueh.ting.chen@gmail.com>
-Allow ramfb on virt.  This lets `-device ramfb' work.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165449614532.19704.7000832880482980398-13@git.sr.ht>
 Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 3 +++
+ target/riscv/vector_helper.c | 20 ++++++++++++++++++++
-file changed, 3 insertions(+)
+file changed, 20 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/vector_helper.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
- #include "sysemu/sysemu.h"
+ {                                                         \
- #include "hw/pci/pci.h"
+     uint32_t vm = vext_vm(desc);                          \
- #include "hw/pci-host/gpex.h"
+     uint32_t vl = env->vl;                                \
-+#include "hw/display/ramfb.h"
++    uint32_t esz = sizeof(TD);                            \
++    uint32_t vlenb = simd_maxsz(desc);                    \
- static const MemMapEntry virt_memmap[] = {
++    uint32_t vta = vext_vta(desc);                        \
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
+     uint32_t i;                                           \
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+     TD s1 =  *((TD *)vs1 + HD(0));                        \
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+                                                           \
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-     mc->numa_mem_supported = true;
+     }                                                     \
-+
+     *((TD *)vd + HD(0)) = s1;                             \
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+     env->vstart = 0;                                      \
 +    /* set tail elements to 1s */                         \
 +    vext_set_elems_1s(vd, vta, esz, vlenb);               \
  }
- static const TypeInfo virt_machine_typeinfo = {
+ /* vd[0] = sum(vs1[0], vs2[*]) */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,           \
  {                                                          \
      uint32_t vm = vext_vm(desc);                           \
      uint32_t vl = env->vl;                                 \
 +    uint32_t esz = sizeof(TD);                             \
 +    uint32_t vlenb = simd_maxsz(desc);                     \
 +    uint32_t vta = vext_vta(desc);                         \
      uint32_t i;                                            \
      TD s1 =  *((TD *)vs1 + HD(0));                         \
                                                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,           \
      }                                                      \
      *((TD *)vd + HD(0)) = s1;                              \
      env->vstart = 0;                                       \
 +    /* set tail elements to 1s */                          \
 +    vext_set_elems_1s(vd, vta, esz, vlenb);                \
  }
  /* Unordered sum */
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
  {
      uint32_t vm = vext_vm(desc);
      uint32_t vl = env->vl;
 +    uint32_t esz = sizeof(uint32_t);
 +    uint32_t vlenb = simd_maxsz(desc);
 +    uint32_t vta = vext_vta(desc);
      uint32_t i;
      uint32_t s1 =  *((uint32_t *)vs1 + H4(0));
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
      }
      *((uint32_t *)vd + H4(0)) = s1;
      env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, esz, vlenb);
  }
  void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
  {
      uint32_t vm = vext_vm(desc);
      uint32_t vl = env->vl;
 +    uint32_t esz = sizeof(uint64_t);
 +    uint32_t vlenb = simd_maxsz(desc);
 +    uint32_t vta = vext_vta(desc);
      uint32_t i;
      uint64_t s1 =  *((uint64_t *)vs1);
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
      }
      *((uint64_t *)vd) = s1;
      env->vstart = 0;
 +    /* set tail elements to 1s */
 +    vext_set_elems_1s(vd, vta, esz, vlenb);
  }
  /*
 --
-.30.1
+.36.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+[PULL 21/25] target/riscv: rvv: Add tail agnostic for vector mask instructions
-From: Jim Shu <cwshu@andestech.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-Like MMU translation, add qemu log of PMP permission checking for
+The tail elements in the destination mask register are updated under
-debugging.
+a tail-agnostic policy.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <165449614532.19704.7000832880482980398-14@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++++++++
+ target/riscv/vector_helper.c            | 30 +++++++++++++++++++++++++
-file changed, 12 insertions(+)
+ target/riscv/insn_trans/trans_rvv.c.inc |  6 +++++
 files changed, 36 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/vector_helper.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-             if (ret == TRANSLATE_SUCCESS) {
+                   uint32_t desc)                          \
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ {                                                         \
-                                                size, access_type, mode);
+     uint32_t vl = env->vl;                                \
-+
++    uint32_t total_elems = env_archcpu(env)->cfg.vlen;    \
-+                qemu_log_mask(CPU_LOG_MMU,
++    uint32_t vta_all_1s = vext_vta_all_1s(desc);          \
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+     uint32_t i;                                           \
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
+     int a, b;                                             \
-+                              __func__, pa, ret, prot_pmp, tlb_size);
+                                                           \
-+
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
-                 prot &= prot_pmp;
+         vext_set_elem_mask(vd, i, OP(b, a));              \
-             }
+     }                                                     \
+     env->vstart = 0;                                      \
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++    /* mask destination register are always tail-         \
-         if (ret == TRANSLATE_SUCCESS) {
++     * agnostic                                           \
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
++     */                                                   \
-                                            size, access_type, mode);
++    /* set tail elements to 1s */                         \
-+
++    if (vta_all_1s) {                                     \
-+            qemu_log_mask(CPU_LOG_MMU,
++        for (; i < total_elems; i++) {                    \
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
++            vext_set_elem_mask(vd, i, 1);                 \
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
++        }                                                 \
-+                          __func__, pa, ret, prot_pmp, tlb_size);
++    }                                                     \
-+
+ }
-             prot &= prot_pmp;
  #define DO_NAND(N, M)  (!(N & M))
@@ -XXX,XX +XXX,XX @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
  {
      uint32_t vm = vext_vm(desc);
      uint32_t vl = env->vl;
 +    uint32_t total_elems = env_archcpu(env)->cfg.vlen;
 +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
      int i;
      bool first_mask_bit = false;
@@ -XXX,XX +XXX,XX @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
          }
      }
+     env->vstart = 0;
++    /* mask destination register are always tail-agnostic */
++    /* set tail elements to 1s */
++    if (vta_all_1s) {
++        for (; i < total_elems; i++) {
++            vext_set_elem_mask(vd, i, 1);
++        }
++    }
+ }
+ void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env,      \
+ {                                                                         \
+     uint32_t vm = vext_vm(desc);                                          \
+     uint32_t vl = env->vl;                                                \
++    uint32_t esz = sizeof(ETYPE);                                         \
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
++    uint32_t vta = vext_vta(desc);                                        \
+     uint32_t sum = 0;                                                     \
+     int i;                                                                \
+                                                                           \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env,      \
+         }                                                                 \
+     }                                                                     \
+     env->vstart = 0;                                                      \
++    /* set tail elements to 1s */                                         \
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
+ }
+ GEN_VEXT_VIOTA_M(viota_m_b, uint8_t,  H1)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc)  \
+ {                                                                         \
+     uint32_t vm = vext_vm(desc);                                          \
+     uint32_t vl = env->vl;                                                \
++    uint32_t esz = sizeof(ETYPE);                                         \
++    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
++    uint32_t vta = vext_vta(desc);                                        \
+     int i;                                                                \
+                                                                           \
+     for (i = env->vstart; i < vl; i++) {                                  \
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc)  \
+         *((ETYPE *)vd + H(i)) = i;                                        \
+     }                                                                     \
+     env->vstart = 0;                                                      \
++    /* set tail elements to 1s */                                         \
++    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
+ }
+ GEN_VEXT_VID_V(vid_v_b, uint8_t,  H1)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
+         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
+                                                                    \
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
++        data =                                                     \
++            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
+                            vreg_ofs(s, a->rs1),                    \
+                            vreg_ofs(s, a->rs2), cpu_env,           \
+@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
+                                                                    \
+         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
++        data =                                                     \
++            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
+                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
+                            cpu_env, s->cfg_ptr->vlen / 8,          \
+@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
+         data = FIELD_DP32(data, VDATA, VM, a->vm);
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+         static gen_helper_gvec_3_ptr * const fns[4] = {
+             gen_helper_viota_m_b, gen_helper_viota_m_h,
+             gen_helper_viota_m_w, gen_helper_viota_m_d,
+@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
+         data = FIELD_DP32(data, VDATA, VM, a->vm);
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+         static gen_helper_gvec_2_ptr * const fns[4] = {
+             gen_helper_vid_v_b, gen_helper_vid_v_h,
+             gen_helper_vid_v_w, gen_helper_vid_v_d,
 --
-.30.1
+.36.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+[PULL 22/25] target/riscv: rvv: Add tail agnostic for vector permutation instructions
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: eopXD <yueh.ting.chen@gmail.com>
-According to the specification the "field SPVP of hstatus controls the
+Signed-off-by: eop Chen <eop.chen@sifive.com>
-privilege level of the access" for the hypervisor virtual-machine load
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-and store instructions HLV, HLVX and HSV.
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Message-Id: <165449614532.19704.7000832880482980398-15@git.sr.ht>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
+ target/riscv/vector_helper.c            | 40 +++++++++++++++++++++++++
-file changed, 14 insertions(+), 11 deletions(-)
+ target/riscv/insn_trans/trans_rvv.c.inc |  7 +++--
 files changed, 45 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/vector_helper.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
-         use_background = true;
+ {                                                                         \
      uint32_t vm = vext_vm(desc);                                          \
      uint32_t vl = env->vl;                                                \
 +    uint32_t esz = sizeof(ETYPE);                                         \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
 +    uint32_t vta = vext_vta(desc);                                        \
      target_ulong offset = s1, i_min, i;                                   \
                                                                            \
      i_min = MAX(env->vstart, offset);                                     \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
          }                                                                 \
          *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset));          \
      }                                                                     \
 +    /* set tail elements to 1s */                                         \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
  }
  /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
      uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE)));           \
      uint32_t vm = vext_vm(desc);                                          \
      uint32_t vl = env->vl;                                                \
 +    uint32_t esz = sizeof(ETYPE);                                         \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
 +    uint32_t vta = vext_vta(desc);                                        \
      target_ulong i_max, i;                                                \
                                                                            \
      i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart);       \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
      }                                                                     \
                                                                            \
      env->vstart = 0;                                                      \
 +    /* set tail elements to 1s */                                         \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
  }
  /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -XXX,XX +XXX,XX @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
      typedef uint##BITWIDTH##_t ETYPE;                                       \
      uint32_t vm = vext_vm(desc);                                            \
      uint32_t vl = env->vl;                                                  \
 +    uint32_t esz = sizeof(ETYPE);                                           \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);            \
 +    uint32_t vta = vext_vta(desc);                                          \
      uint32_t i;                                                             \
                                                                              \
      for (i = env->vstart; i < vl; i++) {                                    \
@@ -XXX,XX +XXX,XX @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
          }                                                                   \
      }                                                                       \
      env->vstart = 0;                                                        \
 +    /* set tail elements to 1s */                                           \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);                \
  }
  GEN_VEXT_VSLIE1UP(8,  H1)
@@ -XXX,XX +XXX,XX @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
      typedef uint##BITWIDTH##_t ETYPE;                                         \
      uint32_t vm = vext_vm(desc);                                              \
      uint32_t vl = env->vl;                                                    \
 +    uint32_t esz = sizeof(ETYPE);                                             \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);              \
 +    uint32_t vta = vext_vta(desc);                                            \
      uint32_t i;                                                               \
                                                                                \
      for (i = env->vstart; i < vl; i++) {                                      \
@@ -XXX,XX +XXX,XX @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
          }                                                                     \
      }                                                                         \
      env->vstart = 0;                                                          \
 +    /* set tail elements to 1s */                                             \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);                  \
  }
  GEN_VEXT_VSLIDE1DOWN(8,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
      uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2)));             \
      uint32_t vm = vext_vm(desc);                                          \
      uint32_t vl = env->vl;                                                \
 +    uint32_t esz = sizeof(TS2);                                           \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
 +    uint32_t vta = vext_vta(desc);                                        \
      uint64_t index;                                                       \
      uint32_t i;                                                           \
                                                                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
          }                                                                 \
      }                                                                     \
      env->vstart = 0;                                                      \
 +    /* set tail elements to 1s */                                         \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
  }
  /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
      uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE)));           \
      uint32_t vm = vext_vm(desc);                                          \
      uint32_t vl = env->vl;                                                \
 +    uint32_t esz = sizeof(ETYPE);                                         \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
 +    uint32_t vta = vext_vta(desc);                                        \
      uint64_t index = s1;                                                  \
      uint32_t i;                                                           \
                                                                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
          }                                                                 \
      }                                                                     \
      env->vstart = 0;                                                      \
 +    /* set tail elements to 1s */                                         \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
  }
  /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
                    CPURISCVState *env, uint32_t desc)                      \
  {                                                                         \
      uint32_t vl = env->vl;                                                \
 +    uint32_t esz = sizeof(ETYPE);                                         \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
 +    uint32_t vta = vext_vta(desc);                                        \
      uint32_t num = 0, i;                                                  \
                                                                            \
      for (i = env->vstart; i < vl; i++) {                                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
          num++;                                                            \
      }                                                                     \
      env->vstart = 0;                                                      \
 +    /* set tail elements to 1s */                                         \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
  }
  /* Compress into vd elements of vs2 where vs1 is enabled */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,                 \
  {                                                                \
      uint32_t vl = env->vl;                                       \
      uint32_t vm = vext_vm(desc);                                 \
 +    uint32_t esz = sizeof(ETYPE);                                \
 +    uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
 +    uint32_t vta = vext_vta(desc);                               \
      uint32_t i;                                                  \
                                                                   \
      for (i = env->vstart; i < vl; i++) {                         \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,                 \
          *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i));       \
      }                                                            \
      env->vstart = 0;                                             \
 +    /* set tail elements to 1s */                                \
 +    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);     \
  }
  GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t,  H2, H1)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
          return false;
      }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+-    if (a->vm && s->vl_eq_vlmax) {
-+    /* MPRV does not affect the virtual-machine load/store
++    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
-+       instructions, HLV, HLVX, and HSV. */
+         int scale = s->lmul - (s->sew + 3);
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+         int vlmax = s->cfg_ptr->vlen >> -scale;
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+         TCGv_i64 dest = tcg_temp_new_i64();
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
+         return false;
              mode = get_field(env->mstatus, MSTATUS_MPP);
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                    __func__, address, access_type, mmu_idx);
 -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 -        if (get_field(env->mstatus, MSTATUS_MPRV)) {
 -            mode = get_field(env->mstatus, MSTATUS_MPP);
 +    /* MPRV does not affect the virtual-machine load/store
 +       instructions, HLV, HLVX, and HSV. */
 +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
 +        mode = get_field(env->hstatus, HSTATUS_SPVP);
 +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
 +               get_field(env->mstatus, MSTATUS_MPRV)) {
 +        mode = get_field(env->mstatus, MSTATUS_MPP);
 +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
 +            two_stage_lookup = true;
          }
      }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+-    if (a->vm && s->vl_eq_vlmax) {
--        access_type != MMU_INST_FETCH &&
++    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
--        get_field(env->mstatus, MSTATUS_MPRV) &&
+         int scale = s->lmul - (s->sew + 3);
--        get_field(env->mstatus, MSTATUS_MPV)) {
+         int vlmax = s->cfg_ptr->vlen >> -scale;
--        two_stage_lookup = true;
+         if (a->rs1 >= vlmax) {
--    }
+@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
--
+         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     if (riscv_cpu_virt_enabled(env) ||
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-          access_type != MMU_INST_FETCH)) {
++        data = FIELD_DP32(data, VDATA, VTA, s->vta);
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
                             cpu_env, s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
      }
      data = FIELD_DP32(data, VDATA, VM, a->vm);
 +    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 +    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                         vreg_ofs(s, a->rs2), cpu_env,
 --
-.30.1
+.36.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: eopXD <eop.chen@sifive.com>
-The current condition for the use of background registers only
+According to v-spec, tail agnostic behavior can be either kept as
-considers the hypervisor load and store instructions,
+undisturbed or set elements' bits to all 1s. To distinguish the
-but not accesses from M mode via MSTATUS_MPRV+MPV.
+difference of tail policies, QEMU should be able to simulate the tail
 agnostic behavior as "set tail elements' bits to all 1s".
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+There are multiple possibility for agnostic elements according to
 v-spec. The main intent of this patch-set tries to add option that
 can distinguish between tail policies. Setting agnostic elements to
 all 1s allows QEMU to express this.
 This commit adds option 'rvv_ta_all_1s' is added to enable the
 behavior, it is default as disabled.
 Signed-off-by: eop Chen <eop.chen@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Message-Id: <165449614532.19704.7000832880482980398-16@git.sr.ht>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ target/riscv/cpu.c | 2 ++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-      * was called. Background registers will be used if the guest has
+     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
-      * forced a two stage translation to be on (in HS or M mode).
-      */
+     DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
++
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
++    DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
-         use_background = true;
+     DEFINE_PROP_END_OF_LIST(),
-     }
+ };
 --
-.30.1
+.36.1

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL 24/25] target/riscv: Don't expose the CPU properties on names CPUs
-From: Frank Chang <frank.chang@sifive.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+There are currently two types of RISC-V CPUs:
-is not enabled.
+ - Generic CPUs (base or any) that allow complete custimisation
  - "Named" CPUs that match existing hardware
-If -1 is returned, exception will be raised and cs->exception_index will
+Users can use the base CPUs to custimise the extensions that they want, for
-be set to the negative return value. The exception will then be treated
+example -cpu rv64,v=true.
 as an instruction access fault instead of illegal instruction fault.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+We originally exposed these as part of the named CPUs as well, but that was
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+by accident.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Exposing the CPU properties to named CPUs means that we accidently
 enable extensions that don't exist on the CPUs by default. For example
 the SiFive E CPU currently support the zba extension, which is a bug.
 This patch instead only exposes the CPU extensions to the generic CPUs.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++---------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 46 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
-     if (env->misa & RVV) {
+     "reserved"
-         return 0;
+ };
-     }
--    return -1;
++static void register_cpu_props(DeviceState *dev);
-+    return -RISCV_EXCP_ILLEGAL_INST;
++
  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
  {
      if (async) {
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #endif
      set_priv_version(env, PRIV_VERSION_1_12_0);
 +    register_cpu_props(DEVICE(obj));
  }
- static int ctr(CPURISCVState *env, int csrno)
+ #if defined(TARGET_RISCV64)
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, MXL_RV64, 0);
 +    register_cpu_props(DEVICE(obj));
  }
  static void rv64_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
  static void rv64_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +
      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 +    cpu->cfg.mmu = false;
  }
  static void rv128_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, MXL_RV128, 0);
 +    register_cpu_props(DEVICE(obj));
  }
  #else
  static void rv32_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, MXL_RV32, 0);
 +    register_cpu_props(DEVICE(obj));
  }
  static void rv32_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
  static void rv32_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +
      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 +    cpu->cfg.mmu = false;
  }
  static void rv32_ibex_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +
      set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 -    qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
 +    cpu->cfg.mmu = false;
 +    cpu->cfg.epmp = true;
  }
  static void rv32_imafcu_nommu_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +
      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      set_resetvec(env, DEFAULT_RSTVEC);
 -    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 +    cpu->cfg.mmu = false;
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
  #elif defined(TARGET_RISCV64)
      set_misa(env, MXL_RV64, 0);
  #endif
 +    register_cpu_props(DEVICE(obj));
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
 +    cpu->cfg.ext_counters = true;
 +    cpu->cfg.ext_ifencei = true;
 +    cpu->cfg.ext_icsr = true;
 +    cpu->cfg.mmu = true;
 +    cpu->cfg.pmp = true;
 +
      cpu_set_cpustate_pointers(cpu);
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
  #endif /* CONFIG_USER_ONLY */
  }
 -static Property riscv_cpu_properties[] = {
 +static Property riscv_cpu_extensions[] = {
      /* Defaults for standard extensions */
      DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
      DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
      DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
      DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 -    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
      DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
      DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
      DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 -    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
 -    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
 -    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
 -
      DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
      DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
      DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
      DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
      DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void register_cpu_props(DeviceState *dev)
 +{
 +    Property *prop;
 +
 +    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 +        qdev_property_add_static(dev, prop);
 +    }
 +}
 +
 +static Property riscv_cpu_properties[] = {
 +    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 +
 +    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
 +    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
 +    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
 +
      DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
      DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
 --
-.30.1
+.36.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
-the address bytes. Note only SPI mode is supported by SST flashes.
+true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
 tcg_gen_gvec_dup_i32().
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
 is required.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Suggested-by: Robert Bu <robert.bu@gmail.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++--
-file changed, 3 insertions(+)
+file changed, 10 insertions(+), 2 deletions(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/block/m25p80.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
-     s->needed_bytes = get_addr_length(s);
+         s1 = get_gpr(s, a->rs1, EXT_SIGN);
-     switch (get_man(s)) {
-     /* Dummy cycles - modeled with bytes writes instead of bits */
+         if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
-+    case MAN_SST:
+-            tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-+        s->needed_bytes += 1;
+-                                MAXSZ(s), MAXSZ(s), s1);
-+        break;
++            if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
-     case MAN_WINBOND:
++                TCGv_i64 s1_i64 = tcg_temp_new_i64();
-         s->needed_bytes += 8;
++                tcg_gen_ext_tl_i64(s1_i64, s1);
-         break;
++                tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
 +                                     MAXSZ(s), MAXSZ(s), s1_i64);
 +                tcg_temp_free_i64(s1_i64);
 +            } else {
 +                tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
 +                                    MAXSZ(s), MAXSZ(s), s1);
 +            }
          } else {
              TCGv_i32 desc;
              TCGv_i64 s1_i64 = tcg_temp_new_i64();
 --
-.30.1
+.36.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:

Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging (2022-06-09 08:25:17 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610

for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54:

target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 7.1

* Update MAINTAINERS
* Add support for Zmmul extension
* Fixup FDT errors when supplying device tree from the command line for virt machine
* Avoid overflowing the addr_config buffer in the SiFive PLIC
* Support -device loader addresses above 2GB
* Correctly wake from WFI on VS-level external interrupts
* Fixes for RV128 support
* Support Vector extension tail agnostic setting elements' bits to all 1s
* Don't expose the CPU properties on named CPUs
* Fix vector extension assert for RV32

----------------------------------------------------------------
Alistair Francis (4):
      MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section
      hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
      target/riscv: Don't expose the CPU properties on names CPUs
      target/riscv: trans_rvv: Avoid assert for RV32 and e64

Andrew Bresticker (1):
      target/riscv: Wake on VS-level external interrupts

Atish Patra (1):
      hw/riscv: virt: Generate fw_cfg DT node correctly

Frédéric Pétrot (1):
      target/riscv/debug.c: keep experimental rv128 support working

Jamie Iles (1):
      hw/core/loader: return image sizes as ssize_t

Weiwei Li (1):
      target/riscv: add support for zmmul extension v0.1

eopXD (16):
      target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
      target/riscv: rvv: Prune redundant access_type parameter passed
      target/riscv: rvv: Rename ambiguous esz
      target/riscv: rvv: Early exit when vstart >= vl
      target/riscv: rvv: Add tail agnostic for vv instructions
      target/riscv: rvv: Add tail agnostic for vector load / store instructions
      target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
      target/riscv: rvv: Add tail agnostic for vector integer shift instructions
      target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
      target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
      target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
      target/riscv: rvv: Add tail agnostic for vector floating-point instructions
      target/riscv: rvv: Add tail agnostic for vector reduction instructions
      target/riscv: rvv: Add tail agnostic for vector mask instructions
      target/riscv: rvv: Add tail agnostic for vector permutation instructions
      target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: Weiwei Li <liweiwei@iscas.ac.cn>

Add support for the zmmul extension v0.1. This extension includes all
multiplication operations from the M extension but not the divide ops.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                      |  1 +
 target/riscv/cpu.c                      |  7 +++++++
 target/riscv/insn_trans/trans_rvm.c.inc | 18 ++++++++++++------
 3 files changed, 20 insertions(+), 6 deletions(-)

From: Atish Patra <atishp@rivosinc.com>

fw_cfg DT node is generated after the create_fdt without any check
if the DT is being loaded from the commandline. This results in
FDT_ERR_EXISTS error if dtb is loaded from the commandline.

Generate fw_cfg node only if the DT is not loaded from the commandline.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220526203500.847165-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
     g_free(name);
 }
 
+static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
+{
+    char *nodename;
+    MachineState *mc = MACHINE(s);
+    hwaddr base = memmap[VIRT_FW_CFG].base;
+    hwaddr size = memmap[VIRT_FW_CFG].size;
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+}
+
 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
 {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     create_fdt_rtc(s, memmap, irq_mmio_phandle);
 
     create_fdt_flash(s, memmap);
+    create_fdt_fw_cfg(s, memmap);
 
 update_bootargs:
     if (cmdline && *cmdline) {
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 static FWCfgState *create_fw_cfg(const MachineState *mc)
 {
     hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
     FWCfgState *fw_cfg;
-    char *nodename;
 
     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
                                   &address_space_memory);
     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
 
-    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-    qemu_fdt_add_subnode(mc->fdt, nodename);
-    qemu_fdt_setprop_string(mc->fdt, nodename,
-                            "compatible", "qemu,fw-cfg-mmio");
-    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
-                                 2, base, 2, size);
-    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
-    g_free(nodename);
     return fw_cfg;
 }
 
-- 
2.36.1

From: Alistair Francis <alistair.francis@wdc.com>

Since commit ad40be27 "target/riscv: Support start kernel directly by
KVM" we have been overflowing the addr_config on "M,MS..."
configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.

This commit changes the loop in sifive_plic_create() from iterating over
the number of harts to just iterating over the addr_config. The
addr_config is based on the hart_config, and will contain interrup details
for all harts. This way we can't iterate past the end of addr_config.

Fixes: ad40be27084536 ("target/riscv: Support start kernel directly by KVM")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1050
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220601013631.196854-1-alistair.francis@opensource.wdc.com>
---
 hw/intc/sifive_plic.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t context_stride, uint32_t aperture_size)
 {
     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
-    int i, j = 0;
+    int i;
     SiFivePLICState *plic;
 
     assert(enable_stride == (enable_stride & -enable_stride));
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 
     plic = SIFIVE_PLIC(dev);
-    for (i = 0; i < num_harts; i++) {
-        CPUState *cpu = qemu_get_cpu(hartid_base + i);
 
-        if (plic->addr_config[j].mode == PLICMode_M) {
-            j++;
-            qdev_connect_gpio_out(dev, num_harts + i,
+    for (i = 0; i < plic->num_addrs; i++) {
+        int cpu_num = plic->addr_config[i].hartid;
+        CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num);
+
+        if (plic->addr_config[i].mode == PLICMode_M) {
+            qdev_connect_gpio_out(dev, num_harts + cpu_num,
                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
         }
-
-        if (plic->addr_config[j].mode == PLICMode_S) {
-            j++;
-            qdev_connect_gpio_out(dev, i,
+        if (plic->addr_config[i].mode == PLICMode_S) {
+            qdev_connect_gpio_out(dev, cpu_num,
                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
         }
     }
-- 
2.36.1

From: Jamie Iles <jamie@nuviainc.com>

Various loader functions return an int which limits images to 2GB which
is fine for things like a BIOS/kernel image, but if we want to be able
to load memory images or large ramdisks then any file over 2GB would
silently fail to load.

Cc: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211111141141.3295094-2-jamie@nuviainc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/loader.h      | 55 +++++++++++++--------------
 hw/arm/armv7m.c          |  2 +-
 hw/arm/boot.c            |  8 ++--
 hw/core/generic-loader.c |  2 +-
 hw/core/loader.c         | 81 +++++++++++++++++++++-------------------
 hw/i386/x86.c            |  2 +-
 hw/riscv/boot.c          |  5 ++-
 7 files changed, 80 insertions(+), 75 deletions(-)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
  *
  * Returns the size of the loaded image on success, -1 otherwise.
  */
-int load_image_targphys_as(const char *filename,
-                           hwaddr addr, uint64_t max_sz, AddressSpace *as);
+ssize_t load_image_targphys_as(const char *filename,
+                               hwaddr addr, uint64_t max_sz, AddressSpace *as);
 
 /**load_targphys_hex_as:
  * @filename: Path to the .hex file
@@ -XXX,XX +XXX,XX @@ int load_image_targphys_as(const char *filename,
  *
  * Returns the size of the loaded .hex file on success, -1 otherwise.
  */
-int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as);
+ssize_t load_targphys_hex_as(const char *filename, hwaddr *entry,
+                             AddressSpace *as);
 
 /** load_image_targphys:
  * Same as load_image_targphys_as(), but doesn't allow the caller to specify
  * an AddressSpace.
  */
-int load_image_targphys(const char *filename, hwaddr,
-                        uint64_t max_sz);
+ssize_t load_image_targphys(const char *filename, hwaddr,
+                            uint64_t max_sz);
 
 /**
  * load_image_mr: load an image into a memory region
@@ -XXX,XX +XXX,XX @@ int load_image_targphys(const char *filename, hwaddr,
  * If the file is larger than the memory region's size the call will fail.
  * Returns -1 on failure, or the size of the file.
  */
-int load_image_mr(const char *filename, MemoryRegion *mr);
+ssize_t load_image_mr(const char *filename, MemoryRegion *mr);
 
 /* This is the limit on the maximum uncompressed image size that
  * load_image_gzipped_buffer() and load_image_gzipped() will read. It prevents
@@ -XXX,XX +XXX,XX @@ int load_image_mr(const char *filename, MemoryRegion *mr);
  */
 #define LOAD_IMAGE_MAX_GUNZIP_BYTES (256 << 20)
 
-int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
-                              uint8_t **buffer);
-int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
+ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
+                                  uint8_t **buffer);
+ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
 
 #define ELF_LOAD_FAILED       -1
 #define ELF_LOAD_NOT_ELF      -2
@@ -XXX,XX +XXX,XX @@ ssize_t load_elf(const char *filename,
  */
 void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp);
 
-int load_aout(const char *filename, hwaddr addr, int max_sz,
-              int bswap_needed, hwaddr target_page_size);
+ssize_t load_aout(const char *filename, hwaddr addr, int max_sz,
+                  int bswap_needed, hwaddr target_page_size);
 
 #define LOAD_UIMAGE_LOADADDR_INVALID (-1)
 
@@ -XXX,XX +XXX,XX @@ int load_aout(const char *filename, hwaddr addr, int max_sz,
  *
  * Returns the size of the loaded image on success, -1 otherwise.
  */
-int load_uimage_as(const char *filename, hwaddr *ep,
-                   hwaddr *loadaddr, int *is_linux,
-                   uint64_t (*translate_fn)(void *, uint64_t),
-                   void *translate_opaque, AddressSpace *as);
+ssize_t load_uimage_as(const char *filename, hwaddr *ep,
+                       hwaddr *loadaddr, int *is_linux,
+                       uint64_t (*translate_fn)(void *, uint64_t),
+                       void *translate_opaque, AddressSpace *as);
 
 /** load_uimage:
  * Same as load_uimage_as(), but doesn't allow the caller to specify an
  * AddressSpace.
  */
-int load_uimage(const char *filename, hwaddr *ep,
-                hwaddr *loadaddr, int *is_linux,
-                uint64_t (*translate_fn)(void *, uint64_t),
-                void *translate_opaque);
+ssize_t load_uimage(const char *filename, hwaddr *ep,
+                    hwaddr *loadaddr, int *is_linux,
+                    uint64_t (*translate_fn)(void *, uint64_t),
+                    void *translate_opaque);
 
 /**
  * load_ramdisk_as:
@@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep,
  *
  * Returns the size of the loaded image on success, -1 otherwise.
  */
-int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
-                    AddressSpace *as);
+ssize_t load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
+                        AddressSpace *as);
 
 /**
  * load_ramdisk:
  * Same as load_ramdisk_as(), but doesn't allow the caller to specify
  * an AddressSpace.
  */
-int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz);
+ssize_t load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz);
 
 ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen);
 
@@ -XXX,XX +XXX,XX @@ void pstrcpy_targphys(const char *name,
 extern bool option_rom_has_mr;
 extern bool rom_file_has_mr;
 
-int rom_add_file(const char *file, const char *fw_dir,
-                 hwaddr addr, int32_t bootindex,
-                 bool option_rom, MemoryRegion *mr, AddressSpace *as);
+ssize_t rom_add_file(const char *file, const char *fw_dir,
+                     hwaddr addr, int32_t bootindex,
+                     bool option_rom, MemoryRegion *mr, AddressSpace *as);
 MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
                            size_t max_len, hwaddr addr,
                            const char *fw_file_name,
@@ -XXX,XX +XXX,XX @@ void hmp_info_roms(Monitor *mon, const QDict *qdict);
 #define rom_add_blob_fixed_as(_f, _b, _l, _a, _as)      \
     rom_add_blob(_f, _b, _l, _l, _a, NULL, NULL, NULL, _as, true)
 
-int rom_add_vga(const char *file);
-int rom_add_option(const char *file, int32_t bootindex);
+ssize_t rom_add_vga(const char *file);
+ssize_t rom_add_option(const char *file, int32_t bootindex);
 
 /* This is the usual maximum in uboot, so if a uImage overflows this, it would
  * overflow on real hardware too. */
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
 
 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
 {
-    int image_size;
+    ssize_t image_size;
     uint64_t entry;
     int big_endian;
     AddressSpace *as;
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque)
     return 0;
 }
 
-static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
+static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
                             uint64_t *lowaddr, uint64_t *highaddr,
                             int elf_machine, AddressSpace *as)
 {
@@ -XXX,XX +XXX,XX @@ static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
     } elf_header;
     int data_swab = 0;
     bool big_endian;
-    int64_t ret = -1;
+    ssize_t ret = -1;
     Error *err = NULL;
 
 
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
     /* Set up for a direct boot of a kernel image file. */
     CPUState *cs;
     AddressSpace *as = arm_boot_address_space(cpu, info);
-    int kernel_size;
+    ssize_t kernel_size;
     int initrd_size;
     int is_linux = 0;
     uint64_t elf_entry;
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
 
     if (kernel_size > info->ram_size) {
         error_report("kernel '%s' is too large to fit in RAM "
-                     "(kernel size %d, RAM size %" PRId64 ")",
+                     "(kernel size %zd, RAM size %" PRId64 ")",
                      info->kernel_filename, kernel_size, info->ram_size);
         exit(1);
     }
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -XXX,XX +XXX,XX @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
     GenericLoaderState *s = GENERIC_LOADER(dev);
     hwaddr entry;
     int big_endian;
-    int size = 0;
+    ssize_t size = 0;
 
     s->set_pc = false;
 
diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t read_targphys(const char *name,
     return did;
 }
 
-int load_image_targphys(const char *filename,
-                        hwaddr addr, uint64_t max_sz)
+ssize_t load_image_targphys(const char *filename,
+                            hwaddr addr, uint64_t max_sz)
 {
     return load_image_targphys_as(filename, addr, max_sz, NULL);
 }
 
 /* return the size or -1 if error */
-int load_image_targphys_as(const char *filename,
-                           hwaddr addr, uint64_t max_sz, AddressSpace *as)
+ssize_t load_image_targphys_as(const char *filename,
+                               hwaddr addr, uint64_t max_sz, AddressSpace *as)
 {
-    int size;
+    ssize_t size;
 
     size = get_image_size(filename);
     if (size < 0 || size > max_sz) {
@@ -XXX,XX +XXX,XX @@ int load_image_targphys_as(const char *filename,
     return size;
 }
 
-int load_image_mr(const char *filename, MemoryRegion *mr)
+ssize_t load_image_mr(const char *filename, MemoryRegion *mr)
 {
-    int size;
+    ssize_t size;
 
     if (!memory_access_is_direct(mr, false)) {
         /* Can only load an image into RAM or ROM */
@@ -XXX,XX +XXX,XX @@ static void bswap_ahdr(struct exec *e)
      : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
 
 
-int load_aout(const char *filename, hwaddr addr, int max_sz,
-              int bswap_needed, hwaddr target_page_size)
+ssize_t load_aout(const char *filename, hwaddr addr, int max_sz,
+                  int bswap_needed, hwaddr target_page_size)
 {
     int fd;
     ssize_t size, ret;
@@ -XXX,XX +XXX,XX @@ toosmall:
 }
 
 /* Load a U-Boot image.  */
-static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
-                            int *is_linux, uint8_t image_type,
-                            uint64_t (*translate_fn)(void *, uint64_t),
-                            void *translate_opaque, AddressSpace *as)
+static ssize_t load_uboot_image(const char *filename, hwaddr *ep,
+                                hwaddr *loadaddr, int *is_linux,
+                                uint8_t image_type,
+                                uint64_t (*translate_fn)(void *, uint64_t),
+                                void *translate_opaque, AddressSpace *as)
 {
     int fd;
-    int size;
+    ssize_t size;
     hwaddr address;
     uboot_image_header_t h;
     uboot_image_header_t *hdr = &h;
@@ -XXX,XX +XXX,XX @@ out:
     return ret;
 }
 
-int load_uimage(const char *filename, hwaddr *ep, hwaddr *loadaddr,
-                int *is_linux,
-                uint64_t (*translate_fn)(void *, uint64_t),
-                void *translate_opaque)
+ssize_t load_uimage(const char *filename, hwaddr *ep, hwaddr *loadaddr,
+                    int *is_linux,
+                    uint64_t (*translate_fn)(void *, uint64_t),
+                    void *translate_opaque)
 {
     return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL,
                             translate_fn, translate_opaque, NULL);
 }
 
-int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr,
-                   int *is_linux,
-                   uint64_t (*translate_fn)(void *, uint64_t),
-                   void *translate_opaque, AddressSpace *as)
+ssize_t load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr,
+                       int *is_linux,
+                       uint64_t (*translate_fn)(void *, uint64_t),
+                       void *translate_opaque, AddressSpace *as)
 {
     return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL,
                             translate_fn, translate_opaque, as);
 }
 
 /* Load a ramdisk.  */
-int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz)
+ssize_t load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz)
 {
     return load_ramdisk_as(filename, addr, max_sz, NULL);
 }
 
-int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
-                    AddressSpace *as)
+ssize_t load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz,
+                        AddressSpace *as)
 {
     return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK,
                             NULL, NULL, as);
 }
 
 /* Load a gzip-compressed kernel to a dynamically allocated buffer. */
-int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
-                              uint8_t **buffer)
+ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
+                                  uint8_t **buffer)
 {
     uint8_t *compressed_data = NULL;
     uint8_t *data = NULL;
@@ -XXX,XX +XXX,XX @@ int load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
 }
 
 /* Load a gzip-compressed kernel. */
-int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
+ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
 {
-    int bytes;
+    ssize_t bytes;
     uint8_t *data;
 
     bytes = load_image_gzipped_buffer(filename, max_sz, &data);
@@ -XXX,XX +XXX,XX @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro)
     return data;
 }
 
-int rom_add_file(const char *file, const char *fw_dir,
-                 hwaddr addr, int32_t bootindex,
-                 bool option_rom, MemoryRegion *mr,
-                 AddressSpace *as)
+ssize_t rom_add_file(const char *file, const char *fw_dir,
+                     hwaddr addr, int32_t bootindex,
+                     bool option_rom, MemoryRegion *mr,
+                     AddressSpace *as)
 {
     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
     Rom *rom;
-    int rc, fd = -1;
+    ssize_t rc;
+    int fd = -1;
     char devpath[100];
 
     if (as && mr) {
@@ -XXX,XX +XXX,XX @@ int rom_add_file(const char *file, const char *fw_dir,
     lseek(fd, 0, SEEK_SET);
     rc = read(fd, rom->data, rom->datasize);
     if (rc != rom->datasize) {
-        fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n",
+        fprintf(stderr, "rom: file %-20s: read error: rc=%zd (expected %zd)\n",
                 rom->name, rc, rom->datasize);
         goto err;
     }
@@ -XXX,XX +XXX,XX @@ int rom_add_elf_program(const char *name, GMappedFile *mapped_file, void *data,
     return 0;
 }
 
-int rom_add_vga(const char *file)
+ssize_t rom_add_vga(const char *file)
 {
     return rom_add_file(file, "vgaroms", 0, -1, true, NULL, NULL);
 }
 
-int rom_add_option(const char *file, int32_t bootindex)
+ssize_t rom_add_option(const char *file, int32_t bootindex)
 {
     return rom_add_file(file, "genroms", 0, bootindex, true, NULL, NULL);
 }
@@ -XXX,XX +XXX,XX @@ out:
 }
 
 /* return size or -1 if error */
-int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as)
+ssize_t load_targphys_hex_as(const char *filename, hwaddr *entry,
+                             AddressSpace *as)
 {
     gsize hex_blob_size;
     gchar *hex_blob;
-    int total_size = 0;
+    ssize_t total_size = 0;
 
     if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) {
         return -1;
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -XXX,XX +XXX,XX @@ void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
     char *filename;
     MemoryRegion *bios, *isa_bios;
     int bios_size, isa_bios_size;
-    int ret;
+    ssize_t ret;
 
     /* BIOS load */
     bios_name = ms->firmware ?: default_firmware;
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb)
 {
-    uint64_t firmware_entry, firmware_size, firmware_end;
+    uint64_t firmware_entry, firmware_end;
+    ssize_t firmware_size;
 
     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
                          &firmware_entry, NULL, &firmware_end, NULL,
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start)
 {
-    int size;
+    ssize_t size;
 
     /*
      * We want to put the initrd far enough into RAM that when the
-- 
2.36.1

From: Andrew Bresticker <abrestic@rivosinc.com>

Whether or not VSEIP is pending isn't reflected in env->mip and must
instead be determined from hstatus.vgein and hgeip. As a result a
CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
specified in the privileged ISA. Just use riscv_cpu_all_pending()
instead, which already accounts for VSEIP.

Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu.c        | 2 +-
 target/riscv/cpu_helper.c | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 uint8_t riscv_cpu_default_priority(int irq);
+uint64_t riscv_cpu_all_pending(CPURISCVState *env);
 int riscv_cpu_mirq_pending(CPURISCVState *env);
 int riscv_cpu_sirq_pending(CPURISCVState *env);
 int riscv_cpu_vsirq_pending(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
      * Definition of the WFI instruction requires it to ignore the privilege
      * mode and delegation registers, but respect individual enables
      */
-    return (env->mip & env->mie) != 0;
+    return riscv_cpu_all_pending(env) != 0;
 #else
     return true;
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
     return best_irq;
 }
 
-static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+uint64_t riscv_cpu_all_pending(CPURISCVState *env)
 {
     uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
     uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
-- 
2.36.1

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ static inline target_ulong trigger_type(CPURISCVState *env,
         tdata1 = RV32_TYPE(type);
         break;
     case MXL_RV64:
+    case MXL_RV128:
         tdata1 = RV64_TYPE(type);
         break;
     default:
@@ -XXX,XX +XXX,XX @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
         tdata1 = RV32_TYPE(t);
         break;
     case MXL_RV64:
+    case MXL_RV128:
         type = extract64(val, 60, 4);
         dmode = extract64(val, 59, 1);
         tdata1 = RV64_TYPE(t);
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

No functional change intended in this commit.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 1132 +++++++++++++++++-----------------
 1 file changed, 565 insertions(+), 567 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
 
 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
                        CPURISCVState *env, uint32_t desc,
-                       uint32_t esz, uint32_t dsz,
                        opivv2_fn *fn)
 {
     uint32_t vm = vext_vm(desc);
@@ -XXX,XX +XXX,XX @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
 }
 
 /* generate the helpers for OPIVV */
-#define GEN_VEXT_VV(NAME, ESZ, DSZ)                       \
+#define GEN_VEXT_VV(NAME)                                 \
 void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
-    do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ,     \
+    do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
                do_##NAME);                                \
 }
 
-GEN_VEXT_VV(vadd_vv_b, 1, 1)
-GEN_VEXT_VV(vadd_vv_h, 2, 2)
-GEN_VEXT_VV(vadd_vv_w, 4, 4)
-GEN_VEXT_VV(vadd_vv_d, 8, 8)
-GEN_VEXT_VV(vsub_vv_b, 1, 1)
-GEN_VEXT_VV(vsub_vv_h, 2, 2)
-GEN_VEXT_VV(vsub_vv_w, 4, 4)
-GEN_VEXT_VV(vsub_vv_d, 8, 8)
+GEN_VEXT_VV(vadd_vv_b)
+GEN_VEXT_VV(vadd_vv_h)
+GEN_VEXT_VV(vadd_vv_w)
+GEN_VEXT_VV(vadd_vv_d)
+GEN_VEXT_VV(vsub_vv_b)
+GEN_VEXT_VV(vsub_vv_h)
+GEN_VEXT_VV(vsub_vv_w)
+GEN_VEXT_VV(vsub_vv_d)
 
 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
 
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
 
 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
                        CPURISCVState *env, uint32_t desc,
-                       uint32_t esz, uint32_t dsz,
                        opivx2_fn fn)
 {
     uint32_t vm = vext_vm(desc);
@@ -XXX,XX +XXX,XX @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
 }
 
 /* generate the helpers for OPIVX */
-#define GEN_VEXT_VX(NAME, ESZ, DSZ)                       \
+#define GEN_VEXT_VX(NAME)                                 \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
-    do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ,      \
+    do_vext_vx(vd, v0, s1, vs2, env, desc,                \
                do_##NAME);                                \
 }
 
-GEN_VEXT_VX(vadd_vx_b, 1, 1)
-GEN_VEXT_VX(vadd_vx_h, 2, 2)
-GEN_VEXT_VX(vadd_vx_w, 4, 4)
-GEN_VEXT_VX(vadd_vx_d, 8, 8)
-GEN_VEXT_VX(vsub_vx_b, 1, 1)
-GEN_VEXT_VX(vsub_vx_h, 2, 2)
-GEN_VEXT_VX(vsub_vx_w, 4, 4)
-GEN_VEXT_VX(vsub_vx_d, 8, 8)
-GEN_VEXT_VX(vrsub_vx_b, 1, 1)
-GEN_VEXT_VX(vrsub_vx_h, 2, 2)
-GEN_VEXT_VX(vrsub_vx_w, 4, 4)
-GEN_VEXT_VX(vrsub_vx_d, 8, 8)
+GEN_VEXT_VX(vadd_vx_b)
+GEN_VEXT_VX(vadd_vx_h)
+GEN_VEXT_VX(vadd_vx_w)
+GEN_VEXT_VX(vadd_vx_d)
+GEN_VEXT_VX(vsub_vx_b)
+GEN_VEXT_VX(vsub_vx_h)
+GEN_VEXT_VX(vsub_vx_w)
+GEN_VEXT_VX(vsub_vx_d)
+GEN_VEXT_VX(vrsub_vx_b)
+GEN_VEXT_VX(vrsub_vx_h)
+GEN_VEXT_VX(vrsub_vx_w)
+GEN_VEXT_VX(vrsub_vx_d)
 
 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
-GEN_VEXT_VV(vwaddu_vv_b, 1, 2)
-GEN_VEXT_VV(vwaddu_vv_h, 2, 4)
-GEN_VEXT_VV(vwaddu_vv_w, 4, 8)
-GEN_VEXT_VV(vwsubu_vv_b, 1, 2)
-GEN_VEXT_VV(vwsubu_vv_h, 2, 4)
-GEN_VEXT_VV(vwsubu_vv_w, 4, 8)
-GEN_VEXT_VV(vwadd_vv_b, 1, 2)
-GEN_VEXT_VV(vwadd_vv_h, 2, 4)
-GEN_VEXT_VV(vwadd_vv_w, 4, 8)
-GEN_VEXT_VV(vwsub_vv_b, 1, 2)
-GEN_VEXT_VV(vwsub_vv_h, 2, 4)
-GEN_VEXT_VV(vwsub_vv_w, 4, 8)
-GEN_VEXT_VV(vwaddu_wv_b, 1, 2)
-GEN_VEXT_VV(vwaddu_wv_h, 2, 4)
-GEN_VEXT_VV(vwaddu_wv_w, 4, 8)
-GEN_VEXT_VV(vwsubu_wv_b, 1, 2)
-GEN_VEXT_VV(vwsubu_wv_h, 2, 4)
-GEN_VEXT_VV(vwsubu_wv_w, 4, 8)
-GEN_VEXT_VV(vwadd_wv_b, 1, 2)
-GEN_VEXT_VV(vwadd_wv_h, 2, 4)
-GEN_VEXT_VV(vwadd_wv_w, 4, 8)
-GEN_VEXT_VV(vwsub_wv_b, 1, 2)
-GEN_VEXT_VV(vwsub_wv_h, 2, 4)
-GEN_VEXT_VV(vwsub_wv_w, 4, 8)
+GEN_VEXT_VV(vwaddu_vv_b)
+GEN_VEXT_VV(vwaddu_vv_h)
+GEN_VEXT_VV(vwaddu_vv_w)
+GEN_VEXT_VV(vwsubu_vv_b)
+GEN_VEXT_VV(vwsubu_vv_h)
+GEN_VEXT_VV(vwsubu_vv_w)
+GEN_VEXT_VV(vwadd_vv_b)
+GEN_VEXT_VV(vwadd_vv_h)
+GEN_VEXT_VV(vwadd_vv_w)
+GEN_VEXT_VV(vwsub_vv_b)
+GEN_VEXT_VV(vwsub_vv_h)
+GEN_VEXT_VV(vwsub_vv_w)
+GEN_VEXT_VV(vwaddu_wv_b)
+GEN_VEXT_VV(vwaddu_wv_h)
+GEN_VEXT_VV(vwaddu_wv_w)
+GEN_VEXT_VV(vwsubu_wv_b)
+GEN_VEXT_VV(vwsubu_wv_h)
+GEN_VEXT_VV(vwsubu_wv_w)
+GEN_VEXT_VV(vwadd_wv_b)
+GEN_VEXT_VV(vwadd_wv_h)
+GEN_VEXT_VV(vwadd_wv_w)
+GEN_VEXT_VV(vwsub_wv_b)
+GEN_VEXT_VV(vwsub_wv_h)
+GEN_VEXT_VV(vwsub_wv_w)
 
 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
-GEN_VEXT_VX(vwaddu_vx_b, 1, 2)
-GEN_VEXT_VX(vwaddu_vx_h, 2, 4)
-GEN_VEXT_VX(vwaddu_vx_w, 4, 8)
-GEN_VEXT_VX(vwsubu_vx_b, 1, 2)
-GEN_VEXT_VX(vwsubu_vx_h, 2, 4)
-GEN_VEXT_VX(vwsubu_vx_w, 4, 8)
-GEN_VEXT_VX(vwadd_vx_b, 1, 2)
-GEN_VEXT_VX(vwadd_vx_h, 2, 4)
-GEN_VEXT_VX(vwadd_vx_w, 4, 8)
-GEN_VEXT_VX(vwsub_vx_b, 1, 2)
-GEN_VEXT_VX(vwsub_vx_h, 2, 4)
-GEN_VEXT_VX(vwsub_vx_w, 4, 8)
-GEN_VEXT_VX(vwaddu_wx_b, 1, 2)
-GEN_VEXT_VX(vwaddu_wx_h, 2, 4)
-GEN_VEXT_VX(vwaddu_wx_w, 4, 8)
-GEN_VEXT_VX(vwsubu_wx_b, 1, 2)
-GEN_VEXT_VX(vwsubu_wx_h, 2, 4)
-GEN_VEXT_VX(vwsubu_wx_w, 4, 8)
-GEN_VEXT_VX(vwadd_wx_b, 1, 2)
-GEN_VEXT_VX(vwadd_wx_h, 2, 4)
-GEN_VEXT_VX(vwadd_wx_w, 4, 8)
-GEN_VEXT_VX(vwsub_wx_b, 1, 2)
-GEN_VEXT_VX(vwsub_wx_h, 2, 4)
-GEN_VEXT_VX(vwsub_wx_w, 4, 8)
+GEN_VEXT_VX(vwaddu_vx_b)
+GEN_VEXT_VX(vwaddu_vx_h)
+GEN_VEXT_VX(vwaddu_vx_w)
+GEN_VEXT_VX(vwsubu_vx_b)
+GEN_VEXT_VX(vwsubu_vx_h)
+GEN_VEXT_VX(vwsubu_vx_w)
+GEN_VEXT_VX(vwadd_vx_b)
+GEN_VEXT_VX(vwadd_vx_h)
+GEN_VEXT_VX(vwadd_vx_w)
+GEN_VEXT_VX(vwsub_vx_b)
+GEN_VEXT_VX(vwsub_vx_h)
+GEN_VEXT_VX(vwsub_vx_w)
+GEN_VEXT_VX(vwaddu_wx_b)
+GEN_VEXT_VX(vwaddu_wx_h)
+GEN_VEXT_VX(vwaddu_wx_w)
+GEN_VEXT_VX(vwsubu_wx_b)
+GEN_VEXT_VX(vwsubu_wx_h)
+GEN_VEXT_VX(vwsubu_wx_w)
+GEN_VEXT_VX(vwadd_wx_b)
+GEN_VEXT_VX(vwadd_wx_h)
+GEN_VEXT_VX(vwadd_wx_w)
+GEN_VEXT_VX(vwsub_wx_b)
+GEN_VEXT_VX(vwsub_wx_h)
+GEN_VEXT_VX(vwsub_wx_w)
 
 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
 #define DO_VADC(N, M, C) (N + M + C)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
-GEN_VEXT_VV(vand_vv_b, 1, 1)
-GEN_VEXT_VV(vand_vv_h, 2, 2)
-GEN_VEXT_VV(vand_vv_w, 4, 4)
-GEN_VEXT_VV(vand_vv_d, 8, 8)
-GEN_VEXT_VV(vor_vv_b, 1, 1)
-GEN_VEXT_VV(vor_vv_h, 2, 2)
-GEN_VEXT_VV(vor_vv_w, 4, 4)
-GEN_VEXT_VV(vor_vv_d, 8, 8)
-GEN_VEXT_VV(vxor_vv_b, 1, 1)
-GEN_VEXT_VV(vxor_vv_h, 2, 2)
-GEN_VEXT_VV(vxor_vv_w, 4, 4)
-GEN_VEXT_VV(vxor_vv_d, 8, 8)
+GEN_VEXT_VV(vand_vv_b)
+GEN_VEXT_VV(vand_vv_h)
+GEN_VEXT_VV(vand_vv_w)
+GEN_VEXT_VV(vand_vv_d)
+GEN_VEXT_VV(vor_vv_b)
+GEN_VEXT_VV(vor_vv_h)
+GEN_VEXT_VV(vor_vv_w)
+GEN_VEXT_VV(vor_vv_d)
+GEN_VEXT_VV(vxor_vv_b)
+GEN_VEXT_VV(vxor_vv_h)
+GEN_VEXT_VV(vxor_vv_w)
+GEN_VEXT_VV(vxor_vv_d)
 
 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
-GEN_VEXT_VX(vand_vx_b, 1, 1)
-GEN_VEXT_VX(vand_vx_h, 2, 2)
-GEN_VEXT_VX(vand_vx_w, 4, 4)
-GEN_VEXT_VX(vand_vx_d, 8, 8)
-GEN_VEXT_VX(vor_vx_b, 1, 1)
-GEN_VEXT_VX(vor_vx_h, 2, 2)
-GEN_VEXT_VX(vor_vx_w, 4, 4)
-GEN_VEXT_VX(vor_vx_d, 8, 8)
-GEN_VEXT_VX(vxor_vx_b, 1, 1)
-GEN_VEXT_VX(vxor_vx_h, 2, 2)
-GEN_VEXT_VX(vxor_vx_w, 4, 4)
-GEN_VEXT_VX(vxor_vx_d, 8, 8)
+GEN_VEXT_VX(vand_vx_b)
+GEN_VEXT_VX(vand_vx_h)
+GEN_VEXT_VX(vand_vx_w)
+GEN_VEXT_VX(vand_vx_d)
+GEN_VEXT_VX(vor_vx_b)
+GEN_VEXT_VX(vor_vx_h)
+GEN_VEXT_VX(vor_vx_w)
+GEN_VEXT_VX(vor_vx_d)
+GEN_VEXT_VX(vxor_vx_b)
+GEN_VEXT_VX(vxor_vx_h)
+GEN_VEXT_VX(vxor_vx_w)
+GEN_VEXT_VX(vxor_vx_d)
 
 /* Vector Single-Width Bit Shift Instructions */
 #define DO_SLL(N, M)  (N << (M))
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
-GEN_VEXT_VV(vminu_vv_b, 1, 1)
-GEN_VEXT_VV(vminu_vv_h, 2, 2)
-GEN_VEXT_VV(vminu_vv_w, 4, 4)
-GEN_VEXT_VV(vminu_vv_d, 8, 8)
-GEN_VEXT_VV(vmin_vv_b, 1, 1)
-GEN_VEXT_VV(vmin_vv_h, 2, 2)
-GEN_VEXT_VV(vmin_vv_w, 4, 4)
-GEN_VEXT_VV(vmin_vv_d, 8, 8)
-GEN_VEXT_VV(vmaxu_vv_b, 1, 1)
-GEN_VEXT_VV(vmaxu_vv_h, 2, 2)
-GEN_VEXT_VV(vmaxu_vv_w, 4, 4)
-GEN_VEXT_VV(vmaxu_vv_d, 8, 8)
-GEN_VEXT_VV(vmax_vv_b, 1, 1)
-GEN_VEXT_VV(vmax_vv_h, 2, 2)
-GEN_VEXT_VV(vmax_vv_w, 4, 4)
-GEN_VEXT_VV(vmax_vv_d, 8, 8)
+GEN_VEXT_VV(vminu_vv_b)
+GEN_VEXT_VV(vminu_vv_h)
+GEN_VEXT_VV(vminu_vv_w)
+GEN_VEXT_VV(vminu_vv_d)
+GEN_VEXT_VV(vmin_vv_b)
+GEN_VEXT_VV(vmin_vv_h)
+GEN_VEXT_VV(vmin_vv_w)
+GEN_VEXT_VV(vmin_vv_d)
+GEN_VEXT_VV(vmaxu_vv_b)
+GEN_VEXT_VV(vmaxu_vv_h)
+GEN_VEXT_VV(vmaxu_vv_w)
+GEN_VEXT_VV(vmaxu_vv_d)
+GEN_VEXT_VV(vmax_vv_b)
+GEN_VEXT_VV(vmax_vv_h)
+GEN_VEXT_VV(vmax_vv_w)
+GEN_VEXT_VV(vmax_vv_d)
 
 RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
 RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
-GEN_VEXT_VX(vminu_vx_b, 1, 1)
-GEN_VEXT_VX(vminu_vx_h, 2, 2)
-GEN_VEXT_VX(vminu_vx_w, 4, 4)
-GEN_VEXT_VX(vminu_vx_d, 8, 8)
-GEN_VEXT_VX(vmin_vx_b, 1, 1)
-GEN_VEXT_VX(vmin_vx_h, 2, 2)
-GEN_VEXT_VX(vmin_vx_w, 4, 4)
-GEN_VEXT_VX(vmin_vx_d, 8, 8)
-GEN_VEXT_VX(vmaxu_vx_b, 1, 1)
-GEN_VEXT_VX(vmaxu_vx_h, 2, 2)
-GEN_VEXT_VX(vmaxu_vx_w, 4, 4)
-GEN_VEXT_VX(vmaxu_vx_d, 8, 8)
-GEN_VEXT_VX(vmax_vx_b, 1, 1)
-GEN_VEXT_VX(vmax_vx_h, 2, 2)
-GEN_VEXT_VX(vmax_vx_w, 4, 4)
-GEN_VEXT_VX(vmax_vx_d, 8, 8)
+GEN_VEXT_VX(vminu_vx_b)
+GEN_VEXT_VX(vminu_vx_h)
+GEN_VEXT_VX(vminu_vx_w)
+GEN_VEXT_VX(vminu_vx_d)
+GEN_VEXT_VX(vmin_vx_b)
+GEN_VEXT_VX(vmin_vx_h)
+GEN_VEXT_VX(vmin_vx_w)
+GEN_VEXT_VX(vmin_vx_d)
+GEN_VEXT_VX(vmaxu_vx_b)
+GEN_VEXT_VX(vmaxu_vx_h)
+GEN_VEXT_VX(vmaxu_vx_w)
+GEN_VEXT_VX(vmaxu_vx_d)
+GEN_VEXT_VX(vmax_vx_b)
+GEN_VEXT_VX(vmax_vx_h)
+GEN_VEXT_VX(vmax_vx_w)
+GEN_VEXT_VX(vmax_vx_d)
 
 /* Vector Single-Width Integer Multiply Instructions */
 #define DO_MUL(N, M) (N * M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
-GEN_VEXT_VV(vmul_vv_b, 1, 1)
-GEN_VEXT_VV(vmul_vv_h, 2, 2)
-GEN_VEXT_VV(vmul_vv_w, 4, 4)
-GEN_VEXT_VV(vmul_vv_d, 8, 8)
+GEN_VEXT_VV(vmul_vv_b)
+GEN_VEXT_VV(vmul_vv_h)
+GEN_VEXT_VV(vmul_vv_w)
+GEN_VEXT_VV(vmul_vv_d)
 
 static int8_t do_mulh_b(int8_t s2, int8_t s1)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
 RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
 RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
 RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
-GEN_VEXT_VV(vmulh_vv_b, 1, 1)
-GEN_VEXT_VV(vmulh_vv_h, 2, 2)
-GEN_VEXT_VV(vmulh_vv_w, 4, 4)
-GEN_VEXT_VV(vmulh_vv_d, 8, 8)
-GEN_VEXT_VV(vmulhu_vv_b, 1, 1)
-GEN_VEXT_VV(vmulhu_vv_h, 2, 2)
-GEN_VEXT_VV(vmulhu_vv_w, 4, 4)
-GEN_VEXT_VV(vmulhu_vv_d, 8, 8)
-GEN_VEXT_VV(vmulhsu_vv_b, 1, 1)
-GEN_VEXT_VV(vmulhsu_vv_h, 2, 2)
-GEN_VEXT_VV(vmulhsu_vv_w, 4, 4)
-GEN_VEXT_VV(vmulhsu_vv_d, 8, 8)
+GEN_VEXT_VV(vmulh_vv_b)
+GEN_VEXT_VV(vmulh_vv_h)
+GEN_VEXT_VV(vmulh_vv_w)
+GEN_VEXT_VV(vmulh_vv_d)
+GEN_VEXT_VV(vmulhu_vv_b)
+GEN_VEXT_VV(vmulhu_vv_h)
+GEN_VEXT_VV(vmulhu_vv_w)
+GEN_VEXT_VV(vmulhu_vv_d)
+GEN_VEXT_VV(vmulhsu_vv_b)
+GEN_VEXT_VV(vmulhsu_vv_h)
+GEN_VEXT_VV(vmulhsu_vv_w)
+GEN_VEXT_VV(vmulhsu_vv_d)
 
 RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
 RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
 RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
 RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
 RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
-GEN_VEXT_VX(vmul_vx_b, 1, 1)
-GEN_VEXT_VX(vmul_vx_h, 2, 2)
-GEN_VEXT_VX(vmul_vx_w, 4, 4)
-GEN_VEXT_VX(vmul_vx_d, 8, 8)
-GEN_VEXT_VX(vmulh_vx_b, 1, 1)
-GEN_VEXT_VX(vmulh_vx_h, 2, 2)
-GEN_VEXT_VX(vmulh_vx_w, 4, 4)
-GEN_VEXT_VX(vmulh_vx_d, 8, 8)
-GEN_VEXT_VX(vmulhu_vx_b, 1, 1)
-GEN_VEXT_VX(vmulhu_vx_h, 2, 2)
-GEN_VEXT_VX(vmulhu_vx_w, 4, 4)
-GEN_VEXT_VX(vmulhu_vx_d, 8, 8)
-GEN_VEXT_VX(vmulhsu_vx_b, 1, 1)
-GEN_VEXT_VX(vmulhsu_vx_h, 2, 2)
-GEN_VEXT_VX(vmulhsu_vx_w, 4, 4)
-GEN_VEXT_VX(vmulhsu_vx_d, 8, 8)
+GEN_VEXT_VX(vmul_vx_b)
+GEN_VEXT_VX(vmul_vx_h)
+GEN_VEXT_VX(vmul_vx_w)
+GEN_VEXT_VX(vmul_vx_d)
+GEN_VEXT_VX(vmulh_vx_b)
+GEN_VEXT_VX(vmulh_vx_h)
+GEN_VEXT_VX(vmulh_vx_w)
+GEN_VEXT_VX(vmulh_vx_d)
+GEN_VEXT_VX(vmulhu_vx_b)
+GEN_VEXT_VX(vmulhu_vx_h)
+GEN_VEXT_VX(vmulhu_vx_w)
+GEN_VEXT_VX(vmulhu_vx_d)
+GEN_VEXT_VX(vmulhsu_vx_b)
+GEN_VEXT_VX(vmulhsu_vx_h)
+GEN_VEXT_VX(vmulhsu_vx_w)
+GEN_VEXT_VX(vmulhsu_vx_d)
 
 /* Vector Integer Divide Instructions */
 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
-GEN_VEXT_VV(vdivu_vv_b, 1, 1)
-GEN_VEXT_VV(vdivu_vv_h, 2, 2)
-GEN_VEXT_VV(vdivu_vv_w, 4, 4)
-GEN_VEXT_VV(vdivu_vv_d, 8, 8)
-GEN_VEXT_VV(vdiv_vv_b, 1, 1)
-GEN_VEXT_VV(vdiv_vv_h, 2, 2)
-GEN_VEXT_VV(vdiv_vv_w, 4, 4)
-GEN_VEXT_VV(vdiv_vv_d, 8, 8)
-GEN_VEXT_VV(vremu_vv_b, 1, 1)
-GEN_VEXT_VV(vremu_vv_h, 2, 2)
-GEN_VEXT_VV(vremu_vv_w, 4, 4)
-GEN_VEXT_VV(vremu_vv_d, 8, 8)
-GEN_VEXT_VV(vrem_vv_b, 1, 1)
-GEN_VEXT_VV(vrem_vv_h, 2, 2)
-GEN_VEXT_VV(vrem_vv_w, 4, 4)
-GEN_VEXT_VV(vrem_vv_d, 8, 8)
+GEN_VEXT_VV(vdivu_vv_b)
+GEN_VEXT_VV(vdivu_vv_h)
+GEN_VEXT_VV(vdivu_vv_w)
+GEN_VEXT_VV(vdivu_vv_d)
+GEN_VEXT_VV(vdiv_vv_b)
+GEN_VEXT_VV(vdiv_vv_h)
+GEN_VEXT_VV(vdiv_vv_w)
+GEN_VEXT_VV(vdiv_vv_d)
+GEN_VEXT_VV(vremu_vv_b)
+GEN_VEXT_VV(vremu_vv_h)
+GEN_VEXT_VV(vremu_vv_w)
+GEN_VEXT_VV(vremu_vv_d)
+GEN_VEXT_VV(vrem_vv_b)
+GEN_VEXT_VV(vrem_vv_h)
+GEN_VEXT_VV(vrem_vv_w)
+GEN_VEXT_VV(vrem_vv_d)
 
 RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
 RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
-GEN_VEXT_VX(vdivu_vx_b, 1, 1)
-GEN_VEXT_VX(vdivu_vx_h, 2, 2)
-GEN_VEXT_VX(vdivu_vx_w, 4, 4)
-GEN_VEXT_VX(vdivu_vx_d, 8, 8)
-GEN_VEXT_VX(vdiv_vx_b, 1, 1)
-GEN_VEXT_VX(vdiv_vx_h, 2, 2)
-GEN_VEXT_VX(vdiv_vx_w, 4, 4)
-GEN_VEXT_VX(vdiv_vx_d, 8, 8)
-GEN_VEXT_VX(vremu_vx_b, 1, 1)
-GEN_VEXT_VX(vremu_vx_h, 2, 2)
-GEN_VEXT_VX(vremu_vx_w, 4, 4)
-GEN_VEXT_VX(vremu_vx_d, 8, 8)
-GEN_VEXT_VX(vrem_vx_b, 1, 1)
-GEN_VEXT_VX(vrem_vx_h, 2, 2)
-GEN_VEXT_VX(vrem_vx_w, 4, 4)
-GEN_VEXT_VX(vrem_vx_d, 8, 8)
+GEN_VEXT_VX(vdivu_vx_b)
+GEN_VEXT_VX(vdivu_vx_h)
+GEN_VEXT_VX(vdivu_vx_w)
+GEN_VEXT_VX(vdivu_vx_d)
+GEN_VEXT_VX(vdiv_vx_b)
+GEN_VEXT_VX(vdiv_vx_h)
+GEN_VEXT_VX(vdiv_vx_w)
+GEN_VEXT_VX(vdiv_vx_d)
+GEN_VEXT_VX(vremu_vx_b)
+GEN_VEXT_VX(vremu_vx_h)
+GEN_VEXT_VX(vremu_vx_w)
+GEN_VEXT_VX(vremu_vx_d)
+GEN_VEXT_VX(vrem_vx_b)
+GEN_VEXT_VX(vrem_vx_h)
+GEN_VEXT_VX(vrem_vx_w)
+GEN_VEXT_VX(vrem_vx_d)
 
 /* Vector Widening Integer Multiply Instructions */
 RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
-GEN_VEXT_VV(vwmul_vv_b, 1, 2)
-GEN_VEXT_VV(vwmul_vv_h, 2, 4)
-GEN_VEXT_VV(vwmul_vv_w, 4, 8)
-GEN_VEXT_VV(vwmulu_vv_b, 1, 2)
-GEN_VEXT_VV(vwmulu_vv_h, 2, 4)
-GEN_VEXT_VV(vwmulu_vv_w, 4, 8)
-GEN_VEXT_VV(vwmulsu_vv_b, 1, 2)
-GEN_VEXT_VV(vwmulsu_vv_h, 2, 4)
-GEN_VEXT_VV(vwmulsu_vv_w, 4, 8)
+GEN_VEXT_VV(vwmul_vv_b)
+GEN_VEXT_VV(vwmul_vv_h)
+GEN_VEXT_VV(vwmul_vv_w)
+GEN_VEXT_VV(vwmulu_vv_b)
+GEN_VEXT_VV(vwmulu_vv_h)
+GEN_VEXT_VV(vwmulu_vv_w)
+GEN_VEXT_VV(vwmulsu_vv_b)
+GEN_VEXT_VV(vwmulsu_vv_h)
+GEN_VEXT_VV(vwmulsu_vv_w)
 
 RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
 RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
-GEN_VEXT_VX(vwmul_vx_b, 1, 2)
-GEN_VEXT_VX(vwmul_vx_h, 2, 4)
-GEN_VEXT_VX(vwmul_vx_w, 4, 8)
-GEN_VEXT_VX(vwmulu_vx_b, 1, 2)
-GEN_VEXT_VX(vwmulu_vx_h, 2, 4)
-GEN_VEXT_VX(vwmulu_vx_w, 4, 8)
-GEN_VEXT_VX(vwmulsu_vx_b, 1, 2)
-GEN_VEXT_VX(vwmulsu_vx_h, 2, 4)
-GEN_VEXT_VX(vwmulsu_vx_w, 4, 8)
+GEN_VEXT_VX(vwmul_vx_b)
+GEN_VEXT_VX(vwmul_vx_h)
+GEN_VEXT_VX(vwmul_vx_w)
+GEN_VEXT_VX(vwmulu_vx_b)
+GEN_VEXT_VX(vwmulu_vx_h)
+GEN_VEXT_VX(vwmulu_vx_w)
+GEN_VEXT_VX(vwmulsu_vx_b)
+GEN_VEXT_VX(vwmulsu_vx_h)
+GEN_VEXT_VX(vwmulsu_vx_w)
 
 /* Vector Single-Width Integer Multiply-Add Instructions */
 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
-GEN_VEXT_VV(vmacc_vv_b, 1, 1)
-GEN_VEXT_VV(vmacc_vv_h, 2, 2)
-GEN_VEXT_VV(vmacc_vv_w, 4, 4)
-GEN_VEXT_VV(vmacc_vv_d, 8, 8)
-GEN_VEXT_VV(vnmsac_vv_b, 1, 1)
-GEN_VEXT_VV(vnmsac_vv_h, 2, 2)
-GEN_VEXT_VV(vnmsac_vv_w, 4, 4)
-GEN_VEXT_VV(vnmsac_vv_d, 8, 8)
-GEN_VEXT_VV(vmadd_vv_b, 1, 1)
-GEN_VEXT_VV(vmadd_vv_h, 2, 2)
-GEN_VEXT_VV(vmadd_vv_w, 4, 4)
-GEN_VEXT_VV(vmadd_vv_d, 8, 8)
-GEN_VEXT_VV(vnmsub_vv_b, 1, 1)
-GEN_VEXT_VV(vnmsub_vv_h, 2, 2)
-GEN_VEXT_VV(vnmsub_vv_w, 4, 4)
-GEN_VEXT_VV(vnmsub_vv_d, 8, 8)
+GEN_VEXT_VV(vmacc_vv_b)
+GEN_VEXT_VV(vmacc_vv_h)
+GEN_VEXT_VV(vmacc_vv_w)
+GEN_VEXT_VV(vmacc_vv_d)
+GEN_VEXT_VV(vnmsac_vv_b)
+GEN_VEXT_VV(vnmsac_vv_h)
+GEN_VEXT_VV(vnmsac_vv_w)
+GEN_VEXT_VV(vnmsac_vv_d)
+GEN_VEXT_VV(vmadd_vv_b)
+GEN_VEXT_VV(vmadd_vv_h)
+GEN_VEXT_VV(vmadd_vv_w)
+GEN_VEXT_VV(vmadd_vv_d)
+GEN_VEXT_VV(vnmsub_vv_b)
+GEN_VEXT_VV(vnmsub_vv_h)
+GEN_VEXT_VV(vnmsub_vv_w)
+GEN_VEXT_VV(vnmsub_vv_d)
 
 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
 static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
-GEN_VEXT_VX(vmacc_vx_b, 1, 1)
-GEN_VEXT_VX(vmacc_vx_h, 2, 2)
-GEN_VEXT_VX(vmacc_vx_w, 4, 4)
-GEN_VEXT_VX(vmacc_vx_d, 8, 8)
-GEN_VEXT_VX(vnmsac_vx_b, 1, 1)
-GEN_VEXT_VX(vnmsac_vx_h, 2, 2)
-GEN_VEXT_VX(vnmsac_vx_w, 4, 4)
-GEN_VEXT_VX(vnmsac_vx_d, 8, 8)
-GEN_VEXT_VX(vmadd_vx_b, 1, 1)
-GEN_VEXT_VX(vmadd_vx_h, 2, 2)
-GEN_VEXT_VX(vmadd_vx_w, 4, 4)
-GEN_VEXT_VX(vmadd_vx_d, 8, 8)
-GEN_VEXT_VX(vnmsub_vx_b, 1, 1)
-GEN_VEXT_VX(vnmsub_vx_h, 2, 2)
-GEN_VEXT_VX(vnmsub_vx_w, 4, 4)
-GEN_VEXT_VX(vnmsub_vx_d, 8, 8)
+GEN_VEXT_VX(vmacc_vx_b)
+GEN_VEXT_VX(vmacc_vx_h)
+GEN_VEXT_VX(vmacc_vx_w)
+GEN_VEXT_VX(vmacc_vx_d)
+GEN_VEXT_VX(vnmsac_vx_b)
+GEN_VEXT_VX(vnmsac_vx_h)
+GEN_VEXT_VX(vnmsac_vx_w)
+GEN_VEXT_VX(vnmsac_vx_d)
+GEN_VEXT_VX(vmadd_vx_b)
+GEN_VEXT_VX(vmadd_vx_h)
+GEN_VEXT_VX(vmadd_vx_w)
+GEN_VEXT_VX(vmadd_vx_d)
+GEN_VEXT_VX(vnmsub_vx_b)
+GEN_VEXT_VX(vnmsub_vx_h)
+GEN_VEXT_VX(vnmsub_vx_w)
+GEN_VEXT_VX(vnmsub_vx_d)
 
 /* Vector Widening Integer Multiply-Add Instructions */
 RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
-GEN_VEXT_VV(vwmaccu_vv_b, 1, 2)
-GEN_VEXT_VV(vwmaccu_vv_h, 2, 4)
-GEN_VEXT_VV(vwmaccu_vv_w, 4, 8)
-GEN_VEXT_VV(vwmacc_vv_b, 1, 2)
-GEN_VEXT_VV(vwmacc_vv_h, 2, 4)
-GEN_VEXT_VV(vwmacc_vv_w, 4, 8)
-GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2)
-GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4)
-GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8)
+GEN_VEXT_VV(vwmaccu_vv_b)
+GEN_VEXT_VV(vwmaccu_vv_h)
+GEN_VEXT_VV(vwmaccu_vv_w)
+GEN_VEXT_VV(vwmacc_vv_b)
+GEN_VEXT_VV(vwmacc_vv_h)
+GEN_VEXT_VV(vwmacc_vv_w)
+GEN_VEXT_VV(vwmaccsu_vv_b)
+GEN_VEXT_VV(vwmaccsu_vv_h)
+GEN_VEXT_VV(vwmaccsu_vv_w)
 
 RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
 RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
-GEN_VEXT_VX(vwmaccu_vx_b, 1, 2)
-GEN_VEXT_VX(vwmaccu_vx_h, 2, 4)
-GEN_VEXT_VX(vwmaccu_vx_w, 4, 8)
-GEN_VEXT_VX(vwmacc_vx_b, 1, 2)
-GEN_VEXT_VX(vwmacc_vx_h, 2, 4)
-GEN_VEXT_VX(vwmacc_vx_w, 4, 8)
-GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2)
-GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4)
-GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8)
-GEN_VEXT_VX(vwmaccus_vx_b, 1, 2)
-GEN_VEXT_VX(vwmaccus_vx_h, 2, 4)
-GEN_VEXT_VX(vwmaccus_vx_w, 4, 8)
+GEN_VEXT_VX(vwmaccu_vx_b)
+GEN_VEXT_VX(vwmaccu_vx_h)
+GEN_VEXT_VX(vwmaccu_vx_w)
+GEN_VEXT_VX(vwmacc_vx_b)
+GEN_VEXT_VX(vwmacc_vx_h)
+GEN_VEXT_VX(vwmacc_vx_w)
+GEN_VEXT_VX(vwmaccsu_vx_b)
+GEN_VEXT_VX(vwmaccsu_vx_h)
+GEN_VEXT_VX(vwmaccsu_vx_w)
+GEN_VEXT_VX(vwmaccus_vx_b)
+GEN_VEXT_VX(vwmaccus_vx_h)
+GEN_VEXT_VX(vwmaccus_vx_w)
 
 /* Vector Integer Merge and Move Instructions */
 #define GEN_VEXT_VMV_VV(NAME, ETYPE, H)                              \
@@ -XXX,XX +XXX,XX @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
 static inline void
 vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
              CPURISCVState *env,
-             uint32_t desc, uint32_t esz, uint32_t dsz,
+             uint32_t desc,
              opivv2_rm_fn *fn)
 {
     uint32_t vm = vext_vm(desc);
@@ -XXX,XX +XXX,XX @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
 }
 
 /* generate helpers for fixed point instructions with OPIVV format */
-#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ)                          \
+#define GEN_VEXT_VV_RM(NAME)                                    \
 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,     \
                   CPURISCVState *env, uint32_t desc)            \
 {                                                               \
-    vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ,         \
+    vext_vv_rm_2(vd, v0, vs1, vs2, env, desc,                   \
                  do_##NAME);                                    \
 }
 
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
 RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
 RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
 RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
-GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vsaddu_vv_b)
+GEN_VEXT_VV_RM(vsaddu_vv_h)
+GEN_VEXT_VV_RM(vsaddu_vv_w)
+GEN_VEXT_VV_RM(vsaddu_vv_d)
 
 typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
                           CPURISCVState *env, int vxrm);
@@ -XXX,XX +XXX,XX @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
 static inline void
 vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
              CPURISCVState *env,
-             uint32_t desc, uint32_t esz, uint32_t dsz,
+             uint32_t desc,
              opivx2_rm_fn *fn)
 {
     uint32_t vm = vext_vm(desc);
@@ -XXX,XX +XXX,XX @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
 }
 
 /* generate helpers for fixed point instructions with OPIVX format */
-#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ)                    \
+#define GEN_VEXT_VX_RM(NAME)                              \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
         void *vs2, CPURISCVState *env, uint32_t desc)     \
 {                                                         \
-    vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ,    \
+    vext_vx_rm_2(vd, v0, s1, vs2, env, desc,              \
                  do_##NAME);                              \
 }
 
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
 RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
 RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
 RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
-GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vsaddu_vx_b)
+GEN_VEXT_VX_RM(vsaddu_vx_h)
+GEN_VEXT_VX_RM(vsaddu_vx_w)
+GEN_VEXT_VX_RM(vsaddu_vx_d)
 
 static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
 RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
 RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
 RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
-GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vsadd_vv_b)
+GEN_VEXT_VV_RM(vsadd_vv_h)
+GEN_VEXT_VV_RM(vsadd_vv_w)
+GEN_VEXT_VV_RM(vsadd_vv_d)
 
 RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
 RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
 RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
 RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
-GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vsadd_vx_b)
+GEN_VEXT_VX_RM(vsadd_vx_h)
+GEN_VEXT_VX_RM(vsadd_vx_w)
+GEN_VEXT_VX_RM(vsadd_vx_d)
 
 static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
 RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
 RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
 RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
-GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vssubu_vv_b)
+GEN_VEXT_VV_RM(vssubu_vv_h)
+GEN_VEXT_VV_RM(vssubu_vv_w)
+GEN_VEXT_VV_RM(vssubu_vv_d)
 
 RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
 RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
 RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
 RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
-GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vssubu_vx_b)
+GEN_VEXT_VX_RM(vssubu_vx_h)
+GEN_VEXT_VX_RM(vssubu_vx_w)
+GEN_VEXT_VX_RM(vssubu_vx_d)
 
 static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
 RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
 RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
 RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
-GEN_VEXT_VV_RM(vssub_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vssub_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vssub_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vssub_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vssub_vv_b)
+GEN_VEXT_VV_RM(vssub_vv_h)
+GEN_VEXT_VV_RM(vssub_vv_w)
+GEN_VEXT_VV_RM(vssub_vv_d)
 
 RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
 RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
 RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
 RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
-GEN_VEXT_VX_RM(vssub_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vssub_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vssub_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vssub_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vssub_vx_b)
+GEN_VEXT_VX_RM(vssub_vx_h)
+GEN_VEXT_VX_RM(vssub_vx_w)
+GEN_VEXT_VX_RM(vssub_vx_d)
 
 /* Vector Single-Width Averaging Add and Subtract */
 static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
-GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vaadd_vv_b)
+GEN_VEXT_VV_RM(vaadd_vv_h)
+GEN_VEXT_VV_RM(vaadd_vv_w)
+GEN_VEXT_VV_RM(vaadd_vv_d)
 
 RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
-GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vaadd_vx_b)
+GEN_VEXT_VX_RM(vaadd_vx_h)
+GEN_VEXT_VX_RM(vaadd_vx_w)
+GEN_VEXT_VX_RM(vaadd_vx_d)
 
 static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
                                uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
-GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vaaddu_vv_b)
+GEN_VEXT_VV_RM(vaaddu_vv_h)
+GEN_VEXT_VV_RM(vaaddu_vv_w)
+GEN_VEXT_VV_RM(vaaddu_vv_d)
 
 RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
-GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vaaddu_vx_b)
+GEN_VEXT_VX_RM(vaaddu_vx_h)
+GEN_VEXT_VX_RM(vaaddu_vx_w)
+GEN_VEXT_VX_RM(vaaddu_vx_d)
 
 static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
-GEN_VEXT_VV_RM(vasub_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vasub_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vasub_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vasub_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vasub_vv_b)
+GEN_VEXT_VV_RM(vasub_vv_h)
+GEN_VEXT_VV_RM(vasub_vv_w)
+GEN_VEXT_VV_RM(vasub_vv_d)
 
 RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
-GEN_VEXT_VX_RM(vasub_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vasub_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vasub_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vasub_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vasub_vx_b)
+GEN_VEXT_VX_RM(vasub_vx_h)
+GEN_VEXT_VX_RM(vasub_vx_w)
+GEN_VEXT_VX_RM(vasub_vx_d)
 
 static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
                                uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
-GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vasubu_vv_b)
+GEN_VEXT_VV_RM(vasubu_vv_h)
+GEN_VEXT_VV_RM(vasubu_vv_w)
+GEN_VEXT_VV_RM(vasubu_vv_d)
 
 RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
-GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vasubu_vx_b)
+GEN_VEXT_VX_RM(vasubu_vx_h)
+GEN_VEXT_VX_RM(vasubu_vx_w)
+GEN_VEXT_VX_RM(vasubu_vx_d)
 
 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
 static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
 RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
 RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
 RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
-GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vsmul_vv_b)
+GEN_VEXT_VV_RM(vsmul_vv_h)
+GEN_VEXT_VV_RM(vsmul_vv_w)
+GEN_VEXT_VV_RM(vsmul_vv_d)
 
 RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
 RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
 RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
 RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
-GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vsmul_vx_b)
+GEN_VEXT_VX_RM(vsmul_vx_h)
+GEN_VEXT_VX_RM(vsmul_vx_w)
+GEN_VEXT_VX_RM(vsmul_vx_d)
 
 /* Vector Single-Width Scaling Shift Instructions */
 static inline uint8_t
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
 RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
 RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
 RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
-GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vssrl_vv_b)
+GEN_VEXT_VV_RM(vssrl_vv_h)
+GEN_VEXT_VV_RM(vssrl_vv_w)
+GEN_VEXT_VV_RM(vssrl_vv_d)
 
 RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
 RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
 RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
 RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
-GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vssrl_vx_b)
+GEN_VEXT_VX_RM(vssrl_vx_h)
+GEN_VEXT_VX_RM(vssrl_vx_w)
+GEN_VEXT_VX_RM(vssrl_vx_d)
 
 static inline int8_t
 vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
 RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
 RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
 RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
-GEN_VEXT_VV_RM(vssra_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vssra_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vssra_vv_w, 4, 4)
-GEN_VEXT_VV_RM(vssra_vv_d, 8, 8)
+GEN_VEXT_VV_RM(vssra_vv_b)
+GEN_VEXT_VV_RM(vssra_vv_h)
+GEN_VEXT_VV_RM(vssra_vv_w)
+GEN_VEXT_VV_RM(vssra_vv_d)
 
 RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
 RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
 RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
 RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
-GEN_VEXT_VX_RM(vssra_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vssra_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vssra_vx_w, 4, 4)
-GEN_VEXT_VX_RM(vssra_vx_d, 8, 8)
+GEN_VEXT_VX_RM(vssra_vx_b)
+GEN_VEXT_VX_RM(vssra_vx_h)
+GEN_VEXT_VX_RM(vssra_vx_w)
+GEN_VEXT_VX_RM(vssra_vx_d)
 
 /* Vector Narrowing Fixed-Point Clip Instructions */
 static inline int8_t
@@ -XXX,XX +XXX,XX @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
 RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
 RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
 RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1)
-GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2)
-GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4)
+GEN_VEXT_VV_RM(vnclip_wv_b)
+GEN_VEXT_VV_RM(vnclip_wv_h)
+GEN_VEXT_VV_RM(vnclip_wv_w)
 
 RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
 RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
 RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1)
-GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2)
-GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4)
+GEN_VEXT_VX_RM(vnclip_wx_b)
+GEN_VEXT_VX_RM(vnclip_wx_h)
+GEN_VEXT_VX_RM(vnclip_wx_w)
 
 static inline uint8_t
 vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -XXX,XX +XXX,XX @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
 RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
 RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
 RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1)
-GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2)
-GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4)
+GEN_VEXT_VV_RM(vnclipu_wv_b)
+GEN_VEXT_VV_RM(vnclipu_wv_h)
+GEN_VEXT_VV_RM(vnclipu_wv_w)
 
 RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
 RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
 RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1)
-GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2)
-GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4)
+GEN_VEXT_VX_RM(vnclipu_wx_b)
+GEN_VEXT_VX_RM(vnclipu_wx_h)
+GEN_VEXT_VX_RM(vnclipu_wx_w)
 
 /*
  *** Vector Float Point Arithmetic Instructions
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \
     *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status);         \
 }
 
-#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ)                   \
+#define GEN_VEXT_VV_ENV(NAME)                             \
 void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
 RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
 RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
 RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
-GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfadd_vv_h)
+GEN_VEXT_VV_ENV(vfadd_vv_w)
+GEN_VEXT_VV_ENV(vfadd_vv_d)
 
 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)        \
 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
     *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
 }
 
-#define GEN_VEXT_VF(NAME, ESZ, DSZ)                       \
+#define GEN_VEXT_VF(NAME)                                 \
 void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
 RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
 RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
 RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
-GEN_VEXT_VF(vfadd_vf_h, 2, 2)
-GEN_VEXT_VF(vfadd_vf_w, 4, 4)
-GEN_VEXT_VF(vfadd_vf_d, 8, 8)
+GEN_VEXT_VF(vfadd_vf_h)
+GEN_VEXT_VF(vfadd_vf_w)
+GEN_VEXT_VF(vfadd_vf_d)
 
 RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
 RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
 RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
-GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfsub_vv_h)
+GEN_VEXT_VV_ENV(vfsub_vv_w)
+GEN_VEXT_VV_ENV(vfsub_vv_d)
 RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
 RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
 RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
-GEN_VEXT_VF(vfsub_vf_h, 2, 2)
-GEN_VEXT_VF(vfsub_vf_w, 4, 4)
-GEN_VEXT_VF(vfsub_vf_d, 8, 8)
+GEN_VEXT_VF(vfsub_vf_h)
+GEN_VEXT_VF(vfsub_vf_w)
+GEN_VEXT_VF(vfsub_vf_d)
 
 static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
 RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
 RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
-GEN_VEXT_VF(vfrsub_vf_h, 2, 2)
-GEN_VEXT_VF(vfrsub_vf_w, 4, 4)
-GEN_VEXT_VF(vfrsub_vf_d, 8, 8)
+GEN_VEXT_VF(vfrsub_vf_h)
+GEN_VEXT_VF(vfrsub_vf_w)
+GEN_VEXT_VF(vfrsub_vf_d)
 
 /* Vector Widening Floating-Point Add/Subtract Instructions */
 static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
 RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
-GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwadd_vv_h)
+GEN_VEXT_VV_ENV(vfwadd_vv_w)
 RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
 RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
-GEN_VEXT_VF(vfwadd_vf_h, 2, 4)
-GEN_VEXT_VF(vfwadd_vf_w, 4, 8)
+GEN_VEXT_VF(vfwadd_vf_h)
+GEN_VEXT_VF(vfwadd_vf_w)
 
 static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
 RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
-GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwsub_vv_h)
+GEN_VEXT_VV_ENV(vfwsub_vv_w)
 RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
 RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
-GEN_VEXT_VF(vfwsub_vf_h, 2, 4)
-GEN_VEXT_VF(vfwsub_vf_w, 4, 8)
+GEN_VEXT_VF(vfwsub_vf_h)
+GEN_VEXT_VF(vfwsub_vf_w)
 
 static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
 RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
-GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwadd_wv_h)
+GEN_VEXT_VV_ENV(vfwadd_wv_w)
 RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
 RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
-GEN_VEXT_VF(vfwadd_wf_h, 2, 4)
-GEN_VEXT_VF(vfwadd_wf_w, 4, 8)
+GEN_VEXT_VF(vfwadd_wf_h)
+GEN_VEXT_VF(vfwadd_wf_w)
 
 static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
 RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
-GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwsub_wv_h)
+GEN_VEXT_VV_ENV(vfwsub_wv_w)
 RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
 RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
-GEN_VEXT_VF(vfwsub_wf_h, 2, 4)
-GEN_VEXT_VF(vfwsub_wf_w, 4, 8)
+GEN_VEXT_VF(vfwsub_wf_h)
+GEN_VEXT_VF(vfwsub_wf_w)
 
 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
 RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
 RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
 RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
-GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmul_vv_h)
+GEN_VEXT_VV_ENV(vfmul_vv_w)
+GEN_VEXT_VV_ENV(vfmul_vv_d)
 RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
 RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
 RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
-GEN_VEXT_VF(vfmul_vf_h, 2, 2)
-GEN_VEXT_VF(vfmul_vf_w, 4, 4)
-GEN_VEXT_VF(vfmul_vf_d, 8, 8)
+GEN_VEXT_VF(vfmul_vf_h)
+GEN_VEXT_VF(vfmul_vf_w)
+GEN_VEXT_VF(vfmul_vf_d)
 
 RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
 RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
 RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
-GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfdiv_vv_h)
+GEN_VEXT_VV_ENV(vfdiv_vv_w)
+GEN_VEXT_VV_ENV(vfdiv_vv_d)
 RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
 RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
 RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
-GEN_VEXT_VF(vfdiv_vf_h, 2, 2)
-GEN_VEXT_VF(vfdiv_vf_w, 4, 4)
-GEN_VEXT_VF(vfdiv_vf_d, 8, 8)
+GEN_VEXT_VF(vfdiv_vf_h)
+GEN_VEXT_VF(vfdiv_vf_w)
+GEN_VEXT_VF(vfdiv_vf_d)
 
 static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
 RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
 RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
-GEN_VEXT_VF(vfrdiv_vf_h, 2, 2)
-GEN_VEXT_VF(vfrdiv_vf_w, 4, 4)
-GEN_VEXT_VF(vfrdiv_vf_d, 8, 8)
+GEN_VEXT_VF(vfrdiv_vf_h)
+GEN_VEXT_VF(vfrdiv_vf_w)
+GEN_VEXT_VF(vfrdiv_vf_d)
 
 /* Vector Widening Floating-Point Multiply */
 static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
 }
 RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
 RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
-GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwmul_vv_h)
+GEN_VEXT_VV_ENV(vfwmul_vv_w)
 RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
 RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
-GEN_VEXT_VF(vfwmul_vf_h, 2, 4)
-GEN_VEXT_VF(vfwmul_vf_w, 4, 8)
+GEN_VEXT_VF(vfwmul_vf_h)
+GEN_VEXT_VF(vfwmul_vf_w)
 
 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
 #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)       \
@@ -XXX,XX +XXX,XX @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
 RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
 RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
-GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmacc_vv_h)
+GEN_VEXT_VV_ENV(vfmacc_vv_w)
+GEN_VEXT_VV_ENV(vfmacc_vv_d)
 
 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)           \
 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
 RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
 RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
 RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
-GEN_VEXT_VF(vfmacc_vf_h, 2, 2)
-GEN_VEXT_VF(vfmacc_vf_w, 4, 4)
-GEN_VEXT_VF(vfmacc_vf_d, 8, 8)
+GEN_VEXT_VF(vfmacc_vf_h)
+GEN_VEXT_VF(vfmacc_vf_w)
+GEN_VEXT_VF(vfmacc_vf_d)
 
 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
 RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
 RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
-GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfnmacc_vv_h)
+GEN_VEXT_VV_ENV(vfnmacc_vv_w)
+GEN_VEXT_VV_ENV(vfnmacc_vv_d)
 RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
 RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
 RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
-GEN_VEXT_VF(vfnmacc_vf_h, 2, 2)
-GEN_VEXT_VF(vfnmacc_vf_w, 4, 4)
-GEN_VEXT_VF(vfnmacc_vf_d, 8, 8)
+GEN_VEXT_VF(vfnmacc_vf_h)
+GEN_VEXT_VF(vfnmacc_vf_w)
+GEN_VEXT_VF(vfnmacc_vf_d)
 
 static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
 RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
 RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
-GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmsac_vv_h)
+GEN_VEXT_VV_ENV(vfmsac_vv_w)
+GEN_VEXT_VV_ENV(vfmsac_vv_d)
 RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
 RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
 RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
-GEN_VEXT_VF(vfmsac_vf_h, 2, 2)
-GEN_VEXT_VF(vfmsac_vf_w, 4, 4)
-GEN_VEXT_VF(vfmsac_vf_d, 8, 8)
+GEN_VEXT_VF(vfmsac_vf_h)
+GEN_VEXT_VF(vfmsac_vf_w)
+GEN_VEXT_VF(vfmsac_vf_d)
 
 static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
 RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
 RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
-GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfnmsac_vv_h)
+GEN_VEXT_VV_ENV(vfnmsac_vv_w)
+GEN_VEXT_VV_ENV(vfnmsac_vv_d)
 RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
 RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
 RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
-GEN_VEXT_VF(vfnmsac_vf_h, 2, 2)
-GEN_VEXT_VF(vfnmsac_vf_w, 4, 4)
-GEN_VEXT_VF(vfnmsac_vf_d, 8, 8)
+GEN_VEXT_VF(vfnmsac_vf_h)
+GEN_VEXT_VF(vfnmsac_vf_w)
+GEN_VEXT_VF(vfnmsac_vf_d)
 
 static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
 RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
 RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
-GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmadd_vv_h)
+GEN_VEXT_VV_ENV(vfmadd_vv_w)
+GEN_VEXT_VV_ENV(vfmadd_vv_d)
 RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
 RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
 RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
-GEN_VEXT_VF(vfmadd_vf_h, 2, 2)
-GEN_VEXT_VF(vfmadd_vf_w, 4, 4)
-GEN_VEXT_VF(vfmadd_vf_d, 8, 8)
+GEN_VEXT_VF(vfmadd_vf_h)
+GEN_VEXT_VF(vfmadd_vf_w)
+GEN_VEXT_VF(vfmadd_vf_d)
 
 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
 RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
 RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
-GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfnmadd_vv_h)
+GEN_VEXT_VV_ENV(vfnmadd_vv_w)
+GEN_VEXT_VV_ENV(vfnmadd_vv_d)
 RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
 RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
 RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
-GEN_VEXT_VF(vfnmadd_vf_h, 2, 2)
-GEN_VEXT_VF(vfnmadd_vf_w, 4, 4)
-GEN_VEXT_VF(vfnmadd_vf_d, 8, 8)
+GEN_VEXT_VF(vfnmadd_vf_h)
+GEN_VEXT_VF(vfnmadd_vf_w)
+GEN_VEXT_VF(vfnmadd_vf_d)
 
 static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
 RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
 RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
-GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmsub_vv_h)
+GEN_VEXT_VV_ENV(vfmsub_vv_w)
+GEN_VEXT_VV_ENV(vfmsub_vv_d)
 RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
 RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
 RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
-GEN_VEXT_VF(vfmsub_vf_h, 2, 2)
-GEN_VEXT_VF(vfmsub_vf_w, 4, 4)
-GEN_VEXT_VF(vfmsub_vf_d, 8, 8)
+GEN_VEXT_VF(vfmsub_vf_h)
+GEN_VEXT_VF(vfmsub_vf_w)
+GEN_VEXT_VF(vfmsub_vf_d)
 
 static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
 RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
 RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
-GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfnmsub_vv_h)
+GEN_VEXT_VV_ENV(vfnmsub_vv_w)
+GEN_VEXT_VV_ENV(vfnmsub_vv_d)
 RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
 RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
 RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
-GEN_VEXT_VF(vfnmsub_vf_h, 2, 2)
-GEN_VEXT_VF(vfnmsub_vf_w, 4, 4)
-GEN_VEXT_VF(vfnmsub_vf_d, 8, 8)
+GEN_VEXT_VF(vfnmsub_vf_h)
+GEN_VEXT_VF(vfnmsub_vf_w)
+GEN_VEXT_VF(vfnmsub_vf_d)
 
 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
 static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
 RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
-GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwmacc_vv_h)
+GEN_VEXT_VV_ENV(vfwmacc_vv_w)
 RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
 RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
-GEN_VEXT_VF(vfwmacc_vf_h, 2, 4)
-GEN_VEXT_VF(vfwmacc_vf_w, 4, 8)
+GEN_VEXT_VF(vfwmacc_vf_h)
+GEN_VEXT_VF(vfwmacc_vf_w)
 
 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
 RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_h)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_w)
 RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
 RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
-GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4)
-GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8)
+GEN_VEXT_VF(vfwnmacc_vf_h)
+GEN_VEXT_VF(vfwnmacc_vf_w)
 
 static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
 RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
-GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwmsac_vv_h)
+GEN_VEXT_VV_ENV(vfwmsac_vv_w)
 RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
 RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
-GEN_VEXT_VF(vfwmsac_vf_h, 2, 4)
-GEN_VEXT_VF(vfwmsac_vf_w, 4, 8)
+GEN_VEXT_VF(vfwmsac_vf_h)
+GEN_VEXT_VF(vfwmsac_vf_w)
 
 static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
 RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_h)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_w)
 RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
 RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
-GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4)
-GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8)
+GEN_VEXT_VF(vfwnmsac_vf_h)
+GEN_VEXT_VF(vfwnmsac_vf_w)
 
 /* Vector Floating-Point Square-Root Instruction */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i,      \
     *((TD *)vd + HD(i)) = OP(s2, &env->fp_status);     \
 }
 
-#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ)                 \
+#define GEN_VEXT_V_ENV(NAME)                           \
 void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
         CPURISCVState *env, uint32_t desc)             \
 {                                                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
 RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
 RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
 RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
-GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfsqrt_v_h)
+GEN_VEXT_V_ENV(vfsqrt_v_w)
+GEN_VEXT_V_ENV(vfsqrt_v_d)
 
 /*
  * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frsqrt7_d(float64 f, float_status *s)
 RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
 RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
 RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
-GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfrsqrt7_v_h)
+GEN_VEXT_V_ENV(vfrsqrt7_v_w)
+GEN_VEXT_V_ENV(vfrsqrt7_v_d)
 
 /*
  * Vector Floating-Point Reciprocal Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frec7_d(float64 f, float_status *s)
 RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
 RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
 RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
-GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfrec7_v_h)
+GEN_VEXT_V_ENV(vfrec7_v_w)
+GEN_VEXT_V_ENV(vfrec7_v_d)
 
 /* Vector Floating-Point MIN/MAX Instructions */
 RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
 RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
 RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
-GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmin_vv_h)
+GEN_VEXT_VV_ENV(vfmin_vv_w)
+GEN_VEXT_VV_ENV(vfmin_vv_d)
 RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
 RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
 RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
-GEN_VEXT_VF(vfmin_vf_h, 2, 2)
-GEN_VEXT_VF(vfmin_vf_w, 4, 4)
-GEN_VEXT_VF(vfmin_vf_d, 8, 8)
+GEN_VEXT_VF(vfmin_vf_h)
+GEN_VEXT_VF(vfmin_vf_w)
+GEN_VEXT_VF(vfmin_vf_d)
 
 RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
 RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
 RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
-GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfmax_vv_h)
+GEN_VEXT_VV_ENV(vfmax_vv_w)
+GEN_VEXT_VV_ENV(vfmax_vv_d)
 RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
 RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
 RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
-GEN_VEXT_VF(vfmax_vf_h, 2, 2)
-GEN_VEXT_VF(vfmax_vf_w, 4, 4)
-GEN_VEXT_VF(vfmax_vf_d, 8, 8)
+GEN_VEXT_VF(vfmax_vf_h)
+GEN_VEXT_VF(vfmax_vf_w)
+GEN_VEXT_VF(vfmax_vf_d)
 
 /* Vector Floating-Point Sign-Injection Instructions */
 static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
 RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
 RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
-GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfsgnj_vv_h)
+GEN_VEXT_VV_ENV(vfsgnj_vv_w)
+GEN_VEXT_VV_ENV(vfsgnj_vv_d)
 RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
 RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
 RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
-GEN_VEXT_VF(vfsgnj_vf_h, 2, 2)
-GEN_VEXT_VF(vfsgnj_vf_w, 4, 4)
-GEN_VEXT_VF(vfsgnj_vf_d, 8, 8)
+GEN_VEXT_VF(vfsgnj_vf_h)
+GEN_VEXT_VF(vfsgnj_vf_w)
+GEN_VEXT_VF(vfsgnj_vf_d)
 
 static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
 RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
 RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_h)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_w)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_d)
 RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
 RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
 RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
-GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2)
-GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4)
-GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8)
+GEN_VEXT_VF(vfsgnjn_vf_h)
+GEN_VEXT_VF(vfsgnjn_vf_w)
+GEN_VEXT_VF(vfsgnjn_vf_d)
 
 static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
 RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
 RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_h)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_w)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_d)
 RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
 RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
 RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
-GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2)
-GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4)
-GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8)
+GEN_VEXT_VF(vfsgnjx_vf_h)
+GEN_VEXT_VF(vfsgnjx_vf_w)
+GEN_VEXT_VF(vfsgnjx_vf_d)
 
 /* Vector Floating-Point Compare Instructions */
 #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP)            \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i)      \
     *((TD *)vd + HD(i)) = OP(s2);                      \
 }
 
-#define GEN_VEXT_V(NAME, ESZ, DSZ)                     \
+#define GEN_VEXT_V(NAME)                               \
 void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
                   CPURISCVState *env, uint32_t desc)   \
 {                                                      \
@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1)
 RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
 RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
 RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
-GEN_VEXT_V(vfclass_v_h, 2, 2)
-GEN_VEXT_V(vfclass_v_w, 4, 4)
-GEN_VEXT_V(vfclass_v_d, 8, 8)
+GEN_VEXT_V(vfclass_v_h)
+GEN_VEXT_V(vfclass_v_w)
+GEN_VEXT_V(vfclass_v_d)
 
 /* Vector Floating-Point Merge Instruction */
 #define GEN_VFMERGE_VF(NAME, ETYPE, H)                        \
@@ -XXX,XX +XXX,XX @@ GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_h)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_w)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_d)
 
 /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
 RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
 RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
 RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_h)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_w)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_d)
 
 /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
 RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
 RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
 RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_h)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_w)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_d)
 
 /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
 RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
 RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
 RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_h)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_w)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
 
 /* Widening Floating-Point/Integer Type-Convert Instructions */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
 /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
 RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
 RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w)
 
 /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */
 RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32)
 RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_h)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_w)
 
 /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w)
 
 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
 RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
 RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
 RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_b)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_h)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_w)
 
 /*
  * vfwcvt.f.f.v vd, vs2, vm
@@ -XXX,XX +XXX,XX @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
 
 RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16)
 RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_h)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
 
 /* Narrowing Floating-Point/Integer Type-Convert Instructions */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w)
 
 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
 RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
 RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
 RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w)
 
 /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
 RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
 RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w)
 
 /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
 RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
 RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w)
 
 /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
 static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
 
 RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
 RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w)
 
 /*
  *** Vector Reduction Operations
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

No functional change intended in this commit.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-2@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 35 ++++++++++++++++-------------------
 1 file changed, 16 insertions(+), 19 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
                  target_ulong stride, CPURISCVState *env,
                  uint32_t desc, uint32_t vm,
                  vext_ldst_elem_fn *ldst_elem,
-                 uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+                 uint32_t esz, uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base,               \
 {                                                                       \
     uint32_t vm = vext_vm(desc);                                        \
     vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN,      \
-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD);      \
+                     ctzl(sizeof(ETYPE)), GETPC());                     \
 }
 
 GEN_VEXT_LD_STRIDE(vlse8_v,  int8_t,  lde_b)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                \
 {                                                                       \
     uint32_t vm = vext_vm(desc);                                        \
     vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN,     \
-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE);     \
+                     ctzl(sizeof(ETYPE)), GETPC());                     \
 }
 
 GEN_VEXT_ST_STRIDE(vsse8_v,  int8_t,  ste_b)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
 static void
 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
              vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
-             uintptr_t ra, MMUAccessType access_type)
+             uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base,         \
 {                                                                       \
     uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE));             \
     vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN,   \
-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD);      \
+                     ctzl(sizeof(ETYPE)), GETPC());                     \
 }                                                                       \
                                                                         \
 void HELPER(NAME)(void *vd, void *v0, target_ulong base,                \
                   CPURISCVState *env, uint32_t desc)                    \
 {                                                                       \
     vext_ldst_us(vd, base, env, desc, LOAD_FN,                          \
-                 ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \
+                 ctzl(sizeof(ETYPE)), env->vl, GETPC());                \
 }
 
 GEN_VEXT_LD_US(vle8_v,  int8_t,  lde_b)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base,          \
 {                                                                        \
     uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE));              \
     vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN,   \
-                     ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE);      \
+                     ctzl(sizeof(ETYPE)), GETPC());                      \
 }                                                                        \
                                                                          \
 void HELPER(NAME)(void *vd, void *v0, target_ulong base,                 \
                   CPURISCVState *env, uint32_t desc)                     \
 {                                                                        \
     vext_ldst_us(vd, base, env, desc, STORE_FN,                          \
-                 ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \
+                 ctzl(sizeof(ETYPE)), env->vl, GETPC());                 \
 }
 
 GEN_VEXT_ST_US(vse8_v,  int8_t,  ste_b)
@@ -XXX,XX +XXX,XX @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
     /* evl = ceil(vl/8) */
     uint8_t evl = (env->vl + 7) >> 3;
     vext_ldst_us(vd, base, env, desc, lde_b,
-                 0, evl, GETPC(), MMU_DATA_LOAD);
+                 0, evl, GETPC());
 }
 
 void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
@@ -XXX,XX +XXX,XX @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
     /* evl = ceil(vl/8) */
     uint8_t evl = (env->vl + 7) >> 3;
     vext_ldst_us(vd, base, env, desc, ste_b,
-                 0, evl, GETPC(), MMU_DATA_STORE);
+                 0, evl, GETPC());
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
                 void *vs2, CPURISCVState *env, uint32_t desc,
                 vext_get_index_addr get_index_addr,
                 vext_ldst_elem_fn *ldst_elem,
-                uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+                uint32_t esz, uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,                   \
                   void *vs2, CPURISCVState *env, uint32_t desc)            \
 {                                                                          \
     vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN,                \
-                    LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+                    LOAD_FN, ctzl(sizeof(ETYPE)), GETPC());                \
 }
 
 GEN_VEXT_LD_INDEX(vlxei8_8_v,   int8_t,  idx_b, lde_b)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,         \
 {                                                                \
     vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN,      \
                     STORE_FN, ctzl(sizeof(ETYPE)),               \
-                    GETPC(), MMU_DATA_STORE);                    \
+                    GETPC());                                    \
 }
 
 GEN_VEXT_ST_INDEX(vsxei8_8_v,   int8_t,  idx_b, ste_b)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
  */
 static void
 vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
-                MMUAccessType access_type)
+                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra)
 {
     uint32_t i, k, off, pos;
     uint32_t nf = vext_nf(desc);
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, target_ulong base,       \
                   CPURISCVState *env, uint32_t desc) \
 {                                                    \
     vext_ldst_whole(vd, base, env, desc, LOAD_FN,    \
-                    ctzl(sizeof(ETYPE)), GETPC(),    \
-                    MMU_DATA_LOAD);                  \
+                    ctzl(sizeof(ETYPE)), GETPC());   \
 }
 
 GEN_VEXT_LD_WHOLE(vl1re8_v,  int8_t,  lde_b)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, target_ulong base,       \
                   CPURISCVState *env, uint32_t desc) \
 {                                                    \
     vext_ldst_whole(vd, base, env, desc, STORE_FN,   \
-                    ctzl(sizeof(ETYPE)), GETPC(),    \
-                    MMU_DATA_STORE);                 \
+                    ctzl(sizeof(ETYPE)), GETPC());   \
 }
 
 GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

No functional change intended in this commit.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-3@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 76 ++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline int32_t vext_lmul(uint32_t desc)
 /*
  * Get the maximum number of elements can be operated.
  *
- * esz: log2 of element size in bytes.
+ * log2_esz: log2 of element size in bytes.
  */
-static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
+static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
 {
     /*
      * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
     uint32_t vlenb = simd_maxsz(desc);
 
     /* Return VLMAX */
-    int scale = vext_lmul(desc) - esz;
+    int scale = vext_lmul(desc) - log2_esz;
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
                  target_ulong stride, CPURISCVState *env,
                  uint32_t desc, uint32_t vm,
                  vext_ldst_elem_fn *ldst_elem,
-                 uint32_t esz, uintptr_t ra)
+                 uint32_t log2_esz, uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
-    uint32_t max_elems = vext_max_elems(desc, esz);
+    uint32_t max_elems = vext_max_elems(desc, log2_esz);
 
     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
         if (!vm && !vext_elem_mask(v0, i)) {
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
 
         k = 0;
         while (k < nf) {
-            target_ulong addr = base + stride * i + (k << esz);
+            target_ulong addr = base + stride * i + (k << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
 /* unmasked unit-stride load and store operation*/
 static void
 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-             vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
+             vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
              uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
-    uint32_t max_elems = vext_max_elems(desc, esz);
+    uint32_t max_elems = vext_max_elems(desc, log2_esz);
 
     /* load bytes from guest memory */
     for (i = env->vstart; i < evl; i++, env->vstart++) {
         k = 0;
         while (k < nf) {
-            target_ulong addr = base + ((i * nf + k) << esz);
+            target_ulong addr = base + ((i * nf + k) << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
                 void *vs2, CPURISCVState *env, uint32_t desc,
                 vext_get_index_addr get_index_addr,
                 vext_ldst_elem_fn *ldst_elem,
-                uint32_t esz, uintptr_t ra)
+                uint32_t log2_esz, uintptr_t ra)
 {
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
     uint32_t vm = vext_vm(desc);
-    uint32_t max_elems = vext_max_elems(desc, esz);
+    uint32_t max_elems = vext_max_elems(desc, log2_esz);
 
     /* load bytes from guest memory */
     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
 
         k = 0;
         while (k < nf) {
-            abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
+            abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
@@ -XXX,XX +XXX,XX @@ static inline void
 vext_ldff(void *vd, void *v0, target_ulong base,
           CPURISCVState *env, uint32_t desc,
           vext_ldst_elem_fn *ldst_elem,
-          uint32_t esz, uintptr_t ra)
+          uint32_t log2_esz, uintptr_t ra)
 {
     void *host;
     uint32_t i, k, vl = 0;
     uint32_t nf = vext_nf(desc);
     uint32_t vm = vext_vm(desc);
-    uint32_t max_elems = vext_max_elems(desc, esz);
+    uint32_t max_elems = vext_max_elems(desc, log2_esz);
     target_ulong addr, offset, remain;
 
     /* probe every access*/
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
         if (!vm && !vext_elem_mask(v0, i)) {
             continue;
         }
-        addr = adjust_addr(env, base + i * (nf << esz));
+        addr = adjust_addr(env, base + i * (nf << log2_esz));
         if (i == 0) {
-            probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+            probe_pages(env, addr, nf << log2_esz, ra, MMU_DATA_LOAD);
         } else {
             /* if it triggers an exception, no need to check watchpoint */
-            remain = nf << esz;
+            remain = nf << log2_esz;
             while (remain > 0) {
                 offset = -(addr | TARGET_PAGE_MASK);
                 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
             continue;
         }
         while (k < nf) {
-            target_ulong addr = base + ((i * nf + k) << esz);
+            target_ulong addr = base + ((i * nf + k) << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
  */
 static void
 vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-                vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra)
+                vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uintptr_t ra)
 {
     uint32_t i, k, off, pos;
     uint32_t nf = vext_nf(desc);
     uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
-    uint32_t max_elems = vlenb >> esz;
+    uint32_t max_elems = vlenb >> log2_esz;
 
     k = env->vstart / max_elems;
     off = env->vstart % max_elems;
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     if (off) {
         /* load/store rest of elements of current segment pointed by vstart */
         for (pos = off; pos < max_elems; pos++, env->vstart++) {
-            target_ulong addr = base + ((pos + k * max_elems) << esz);
+            target_ulong addr = base + ((pos + k * max_elems) << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
         }
         k++;
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     /* load/store elements for rest of segments */
     for (; k < nf; k++) {
         for (i = 0; i < max_elems; i++, env->vstart++) {
-            target_ulong addr = base + ((i + k * max_elems) << esz);
+            target_ulong addr = base + ((i + k * max_elems) << log2_esz);
             ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
         }
     }
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
 
-#define GEN_VEXT_VSLIE1UP(ESZ, H)                                           \
-static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
-                     CPURISCVState *env, uint32_t desc)                     \
+#define GEN_VEXT_VSLIE1UP(BITWIDTH, H)                                      \
+static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
+                     void *vs2, CPURISCVState *env, uint32_t desc)          \
 {                                                                           \
-    typedef uint##ESZ##_t ETYPE;                                            \
+    typedef uint##BITWIDTH##_t ETYPE;                                       \
     uint32_t vm = vext_vm(desc);                                            \
     uint32_t vl = env->vl;                                                  \
     uint32_t i;                                                             \
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIE1UP(16, H2)
 GEN_VEXT_VSLIE1UP(32, H4)
 GEN_VEXT_VSLIE1UP(64, H8)
 
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ)                          \
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, BITWIDTH)                     \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
                   CPURISCVState *env, uint32_t desc)              \
 {                                                                 \
-    vslide1up_##ESZ(vd, v0, s1, vs2, env, desc);                  \
+    vslide1up_##BITWIDTH(vd, v0, s1, vs2, env, desc);             \
 }
 
 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16)
 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
 
-#define GEN_VEXT_VSLIDE1DOWN(ESZ, H)                                          \
-static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
-                       CPURISCVState *env, uint32_t desc)                     \
+#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H)                                     \
+static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
+                       void *vs2, CPURISCVState *env, uint32_t desc)          \
 {                                                                             \
-    typedef uint##ESZ##_t ETYPE;                                              \
+    typedef uint##BITWIDTH##_t ETYPE;                                         \
     uint32_t vm = vext_vm(desc);                                              \
     uint32_t vl = env->vl;                                                    \
     uint32_t i;                                                               \
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1DOWN(16, H2)
 GEN_VEXT_VSLIDE1DOWN(32, H4)
 GEN_VEXT_VSLIDE1DOWN(64, H8)
 
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ)                        \
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, BITWIDTH)                   \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
                   CPURISCVState *env, uint32_t desc)              \
 {                                                                 \
-    vslide1down_##ESZ(vd, v0, s1, vs2, env, desc);                \
+    vslide1down_##BITWIDTH(vd, v0, s1, vs2, env, desc);           \
 }
 
 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32)
 GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64)
 
 /* Vector Floating-Point Slide Instructions */
-#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ)                     \
+#define GEN_VEXT_VFSLIDE1UP_VF(NAME, BITWIDTH)                \
 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
                   CPURISCVState *env, uint32_t desc)          \
 {                                                             \
-    vslide1up_##ESZ(vd, v0, s1, vs2, env, desc);              \
+    vslide1up_##BITWIDTH(vd, v0, s1, vs2, env, desc);         \
 }
 
 /* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16)
 GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32)
 GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64)
 
-#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ)                   \
+#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, BITWIDTH)              \
 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
                   CPURISCVState *env, uint32_t desc)          \
 {                                                             \
-    vslide1down_##ESZ(vd, v0, s1, vs2, env, desc);            \
+    vslide1down_##BITWIDTH(vd, v0, s1, vs2, env, desc);       \
 }
 
 /* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.

vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselves
require vstart to be zero. So they don't need the early exit.

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
     }
 
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     if (a->vm && s->vl_eq_vlmax) {
         gvec_fn(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
             };
             TCGLabel *over = gen_new_label();
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
                                cpu_env, s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
         TCGv s1;
         TCGLabel *over = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         s1 = get_gpr(s, a->rs1, EXT_SIGN);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
             };
             TCGLabel *over = gen_new_label();
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             s1 = tcg_constant_i64(simm);
             dest = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
 
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         TCGLabel *over = gen_new_label();                        \
         gen_set_rm(s, RISCV_FRM_DYN);                            \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
                                                                  \
         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
         TCGLabel *over = gen_new_label();
         gen_set_rm(s, rm);
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             };
             TCGLabel *over = gen_new_label();
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
             t1 = tcg_temp_new_i64();
             /* NaN-box f[rs1] */
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, FRM);                                        \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, RISCV_FRM_DYN);                              \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, FRM);                                        \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         TCGLabel *over = gen_new_label();                          \
         gen_set_rm(s, FRM);                                        \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
         gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
         TCGLabel *over = gen_new_label();                          \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
     gen_helper_gvec_3_ptr *fn;
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
     static gen_helper_gvec_3_ptr * const fns[6][4] = {
         {
-- 
2.36.1

From: eopXD <eop.chen@sifive.com>

According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".

There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.

This is the first commit regarding the optional tail agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                      |   2 +
 target/riscv/internals.h                |   5 +-
 target/riscv/cpu_helper.c               |   2 +
 target/riscv/translate.c                |   2 +
 target/riscv/vector_helper.c            | 296 +++++++++++++-----------
 target/riscv/insn_trans/trans_rvv.c.inc |   3 +-
 6 files changed, 178 insertions(+), 132 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
     bool ext_zmmul;
+    bool rvv_ta_all_1s;
 
     uint32_t mvendorid;
     uint64_t marchid;
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, XL, 20, 2)
 /* If PointerMasking should be applied */
 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
+FIELD(TB_FLAGS, VTA, 24, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -XXX,XX +XXX,XX @@
 /* share data between vector helpers and decode code */
 FIELD(VDATA, VM, 0, 1)
 FIELD(VDATA, LMUL, 1, 3)
-FIELD(VDATA, NF, 4, 4)
-FIELD(VDATA, WD, 4, 1)
+FIELD(VDATA, VTA, 4, 1)
+FIELD(VDATA, NF, 5, 4)
+FIELD(VDATA, WD, 5, 1)
 
 /* float point classify helpers */
 target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                     FIELD_EX64(env->vtype, VTYPE, VLMUL));
         flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
+                    FIELD_EX64(env->vtype, VTYPE, VTA));
     } else {
         flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
     }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      */
     int8_t lmul;
     uint8_t sew;
+    uint8_t vta;
     target_ulong vstart;
     bool vl_eq_vlmax;
     uint8_t ntemp;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
     ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
+    ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
     ctx->vstart = env->vstart;
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->misa_mxl_max = env->misa_mxl_max;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline int32_t vext_lmul(uint32_t desc)
     return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
 }
 
+static inline uint32_t vext_vta(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VTA);
+}
+
 /*
  * Get the maximum number of elements can be operated.
  *
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
+/*
+ * Get number of total elements, including prestart, body and tail elements.
+ * Note that when LMUL < 1, the tail includes the elements past VLMAX that
+ * are held in the same vector register.
+ */
+static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
+                                            uint32_t esz)
+{
+    uint32_t vlenb = simd_maxsz(desc);
+    uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
+    int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
+                  ctzl(esz) - ctzl(sew) + vext_lmul(desc);
+    return (vlenb << emul) / esz;
+}
+
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 {
     return (addr & env->cur_pmmask) | env->cur_pmbase;
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
     }
 }
 
+/* set agnostic elements to 1s */
+static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+                              uint32_t tot)
+{
+    if (is_agnostic == 0) {
+        /* policy undisturbed */
+        return;
+    }
+    if (tot - cnt == 0) {
+        return ;
+    }
+    memset(base + cnt, -1, tot - cnt);
+}
+
 static inline void vext_set_elem_mask(void *v0, int index,
                                       uint8_t value)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
 
 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
                        CPURISCVState *env, uint32_t desc,
-                       opivv2_fn *fn)
+                       opivv2_fn *fn, uint32_t esz)
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
     uint32_t i;
 
     for (i = env->vstart; i < vl; i++) {
@@ -XXX,XX +XXX,XX @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
         fn(vd, vs1, vs2, i);
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 }
 
 /* generate the helpers for OPIVV */
-#define GEN_VEXT_VV(NAME)                                 \
+#define GEN_VEXT_VV(NAME, ESZ)                            \
 void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
     do_vext_vv(vd, v0, vs1, vs2, env, desc,               \
-               do_##NAME);                                \
+               do_##NAME, ESZ);                           \
 }
 
-GEN_VEXT_VV(vadd_vv_b)
-GEN_VEXT_VV(vadd_vv_h)
-GEN_VEXT_VV(vadd_vv_w)
-GEN_VEXT_VV(vadd_vv_d)
-GEN_VEXT_VV(vsub_vv_b)
-GEN_VEXT_VV(vsub_vv_h)
-GEN_VEXT_VV(vsub_vv_w)
-GEN_VEXT_VV(vsub_vv_d)
+GEN_VEXT_VV(vadd_vv_b, 1)
+GEN_VEXT_VV(vadd_vv_h, 2)
+GEN_VEXT_VV(vadd_vv_w, 4)
+GEN_VEXT_VV(vadd_vv_d, 8)
+GEN_VEXT_VV(vsub_vv_b, 1)
+GEN_VEXT_VV(vsub_vv_h, 2)
+GEN_VEXT_VV(vsub_vv_w, 4)
+GEN_VEXT_VV(vsub_vv_d, 8)
 
 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
 
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
-GEN_VEXT_VV(vwaddu_vv_b)
-GEN_VEXT_VV(vwaddu_vv_h)
-GEN_VEXT_VV(vwaddu_vv_w)
-GEN_VEXT_VV(vwsubu_vv_b)
-GEN_VEXT_VV(vwsubu_vv_h)
-GEN_VEXT_VV(vwsubu_vv_w)
-GEN_VEXT_VV(vwadd_vv_b)
-GEN_VEXT_VV(vwadd_vv_h)
-GEN_VEXT_VV(vwadd_vv_w)
-GEN_VEXT_VV(vwsub_vv_b)
-GEN_VEXT_VV(vwsub_vv_h)
-GEN_VEXT_VV(vwsub_vv_w)
-GEN_VEXT_VV(vwaddu_wv_b)
-GEN_VEXT_VV(vwaddu_wv_h)
-GEN_VEXT_VV(vwaddu_wv_w)
-GEN_VEXT_VV(vwsubu_wv_b)
-GEN_VEXT_VV(vwsubu_wv_h)
-GEN_VEXT_VV(vwsubu_wv_w)
-GEN_VEXT_VV(vwadd_wv_b)
-GEN_VEXT_VV(vwadd_wv_h)
-GEN_VEXT_VV(vwadd_wv_w)
-GEN_VEXT_VV(vwsub_wv_b)
-GEN_VEXT_VV(vwsub_wv_h)
-GEN_VEXT_VV(vwsub_wv_w)
+GEN_VEXT_VV(vwaddu_vv_b, 2)
+GEN_VEXT_VV(vwaddu_vv_h, 4)
+GEN_VEXT_VV(vwaddu_vv_w, 8)
+GEN_VEXT_VV(vwsubu_vv_b, 2)
+GEN_VEXT_VV(vwsubu_vv_h, 4)
+GEN_VEXT_VV(vwsubu_vv_w, 8)
+GEN_VEXT_VV(vwadd_vv_b, 2)
+GEN_VEXT_VV(vwadd_vv_h, 4)
+GEN_VEXT_VV(vwadd_vv_w, 8)
+GEN_VEXT_VV(vwsub_vv_b, 2)
+GEN_VEXT_VV(vwsub_vv_h, 4)
+GEN_VEXT_VV(vwsub_vv_w, 8)
+GEN_VEXT_VV(vwaddu_wv_b, 2)
+GEN_VEXT_VV(vwaddu_wv_h, 4)
+GEN_VEXT_VV(vwaddu_wv_w, 8)
+GEN_VEXT_VV(vwsubu_wv_b, 2)
+GEN_VEXT_VV(vwsubu_wv_h, 4)
+GEN_VEXT_VV(vwsubu_wv_w, 8)
+GEN_VEXT_VV(vwadd_wv_b, 2)
+GEN_VEXT_VV(vwadd_wv_h, 4)
+GEN_VEXT_VV(vwadd_wv_w, 8)
+GEN_VEXT_VV(vwsub_wv_b, 2)
+GEN_VEXT_VV(vwsub_wv_h, 4)
+GEN_VEXT_VV(vwsub_wv_w, 8)
 
 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
-GEN_VEXT_VV(vand_vv_b)
-GEN_VEXT_VV(vand_vv_h)
-GEN_VEXT_VV(vand_vv_w)
-GEN_VEXT_VV(vand_vv_d)
-GEN_VEXT_VV(vor_vv_b)
-GEN_VEXT_VV(vor_vv_h)
-GEN_VEXT_VV(vor_vv_w)
-GEN_VEXT_VV(vor_vv_d)
-GEN_VEXT_VV(vxor_vv_b)
-GEN_VEXT_VV(vxor_vv_h)
-GEN_VEXT_VV(vxor_vv_w)
-GEN_VEXT_VV(vxor_vv_d)
+GEN_VEXT_VV(vand_vv_b, 1)
+GEN_VEXT_VV(vand_vv_h, 2)
+GEN_VEXT_VV(vand_vv_w, 4)
+GEN_VEXT_VV(vand_vv_d, 8)
+GEN_VEXT_VV(vor_vv_b, 1)
+GEN_VEXT_VV(vor_vv_h, 2)
+GEN_VEXT_VV(vor_vv_w, 4)
+GEN_VEXT_VV(vor_vv_d, 8)
+GEN_VEXT_VV(vxor_vv_b, 1)
+GEN_VEXT_VV(vxor_vv_h, 2)
+GEN_VEXT_VV(vxor_vv_w, 4)
+GEN_VEXT_VV(vxor_vv_d, 8)
 
 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
 RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
-GEN_VEXT_VV(vminu_vv_b)
-GEN_VEXT_VV(vminu_vv_h)
-GEN_VEXT_VV(vminu_vv_w)
-GEN_VEXT_VV(vminu_vv_d)
-GEN_VEXT_VV(vmin_vv_b)
-GEN_VEXT_VV(vmin_vv_h)
-GEN_VEXT_VV(vmin_vv_w)
-GEN_VEXT_VV(vmin_vv_d)
-GEN_VEXT_VV(vmaxu_vv_b)
-GEN_VEXT_VV(vmaxu_vv_h)
-GEN_VEXT_VV(vmaxu_vv_w)
-GEN_VEXT_VV(vmaxu_vv_d)
-GEN_VEXT_VV(vmax_vv_b)
-GEN_VEXT_VV(vmax_vv_h)
-GEN_VEXT_VV(vmax_vv_w)
-GEN_VEXT_VV(vmax_vv_d)
+GEN_VEXT_VV(vminu_vv_b, 1)
+GEN_VEXT_VV(vminu_vv_h, 2)
+GEN_VEXT_VV(vminu_vv_w, 4)
+GEN_VEXT_VV(vminu_vv_d, 8)
+GEN_VEXT_VV(vmin_vv_b, 1)
+GEN_VEXT_VV(vmin_vv_h, 2)
+GEN_VEXT_VV(vmin_vv_w, 4)
+GEN_VEXT_VV(vmin_vv_d, 8)
+GEN_VEXT_VV(vmaxu_vv_b, 1)
+GEN_VEXT_VV(vmaxu_vv_h, 2)
+GEN_VEXT_VV(vmaxu_vv_w, 4)
+GEN_VEXT_VV(vmaxu_vv_d, 8)
+GEN_VEXT_VV(vmax_vv_b, 1)
+GEN_VEXT_VV(vmax_vv_h, 2)
+GEN_VEXT_VV(vmax_vv_w, 4)
+GEN_VEXT_VV(vmax_vv_d, 8)
 
 RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
 RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
 RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
-GEN_VEXT_VV(vmul_vv_b)
-GEN_VEXT_VV(vmul_vv_h)
-GEN_VEXT_VV(vmul_vv_w)
-GEN_VEXT_VV(vmul_vv_d)
+GEN_VEXT_VV(vmul_vv_b, 1)
+GEN_VEXT_VV(vmul_vv_h, 2)
+GEN_VEXT_VV(vmul_vv_w, 4)
+GEN_VEXT_VV(vmul_vv_d, 8)
 
 static int8_t do_mulh_b(int8_t s2, int8_t s1)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
 RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
 RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
 RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
-GEN_VEXT_VV(vmulh_vv_b)
-GEN_VEXT_VV(vmulh_vv_h)
-GEN_VEXT_VV(vmulh_vv_w)
-GEN_VEXT_VV(vmulh_vv_d)
-GEN_VEXT_VV(vmulhu_vv_b)
-GEN_VEXT_VV(vmulhu_vv_h)
-GEN_VEXT_VV(vmulhu_vv_w)
-GEN_VEXT_VV(vmulhu_vv_d)
-GEN_VEXT_VV(vmulhsu_vv_b)
-GEN_VEXT_VV(vmulhsu_vv_h)
-GEN_VEXT_VV(vmulhsu_vv_w)
-GEN_VEXT_VV(vmulhsu_vv_d)
+GEN_VEXT_VV(vmulh_vv_b, 1)
+GEN_VEXT_VV(vmulh_vv_h, 2)
+GEN_VEXT_VV(vmulh_vv_w, 4)
+GEN_VEXT_VV(vmulh_vv_d, 8)
+GEN_VEXT_VV(vmulhu_vv_b, 1)
+GEN_VEXT_VV(vmulhu_vv_h, 2)
+GEN_VEXT_VV(vmulhu_vv_w, 4)
+GEN_VEXT_VV(vmulhu_vv_d, 8)
+GEN_VEXT_VV(vmulhsu_vv_b, 1)
+GEN_VEXT_VV(vmulhsu_vv_h, 2)
+GEN_VEXT_VV(vmulhsu_vv_w, 4)
+GEN_VEXT_VV(vmulhsu_vv_d, 8)
 
 RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
 RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
 RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
-GEN_VEXT_VV(vdivu_vv_b)
-GEN_VEXT_VV(vdivu_vv_h)
-GEN_VEXT_VV(vdivu_vv_w)
-GEN_VEXT_VV(vdivu_vv_d)
-GEN_VEXT_VV(vdiv_vv_b)
-GEN_VEXT_VV(vdiv_vv_h)
-GEN_VEXT_VV(vdiv_vv_w)
-GEN_VEXT_VV(vdiv_vv_d)
-GEN_VEXT_VV(vremu_vv_b)
-GEN_VEXT_VV(vremu_vv_h)
-GEN_VEXT_VV(vremu_vv_w)
-GEN_VEXT_VV(vremu_vv_d)
-GEN_VEXT_VV(vrem_vv_b)
-GEN_VEXT_VV(vrem_vv_h)
-GEN_VEXT_VV(vrem_vv_w)
-GEN_VEXT_VV(vrem_vv_d)
+GEN_VEXT_VV(vdivu_vv_b, 1)
+GEN_VEXT_VV(vdivu_vv_h, 2)
+GEN_VEXT_VV(vdivu_vv_w, 4)
+GEN_VEXT_VV(vdivu_vv_d, 8)
+GEN_VEXT_VV(vdiv_vv_b, 1)
+GEN_VEXT_VV(vdiv_vv_h, 2)
+GEN_VEXT_VV(vdiv_vv_w, 4)
+GEN_VEXT_VV(vdiv_vv_d, 8)
+GEN_VEXT_VV(vremu_vv_b, 1)
+GEN_VEXT_VV(vremu_vv_h, 2)
+GEN_VEXT_VV(vremu_vv_w, 4)
+GEN_VEXT_VV(vremu_vv_d, 8)
+GEN_VEXT_VV(vrem_vv_b, 1)
+GEN_VEXT_VV(vrem_vv_h, 2)
+GEN_VEXT_VV(vrem_vv_w, 4)
+GEN_VEXT_VV(vrem_vv_d, 8)
 
 RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
 RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
 RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
-GEN_VEXT_VV(vwmul_vv_b)
-GEN_VEXT_VV(vwmul_vv_h)
-GEN_VEXT_VV(vwmul_vv_w)
-GEN_VEXT_VV(vwmulu_vv_b)
-GEN_VEXT_VV(vwmulu_vv_h)
-GEN_VEXT_VV(vwmulu_vv_w)
-GEN_VEXT_VV(vwmulsu_vv_b)
-GEN_VEXT_VV(vwmulsu_vv_h)
-GEN_VEXT_VV(vwmulsu_vv_w)
+GEN_VEXT_VV(vwmul_vv_b, 2)
+GEN_VEXT_VV(vwmul_vv_h, 4)
+GEN_VEXT_VV(vwmul_vv_w, 8)
+GEN_VEXT_VV(vwmulu_vv_b, 2)
+GEN_VEXT_VV(vwmulu_vv_h, 4)
+GEN_VEXT_VV(vwmulu_vv_w, 8)
+GEN_VEXT_VV(vwmulsu_vv_b, 2)
+GEN_VEXT_VV(vwmulsu_vv_h, 4)
+GEN_VEXT_VV(vwmulsu_vv_w, 8)
 
 RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
 RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
 RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
-GEN_VEXT_VV(vmacc_vv_b)
-GEN_VEXT_VV(vmacc_vv_h)
-GEN_VEXT_VV(vmacc_vv_w)
-GEN_VEXT_VV(vmacc_vv_d)
-GEN_VEXT_VV(vnmsac_vv_b)
-GEN_VEXT_VV(vnmsac_vv_h)
-GEN_VEXT_VV(vnmsac_vv_w)
-GEN_VEXT_VV(vnmsac_vv_d)
-GEN_VEXT_VV(vmadd_vv_b)
-GEN_VEXT_VV(vmadd_vv_h)
-GEN_VEXT_VV(vmadd_vv_w)
-GEN_VEXT_VV(vmadd_vv_d)
-GEN_VEXT_VV(vnmsub_vv_b)
-GEN_VEXT_VV(vnmsub_vv_h)
-GEN_VEXT_VV(vnmsub_vv_w)
-GEN_VEXT_VV(vnmsub_vv_d)
+GEN_VEXT_VV(vmacc_vv_b, 1)
+GEN_VEXT_VV(vmacc_vv_h, 2)
+GEN_VEXT_VV(vmacc_vv_w, 4)
+GEN_VEXT_VV(vmacc_vv_d, 8)
+GEN_VEXT_VV(vnmsac_vv_b, 1)
+GEN_VEXT_VV(vnmsac_vv_h, 2)
+GEN_VEXT_VV(vnmsac_vv_w, 4)
+GEN_VEXT_VV(vnmsac_vv_d, 8)
+GEN_VEXT_VV(vmadd_vv_b, 1)
+GEN_VEXT_VV(vmadd_vv_h, 2)
+GEN_VEXT_VV(vmadd_vv_w, 4)
+GEN_VEXT_VV(vmadd_vv_d, 8)
+GEN_VEXT_VV(vnmsub_vv_b, 1)
+GEN_VEXT_VV(vnmsub_vv_h, 2)
+GEN_VEXT_VV(vnmsub_vv_w, 4)
+GEN_VEXT_VV(vnmsub_vv_d, 8)
 
 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \
 static void do_##NAME(void *vd, target_long s1, void *vs2, int i)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
 RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
-GEN_VEXT_VV(vwmaccu_vv_b)
-GEN_VEXT_VV(vwmaccu_vv_h)
-GEN_VEXT_VV(vwmaccu_vv_w)
-GEN_VEXT_VV(vwmacc_vv_b)
-GEN_VEXT_VV(vwmacc_vv_h)
-GEN_VEXT_VV(vwmacc_vv_w)
-GEN_VEXT_VV(vwmaccsu_vv_b)
-GEN_VEXT_VV(vwmaccsu_vv_h)
-GEN_VEXT_VV(vwmaccsu_vv_w)
+GEN_VEXT_VV(vwmaccu_vv_b, 2)
+GEN_VEXT_VV(vwmaccu_vv_h, 4)
+GEN_VEXT_VV(vwmaccu_vv_w, 8)
+GEN_VEXT_VV(vwmacc_vv_b, 2)
+GEN_VEXT_VV(vwmacc_vv_h, 4)
+GEN_VEXT_VV(vwmacc_vv_w, 8)
+GEN_VEXT_VV(vwmaccsu_vv_b, 2)
+GEN_VEXT_VV(vwmaccsu_vv_h, 4)
+GEN_VEXT_VV(vwmaccsu_vv_w, 8)
 
 RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
 RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
     tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         gvec_fn(s->sew, vreg_ofs(s, a->rd),
                 vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
                 MAXSZ(s), MAXSZ(s));
@@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
                            cpu_env, s->cfg_ptr->vlen / 8,
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.

A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail elements.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                |  2 +
 target/riscv/vector_helper.c            | 60 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc |  6 +++
 3 files changed, 68 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t lmul;
     uint8_t sew;
     uint8_t vta;
+    bool cfg_vta_all_1s;
     target_ulong vstart;
     bool vl_eq_vlmax;
     uint8_t ntemp;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
     ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
     ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
+    ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
     ctx->vstart = env->vstart;
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->misa_mxl_max = env->misa_mxl_max;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
     uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
 
     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
         if (!vm && !vext_elem_mask(v0, i)) {
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
         }
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
+                          (k * max_elems + max_elems) * esz);
+    }
+    if (nf * max_elems % total_elems != 0) {
+        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+        uint32_t registers_used =
+            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+                          registers_used * vlenb);
+    }
 }
 
 #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)                        \
@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     uint32_t i, k;
     uint32_t nf = vext_nf(desc);
     uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
 
     /* load bytes from guest memory */
     for (i = env->vstart; i < evl; i++, env->vstart++) {
@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         }
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz,
+                          (k * max_elems + max_elems) * esz);
+    }
+    if (nf * max_elems % total_elems != 0) {
+        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+        uint32_t registers_used =
+            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+                          registers_used * vlenb);
+    }
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
     uint32_t nf = vext_nf(desc);
     uint32_t vm = vext_vm(desc);
     uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
 
     /* load bytes from guest memory */
     for (i = env->vstart; i < env->vl; i++, env->vstart++) {
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
         }
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
+                          (k * max_elems + max_elems) * esz);
+    }
+    if (nf * max_elems % total_elems != 0) {
+        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+        uint32_t registers_used =
+            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+                          registers_used * vlenb);
+    }
 }
 
 #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN)                  \
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
     uint32_t nf = vext_nf(desc);
     uint32_t vm = vext_vm(desc);
     uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
     target_ulong addr, offset, remain;
 
     /* probe every access*/
@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
         }
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
+                          (k * max_elems + max_elems) * esz);
+    }
+    if (nf * max_elems % total_elems != 0) {
+        uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+        uint32_t registers_used =
+            ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+        vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+                          registers_used * vlenb);
+    }
 }
 
 #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN)               \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
     data = FIELD_DP32(data, VDATA, VM, a->vm);
     data = FIELD_DP32(data, VDATA, LMUL, emul);
     data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
     return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
     /* EMUL = 1, NFIELDS = 1 */
     data = FIELD_DP32(data, VDATA, LMUL, 0);
     data = FIELD_DP32(data, VDATA, NF, 1);
+    /* Mask destination register are always tail-agnostic */
+    data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
     return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
     data = FIELD_DP32(data, VDATA, VM, a->vm);
     data = FIELD_DP32(data, VDATA, LMUL, emul);
     data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
     return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
     data = FIELD_DP32(data, VDATA, VM, a->vm);
     data = FIELD_DP32(data, VDATA, LMUL, emul);
     data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
     return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
     data = FIELD_DP32(data, VDATA, VM, a->vm);
     data = FIELD_DP32(data, VDATA, LMUL, emul);
     data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
     return ldff_trans(a->rd, a->rs1, data, fn, s);
 }
 
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/internals.h                |   5 +-
 target/riscv/vector_helper.c            | 314 +++++++++++++-----------
 target/riscv/insn_trans/trans_rvv.c.inc |  13 +-
 3 files changed, 190 insertions(+), 142 deletions(-)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -XXX,XX +XXX,XX @@
 FIELD(VDATA, VM, 0, 1)
 FIELD(VDATA, LMUL, 1, 3)
 FIELD(VDATA, VTA, 4, 1)
-FIELD(VDATA, NF, 5, 4)
-FIELD(VDATA, WD, 5, 1)
+FIELD(VDATA, VTA_ALL_1S, 5, 1)
+FIELD(VDATA, NF, 6, 4)
+FIELD(VDATA, WD, 6, 1)
 
 /* float point classify helpers */
 target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_vta(uint32_t desc)
     return FIELD_EX32(simd_data(desc), VDATA, VTA);
 }
 
+static inline uint32_t vext_vta_all_1s(uint32_t desc)
+{
+    return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
+}
+
 /*
  * Get the maximum number of elements can be operated.
  *
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
 
 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
                        CPURISCVState *env, uint32_t desc,
-                       opivx2_fn fn)
+                       opivx2_fn fn, uint32_t esz)
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
     uint32_t i;
 
     for (i = env->vstart; i < vl; i++) {
@@ -XXX,XX +XXX,XX @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
         fn(vd, s1, vs2, i);
     }
     env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 }
 
 /* generate the helpers for OPIVX */
-#define GEN_VEXT_VX(NAME)                                 \
+#define GEN_VEXT_VX(NAME, ESZ)                            \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
     do_vext_vx(vd, v0, s1, vs2, env, desc,                \
-               do_##NAME);                                \
-}
-
-GEN_VEXT_VX(vadd_vx_b)
-GEN_VEXT_VX(vadd_vx_h)
-GEN_VEXT_VX(vadd_vx_w)
-GEN_VEXT_VX(vadd_vx_d)
-GEN_VEXT_VX(vsub_vx_b)
-GEN_VEXT_VX(vsub_vx_h)
-GEN_VEXT_VX(vsub_vx_w)
-GEN_VEXT_VX(vsub_vx_d)
-GEN_VEXT_VX(vrsub_vx_b)
-GEN_VEXT_VX(vrsub_vx_h)
-GEN_VEXT_VX(vrsub_vx_w)
-GEN_VEXT_VX(vrsub_vx_d)
+               do_##NAME, ESZ);                           \
+}
+
+GEN_VEXT_VX(vadd_vx_b, 1)
+GEN_VEXT_VX(vadd_vx_h, 2)
+GEN_VEXT_VX(vadd_vx_w, 4)
+GEN_VEXT_VX(vadd_vx_d, 8)
+GEN_VEXT_VX(vsub_vx_b, 1)
+GEN_VEXT_VX(vsub_vx_h, 2)
+GEN_VEXT_VX(vsub_vx_w, 4)
+GEN_VEXT_VX(vsub_vx_d, 8)
+GEN_VEXT_VX(vrsub_vx_b, 1)
+GEN_VEXT_VX(vrsub_vx_h, 2)
+GEN_VEXT_VX(vrsub_vx_w, 4)
+GEN_VEXT_VX(vrsub_vx_d, 8)
 
 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
-GEN_VEXT_VX(vwaddu_vx_b)
-GEN_VEXT_VX(vwaddu_vx_h)
-GEN_VEXT_VX(vwaddu_vx_w)
-GEN_VEXT_VX(vwsubu_vx_b)
-GEN_VEXT_VX(vwsubu_vx_h)
-GEN_VEXT_VX(vwsubu_vx_w)
-GEN_VEXT_VX(vwadd_vx_b)
-GEN_VEXT_VX(vwadd_vx_h)
-GEN_VEXT_VX(vwadd_vx_w)
-GEN_VEXT_VX(vwsub_vx_b)
-GEN_VEXT_VX(vwsub_vx_h)
-GEN_VEXT_VX(vwsub_vx_w)
-GEN_VEXT_VX(vwaddu_wx_b)
-GEN_VEXT_VX(vwaddu_wx_h)
-GEN_VEXT_VX(vwaddu_wx_w)
-GEN_VEXT_VX(vwsubu_wx_b)
-GEN_VEXT_VX(vwsubu_wx_h)
-GEN_VEXT_VX(vwsubu_wx_w)
-GEN_VEXT_VX(vwadd_wx_b)
-GEN_VEXT_VX(vwadd_wx_h)
-GEN_VEXT_VX(vwadd_wx_w)
-GEN_VEXT_VX(vwsub_wx_b)
-GEN_VEXT_VX(vwsub_wx_h)
-GEN_VEXT_VX(vwsub_wx_w)
+GEN_VEXT_VX(vwaddu_vx_b, 2)
+GEN_VEXT_VX(vwaddu_vx_h, 4)
+GEN_VEXT_VX(vwaddu_vx_w, 8)
+GEN_VEXT_VX(vwsubu_vx_b, 2)
+GEN_VEXT_VX(vwsubu_vx_h, 4)
+GEN_VEXT_VX(vwsubu_vx_w, 8)
+GEN_VEXT_VX(vwadd_vx_b, 2)
+GEN_VEXT_VX(vwadd_vx_h, 4)
+GEN_VEXT_VX(vwadd_vx_w, 8)
+GEN_VEXT_VX(vwsub_vx_b, 2)
+GEN_VEXT_VX(vwsub_vx_h, 4)
+GEN_VEXT_VX(vwsub_vx_w, 8)
+GEN_VEXT_VX(vwaddu_wx_b, 2)
+GEN_VEXT_VX(vwaddu_wx_h, 4)
+GEN_VEXT_VX(vwaddu_wx_w, 8)
+GEN_VEXT_VX(vwsubu_wx_b, 2)
+GEN_VEXT_VX(vwsubu_wx_h, 4)
+GEN_VEXT_VX(vwsubu_wx_w, 8)
+GEN_VEXT_VX(vwadd_wx_b, 2)
+GEN_VEXT_VX(vwadd_wx_h, 4)
+GEN_VEXT_VX(vwadd_wx_w, 8)
+GEN_VEXT_VX(vwsub_wx_b, 2)
+GEN_VEXT_VX(vwsub_wx_h, 4)
+GEN_VEXT_VX(vwsub_wx_w, 8)
 
 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
 #define DO_VADC(N, M, C) (N + M + C)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
                   CPURISCVState *env, uint32_t desc)          \
 {                                                             \
     uint32_t vl = env->vl;                                    \
+    uint32_t esz = sizeof(ETYPE);                             \
+    uint32_t total_elems =                                    \
+        vext_get_total_elems(env, desc, esz);                 \
+    uint32_t vta = vext_vta(desc);                            \
     uint32_t i;                                               \
                                                               \
     for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
         *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry);         \
     }                                                         \
     env->vstart = 0;                                          \
+    /* set tail elements to 1s */                             \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);  \
 }
 
 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t,  H1, DO_VADC)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,        \
                   CPURISCVState *env, uint32_t desc)                     \
 {                                                                        \
     uint32_t vl = env->vl;                                               \
+    uint32_t esz = sizeof(ETYPE);                                        \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);         \
+    uint32_t vta = vext_vta(desc);                                       \
     uint32_t i;                                                          \
                                                                          \
     for (i = env->vstart; i < vl; i++) {                                 \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,        \
         *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
     }                                                                    \
     env->vstart = 0;                                          \
+    /* set tail elements to 1s */                                        \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);             \
 }
 
 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t,  H1, DO_VADC)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
 {                                                             \
     uint32_t vl = env->vl;                                    \
     uint32_t vm = vext_vm(desc);                              \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
     uint32_t i;                                               \
                                                               \
     for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
         vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry));      \
     }                                                         \
     env->vstart = 0;                                          \
+    /* mask destination register are always tail-agnostic */  \
+    /* set tail elements to 1s */                             \
+    if (vta_all_1s) {                                         \
+        for (; i < total_elems; i++) {                        \
+            vext_set_elem_mask(vd, i, 1);                     \
+        }                                                     \
+    }                                                         \
 }
 
 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t,  H1, DO_MADC)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,          \
 {                                                               \
     uint32_t vl = env->vl;                                      \
     uint32_t vm = vext_vm(desc);                                \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;          \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                \
     uint32_t i;                                                 \
                                                                 \
     for (i = env->vstart; i < vl; i++) {                        \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,          \
                 DO_OP(s2, (ETYPE)(target_long)s1, carry));      \
     }                                                           \
     env->vstart = 0;                                            \
+    /* mask destination register are always tail-agnostic */    \
+    /* set tail elements to 1s */                               \
+    if (vta_all_1s) {                                           \
+        for (; i < total_elems; i++) {                          \
+            vext_set_elem_mask(vd, i, 1);                       \
+        }                                                       \
+    }                                                           \
 }
 
 GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t,  H1, DO_MADC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
-GEN_VEXT_VX(vand_vx_b)
-GEN_VEXT_VX(vand_vx_h)
-GEN_VEXT_VX(vand_vx_w)
-GEN_VEXT_VX(vand_vx_d)
-GEN_VEXT_VX(vor_vx_b)
-GEN_VEXT_VX(vor_vx_h)
-GEN_VEXT_VX(vor_vx_w)
-GEN_VEXT_VX(vor_vx_d)
-GEN_VEXT_VX(vxor_vx_b)
-GEN_VEXT_VX(vxor_vx_h)
-GEN_VEXT_VX(vxor_vx_w)
-GEN_VEXT_VX(vxor_vx_d)
+GEN_VEXT_VX(vand_vx_b, 1)
+GEN_VEXT_VX(vand_vx_h, 2)
+GEN_VEXT_VX(vand_vx_w, 4)
+GEN_VEXT_VX(vand_vx_d, 8)
+GEN_VEXT_VX(vor_vx_b, 1)
+GEN_VEXT_VX(vor_vx_h, 2)
+GEN_VEXT_VX(vor_vx_w, 4)
+GEN_VEXT_VX(vor_vx_d, 8)
+GEN_VEXT_VX(vxor_vx_b, 1)
+GEN_VEXT_VX(vxor_vx_h, 2)
+GEN_VEXT_VX(vxor_vx_w, 4)
+GEN_VEXT_VX(vxor_vx_d, 8)
 
 /* Vector Single-Width Bit Shift Instructions */
 #define DO_SLL(N, M)  (N << (M))
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
 RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
-GEN_VEXT_VX(vminu_vx_b)
-GEN_VEXT_VX(vminu_vx_h)
-GEN_VEXT_VX(vminu_vx_w)
-GEN_VEXT_VX(vminu_vx_d)
-GEN_VEXT_VX(vmin_vx_b)
-GEN_VEXT_VX(vmin_vx_h)
-GEN_VEXT_VX(vmin_vx_w)
-GEN_VEXT_VX(vmin_vx_d)
-GEN_VEXT_VX(vmaxu_vx_b)
-GEN_VEXT_VX(vmaxu_vx_h)
-GEN_VEXT_VX(vmaxu_vx_w)
-GEN_VEXT_VX(vmaxu_vx_d)
-GEN_VEXT_VX(vmax_vx_b)
-GEN_VEXT_VX(vmax_vx_h)
-GEN_VEXT_VX(vmax_vx_w)
-GEN_VEXT_VX(vmax_vx_d)
+GEN_VEXT_VX(vminu_vx_b, 1)
+GEN_VEXT_VX(vminu_vx_h, 2)
+GEN_VEXT_VX(vminu_vx_w, 4)
+GEN_VEXT_VX(vminu_vx_d, 8)
+GEN_VEXT_VX(vmin_vx_b, 1)
+GEN_VEXT_VX(vmin_vx_h, 2)
+GEN_VEXT_VX(vmin_vx_w, 4)
+GEN_VEXT_VX(vmin_vx_d, 8)
+GEN_VEXT_VX(vmaxu_vx_b, 1)
+GEN_VEXT_VX(vmaxu_vx_h, 2)
+GEN_VEXT_VX(vmaxu_vx_w, 4)
+GEN_VEXT_VX(vmaxu_vx_d, 8)
+GEN_VEXT_VX(vmax_vx_b, 1)
+GEN_VEXT_VX(vmax_vx_h, 2)
+GEN_VEXT_VX(vmax_vx_w, 4)
+GEN_VEXT_VX(vmax_vx_d, 8)
 
 /* Vector Single-Width Integer Multiply Instructions */
 #define DO_MUL(N, M) (N * M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
 RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
 RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
 RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
-GEN_VEXT_VX(vmul_vx_b)
-GEN_VEXT_VX(vmul_vx_h)
-GEN_VEXT_VX(vmul_vx_w)
-GEN_VEXT_VX(vmul_vx_d)
-GEN_VEXT_VX(vmulh_vx_b)
-GEN_VEXT_VX(vmulh_vx_h)
-GEN_VEXT_VX(vmulh_vx_w)
-GEN_VEXT_VX(vmulh_vx_d)
-GEN_VEXT_VX(vmulhu_vx_b)
-GEN_VEXT_VX(vmulhu_vx_h)
-GEN_VEXT_VX(vmulhu_vx_w)
-GEN_VEXT_VX(vmulhu_vx_d)
-GEN_VEXT_VX(vmulhsu_vx_b)
-GEN_VEXT_VX(vmulhsu_vx_h)
-GEN_VEXT_VX(vmulhsu_vx_w)
-GEN_VEXT_VX(vmulhsu_vx_d)
+GEN_VEXT_VX(vmul_vx_b, 1)
+GEN_VEXT_VX(vmul_vx_h, 2)
+GEN_VEXT_VX(vmul_vx_w, 4)
+GEN_VEXT_VX(vmul_vx_d, 8)
+GEN_VEXT_VX(vmulh_vx_b, 1)
+GEN_VEXT_VX(vmulh_vx_h, 2)
+GEN_VEXT_VX(vmulh_vx_w, 4)
+GEN_VEXT_VX(vmulh_vx_d, 8)
+GEN_VEXT_VX(vmulhu_vx_b, 1)
+GEN_VEXT_VX(vmulhu_vx_h, 2)
+GEN_VEXT_VX(vmulhu_vx_w, 4)
+GEN_VEXT_VX(vmulhu_vx_d, 8)
+GEN_VEXT_VX(vmulhsu_vx_b, 1)
+GEN_VEXT_VX(vmulhsu_vx_h, 2)
+GEN_VEXT_VX(vmulhsu_vx_w, 4)
+GEN_VEXT_VX(vmulhsu_vx_d, 8)
 
 /* Vector Integer Divide Instructions */
 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
 RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
-GEN_VEXT_VX(vdivu_vx_b)
-GEN_VEXT_VX(vdivu_vx_h)
-GEN_VEXT_VX(vdivu_vx_w)
-GEN_VEXT_VX(vdivu_vx_d)
-GEN_VEXT_VX(vdiv_vx_b)
-GEN_VEXT_VX(vdiv_vx_h)
-GEN_VEXT_VX(vdiv_vx_w)
-GEN_VEXT_VX(vdiv_vx_d)
-GEN_VEXT_VX(vremu_vx_b)
-GEN_VEXT_VX(vremu_vx_h)
-GEN_VEXT_VX(vremu_vx_w)
-GEN_VEXT_VX(vremu_vx_d)
-GEN_VEXT_VX(vrem_vx_b)
-GEN_VEXT_VX(vrem_vx_h)
-GEN_VEXT_VX(vrem_vx_w)
-GEN_VEXT_VX(vrem_vx_d)
+GEN_VEXT_VX(vdivu_vx_b, 1)
+GEN_VEXT_VX(vdivu_vx_h, 2)
+GEN_VEXT_VX(vdivu_vx_w, 4)
+GEN_VEXT_VX(vdivu_vx_d, 8)
+GEN_VEXT_VX(vdiv_vx_b, 1)
+GEN_VEXT_VX(vdiv_vx_h, 2)
+GEN_VEXT_VX(vdiv_vx_w, 4)
+GEN_VEXT_VX(vdiv_vx_d, 8)
+GEN_VEXT_VX(vremu_vx_b, 1)
+GEN_VEXT_VX(vremu_vx_h, 2)
+GEN_VEXT_VX(vremu_vx_w, 4)
+GEN_VEXT_VX(vremu_vx_d, 8)
+GEN_VEXT_VX(vrem_vx_b, 1)
+GEN_VEXT_VX(vrem_vx_h, 2)
+GEN_VEXT_VX(vrem_vx_w, 4)
+GEN_VEXT_VX(vrem_vx_d, 8)
 
 /* Vector Widening Integer Multiply Instructions */
 RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
 RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
-GEN_VEXT_VX(vwmul_vx_b)
-GEN_VEXT_VX(vwmul_vx_h)
-GEN_VEXT_VX(vwmul_vx_w)
-GEN_VEXT_VX(vwmulu_vx_b)
-GEN_VEXT_VX(vwmulu_vx_h)
-GEN_VEXT_VX(vwmulu_vx_w)
-GEN_VEXT_VX(vwmulsu_vx_b)
-GEN_VEXT_VX(vwmulsu_vx_h)
-GEN_VEXT_VX(vwmulsu_vx_w)
+GEN_VEXT_VX(vwmul_vx_b, 2)
+GEN_VEXT_VX(vwmul_vx_h, 4)
+GEN_VEXT_VX(vwmul_vx_w, 8)
+GEN_VEXT_VX(vwmulu_vx_b, 2)
+GEN_VEXT_VX(vwmulu_vx_h, 4)
+GEN_VEXT_VX(vwmulu_vx_w, 8)
+GEN_VEXT_VX(vwmulsu_vx_b, 2)
+GEN_VEXT_VX(vwmulsu_vx_h, 4)
+GEN_VEXT_VX(vwmulsu_vx_w, 8)
 
 /* Vector Single-Width Integer Multiply-Add Instructions */
 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
 RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
-GEN_VEXT_VX(vmacc_vx_b)
-GEN_VEXT_VX(vmacc_vx_h)
-GEN_VEXT_VX(vmacc_vx_w)
-GEN_VEXT_VX(vmacc_vx_d)
-GEN_VEXT_VX(vnmsac_vx_b)
-GEN_VEXT_VX(vnmsac_vx_h)
-GEN_VEXT_VX(vnmsac_vx_w)
-GEN_VEXT_VX(vnmsac_vx_d)
-GEN_VEXT_VX(vmadd_vx_b)
-GEN_VEXT_VX(vmadd_vx_h)
-GEN_VEXT_VX(vmadd_vx_w)
-GEN_VEXT_VX(vmadd_vx_d)
-GEN_VEXT_VX(vnmsub_vx_b)
-GEN_VEXT_VX(vnmsub_vx_h)
-GEN_VEXT_VX(vnmsub_vx_w)
-GEN_VEXT_VX(vnmsub_vx_d)
+GEN_VEXT_VX(vmacc_vx_b, 1)
+GEN_VEXT_VX(vmacc_vx_h, 2)
+GEN_VEXT_VX(vmacc_vx_w, 4)
+GEN_VEXT_VX(vmacc_vx_d, 8)
+GEN_VEXT_VX(vnmsac_vx_b, 1)
+GEN_VEXT_VX(vnmsac_vx_h, 2)
+GEN_VEXT_VX(vnmsac_vx_w, 4)
+GEN_VEXT_VX(vnmsac_vx_d, 8)
+GEN_VEXT_VX(vmadd_vx_b, 1)
+GEN_VEXT_VX(vmadd_vx_h, 2)
+GEN_VEXT_VX(vmadd_vx_w, 4)
+GEN_VEXT_VX(vmadd_vx_d, 8)
+GEN_VEXT_VX(vnmsub_vx_b, 1)
+GEN_VEXT_VX(vnmsub_vx_h, 2)
+GEN_VEXT_VX(vnmsub_vx_w, 4)
+GEN_VEXT_VX(vnmsub_vx_d, 8)
 
 /* Vector Widening Integer Multiply-Add Instructions */
 RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
 RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
-GEN_VEXT_VX(vwmaccu_vx_b)
-GEN_VEXT_VX(vwmaccu_vx_h)
-GEN_VEXT_VX(vwmaccu_vx_w)
-GEN_VEXT_VX(vwmacc_vx_b)
-GEN_VEXT_VX(vwmacc_vx_h)
-GEN_VEXT_VX(vwmacc_vx_w)
-GEN_VEXT_VX(vwmaccsu_vx_b)
-GEN_VEXT_VX(vwmaccsu_vx_h)
-GEN_VEXT_VX(vwmaccsu_vx_w)
-GEN_VEXT_VX(vwmaccus_vx_b)
-GEN_VEXT_VX(vwmaccus_vx_h)
-GEN_VEXT_VX(vwmaccus_vx_w)
+GEN_VEXT_VX(vwmaccu_vx_b, 2)
+GEN_VEXT_VX(vwmaccu_vx_h, 4)
+GEN_VEXT_VX(vwmaccu_vx_w, 8)
+GEN_VEXT_VX(vwmacc_vx_b, 2)
+GEN_VEXT_VX(vwmacc_vx_h, 4)
+GEN_VEXT_VX(vwmacc_vx_w, 8)
+GEN_VEXT_VX(vwmaccsu_vx_b, 2)
+GEN_VEXT_VX(vwmaccsu_vx_h, 4)
+GEN_VEXT_VX(vwmaccsu_vx_w, 8)
+GEN_VEXT_VX(vwmaccus_vx_b, 2)
+GEN_VEXT_VX(vwmaccus_vx_h, 4)
+GEN_VEXT_VX(vwmaccus_vx_w, 8)
 
 /* Vector Integer Merge and Move Instructions */
 #define GEN_VEXT_VMV_VV(NAME, ETYPE, H)                              \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
 
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
     desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
                                       s->cfg_ptr->vlen / 8, data));
 
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
         return false;
     }
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         TCGv_i64 src1 = tcg_temp_new_i64();
 
         tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN));
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
 
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
     desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
                                       s->cfg_ptr->vlen / 8, data));
 
@@ -XXX,XX +XXX,XX @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
         return false;
     }
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                 extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
         mark_vs_dirty(s);
@@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1),
                            vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data =                                                     \
+            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,                          \
 {                                                                         \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(TS1);                                           \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     uint32_t i;                                                           \
                                                                           \
     for (i = env->vstart; i < vl; i++) {                                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,                          \
         *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK);                        \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t,  uint8_t, H1, H1, DO_SLL, 0x7)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,      \
 {                                                           \
     uint32_t vm = vext_vm(desc);                            \
     uint32_t vl = env->vl;                                  \
+    uint32_t esz = sizeof(TD);                              \
+    uint32_t total_elems =                                  \
+        vext_get_total_elems(env, desc, esz);               \
+    uint32_t vta = vext_vta(desc);                          \
     uint32_t i;                                             \
                                                             \
     for (i = env->vstart; i < vl; i++) {                    \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,      \
         *((TD *)vd + HD(i)) = OP(s2, s1 & MASK);            \
     }                                                       \
     env->vstart = 0;                                        \
+    /* set tail elements to 1s */                           \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);\
 }
 
 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
         return false;
     }
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         TCGv_i32 src1 = tcg_temp_new_i32();
 
         tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

Compares write mask registers, and so always operate under a tail-
agnostic policy.

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
 {                                                             \
     uint32_t vm = vext_vm(desc);                              \
     uint32_t vl = env->vl;                                    \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
     uint32_t i;                                               \
                                                               \
     for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
         vext_set_elem_mask(vd, i, DO_OP(s2, s1));             \
     }                                                         \
     env->vstart = 0;                                          \
+    /* mask destination register are always tail-agnostic */  \
+    /* set tail elements to 1s */                             \
+    if (vta_all_1s) {                                         \
+        for (; i < total_elems; i++) {                        \
+            vext_set_elem_mask(vd, i, 1);                     \
+        }                                                     \
+    }                                                         \
 }
 
 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t,  H1, DO_MSEQ)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,   \
 {                                                                   \
     uint32_t vm = vext_vm(desc);                                    \
     uint32_t vl = env->vl;                                          \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;              \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                    \
     uint32_t i;                                                     \
                                                                     \
     for (i = env->vstart; i < vl; i++) {                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,   \
                 DO_OP(s2, (ETYPE)(target_long)s1));                 \
     }                                                               \
     env->vstart = 0;                                                \
+    /* mask destination register are always tail-agnostic */        \
+    /* set tail elements to 1s */                                   \
+    if (vta_all_1s) {                                               \
+        for (; i < total_elems; i++) {                              \
+            vext_set_elem_mask(vd, i, 1);                           \
+        }                                                           \
+    }                                                               \
 }
 
 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t,  H1, DO_MSEQ)
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c            | 20 ++++++++++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++----
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env,           \
                   uint32_t desc)                                     \
 {                                                                    \
     uint32_t vl = env->vl;                                           \
+    uint32_t esz = sizeof(ETYPE);                                    \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
+    uint32_t vta = vext_vta(desc);                                   \
     uint32_t i;                                                      \
                                                                      \
     for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env,           \
         *((ETYPE *)vd + H(i)) = s1;                                  \
     }                                                                \
     env->vstart = 0;                                                 \
+    /* set tail elements to 1s */                                    \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
 }
 
 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env,         \
                   uint32_t desc)                                     \
 {                                                                    \
     uint32_t vl = env->vl;                                           \
+    uint32_t esz = sizeof(ETYPE);                                    \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
+    uint32_t vta = vext_vta(desc);                                   \
     uint32_t i;                                                      \
                                                                      \
     for (i = env->vstart; i < vl; i++) {                             \
         *((ETYPE *)vd + H(i)) = (ETYPE)s1;                           \
     }                                                                \
     env->vstart = 0;                                                 \
+    /* set tail elements to 1s */                                    \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
 }
 
 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,          \
                   CPURISCVState *env, uint32_t desc)                 \
 {                                                                    \
     uint32_t vl = env->vl;                                           \
+    uint32_t esz = sizeof(ETYPE);                                    \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
+    uint32_t vta = vext_vta(desc);                                   \
     uint32_t i;                                                      \
                                                                      \
     for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,          \
         *((ETYPE *)vd + H(i)) = *(vt + H(i));                        \
     }                                                                \
     env->vstart = 0;                                                 \
+    /* set tail elements to 1s */                                    \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
 }
 
 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,               \
                   void *vs2, CPURISCVState *env, uint32_t desc)      \
 {                                                                    \
     uint32_t vl = env->vl;                                           \
+    uint32_t esz = sizeof(ETYPE);                                    \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);     \
+    uint32_t vta = vext_vta(desc);                                   \
     uint32_t i;                                                      \
                                                                      \
     for (i = env->vstart; i < vl; i++) {                             \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,               \
         *((ETYPE *)vd + H(i)) = d;                                   \
     }                                                                \
     env->vstart = 0;                                                 \
+    /* set tail elements to 1s */                                    \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);         \
 }
 
 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t,  H1)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
         vext_check_isa_ill(s) &&
         /* vmv.v.v has rs2 = 0 and vm = 1 */
         vext_check_sss(s, a->rd, a->rs1, 0, 1)) {
-        if (s->vl_eq_vlmax) {
+        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
             tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
                              vreg_ofs(s, a->rs1),
                              MAXSZ(s), MAXSZ(s));
         } else {
             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);
             static gen_helper_gvec_2_ptr * const fns[4] = {
                 gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
                 gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
 
         s1 = get_gpr(s, a->rs1, EXT_SIGN);
 
-        if (s->vl_eq_vlmax) {
+        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
             tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
                                 MAXSZ(s), MAXSZ(s), s1);
         } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             TCGv_i64 s1_i64 = tcg_temp_new_i64();
             TCGv_ptr dest = tcg_temp_new_ptr();
             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);
             static gen_helper_vmv_vx * const fns[4] = {
                 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
                 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
         /* vmv.v.i has rs2 = 0 and vm = 1 */
         vext_check_ss(s, a->rd, 0, 1)) {
         int64_t simm = sextract64(a->rs1, 0, 5);
-        if (s->vl_eq_vlmax) {
+        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
             tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
                                  MAXSZ(s), MAXSZ(s), simm);
             mark_vs_dirty(s);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
             TCGv_i64 s1;
             TCGv_ptr dest;
             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);
             static gen_helper_vmv_vx * const fns[4] = {
                 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
                 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
 
         TCGv_i64 t1;
 
-        if (s->vl_eq_vlmax) {
+        if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
             t1 = tcg_temp_new_i64();
             /* NaN-box f[rs1] */
             do_nanbox(s, t1, cpu_fpr[a->rs1]);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             TCGv_ptr dest;
             TCGv_i32 desc;
             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+            data = FIELD_DP32(data, VDATA, VTA, s->vta);
             static gen_helper_vmv_vx * const fns[3] = {
                 gen_helper_vmv_v_x_h,
                 gen_helper_vmv_v_x_w,
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline void
 vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
              CPURISCVState *env,
              uint32_t desc,
-             opivv2_rm_fn *fn)
+             opivv2_rm_fn *fn, uint32_t esz)
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
 
     switch (env->vxrm) {
     case 0: /* rnu */
@@ -XXX,XX +XXX,XX @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
                      env, vl, vm, 3, fn);
         break;
     }
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 }
 
 /* generate helpers for fixed point instructions with OPIVV format */
-#define GEN_VEXT_VV_RM(NAME)                                    \
+#define GEN_VEXT_VV_RM(NAME, ESZ)                               \
 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,     \
                   CPURISCVState *env, uint32_t desc)            \
 {                                                               \
     vext_vv_rm_2(vd, v0, vs1, vs2, env, desc,                   \
-                 do_##NAME);                                    \
+                 do_##NAME, ESZ);                               \
 }
 
 static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
 RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
 RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
 RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
-GEN_VEXT_VV_RM(vsaddu_vv_b)
-GEN_VEXT_VV_RM(vsaddu_vv_h)
-GEN_VEXT_VV_RM(vsaddu_vv_w)
-GEN_VEXT_VV_RM(vsaddu_vv_d)
+GEN_VEXT_VV_RM(vsaddu_vv_b, 1)
+GEN_VEXT_VV_RM(vsaddu_vv_h, 2)
+GEN_VEXT_VV_RM(vsaddu_vv_w, 4)
+GEN_VEXT_VV_RM(vsaddu_vv_d, 8)
 
 typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
                           CPURISCVState *env, int vxrm);
@@ -XXX,XX +XXX,XX @@ static inline void
 vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
              CPURISCVState *env,
              uint32_t desc,
-             opivx2_rm_fn *fn)
+             opivx2_rm_fn *fn, uint32_t esz)
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+    uint32_t vta = vext_vta(desc);
 
     switch (env->vxrm) {
     case 0: /* rnu */
@@ -XXX,XX +XXX,XX @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
                      env, vl, vm, 3, fn);
         break;
     }
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);
 }
 
 /* generate helpers for fixed point instructions with OPIVX format */
-#define GEN_VEXT_VX_RM(NAME)                              \
+#define GEN_VEXT_VX_RM(NAME, ESZ)                         \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
         void *vs2, CPURISCVState *env, uint32_t desc)     \
 {                                                         \
     vext_vx_rm_2(vd, v0, s1, vs2, env, desc,              \
-                 do_##NAME);                              \
+                 do_##NAME, ESZ);                         \
 }
 
 RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
 RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
 RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
 RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
-GEN_VEXT_VX_RM(vsaddu_vx_b)
-GEN_VEXT_VX_RM(vsaddu_vx_h)
-GEN_VEXT_VX_RM(vsaddu_vx_w)
-GEN_VEXT_VX_RM(vsaddu_vx_d)
+GEN_VEXT_VX_RM(vsaddu_vx_b, 1)
+GEN_VEXT_VX_RM(vsaddu_vx_h, 2)
+GEN_VEXT_VX_RM(vsaddu_vx_w, 4)
+GEN_VEXT_VX_RM(vsaddu_vx_d, 8)
 
 static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
 RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
 RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
 RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
-GEN_VEXT_VV_RM(vsadd_vv_b)
-GEN_VEXT_VV_RM(vsadd_vv_h)
-GEN_VEXT_VV_RM(vsadd_vv_w)
-GEN_VEXT_VV_RM(vsadd_vv_d)
+GEN_VEXT_VV_RM(vsadd_vv_b, 1)
+GEN_VEXT_VV_RM(vsadd_vv_h, 2)
+GEN_VEXT_VV_RM(vsadd_vv_w, 4)
+GEN_VEXT_VV_RM(vsadd_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
 RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
 RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
 RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
-GEN_VEXT_VX_RM(vsadd_vx_b)
-GEN_VEXT_VX_RM(vsadd_vx_h)
-GEN_VEXT_VX_RM(vsadd_vx_w)
-GEN_VEXT_VX_RM(vsadd_vx_d)
+GEN_VEXT_VX_RM(vsadd_vx_b, 1)
+GEN_VEXT_VX_RM(vsadd_vx_h, 2)
+GEN_VEXT_VX_RM(vsadd_vx_w, 4)
+GEN_VEXT_VX_RM(vsadd_vx_d, 8)
 
 static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
 RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
 RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
 RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
-GEN_VEXT_VV_RM(vssubu_vv_b)
-GEN_VEXT_VV_RM(vssubu_vv_h)
-GEN_VEXT_VV_RM(vssubu_vv_w)
-GEN_VEXT_VV_RM(vssubu_vv_d)
+GEN_VEXT_VV_RM(vssubu_vv_b, 1)
+GEN_VEXT_VV_RM(vssubu_vv_h, 2)
+GEN_VEXT_VV_RM(vssubu_vv_w, 4)
+GEN_VEXT_VV_RM(vssubu_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
 RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
 RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
 RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
-GEN_VEXT_VX_RM(vssubu_vx_b)
-GEN_VEXT_VX_RM(vssubu_vx_h)
-GEN_VEXT_VX_RM(vssubu_vx_w)
-GEN_VEXT_VX_RM(vssubu_vx_d)
+GEN_VEXT_VX_RM(vssubu_vx_b, 1)
+GEN_VEXT_VX_RM(vssubu_vx_h, 2)
+GEN_VEXT_VX_RM(vssubu_vx_w, 4)
+GEN_VEXT_VX_RM(vssubu_vx_d, 8)
 
 static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
 RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
 RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
 RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
-GEN_VEXT_VV_RM(vssub_vv_b)
-GEN_VEXT_VV_RM(vssub_vv_h)
-GEN_VEXT_VV_RM(vssub_vv_w)
-GEN_VEXT_VV_RM(vssub_vv_d)
+GEN_VEXT_VV_RM(vssub_vv_b, 1)
+GEN_VEXT_VV_RM(vssub_vv_h, 2)
+GEN_VEXT_VV_RM(vssub_vv_w, 4)
+GEN_VEXT_VV_RM(vssub_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
 RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
 RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
 RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
-GEN_VEXT_VX_RM(vssub_vx_b)
-GEN_VEXT_VX_RM(vssub_vx_h)
-GEN_VEXT_VX_RM(vssub_vx_w)
-GEN_VEXT_VX_RM(vssub_vx_d)
+GEN_VEXT_VX_RM(vssub_vx_b, 1)
+GEN_VEXT_VX_RM(vssub_vx_h, 2)
+GEN_VEXT_VX_RM(vssub_vx_w, 4)
+GEN_VEXT_VX_RM(vssub_vx_d, 8)
 
 /* Vector Single-Width Averaging Add and Subtract */
 static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
 RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
-GEN_VEXT_VV_RM(vaadd_vv_b)
-GEN_VEXT_VV_RM(vaadd_vv_h)
-GEN_VEXT_VV_RM(vaadd_vv_w)
-GEN_VEXT_VV_RM(vaadd_vv_d)
+GEN_VEXT_VV_RM(vaadd_vv_b, 1)
+GEN_VEXT_VV_RM(vaadd_vv_h, 2)
+GEN_VEXT_VV_RM(vaadd_vv_w, 4)
+GEN_VEXT_VV_RM(vaadd_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
 RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
-GEN_VEXT_VX_RM(vaadd_vx_b)
-GEN_VEXT_VX_RM(vaadd_vx_h)
-GEN_VEXT_VX_RM(vaadd_vx_w)
-GEN_VEXT_VX_RM(vaadd_vx_d)
+GEN_VEXT_VX_RM(vaadd_vx_b, 1)
+GEN_VEXT_VX_RM(vaadd_vx_h, 2)
+GEN_VEXT_VX_RM(vaadd_vx_w, 4)
+GEN_VEXT_VX_RM(vaadd_vx_d, 8)
 
 static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
                                uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
 RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
-GEN_VEXT_VV_RM(vaaddu_vv_b)
-GEN_VEXT_VV_RM(vaaddu_vv_h)
-GEN_VEXT_VV_RM(vaaddu_vv_w)
-GEN_VEXT_VV_RM(vaaddu_vv_d)
+GEN_VEXT_VV_RM(vaaddu_vv_b, 1)
+GEN_VEXT_VV_RM(vaaddu_vv_h, 2)
+GEN_VEXT_VV_RM(vaaddu_vv_w, 4)
+GEN_VEXT_VV_RM(vaaddu_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
 RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
-GEN_VEXT_VX_RM(vaaddu_vx_b)
-GEN_VEXT_VX_RM(vaaddu_vx_h)
-GEN_VEXT_VX_RM(vaaddu_vx_w)
-GEN_VEXT_VX_RM(vaaddu_vx_d)
+GEN_VEXT_VX_RM(vaaddu_vx_b, 1)
+GEN_VEXT_VX_RM(vaaddu_vx_h, 2)
+GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
+GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
 
 static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
 {
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
 RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
-GEN_VEXT_VV_RM(vasub_vv_b)
-GEN_VEXT_VV_RM(vasub_vv_h)
-GEN_VEXT_VV_RM(vasub_vv_w)
-GEN_VEXT_VV_RM(vasub_vv_d)
+GEN_VEXT_VV_RM(vasub_vv_b, 1)
+GEN_VEXT_VV_RM(vasub_vv_h, 2)
+GEN_VEXT_VV_RM(vasub_vv_w, 4)
+GEN_VEXT_VV_RM(vasub_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
 RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
-GEN_VEXT_VX_RM(vasub_vx_b)
-GEN_VEXT_VX_RM(vasub_vx_h)
-GEN_VEXT_VX_RM(vasub_vx_w)
-GEN_VEXT_VX_RM(vasub_vx_d)
+GEN_VEXT_VX_RM(vasub_vx_b, 1)
+GEN_VEXT_VX_RM(vasub_vx_h, 2)
+GEN_VEXT_VX_RM(vasub_vx_w, 4)
+GEN_VEXT_VX_RM(vasub_vx_d, 8)
 
 static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
                                uint32_t a, uint32_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
 RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
-GEN_VEXT_VV_RM(vasubu_vv_b)
-GEN_VEXT_VV_RM(vasubu_vv_h)
-GEN_VEXT_VV_RM(vasubu_vv_w)
-GEN_VEXT_VV_RM(vasubu_vv_d)
+GEN_VEXT_VV_RM(vasubu_vv_b, 1)
+GEN_VEXT_VV_RM(vasubu_vv_h, 2)
+GEN_VEXT_VV_RM(vasubu_vv_w, 4)
+GEN_VEXT_VV_RM(vasubu_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
 RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
-GEN_VEXT_VX_RM(vasubu_vx_b)
-GEN_VEXT_VX_RM(vasubu_vx_h)
-GEN_VEXT_VX_RM(vasubu_vx_w)
-GEN_VEXT_VX_RM(vasubu_vx_d)
+GEN_VEXT_VX_RM(vasubu_vx_b, 1)
+GEN_VEXT_VX_RM(vasubu_vx_h, 2)
+GEN_VEXT_VX_RM(vasubu_vx_w, 4)
+GEN_VEXT_VX_RM(vasubu_vx_d, 8)
 
 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
 static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
 RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
 RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
 RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
-GEN_VEXT_VV_RM(vsmul_vv_b)
-GEN_VEXT_VV_RM(vsmul_vv_h)
-GEN_VEXT_VV_RM(vsmul_vv_w)
-GEN_VEXT_VV_RM(vsmul_vv_d)
+GEN_VEXT_VV_RM(vsmul_vv_b, 1)
+GEN_VEXT_VV_RM(vsmul_vv_h, 2)
+GEN_VEXT_VV_RM(vsmul_vv_w, 4)
+GEN_VEXT_VV_RM(vsmul_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
 RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
 RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
 RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
-GEN_VEXT_VX_RM(vsmul_vx_b)
-GEN_VEXT_VX_RM(vsmul_vx_h)
-GEN_VEXT_VX_RM(vsmul_vx_w)
-GEN_VEXT_VX_RM(vsmul_vx_d)
+GEN_VEXT_VX_RM(vsmul_vx_b, 1)
+GEN_VEXT_VX_RM(vsmul_vx_h, 2)
+GEN_VEXT_VX_RM(vsmul_vx_w, 4)
+GEN_VEXT_VX_RM(vsmul_vx_d, 8)
 
 /* Vector Single-Width Scaling Shift Instructions */
 static inline uint8_t
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
 RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
 RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
 RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
-GEN_VEXT_VV_RM(vssrl_vv_b)
-GEN_VEXT_VV_RM(vssrl_vv_h)
-GEN_VEXT_VV_RM(vssrl_vv_w)
-GEN_VEXT_VV_RM(vssrl_vv_d)
+GEN_VEXT_VV_RM(vssrl_vv_b, 1)
+GEN_VEXT_VV_RM(vssrl_vv_h, 2)
+GEN_VEXT_VV_RM(vssrl_vv_w, 4)
+GEN_VEXT_VV_RM(vssrl_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
 RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
 RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
 RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
-GEN_VEXT_VX_RM(vssrl_vx_b)
-GEN_VEXT_VX_RM(vssrl_vx_h)
-GEN_VEXT_VX_RM(vssrl_vx_w)
-GEN_VEXT_VX_RM(vssrl_vx_d)
+GEN_VEXT_VX_RM(vssrl_vx_b, 1)
+GEN_VEXT_VX_RM(vssrl_vx_h, 2)
+GEN_VEXT_VX_RM(vssrl_vx_w, 4)
+GEN_VEXT_VX_RM(vssrl_vx_d, 8)
 
 static inline int8_t
 vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
 RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
 RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
 RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
-GEN_VEXT_VV_RM(vssra_vv_b)
-GEN_VEXT_VV_RM(vssra_vv_h)
-GEN_VEXT_VV_RM(vssra_vv_w)
-GEN_VEXT_VV_RM(vssra_vv_d)
+GEN_VEXT_VV_RM(vssra_vv_b, 1)
+GEN_VEXT_VV_RM(vssra_vv_h, 2)
+GEN_VEXT_VV_RM(vssra_vv_w, 4)
+GEN_VEXT_VV_RM(vssra_vv_d, 8)
 
 RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
 RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
 RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
 RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
-GEN_VEXT_VX_RM(vssra_vx_b)
-GEN_VEXT_VX_RM(vssra_vx_h)
-GEN_VEXT_VX_RM(vssra_vx_w)
-GEN_VEXT_VX_RM(vssra_vx_d)
+GEN_VEXT_VX_RM(vssra_vx_b, 1)
+GEN_VEXT_VX_RM(vssra_vx_h, 2)
+GEN_VEXT_VX_RM(vssra_vx_w, 4)
+GEN_VEXT_VX_RM(vssra_vx_d, 8)
 
 /* Vector Narrowing Fixed-Point Clip Instructions */
 static inline int8_t
@@ -XXX,XX +XXX,XX @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
 RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
 RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
 RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_wv_b)
-GEN_VEXT_VV_RM(vnclip_wv_h)
-GEN_VEXT_VV_RM(vnclip_wv_w)
+GEN_VEXT_VV_RM(vnclip_wv_b, 1)
+GEN_VEXT_VV_RM(vnclip_wv_h, 2)
+GEN_VEXT_VV_RM(vnclip_wv_w, 4)
 
 RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
 RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
 RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_wx_b)
-GEN_VEXT_VX_RM(vnclip_wx_h)
-GEN_VEXT_VX_RM(vnclip_wx_w)
+GEN_VEXT_VX_RM(vnclip_wx_b, 1)
+GEN_VEXT_VX_RM(vnclip_wx_h, 2)
+GEN_VEXT_VX_RM(vnclip_wx_w, 4)
 
 static inline uint8_t
 vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -XXX,XX +XXX,XX @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
 RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
 RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
 RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_wv_b)
-GEN_VEXT_VV_RM(vnclipu_wv_h)
-GEN_VEXT_VV_RM(vnclipu_wv_w)
+GEN_VEXT_VV_RM(vnclipu_wv_b, 1)
+GEN_VEXT_VV_RM(vnclipu_wv_h, 2)
+GEN_VEXT_VV_RM(vnclipu_wv_w, 4)
 
 RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
 RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
 RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_wx_b)
-GEN_VEXT_VX_RM(vnclipu_wx_h)
-GEN_VEXT_VX_RM(vnclipu_wx_w)
+GEN_VEXT_VX_RM(vnclipu_wx_b, 1)
+GEN_VEXT_VX_RM(vnclipu_wx_h, 2)
+GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
 
 /*
  *** Vector Float Point Arithmetic Instructions
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

Compares write mask registers, and so always operate under a tail-
agnostic policy.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-12@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c            | 440 +++++++++++++-----------
 target/riscv/insn_trans/trans_rvv.c.inc |  17 +
 2 files changed, 261 insertions(+), 196 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \
     *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status);         \
 }
 
-#define GEN_VEXT_VV_ENV(NAME)                             \
+#define GEN_VEXT_VV_ENV(NAME, ESZ)                        \
 void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
     uint32_t vm = vext_vm(desc);                          \
     uint32_t vl = env->vl;                                \
+    uint32_t total_elems =                                \
+        vext_get_total_elems(env, desc, ESZ);             \
+    uint32_t vta = vext_vta(desc);                        \
     uint32_t i;                                           \
                                                           \
     for (i = env->vstart; i < vl; i++) {                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
         do_##NAME(vd, vs1, vs2, i, env);                  \
     }                                                     \
     env->vstart = 0;                                      \
+    /* set tail elements to 1s */                         \
+    vext_set_elems_1s(vd, vta, vl * ESZ,                  \
+                      total_elems * ESZ);                 \
 }
 
 RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
 RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
 RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
-GEN_VEXT_VV_ENV(vfadd_vv_h)
-GEN_VEXT_VV_ENV(vfadd_vv_w)
-GEN_VEXT_VV_ENV(vfadd_vv_d)
+GEN_VEXT_VV_ENV(vfadd_vv_h, 2)
+GEN_VEXT_VV_ENV(vfadd_vv_w, 4)
+GEN_VEXT_VV_ENV(vfadd_vv_d, 8)
 
 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)        \
 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
     *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
 }
 
-#define GEN_VEXT_VF(NAME)                                 \
+#define GEN_VEXT_VF(NAME, ESZ)                            \
 void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
                   void *vs2, CPURISCVState *env,          \
                   uint32_t desc)                          \
 {                                                         \
     uint32_t vm = vext_vm(desc);                          \
     uint32_t vl = env->vl;                                \
+    uint32_t total_elems =                                \
+        vext_get_total_elems(env, desc, ESZ);              \
+    uint32_t vta = vext_vta(desc);                        \
     uint32_t i;                                           \
                                                           \
     for (i = env->vstart; i < vl; i++) {                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
         do_##NAME(vd, s1, vs2, i, env);                   \
     }                                                     \
     env->vstart = 0;                                      \
+    /* set tail elements to 1s */                         \
+    vext_set_elems_1s(vd, vta, vl * ESZ,                  \
+                      total_elems * ESZ);                 \
 }
 
 RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
 RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
 RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
-GEN_VEXT_VF(vfadd_vf_h)
-GEN_VEXT_VF(vfadd_vf_w)
-GEN_VEXT_VF(vfadd_vf_d)
+GEN_VEXT_VF(vfadd_vf_h, 2)
+GEN_VEXT_VF(vfadd_vf_w, 4)
+GEN_VEXT_VF(vfadd_vf_d, 8)
 
 RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
 RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
 RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
-GEN_VEXT_VV_ENV(vfsub_vv_h)
-GEN_VEXT_VV_ENV(vfsub_vv_w)
-GEN_VEXT_VV_ENV(vfsub_vv_d)
+GEN_VEXT_VV_ENV(vfsub_vv_h, 2)
+GEN_VEXT_VV_ENV(vfsub_vv_w, 4)
+GEN_VEXT_VV_ENV(vfsub_vv_d, 8)
 RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
 RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
 RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
-GEN_VEXT_VF(vfsub_vf_h)
-GEN_VEXT_VF(vfsub_vf_w)
-GEN_VEXT_VF(vfsub_vf_d)
+GEN_VEXT_VF(vfsub_vf_h, 2)
+GEN_VEXT_VF(vfsub_vf_w, 4)
+GEN_VEXT_VF(vfsub_vf_d, 8)
 
 static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
 RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
 RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
-GEN_VEXT_VF(vfrsub_vf_h)
-GEN_VEXT_VF(vfrsub_vf_w)
-GEN_VEXT_VF(vfrsub_vf_d)
+GEN_VEXT_VF(vfrsub_vf_h, 2)
+GEN_VEXT_VF(vfrsub_vf_w, 4)
+GEN_VEXT_VF(vfrsub_vf_d, 8)
 
 /* Vector Widening Floating-Point Add/Subtract Instructions */
 static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
 RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
-GEN_VEXT_VV_ENV(vfwadd_vv_h)
-GEN_VEXT_VV_ENV(vfwadd_vv_w)
+GEN_VEXT_VV_ENV(vfwadd_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwadd_vv_w, 8)
 RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
 RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
-GEN_VEXT_VF(vfwadd_vf_h)
-GEN_VEXT_VF(vfwadd_vf_w)
+GEN_VEXT_VF(vfwadd_vf_h, 4)
+GEN_VEXT_VF(vfwadd_vf_w, 8)
 
 static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
 RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
-GEN_VEXT_VV_ENV(vfwsub_vv_h)
-GEN_VEXT_VV_ENV(vfwsub_vv_w)
+GEN_VEXT_VV_ENV(vfwsub_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwsub_vv_w, 8)
 RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
 RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
-GEN_VEXT_VF(vfwsub_vf_h)
-GEN_VEXT_VF(vfwsub_vf_w)
+GEN_VEXT_VF(vfwsub_vf_h, 4)
+GEN_VEXT_VF(vfwsub_vf_w, 8)
 
 static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
 RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
-GEN_VEXT_VV_ENV(vfwadd_wv_h)
-GEN_VEXT_VV_ENV(vfwadd_wv_w)
+GEN_VEXT_VV_ENV(vfwadd_wv_h, 4)
+GEN_VEXT_VV_ENV(vfwadd_wv_w, 8)
 RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
 RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
-GEN_VEXT_VF(vfwadd_wf_h)
-GEN_VEXT_VF(vfwadd_wf_w)
+GEN_VEXT_VF(vfwadd_wf_h, 4)
+GEN_VEXT_VF(vfwadd_wf_w, 8)
 
 static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
 
 RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
 RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
-GEN_VEXT_VV_ENV(vfwsub_wv_h)
-GEN_VEXT_VV_ENV(vfwsub_wv_w)
+GEN_VEXT_VV_ENV(vfwsub_wv_h, 4)
+GEN_VEXT_VV_ENV(vfwsub_wv_w, 8)
 RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
 RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
-GEN_VEXT_VF(vfwsub_wf_h)
-GEN_VEXT_VF(vfwsub_wf_w)
+GEN_VEXT_VF(vfwsub_wf_h, 4)
+GEN_VEXT_VF(vfwsub_wf_w, 8)
 
 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
 RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
 RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
 RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
-GEN_VEXT_VV_ENV(vfmul_vv_h)
-GEN_VEXT_VV_ENV(vfmul_vv_w)
-GEN_VEXT_VV_ENV(vfmul_vv_d)
+GEN_VEXT_VV_ENV(vfmul_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmul_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmul_vv_d, 8)
 RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
 RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
 RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
-GEN_VEXT_VF(vfmul_vf_h)
-GEN_VEXT_VF(vfmul_vf_w)
-GEN_VEXT_VF(vfmul_vf_d)
+GEN_VEXT_VF(vfmul_vf_h, 2)
+GEN_VEXT_VF(vfmul_vf_w, 4)
+GEN_VEXT_VF(vfmul_vf_d, 8)
 
 RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
 RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
 RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
-GEN_VEXT_VV_ENV(vfdiv_vv_h)
-GEN_VEXT_VV_ENV(vfdiv_vv_w)
-GEN_VEXT_VV_ENV(vfdiv_vv_d)
+GEN_VEXT_VV_ENV(vfdiv_vv_h, 2)
+GEN_VEXT_VV_ENV(vfdiv_vv_w, 4)
+GEN_VEXT_VV_ENV(vfdiv_vv_d, 8)
 RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
 RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
 RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
-GEN_VEXT_VF(vfdiv_vf_h)
-GEN_VEXT_VF(vfdiv_vf_w)
-GEN_VEXT_VF(vfdiv_vf_d)
+GEN_VEXT_VF(vfdiv_vf_h, 2)
+GEN_VEXT_VF(vfdiv_vf_w, 4)
+GEN_VEXT_VF(vfdiv_vf_d, 8)
 
 static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
 RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
 RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
-GEN_VEXT_VF(vfrdiv_vf_h)
-GEN_VEXT_VF(vfrdiv_vf_w)
-GEN_VEXT_VF(vfrdiv_vf_d)
+GEN_VEXT_VF(vfrdiv_vf_h, 2)
+GEN_VEXT_VF(vfrdiv_vf_w, 4)
+GEN_VEXT_VF(vfrdiv_vf_d, 8)
 
 /* Vector Widening Floating-Point Multiply */
 static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
 }
 RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
 RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
-GEN_VEXT_VV_ENV(vfwmul_vv_h)
-GEN_VEXT_VV_ENV(vfwmul_vv_w)
+GEN_VEXT_VV_ENV(vfwmul_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwmul_vv_w, 8)
 RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
 RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
-GEN_VEXT_VF(vfwmul_vf_h)
-GEN_VEXT_VF(vfwmul_vf_w)
+GEN_VEXT_VF(vfwmul_vf_h, 4)
+GEN_VEXT_VF(vfwmul_vf_w, 8)
 
 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
 #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)       \
@@ -XXX,XX +XXX,XX @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
 RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
 RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
-GEN_VEXT_VV_ENV(vfmacc_vv_h)
-GEN_VEXT_VV_ENV(vfmacc_vv_w)
-GEN_VEXT_VV_ENV(vfmacc_vv_d)
+GEN_VEXT_VV_ENV(vfmacc_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmacc_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmacc_vv_d, 8)
 
 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)           \
 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i,    \
 RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
 RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
 RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
-GEN_VEXT_VF(vfmacc_vf_h)
-GEN_VEXT_VF(vfmacc_vf_w)
-GEN_VEXT_VF(vfmacc_vf_d)
+GEN_VEXT_VF(vfmacc_vf_h, 2)
+GEN_VEXT_VF(vfmacc_vf_w, 4)
+GEN_VEXT_VF(vfmacc_vf_d, 8)
 
 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
 RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
 RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
-GEN_VEXT_VV_ENV(vfnmacc_vv_h)
-GEN_VEXT_VV_ENV(vfnmacc_vv_w)
-GEN_VEXT_VV_ENV(vfnmacc_vv_d)
+GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2)
+GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4)
+GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8)
 RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
 RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
 RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
-GEN_VEXT_VF(vfnmacc_vf_h)
-GEN_VEXT_VF(vfnmacc_vf_w)
-GEN_VEXT_VF(vfnmacc_vf_d)
+GEN_VEXT_VF(vfnmacc_vf_h, 2)
+GEN_VEXT_VF(vfnmacc_vf_w, 4)
+GEN_VEXT_VF(vfnmacc_vf_d, 8)
 
 static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
 RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
 RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
-GEN_VEXT_VV_ENV(vfmsac_vv_h)
-GEN_VEXT_VV_ENV(vfmsac_vv_w)
-GEN_VEXT_VV_ENV(vfmsac_vv_d)
+GEN_VEXT_VV_ENV(vfmsac_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmsac_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmsac_vv_d, 8)
 RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
 RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
 RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
-GEN_VEXT_VF(vfmsac_vf_h)
-GEN_VEXT_VF(vfmsac_vf_w)
-GEN_VEXT_VF(vfmsac_vf_d)
+GEN_VEXT_VF(vfmsac_vf_h, 2)
+GEN_VEXT_VF(vfmsac_vf_w, 4)
+GEN_VEXT_VF(vfmsac_vf_d, 8)
 
 static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
 RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
 RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
-GEN_VEXT_VV_ENV(vfnmsac_vv_h)
-GEN_VEXT_VV_ENV(vfnmsac_vv_w)
-GEN_VEXT_VV_ENV(vfnmsac_vv_d)
+GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2)
+GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4)
+GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8)
 RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
 RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
 RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
-GEN_VEXT_VF(vfnmsac_vf_h)
-GEN_VEXT_VF(vfnmsac_vf_w)
-GEN_VEXT_VF(vfnmsac_vf_d)
+GEN_VEXT_VF(vfnmsac_vf_h, 2)
+GEN_VEXT_VF(vfnmsac_vf_w, 4)
+GEN_VEXT_VF(vfnmsac_vf_d, 8)
 
 static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
 RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
 RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
-GEN_VEXT_VV_ENV(vfmadd_vv_h)
-GEN_VEXT_VV_ENV(vfmadd_vv_w)
-GEN_VEXT_VV_ENV(vfmadd_vv_d)
+GEN_VEXT_VV_ENV(vfmadd_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmadd_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmadd_vv_d, 8)
 RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
 RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
 RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
-GEN_VEXT_VF(vfmadd_vf_h)
-GEN_VEXT_VF(vfmadd_vf_w)
-GEN_VEXT_VF(vfmadd_vf_d)
+GEN_VEXT_VF(vfmadd_vf_h, 2)
+GEN_VEXT_VF(vfmadd_vf_w, 4)
+GEN_VEXT_VF(vfmadd_vf_d, 8)
 
 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
 RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
 RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
-GEN_VEXT_VV_ENV(vfnmadd_vv_h)
-GEN_VEXT_VV_ENV(vfnmadd_vv_w)
-GEN_VEXT_VV_ENV(vfnmadd_vv_d)
+GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2)
+GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4)
+GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8)
 RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
 RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
 RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
-GEN_VEXT_VF(vfnmadd_vf_h)
-GEN_VEXT_VF(vfnmadd_vf_w)
-GEN_VEXT_VF(vfnmadd_vf_d)
+GEN_VEXT_VF(vfnmadd_vf_h, 2)
+GEN_VEXT_VF(vfnmadd_vf_w, 4)
+GEN_VEXT_VF(vfnmadd_vf_d, 8)
 
 static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
 RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
 RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
-GEN_VEXT_VV_ENV(vfmsub_vv_h)
-GEN_VEXT_VV_ENV(vfmsub_vv_w)
-GEN_VEXT_VV_ENV(vfmsub_vv_d)
+GEN_VEXT_VV_ENV(vfmsub_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmsub_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmsub_vv_d, 8)
 RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
 RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
 RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
-GEN_VEXT_VF(vfmsub_vf_h)
-GEN_VEXT_VF(vfmsub_vf_w)
-GEN_VEXT_VF(vfmsub_vf_d)
+GEN_VEXT_VF(vfmsub_vf_h, 2)
+GEN_VEXT_VF(vfmsub_vf_w, 4)
+GEN_VEXT_VF(vfmsub_vf_d, 8)
 
 static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
 RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
 RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
 RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
-GEN_VEXT_VV_ENV(vfnmsub_vv_h)
-GEN_VEXT_VV_ENV(vfnmsub_vv_w)
-GEN_VEXT_VV_ENV(vfnmsub_vv_d)
+GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2)
+GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4)
+GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8)
 RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
 RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
 RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
-GEN_VEXT_VF(vfnmsub_vf_h)
-GEN_VEXT_VF(vfnmsub_vf_w)
-GEN_VEXT_VF(vfnmsub_vf_d)
+GEN_VEXT_VF(vfnmsub_vf_h, 2)
+GEN_VEXT_VF(vfnmsub_vf_w, 4)
+GEN_VEXT_VF(vfnmsub_vf_d, 8)
 
 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
 static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
 RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
-GEN_VEXT_VV_ENV(vfwmacc_vv_h)
-GEN_VEXT_VV_ENV(vfwmacc_vv_w)
+GEN_VEXT_VV_ENV(vfwmacc_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwmacc_vv_w, 8)
 RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
 RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
-GEN_VEXT_VF(vfwmacc_vf_h)
-GEN_VEXT_VF(vfwmacc_vf_w)
+GEN_VEXT_VF(vfwmacc_vf_h, 4)
+GEN_VEXT_VF(vfwmacc_vf_w, 8)
 
 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
 RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_h)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_w)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 8)
 RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
 RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
-GEN_VEXT_VF(vfwnmacc_vf_h)
-GEN_VEXT_VF(vfwnmacc_vf_w)
+GEN_VEXT_VF(vfwnmacc_vf_h, 4)
+GEN_VEXT_VF(vfwnmacc_vf_w, 8)
 
 static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
 RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
-GEN_VEXT_VV_ENV(vfwmsac_vv_h)
-GEN_VEXT_VV_ENV(vfwmsac_vv_w)
+GEN_VEXT_VV_ENV(vfwmsac_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwmsac_vv_w, 8)
 RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
 RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
-GEN_VEXT_VF(vfwmsac_vf_h)
-GEN_VEXT_VF(vfwmsac_vf_w)
+GEN_VEXT_VF(vfwmsac_vf_h, 4)
+GEN_VEXT_VF(vfwmsac_vf_w, 8)
 
 static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
 RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_h)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_w)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 4)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 8)
 RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
 RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
-GEN_VEXT_VF(vfwnmsac_vf_h)
-GEN_VEXT_VF(vfwnmsac_vf_w)
+GEN_VEXT_VF(vfwnmsac_vf_h, 4)
+GEN_VEXT_VF(vfwnmsac_vf_w, 8)
 
 /* Vector Floating-Point Square-Root Instruction */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i,      \
     *((TD *)vd + HD(i)) = OP(s2, &env->fp_status);     \
 }
 
-#define GEN_VEXT_V_ENV(NAME)                           \
+#define GEN_VEXT_V_ENV(NAME, ESZ)                      \
 void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
         CPURISCVState *env, uint32_t desc)             \
 {                                                      \
     uint32_t vm = vext_vm(desc);                       \
     uint32_t vl = env->vl;                             \
+    uint32_t total_elems =                             \
+        vext_get_total_elems(env, desc, ESZ);          \
+    uint32_t vta = vext_vta(desc);                     \
     uint32_t i;                                        \
                                                        \
     if (vl == 0) {                                     \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
         do_##NAME(vd, vs2, i, env);                    \
     }                                                  \
     env->vstart = 0;                                   \
+    vext_set_elems_1s(vd, vta, vl * ESZ,               \
+                      total_elems * ESZ);              \
 }
 
 RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
 RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
 RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
-GEN_VEXT_V_ENV(vfsqrt_v_h)
-GEN_VEXT_V_ENV(vfsqrt_v_w)
-GEN_VEXT_V_ENV(vfsqrt_v_d)
+GEN_VEXT_V_ENV(vfsqrt_v_h, 2)
+GEN_VEXT_V_ENV(vfsqrt_v_w, 4)
+GEN_VEXT_V_ENV(vfsqrt_v_d, 8)
 
 /*
  * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frsqrt7_d(float64 f, float_status *s)
 RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
 RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
 RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
-GEN_VEXT_V_ENV(vfrsqrt7_v_h)
-GEN_VEXT_V_ENV(vfrsqrt7_v_w)
-GEN_VEXT_V_ENV(vfrsqrt7_v_d)
+GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2)
+GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4)
+GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8)
 
 /*
  * Vector Floating-Point Reciprocal Estimate Instruction
@@ -XXX,XX +XXX,XX @@ static float64 frec7_d(float64 f, float_status *s)
 RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
 RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
 RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
-GEN_VEXT_V_ENV(vfrec7_v_h)
-GEN_VEXT_V_ENV(vfrec7_v_w)
-GEN_VEXT_V_ENV(vfrec7_v_d)
+GEN_VEXT_V_ENV(vfrec7_v_h, 2)
+GEN_VEXT_V_ENV(vfrec7_v_w, 4)
+GEN_VEXT_V_ENV(vfrec7_v_d, 8)
 
 /* Vector Floating-Point MIN/MAX Instructions */
 RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
 RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
 RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
-GEN_VEXT_VV_ENV(vfmin_vv_h)
-GEN_VEXT_VV_ENV(vfmin_vv_w)
-GEN_VEXT_VV_ENV(vfmin_vv_d)
+GEN_VEXT_VV_ENV(vfmin_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmin_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmin_vv_d, 8)
 RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
 RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
 RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
-GEN_VEXT_VF(vfmin_vf_h)
-GEN_VEXT_VF(vfmin_vf_w)
-GEN_VEXT_VF(vfmin_vf_d)
+GEN_VEXT_VF(vfmin_vf_h, 2)
+GEN_VEXT_VF(vfmin_vf_w, 4)
+GEN_VEXT_VF(vfmin_vf_d, 8)
 
 RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
 RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
 RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
-GEN_VEXT_VV_ENV(vfmax_vv_h)
-GEN_VEXT_VV_ENV(vfmax_vv_w)
-GEN_VEXT_VV_ENV(vfmax_vv_d)
+GEN_VEXT_VV_ENV(vfmax_vv_h, 2)
+GEN_VEXT_VV_ENV(vfmax_vv_w, 4)
+GEN_VEXT_VV_ENV(vfmax_vv_d, 8)
 RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
 RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
 RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
-GEN_VEXT_VF(vfmax_vf_h)
-GEN_VEXT_VF(vfmax_vf_w)
-GEN_VEXT_VF(vfmax_vf_d)
+GEN_VEXT_VF(vfmax_vf_h, 2)
+GEN_VEXT_VF(vfmax_vf_w, 4)
+GEN_VEXT_VF(vfmax_vf_d, 8)
 
 /* Vector Floating-Point Sign-Injection Instructions */
 static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
 RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
 RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
-GEN_VEXT_VV_ENV(vfsgnj_vv_h)
-GEN_VEXT_VV_ENV(vfsgnj_vv_w)
-GEN_VEXT_VV_ENV(vfsgnj_vv_d)
+GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2)
+GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4)
+GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8)
 RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
 RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
 RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
-GEN_VEXT_VF(vfsgnj_vf_h)
-GEN_VEXT_VF(vfsgnj_vf_w)
-GEN_VEXT_VF(vfsgnj_vf_d)
+GEN_VEXT_VF(vfsgnj_vf_h, 2)
+GEN_VEXT_VF(vfsgnj_vf_w, 4)
+GEN_VEXT_VF(vfsgnj_vf_d, 8)
 
 static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
 RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
 RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_h)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_w)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_d)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8)
 RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
 RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
 RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
-GEN_VEXT_VF(vfsgnjn_vf_h)
-GEN_VEXT_VF(vfsgnjn_vf_w)
-GEN_VEXT_VF(vfsgnjn_vf_d)
+GEN_VEXT_VF(vfsgnjn_vf_h, 2)
+GEN_VEXT_VF(vfsgnjn_vf_w, 4)
+GEN_VEXT_VF(vfsgnjn_vf_d, 8)
 
 static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
 RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
 RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
 RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_h)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_w)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_d)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8)
 RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
 RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
 RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
-GEN_VEXT_VF(vfsgnjx_vf_h)
-GEN_VEXT_VF(vfsgnjx_vf_w)
-GEN_VEXT_VF(vfsgnjx_vf_d)
+GEN_VEXT_VF(vfsgnjx_vf_h, 2)
+GEN_VEXT_VF(vfsgnjx_vf_w, 4)
+GEN_VEXT_VF(vfsgnjx_vf_d, 8)
 
 /* Vector Floating-Point Compare Instructions */
 #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP)            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
 {                                                             \
     uint32_t vm = vext_vm(desc);                              \
     uint32_t vl = env->vl;                                    \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
     uint32_t i;                                               \
                                                               \
     for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,   \
                            DO_OP(s2, s1, &env->fp_status));   \
     }                                                         \
     env->vstart = 0;                                          \
+    /* mask destination register are always tail-agnostic */  \
+    /* set tail elements to 1s */                             \
+    if (vta_all_1s) {                                         \
+        for (; i < total_elems; i++) {                        \
+            vext_set_elem_mask(vd, i, 1);                     \
+        }                                                     \
+    }                                                         \
 }
 
 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2,       \
 {                                                                   \
     uint32_t vm = vext_vm(desc);                                    \
     uint32_t vl = env->vl;                                          \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;              \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                    \
     uint32_t i;                                                     \
                                                                     \
     for (i = env->vstart; i < vl; i++) {                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2,       \
                            DO_OP(s2, (ETYPE)s1, &env->fp_status));  \
     }                                                               \
     env->vstart = 0;                                                \
+    /* mask destination register are always tail-agnostic */        \
+    /* set tail elements to 1s */                                   \
+    if (vta_all_1s) {                                               \
+        for (; i < total_elems; i++) {                              \
+            vext_set_elem_mask(vd, i, 1);                           \
+        }                                                           \
+    }                                                               \
 }
 
 GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
@@ -XXX,XX +XXX,XX @@ static void do_##NAME(void *vd, void *vs2, int i)      \
     *((TD *)vd + HD(i)) = OP(s2);                      \
 }
 
-#define GEN_VEXT_V(NAME)                               \
+#define GEN_VEXT_V(NAME, ESZ)                          \
 void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
                   CPURISCVState *env, uint32_t desc)   \
 {                                                      \
     uint32_t vm = vext_vm(desc);                       \
     uint32_t vl = env->vl;                             \
+    uint32_t total_elems =                             \
+        vext_get_total_elems(env, desc, ESZ);          \
+    uint32_t vta = vext_vta(desc);                     \
     uint32_t i;                                        \
                                                        \
     for (i = env->vstart; i < vl; i++) {               \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
         do_##NAME(vd, vs2, i);                         \
     }                                                  \
     env->vstart = 0;                                   \
+    /* set tail elements to 1s */                      \
+    vext_set_elems_1s(vd, vta, vl * ESZ,               \
+                      total_elems * ESZ);              \
 }
 
 target_ulong fclass_h(uint64_t frs1)
@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1)
 RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
 RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
 RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
-GEN_VEXT_V(vfclass_v_h)
-GEN_VEXT_V(vfclass_v_w)
-GEN_VEXT_V(vfclass_v_d)
+GEN_VEXT_V(vfclass_v_h, 2)
+GEN_VEXT_V(vfclass_v_w, 4)
+GEN_VEXT_V(vfclass_v_d, 8)
 
 /* Vector Floating-Point Merge Instruction */
+
 #define GEN_VFMERGE_VF(NAME, ETYPE, H)                        \
 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
                   CPURISCVState *env, uint32_t desc)          \
 {                                                             \
     uint32_t vm = vext_vm(desc);                              \
     uint32_t vl = env->vl;                                    \
+    uint32_t esz = sizeof(ETYPE);                             \
+    uint32_t total_elems =                                    \
+        vext_get_total_elems(env, desc, esz);                 \
+    uint32_t vta = vext_vta(desc);                            \
     uint32_t i;                                               \
                                                               \
     for (i = env->vstart; i < vl; i++) {                      \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
           = (!vm && !vext_elem_mask(v0, i) ? s2 : s1);        \
     }                                                         \
     env->vstart = 0;                                          \
+    /* set tail elements to 1s */                             \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);  \
 }
 
 GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2)
@@ -XXX,XX +XXX,XX @@ GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
 RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_h)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_w)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_d)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8)
 
 /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
 RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
 RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
 RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_h)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_w)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_d)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8)
 
 /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
 RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
 RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
 RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_h)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_w)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_d)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8)
 
 /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
 RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
 RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
 RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_h)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_w)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8)
 
 /* Widening Floating-Point/Integer Type-Convert Instructions */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d)
 /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
 RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
 RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 8)
 
 /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */
 RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32)
 RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_h)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_w)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
 
 /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
 RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 2)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 8)
 
 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
 RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
 RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
 RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_b)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_h)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_w)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 2)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
 
 /*
  * vfwcvt.f.f.v vd, vs2, vm
@@ -XXX,XX +XXX,XX @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
 
 RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16)
 RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_h)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8)
 
 /* Narrowing Floating-Point/Integer Type-Convert Instructions */
 /* (TD, T2, TX2) */
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
 RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_b)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_h)
-GEN_VEXT_V_ENV(vfncvt_xu_f_w_w)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4)
 
 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
 RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
 RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
 RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_b)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_h)
-GEN_VEXT_V_ENV(vfncvt_x_f_w_w)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
 
 /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
 RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
 RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_w_h)
-GEN_VEXT_V_ENV(vfncvt_f_xu_w_w)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4)
 
 /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
 RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
 RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_w_h)
-GEN_VEXT_V_ENV(vfncvt_f_x_w_w)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4)
 
 /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
 static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -XXX,XX +XXX,XX @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
 
 RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
 RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_w_h)
-GEN_VEXT_V_ENV(vfncvt_f_f_w_w)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
 
 /*
  *** Vector Reduction Operations
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data =                                                     \
+            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)            \
         gen_set_rm(s, RISCV_FRM_DYN);                             \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);            \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);              \
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S,                \
+                          s->cfg_vta_all_1s);                     \
         return opfvf_trans(a->rd, a->rs1, a->rs2, data,           \
                            fns[s->sew - 1], s);                   \
     }                                                             \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
                                                                  \
         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                            vreg_ofs(s, a->rs1),                  \
                            vreg_ofs(s, a->rs2), cpu_env,         \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         gen_set_rm(s, RISCV_FRM_DYN);                            \
         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
         return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                            fns[s->sew - 1], s);                  \
     }                                                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
         gen_set_rm(s, RISCV_FRM_DYN);                            \
         data = FIELD_DP32(data, VDATA, VM, a->vm);               \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
         return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                            fns[s->sew - 1], s);                  \
     }                                                            \
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs2), cpu_env,
                            s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
                            s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
                            s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
                            s->cfg_ptr->vlen / 8,                   \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs2), cpu_env,           \
                            s->cfg_ptr->vlen / 8,                   \
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
 {                                                         \
     uint32_t vm = vext_vm(desc);                          \
     uint32_t vl = env->vl;                                \
+    uint32_t esz = sizeof(TD);                            \
+    uint32_t vlenb = simd_maxsz(desc);                    \
+    uint32_t vta = vext_vta(desc);                        \
     uint32_t i;                                           \
     TD s1 =  *((TD *)vs1 + HD(0));                        \
                                                           \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
     }                                                     \
     *((TD *)vd + HD(0)) = s1;                             \
     env->vstart = 0;                                      \
+    /* set tail elements to 1s */                         \
+    vext_set_elems_1s(vd, vta, esz, vlenb);               \
 }
 
 /* vd[0] = sum(vs1[0], vs2[*]) */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,           \
 {                                                          \
     uint32_t vm = vext_vm(desc);                           \
     uint32_t vl = env->vl;                                 \
+    uint32_t esz = sizeof(TD);                             \
+    uint32_t vlenb = simd_maxsz(desc);                     \
+    uint32_t vta = vext_vta(desc);                         \
     uint32_t i;                                            \
     TD s1 =  *((TD *)vs1 + HD(0));                         \
                                                            \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,           \
     }                                                      \
     *((TD *)vd + HD(0)) = s1;                              \
     env->vstart = 0;                                       \
+    /* set tail elements to 1s */                          \
+    vext_set_elems_1s(vd, vta, esz, vlenb);                \
 }
 
 /* Unordered sum */
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t esz = sizeof(uint32_t);
+    uint32_t vlenb = simd_maxsz(desc);
+    uint32_t vta = vext_vta(desc);
     uint32_t i;
     uint32_t s1 =  *((uint32_t *)vs1 + H4(0));
 
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
     }
     *((uint32_t *)vd + H4(0)) = s1;
     env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, esz, vlenb);
 }
 
 void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t esz = sizeof(uint64_t);
+    uint32_t vlenb = simd_maxsz(desc);
+    uint32_t vta = vext_vta(desc);
     uint32_t i;
     uint64_t s1 =  *((uint64_t *)vs1);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
     }
     *((uint64_t *)vd) = s1;
     env->vstart = 0;
+    /* set tail elements to 1s */
+    vext_set_elems_1s(vd, vta, esz, vlenb);
 }
 
 /*
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

The tail elements in the destination mask register are updated under
a tail-agnostic policy.

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
                   uint32_t desc)                          \
 {                                                         \
     uint32_t vl = env->vl;                                \
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;    \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);          \
     uint32_t i;                                           \
     int a, b;                                             \
                                                           \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
         vext_set_elem_mask(vd, i, OP(b, a));              \
     }                                                     \
     env->vstart = 0;                                      \
+    /* mask destination register are always tail-         \
+     * agnostic                                           \
+     */                                                   \
+    /* set tail elements to 1s */                         \
+    if (vta_all_1s) {                                     \
+        for (; i < total_elems; i++) {                    \
+            vext_set_elem_mask(vd, i, 1);                 \
+        }                                                 \
+    }                                                     \
 }
 
 #define DO_NAND(N, M)  (!(N & M))
@@ -XXX,XX +XXX,XX @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
 {
     uint32_t vm = vext_vm(desc);
     uint32_t vl = env->vl;
+    uint32_t total_elems = env_archcpu(env)->cfg.vlen;
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);
     int i;
     bool first_mask_bit = false;
 
@@ -XXX,XX +XXX,XX @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
         }
     }
     env->vstart = 0;
+    /* mask destination register are always tail-agnostic */
+    /* set tail elements to 1s */
+    if (vta_all_1s) {
+        for (; i < total_elems; i++) {
+            vext_set_elem_mask(vd, i, 1);
+        }
+    }
 }
 
 void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env,      \
 {                                                                         \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     uint32_t sum = 0;                                                     \
     int i;                                                                \
                                                                           \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env,      \
         }                                                                 \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 GEN_VEXT_VIOTA_M(viota_m_b, uint8_t,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc)  \
 {                                                                         \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     int i;                                                                \
                                                                           \
     for (i = env->vstart; i < vl; i++) {                                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc)  \
         *((ETYPE *)vd + H(i)) = i;                                        \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 GEN_VEXT_VID_V(vid_v_b, uint8_t,  H1)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a)                \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data =                                                     \
+            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                            vreg_ofs(s, a->rs1),                    \
                            vreg_ofs(s, a->rs2), cpu_env,           \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                                    \
         data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
+        data =                                                     \
+            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
                            vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
                            cpu_env, s->cfg_ptr->vlen / 8,          \
@@ -XXX,XX +XXX,XX @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         static gen_helper_gvec_3_ptr * const fns[4] = {
             gen_helper_viota_m_b, gen_helper_viota_m_h,
             gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
 
         data = FIELD_DP32(data, VDATA, VM, a->vm);
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         static gen_helper_gvec_2_ptr * const fns[4] = {
             gen_helper_vid_v_b, gen_helper_vid_v_h,
             gen_helper_vid_v_w, gen_helper_vid_v_d,
-- 
2.36.1

From: eopXD <yueh.ting.chen@gmail.com>

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-15@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c            | 40 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc |  7 +++--
 2 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
 {                                                                         \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     target_ulong offset = s1, i_min, i;                                   \
                                                                           \
     i_min = MAX(env->vstart, offset);                                     \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
         }                                                                 \
         *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset));          \
     }                                                                     \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
     uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE)));           \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     target_ulong i_max, i;                                                \
                                                                           \
     i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart);       \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
     }                                                                     \
                                                                           \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -XXX,XX +XXX,XX @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
     typedef uint##BITWIDTH##_t ETYPE;                                       \
     uint32_t vm = vext_vm(desc);                                            \
     uint32_t vl = env->vl;                                                  \
+    uint32_t esz = sizeof(ETYPE);                                           \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);            \
+    uint32_t vta = vext_vta(desc);                                          \
     uint32_t i;                                                             \
                                                                             \
     for (i = env->vstart; i < vl; i++) {                                    \
@@ -XXX,XX +XXX,XX @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
         }                                                                   \
     }                                                                       \
     env->vstart = 0;                                                        \
+    /* set tail elements to 1s */                                           \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);                \
 }
 
 GEN_VEXT_VSLIE1UP(8,  H1)
@@ -XXX,XX +XXX,XX @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
     typedef uint##BITWIDTH##_t ETYPE;                                         \
     uint32_t vm = vext_vm(desc);                                              \
     uint32_t vl = env->vl;                                                    \
+    uint32_t esz = sizeof(ETYPE);                                             \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);              \
+    uint32_t vta = vext_vta(desc);                                            \
     uint32_t i;                                                               \
                                                                               \
     for (i = env->vstart; i < vl; i++) {                                      \
@@ -XXX,XX +XXX,XX @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
         }                                                                     \
     }                                                                         \
     env->vstart = 0;                                                          \
+    /* set tail elements to 1s */                                             \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);                  \
 }
 
 GEN_VEXT_VSLIDE1DOWN(8,  H1)
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
     uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2)));             \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(TS2);                                           \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     uint64_t index;                                                       \
     uint32_t i;                                                           \
                                                                           \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
         }                                                                 \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
     uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE)));           \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     uint64_t index = s1;                                                  \
     uint32_t i;                                                           \
                                                                           \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
         }                                                                 \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
                   CPURISCVState *env, uint32_t desc)                      \
 {                                                                         \
     uint32_t vl = env->vl;                                                \
+    uint32_t esz = sizeof(ETYPE);                                         \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz);          \
+    uint32_t vta = vext_vta(desc);                                        \
     uint32_t num = 0, i;                                                  \
                                                                           \
     for (i = env->vstart; i < vl; i++) {                                  \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
         num++;                                                            \
     }                                                                     \
     env->vstart = 0;                                                      \
+    /* set tail elements to 1s */                                         \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
 }
 
 /* Compress into vd elements of vs2 where vs1 is enabled */
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,                 \
 {                                                                \
     uint32_t vl = env->vl;                                       \
     uint32_t vm = vext_vm(desc);                                 \
+    uint32_t esz = sizeof(ETYPE);                                \
+    uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+    uint32_t vta = vext_vta(desc);                               \
     uint32_t i;                                                  \
                                                                  \
     for (i = env->vstart; i < vl; i++) {                         \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,                 \
         *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i));       \
     }                                                            \
     env->vstart = 0;                                             \
+    /* set tail elements to 1s */                                \
+    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);     \
 }
 
 GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t,  H2, H1)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
         return false;
     }
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         int scale = s->lmul - (s->sew + 3);
         int vlmax = s->cfg_ptr->vlen >> -scale;
         TCGv_i64 dest = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
         return false;
     }
 
-    if (a->vm && s->vl_eq_vlmax) {
+    if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
         int scale = s->lmul - (s->sew + 3);
         int vlmax = s->cfg_ptr->vlen >> -scale;
         if (a->rs1 >= vlmax) {
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
         data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
         tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                            vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
                            cpu_env, s->cfg_ptr->vlen / 8,
@@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
     }
 
     data = FIELD_DP32(data, VDATA, VM, a->vm);
+    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
 
     tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                        vreg_ofs(s, a->rs2), cpu_env,
-- 
2.36.1

From: eopXD <eop.chen@sifive.com>

This commit adds option 'rvv_ta_all_1s' is added to enable the
behavior, it is default as disabled.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-16@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 
     DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+
+    DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.36.1

From: Alistair Francis <alistair.francis@wdc.com>

There are currently two types of RISC-V CPUs:
 - Generic CPUs (base or any) that allow complete custimisation
 - "Named" CPUs that match existing hardware

Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.

We originally exposed these as part of the named CPUs as well, but that was
by accident.

Exposing the CPU properties to named CPUs means that we accidently
enable extensions that don't exist on the CPUs by default. For example
the SiFive E CPU currently support the zba extension, which is a bug.

This patch instead only exposes the CPU extensions to the generic CPUs.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 46 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
     "reserved"
 };
 
+static void register_cpu_props(DeviceState *dev);
+
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
     if (async) {
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
     set_priv_version(env, PRIV_VERSION_1_12_0);
+    register_cpu_props(DEVICE(obj));
 }
 
 #if defined(TARGET_RISCV64)
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV64, 0);
+    register_cpu_props(DEVICE(obj));
 }
 
 static void rv64_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
 static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    cpu->cfg.mmu = false;
 }
 
 static void rv128_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV128, 0);
+    register_cpu_props(DEVICE(obj));
 }
 #else
 static void rv32_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV32, 0);
+    register_cpu_props(DEVICE(obj));
 }
 
 static void rv32_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
 static void rv32_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    cpu->cfg.mmu = false;
 }
 
 static void rv32_ibex_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
-    qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
+    cpu->cfg.mmu = false;
+    cpu->cfg.epmp = true;
 }
 
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
-    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    cpu->cfg.mmu = false;
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
 #elif defined(TARGET_RISCV64)
     set_misa(env, MXL_RV64, 0);
 #endif
+    register_cpu_props(DEVICE(obj));
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
 
+    cpu->cfg.ext_counters = true;
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.mmu = true;
+    cpu->cfg.pmp = true;
+
     cpu_set_cpustate_pointers(cpu);
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 #endif /* CONFIG_USER_ONLY */
 }
 
-static Property riscv_cpu_properties[] = {
+static Property riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
-    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
-    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
-    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
-
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
 
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void register_cpu_props(DeviceState *dev)
+{
+    Property *prop;
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
+}
+
+static Property riscv_cpu_properties[] = {
+    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+
+    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
+
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 
     DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
-- 
2.36.1

From: Alistair Francis <alistair.francis@wdc.com>

When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().

This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)