Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/23] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
   Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220525
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 8fe63fe8e512d77583d6798acd2164f1fa1e40ab:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  hw/core: loader: Set is_linux to true for VxWorks uImage (2022-05-24 10:38:50 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Third RISC-V PR for QEMU 7.1
-This PR includes:
+ * Fixes for accessing VS hypervisor CSRs
- - Fix for vector CSR access
+ * Improvements for RISC-V Vector extension
- - Improvements to the Ibex UART device
+ * Fixes for accessing mtimecmp
- - PMP improvements and bug fixes
+ * Add new short-isa-string CPU option
- - Hypervisor extension bug fixes
+ * Improvements to RISC-V machine error handling
- - ramfb support for the virt machine
+ * Disable the "G" extension by default internally, no functional change
- - Fast read support for SST flash
+ * Enforce floating point extension requirements
- - Improvements to the microchip_pfsoc machine
+ * Cleanup ISA extension checks
  * Resolve redundant property accessors
  * Fix typo of mimpid cpu option
  * Improvements for virtulisation
  * Add zicsr/zifencei to isa_string
  * Support for VxWorks uImage
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Anup Patel (4):
-      hw/char: disable ibex uart receive if the buffer is full
+      target/riscv: Fix csr number based privilege checking
       target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
       target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
       hw/riscv: virt: Fix interrupt parent for dynamic platform devices
-Asherah Connor (2):
+Atish Patra (1):
-      hw/riscv: Add fw_cfg support to virt
+      hw/intc: Pass correct hartid while updating mtimecmp
       hw/riscv: allow ramfb on virt
-Bin Meng (3):
+Bernhard Beschow (2):
-      hw/block: m25p80: Support fast read for SST flashes
+      hw/vfio/pci-quirks: Resolve redundant property getters
-      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+      hw/riscv/sifive_u: Resolve redundant property accessors
-      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
 Bin Meng (2):
       hw/core: Sync uboot_image.h from U-Boot v2022.01
       hw/core: loader: Set is_linux to true for VxWorks uImage
 Dylan Reid (1):
       target/riscv: Fix VS mode hypervisor CSR access
 Frank Chang (1):
-      target/riscv: fix vs() to return proper error code
+      target/riscv: Fix typo of mimpid cpu option
-Georg Kotheimer (6):
+Hongren (Zenithal) Zheng (1):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+      target/riscv: add zicsr/zifencei to isa_string
       target/riscv: Make VSTIP and VSEIP read-only in hip
       target/riscv: Use background registers also for MSTATUS_MPV
       target/riscv: Fix read and write accesses to vsip and vsie
       target/riscv: Add proper two-stage lookup exception detection
       target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
+Tsukasa OI (9):
-      target/riscv: propagate PMP permission to TLB page
+      target/riscv: Move Zhinx* extensions on ISA string
-      target/riscv: add log of PMP permission checking
+      target/riscv: Add short-isa-string option
-      target/riscv: flush TLB pages if PMP permission has been changed
+      hw/riscv: Make CPU config error handling generous (virt/spike)
       hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
       target/riscv: Fix coding style on "G" expansion
       target/riscv: Disable "G" by default
       target/riscv: Change "G" expansion
       target/riscv: FP extension requirements
       target/riscv: Move/refactor ISA extension checks
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
+Weiwei Li (1):
- docs/system/target-riscv.rst               |   1 +
+      target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
  include/hw/char/ibex_uart.h                |   4 +
  include/hw/riscv/microchip_pfsoc.h         |   1 +
  include/hw/riscv/virt.h                    |   2 +
  target/riscv/cpu.h                         |   4 +
  target/riscv/pmp.h                         |   4 +-
  hw/block/m25p80.c                          |   3 +
  hw/char/ibex_uart.c                        |  23 +++-
  hw/riscv/microchip_pfsoc.c                 |   6 +
  hw/riscv/virt.c                            |  33 ++++++
  target/riscv/cpu.c                         |   1 +
  target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
  target/riscv/csr.c                         |  77 +++++++------
  target/riscv/pmp.c                         |  84 ++++++++++----
  target/riscv/translate.c                   | 179 +----------------------------
  hw/riscv/Kconfig                           |   1 +
 files changed, 367 insertions(+), 289 deletions(-)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+eopXD (1):
+      target/riscv: rvv: Fix early exit condition for whole register load/store
+ hw/core/uboot_image.h                   | 213 +++++++++++++++++++++-----------
+ target/riscv/cpu.h                      |  12 +-
+ hw/core/loader.c                        |  15 +++
+ hw/intc/riscv_aclint.c                  |   3 +-
+ hw/riscv/opentitan.c                    |   2 +-
+ hw/riscv/sifive_e.c                     |   2 +-
+ hw/riscv/sifive_u.c                     |  28 +----
+ hw/riscv/spike.c                        |   2 +-
+ hw/riscv/virt.c                         |  27 ++--
+ hw/vfio/pci-quirks.c                    |  34 ++---
+ target/riscv/cpu.c                      |  91 ++++++++++----
+ target/riscv/cpu_helper.c               |   4 +-
+ target/riscv/csr.c                      |  26 ++--
+ target/riscv/translate.c                |  17 ++-
+ target/riscv/insn_trans/trans_rvv.c.inc |  58 +++++----
+files changed, 325 insertions(+), 209 deletions(-)

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Dylan Reid <dylan@rivosinc.com>
-The previous implementation was broken in many ways:
+VS mode access to hypervisor CSRs should generate virtual, not illegal,
- - Used mideleg instead of hideleg to mask accesses
+instruction exceptions.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Don't return early and indicate an illegal instruction exception when
 accessing a hypervisor CSR from VS mode. Instead, fall through to the
 `hmode` predicate to return the correct virtual instruction exception.
 Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/csr.c | 10 +++++-----
-file changed, 34 insertions(+), 34 deletions(-)
+file changed, 5 insertions(+), 5 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
-     return write_mstatus(env, CSR_MSTATUS, newval);
+ #if !defined(CONFIG_USER_ONLY)
- }
+     int effective_priv = env->priv;
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+-    if (riscv_has_ext(env, RVH) &&
-+{
+-        env->priv == PRV_S &&
-+    /* Shift the VS bits to their S bit location in vsie */
+-        !riscv_cpu_virt_enabled(env)) {
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
-+    return 0;
+         /*
-+}
+-         * We are in S mode without virtualisation, therefore we are in HS Mode.
-+
++         * We are in either HS or VS mode.
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+          * Add 1 to the effective privledge level to allow us to access the
- {
+-         * Hypervisor CSRs.
-     if (riscv_cpu_virt_enabled(env)) {
++         * Hypervisor CSRs. The `hmode` predicate will determine if access
--        /* Tell the guest the VS bits, shifted to the S bit locations */
++         * should be allowed(HS) or if a virtual instruction exception should be
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
++         * raised(VS).
-+        read_vsie(env, CSR_VSIE, val);
+          */
-     } else {
+         effective_priv++;
          *val = env->mie & env->mideleg;
      }
-     return 0;
- }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
-+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
- {
--    target_ulong newval;
-+    /* Shift the S bits to their VS bit location in mie */
-+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
-+    return write_mie(env, CSR_MIE, newval);
-+}
-+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
-+{
-     if (riscv_cpu_virt_enabled(env)) {
--        /* Shift the guests S bits to VS */
--        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
--                 ((val << 1) & VS_MODE_INTERRUPTS);
-+        write_vsie(env, CSR_VSIE, val);
-     } else {
--        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
-+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
-+                              (val & S_MODE_INTERRUPTS);
-+        write_mie(env, CSR_MIE, newval);
-     }
--    return write_mie(env, CSR_MIE, newval);
-+    return 0;
- }
- static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
-@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
-     return 0;
- }
-+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-+                    target_ulong new_value, target_ulong write_mask)
-+{
-+    /* Shift the S bits to their VS bit location in mip */
-+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
-+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
-+    *ret_value &= VS_MODE_INTERRUPTS;
-+    /* Shift the VS bits to their S bit location in vsip */
-+    *ret_value >>= 1;
-+    return ret;
-+}
-+
- static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
- {
-     int ret;
-     if (riscv_cpu_virt_enabled(env)) {
--        /* Shift the new values to line up with the VS bits */
--        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
--                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
--        ret &= vsip_writable_mask;
--        ret >>= 1;
-+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
-     } else {
-         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
-                       write_mask & env->mideleg & sip_writable_mask);
-@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
-     return 0;
- }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
--                    target_ulong new_value, target_ulong write_mask)
--{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & env->mideleg & vsip_writable_mask);
--    return ret;
--}
--
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
--{
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
--    return 0;
--}
--
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
--{
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
--    return write_mie(env, CSR_MIE, newval);
--}
--
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
- {
-     *val = env->vstvec;
 --
-.30.1
+.35.3

-New patch
+[PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store
+From: eopXD <eop.chen@sifive.com>
+Vector whole register load instructions have EEW encoded in the opcode,
+so we shouldn't take SEW here. Vector whole register store instructions
+are always EEW=8.
+Signed-off-by: eop Chen <eop.chen@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++------------
+file changed, 31 insertions(+), 27 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
+ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
+ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
+-                             gen_helper_ldst_whole *fn, DisasContext *s,
+-                             bool is_store)
++                             uint32_t width, gen_helper_ldst_whole *fn,
++                             DisasContext *s, bool is_store)
+ {
+-    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
++    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
+     TCGLabel *over = gen_new_label();
+     tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
+@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
+  * load and store whole register instructions ignore vtype and vl setting.
+  * Thus, we don't need to check vill bit. (Section 7.9)
+  */
+-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE)                      \
++#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE)               \
+ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)                 \
+ {                                                                         \
+     if (require_rvv(s) &&                                                 \
+         QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                                 \
+-        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
+-                                s, IS_STORE);                             \
++        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH,             \
++                                gen_helper_##NAME, s, IS_STORE);          \
+     }                                                                     \
+     return false;                                                         \
+ }
+-GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
+-GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
+-GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
+-GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
+-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
+-
+-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
+-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
+-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
+-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
++GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, 1, false)
++GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
++GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
++GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
++GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, 1, false)
++GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
++GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
++GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
++GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, 1, false)
++GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
++GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
++GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
++GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, 1, false)
++GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
++GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
++GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
++
++/*
++ * The vector whole register store instructions are encoded similar to
++ * unmasked unit-stride store of elements with EEW=8.
++ */
++GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
++GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
++GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
++GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
+ /*
+  *** Vector Integer Arithmetic Instructions
+--
+.35.3

-[PULL 04/16] target/riscv: add log of PMP permission checking
+[PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp
-From: Jim Shu <cwshu@andestech.com>
+From: Atish Patra <atishp@rivosinc.com>
-Like MMU translation, add qemu log of PMP permission checking for
+timecmp update function should be invoked with hartid for which
-debugging.
+timecmp is being updated. The following patch passes the incorrect
 hartid to the update function.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
 Signed-off-by: Atish Patra <atishp@rivosinc.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Anup Patel <anup@brainfault.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
+Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++++++++
+ hw/intc/riscv_aclint.c | 3 ++-
-file changed, 12 insertions(+)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/hw/intc/riscv_aclint.c
-+++ b/target/riscv/cpu_helper.c
++++ b/hw/intc/riscv_aclint.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
-             if (ret == TRANSLATE_SUCCESS) {
+                 continue;
                  ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                 size, access_type, mode);
 +
 +                qemu_log_mask(CPU_LOG_MMU,
 +                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
 +                              " %d tlb_size " TARGET_FMT_lu "\n",
 +                              __func__, pa, ret, prot_pmp, tlb_size);
 +
                  prot &= prot_pmp;
              }
+             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+-                                              i, env->timecmp);
-         if (ret == TRANSLATE_SUCCESS) {
++                                              mtimer->hartid_base + i,
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
++                                              env->timecmp);
                                             size, access_type, mode);
 +
 +            qemu_log_mask(CPU_LOG_MMU,
 +                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
 +                          " %d tlb_size " TARGET_FMT_lu "\n",
 +                          __func__, pa, ret, prot_pmp, tlb_size);
 +
              prot &= prot_pmp;
          }
+         return;
      }
 --
-.30.1
+.35.3

-New patch
+[PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
+Because extension category ordering of "H" is going to be after "V",
+their ordering is going to be valid (on canonical order).
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+         ISA_EDATA_ENTRY(zfh, ext_zfh),
+         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+         ISA_EDATA_ENTRY(zdinx, ext_zdinx),
+         ISA_EDATA_ENTRY(zba, ext_zba),
+         ISA_EDATA_ENTRY(zbb, ext_zbb),
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+         ISA_EDATA_ENTRY(zkt, ext_zkt),
+         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
+         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
++        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
++        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+         ISA_EDATA_ENTRY(svinval, ext_svinval),
+         ISA_EDATA_ENTRY(svnapot, ext_svnapot),
+         ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+--
+.35.3

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 05/23] target/riscv: Add short-isa-string option
-From: Jim Shu <cwshu@andestech.com>
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+Because some operating systems don't correctly parse long ISA extension
-Fix it by propagating PMP permission to TLB page permission.
+string, this commit adds short-isa-string boolean option to disable
 generating long ISA extension strings on Device Tree.
-PMP permission checking also use MMU-style API to change TLB permission
+For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
-and size.
+earlier) with FPU support caused a kernel panic.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Operating Systems which short-isa-string might be helpful:
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+.  Linux (5.17 or earlier)
 .  FreeBSD (at least 14.0-CURRENT)
 .  OpenBSD (at least current development version)
 Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/cpu.h | 2 ++
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+ target/riscv/cpu.c | 6 +++++-
- target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
+files changed, 7 insertions(+), 1 deletion(-)
 files changed, 125 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/pmp.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     target_ulong val);
+     bool aia;
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+     bool debug;
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+     uint64_t resetvec;
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
++
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
++    bool short_isa_string;
-+    target_ulong mode);
+ };
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-                          target_ulong *tlb_size);
+ typedef struct RISCVCPUConfig RISCVCPUConfig;
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  void pmp_update_rule_nums(CPURISCVState *env);
  uint32_t pmp_get_num_rules(CPURISCVState *env);
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
  #endif
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-     env->load_res = -1;
+     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
- }
+     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 +/*
 + * get_physical_address_pmp - check PMP permission for this physical address
 + *
 + * Match the PMP region and check permission for this physical address and it's
 + * TLB page. Returns 0 if the permission checking was successful
 + *
 + * @env: CPURISCVState
 + * @prot: The returned protection attributes
 + * @tlb_size: TLB page size containing addr. It could be modified after PMP
 + *            permission checking. NULL if not set TLB page for addr.
 + * @addr: The physical address to be checked permission
 + * @access_type: The type of MMU access
 + * @mode: Indicates current privilege level.
 + */
 +static int get_physical_address_pmp(CPURISCVState *env, int *prot,
 +                                    target_ulong *tlb_size, hwaddr addr,
 +                                    int size, MMUAccessType access_type,
 +                                    int mode)
 +{
 +    pmp_priv_t pmp_priv;
 +    target_ulong tlb_size_pmp = 0;
 +
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
++    DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
-+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+     DEFINE_PROP_END_OF_LIST(),
-+        return TRANSLATE_SUCCESS;
+ };
-+    }
-+
+@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
 +    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 +                            mode)) {
 +        *prot = 0;
 +        return TRANSLATE_PMP_FAIL;
 +    }
 +
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
 +    }
 +
 +    return TRANSLATE_SUCCESS;
 +}
 +
  /* get_physical_address - get the physical address for this virtual address
   *
   * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
              pte_addr = base + idx * ptesize;
          }
 -        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 -            1 << MMU_DATA_LOAD, PRV_S)) {
 +        int pmp_prot;
 +        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
 +                                               sizeof(target_ulong),
 +                                               MMU_DATA_LOAD, PRV_S);
 +        if (pmp_ret != TRANSLATE_SUCCESS) {
              return TRANSLATE_PMP_FAIL;
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
  #ifndef CONFIG_USER_ONLY
      vaddr im_address;
      hwaddr pa = 0;
 -    int prot, prot2;
 +    int prot, prot2, prot_pmp;
      bool pmp_violation = false;
      bool first_stage_error = true;
      bool two_stage_lookup = false;
      int ret = TRANSLATE_FAIL;
      int mode = mmu_idx;
 -    target_ulong tlb_size = 0;
 +    /* default TLB page size */
 +    target_ulong tlb_size = TARGET_PAGE_SIZE;
      env->guest_phys_fault_addr = 0;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
              prot &= prot2;
 -            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -                (ret == TRANSLATE_SUCCESS) &&
 -                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -                ret = TRANSLATE_PMP_FAIL;
 +            if (ret == TRANSLATE_SUCCESS) {
 +                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                               size, access_type, mode);
 +                prot &= prot_pmp;
              }
              if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        "%s address=%" VADDR_PRIx " ret %d physical "
                        TARGET_FMT_plx " prot %d\n",
                        __func__, address, ret, pa, prot);
 -    }
 -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -        (ret == TRANSLATE_SUCCESS) &&
 -        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -        ret = TRANSLATE_PMP_FAIL;
 +        if (ret == TRANSLATE_SUCCESS) {
 +            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                           size, access_type, mode);
 +            prot &= prot_pmp;
 +        }
      }
 +
      if (ret == TRANSLATE_PMP_FAIL) {
          pmp_violation = true;
      }
      if (ret == TRANSLATE_SUCCESS) {
 -        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
 -            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 -                         prot, mmu_idx, tlb_size);
 -        } else {
 -            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 -                         prot, mmu_idx, TARGET_PAGE_SIZE);
 -        }
 +        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 +                     prot, mmu_idx, tlb_size);
          return true;
      } else if (probe) {
          return false;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
      return result;
  }
 +/*
 + * Check if the address has required RWX privs when no PMP entry is matched.
 + */
 +static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
 +{
 +    bool ret;
 +
 +    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
 +        /*
 +         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
 +         * or no PMP entry matches an M-Mode access, the access succeeds.
 +         */
 +        ret = true;
 +        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +    } else {
 +        /*
 +         * Other modes are not allowed to succeed if they don't * match a rule,
 +         * but there are rules. We've checked for no rule earlier in this
 +         * function.
 +         */
 +        ret = false;
 +        *allowed_privs = 0;
 +    }
 +
 +    return ret;
 +}
 +
  /*
   * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
   * Check if the address has required RWX privs to complete desired operation
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
      int i = 0;
      int ret = -1;
      int pmp_size = 0;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
+     *p = '\0';
-     /* No rule matched */
+-    riscv_isa_string_ext(cpu, &isa_str, maxlen);
-     if (ret == -1) {
++    if (!cpu->cfg.short_isa_string) {
--        if (mode == PRV_M) {
++        riscv_isa_string_ext(cpu, &isa_str, maxlen);
--            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
++    }
--                      * M-Mode access, the access succeeds */
+     return isa_str;
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
--
- /*
-  * Handle a write to a pmpcfg CSP
-  */
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-     return false;
- }
-+
-+/*
-+ * Convert PMP privilege to TLB page privilege.
-+ */
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
-+{
-+    int prot = 0;
-+
-+    if (pmp_priv & PMP_READ) {
-+        prot |= PAGE_READ;
-+    }
-+    if (pmp_priv & PMP_WRITE) {
-+        prot |= PAGE_WRITE;
-+    }
-+    if (pmp_priv & PMP_EXEC) {
-+        prot |= PAGE_EXEC;
-+    }
-+
-+    return prot;
-+}
 --
-.30.1
+.35.3

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike)
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
-Provides fw_cfg for the virt machine on riscv.  This enables
+If specified CPU configuration is not valid, not just it prints error
-using e.g.  ramfb later.
+message, it aborts and generates core dumps (depends on the operating
 system).  This kind of error handling should be used only when a serious
 runtime error occurs.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+This commit makes error handling on CPU configuration more generous on
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+virt/spike machines.  It now just prints error message and quits (without
 coredumps and aborts).
 Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ hw/riscv/spike.c | 2 +-
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+ hw/riscv/virt.c  | 2 +-
- hw/riscv/Kconfig        |  1 +
+files changed, 2 insertions(+), 2 deletions(-)
 files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/hw/riscv/spike.c
-+++ b/include/hw/riscv/virt.h
++++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+                                 base_hartid, &error_abort);
-     DeviceState *plic[VIRT_SOCKETS_MAX];
+         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
-     PFlashCFI01 *flash[2];
+                                 hart_count, &error_abort);
-+    FWCfgState *fw_cfg;
+-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
++        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
-     int fdt_size;
- };
+         /* Core Local Interruptor (timer and IPI) for each socket */
-@@ -XXX,XX +XXX,XX @@ enum {
+         riscv_aclint_swi_create(
      VIRT_PLIC,
      VIRT_UART0,
      VIRT_VIRTIO,
 +    VIRT_FW_CFG,
      VIRT_FLASH,
      VIRT_DRAM,
      VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
-+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
-     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
-     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
-     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
-@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-     return dev;
- }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
-+{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
-+    FWCfgState *fw_cfg;
-+    char *nodename;
-+
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
-+                                  &address_space_memory);
-+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-+
-+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-+    qemu_fdt_add_subnode(mc->fdt, nodename);
-+    qemu_fdt_setprop_string(mc->fdt, nodename,
-+                            "compatible", "qemu,fw-cfg-mmio");
-+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
-+                                 2, base, 2, size);
-+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
-+    g_free(nodename);
-+    return fw_cfg;
-+}
-+
- static void virt_machine_init(MachineState *machine)
- {
-     const MemMapEntry *memmap = virt_memmap;
 @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-         start_addr = virt_memmap[VIRT_FLASH].base;
+                                 base_hartid, &error_abort);
-     }
+         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                 hart_count, &error_abort);
-+    /*
+-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
++        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-+     */
+         if (!kvm_enabled()) {
-+    s->fw_cfg = create_fw_cfg(machine);
+             if (s->have_aclint) {
 +    rom_set_fw(s->fw_cfg);
 +
      /* Compute the fdt load address in dram */
      fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                     machine->ram_size, machine->fdt);
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select SIFIVE_PLIC
      select SIFIVE_TEST
      select VIRTIO_MMIO
 +    select FW_CFG_DMA
  config SIFIVE_E
      bool
 --
-.30.1
+.35.3

-New patch
+[PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+If specified CPU configuration is not valid, not just it prints error
+message, it aborts and generates core dumps (depends on the operating
+system).  This kind of error handling should be used only when a serious
+runtime error occurs.
+This commit makes error handling on CPU configuration more generous on
+sifive_e/u and opentitan machines.  It now just prints error message and
+quits (without coredumps and aborts).
+This is separate from spike/virt because it involves different type
+(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/opentitan.c | 2 +-
+ hw/riscv/sifive_e.c  | 2 +-
+ hw/riscv/sifive_u.c  | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+                             &error_abort);
+     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
+     /* Boot ROM */
+     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
+diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_e.c
++++ b/hw/riscv/sifive_e.c
+@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
+     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
+                             &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
+     /* Mask ROM */
+     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_u.c
++++ b/hw/riscv/sifive_u.c
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
+     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
++    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
++    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
+     /*
+      * The cluster must be realized after the RISC-V hart array container,
+      * as the container's CPU object is only created on realize, and the
+--
+.35.3

-New patch
+[PULL 08/23] target/riscv: Fix coding style on "G" expansion
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+Because ext_? members are boolean variables, operator `&&' should be
+used instead of `&'.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
+Message-Id: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             return;
+         }
+-        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+-                                cpu->cfg.ext_a & cpu->cfg.ext_f &
++        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
++                                cpu->cfg.ext_a && cpu->cfg.ext_f &&
+                                 cpu->cfg.ext_d)) {
+             warn_report("Setting G will also set IMAFD");
+             cpu->cfg.ext_i = true;
+--
+.35.3

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL 09/23] target/riscv: Disable "G" by default
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
-The current condition for the use of background registers only
+Because "G" virtual extension expands to "IMAFD", we cannot separately
-considers the hypervisor load and store instructions,
+disable extensions like "F" or "D" without disabling "G".  Because all
-but not accesses from M mode via MSTATUS_MPRV+MPV.
+"IMAFD" are enabled by default, it's harmless to disable "G" by default.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Message-Id: <cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-      * was called. Background registers will be used if the guest has
+     /* Defaults for standard extensions */
-      * forced a two stage translation to be on (in HS or M mode).
+     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
-      */
+     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+-    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
++    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
-         use_background = true;
+     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
-     }
+     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
+     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 --
-.30.1
+.35.3

-New patch
+[PULL 10/23] target/riscv: Change "G" expansion
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
+Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
+be (virtually) enabled as well, it should be safe to change its expansion.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 7 +++++--
+file changed, 5 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+         if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+                                 cpu->cfg.ext_a && cpu->cfg.ext_f &&
+-                                cpu->cfg.ext_d)) {
+-            warn_report("Setting G will also set IMAFD");
++                                cpu->cfg.ext_d &&
++                                cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
++            warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+             cpu->cfg.ext_i = true;
+             cpu->cfg.ext_m = true;
+             cpu->cfg.ext_a = true;
+             cpu->cfg.ext_f = true;
+             cpu->cfg.ext_d = true;
++            cpu->cfg.ext_icsr = true;
++            cpu->cfg.ext_ifencei = true;
+         }
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+--
+.35.3

-New patch
+[PULL 11/23] target/riscv: FP extension requirements
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
+QEMU allowed inconsistent configurations that made floating point
+arithmetic effectively unusable.
+This commit adds certain checks for consistent FP arithmetic:
+-   F requires Zicsr
+-   Zfinx requires Zicsr
+-   Zfh/Zfhmin require F
+-   D requires F
+-   V requires D
+Because F/D/Zicsr are enabled by default (and an error will not occur unless
+we manually disable one or more of prerequisites), this commit just enforces
+the user to give consistent combinations.
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 25 +++++++++++++++++++++++++
+file changed, 25 insertions(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_ifencei = true;
+         }
++        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
++            error_setg(errp, "F extension requires Zicsr");
++            return;
++        }
++
++        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
++            error_setg(errp, "Zfh/Zfhmin extensions require F extension");
++            return;
++        }
++
++        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
++            error_setg(errp, "D extension requires F extension");
++            return;
++        }
++
++        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
++            error_setg(errp, "V extension requires D extension");
++            return;
++        }
++
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+             cpu->cfg.ext_zhinxmin) {
+             cpu->cfg.ext_zfinx = true;
+         }
++        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
++            error_setg(errp, "Zfinx extension requires Zicsr");
++            return;
++        }
++
+         if (cpu->cfg.ext_zk) {
+             cpu->cfg.ext_zkn = true;
+             cpu->cfg.ext_zkr = true;
+--
+.35.3

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 12/23] target/riscv: Move/refactor ISA extension checks
-From: Alexander Wagner <alexander.wagner@ulal.de>
+From: Tsukasa OI <research_trasio@irq.a4lg.com>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+We should separate "check" and "configure" steps as possible.
-the newest received byte. The rx_level variable is added to allow the use of
+This commit separates both steps except vector/Zfinx-related checks.
 the existing OpenTitan driver libraries.
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
+Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
+Message-Id: <c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ target/riscv/cpu.c | 31 ++++++++++++++++---------------
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+file changed, 16 insertions(+), 15 deletions(-)
 files changed, 22 insertions(+), 5 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
+--- a/target/riscv/cpu.c
-+++ b/include/hw/char/ibex_uart.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
+             return;
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
+         }
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
++        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
++            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
- REG32(OVRD, 0x24)
++            return;
- REG32(VAL, 0x28)
++        }
  REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
      uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
      uint32_t tx_level;
 +    uint32_t rx_level;
 +
-     QEMUTimer *fifo_trigger_handle;
++        /* Set the ISA extensions, checks should have happened above */
-     uint64_t char_tx_time;
+         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+             cpu->cfg.ext_zhinxmin) {
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
+             cpu->cfg.ext_zfinx = true;
-index XXXXXXX..XXXXXXX 100644
+         }
---- a/hw/char/ibex_uart.c
-+++ b/hw/char/ibex_uart.c
+-        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
+-            error_setg(errp, "Zfinx extension requires Zicsr");
- {
+-            return;
-     IbexUartState *s = opaque;
++        if (cpu->cfg.ext_zfinx) {
++            if (!cpu->cfg.ext_icsr) {
--    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
++                error_setg(errp, "Zfinx extension requires Zicsr");
-+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
++                return;
-+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
++            }
-         return 1;
++            if (cpu->cfg.ext_f) {
-     }
++                error_setg(errp,
++                    "Zfinx cannot be supported together with F extension");
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
++                return;
      s->uart_status &= ~R_STATUS_RXIDLE_MASK;
      s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
 +    /* The RXFULL is set after receiving a single byte
 +     * as the FIFO buffers are not yet implemented.
 +     */
 +    s->uart_status |= R_STATUS_RXFULL_MASK;
 +    s->rx_level += 1;
      if (size > rx_fifo_level) {
          s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
      s->uart_timeout_ctrl = 0x00000000;
      s->tx_level = 0;
 +    s->rx_level = 0;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
-         break;
-     case R_WDATA:
+         if (cpu->cfg.ext_zk) {
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
-     case R_FIFO_STATUS:
+             cpu->cfg.ext_zksh = true;
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
+-        /* Set the ISA extensions, checks should have happened above */
+         if (cpu->cfg.ext_i) {
+             ext |= RVI;
+         }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             }
+             set_vext_version(env, vext_version);
+         }
+-        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+-            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
+-            return;
+-        }
+         if (cpu->cfg.ext_j) {
+             ext |= RVJ;
+         }
+-        if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
+-                                   cpu->cfg.ext_zfhmin)) {
+-            error_setg(errp,
+-                    "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
+-                    " 'Zfhmin'");
+-            return;
+-        }
+         set_misa(env, env->misa_mxl, ext);
+     }
 --
-.30.1
+.35.3

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Bernhard Beschow <shentey@gmail.com>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+The QOM API already provides getters for uint64 and uint32 values, so reuse
-further compressed instruction decoding. However, prior to this change,
+them.
 we did not raise an illegal instruction exception, if decode_RV32_64C()
 fails to decode the instruction. This means that we skipped illegal
 compressed instructions instead of raising an illegal instruction
 exception.
-Instead of patching decode_RV32_64C(), we can just remove it,
+Signed-off-by: Bernhard Beschow <shentey@gmail.com>
 as it is dead code since f330433b363 anyway.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220301225220.239065-2-shentey@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ hw/vfio/pci-quirks.c | 34 +++++++++-------------------------
-file changed, 1 insertion(+), 178 deletions(-)
+file changed, 9 insertions(+), 25 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/hw/vfio/pci-quirks.c
-+++ b/target/riscv/translate.c
++++ b/hw/vfio/pci-quirks.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
-     CPUState *cs;
+     return 0;
  } DisasContext;
 -#ifdef TARGET_RISCV64
 -/* convert riscv funct3 to qemu memop for load/store */
 -static const int tcg_memop_lookup[8] = {
 -    [0 ... 7] = -1,
 -    [0] = MO_SB,
 -    [1] = MO_TESW,
 -    [2] = MO_TESL,
 -    [3] = MO_TEQ,
 -    [4] = MO_UB,
 -    [5] = MO_TEUW,
 -    [6] = MO_TEUL,
 -};
 -#endif
 -
  #ifdef TARGET_RISCV64
  #define CASE_OP_32_64(X) case X: case glue(X, W)
  #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
--#ifdef TARGET_RISCV64
+-static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
--static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+-                                     const char *name,
--        target_long imm)
+-                                     void *opaque, Error **errp)
 -{
--    TCGv t0 = tcg_temp_new();
+-    uint64_t tgt = (uintptr_t) opaque;
--    TCGv t1 = tcg_temp_new();
+-    visit_type_uint64(v, name, &tgt, errp);
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
--static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+-static void vfio_pci_nvlink2_get_link_speed(Object *obj, Visitor *v,
--        target_long imm)
+-                                                 const char *name,
 -                                                 void *opaque, Error **errp)
 -{
--    TCGv t0 = tcg_temp_new();
+-    uint32_t link_speed = (uint32_t)(uintptr_t) opaque;
--    TCGv dat = tcg_temp_new();
+-    visit_type_uint32(v, name, &link_speed, errp);
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
--static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
+ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
-     TCGv_i32 t0;
+     int ret;
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
+@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
-     tcg_temp_free_i32(t0);
+                                nv2reg->size, p);
- }
+     QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
--static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
+-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
--{
+-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
--    uint8_t funct3 = extract16(opcode, 13, 3);
+-                        (void *) (uintptr_t) cap->tgt);
--    uint8_t rd_rs2 = GET_C_RS2S(opcode);
++    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
--    uint8_t rs1s = GET_C_RS1S(opcode);
++                                   (uint64_t *) &cap->tgt,
--
++                                   OBJ_PROP_FLAG_READ);
--    switch (funct3) {
+     trace_vfio_pci_nvidia_gpu_setup_quirk(vdev->vbasedev.name, cap->tgt,
--    case 3:
+                                           nv2reg->size);
--#if defined(TARGET_RISCV64)
+ free_exit:
--        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
+@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp)
--        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+         QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
--                 GET_C_LD_IMM(opcode));
+     }
--#else
--        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
+-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
--        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
+-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
--                    GET_C_LW_IMM(opcode));
+-                        (void *) (uintptr_t) captgt->tgt);
--#endif
++    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
--        break;
++                                   (uint64_t *) &captgt->tgt,
--    case 7:
++                                   OBJ_PROP_FLAG_READ);
--#if defined(TARGET_RISCV64)
+     trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev->vbasedev.name, captgt->tgt,
--        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
+                                               atsdreg->size);
--        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
--                  GET_C_LD_IMM(opcode));
+-    object_property_add(OBJECT(vdev), "nvlink2-link-speed", "uint32",
--#else
+-                        vfio_pci_nvlink2_get_link_speed, NULL, NULL,
--        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
+-                        (void *) (uintptr_t) capspeed->link_speed);
--        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
++    object_property_add_uint32_ptr(OBJECT(vdev), "nvlink2-link-speed",
--                     GET_C_LW_IMM(opcode));
++                                   &capspeed->link_speed,
--#endif
++                                   OBJ_PROP_FLAG_READ);
--        break;
+     trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev->vbasedev.name,
--    }
+                                               capspeed->link_speed);
--}
+ free_exit:
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.35.3

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors
-From: Jim Shu <cwshu@andestech.com>
+From: Bernhard Beschow <shentey@gmail.com>
-If PMP permission of any address has been changed by updating PMP entry,
+The QOM API already provides accessors for uint32 values, so reuse them.
 flush all TLB pages to prevent from getting old permission.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: Bernhard Beschow <shentey@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
+Message-Id: <20220301225220.239065-3-shentey@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ hw/riscv/sifive_u.c | 24 ++++--------------------
-file changed, 4 insertions(+)
+file changed, 4 insertions(+), 20 deletions(-)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/hw/riscv/sifive_u.c
-+++ b/target/riscv/pmp.c
++++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
- #include "qapi/error.h"
+     s->start_in_flash = value;
  #include "cpu.h"
  #include "trace.h"
 +#include "exec/exec-all.h"
  static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
      uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
          cfg_val = (val >> 8 * i)  & 0xff;
          pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
      }
 +
 +    /* If PMP permission of any addr has been changed, flush TLB pages. */
 +    tlb_flush(env_cpu(env));
  }
+-static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
+-                                             const char *name, void *opaque,
+-                                             Error **errp)
+-{
+-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+-}
+-
+-static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
+-                                             const char *name, void *opaque,
+-                                             Error **errp)
+-{
+-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+-}
+-
+ static void sifive_u_machine_instance_init(Object *obj)
+ {
+     SiFiveUState *s = RISCV_U_MACHINE(obj);
+     s->start_in_flash = false;
+     s->msel = 0;
+-    object_property_add(obj, "msel", "uint32",
+-                        sifive_u_machine_get_uint32_prop,
+-                        sifive_u_machine_set_uint32_prop, NULL, &s->msel);
++    object_property_add_uint32_ptr(obj, "msel", &s->msel,
++                                   OBJ_PROP_FLAG_READWRITE);
+     object_property_set_description(obj, "msel",
+                                     "Mode Select (MSEL[3:0]) pin state");
+     s->serial = OTP_SERIAL;
+-    object_property_add(obj, "serial", "uint32",
+-                        sifive_u_machine_get_uint32_prop,
+-                        sifive_u_machine_set_uint32_prop, NULL, &s->serial);
++    object_property_add_uint32_ptr(obj, "serial", &s->serial,
++                                   OBJ_PROP_FLAG_READWRITE);
+     object_property_set_description(obj, "serial", "Board serial number");
+ }
 --
-.30.1
+.35.3

-New patch
+[PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
+From: Weiwei Li <liweiwei@iscas.ac.cn>
+ - setting ext_g will implicitly set ext_i
+Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 24 ++++++++++++------------
+file changed, 12 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+         uint32_t ext = 0;
+         /* Do some ISA extension error checking */
+-        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+-            error_setg(errp,
+-                       "I and E extensions are incompatible");
+-            return;
+-        }
+-
+-        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+-            error_setg(errp,
+-                       "Either I or E extension must be set");
+-            return;
+-        }
+-
+         if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+                                 cpu->cfg.ext_a && cpu->cfg.ext_f &&
+                                 cpu->cfg.ext_d &&
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             cpu->cfg.ext_ifencei = true;
+         }
++        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
++            error_setg(errp,
++                       "I and E extensions are incompatible");
++            return;
++        }
++
++        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
++            error_setg(errp,
++                       "Either I or E extension must be set");
++            return;
++        }
++
+         if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+             error_setg(errp, "F extension requires Zicsr");
+             return;
+--
+.35.3

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL 16/23] target/riscv: Fix typo of mimpid cpu option
 From: Frank Chang <frank.chang@sifive.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+"mimpid" cpu option was mistyped to "mipid".
 is not enabled.
-If -1 is returned, exception will be raised and cs->exception_index will
+Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values")
 be set to the negative return value. The exception will then be treated
 as an instruction access fault instead of illegal instruction fault.
 Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/cpu.h | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
+ target/riscv/cpu.c | 4 ++--
  target/riscv/csr.c | 8 ++++----
 files changed, 7 insertions(+), 7 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     uint32_t mvendorid;
+     uint64_t marchid;
+-    uint64_t mipid;
++    uint64_t mimpid;
+     /* Vendor-specific custom extensions */
+     bool ext_XVentanaCondOps;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@
+ #define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
+                              (QEMU_VERSION_MINOR << 8)  | \
+                              (QEMU_VERSION_MICRO))
+-#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
++#define RISCV_CPU_MIMPID    RISCV_CPU_MARCHID
+ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+-    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
++    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
+     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
-     if (env->misa & RVV) {
+     return RISCV_EXCP_NONE;
          return 0;
      }
 -    return -1;
 +    return -RISCV_EXCP_ILLEGAL_INST;
  }
- static int ctr(CPURISCVState *env, int csrno)
+-static RISCVException read_mipid(CPURISCVState *env, int csrno,
 -                                 target_ulong *val)
 +static RISCVException read_mimpid(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      CPUState *cs = env_cpu(env);
      RISCVCPU *cpu = RISCV_CPU(cs);
 -    *val = cpu->cfg.mipid;
 +    *val = cpu->cfg.mimpid;
      return RISCV_EXCP_NONE;
  }
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      /* Machine Information Registers */
      [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
      [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
 -    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
 +    [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
      [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
 --
-.30.1
+.35.3

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL 17/23] target/riscv: Fix csr number based privilege checking
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Anup Patel <apatel@ventanamicro.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
 the riscv_csrrw_check() function should generate virtual instruction
 trap instead illegal instruction trap.
 Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
 Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ target/riscv/csr.c | 8 ++++++--
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 6 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+     int read_only = get_field(csrno, 0xC00) == 3;
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+     int csr_min_priv = csr_ops[csrno].min_priv_ver;
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+ #if !defined(CONFIG_USER_ONLY)
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+-    int effective_priv = env->priv;
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
++    int csr_priv, effective_priv = env->priv;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
+     if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
+         /*
- static const char valid_vm_1_10_32[16] = {
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
-@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+         effective_priv++;
-                    target_ulong new_value, target_ulong write_mask)
+     }
- {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+-    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
--                      write_mask & hip_writable_mask);
++    csr_priv = get_field(csrno, 0x300);
-+                      write_mask & hvip_writable_mask);
++    if (!env->debugger && (effective_priv < csr_priv)) {
++        if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
--    *ret_value &= hip_writable_mask;
++            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+    *ret_value &= hvip_writable_mask;
++        }
+         return RISCV_EXCP_ILLEGAL_INST;
-     return ret;
+     }
- }
+ #endif
 --
-.30.1
+.35.3

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+[PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Anup Patel <apatel@ventanamicro.com>
-According to the specification the "field SPVP of hstatus controls the
+Currently, QEMU does not set hstatus.GVA bit for traps taken from
-privilege level of the access" for the hypervisor virtual-machine load
+HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
-and store instructions HLV, HLVX and HSV.
+on QEMU. This was working previously.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+This patch updates riscv_cpu_do_interrupt() to fix the above issue.
 Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
 Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
+ target/riscv/cpu_helper.c | 3 +--
-file changed, 14 insertions(+), 11 deletions(-)
+file changed, 1 insertion(+), 2 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         use_background = true;
+         case RISCV_EXCP_INST_PAGE_FAULT:
-     }
+         case RISCV_EXCP_LOAD_PAGE_FAULT:
+         case RISCV_EXCP_STORE_PAGE_FAULT:
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+-            write_gva = true;
-+    /* MPRV does not affect the virtual-machine load/store
++            write_gva = env->two_stage_lookup;
-+       instructions, HLV, HLVX, and HSV. */
+             tval = env->badaddr;
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+             break;
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+         case RISCV_EXCP_ILLEGAL_INST:
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
+                 /* Trap into HS mode */
-             mode = get_field(env->mstatus, MSTATUS_MPP);
+                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                  htval = env->guest_phys_fault_addr;
 -                write_gva = false;
              }
              env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
          }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
-                   __func__, address, access_type, mmu_idx);
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
--        if (get_field(env->mstatus, MSTATUS_MPRV)) {
--            mode = get_field(env->mstatus, MSTATUS_MPP);
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
-+               get_field(env->mstatus, MSTATUS_MPRV)) {
-+        mode = get_field(env->mstatus, MSTATUS_MPP);
-+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
-+            two_stage_lookup = true;
-         }
-     }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
--        access_type != MMU_INST_FETCH &&
--        get_field(env->mstatus, MSTATUS_MPRV) &&
--        get_field(env->mstatus, MSTATUS_MPV)) {
--        two_stage_lookup = true;
--    }
--
-     if (riscv_cpu_virt_enabled(env) ||
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-          access_type != MMU_INST_FETCH)) {
 --
-.30.1
+.35.3

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Anup Patel <apatel@ventanamicro.com>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Currently, the [m|s]tval CSRs are set with trapping instruction encoding
-short of its purpose, as all it checks is whether two-stage address
+only for illegal instruction traps taken at the time of instruction
-translation either via the hypervisor-load store instructions or the
+decoding.
 MPRV feature would be allowed.
-What we really need instead is whether two-stage address translation was
+In RISC-V world, a valid instructions might also trap as illegal or
-active when the exception was raised. However, in riscv_cpu_do_interrupt
+virtual instruction based to trapping bits in various CSRs (such as
-we do not have the information to reliably detect this. Therefore, when
+mstatus.TVM or hstatus.VTVM).
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+We improve setting of [m|s]tval CSRs for all types of illegal and
 virtual instruction traps.
 Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/cpu.h        |  8 +++++++-
- target/riscv/cpu.c        |  1 +
+ target/riscv/cpu.c        |  2 ++
- target/riscv/cpu_helper.c | 21 ++++++++-------------
+ target/riscv/cpu_helper.c |  1 +
-files changed, 13 insertions(+), 13 deletions(-)
+ target/riscv/translate.c  | 17 +++++++++++++----
 files changed, 23 insertions(+), 5 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@
-     target_ulong satp_hs;
-     uint64_t mstatus_hs;
+ #define TCG_GUEST_DEFAULT_MO 0
-+    /* Signals whether the current exception occurred with two-stage address
++/*
-+       translation active. */
++ * RISC-V-specific extra insn start words:
-+    bool two_stage_lookup;
++ * 1: Original instruction opcode
 + */
 +#define TARGET_INSN_START_EXTRA_WORDS 1
 +
-     target_ulong scounteren;
+ #define TYPE_RISCV_CPU "riscv-cpu"
-     target_ulong mcounteren;
  #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
      target_ulong frm;
      target_ulong badaddr;
 -    uint32_t bins;
 +    target_ulong bins;
      target_ulong guest_phys_fault_addr;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
+     } else {
+         env->pc = data[0];
+     }
++    env->bins = data[1];
+ }
+ static void riscv_cpu_reset(DeviceState *dev)
 @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
      env->mcause = 0;
+     env->miclaim = MIP_SGEIP;
      env->pc = env->resetvec;
-+    env->two_stage_lookup = false;
++    env->bins = 0;
- #endif
+     env->two_stage_lookup = false;
-     cs->exception_index = EXCP_NONE;
-     env->load_res = -1;
+     /* Initialized default priorities of local interrupts. */
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         g_assert_not_reached();
+             tval = env->badaddr;
-     }
+             break;
-     env->badaddr = address;
+         case RISCV_EXCP_ILLEGAL_INST:
-+    env->two_stage_lookup = two_stage;
++        case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
              tval = env->bins;
              break;
          default:
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* PointerMasking extension */
      bool pm_mask_enabled;
      bool pm_base_enabled;
 +    /* TCG of the current insn_start */
 +    TCGOp *insn_start;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
  static void gen_exception_illegal(DisasContext *ctx)
  {
 -    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
 -                   offsetof(CPURISCVState, bins));
 -
      generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ /* Include decoders for factored-out extensions */
-     }
+ #include "decode-XVentanaCondOps.c.inc"
-     env->badaddr = addr;
++static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
++{
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
++    assert(ctx->insn_start != NULL);
-     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
++    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
 +    ctx->insn_start = NULL;
 +}
 +
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
      /*
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
      /* Check for compressed insn */
      if (extract16(opcode, 0, 2) != 3) {
 +        decode_save_opc(ctx, opcode);
          if (!has_ext(ctx, RVC)) {
              gen_exception_illegal(ctx);
          } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          opcode32 = deposit32(opcode32, 16, 16,
                               translator_lduw(env, &ctx->base,
                                               ctx->base.pc_next + 2));
 +        decode_save_opc(ctx, opcode32);
          ctx->opcode = opcode32;
          ctx->pc_succ_insn = ctx->base.pc_next + 4;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
  {
      DisasContext *ctx = container_of(dcbase, DisasContext, base);
 -    tcg_gen_insn_start(ctx->base.pc_next);
 +    tcg_gen_insn_start(ctx->base.pc_next, 0);
 +    ctx->insn_start = tcg_last_op();
  }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          g_assert_not_reached();
      }
      env->badaddr = addr;
 +    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
 +                            riscv_cpu_two_stage_lookup(mmu_idx);
      riscv_raise_exception(env, cs->exception_index, retaddr);
  }
  #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          /* handle the trap in S-mode */
          if (riscv_has_ext(env, RVH)) {
              target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 -            bool two_stage_lookup = false;
 -            if (env->priv == PRV_M ||
 -                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                    get_field(env->hstatus, HSTATUS_HU))) {
 -                    two_stage_lookup = true;
 -            }
 -
 -            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
 +            if (env->two_stage_lookup && write_tval) {
                  /*
                   * If we are writing a guest virtual address to stval, set
                   * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  riscv_cpu_set_force_hs_excep(env, 0);
              } else {
                  /* Trap into HS mode */
 -                if (!two_stage_lookup) {
 -                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 -                                             riscv_cpu_virt_enabled(env));
 -                }
 +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                  htval = env->guest_phys_fault_addr;
              }
          }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
       * RISC-V ISA Specification.
       */
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.35.3

-[PULL 10/16] hw/riscv: allow ramfb on virt
+[PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Anup Patel <apatel@ventanamicro.com>
-Allow ramfb on virt.  This lets `-device ramfb' work.
+When both APLIC and IMSIC are present in virt machine, the APLIC should
 be used as parent interrupt controller for dynamic platform devices.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+In case of  multiple sockets, we should prefer interrupt controller of
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+socket0 for dynamic platform devices.
 Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
 platform FDT entries")
 Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
+Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 3 +++
+ hw/riscv/virt.c | 25 ++++++++++++-------------
-file changed, 3 insertions(+)
+file changed, 12 insertions(+), 13 deletions(-)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
- #include "sysemu/sysemu.h"
+     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
- #include "hw/pci/pci.h"
+         plic_phandles[socket]);
- #include "hw/pci-host/gpex.h"
-+#include "hw/display/ramfb.h"
+-    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+-                                   memmap[VIRT_PLATFORM_BUS].base,
- static const MemMapEntry virt_memmap[] = {
+-                                   memmap[VIRT_PLATFORM_BUS].size,
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
+-                                   VIRT_PLATFORM_BUS_IRQ);
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
++    if (!socket) {
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
++        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
++                                       memmap[VIRT_PLATFORM_BUS].base,
-     mc->numa_mem_supported = true;
++                                       memmap[VIRT_PLATFORM_BUS].size,
-+
++                                       VIRT_PLATFORM_BUS_IRQ);
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
++    }
- }
+     g_free(plic_name);
- static const TypeInfo virt_machine_typeinfo = {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
      }
      qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
 -    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
 -                                   memmap[VIRT_PLATFORM_BUS].base,
 -                                   memmap[VIRT_PLATFORM_BUS].size,
 -                                   VIRT_PLATFORM_BUS_IRQ);
 -
      g_free(imsic_name);
      /* S-level IMSIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
      riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
      qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 -    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
 -                                   memmap[VIRT_PLATFORM_BUS].base,
 -                                   memmap[VIRT_PLATFORM_BUS].size,
 -                                   VIRT_PLATFORM_BUS_IRQ);
 +    if (!socket) {
 +        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
 +                                       memmap[VIRT_PLATFORM_BUS].base,
 +                                       memmap[VIRT_PLATFORM_BUS].size,
 +                                       VIRT_PLATFORM_BUS_IRQ);
 +    }
      g_free(aplic_name);
 --
-.30.1
+.35.3

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 21/23] target/riscv: add zicsr/zifencei to isa_string
-From: Bin Meng <bin.meng@windriver.com>
+From: "Hongren (Zenithal) Zheng" <i@zenithal.me>
-This adds the documentation to describe what is supported for the
+Zicsr/Zifencei is not in 'I' since ISA version 20190608,
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+thus to fully express the capability of the CPU,
 they should be exposed in isa_string.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
 Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Message-Id: <YoTqwpfrodveJ7CR@Sun>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ target/riscv/cpu.c | 2 ++
- docs/system/target-riscv.rst               |  1 +
+file changed, 2 insertions(+)
 files changed, 90 insertions(+)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
 +Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
 +=============================================================
 +
 +Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
 +SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
 +
 +For more details about Microchip PolarFire SoC, please see:
 +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
 +
 +The Icicle Kit board information can be found here:
 +https://www.microsemi.com/existing-parts/parts/152514
 +
 +Supported devices
 +-----------------
 +
 +The ``microchip-icicle-kit`` machine supports the following devices:
 +
 + * 1 E51 core
 + * 4 U54 cores
 + * Core Level Interruptor (CLINT)
 + * Platform-Level Interrupt Controller (PLIC)
 + * L2 Loosely Integrated Memory (L2-LIM)
 + * DDR memory controller
 + * 5 MMUARTs
 + * 1 DMA controller
 + * 2 GEM Ethernet controllers
 + * 1 SDHC storage controller
 +
 +Boot options
 +------------
 +
 +The ``microchip-icicle-kit`` machine can start using the standard -bios
 +functionality for loading its BIOS image, aka Hart Software Services (HSS_).
 +HSS loads the second stage bootloader U-Boot from an SD card. It does not
 +support direct kernel loading via the -kernel option. One has to load kernel
 +from U-Boot.
 +
 +The memory is set to 1537 MiB by default which is the minimum required high
 +memory size by HSS. A sanity check on ram size is performed in the machine
 +init routine to prompt user to increase the RAM size to > 1537 MiB when less
 +than 1537 MiB ram is detected.
 +
 +Boot the machine
 +----------------
 +
 +HSS 2020.12 release is tested at the time of writing. To build an HSS image
 +that can be booted by the ``microchip-icicle-kit`` machine, type the following
 +in the HSS source tree:
 +
 +.. code-block:: bash
 +
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ cp boards/mpfs-icicle-kit-es/def_config .config
 +  $ make BOARD=mpfs-icicle-kit-es
 +
 +Download the official SD card image released by Microchip and prepare it for
 +QEMU usage:
 +
 +.. code-block:: bash
 +
 +  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
 +
 +Then we can boot the machine by:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
 +      -bios path/to/hss.bin -sd path/to/sdcard.img \
 +      -nic user,model=cadence_gem \
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
 +      -serial chardev:serial1
 +
 +With above command line, current terminal session will be used for the first
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
 +  $ minicom -D unix\#serial1.sock
 +
 +HSS output is on the first serial port (stdio) and U-Boot outputs on the
 +second serial port. U-Boot will automatically load the Linux kernel from
 +the SD card image.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-riscv.rst
+--- a/target/riscv/cpu.c
-+++ b/docs/system/target-riscv.rst
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
- .. toctree::
+      *    extensions by an underscore.
-    :maxdepth: 1
+      */
+     struct isa_ext_data isa_edata_arr[] = {
-+   riscv/microchip-icicle-kit
++        ISA_EDATA_ENTRY(zicsr, ext_icsr),
-    riscv/sifive_u
++        ISA_EDATA_ENTRY(zifencei, ext_ifencei),
+         ISA_EDATA_ENTRY(zfh, ext_zfh),
- RISC-V CPU features
+         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
          ISA_EDATA_ENTRY(zfinx, ext_zfinx),
 --
-.30.1
+.35.3

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01
 From: Bin Meng <bin.meng@windriver.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
-been updated to use a register mapped at 0x4f000000 instead of a
-GPIO to control whether eMMC or SD card is to be used. With this
+[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h
 support the same HSS image can be used for both eMMC and SD card
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
 With this commit, HSS image built from 2020.12 release boots again.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ hw/core/uboot_image.h | 213 ++++++++++++++++++++++++++++--------------
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+file changed, 142 insertions(+), 71 deletions(-)
-files changed, 7 insertions(+)
+diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h
 diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/hw/core/uboot_image.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/hw/core/uboot_image.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@
-     MICROCHIP_PFSOC_ENVM_DATA,
++/* SPDX-License-Identifier: GPL-2.0+ */
-     MICROCHIP_PFSOC_QSPI_XIP,
+ /*
-     MICROCHIP_PFSOC_IOSCB,
++ * (C) Copyright 2008 Semihalf
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
++ *
-     MICROCHIP_PFSOC_DRAM_LO,
+  * (C) Copyright 2000-2005
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-     MICROCHIP_PFSOC_DRAM_HI,
+- *
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+- * See file CREDITS for list of people who contributed to this
-index XXXXXXX..XXXXXXX 100644
+- * project.
---- a/hw/riscv/microchip_pfsoc.c
+- *
-+++ b/hw/riscv/microchip_pfsoc.c
+- * This program is free software; you can redistribute it and/or
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
+- * modify it under the terms of the GNU General Public License as
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+- * published by the Free Software Foundation; either version 2 of
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+- * the License, or (at your option) any later version.
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+- *
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
+- * This program is distributed in the hope that it will be useful,
-     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     See the
-     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+- * GNU General Public License for more details.
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+- *
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+- * You should have received a copy of the GNU General Public License along
-                     memmap[MICROCHIP_PFSOC_IOSCB].base);
+- * with this program; if not, see <http://www.gnu.org/licenses/>.
+- *
-+    /* eMMC/SD mux */
+  ********************************************************************
-+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+  * NOTE: This header file defines an interface to U-Boot. Including
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+  * this (unmodified) header file in another file is considered normal
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+@@ -XXX,XX +XXX,XX @@
-+
-     /* QSPI Flash */
+ /*
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
+  * Operating System Codes
-                            "microchip.pfsoc.qspi_xip",
++ *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_OS_INVALID        0    /* Invalid OS    */
 -#define IH_OS_OPENBSD        1    /* OpenBSD    */
 -#define IH_OS_NETBSD        2    /* NetBSD    */
 -#define IH_OS_FREEBSD        3    /* FreeBSD    */
 -#define IH_OS_4_4BSD        4    /* 4.4BSD    */
 -#define IH_OS_LINUX        5    /* Linux    */
 -#define IH_OS_SVR4        6    /* SVR4        */
 -#define IH_OS_ESIX        7    /* Esix        */
 -#define IH_OS_SOLARIS        8    /* Solaris    */
 -#define IH_OS_IRIX        9    /* Irix        */
 -#define IH_OS_SCO        10    /* SCO        */
 -#define IH_OS_DELL        11    /* Dell        */
 -#define IH_OS_NCR        12    /* NCR        */
 -#define IH_OS_LYNXOS        13    /* LynxOS    */
 -#define IH_OS_VXWORKS        14    /* VxWorks    */
 -#define IH_OS_PSOS        15    /* pSOS        */
 -#define IH_OS_QNX        16    /* QNX        */
 -#define IH_OS_U_BOOT        17    /* Firmware    */
 -#define IH_OS_RTEMS        18    /* RTEMS    */
 -#define IH_OS_ARTOS        19    /* ARTOS    */
 -#define IH_OS_UNITY        20    /* Unity OS    */
 +enum {
 +    IH_OS_INVALID        = 0,    /* Invalid OS    */
 +    IH_OS_OPENBSD,            /* OpenBSD    */
 +    IH_OS_NETBSD,            /* NetBSD    */
 +    IH_OS_FREEBSD,            /* FreeBSD    */
 +    IH_OS_4_4BSD,            /* 4.4BSD    */
 +    IH_OS_LINUX,            /* Linux    */
 +    IH_OS_SVR4,            /* SVR4        */
 +    IH_OS_ESIX,            /* Esix        */
 +    IH_OS_SOLARIS,            /* Solaris    */
 +    IH_OS_IRIX,            /* Irix        */
 +    IH_OS_SCO,            /* SCO        */
 +    IH_OS_DELL,            /* Dell        */
 +    IH_OS_NCR,            /* NCR        */
 +    IH_OS_LYNXOS,            /* LynxOS    */
 +    IH_OS_VXWORKS,            /* VxWorks    */
 +    IH_OS_PSOS,            /* pSOS        */
 +    IH_OS_QNX,            /* QNX        */
 +    IH_OS_U_BOOT,            /* Firmware    */
 +    IH_OS_RTEMS,            /* RTEMS    */
 +    IH_OS_ARTOS,            /* ARTOS    */
 +    IH_OS_UNITY,            /* Unity OS    */
 +    IH_OS_INTEGRITY,        /* INTEGRITY    */
 +    IH_OS_OSE,            /* OSE        */
 +    IH_OS_PLAN9,            /* Plan 9    */
 +    IH_OS_OPENRTOS,        /* OpenRTOS    */
 +    IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
 +    IH_OS_TEE,            /* Trusted Execution Environment */
 +    IH_OS_OPENSBI,            /* RISC-V OpenSBI */
 +    IH_OS_EFI,            /* EFI Firmware (e.g. GRUB2) */
 +
 +    IH_OS_COUNT,
 +};
  /*
   * CPU Architecture Codes (supported by Linux)
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_CPU_INVALID        0    /* Invalid CPU    */
 -#define IH_CPU_ALPHA        1    /* Alpha    */
 -#define IH_CPU_ARM        2    /* ARM        */
 -#define IH_CPU_I386        3    /* Intel x86    */
 -#define IH_CPU_IA64        4    /* IA64        */
 -#define IH_CPU_MIPS        5    /* MIPS        */
 -#define IH_CPU_MIPS64        6    /* MIPS     64 Bit */
 -#define IH_CPU_PPC        7    /* PowerPC    */
 -#define IH_CPU_S390        8    /* IBM S390    */
 -#define IH_CPU_SH        9    /* SuperH    */
 -#define IH_CPU_SPARC        10    /* Sparc    */
 -#define IH_CPU_SPARC64        11    /* Sparc 64 Bit */
 -#define IH_CPU_M68K        12    /* M68K        */
 -#define IH_CPU_NIOS        13    /* Nios-32    */
 -#define IH_CPU_MICROBLAZE    14    /* MicroBlaze   */
 -#define IH_CPU_NIOS2        15    /* Nios-II    */
 -#define IH_CPU_BLACKFIN        16    /* Blackfin    */
 -#define IH_CPU_AVR32        17    /* AVR32    */
 +enum {
 +    IH_ARCH_INVALID        = 0,    /* Invalid CPU    */
 +    IH_ARCH_ALPHA,            /* Alpha    */
 +    IH_ARCH_ARM,            /* ARM        */
 +    IH_ARCH_I386,            /* Intel x86    */
 +    IH_ARCH_IA64,            /* IA64        */
 +    IH_ARCH_MIPS,            /* MIPS        */
 +    IH_ARCH_MIPS64,            /* MIPS     64 Bit */
 +    IH_ARCH_PPC,            /* PowerPC    */
 +    IH_ARCH_S390,            /* IBM S390    */
 +    IH_ARCH_SH,            /* SuperH    */
 +    IH_ARCH_SPARC,            /* Sparc    */
 +    IH_ARCH_SPARC64,        /* Sparc 64 Bit */
 +    IH_ARCH_M68K,            /* M68K        */
 +    IH_ARCH_NIOS,            /* Nios-32    */
 +    IH_ARCH_MICROBLAZE,        /* MicroBlaze   */
 +    IH_ARCH_NIOS2,            /* Nios-II    */
 +    IH_ARCH_BLACKFIN,        /* Blackfin    */
 +    IH_ARCH_AVR32,            /* AVR32    */
 +    IH_ARCH_ST200,            /* STMicroelectronics ST200  */
 +    IH_ARCH_SANDBOX,        /* Sandbox architecture (test only) */
 +    IH_ARCH_NDS32,            /* ANDES Technology - NDS32  */
 +    IH_ARCH_OPENRISC,        /* OpenRISC 1000  */
 +    IH_ARCH_ARM64,            /* ARM64    */
 +    IH_ARCH_ARC,            /* Synopsys DesignWare ARC */
 +    IH_ARCH_X86_64,            /* AMD x86_64, Intel and Via */
 +    IH_ARCH_XTENSA,            /* Xtensa    */
 +    IH_ARCH_RISCV,            /* RISC-V */
 +
 +    IH_ARCH_COUNT,
 +};
  /*
   * Image Types
@@ -XXX,XX +XXX,XX @@
   *    U-Boot's command interpreter; this feature is especially
   *    useful when you configure U-Boot to use a real shell (hush)
   *    as command interpreter (=> Shell Scripts).
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_TYPE_INVALID        0    /* Invalid Image        */
 -#define IH_TYPE_STANDALONE    1    /* Standalone Program        */
 -#define IH_TYPE_KERNEL        2    /* OS Kernel Image        */
 -#define IH_TYPE_RAMDISK        3    /* RAMDisk Image        */
 -#define IH_TYPE_MULTI        4    /* Multi-File Image        */
 -#define IH_TYPE_FIRMWARE    5    /* Firmware Image        */
 -#define IH_TYPE_SCRIPT        6    /* Script file            */
 -#define IH_TYPE_FILESYSTEM    7    /* Filesystem Image (any type)    */
 -#define IH_TYPE_FLATDT        8    /* Binary Flat Device Tree Blob    */
 -#define IH_TYPE_KERNEL_NOLOAD  14    /* OS Kernel Image (noload)    */
 +enum {
 +    IH_TYPE_INVALID        = 0,    /* Invalid Image        */
 +    IH_TYPE_STANDALONE,        /* Standalone Program        */
 +    IH_TYPE_KERNEL,            /* OS Kernel Image        */
 +    IH_TYPE_RAMDISK,        /* RAMDisk Image        */
 +    IH_TYPE_MULTI,            /* Multi-File Image        */
 +    IH_TYPE_FIRMWARE,        /* Firmware Image        */
 +    IH_TYPE_SCRIPT,            /* Script file            */
 +    IH_TYPE_FILESYSTEM,        /* Filesystem Image (any type)    */
 +    IH_TYPE_FLATDT,            /* Binary Flat Device Tree Blob    */
 +    IH_TYPE_KWBIMAGE,        /* Kirkwood Boot Image        */
 +    IH_TYPE_IMXIMAGE,        /* Freescale IMXBoot Image    */
 +    IH_TYPE_UBLIMAGE,        /* Davinci UBL Image        */
 +    IH_TYPE_OMAPIMAGE,        /* TI OMAP Config Header Image    */
 +    IH_TYPE_AISIMAGE,        /* TI Davinci AIS Image        */
 +    /* OS Kernel Image, can run from any load address */
 +    IH_TYPE_KERNEL_NOLOAD,
 +    IH_TYPE_PBLIMAGE,        /* Freescale PBL Boot Image    */
 +    IH_TYPE_MXSIMAGE,        /* Freescale MXSBoot Image    */
 +    IH_TYPE_GPIMAGE,        /* TI Keystone GPHeader Image    */
 +    IH_TYPE_ATMELIMAGE,        /* ATMEL ROM bootable Image    */
 +    IH_TYPE_SOCFPGAIMAGE,        /* Altera SOCFPGA CV/AV Preloader */
 +    IH_TYPE_X86_SETUP,        /* x86 setup.bin Image        */
 +    IH_TYPE_LPC32XXIMAGE,        /* x86 setup.bin Image        */
 +    IH_TYPE_LOADABLE,        /* A list of typeless images    */
 +    IH_TYPE_RKIMAGE,        /* Rockchip Boot Image        */
 +    IH_TYPE_RKSD,            /* Rockchip SD card        */
 +    IH_TYPE_RKSPI,            /* Rockchip SPI image        */
 +    IH_TYPE_ZYNQIMAGE,        /* Xilinx Zynq Boot Image */
 +    IH_TYPE_ZYNQMPIMAGE,        /* Xilinx ZynqMP Boot Image */
 +    IH_TYPE_ZYNQMPBIF,        /* Xilinx ZynqMP Boot Image (bif) */
 +    IH_TYPE_FPGA,            /* FPGA Image */
 +    IH_TYPE_VYBRIDIMAGE,    /* VYBRID .vyb Image */
 +    IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
 +    IH_TYPE_FIRMWARE_IVT,        /* Firmware Image with HABv4 IVT */
 +    IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
 +    IH_TYPE_STM32IMAGE,        /* STMicroelectronics STM32 Image */
 +    IH_TYPE_SOCFPGAIMAGE_V1,    /* Altera SOCFPGA A10 Preloader    */
 +    IH_TYPE_MTKIMAGE,        /* MediaTek BootROM loadable Image */
 +    IH_TYPE_IMX8MIMAGE,        /* Freescale IMX8MBoot Image    */
 +    IH_TYPE_IMX8IMAGE,        /* Freescale IMX8Boot Image    */
 +    IH_TYPE_COPRO,            /* Coprocessor Image for remoteproc*/
 +    IH_TYPE_SUNXI_EGON,        /* Allwinner eGON Boot Image */
 +
 +    IH_TYPE_COUNT,            /* Number of image types */
 +};
  /*
   * Compression Types
 + *
 + * The following are exposed to uImage header.
 + * New IDs *MUST* be appended at the end of the list and *NEVER*
 + * inserted for backward compatibility.
   */
 -#define IH_COMP_NONE        0    /*  No     Compression Used    */
 -#define IH_COMP_GZIP        1    /* gzip     Compression Used    */
 -#define IH_COMP_BZIP2        2    /* bzip2 Compression Used    */
 +enum {
 +    IH_COMP_NONE        = 0,    /*  No     Compression Used    */
 +    IH_COMP_GZIP,            /* gzip     Compression Used    */
 +    IH_COMP_BZIP2,            /* bzip2 Compression Used    */
 +    IH_COMP_LZMA,            /* lzma  Compression Used    */
 +    IH_COMP_LZO,            /* lzo   Compression Used    */
 +    IH_COMP_LZ4,            /* lz4   Compression Used    */
 +    IH_COMP_ZSTD,            /* zstd   Compression Used    */
 +
 +    IH_COMP_COUNT,
 +};
  #define IH_MAGIC    0x27051956    /* Image Magic Number        */
  #define IH_NMLEN        32    /* Image Name Length        */
  /*
 - * all data in network byte order (aka natural aka bigendian)
 + * Legacy format image header,
 + * all data in network byte order (aka natural aka bigendian).
   */
 -
  typedef struct uboot_image_header {
      uint32_t    ih_magic;    /* Image Header Magic Number    */
      uint32_t    ih_hcrc;    /* Image Header CRC Checksum    */
 --
-.30.1
+.35.3

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage
 From: Bin Meng <bin.meng@windriver.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+VxWorks 7 uses the same boot interface as the Linux kernel on Arm
-the address bytes. Note only SPI mode is supported by SST flashes.
+(64-bit only), PowerPC and RISC-V architectures. Add logic to set
+is_linux to true for VxWorks uImage for these architectures in
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+load_uboot_image().
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ hw/core/loader.c | 15 +++++++++++++++
-file changed, 3 insertions(+)
+file changed, 15 insertions(+)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/hw/core/loader.c b/hw/core/loader.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/core/loader.c
-+++ b/hw/block/m25p80.c
++++ b/hw/core/loader.c
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
-     s->needed_bytes = get_addr_length(s);
+         if (is_linux) {
-     switch (get_man(s)) {
+             if (hdr->ih_os == IH_OS_LINUX) {
-     /* Dummy cycles - modeled with bytes writes instead of bits */
+                 *is_linux = 1;
-+    case MAN_SST:
++            } else if (hdr->ih_os == IH_OS_VXWORKS) {
-+        s->needed_bytes += 1;
++                /*
-+        break;
++                 * VxWorks 7 uses the same boot interface as the Linux kernel
-     case MAN_WINBOND:
++                 * on Arm (64-bit only), PowerPC and RISC-V architectures.
-         s->needed_bytes += 8;
++                 */
-         break;
++                switch (hdr->ih_arch) {
 +                case IH_ARCH_ARM64:
 +                case IH_ARCH_PPC:
 +                case IH_ARCH_RISCV:
 +                    *is_linux = 1;
 +                    break;
 +                default:
 +                    *is_linux = 0;
 +                    break;
 +                }
              } else {
                  *is_linux = 0;
              }
 --
-.30.1
+.35.3

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:

Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220525

for you to fetch changes up to 8fe63fe8e512d77583d6798acd2164f1fa1e40ab:

hw/core: loader: Set is_linux to true for VxWorks uImage (2022-05-24 10:38:50 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.1

* Fixes for accessing VS hypervisor CSRs
 * Improvements for RISC-V Vector extension
 * Fixes for accessing mtimecmp
 * Add new short-isa-string CPU option
 * Improvements to RISC-V machine error handling
 * Disable the "G" extension by default internally, no functional change
 * Enforce floating point extension requirements
 * Cleanup ISA extension checks
 * Resolve redundant property accessors
 * Fix typo of mimpid cpu option
 * Improvements for virtulisation
 * Add zicsr/zifencei to isa_string
 * Support for VxWorks uImage

----------------------------------------------------------------
Anup Patel (4):
      target/riscv: Fix csr number based privilege checking
      target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
      target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
      hw/riscv: virt: Fix interrupt parent for dynamic platform devices

Atish Patra (1):
      hw/intc: Pass correct hartid while updating mtimecmp

Bernhard Beschow (2):
      hw/vfio/pci-quirks: Resolve redundant property getters
      hw/riscv/sifive_u: Resolve redundant property accessors

Bin Meng (2):
      hw/core: Sync uboot_image.h from U-Boot v2022.01
      hw/core: loader: Set is_linux to true for VxWorks uImage

Dylan Reid (1):
      target/riscv: Fix VS mode hypervisor CSR access

Frank Chang (1):
      target/riscv: Fix typo of mimpid cpu option

Hongren (Zenithal) Zheng (1):
      target/riscv: add zicsr/zifencei to isa_string

Tsukasa OI (9):
      target/riscv: Move Zhinx* extensions on ISA string
      target/riscv: Add short-isa-string option
      hw/riscv: Make CPU config error handling generous (virt/spike)
      hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
      target/riscv: Fix coding style on "G" expansion
      target/riscv: Disable "G" by default
      target/riscv: Change "G" expansion
      target/riscv: FP extension requirements
      target/riscv: Move/refactor ISA extension checks

Weiwei Li (1):
      target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

eopXD (1):
      target/riscv: rvv: Fix early exit condition for whole register load/store

From: Dylan Reid <dylan@rivosinc.com>

VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.

Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.

Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
 #if !defined(CONFIG_USER_ONLY)
     int effective_priv = env->priv;
 
-    if (riscv_has_ext(env, RVH) &&
-        env->priv == PRV_S &&
-        !riscv_cpu_virt_enabled(env)) {
+    if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
         /*
-         * We are in S mode without virtualisation, therefore we are in HS Mode.
+         * We are in either HS or VS mode.
          * Add 1 to the effective privledge level to allow us to access the
-         * Hypervisor CSRs.
+         * Hypervisor CSRs. The `hmode` predicate will determine if access
+         * should be allowed(HS) or if a virtual instruction exception should be
+         * raised(VS).
          */
         effective_priv++;
     }
-- 
2.35.3

From: eopXD <eop.chen@sifive.com>

Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++------------
 1 file changed, 31 insertions(+), 27 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
 typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
 
 static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
-                             gen_helper_ldst_whole *fn, DisasContext *s,
-                             bool is_store)
+                             uint32_t width, gen_helper_ldst_whole *fn,
+                             DisasContext *s, bool is_store)
 {
-    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
+    uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
     TCGLabel *over = gen_new_label();
     tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
  * load and store whole register instructions ignore vtype and vl setting.
  * Thus, we don't need to check vill bit. (Section 7.9)
  */
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE)                      \
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE)               \
 static bool trans_##NAME(DisasContext *s, arg_##NAME * a)                 \
 {                                                                         \
     if (require_rvv(s) &&                                                 \
         QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                                 \
-        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
-                                s, IS_STORE);                             \
+        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH,             \
+                                gen_helper_##NAME, s, IS_STORE);          \
     }                                                                     \
     return false;                                                         \
 }
 
-GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, false)
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
-GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, false)
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
-GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, false)
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
-GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, false)
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
-
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
+GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, 1, false)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
+GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, 1, false)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
+GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, 1, false)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
+GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, 1, false)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
+
+/*
+ * The vector whole register store instructions are encoded similar to
+ * unmasked unit-stride store of elements with EEW=8.
+ */
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
 
 /*
  *** Vector Integer Arithmetic Instructions
-- 
2.35.3

From: Atish Patra <atishp@rivosinc.com>

timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.

Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aclint.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
                 continue;
             }
             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
-                                              i, env->timecmp);
+                                              mtimer->hartid_base + i,
+                                              env->timecmp);
         }
         return;
     }
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
         ISA_EDATA_ENTRY(zfh, ext_zfh),
         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
         ISA_EDATA_ENTRY(zdinx, ext_zdinx),
         ISA_EDATA_ENTRY(zba, ext_zba),
         ISA_EDATA_ENTRY(zbb, ext_zbb),
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
         ISA_EDATA_ENTRY(zkt, ext_zkt),
         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
         ISA_EDATA_ENTRY(svinval, ext_svinval),
         ISA_EDATA_ENTRY(svnapot, ext_svnapot),
         ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.

For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier) with FPU support caused a kernel panic.

Operating Systems which short-isa-string might be helpful:

1.  Linux (5.17 or earlier)
2.  FreeBSD (at least 14.0-CURRENT)
3.  OpenBSD (at least current development version)

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool aia;
     bool debug;
     uint64_t resetvec;
+
+    bool short_isa_string;
 };
 
 typedef struct RISCVCPUConfig RISCVCPUConfig;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
 
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+
+    DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
         }
     }
     *p = '\0';
-    riscv_isa_string_ext(cpu, &isa_str, maxlen);
+    if (!cpu->cfg.short_isa_string) {
+        riscv_isa_string_ext(cpu, &isa_str, maxlen);
+    }
     return isa_str;
 }
 
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
virt/spike machines.  It now just prints error message and quits (without
coredumps and aborts).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 2 +-
 hw/riscv/virt.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                 base_hartid, &error_abort);
         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
                                 hart_count, &error_abort);
-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
 
         /* Core Local Interruptor (timer and IPI) for each socket */
         riscv_aclint_swi_create(
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                 base_hartid, &error_abort);
         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
                                 hart_count, &error_abort);
-        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
 
         if (!kvm_enabled()) {
             if (s->have_aclint) {
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines.  It now just prints error message and
quits (without coredumps and aborts).

This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 hw/riscv/sifive_e.c  | 2 +-
 hw/riscv/sifive_u.c  | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
     /* Boot ROM */
     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 
     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
                             &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
     /* Mask ROM */
     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
+    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
     /*
      * The cluster must be realized after the RISC-V hart array container,
      * as the container's CPU object is only created on realize, and the
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G".  Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     /* Defaults for standard extensions */
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
-    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
+    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
-- 
2.35.3

From: Tsukasa OI <research_trasio@irq.a4lg.com>

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.

This commit adds certain checks for consistent FP arithmetic:

-   F requires Zicsr
-   Zfinx requires Zicsr
-   Zfh/Zfhmin require F
-   D requires F
-   V requires D

Because F/D/Zicsr are enabled by default (and an error will not occur unless
we manually disable one or more of prerequisites), this commit just enforces
the user to give consistent combinations.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+
+        /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
             cpu->cfg.ext_zhinxmin) {
             cpu->cfg.ext_zfinx = true;
         }
 
-        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
-            error_setg(errp, "Zfinx extension requires Zicsr");
-            return;
+        if (cpu->cfg.ext_zfinx) {
+            if (!cpu->cfg.ext_icsr) {
+                error_setg(errp, "Zfinx extension requires Zicsr");
+                return;
+            }
+            if (cpu->cfg.ext_f) {
+                error_setg(errp,
+                    "Zfinx cannot be supported together with F extension");
+                return;
+            }
         }
 
         if (cpu->cfg.ext_zk) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_zksh = true;
         }
 
-        /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
             ext |= RVI;
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
-        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
-            return;
-        }
         if (cpu->cfg.ext_j) {
             ext |= RVJ;
         }
-        if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
-                                   cpu->cfg.ext_zfhmin)) {
-            error_setg(errp,
-                    "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
-                    " 'Zfhmin'");
-            return;
-        }
 
         set_misa(env, env->misa_mxl, ext);
     }
-- 
2.35.3

From: Bernhard Beschow <shentey@gmail.com>

The QOM API already provides getters for uint64 and uint32 values, so reuse
them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301225220.239065-2-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/vfio/pci-quirks.c | 34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -XXX,XX +XXX,XX @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
     return 0;
 }
 
-static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
-                                     const char *name,
-                                     void *opaque, Error **errp)
-{
-    uint64_t tgt = (uintptr_t) opaque;
-    visit_type_uint64(v, name, &tgt, errp);
-}
-
-static void vfio_pci_nvlink2_get_link_speed(Object *obj, Visitor *v,
-                                                 const char *name,
-                                                 void *opaque, Error **errp)
-{
-    uint32_t link_speed = (uint32_t)(uintptr_t) opaque;
-    visit_type_uint32(v, name, &link_speed, errp);
-}
-
 int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
 {
     int ret;
@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp)
                                nv2reg->size, p);
     QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
 
-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
-                        (void *) (uintptr_t) cap->tgt);
+    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
+                                   (uint64_t *) &cap->tgt,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvidia_gpu_setup_quirk(vdev->vbasedev.name, cap->tgt,
                                           nv2reg->size);
 free_exit:
@@ -XXX,XX +XXX,XX @@ int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp)
         QLIST_INSERT_HEAD(&vdev->bars[0].quirks, quirk, next);
     }
 
-    object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64",
-                        vfio_pci_nvlink2_get_tgt, NULL, NULL,
-                        (void *) (uintptr_t) captgt->tgt);
+    object_property_add_uint64_ptr(OBJECT(vdev), "nvlink2-tgt",
+                                   (uint64_t *) &captgt->tgt,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev->vbasedev.name, captgt->tgt,
                                               atsdreg->size);
 
-    object_property_add(OBJECT(vdev), "nvlink2-link-speed", "uint32",
-                        vfio_pci_nvlink2_get_link_speed, NULL, NULL,
-                        (void *) (uintptr_t) capspeed->link_speed);
+    object_property_add_uint32_ptr(OBJECT(vdev), "nvlink2-link-speed",
+                                   &capspeed->link_speed,
+                                   OBJ_PROP_FLAG_READ);
     trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev->vbasedev.name,
                                               capspeed->link_speed);
 free_exit:
-- 
2.35.3

From: Bernhard Beschow <shentey@gmail.com>

The QOM API already provides accessors for uint32 values, so reuse them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220301225220.239065-3-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 24 ++++--------------------
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
     s->start_in_flash = value;
 }
 
-static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
-                                             const char *name, void *opaque,
-                                             Error **errp)
-{
-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
-static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
-                                             const char *name, void *opaque,
-                                             Error **errp)
-{
-    visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
 static void sifive_u_machine_instance_init(Object *obj)
 {
     SiFiveUState *s = RISCV_U_MACHINE(obj);
 
     s->start_in_flash = false;
     s->msel = 0;
-    object_property_add(obj, "msel", "uint32",
-                        sifive_u_machine_get_uint32_prop,
-                        sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+    object_property_add_uint32_ptr(obj, "msel", &s->msel,
+                                   OBJ_PROP_FLAG_READWRITE);
     object_property_set_description(obj, "msel",
                                     "Mode Select (MSEL[3:0]) pin state");
 
     s->serial = OTP_SERIAL;
-    object_property_add(obj, "serial", "uint32",
-                        sifive_u_machine_get_uint32_prop,
-                        sifive_u_machine_set_uint32_prop, NULL, &s->serial);
+    object_property_add_uint32_ptr(obj, "serial", &s->serial,
+                                   OBJ_PROP_FLAG_READWRITE);
     object_property_set_description(obj, "serial", "Board serial number");
 }
 
-- 
2.35.3

From: Weiwei Li <liweiwei@iscas.ac.cn>

- setting ext_g will implicitly set ext_i

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

"mimpid" cpu option was mistyped to "mipid".

Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 +-
 target/riscv/cpu.c | 4 ++--
 target/riscv/csr.c | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
 
     uint32_t mvendorid;
     uint64_t marchid;
-    uint64_t mipid;
+    uint64_t mimpid;
 
     /* Vendor-specific custom extensions */
     bool ext_XVentanaCondOps;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
                              (QEMU_VERSION_MINOR << 8)  | \
                              (QEMU_VERSION_MICRO))
-#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
+#define RISCV_CPU_MIMPID    RISCV_CPU_MARCHID
 
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
-    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+    DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
 
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_mipid(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+static RISCVException read_mimpid(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     CPUState *cs = env_cpu(env);
     RISCVCPU *cpu = RISCV_CPU(cs);
 
-    *val = cpu->cfg.mipid;
+    *val = cpu->cfg.mimpid;
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     /* Machine Information Registers */
     [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
     [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
-    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
+    [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
 
     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.

Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     int read_only = get_field(csrno, 0xC00) == 3;
     int csr_min_priv = csr_ops[csrno].min_priv_ver;
 #if !defined(CONFIG_USER_ONLY)
-    int effective_priv = env->priv;
+    int csr_priv, effective_priv = env->priv;
 
     if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
         /*
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
         effective_priv++;
     }
 
-    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
+    csr_priv = get_field(csrno, 0x300);
+    if (!env->debugger && (effective_priv < csr_priv)) {
+        if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         case RISCV_EXCP_INST_PAGE_FAULT:
         case RISCV_EXCP_LOAD_PAGE_FAULT:
         case RISCV_EXCP_STORE_PAGE_FAULT:
-            write_gva = true;
+            write_gva = env->two_stage_lookup;
             tval = env->badaddr;
             break;
         case RISCV_EXCP_ILLEGAL_INST:
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 /* Trap into HS mode */
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
-                write_gva = false;
             }
             env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
         }
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.

In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM or hstatus.VTVM).

We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  8 +++++++-
 target/riscv/cpu.c        |  2 ++
 target/riscv/cpu_helper.c |  1 +
 target/riscv/translate.c  | 17 +++++++++++++----
 4 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 
 #define TCG_GUEST_DEFAULT_MO 0
 
+/*
+ * RISC-V-specific extra insn start words:
+ * 1: Original instruction opcode
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #define TYPE_RISCV_CPU "riscv-cpu"
 
 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
     target_ulong frm;
 
     target_ulong badaddr;
-    uint32_t bins;
+    target_ulong bins;
 
     target_ulong guest_phys_fault_addr;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
     } else {
         env->pc = data[0];
     }
+    env->bins = data[1];
 }
 
 static void riscv_cpu_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mcause = 0;
     env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
+    env->bins = 0;
     env->two_stage_lookup = false;
 
     /* Initialized default priorities of local interrupts. */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->badaddr;
             break;
         case RISCV_EXCP_ILLEGAL_INST:
+        case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
             tval = env->bins;
             break;
         default:
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* PointerMasking extension */
     bool pm_mask_enabled;
     bool pm_base_enabled;
+    /* TCG of the current insn_start */
+    TCGOp *insn_start;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
 
 static void gen_exception_illegal(DisasContext *ctx)
 {
-    tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
-                   offsetof(CPURISCVState, bins));
-
     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 }
 
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 /* Include decoders for factored-out extensions */
 #include "decode-XVentanaCondOps.c.inc"
 
+static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
+{
+    assert(ctx->insn_start != NULL);
+    tcg_set_insn_start_param(ctx->insn_start, 1, opc);
+    ctx->insn_start = NULL;
+}
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 
     /* Check for compressed insn */
     if (extract16(opcode, 0, 2) != 3) {
+        decode_save_opc(ctx, opcode);
         if (!has_ext(ctx, RVC)) {
             gen_exception_illegal(ctx);
         } else {
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         opcode32 = deposit32(opcode32, 16, 16,
                              translator_lduw(env, &ctx->base,
                                              ctx->base.pc_next + 2));
+        decode_save_opc(ctx, opcode32);
         ctx->opcode = opcode32;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next);
+    tcg_gen_insn_start(ctx->base.pc_next, 0);
+    ctx->insn_start = tcg_last_op();
 }
 
 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-- 
2.35.3

From: Anup Patel <apatel@ventanamicro.com>

When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.

In case of  multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.

Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
platform FDT entries")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
+    if (!socket) {
+        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+                                       memmap[VIRT_PLATFORM_BUS].base,
+                                       memmap[VIRT_PLATFORM_BUS].size,
+                                       VIRT_PLATFORM_BUS_IRQ);
+    }
 
     g_free(plic_name);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     }
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
-
     g_free(imsic_name);
 
     /* S-level IMSIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 
-    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
-                                   memmap[VIRT_PLATFORM_BUS].base,
-                                   memmap[VIRT_PLATFORM_BUS].size,
-                                   VIRT_PLATFORM_BUS_IRQ);
+    if (!socket) {
+        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+                                       memmap[VIRT_PLATFORM_BUS].base,
+                                       memmap[VIRT_PLATFORM_BUS].size,
+                                       VIRT_PLATFORM_BUS_IRQ);
+    }
 
     g_free(aplic_name);
 
-- 
2.35.3

From: "Hongren (Zenithal) Zheng" <i@zenithal.me>

Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
      *    extensions by an underscore.
      */
     struct isa_ext_data isa_edata_arr[] = {
+        ISA_EDATA_ENTRY(zicsr, ext_icsr),
+        ISA_EDATA_ENTRY(zifencei, ext_ifencei),
         ISA_EDATA_ENTRY(zfh, ext_zfh),
         ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
         ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-- 
2.35.3

From: Bin Meng <bin.meng@windriver.com>

Sync uboot_image.h from upstream U-Boot v2022.01 release [1].

[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/core/uboot_image.h | 213 ++++++++++++++++++++++++++++--------------
 1 file changed, 142 insertions(+), 71 deletions(-)

diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/uboot_image.h
+++ b/hw/core/uboot_image.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * (C) Copyright 2008 Semihalf
+ *
  * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
  ********************************************************************
  * NOTE: This header file defines an interface to U-Boot. Including
  * this (unmodified) header file in another file is considered normal
@@ -XXX,XX +XXX,XX @@
 
 /*
  * Operating System Codes
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_OS_INVALID		0	/* Invalid OS	*/
-#define IH_OS_OPENBSD		1	/* OpenBSD	*/
-#define IH_OS_NETBSD		2	/* NetBSD	*/
-#define IH_OS_FREEBSD		3	/* FreeBSD	*/
-#define IH_OS_4_4BSD		4	/* 4.4BSD	*/
-#define IH_OS_LINUX		5	/* Linux	*/
-#define IH_OS_SVR4		6	/* SVR4		*/
-#define IH_OS_ESIX		7	/* Esix		*/
-#define IH_OS_SOLARIS		8	/* Solaris	*/
-#define IH_OS_IRIX		9	/* Irix		*/
-#define IH_OS_SCO		10	/* SCO		*/
-#define IH_OS_DELL		11	/* Dell		*/
-#define IH_OS_NCR		12	/* NCR		*/
-#define IH_OS_LYNXOS		13	/* LynxOS	*/
-#define IH_OS_VXWORKS		14	/* VxWorks	*/
-#define IH_OS_PSOS		15	/* pSOS		*/
-#define IH_OS_QNX		16	/* QNX		*/
-#define IH_OS_U_BOOT		17	/* Firmware	*/
-#define IH_OS_RTEMS		18	/* RTEMS	*/
-#define IH_OS_ARTOS		19	/* ARTOS	*/
-#define IH_OS_UNITY		20	/* Unity OS	*/
+enum {
+	IH_OS_INVALID		= 0,	/* Invalid OS	*/
+	IH_OS_OPENBSD,			/* OpenBSD	*/
+	IH_OS_NETBSD,			/* NetBSD	*/
+	IH_OS_FREEBSD,			/* FreeBSD	*/
+	IH_OS_4_4BSD,			/* 4.4BSD	*/
+	IH_OS_LINUX,			/* Linux	*/
+	IH_OS_SVR4,			/* SVR4		*/
+	IH_OS_ESIX,			/* Esix		*/
+	IH_OS_SOLARIS,			/* Solaris	*/
+	IH_OS_IRIX,			/* Irix		*/
+	IH_OS_SCO,			/* SCO		*/
+	IH_OS_DELL,			/* Dell		*/
+	IH_OS_NCR,			/* NCR		*/
+	IH_OS_LYNXOS,			/* LynxOS	*/
+	IH_OS_VXWORKS,			/* VxWorks	*/
+	IH_OS_PSOS,			/* pSOS		*/
+	IH_OS_QNX,			/* QNX		*/
+	IH_OS_U_BOOT,			/* Firmware	*/
+	IH_OS_RTEMS,			/* RTEMS	*/
+	IH_OS_ARTOS,			/* ARTOS	*/
+	IH_OS_UNITY,			/* Unity OS	*/
+	IH_OS_INTEGRITY,		/* INTEGRITY	*/
+	IH_OS_OSE,			/* OSE		*/
+	IH_OS_PLAN9,			/* Plan 9	*/
+	IH_OS_OPENRTOS,		/* OpenRTOS	*/
+	IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
+	IH_OS_TEE,			/* Trusted Execution Environment */
+	IH_OS_OPENSBI,			/* RISC-V OpenSBI */
+	IH_OS_EFI,			/* EFI Firmware (e.g. GRUB2) */
+
+	IH_OS_COUNT,
+};
 
 /*
  * CPU Architecture Codes (supported by Linux)
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_CPU_INVALID		0	/* Invalid CPU	*/
-#define IH_CPU_ALPHA		1	/* Alpha	*/
-#define IH_CPU_ARM		2	/* ARM		*/
-#define IH_CPU_I386		3	/* Intel x86	*/
-#define IH_CPU_IA64		4	/* IA64		*/
-#define IH_CPU_MIPS		5	/* MIPS		*/
-#define IH_CPU_MIPS64		6	/* MIPS	 64 Bit */
-#define IH_CPU_PPC		7	/* PowerPC	*/
-#define IH_CPU_S390		8	/* IBM S390	*/
-#define IH_CPU_SH		9	/* SuperH	*/
-#define IH_CPU_SPARC		10	/* Sparc	*/
-#define IH_CPU_SPARC64		11	/* Sparc 64 Bit */
-#define IH_CPU_M68K		12	/* M68K		*/
-#define IH_CPU_NIOS		13	/* Nios-32	*/
-#define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
-#define IH_CPU_NIOS2		15	/* Nios-II	*/
-#define IH_CPU_BLACKFIN		16	/* Blackfin	*/
-#define IH_CPU_AVR32		17	/* AVR32	*/
+enum {
+	IH_ARCH_INVALID		= 0,	/* Invalid CPU	*/
+	IH_ARCH_ALPHA,			/* Alpha	*/
+	IH_ARCH_ARM,			/* ARM		*/
+	IH_ARCH_I386,			/* Intel x86	*/
+	IH_ARCH_IA64,			/* IA64		*/
+	IH_ARCH_MIPS,			/* MIPS		*/
+	IH_ARCH_MIPS64,			/* MIPS	 64 Bit */
+	IH_ARCH_PPC,			/* PowerPC	*/
+	IH_ARCH_S390,			/* IBM S390	*/
+	IH_ARCH_SH,			/* SuperH	*/
+	IH_ARCH_SPARC,			/* Sparc	*/
+	IH_ARCH_SPARC64,		/* Sparc 64 Bit */
+	IH_ARCH_M68K,			/* M68K		*/
+	IH_ARCH_NIOS,			/* Nios-32	*/
+	IH_ARCH_MICROBLAZE,		/* MicroBlaze   */
+	IH_ARCH_NIOS2,			/* Nios-II	*/
+	IH_ARCH_BLACKFIN,		/* Blackfin	*/
+	IH_ARCH_AVR32,			/* AVR32	*/
+	IH_ARCH_ST200,			/* STMicroelectronics ST200  */
+	IH_ARCH_SANDBOX,		/* Sandbox architecture (test only) */
+	IH_ARCH_NDS32,			/* ANDES Technology - NDS32  */
+	IH_ARCH_OPENRISC,		/* OpenRISC 1000  */
+	IH_ARCH_ARM64,			/* ARM64	*/
+	IH_ARCH_ARC,			/* Synopsys DesignWare ARC */
+	IH_ARCH_X86_64,			/* AMD x86_64, Intel and Via */
+	IH_ARCH_XTENSA,			/* Xtensa	*/
+	IH_ARCH_RISCV,			/* RISC-V */
+
+	IH_ARCH_COUNT,
+};
 
 /*
  * Image Types
@@ -XXX,XX +XXX,XX @@
  *	U-Boot's command interpreter; this feature is especially
  *	useful when you configure U-Boot to use a real shell (hush)
  *	as command interpreter (=> Shell Scripts).
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
 
-#define IH_TYPE_INVALID		0	/* Invalid Image		*/
-#define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
-#define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
-#define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
-#define IH_TYPE_MULTI		4	/* Multi-File Image		*/
-#define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
-#define IH_TYPE_SCRIPT		6	/* Script file			*/
-#define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
-#define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
-#define IH_TYPE_KERNEL_NOLOAD  14	/* OS Kernel Image (noload)	*/
+enum {
+	IH_TYPE_INVALID		= 0,	/* Invalid Image		*/
+	IH_TYPE_STANDALONE,		/* Standalone Program		*/
+	IH_TYPE_KERNEL,			/* OS Kernel Image		*/
+	IH_TYPE_RAMDISK,		/* RAMDisk Image		*/
+	IH_TYPE_MULTI,			/* Multi-File Image		*/
+	IH_TYPE_FIRMWARE,		/* Firmware Image		*/
+	IH_TYPE_SCRIPT,			/* Script file			*/
+	IH_TYPE_FILESYSTEM,		/* Filesystem Image (any type)	*/
+	IH_TYPE_FLATDT,			/* Binary Flat Device Tree Blob	*/
+	IH_TYPE_KWBIMAGE,		/* Kirkwood Boot Image		*/
+	IH_TYPE_IMXIMAGE,		/* Freescale IMXBoot Image	*/
+	IH_TYPE_UBLIMAGE,		/* Davinci UBL Image		*/
+	IH_TYPE_OMAPIMAGE,		/* TI OMAP Config Header Image	*/
+	IH_TYPE_AISIMAGE,		/* TI Davinci AIS Image		*/
+	/* OS Kernel Image, can run from any load address */
+	IH_TYPE_KERNEL_NOLOAD,
+	IH_TYPE_PBLIMAGE,		/* Freescale PBL Boot Image	*/
+	IH_TYPE_MXSIMAGE,		/* Freescale MXSBoot Image	*/
+	IH_TYPE_GPIMAGE,		/* TI Keystone GPHeader Image	*/
+	IH_TYPE_ATMELIMAGE,		/* ATMEL ROM bootable Image	*/
+	IH_TYPE_SOCFPGAIMAGE,		/* Altera SOCFPGA CV/AV Preloader */
+	IH_TYPE_X86_SETUP,		/* x86 setup.bin Image		*/
+	IH_TYPE_LPC32XXIMAGE,		/* x86 setup.bin Image		*/
+	IH_TYPE_LOADABLE,		/* A list of typeless images	*/
+	IH_TYPE_RKIMAGE,		/* Rockchip Boot Image		*/
+	IH_TYPE_RKSD,			/* Rockchip SD card		*/
+	IH_TYPE_RKSPI,			/* Rockchip SPI image		*/
+	IH_TYPE_ZYNQIMAGE,		/* Xilinx Zynq Boot Image */
+	IH_TYPE_ZYNQMPIMAGE,		/* Xilinx ZynqMP Boot Image */
+	IH_TYPE_ZYNQMPBIF,		/* Xilinx ZynqMP Boot Image (bif) */
+	IH_TYPE_FPGA,			/* FPGA Image */
+	IH_TYPE_VYBRIDIMAGE,	/* VYBRID .vyb Image */
+	IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
+	IH_TYPE_FIRMWARE_IVT,		/* Firmware Image with HABv4 IVT */
+	IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
+	IH_TYPE_STM32IMAGE,		/* STMicroelectronics STM32 Image */
+	IH_TYPE_SOCFPGAIMAGE_V1,	/* Altera SOCFPGA A10 Preloader	*/
+	IH_TYPE_MTKIMAGE,		/* MediaTek BootROM loadable Image */
+	IH_TYPE_IMX8MIMAGE,		/* Freescale IMX8MBoot Image	*/
+	IH_TYPE_IMX8IMAGE,		/* Freescale IMX8Boot Image	*/
+	IH_TYPE_COPRO,			/* Coprocessor Image for remoteproc*/
+	IH_TYPE_SUNXI_EGON,		/* Allwinner eGON Boot Image */
+
+	IH_TYPE_COUNT,			/* Number of image types */
+};
 
 /*
  * Compression Types
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
  */
-#define IH_COMP_NONE		0	/*  No	 Compression Used	*/
-#define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
-#define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
+enum {
+	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
+	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
+	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
+	IH_COMP_LZMA,			/* lzma  Compression Used	*/
+	IH_COMP_LZO,			/* lzo   Compression Used	*/
+	IH_COMP_LZ4,			/* lz4   Compression Used	*/
+	IH_COMP_ZSTD,			/* zstd   Compression Used	*/
+
+	IH_COMP_COUNT,
+};
 
 #define IH_MAGIC	0x27051956	/* Image Magic Number		*/
 #define IH_NMLEN		32	/* Image Name Length		*/
 
 /*
- * all data in network byte order (aka natural aka bigendian)
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
  */
-
 typedef struct uboot_image_header {
 	uint32_t	ih_magic;	/* Image Header Magic Number	*/
 	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
-- 
2.35.3

From: Bin Meng <bin.meng@windriver.com>

VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/core/loader.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
         if (is_linux) {
             if (hdr->ih_os == IH_OS_LINUX) {
                 *is_linux = 1;
+            } else if (hdr->ih_os == IH_OS_VXWORKS) {
+                /*
+                 * VxWorks 7 uses the same boot interface as the Linux kernel
+                 * on Arm (64-bit only), PowerPC and RISC-V architectures.
+                 */
+                switch (hdr->ih_arch) {
+                case IH_ARCH_ARM64:
+                case IH_ARCH_PPC:
+                case IH_ARCH_RISCV:
+                    *is_linux = 1;
+                    break;
+                default:
+                    *is_linux = 0;
+                    break;
+                }
             } else {
                 *is_linux = 0;
             }
-- 
2.35.3