Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/61] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:
   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20 16:13:17 +0000)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Third RISC-V PR for QEMU 7.0
-This PR includes:
+ * Fixes for OpenTitan timer
- - Fix for vector CSR access
+ * Correction of OpenTitan PLIC stride length
- - Improvements to the Ibex UART device
+ * RISC-V KVM support
- - PMP improvements and bug fixes
+ * Device tree code cleanup
- - Hypervisor extension bug fixes
+ * Support for the Zve64f and Zve32f extensions
- - ramfb support for the virt machine
+ * OpenSBI binary loading support for the Spike machine
- - Fast read support for SST flash
+ * Removal of OpenSBI ELFs
- - Improvements to the microchip_pfsoc machine
+ * Support for the UXL field in xstatus
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Anup Patel (3):
-      hw/char: disable ibex uart receive if the buffer is full
+      hw/riscv: spike: Allow using binary firmware as bios
       hw/riscv: Remove macros for ELF BIOS image names
       roms/opensbi: Remove ELF images
-Asherah Connor (2):
+Frank Chang (17):
-      hw/riscv: Add fw_cfg support to virt
+      target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
-      hw/riscv: allow ramfb on virt
+      target/riscv: rvv-1.0: Add Zve64f support for configuration insns
       target/riscv: rvv-1.0: Add Zve64f support for load and store insns
       target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
       target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
       target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
       target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
       target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
       target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
       target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
       target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
       target/riscv: rvv-1.0: Add Zve32f support for configuration insns
       target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
       target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
       target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
       target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
       target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
-Bin Meng (3):
+LIU Zhiwei (23):
-      hw/block: m25p80: Support fast read for SST flashes
+      target/riscv: Adjust pmpcfg access with mxl
-      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+      target/riscv: Don't save pc when exception return
-      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+      target/riscv: Sign extend link reg for jal and jalr
       target/riscv: Sign extend pc for different XLEN
       target/riscv: Create xl field in env
       target/riscv: Ignore the pc bits above XLEN
       target/riscv: Extend pc for runtime pc write
       target/riscv: Use gdb xml according to max mxlen
       target/riscv: Relax debug check for pm write
       target/riscv: Adjust csr write mask with XLEN
       target/riscv: Create current pm fields in env
       target/riscv: Alloc tcg global for cur_pm[mask|base]
       target/riscv: Calculate address according to XLEN
       target/riscv: Split pm_enabled into mask and base
       target/riscv: Split out the vill from vtype
       target/riscv: Adjust vsetvl according to XLEN
       target/riscv: Remove VILL field in VTYPE
       target/riscv: Fix check range for first fault only
       target/riscv: Adjust vector address with mask
       target/riscv: Adjust scalar reg in vector with XLEN
       target/riscv: Set default XLEN for hypervisor
       target/riscv: Enable uxl field write
       target/riscv: Relax UXL field for debugging
-Frank Chang (1):
+Thomas Huth (1):
-      target/riscv: fix vs() to return proper error code
+      softmmu/device_tree: Silence compiler warning with --enable-sanitizers
-Georg Kotheimer (6):
+Wilfred Mallawa (3):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+      hw: timer: ibex_timer: Fixup reading w/o register
-      target/riscv: Make VSTIP and VSEIP read-only in hip
+      riscv: opentitan: fixup plic stride len
-      target/riscv: Use background registers also for MSTATUS_MPV
+      hw: timer: ibex_timer: update/add reg address
       target/riscv: Fix read and write accesses to vsip and vsie
       target/riscv: Add proper two-stage lookup exception detection
       target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
+Yanan Wang (1):
-      target/riscv: propagate PMP permission to TLB page
+      softmmu/device_tree: Remove redundant pointer assignment
       target/riscv: add log of PMP permission checking
       target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
+Yifei Jiang (13):
- docs/system/target-riscv.rst               |   1 +
+      update-linux-headers: Add asm-riscv/kvm.h
- include/hw/char/ibex_uart.h                |   4 +
+      target/riscv: Add target/riscv/kvm.c to place the public kvm interface
- include/hw/riscv/microchip_pfsoc.h         |   1 +
+      target/riscv: Implement function kvm_arch_init_vcpu
- include/hw/riscv/virt.h                    |   2 +
+      target/riscv: Implement kvm_arch_get_registers
- target/riscv/cpu.h                         |   4 +
+      target/riscv: Implement kvm_arch_put_registers
- target/riscv/pmp.h                         |   4 +-
+      target/riscv: Support start kernel directly by KVM
- hw/block/m25p80.c                          |   3 +
+      target/riscv: Support setting external interrupt by KVM
- hw/char/ibex_uart.c                        |  23 +++-
+      target/riscv: Handle KVM_EXIT_RISCV_SBI exit
- hw/riscv/microchip_pfsoc.c                 |   6 +
+      target/riscv: Add host cpu type
- hw/riscv/virt.c                            |  33 ++++++
+      target/riscv: Add kvm_riscv_get/put_regs_timer
- target/riscv/cpu.c                         |   1 +
+      target/riscv: Implement virtual time adjusting with vm state changing
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
+      target/riscv: Support virtual time context synchronization
- target/riscv/csr.c                         |  77 +++++++------
+      target/riscv: enable riscv kvm accel
  target/riscv/pmp.c                         |  84 ++++++++++----
  target/riscv/translate.c                   | 179 +----------------------------
  hw/riscv/Kconfig                           |   1 +
 files changed, 367 insertions(+), 289 deletions(-)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ meson.build                                    |   2 +
+ include/hw/char/riscv_htif.h                   |   5 +-
+ include/hw/riscv/boot.h                        |   3 +-
+ include/hw/riscv/spike.h                       |   1 +
+ include/hw/timer/ibex_timer.h                  |   1 -
+ linux-headers/asm-riscv/kvm.h                  | 128 ++++++
+ target/riscv/cpu.h                             |  58 ++-
+ target/riscv/cpu_bits.h                        |   3 +
+ target/riscv/helper.h                          |   4 +-
+ target/riscv/kvm_riscv.h                       |  25 ++
+ target/riscv/sbi_ecall_interface.h             |  72 ++++
+ hw/char/riscv_htif.c                           |  33 +-
+ hw/intc/sifive_plic.c                          |  20 +-
+ hw/riscv/boot.c                                |  16 +-
+ hw/riscv/opentitan.c                           |   2 +-
+ hw/riscv/spike.c                               |  45 ++-
+ hw/riscv/virt.c                                |  83 ++--
+ hw/timer/ibex_timer.c                          |  25 +-
+ softmmu/device_tree.c                          |  11 +-
+ target/riscv/cpu.c                             |  77 +++-
+ target/riscv/cpu_helper.c                      |  99 ++---
+ target/riscv/csr.c                             |  90 ++++-
+ target/riscv/gdbstub.c                         |  71 +++-
+ target/riscv/kvm-stub.c                        |  30 ++
+ target/riscv/kvm.c                             | 535 +++++++++++++++++++++++++
+ target/riscv/machine.c                         |  46 ++-
+ target/riscv/op_helper.c                       |   7 +-
+ target/riscv/pmp.c                             |  12 +-
+ target/riscv/translate.c                       |  94 +++--
+ target/riscv/vector_helper.c                   |  39 +-
+ target/riscv/insn_trans/trans_privileged.c.inc |   9 +-
+ target/riscv/insn_trans/trans_rva.c.inc        |   9 +-
+ target/riscv/insn_trans/trans_rvd.c.inc        |  19 +-
+ target/riscv/insn_trans/trans_rvf.c.inc        |  19 +-
+ target/riscv/insn_trans/trans_rvi.c.inc        |  39 +-
+ target/riscv/insn_trans/trans_rvv.c.inc        | 225 +++++++++--
+ .gitlab-ci.d/opensbi.yml                       |   2 -
+ pc-bios/meson.build                            |   2 -
+ pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
+ pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
+ roms/Makefile                                  |   2 -
+ target/riscv/meson.build                       |   1 +
+files changed, 1608 insertions(+), 356 deletions(-)
+ create mode 100644 linux-headers/asm-riscv/kvm.h
+ create mode 100644 target/riscv/kvm_riscv.h
+ create mode 100644 target/riscv/sbi_ecall_interface.h
+ create mode 100644 target/riscv/kvm-stub.c
+ create mode 100644 target/riscv/kvm.c
+ delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
+ delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

-New patch
+[PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+This change fixes a bug where a write only register is read.
+As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
+the 'INTR_TEST0' register is write only.
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/timer/ibex_timer.h |  1 -
+ hw/timer/ibex_timer.c         | 14 +++++---------
+files changed, 5 insertions(+), 10 deletions(-)
+diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/timer/ibex_timer.h
++++ b/include/hw/timer/ibex_timer.h
+@@ -XXX,XX +XXX,XX @@ struct IbexTimerState {
+     uint32_t timer_compare_upper0;
+     uint32_t timer_intr_enable;
+     uint32_t timer_intr_state;
+-    uint32_t timer_intr_test;
+     uint32_t timebase_freq;
+diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/ibex_timer.c
++++ b/hw/timer/ibex_timer.c
+@@ -XXX,XX +XXX,XX @@ static void ibex_timer_reset(DeviceState *dev)
+     s->timer_compare_upper0 = 0xFFFFFFFF;
+     s->timer_intr_enable = 0x00000000;
+     s->timer_intr_state = 0x00000000;
+-    s->timer_intr_test = 0x00000000;
+     ibex_timer_update_irqs(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
+         retvalue = s->timer_intr_state;
+         break;
+     case R_INTR_TEST:
+-        retvalue = s->timer_intr_test;
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "Attempted to read INTR_TEST, a write only register");
+         break;
+     default:
+         qemu_log_mask(LOG_GUEST_ERROR,
+@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
+         s->timer_intr_state &= ~val;
+         break;
+     case R_INTR_TEST:
+-        s->timer_intr_test = val;
+-        if (s->timer_intr_enable &
+-            s->timer_intr_test &
+-            R_INTR_ENABLE_IE_0_MASK) {
++        if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
+             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+             qemu_set_irq(s->irq, true);
+         }
+@@ -XXX,XX +XXX,XX @@ static int ibex_timer_post_load(void *opaque, int version_id)
+ static const VMStateDescription vmstate_ibex_timer = {
+     .name = TYPE_IBEX_TIMER,
+-    .version_id = 1,
+-    .minimum_version_id = 1,
++    .version_id = 2,
++    .minimum_version_id = 2,
+     .post_load = ibex_timer_post_load,
+     .fields = (VMStateField[]) {
+         VMSTATE_UINT32(timer_ctrl, IbexTimerState),
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ibex_timer = {
+         VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
+         VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
+         VMSTATE_UINT32(timer_intr_state, IbexTimerState),
+-        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
+         VMSTATE_END_OF_LIST()
+     }
+ };
+--
+.31.1

-New patch
+[PULL 02/61] riscv: opentitan: fixup plic stride len
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+The following change was made to rectify incorrectly set stride length
+on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
+discovered whilst attempting to fix a bug where a timer_interrupt was
+not serviced on TockOS-OpenTitan.
+[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Tested-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/opentitan.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+     qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
+-    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
++    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
+--
+.31.1

-New patch
+[PULL 03/61] hw: timer: ibex_timer: update/add reg address
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+The following changes:
+. Fixes the incorrectly set CTRL register address. As
+per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
+The CTRL register is @ 0x04.
+This was found when attempting to fixup a bug where a timer_interrupt
+was not serviced on TockOS-OpenTitan.
+. Adds ALERT_TEST register as documented on [1], adding repective
+   switch cases to error handle and later implement functionality.
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Tested-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/timer/ibex_timer.c | 11 ++++++++++-
+file changed, 10 insertions(+), 1 deletion(-)
+diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/ibex_timer.c
++++ b/hw/timer/ibex_timer.c
+@@ -XXX,XX +XXX,XX @@
+ #include "target/riscv/cpu.h"
+ #include "migration/vmstate.h"
+-REG32(CTRL, 0x00)
++REG32(ALERT_TEST, 0x00)
++    FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
++REG32(CTRL, 0x04)
+     FIELD(CTRL, ACTIVE, 0, 1)
+ REG32(CFG0, 0x100)
+     FIELD(CFG0, PRESCALE, 0, 12)
+@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
+     uint64_t retvalue = 0;
+     switch (addr >> 2) {
++    case R_ALERT_TEST:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                        "Attempted to read ALERT_TEST, a write only register");
++        break;
+     case R_CTRL:
+         retvalue = s->timer_ctrl;
+         break;
+@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
+     uint32_t val = val64;
+     switch (addr >> 2) {
++    case R_ALERT_TEST:
++        qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
++        break;
+     case R_CTRL:
+         s->timer_ctrl = val;
+         break;
+--
+.31.1

-New patch
+[PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h
+From: Yifei Jiang <jiangyifei@huawei.com>
+Add asm-riscv/kvm.h for RISC-V KVM.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-2-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ linux-headers/asm-riscv/kvm.h | 128 ++++++++++++++++++++++++++++++++++
+file changed, 128 insertions(+)
+ create mode 100644 linux-headers/asm-riscv/kvm.h
+diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/linux-headers/asm-riscv/kvm.h
+@@ -XXX,XX +XXX,XX @@
++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
++/*
++ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
++ *
++ * Authors:
++ *     Anup Patel <anup.patel@wdc.com>
++ */
++
++#ifndef __LINUX_KVM_RISCV_H
++#define __LINUX_KVM_RISCV_H
++
++#ifndef __ASSEMBLY__
++
++#include <linux/types.h>
++#include <asm/ptrace.h>
++
++#define __KVM_HAVE_READONLY_MEM
++
++#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
++
++#define KVM_INTERRUPT_SET    -1U
++#define KVM_INTERRUPT_UNSET    -2U
++
++/* for KVM_GET_REGS and KVM_SET_REGS */
++struct kvm_regs {
++};
++
++/* for KVM_GET_FPU and KVM_SET_FPU */
++struct kvm_fpu {
++};
++
++/* KVM Debug exit structure */
++struct kvm_debug_exit_arch {
++};
++
++/* for KVM_SET_GUEST_DEBUG */
++struct kvm_guest_debug_arch {
++};
++
++/* definition of registers in kvm_run */
++struct kvm_sync_regs {
++};
++
++/* for KVM_GET_SREGS and KVM_SET_SREGS */
++struct kvm_sregs {
++};
++
++/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
++struct kvm_riscv_config {
++    unsigned long isa;
++};
++
++/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
++struct kvm_riscv_core {
++    struct user_regs_struct regs;
++    unsigned long mode;
++};
++
++/* Possible privilege modes for kvm_riscv_core */
++#define KVM_RISCV_MODE_S    1
++#define KVM_RISCV_MODE_U    0
++
++/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
++struct kvm_riscv_csr {
++    unsigned long sstatus;
++    unsigned long sie;
++    unsigned long stvec;
++    unsigned long sscratch;
++    unsigned long sepc;
++    unsigned long scause;
++    unsigned long stval;
++    unsigned long sip;
++    unsigned long satp;
++    unsigned long scounteren;
++};
++
++/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
++struct kvm_riscv_timer {
++    __u64 frequency;
++    __u64 time;
++    __u64 compare;
++    __u64 state;
++};
++
++/* Possible states for kvm_riscv_timer */
++#define KVM_RISCV_TIMER_STATE_OFF    0
++#define KVM_RISCV_TIMER_STATE_ON    1
++
++#define KVM_REG_SIZE(id)        \
++    (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
++
++/* If you need to interpret the index values, here is the key: */
++#define KVM_REG_RISCV_TYPE_MASK        0x00000000FF000000
++#define KVM_REG_RISCV_TYPE_SHIFT    24
++
++/* Config registers are mapped as type 1 */
++#define KVM_REG_RISCV_CONFIG        (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_CONFIG_REG(name)    \
++    (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
++
++/* Core registers are mapped as type 2 */
++#define KVM_REG_RISCV_CORE        (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_CORE_REG(name)    \
++        (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
++
++/* Control and status registers are mapped as type 3 */
++#define KVM_REG_RISCV_CSR        (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_CSR_REG(name)    \
++        (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
++
++/* Timer registers are mapped as type 4 */
++#define KVM_REG_RISCV_TIMER        (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_TIMER_REG(name)    \
++        (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
++
++/* F extension registers are mapped as type 5 */
++#define KVM_REG_RISCV_FP_F        (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_FP_F_REG(name)    \
++        (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
++
++/* D extension registers are mapped as type 6 */
++#define KVM_REG_RISCV_FP_D        (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
++#define KVM_REG_RISCV_FP_D_REG(name)    \
++        (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
++
++#endif
++
++#endif /* __LINUX_KVM_RISCV_H */
+--
+.31.1

-New patch
+[PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
+From: Yifei Jiang <jiangyifei@huawei.com>
+Add target/riscv/kvm.c to place kvm_arch_* function needed by
+kvm/kvm-all.c.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-3-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm.c       | 133 +++++++++++++++++++++++++++++++++++++++
+ target/riscv/meson.build |   1 +
+files changed, 134 insertions(+)
+ create mode 100644 target/riscv/kvm.c
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * RISC-V implementation of KVM hooks
++ *
++ * Copyright (c) 2020 Huawei Technologies Co., Ltd
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2 or later, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "qemu/osdep.h"
++#include <sys/ioctl.h>
++
++#include <linux/kvm.h>
++
++#include "qemu-common.h"
++#include "qemu/timer.h"
++#include "qemu/error-report.h"
++#include "qemu/main-loop.h"
++#include "sysemu/sysemu.h"
++#include "sysemu/kvm.h"
++#include "sysemu/kvm_int.h"
++#include "cpu.h"
++#include "trace.h"
++#include "hw/pci/pci.h"
++#include "exec/memattrs.h"
++#include "exec/address-spaces.h"
++#include "hw/boards.h"
++#include "hw/irq.h"
++#include "qemu/log.h"
++#include "hw/loader.h"
++
++const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
++    KVM_CAP_LAST_INFO
++};
++
++int kvm_arch_get_registers(CPUState *cs)
++{
++    return 0;
++}
++
++int kvm_arch_put_registers(CPUState *cs, int level)
++{
++    return 0;
++}
++
++int kvm_arch_release_virq_post(int virq)
++{
++    return 0;
++}
++
++int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
++                             uint64_t address, uint32_t data, PCIDevice *dev)
++{
++    return 0;
++}
++
++int kvm_arch_destroy_vcpu(CPUState *cs)
++{
++    return 0;
++}
++
++unsigned long kvm_arch_vcpu_id(CPUState *cpu)
++{
++    return cpu->cpu_index;
++}
++
++void kvm_arch_init_irq_routing(KVMState *s)
++{
++}
++
++int kvm_arch_init_vcpu(CPUState *cs)
++{
++    return 0;
++}
++
++int kvm_arch_msi_data_to_gsi(uint32_t data)
++{
++    abort();
++}
++
++int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
++                                int vector, PCIDevice *dev)
++{
++    return 0;
++}
++
++int kvm_arch_init(MachineState *ms, KVMState *s)
++{
++    return 0;
++}
++
++int kvm_arch_irqchip_create(KVMState *s)
++{
++    return 0;
++}
++
++int kvm_arch_process_async_events(CPUState *cs)
++{
++    return 0;
++}
++
++void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
++{
++}
++
++MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
++{
++    return MEMTXATTRS_UNSPECIFIED;
++}
++
++bool kvm_arch_stop_on_emulation_error(CPUState *cs)
++{
++    return true;
++}
++
++int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
++{
++    return 0;
++}
++
++bool kvm_arch_cpu_check_are_resettable(void)
++{
++    return true;
++}
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+   'translate.c',
+   'm128_helper.c'
+ ))
++riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+ riscv_softmmu_ss = ss.source_set()
+ riscv_softmmu_ss.add(files(
+--
+.31.1

-New patch
+[PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu
+From: Yifei Jiang <jiangyifei@huawei.com>
+Get isa info from kvm while kvm init.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-4-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm.c | 34 +++++++++++++++++++++++++++++++++-
+file changed, 33 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/log.h"
+ #include "hw/loader.h"
++static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
++                                 uint64_t idx)
++{
++    uint64_t id = KVM_REG_RISCV | type | idx;
++
++    switch (riscv_cpu_mxl(env)) {
++    case MXL_RV32:
++        id |= KVM_REG_SIZE_U32;
++        break;
++    case MXL_RV64:
++        id |= KVM_REG_SIZE_U64;
++        break;
++    default:
++        g_assert_not_reached();
++    }
++    return id;
++}
++
+ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+     KVM_CAP_LAST_INFO
+ };
+@@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s)
+ int kvm_arch_init_vcpu(CPUState *cs)
+ {
+-    return 0;
++    int ret = 0;
++    target_ulong isa;
++    RISCVCPU *cpu = RISCV_CPU(cs);
++    CPURISCVState *env = &cpu->env;
++    uint64_t id;
++
++    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
++                          KVM_REG_RISCV_CONFIG_REG(isa));
++    ret = kvm_get_one_reg(cs, id, &isa);
++    if (ret) {
++        return ret;
++    }
++    env->misa_ext = isa;
++
++    return ret;
+ }
+ int kvm_arch_msi_data_to_gsi(uint32_t data)
+--
+.31.1

-New patch
+[PULL 07/61] target/riscv: Implement kvm_arch_get_registers
+From: Yifei Jiang <jiangyifei@huawei.com>
+Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-5-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm.c | 112 ++++++++++++++++++++++++++++++++++++++++++++-
+file changed, 111 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+     return id;
+ }
++#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
++                 KVM_REG_RISCV_CORE_REG(name))
++
++#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
++                 KVM_REG_RISCV_CSR_REG(name))
++
++#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
++
++#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
++
++#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
++    do { \
++        int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
++        if (ret) { \
++            return ret; \
++        } \
++    } while (0)
++
++static int kvm_riscv_get_regs_core(CPUState *cs)
++{
++    int ret = 0;
++    int i;
++    target_ulong reg;
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
++
++    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
++    if (ret) {
++        return ret;
++    }
++    env->pc = reg;
++
++    for (i = 1; i < 32; i++) {
++        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
++        ret = kvm_get_one_reg(cs, id, &reg);
++        if (ret) {
++            return ret;
++        }
++        env->gpr[i] = reg;
++    }
++
++    return ret;
++}
++
++static int kvm_riscv_get_regs_csr(CPUState *cs)
++{
++    int ret = 0;
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
++
++    KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
++    KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
++    KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
++    KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
++    KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
++    KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
++    KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
++    KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
++    KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
++    return ret;
++}
++
++static int kvm_riscv_get_regs_fp(CPUState *cs)
++{
++    int ret = 0;
++    int i;
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
++
++    if (riscv_has_ext(env, RVD)) {
++        uint64_t reg;
++        for (i = 0; i < 32; i++) {
++            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
++            if (ret) {
++                return ret;
++            }
++            env->fpr[i] = reg;
++        }
++        return ret;
++    }
++
++    if (riscv_has_ext(env, RVF)) {
++        uint32_t reg;
++        for (i = 0; i < 32; i++) {
++            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
++            if (ret) {
++                return ret;
++            }
++            env->fpr[i] = reg;
++        }
++        return ret;
++    }
++
++    return ret;
++}
++
+ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+     KVM_CAP_LAST_INFO
+ };
+ int kvm_arch_get_registers(CPUState *cs)
+ {
+-    return 0;
++    int ret = 0;
++
++    ret = kvm_riscv_get_regs_core(cs);
++    if (ret) {
++        return ret;
++    }
++
++    ret = kvm_riscv_get_regs_csr(cs);
++    if (ret) {
++        return ret;
++    }
++
++    ret = kvm_riscv_get_regs_fp(cs);
++    if (ret) {
++        return ret;
++    }
++
++    return ret;
+ }
+ int kvm_arch_put_registers(CPUState *cs, int level)
+--
+.31.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 08/61] target/riscv: Implement kvm_arch_put_registers
-From: Jim Shu <cwshu@andestech.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
 Fix it by propagating PMP permission to TLB page permission.
-PMP permission checking also use MMU-style API to change TLB permission
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-and size.
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
 Signed-off-by: Jim Shu <cwshu@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
 Message-id: 20220112081329.1835-6-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/kvm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++-
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+file changed, 103 insertions(+), 1 deletion(-)
  target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 files changed, 125 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
+--- a/target/riscv/kvm.c
-+++ b/target/riscv/pmp.h
++++ b/target/riscv/kvm.c
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-     target_ulong val);
+         } \
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+     } while (0)
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
++#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
++    do { \
-+    target_ulong mode);
++        int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
++        if (ret) { \
-                          target_ulong *tlb_size);
++            return ret; \
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
++        } \
- void pmp_update_rule_nums(CPURISCVState *env);
++    } while (0)
- uint32_t pmp_get_num_rules(CPURISCVState *env);
++
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
+ static int kvm_riscv_get_regs_core(CPUState *cs)
+ {
- #endif
+     int ret = 0;
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_core(CPUState *cs)
-index XXXXXXX..XXXXXXX 100644
+     return ret;
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
      env->load_res = -1;
  }
-+/*
++static int kvm_riscv_put_regs_core(CPUState *cs)
 + * get_physical_address_pmp - check PMP permission for this physical address
 + *
 + * Match the PMP region and check permission for this physical address and it's
 + * TLB page. Returns 0 if the permission checking was successful
 + *
 + * @env: CPURISCVState
 + * @prot: The returned protection attributes
 + * @tlb_size: TLB page size containing addr. It could be modified after PMP
 + *            permission checking. NULL if not set TLB page for addr.
 + * @addr: The physical address to be checked permission
 + * @access_type: The type of MMU access
 + * @mode: Indicates current privilege level.
 + */
 +static int get_physical_address_pmp(CPURISCVState *env, int *prot,
 +                                    target_ulong *tlb_size, hwaddr addr,
 +                                    int size, MMUAccessType access_type,
 +                                    int mode)
 +{
-+    pmp_priv_t pmp_priv;
++    int ret = 0;
-+    target_ulong tlb_size_pmp = 0;
++    int i;
 +    target_ulong reg;
 +    CPURISCVState *env = &RISCV_CPU(cs)->env;
 +
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
++    reg = env->pc;
-+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
++    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
-+        return TRANSLATE_SUCCESS;
++    if (ret) {
 +        return ret;
 +    }
 +
-+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
++    for (i = 1; i < 32; i++) {
-+                            mode)) {
++        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
-+        *prot = 0;
++        reg = env->gpr[i];
-+        return TRANSLATE_PMP_FAIL;
++        ret = kvm_set_one_reg(cs, id, &reg);
-+    }
++        if (ret) {
-+
++            return ret;
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
-+    }
-+
-+    return TRANSLATE_SUCCESS;
-+}
-+
- /* get_physical_address - get the physical address for this virtual address
-  *
-  * Do a page table walk to obtain the physical address corresponding to a
-@@ -XXX,XX +XXX,XX @@ restart:
-             pte_addr = base + idx * ptesize;
-         }
--        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
--            1 << MMU_DATA_LOAD, PRV_S)) {
-+        int pmp_prot;
-+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
-+                                               sizeof(target_ulong),
-+                                               MMU_DATA_LOAD, PRV_S);
-+        if (pmp_ret != TRANSLATE_SUCCESS) {
-             return TRANSLATE_PMP_FAIL;
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- #ifndef CONFIG_USER_ONLY
-     vaddr im_address;
-     hwaddr pa = 0;
--    int prot, prot2;
-+    int prot, prot2, prot_pmp;
-     bool pmp_violation = false;
-     bool first_stage_error = true;
-     bool two_stage_lookup = false;
-     int ret = TRANSLATE_FAIL;
-     int mode = mmu_idx;
--    target_ulong tlb_size = 0;
-+    /* default TLB page size */
-+    target_ulong tlb_size = TARGET_PAGE_SIZE;
-     env->guest_phys_fault_addr = 0;
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             prot &= prot2;
--            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--                (ret == TRANSLATE_SUCCESS) &&
--                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--                ret = TRANSLATE_PMP_FAIL;
-+            if (ret == TRANSLATE_SUCCESS) {
-+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                               size, access_type, mode);
-+                prot &= prot_pmp;
-             }
-             if (ret != TRANSLATE_SUCCESS) {
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                       "%s address=%" VADDR_PRIx " ret %d physical "
-                       TARGET_FMT_plx " prot %d\n",
-                       __func__, address, ret, pa, prot);
--    }
--    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--        (ret == TRANSLATE_SUCCESS) &&
--        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--        ret = TRANSLATE_PMP_FAIL;
-+        if (ret == TRANSLATE_SUCCESS) {
-+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                           size, access_type, mode);
-+            prot &= prot_pmp;
-+        }
-     }
-+
-     if (ret == TRANSLATE_PMP_FAIL) {
-         pmp_violation = true;
-     }
-     if (ret == TRANSLATE_SUCCESS) {
--        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
--            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
--                         prot, mmu_idx, tlb_size);
--        } else {
--            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--                         prot, mmu_idx, TARGET_PAGE_SIZE);
--        }
-+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-+                     prot, mmu_idx, tlb_size);
-         return true;
-     } else if (probe) {
-         return false;
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
-     return result;
- }
-+/*
-+ * Check if the address has required RWX privs when no PMP entry is matched.
-+ */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode)
-+{
-+    bool ret;
-+
-+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-+        /*
-+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
-+         * or no PMP entry matches an M-Mode access, the access succeeds.
-+         */
-+        ret = true;
-+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-+    } else {
-+        /*
-+         * Other modes are not allowed to succeed if they don't * match a rule,
-+         * but there are rules. We've checked for no rule earlier in this
-+         * function.
-+         */
-+        ret = false;
-+        *allowed_privs = 0;
 +    }
 +
 +    return ret;
 +}
 +
+ static int kvm_riscv_get_regs_csr(CPUState *cs)
  /*
   * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
   * Check if the address has required RWX privs to complete desired operation
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
-     int i = 0;
+     int ret = 0;
-     int ret = -1;
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
-     int pmp_size = 0;
+     return ret;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
      /* No rule matched */
      if (ret == -1) {
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
--
++static int kvm_riscv_put_regs_csr(CPUState *cs)
- /*
++{
-  * Handle a write to a pmpcfg CSP
++    int ret = 0;
-  */
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
++
++    KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
-     return false;
++    KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
 +    KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
 +    KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
 +    KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
 +    KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
 +    KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
 +    KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
 +    KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
 +
 +    return ret;
 +}
 +
  static int kvm_riscv_get_regs_fp(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
      return ret;
  }
++static int kvm_riscv_put_regs_fp(CPUState *cs)
++{
++    int ret = 0;
++    int i;
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
 +
-+/*
++    if (riscv_has_ext(env, RVD)) {
-+ * Convert PMP privilege to TLB page privilege.
++        uint64_t reg;
-+ */
++        for (i = 0; i < 32; i++) {
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
++            reg = env->fpr[i];
-+{
++            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
-+    int prot = 0;
++            if (ret) {
-+
++                return ret;
-+    if (pmp_priv & PMP_READ) {
++            }
-+        prot |= PAGE_READ;
++        }
-+    }
++        return ret;
 +    if (pmp_priv & PMP_WRITE) {
 +        prot |= PAGE_WRITE;
 +    }
 +    if (pmp_priv & PMP_EXEC) {
 +        prot |= PAGE_EXEC;
 +    }
 +
-+    return prot;
++    if (riscv_has_ext(env, RVF)) {
 +        uint32_t reg;
 +        for (i = 0; i < 32; i++) {
 +            reg = env->fpr[i];
 +            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
 +            if (ret) {
 +                return ret;
 +            }
 +        }
 +        return ret;
 +    }
 +
 +    return ret;
 +}
++
++
+ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+     KVM_CAP_LAST_INFO
+ };
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
+ int kvm_arch_put_registers(CPUState *cs, int level)
+ {
+-    return 0;
++    int ret = 0;
++
++    ret = kvm_riscv_put_regs_core(cs);
++    if (ret) {
++        return ret;
++    }
++
++    ret = kvm_riscv_put_regs_csr(cs);
++    if (ret) {
++        return ret;
++    }
++
++    ret = kvm_riscv_put_regs_fp(cs);
++    if (ret) {
++        return ret;
++    }
++
++    return ret;
+ }
+ int kvm_arch_release_virq_post(int virq)
 --
-.30.1
+.31.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+[PULL 09/61] target/riscv: Support start kernel directly by KVM
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Yifei Jiang <jiangyifei@huawei.com>
-Allow ramfb on virt.  This lets `-device ramfb' work.
+Get kernel and fdt start address in virt.c, and pass them to KVM
+when cpu reset. Add kvm_riscv.h to place riscv specific interface.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+In addition, PLIC is created without M-mode PLIC contexts when KVM
 is enabled.
 Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Mingwang Li <limingwang@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
+Reviewed-by: Anup Patel <anup@brainfault.org>
 Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 3 +++
+ include/hw/riscv/boot.h  |  1 +
-file changed, 3 insertions(+)
+ target/riscv/cpu.h       |  3 ++
+ target/riscv/kvm_riscv.h | 24 ++++++++++++
  hw/intc/sifive_plic.c    | 20 +++++++---
  hw/riscv/boot.c          | 16 +++++++-
  hw/riscv/virt.c          | 83 ++++++++++++++++++++++++++++------------
  target/riscv/cpu.c       |  8 ++++
  target/riscv/kvm-stub.c  | 25 ++++++++++++
  target/riscv/kvm.c       | 14 +++++++
  target/riscv/meson.build |  2 +-
 files changed, 164 insertions(+), 32 deletions(-)
  create mode 100644 target/riscv/kvm_riscv.h
  create mode 100644 target/riscv/kvm-stub.c
 diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/boot.h
 +++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
                                    hwaddr rom_size,
                                    uint32_t reset_vec_size,
                                    uint64_t kernel_entry);
 +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
  #endif /* RISCV_BOOT_H */
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
      /* Fields from here on are preserved across CPU reset. */
      QEMUTimer *timer; /* Internal timer */
 +
 +    hwaddr kernel_addr;
 +    hwaddr fdt_addr;
  };
  OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
 diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU KVM support -- RISC-V specific functions.
 + *
 + * Copyright (c) 2020 Huawei Technologies Co., Ltd
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef QEMU_KVM_RISCV_H
 +#define QEMU_KVM_RISCV_H
 +
 +void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 +
 +#endif
 diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/sifive_plic.c
 +++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
  #include "target/riscv/cpu.h"
  #include "migration/vmstate.h"
  #include "hw/irq.h"
 +#include "sysemu/kvm.h"
  static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
  {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
      uint32_t context_stride, uint32_t aperture_size)
  {
      DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
 -    int i;
 +    int i, j = 0;
 +    SiFivePLICState *plic;
      assert(enable_stride == (enable_stride & -enable_stride));
      assert(context_stride == (context_stride & -context_stride));
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 +    plic = SIFIVE_PLIC(dev);
      for (i = 0; i < num_harts; i++) {
          CPUState *cpu = qemu_get_cpu(hartid_base + i);
 -        qdev_connect_gpio_out(dev, i,
 -                              qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
 -        qdev_connect_gpio_out(dev, num_harts + i,
 -                              qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
 +        if (plic->addr_config[j].mode == PLICMode_M) {
 +            j++;
 +            qdev_connect_gpio_out(dev, num_harts + i,
 +                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
 +        }
 +
 +        if (plic->addr_config[j].mode == PLICMode_S) {
 +            j++;
 +            qdev_connect_gpio_out(dev, i,
 +                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
 +        }
      }
      return dev;
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
  #include "elf.h"
  #include "sysemu/device_tree.h"
  #include "sysemu/qtest.h"
 +#include "sysemu/kvm.h"
  #include <libfdt.h>
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
          CPUState *cs = qemu_get_cpu(i);
          CPURISCVState *env = &RISCV_CPU(cs)->env;
 -        if (riscv_has_ext(env, RVS)) {
 +        if (kvm_enabled()) {
 +            vals[i] = "S";
 +        } else if (riscv_has_ext(env, RVS)) {
              vals[i] = "MS";
          } else {
              vals[i] = "M";
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
      return;
  }
 +
 +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
 +{
 +    CPUState *cs;
 +
 +    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
 +        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
 +        riscv_cpu->env.kernel_addr = kernel_addr;
 +        riscv_cpu->env.fdt_addr = fdt_addr;
 +    }
 +}
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
 @@ -XXX,XX +XXX,XX @@
+ #include "chardev/char.h"
+ #include "sysemu/device_tree.h"
  #include "sysemu/sysemu.h"
++#include "sysemu/kvm.h"
  #include "hw/pci/pci.h"
  #include "hw/pci-host/gpex.h"
-+#include "hw/display/ramfb.h"
+ #include "hw/display/ramfb.h"
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
- static const MemMapEntry virt_memmap[] = {
+         "sifive,plic-1.0.0", "riscv,plic0"
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
+     };
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+-    plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
++    if (kvm_enabled()) {
-     mc->numa_mem_supported = true;
++        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
-+
++    } else {
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
++        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 +    }
      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
 -        plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
 -        plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 -        plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
 -        plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 +        if (kvm_enabled()) {
 +            plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
 +        } else {
 +            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 +            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
 +            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 +        }
      }
      plic_phandles[socket] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          create_fdt_socket_memory(s, memmap, socket);
 -        if (s->have_aclint) {
 -            create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
 -        } else {
 -            create_fdt_socket_clint(s, memmap, socket, intc_phandles);
 +        if (!kvm_enabled()) {
 +            if (s->have_aclint) {
 +                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
 +            } else {
 +                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
 +            }
          }
          create_fdt_socket_plic(s, memmap, socket, phandle,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                  hart_count, &error_abort);
          sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 -        /* Per-socket CLINT */
 -        riscv_aclint_swi_create(
 -            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 -            base_hartid, hart_count, false);
 -        riscv_aclint_mtimer_create(
 -            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
 -                RISCV_ACLINT_SWI_SIZE,
 -            RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 -            RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 -            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 -
 -        /* Per-socket ACLINT SSWI */
 -        if (s->have_aclint) {
 +        if (!kvm_enabled()) {
 +            /* Per-socket CLINT */
              riscv_aclint_swi_create(
 -                memmap[VIRT_ACLINT_SSWI].base +
 -                    i * memmap[VIRT_ACLINT_SSWI].size,
 -                base_hartid, hart_count, true);
 +                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 +                base_hartid, hart_count, false);
 +            riscv_aclint_mtimer_create(
 +                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
 +                    RISCV_ACLINT_SWI_SIZE,
 +                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 +                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 +                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
 +
 +            /* Per-socket ACLINT SSWI */
 +            if (s->have_aclint) {
 +                riscv_aclint_swi_create(
 +                    memmap[VIRT_ACLINT_SSWI].base +
 +                        i * memmap[VIRT_ACLINT_SSWI].size,
 +                    base_hartid, hart_count, true);
 +            }
          }
          /* Per-socket PLIC hart topology configuration string */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                  mask_rom);
 +    /*
 +     * Only direct boot kernel is currently supported for KVM VM,
 +     * so the "-bios" parameter is ignored and treated like "-bios none"
 +     * when KVM is enabled.
 +     */
 +    if (kvm_enabled()) {
 +        g_free(machine->firmware);
 +        machine->firmware = g_strdup("none");
 +    }
 +
      if (riscv_is_32bit(&s->soc[0])) {
          firmware_end_addr = riscv_find_and_load_firmware(machine,
                                      RISCV32_BIOS_BIN, start_addr, NULL);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                virt_memmap[VIRT_MROM].size, kernel_entry,
                                fdt_load_addr, machine->fdt);
 +    /*
 +     * Only direct boot kernel is currently supported for KVM VM,
 +     * So here setup kernel start address and fdt address.
 +     * TODO:Support firmware loading and integrate to TCG start
 +     */
 +    if (kvm_enabled()) {
 +        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
 +    }
 +
      /* SiFive Test MMIO device */
      sifive_test_create(memmap[VIRT_TEST].base);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
  #include "fpu/softfloat-helpers.h"
 +#include "sysemu/kvm.h"
 +#include "kvm_riscv.h"
  /* RISC-V CPU definitions */
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      cs->exception_index = RISCV_EXCP_NONE;
      env->load_res = -1;
      set_default_nan_mode(1, &env->fp_status);
 +
 +#ifndef CONFIG_USER_ONLY
 +    if (kvm_enabled()) {
 +        kvm_riscv_reset_vcpu(cpu);
 +    }
 +#endif
  }
- static const TypeInfo virt_machine_typeinfo = {
+ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU KVM RISC-V specific function stubs
 + *
 + * Copyright (c) 2020 Huawei Technologies Co., Ltd
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "kvm_riscv.h"
 +
 +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 +{
 +    abort();
 +}
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/irq.h"
  #include "qemu/log.h"
  #include "hw/loader.h"
 +#include "kvm_riscv.h"
  static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                   uint64_t idx)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
      return 0;
  }
 +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 +{
 +    CPURISCVState *env = &cpu->env;
 +
 +    if (!kvm_enabled()) {
 +        return;
 +    }
 +    env->pc = cpu->env.kernel_addr;
 +    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
 +    env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
 +    env->satp = 0;
 +}
 +
  bool kvm_arch_cpu_check_are_resettable(void)
  {
      return true;
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
    'translate.c',
    'm128_helper.c'
  ))
 -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
  riscv_softmmu_ss = ss.source_set()
  riscv_softmmu_ss.add(files(
 --
-.30.1
+.31.1

-New patch
+[PULL 10/61] target/riscv: Support setting external interrupt by KVM
+From: Yifei Jiang <jiangyifei@huawei.com>
+When KVM is enabled, set the S-mode external interrupt through
+kvm_riscv_set_irq function.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-8-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm_riscv.h |  1 +
+ target/riscv/cpu.c       |  6 +++++-
+ target/riscv/kvm-stub.c  |  5 +++++
+ target/riscv/kvm.c       | 17 +++++++++++++++++
+files changed, 28 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm_riscv.h
++++ b/target/riscv/kvm_riscv.h
+@@ -XXX,XX +XXX,XX @@
+ #define QEMU_KVM_RISCV_H
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
++void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
+ #endif
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
+     case IRQ_S_EXT:
+     case IRQ_VS_EXT:
+     case IRQ_M_EXT:
+-        riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
++        if (kvm_enabled()) {
++            kvm_riscv_set_irq(cpu, irq, level);
++        } else {
++            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
++        }
+         break;
+     default:
+         g_assert_not_reached();
+diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm-stub.c
++++ b/target/riscv/kvm-stub.c
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+ {
+     abort();
+ }
++
++void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
++{
++    abort();
++}
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+     env->satp = 0;
+ }
++void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
++{
++    int ret;
++    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
++
++    if (irq != IRQ_S_EXT) {
++        perror("kvm riscv set irq != IRQ_S_EXT\n");
++        abort();
++    }
++
++    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
++    if (ret < 0) {
++        perror("Set irq failed");
++        abort();
++    }
++}
++
+ bool kvm_arch_cpu_check_are_resettable(void)
+ {
+     return true;
+--
+.31.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
-From: Bin Meng <bin.meng@windriver.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-This adds the documentation to describe what is supported for the
+Use char-fe to handle console sbi call, which implement early
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+console io while apply 'earlycon=sbi' into kernel parameters.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Mingwang Li <limingwang@huawei.com>
 Reviewed-by: Anup Patel <anup.patel@wdc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
- docs/system/target-riscv.rst               |  1 +
+ target/riscv/kvm.c                 | 42 ++++++++++++++++-
-files changed, 90 insertions(+)
+files changed, 113 insertions(+), 1 deletion(-)
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ create mode 100644 target/riscv/sbi_ecall_interface.h
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
++++ b/target/riscv/sbi_ecall_interface.h
 @@ -XXX,XX +XXX,XX @@
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
++/*
-+=============================================================
++ * SPDX-License-Identifier: BSD-2-Clause
 + *
 + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
 + *
 + * Authors:
 + *   Anup Patel <anup.patel@wdc.com>
 + */
 +
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
++#ifndef __SBI_ECALL_INTERFACE_H__
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
++#define __SBI_ECALL_INTERFACE_H__
 +
-+For more details about Microchip PolarFire SoC, please see:
++/* clang-format off */
 +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
 +
-+The Icicle Kit board information can be found here:
++/* SBI Extension IDs */
-+https://www.microsemi.com/existing-parts/parts/152514
++#define SBI_EXT_0_1_SET_TIMER           0x0
 +#define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
 +#define SBI_EXT_0_1_CONSOLE_GETCHAR     0x2
 +#define SBI_EXT_0_1_CLEAR_IPI           0x3
 +#define SBI_EXT_0_1_SEND_IPI            0x4
 +#define SBI_EXT_0_1_REMOTE_FENCE_I      0x5
 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
 +#define SBI_EXT_0_1_SHUTDOWN            0x8
 +#define SBI_EXT_BASE                    0x10
 +#define SBI_EXT_TIME                    0x54494D45
 +#define SBI_EXT_IPI                     0x735049
 +#define SBI_EXT_RFENCE                  0x52464E43
 +#define SBI_EXT_HSM                     0x48534D
 +
-+Supported devices
++/* SBI function IDs for BASE extension*/
-+-----------------
++#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
 +#define SBI_EXT_BASE_GET_IMP_ID         0x1
 +#define SBI_EXT_BASE_GET_IMP_VERSION    0x2
 +#define SBI_EXT_BASE_PROBE_EXT          0x3
 +#define SBI_EXT_BASE_GET_MVENDORID      0x4
 +#define SBI_EXT_BASE_GET_MARCHID        0x5
 +#define SBI_EXT_BASE_GET_MIMPID         0x6
 +
-+The ``microchip-icicle-kit`` machine supports the following devices:
++/* SBI function IDs for TIME extension*/
 +#define SBI_EXT_TIME_SET_TIMER          0x0
 +
-+ * 1 E51 core
++/* SBI function IDs for IPI extension*/
-+ * 4 U54 cores
++#define SBI_EXT_IPI_SEND_IPI            0x0
 + * Core Level Interruptor (CLINT)
 + * Platform-Level Interrupt Controller (PLIC)
 + * L2 Loosely Integrated Memory (L2-LIM)
 + * DDR memory controller
 + * 5 MMUARTs
 + * 1 DMA controller
 + * 2 GEM Ethernet controllers
 + * 1 SDHC storage controller
 +
-+Boot options
++/* SBI function IDs for RFENCE extension*/
-+------------
++#define SBI_EXT_RFENCE_REMOTE_FENCE_I       0x0
 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA    0x1
 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID  0x2
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x3
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x5
 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
 +
-+The ``microchip-icicle-kit`` machine can start using the standard -bios
++/* SBI function IDs for HSM extension */
-+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
++#define SBI_EXT_HSM_HART_START          0x0
-+HSS loads the second stage bootloader U-Boot from an SD card. It does not
++#define SBI_EXT_HSM_HART_STOP           0x1
-+support direct kernel loading via the -kernel option. One has to load kernel
++#define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +from U-Boot.
 +
-+The memory is set to 1537 MiB by default which is the minimum required high
++#define SBI_HSM_HART_STATUS_STARTED     0x0
-+memory size by HSS. A sanity check on ram size is performed in the machine
++#define SBI_HSM_HART_STATUS_STOPPED     0x1
-+init routine to prompt user to increase the RAM size to > 1537 MiB when less
++#define SBI_HSM_HART_STATUS_START_PENDING   0x2
-+than 1537 MiB ram is detected.
++#define SBI_HSM_HART_STATUS_STOP_PENDING    0x3
 +
-+Boot the machine
++#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
-+----------------
++#define SBI_SPEC_VERSION_MAJOR_MASK     0x7f
 +#define SBI_SPEC_VERSION_MINOR_MASK     0xffffff
 +#define SBI_EXT_VENDOR_START            0x09000000
 +#define SBI_EXT_VENDOR_END              0x09FFFFFF
 +/* clang-format on */
 +
-+HSS 2020.12 release is tested at the time of writing. To build an HSS image
++#endif
-+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
-+in the HSS source tree:
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/log.h"
  #include "hw/loader.h"
  #include "kvm_riscv.h"
 +#include "sbi_ecall_interface.h"
 +#include "chardev/char-fe.h"
  static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                   uint64_t idx)
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 +{
 +    int ret = 0;
 +    unsigned char ch;
 +    switch (run->riscv_sbi.extension_id) {
 +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
 +        ch = run->riscv_sbi.args[0];
 +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +        break;
 +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
 +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
 +        if (ret == sizeof(ch)) {
 +            run->riscv_sbi.args[0] = ch;
 +        } else {
 +            run->riscv_sbi.args[0] = -1;
 +        }
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 +                      __func__, run->riscv_sbi.extension_id);
 +        ret = -1;
 +        break;
 +    }
 +    return ret;
 +}
 +
-+.. code-block:: bash
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-+
+ {
-+  $ export CROSS_COMPILE=riscv64-linux-
+-    return 0;
-+  $ cp boards/mpfs-icicle-kit-es/def_config .config
++    int ret = 0;
-+  $ make BOARD=mpfs-icicle-kit-es
++    switch (run->exit_reason) {
-+
++    case KVM_EXIT_RISCV_SBI:
-+Download the official SD card image released by Microchip and prepare it for
++        ret = kvm_riscv_handle_sbi(cs, run);
-+QEMU usage:
++        break;
-+
++    default:
-+.. code-block:: bash
++        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-+
++                      __func__, run->exit_reason);
-+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++        ret = -1;
-+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++        break;
-+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
++    }
-+
++    return ret;
-+Then we can boot the machine by:
+ }
-+
-+.. code-block:: bash
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 +
 +  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
 +      -bios path/to/hss.bin -sd path/to/sdcard.img \
 +      -nic user,model=cadence_gem \
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
 +      -serial chardev:serial1
 +
 +With above command line, current terminal session will be used for the first
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
 +  $ minicom -D unix\#serial1.sock
 +
 +HSS output is on the first serial port (stdio) and U-Boot outputs on the
 +second serial port. U-Boot will automatically load the Linux kernel from
 +the SD card image.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/target-riscv.rst
 +++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
  .. toctree::
     :maxdepth: 1
 +   riscv/microchip-icicle-kit
     riscv/sifive_u
  RISC-V CPU features
 --
-.30.1
+.31.1

-New patch
+[PULL 12/61] target/riscv: Add host cpu type
+From: Yifei Jiang <jiangyifei@huawei.com>
+'host' type cpu is set isa to RV32 or RV64 simply, more isa info
+will obtain from KVM in kvm_arch_init_vcpu()
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h |  1 +
+ target/riscv/cpu.c | 15 +++++++++++++++
+files changed, 16 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
+ #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
+ #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
++#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
+ #if defined(TARGET_RISCV32)
+ # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
+ }
+ #endif
++#if defined(CONFIG_KVM)
++static void riscv_host_cpu_init(Object *obj)
++{
++    CPURISCVState *env = &RISCV_CPU(obj)->env;
++#if defined(TARGET_RISCV32)
++    set_misa(env, MXL_RV32, 0);
++#elif defined(TARGET_RISCV64)
++    set_misa(env, MXL_RV64, 0);
++#endif
++}
++#endif
++
+ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
+ {
+     ObjectClass *oc;
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
+         .class_init = riscv_cpu_class_init,
+     },
+     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
++#if defined(CONFIG_KVM)
++    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
++#endif
+ #if defined(TARGET_RISCV32)
+     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
+     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
+--
+.31.1

-New patch
+[PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer
+From: Yifei Jiang <jiangyifei@huawei.com>
+Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
+from KVM.
+To set register of RISCV_TIMER_REG(state) will occur a error from KVM
+on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
+that adaping in QEMU.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h |  7 +++++
+ target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
+files changed, 79 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     hwaddr kernel_addr;
+     hwaddr fdt_addr;
++
++    /* kvm timer */
++    bool kvm_timer_dirty;
++    uint64_t kvm_timer_time;
++    uint64_t kvm_timer_compare;
++    uint64_t kvm_timer_state;
++    uint64_t kvm_timer_frequency;
+ };
+ OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "kvm_riscv.h"
+ #include "sbi_ecall_interface.h"
+ #include "chardev/char-fe.h"
++#include "migration/migration.h"
+ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+                                  uint64_t idx)
+@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+ #define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
+                  KVM_REG_RISCV_CSR_REG(name))
++#define RISCV_TIMER_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
++                 KVM_REG_RISCV_TIMER_REG(name))
++
+ #define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
+ #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
+@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+         } \
+     } while (0)
++#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
++    do { \
++        int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
++        if (ret) { \
++            abort(); \
++        } \
++    } while (0)
++
++#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
++    do { \
++        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
++        if (ret) { \
++            abort(); \
++        } \
++    } while (0)
++
+ static int kvm_riscv_get_regs_core(CPUState *cs)
+ {
+     int ret = 0;
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
+     return ret;
+ }
++static void kvm_riscv_get_regs_timer(CPUState *cs)
++{
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
++
++    if (env->kvm_timer_dirty) {
++        return;
++    }
++
++    KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
++    KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
++    KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
++    KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
++
++    env->kvm_timer_dirty = true;
++}
++
++static void kvm_riscv_put_regs_timer(CPUState *cs)
++{
++    uint64_t reg;
++    CPURISCVState *env = &RISCV_CPU(cs)->env;
++
++    if (!env->kvm_timer_dirty) {
++        return;
++    }
++
++    KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
++    KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
++
++    /*
++     * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
++     * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
++     * doesn't matter that adaping in QEMU now.
++     * TODO If KVM changes, adapt here.
++     */
++    if (env->kvm_timer_state) {
++        KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
++    }
++
++    /*
++     * For now, migration will not work between Hosts with different timer
++     * frequency. Therefore, we should check whether they are the same here
++     * during the migration.
++     */
++    if (migration_is_running(migrate_get_current()->state)) {
++        KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
++        if (reg != env->kvm_timer_frequency) {
++            error_report("Dst Hosts timer frequency != Src Hosts");
++        }
++    }
++
++    env->kvm_timer_dirty = false;
++}
+ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+     KVM_CAP_LAST_INFO
+--
+.31.1

-New patch
+[PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing
+From: Yifei Jiang <jiangyifei@huawei.com>
+We hope that virtual time adjusts with vm state changing. When a vm
+is stopped, guest virtual time should stop counting and kvm_timer
+should be stopped. When the vm is resumed, guest virtual time should
+continue to count and kvm_timer should be restored.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220112081329.1835-12-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm.c | 15 +++++++++++++++
+file changed, 15 insertions(+)
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sbi_ecall_interface.h"
+ #include "chardev/char-fe.h"
+ #include "migration/migration.h"
++#include "sysemu/runstate.h"
+ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+                                  uint64_t idx)
+@@ -XXX,XX +XXX,XX @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+     return cpu->cpu_index;
+ }
++static void kvm_riscv_vm_state_change(void *opaque, bool running,
++                                      RunState state)
++{
++    CPUState *cs = opaque;
++
++    if (running) {
++        kvm_riscv_put_regs_timer(cs);
++    } else {
++        kvm_riscv_get_regs_timer(cs);
++    }
++}
++
+ void kvm_arch_init_irq_routing(KVMState *s)
+ {
+ }
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
+     CPURISCVState *env = &cpu->env;
+     uint64_t id;
++    qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
++
+     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+                           KVM_REG_RISCV_CONFIG_REG(isa));
+     ret = kvm_get_one_reg(cs, id, &isa);
+--
+.31.1

-New patch
+[PULL 15/61] target/riscv: Support virtual time context synchronization
+From: Yifei Jiang <jiangyifei@huawei.com>
+Add virtual time context description to vmstate_kvmtimer. After cpu being
+loaded, virtual time context is updated to KVM.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Anup Patel <anup.patel@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
+file changed, 30 insertions(+)
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/machine.c
++++ b/target/riscv/machine.c
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_rv128 = {
+     }
+ };
++static bool kvmtimer_needed(void *opaque)
++{
++    return kvm_enabled();
++}
++
++static int cpu_post_load(void *opaque, int version_id)
++{
++    RISCVCPU *cpu = opaque;
++    CPURISCVState *env = &cpu->env;
++
++    env->kvm_timer_dirty = true;
++    return 0;
++}
++
++static const VMStateDescription vmstate_kvmtimer = {
++    .name = "cpu/kvmtimer",
++    .version_id = 1,
++    .minimum_version_id = 1,
++    .needed = kvmtimer_needed,
++    .post_load = cpu_post_load,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
++        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
++        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
++
++        VMSTATE_END_OF_LIST()
++    }
++};
++
+ const VMStateDescription vmstate_riscv_cpu = {
+     .name = "cpu",
+     .version_id = 3,
+@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
+         &vmstate_vector,
+         &vmstate_pointermasking,
+         &vmstate_rv128,
++        &vmstate_kvmtimer,
+         NULL
+     }
+ };
+--
+.31.1

-New patch
+[PULL 16/61] target/riscv: enable riscv kvm accel
+From: Yifei Jiang <jiangyifei@huawei.com>
+Add riscv kvm support in meson.build file.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Mingwang Li <limingwang@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Anup Patel <anup@brainfault.org>
+Message-id: 20220112081329.1835-14-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ meson.build | 2 ++
+file changed, 2 insertions(+)
+diff --git a/meson.build b/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/meson.build
++++ b/meson.build
+@@ -XXX,XX +XXX,XX @@ elif cpu in ['ppc', 'ppc64']
+   kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
+ elif cpu in ['mips', 'mips64']
+   kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
++elif cpu in ['riscv']
++  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
+ else
+   kvm_targets = []
+ endif
+--
+.31.1

-New patch
+[PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers
+From: Thomas Huth <thuth@redhat.com>
+If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
+complains:
+.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
+.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
+ in this function [-Werror=maybe-uninitialized]
+     int namelen, retval;
+                  ^~~~~~
+It's a false warning since the while loop is always executed at least
+once (p has to be non-NULL, otherwise the derefence in the if-statement
+earlier will crash). Thus let's switch to a do-while loop here instead
+to make the compiler happy in all cases.
+Signed-off-by: Thomas Huth <thuth@redhat.com>
+Reviewed-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Message-id: 20220107133844.145039-1-thuth@redhat.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ softmmu/device_tree.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
+index XXXXXXX..XXXXXXX 100644
+--- a/softmmu/device_tree.c
++++ b/softmmu/device_tree.c
+@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
+         return -1;
+     }
+-    while (p) {
++    do {
+         name = p + 1;
+         p = strchr(name, '/');
+         namelen = p != NULL ? p - name : strlen(name);
+@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
+         }
+         parent = retval;
+-    }
++    } while (p);
+     return retval;
+ }
+--
+.31.1

-New patch
+[PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment
+From: Yanan Wang <wangyanan55@huawei.com>
+The pointer assignment "const char *p = path;" in function
+qemu_fdt_add_path is unnecessary. Let's remove it and just
+use the "path" passed in. No functional change.
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
+Reviewed-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Message-id: 20220111032758.27804-1-wangyanan55@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ softmmu/device_tree.c | 9 ++++-----
+file changed, 4 insertions(+), 5 deletions(-)
+diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
+index XXXXXXX..XXXXXXX 100644
+--- a/softmmu/device_tree.c
++++ b/softmmu/device_tree.c
+@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
+ int qemu_fdt_add_path(void *fdt, const char *path)
+ {
+     const char *name;
+-    const char *p = path;
+     int namelen, retval;
+     int parent = 0;
+@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
+     }
+     do {
+-        name = p + 1;
+-        p = strchr(name, '/');
+-        namelen = p != NULL ? p - name : strlen(name);
++        name = path + 1;
++        path = strchr(name, '/');
++        namelen = path != NULL ? path - name : strlen(name);
+         retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
+         if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
+@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
+         }
+         parent = retval;
+-    } while (p);
++    } while (path);
+     return retval;
+ }
+--
+.31.1

-New patch
+[PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
+From: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-2-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h        | 1 +
+ target/riscv/cpu.c        | 4 ++++
+ target/riscv/cpu_helper.c | 5 ++++-
+ target/riscv/csr.c        | 6 +++++-
+ target/riscv/translate.c  | 2 ++
+files changed, 16 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+         bool ext_icsr;
+         bool ext_zfh;
+         bool ext_zfhmin;
++        bool ext_zve64f;
+         char *priv_spec;
+         char *user_spec;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             }
+             set_vext_version(env, vext_version);
+         }
++        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
++            error_setg(errp, "Zve64f extension depends upon RVF.");
++            return;
++        }
+         if (cpu->cfg.ext_j) {
+             ext |= RVJ;
+         }
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
+ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                           target_ulong *cs_base, uint32_t *pflags)
+ {
++    CPUState *cs = env_cpu(env);
++    RISCVCPU *cpu = RISCV_CPU(cs);
++
+     uint32_t flags = 0;
+     *pc = env->pc;
+     *cs_base = 0;
+-    if (riscv_has_ext(env, RVV)) {
++    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+         /*
+          * If env->vl equals to VLMAX, we can use generic vector operation
+          * expanders (GVEC) to accerlate the vector operations.
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
+ static RISCVException vs(CPURISCVState *env, int csrno)
+ {
+-    if (env->misa_ext & RVV) {
++    CPUState *cs = env_cpu(env);
++    RISCVCPU *cpu = RISCV_CPU(cs);
++
++    if (env->misa_ext & RVV ||
++        cpu->cfg.ext_zve64f) {
+ #if !defined(CONFIG_USER_ONLY)
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+             return RISCV_EXCP_ILLEGAL_INST;
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     bool ext_ifencei;
+     bool ext_zfh;
+     bool ext_zfhmin;
++    bool ext_zve64f;
+     bool hlsx;
+     /* vector extension */
+     bool vill;
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+     ctx->ext_zfh = cpu->cfg.ext_zfh;
+     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
++    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
+     ctx->vlen = cpu->cfg.vlen;
+     ctx->elen = cpu->cfg.elen;
+     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
+--
+.31.1

-New patch
+[PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
+From: Frank Chang <frank.chang@sifive.com>
+All Zve* extensions support the vector configuration instructions.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-3-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
+ {
+     TCGv s1, dst;
+-    if (!require_rvv(s) || !has_ext(s, RVV)) {
++    if (!require_rvv(s) ||
++        !(has_ext(s, RVV) || s->ext_zve64f)) {
+         return false;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+ {
+     TCGv dst;
+-    if (!require_rvv(s) || !has_ext(s, RVV)) {
++    if (!require_rvv(s) ||
++        !(has_ext(s, RVV) || s->ext_zve64f)) {
+         return false;
+     }
+--
+.31.1

-New patch
+[PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
+From: Frank Chang <frank.chang@sifive.com>
+All Zve* extensions support all vector load and store instructions,
+except Zve64* extensions do not support EEW=64 for index values when
+XLEN=32.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-4-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
+file changed, 15 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
+                                 uint8_t eew)
+ {
+     int8_t emul = eew - s->sew + s->lmul;
+-    return (emul >= -3 && emul <= 3) &&
+-            require_align(vs2, emul) &&
+-            require_align(vd, s->lmul) &&
+-            require_nf(vd, nf, s->lmul);
++    bool ret = (emul >= -3 && emul <= 3) &&
++               require_align(vs2, emul) &&
++               require_align(vd, s->lmul) &&
++               require_nf(vd, nf, s->lmul);
++
++    /*
++     * All Zve* extensions support all vector load and store instructions,
++     * except Zve64* extensions do not support EEW=64 for index values
++     * when XLEN=32. (Section 18.2)
++     */
++    if (get_xl(s) == MXL_RV32) {
++        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
++    }
++
++    return ret;
+ }
+ /*
+--
+.31.1

-New patch
+[PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
+From: Frank Chang <frank.chang@sifive.com>
+All Zve* extensions support all vector integer instructions,
+except that the vmulh integer multiply variants that return the
+high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
+vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-5-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
+file changed, 33 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
+ GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
+ /* Vector Single-Width Integer Multiply Instructions */
++
++static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
++{
++    /*
++     * All Zve* extensions support all vector integer instructions,
++     * except that the vmulh integer multiply variants
++     * that return the high word of the product
++     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
++     * are not included for EEW=64 in Zve64*. (Section 18.2)
++     */
++    return opivv_check(s, a) &&
++           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
++}
++
++static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
++{
++    /*
++     * All Zve* extensions support all vector integer instructions,
++     * except that the vmulh integer multiply variants
++     * that return the high word of the product
++     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
++     * are not included for EEW=64 in Zve64*. (Section 18.2)
++     */
++    return opivx_check(s, a) &&
++           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
++}
++
+ GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
+-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
+-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
+-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
++GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
++GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
++GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
+ GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
+-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
+-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
+-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
++GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
++GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
++GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
+ /* Vector Integer Divide Instructions */
+ GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
+--
+.31.1

-New patch
+[PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
+From: Frank Chang <frank.chang@sifive.com>
+All Zve* extensions support all vector fixed-point arithmetic
+instructions, except that vsmul.vv and vsmul.vx are not supported
+for EEW=64 in Zve64*.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-6-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
+file changed, 25 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
+ GEN_OPIVX_TRANS(vasubu_vx,  opivx_check)
+ /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+-GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
+-GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
++
++static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
++{
++    /*
++     * All Zve* extensions support all vector fixed-point arithmetic
++     * instructions, except that vsmul.vv and vsmul.vx are not supported
++     * for EEW=64 in Zve64*. (Section 18.2)
++     */
++    return opivv_check(s, a) &&
++           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
++}
++
++static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
++{
++    /*
++     * All Zve* extensions support all vector fixed-point arithmetic
++     * instructions, except that vsmul.vv and vsmul.vx are not supported
++     * for EEW=64 in Zve64*. (Section 18.2)
++     */
++    return opivx_check(s, a) &&
++           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
++}
++
++GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
++GEN_OPIVX_TRANS(vsmul_vx,  vsmul_vx_check)
+ /* Vector Single-Width Scaling Shift Instructions */
+ GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
+--
+.31.1

-New patch
+[PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
+From: Frank Chang <frank.chang@sifive.com>
+Zve64f extension requires the scalar processor to implement the F
+extension and implement all vector floating-point instructions for
+floating-point operands with EEW=32 (i.e., no widening floating-point
+operations).
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-7-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
+file changed, 31 insertions(+), 10 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
+     }
+ }
++static bool require_zve64f(DisasContext *s)
++{
++    /* RVV + Zve64f = RVV. */
++    if (has_ext(s, RVV)) {
++        return true;
++    }
++
++    /* Zve64f doesn't support FP64. (Section 18.2) */
++    return s->ext_zve64f ? s->sew <= MO_32 : true;
++}
++
+ /* Destination vector register group cannot overlap source mask register. */
+ static bool require_vm(int vm, int vd)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
++           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
++           require_zve64f(s);
+ }
+ /* OPFVV without GVEC IR */
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_ss(s, a->rd, a->rs2, a->vm);
++           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           require_zve64f(s);
+ }
+ /* OPFVF without GVEC IR */
+@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            /* OPFV instructions ignore vs1 check */
+-           vext_check_ss(s, a->rd, a->rs2, a->vm);
++           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           require_zve64f(s);
+ }
+ static bool do_opfv(DisasContext *s, arg_rmr *a,
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
++           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
++           require_zve64f(s);
+ }
+ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_ms(s, a->rd, a->rs2);
++           vext_check_ms(s, a->rd, a->rs2) &&
++           require_zve64f(s);
+ }
+ GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
+     if (require_rvv(s) &&
+         require_rvf(s) &&
+         vext_check_isa_ill(s) &&
+-        require_align(a->rd, s->lmul)) {
++        require_align(a->rd, s->lmul) &&
++        require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+         TCGv_i64 t1;
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
+ {
+     if (require_rvv(s) &&
+         require_rvf(s) &&
+-        vext_check_isa_ill(s)) {
++        vext_check_isa_ill(s) &&
++        require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+         unsigned int ofs = (8 << s->sew);
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
+ {
+     if (require_rvv(s) &&
+         require_rvf(s) &&
+-        vext_check_isa_ill(s)) {
++        vext_check_isa_ill(s) &&
++        require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+         /* The instructions ignore LMUL and vector register group. */
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
+ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
+ {
+     return slideup_check(s, a) &&
+-           require_rvf(s);
++           require_rvf(s) &&
++           require_zve64f(s);
+ }
+ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
+ {
+     return slidedown_check(s, a) &&
+-           require_rvf(s);
++           require_rvf(s) &&
++           require_zve64f(s);
+ }
+ GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
+--
+.31.1

-New patch
+[PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
+From: Frank Chang <frank.chang@sifive.com>
+Vector single-width floating-point reduction operations for EEW=32 are
+supported for Zve64f extension.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-8-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
+ static bool freduction_check(DisasContext *s, arg_rmrr *a)
+ {
+     return reduction_check(s, a) &&
+-           require_rvf(s);
++           require_rvf(s) &&
++           require_zve64f(s);
+ }
+ GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
+--
+.31.1

-New patch
+[PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
+From: Frank Chang <frank.chang@sifive.com>
+Vector widening conversion instructions are provided to and from all
+supported integer EEWs for Zve64f extension.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-9-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
+file changed, 25 insertions(+), 7 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
+     return s->ext_zve64f ? s->sew <= MO_32 : true;
+ }
++static bool require_scale_zve64f(DisasContext *s)
++{
++    /* RVV + Zve64f = RVV. */
++    if (has_ext(s, RVV)) {
++        return true;
++    }
++
++    /* Zve64f doesn't support FP64. (Section 18.2) */
++    return s->ext_zve64f ? s->sew <= MO_16 : true;
++}
++
+ /* Destination vector register group cannot overlap source mask register. */
+ static bool require_vm(int vm, int vd)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
++           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ /* OPFVV with WIDEN */
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_ds(s, a->rd, a->rs2, a->vm);
++           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ /* OPFVF with WIDEN */
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
++           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ /* WIDEN OPFVV with WIDEN */
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+-           vext_check_dd(s, a->rd, a->rs2, a->vm);
++           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ /* WIDEN OPFVF with WIDEN */
+@@ -XXX,XX +XXX,XX @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
+ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_widen_check(s, a) &&
+-           require_rvf(s);
++           require_rvf(s) &&
++           require_zve64f(s);
+ }
+ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_widen_check(s, a) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           (s->sew != MO_8) &&
++           require_scale_zve64f(s);
+ }
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
+            require_scale_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            /* OPFV widening instructions ignore vs1 check */
+-           vext_check_ds(s, a->rd, a->rs2, a->vm);
++           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
+--
+.31.1

-New patch
+[PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
+From: Frank Chang <frank.chang@sifive.com>
+Vector narrowing conversion instructions are provided to and from all
+supported integer EEWs for Zve64f extension.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-10-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
+file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
+            require_rvf(s) &&
+-           (s->sew != MO_64);
++           (s->sew != MO_64) &&
++           require_zve64f(s);
+ }
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           (s->sew != MO_8) &&
++           require_scale_zve64f(s);
+ }
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
+@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+            require_scale_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            /* OPFV narrowing instructions ignore vs1 check */
+-           vext_check_sd(s, a->rd, a->rs2, a->vm);
++           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
++           require_scale_zve64f(s);
+ }
+ #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
+--
+.31.1

-New patch
+[PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
+From: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-11-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
++    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+--
+.31.1

-New patch
+[PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
+From: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-12-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h        | 1 +
+ target/riscv/cpu.c        | 4 ++--
+ target/riscv/cpu_helper.c | 2 +-
+ target/riscv/csr.c        | 2 +-
+ target/riscv/translate.c  | 2 ++
+files changed, 7 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+         bool ext_icsr;
+         bool ext_zfh;
+         bool ext_zfhmin;
++        bool ext_zve32f;
+         bool ext_zve64f;
+         char *priv_spec;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+             }
+             set_vext_version(env, vext_version);
+         }
+-        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
+-            error_setg(errp, "Zve64f extension depends upon RVF.");
++        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
++            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
+             return;
+         }
+         if (cpu->cfg.ext_j) {
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+     *pc = env->pc;
+     *cs_base = 0;
+-    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
++    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+         /*
+          * If env->vl equals to VLMAX, we can use generic vector operation
+          * expanders (GVEC) to accerlate the vector operations.
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException vs(CPURISCVState *env, int csrno)
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     if (env->misa_ext & RVV ||
+-        cpu->cfg.ext_zve64f) {
++        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+ #if !defined(CONFIG_USER_ONLY)
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+             return RISCV_EXCP_ILLEGAL_INST;
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     bool ext_ifencei;
+     bool ext_zfh;
+     bool ext_zfhmin;
++    bool ext_zve32f;
+     bool ext_zve64f;
+     bool hlsx;
+     /* vector extension */
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+     ctx->ext_zfh = cpu->cfg.ext_zfh;
+     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
++    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
+     ctx->ext_zve64f = cpu->cfg.ext_zve64f;
+     ctx->vlen = cpu->cfg.vlen;
+     ctx->elen = cpu->cfg.elen;
+--
+.31.1

-New patch
+[PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
+From: Frank Chang <frank.chang@sifive.com>
+All Zve* extensions support the vector configuration instructions.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-13-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
+     TCGv s1, dst;
+     if (!require_rvv(s) ||
+-        !(has_ext(s, RVV) || s->ext_zve64f)) {
++        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+         return false;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+     TCGv dst;
+     if (!require_rvv(s) ||
+-        !(has_ext(s, RVV) || s->ext_zve64f)) {
++        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+         return false;
+     }
+--
+.31.1

-New patch
+[PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
+From: Frank Chang <frank.chang@sifive.com>
+Zve32f extension requires the scalar processor to implement the F
+extension and implement all vector floating-point instructions for
+floating-point operands with EEW=32 (i.e., no widening floating-point
+operations).
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-14-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
+file changed, 21 insertions(+)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
+     }
+ }
++static bool require_zve32f(DisasContext *s)
++{
++    /* RVV + Zve32f = RVV. */
++    if (has_ext(s, RVV)) {
++        return true;
++    }
++
++    /* Zve32f doesn't support FP64. (Section 18.2) */
++    return s->ext_zve32f ? s->sew <= MO_32 : true;
++}
++
+ static bool require_zve64f(DisasContext *s)
+ {
+     /* RVV + Zve64f = RVV. */
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
+            vext_check_isa_ill(s) &&
+            /* OPFV instructions ignore vs1 check */
+            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
+            require_rvf(s) &&
+            vext_check_isa_ill(s) &&
+            vext_check_ms(s, a->rd, a->rs2) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
+         require_rvf(s) &&
+         vext_check_isa_ill(s) &&
+         require_align(a->rd, s->lmul) &&
++        require_zve32f(s) &&
+         require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
+     if (require_rvv(s) &&
+         require_rvf(s) &&
+         vext_check_isa_ill(s) &&
++        require_zve32f(s) &&
+         require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
+     if (require_rvv(s) &&
+         require_rvf(s) &&
+         vext_check_isa_ill(s) &&
++        require_zve32f(s) &&
+         require_zve64f(s)) {
+         gen_set_rm(s, RISCV_FRM_DYN);
+@@ -XXX,XX +XXX,XX @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
+ {
+     return slideup_check(s, a) &&
+            require_rvf(s) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
+ {
+     return slidedown_check(s, a) &&
+            require_rvf(s) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+--
+.31.1

-New patch
+[PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
+From: Frank Chang <frank.chang@sifive.com>
+Vector single-width floating-point reduction operations for EEW=32 are
+supported for Zve32f extension.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-15-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
+ {
+     return reduction_check(s, a) &&
+            require_rvf(s) &&
++           require_zve32f(s) &&
+            require_zve64f(s);
+ }
+--
+.31.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Frank Chang <frank.chang@sifive.com>
-The previous implementation was broken in many ways:
+Vector widening conversion instructions are provided to and from all
- - Used mideleg instead of hideleg to mask accesses
+supported integer EEWs for Zve32f extension.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-id: 20220118014522.13613-16-frank.chang@sifive.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
-file changed, 34 insertions(+), 34 deletions(-)
+file changed, 18 insertions(+)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/csr.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static bool require_zve32f(DisasContext *s)
-     return write_mstatus(env, CSR_MSTATUS, newval);
+     return s->ext_zve32f ? s->sew <= MO_32 : true;
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static bool require_scale_zve32f(DisasContext *s)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    /* RVV + Zve32f = RVV. */
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    if (has_ext(s, RVV)) {
-+    return 0;
++        return true;
 +    }
 +
 +    /* Zve32f doesn't support FP64. (Section 18.2) */
 +    return s->ext_zve64f ? s->sew <= MO_16 : true;
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+ static bool require_zve64f(DisasContext *s)
  {
-     if (riscv_cpu_virt_enabled(env)) {
+     /* RVV + Zve64f = RVV. */
--        /* Tell the guest the VS bits, shifted to the S bit locations */
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+            (s->sew != MO_8) &&
-+        read_vsie(env, CSR_VSIE, val);
+            vext_check_isa_ill(s) &&
-     } else {
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
-         *val = env->mie & env->mideleg;
++           require_scale_zve32f(s) &&
-     }
+            require_scale_zve64f(s);
      return 0;
  }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+            (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_ds(s, a->rd, a->rs2, a->vm) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  {
--    target_ulong newval;
+     return opfv_widen_check(s, a) &&
-+    /* Shift the S bits to their VS bit location in mie */
+            require_rvf(s) &&
-+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
++           require_zve32f(s) &&
-+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+            require_zve64f(s);
 +    return write_mie(env, CSR_MIE, newval);
 +}
 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +{
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the guests S bits to VS */
 -        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 -                 ((val << 1) & VS_MODE_INTERRUPTS);
 +        write_vsie(env, CSR_VSIE, val);
      } else {
 -        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 +        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 +                              (val & S_MODE_INTERRUPTS);
 +        write_mie(env, CSR_MIE, newval);
      }
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
- static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
-@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+     return opfv_widen_check(s, a) &&
-     return 0;
+            require_scale_rvf(s) &&
             (s->sew != MO_8) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
-+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
-+                    target_ulong new_value, target_ulong write_mask)
+            vext_check_isa_ill(s) &&
-+{
+            /* OPFV widening instructions ignore vs1 check */
-+    /* Shift the S bits to their VS bit location in mip */
+            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
++           require_scale_zve32f(s) &&
-+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+            require_scale_zve64f(s);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
  static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
      int ret;
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the new values to line up with the VS bits */
 -        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 -                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
 -        ret &= vsip_writable_mask;
 -        ret >>= 1;
 +        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
      } else {
          ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                        write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
--                    target_ulong new_value, target_ulong write_mask)
--{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & env->mideleg & vsip_writable_mask);
--    return ret;
--}
--
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
--{
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
--    return 0;
--}
--
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
--{
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
--    return write_mie(env, CSR_MIE, newval);
--}
--
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
- {
-     *val = env->vstvec;
 --
-.30.1
+.31.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
-From: Bin Meng <bin.meng@windriver.com>
+From: Frank Chang <frank.chang@sifive.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+Vector narrowing conversion instructions are provided to and from all
-the address bytes. Note only SPI mode is supported by SST flashes.
+supported integer EEWs for Zve32f extension.
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Message-id: 20220118014522.13613-17-frank.chang@sifive.com
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 file changed, 3 insertions(+)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/block/m25p80.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
-     s->needed_bytes = get_addr_length(s);
+     return opfv_narrow_check(s, a) &&
-     switch (get_man(s)) {
+            require_rvf(s) &&
-     /* Dummy cycles - modeled with bytes writes instead of bits */
+            (s->sew != MO_64) &&
-+    case MAN_SST:
++           require_zve32f(s) &&
-+        s->needed_bytes += 1;
+            require_zve64f(s);
-+        break;
+ }
-     case MAN_WINBOND:
-         s->needed_bytes += 8;
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-         break;
+     return opfv_narrow_check(s, a) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
             vext_check_isa_ill(s) &&
             /* OPFV narrowing instructions ignore vs1 check */
             vext_check_sd(s, a->rd, a->rs2, a->vm) &&
 +           require_scale_zve32f(s) &&
             require_scale_zve64f(s);
  }
 --
-.30.1
+.31.1

-New patch
+[PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
+From: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220118014522.13613-18-frank.chang@sifive.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
++    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
+     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+--
+.31.1

-New patch
+[PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios
+From: Anup Patel <apatel@ventanamicro.com>
 Currently, we have to use OpenSBI firmware ELF as bios for the spike
 machine because the HTIF console requires ELF for parsing "fromhost"
 and "tohost" symbols.
 The latest OpenSBI can now optionally pick-up HTIF register address
 from HTIF DT node so using this feature spike machine can now use
 OpenSBI firmware BIN as bios.
 Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/char/riscv_htif.h |  5 ++++-
  include/hw/riscv/spike.h     |  1 +
  hw/char/riscv_htif.c         | 33 +++++++++++++++++++----------
  hw/riscv/spike.c             | 41 ++++++++++++++++++++++--------------
 files changed, 52 insertions(+), 28 deletions(-)
 diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/char/riscv_htif.h
 +++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ extern const MemoryRegionOps htif_io_ops;
  void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
      uint64_t st_size);
 +/* Check if HTIF uses ELF symbols */
 +bool htif_uses_elf_symbols(void);
 +
  /* legacy pre qom */
  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
 -    CPURISCVState *env, Chardev *chr);
 +    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
  #endif
 diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/spike.h
 +++ b/include/hw/riscv/spike.h
@@ -XXX,XX +XXX,XX @@ struct SpikeState {
  enum {
      SPIKE_MROM,
 +    SPIKE_HTIF,
      SPIKE_CLINT,
      SPIKE_DRAM
  };
 diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/riscv_htif.c
 +++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
      .write = htif_mm_write,
  };
 +bool htif_uses_elf_symbols(void)
 +{
 +    return (address_symbol_set == 3) ? true : false;
 +}
 +
  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
 -    CPURISCVState *env, Chardev *chr)
 +    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
  {
 -    uint64_t base = MIN(tohost_addr, fromhost_addr);
 -    uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
 -    uint64_t tohost_offset = tohost_addr - base;
 -    uint64_t fromhost_offset = fromhost_addr - base;
 +    uint64_t base, size, tohost_offset, fromhost_offset;
 +
 +    if (!htif_uses_elf_symbols()) {
 +        fromhost_addr = nonelf_base;
 +        tohost_addr = nonelf_base + 8;
 +    }
 +
 +    base = MIN(tohost_addr, fromhost_addr);
 +    size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
 +    tohost_offset = tohost_addr - base;
 +    fromhost_offset = fromhost_addr - base;
      HTIFState *s = g_malloc0(sizeof(HTIFState));
      s->address_space = address_space;
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
      qemu_chr_fe_init(&s->chr, chr, &error_abort);
      qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
          htif_be_change, s, NULL, true);
 -    if (address_symbol_set == 3) {
 -        memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
 -                              TYPE_HTIF_UART, size);
 -        memory_region_add_subregion_overlap(address_space, base,
 -                                            &s->mmio, 1);
 -    }
 +
 +    memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
 +                          TYPE_HTIF_UART, size);
 +    memory_region_add_subregion_overlap(address_space, base,
 +                                        &s->mmio, 1);
      return s;
  }
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
  static const MemMapEntry spike_memmap[] = {
      [SPIKE_MROM] =     {     0x1000,     0xf000 },
 +    [SPIKE_HTIF] =     {  0x1000000,     0x1000 },
      [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
      [SPIKE_DRAM] =     { 0x80000000,        0x0 },
  };
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
      qemu_fdt_add_subnode(fdt, "/htif");
      qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
 +    if (!htif_uses_elf_symbols()) {
 +        qemu_fdt_setprop_cells(fdt, "/htif", "reg",
 +            0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
 +    }
      qemu_fdt_add_subnode(fdt, "/soc");
      qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
      if (cmdline) {
          qemu_fdt_add_subnode(fdt, "/chosen");
          qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 +        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
      }
  }
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
          machine->ram);
 -    /* create device tree */
 -    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 -               riscv_is_32bit(&s->soc[0]));
 -
      /* boot rom */
      memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
                             memmap[SPIKE_MROM].size, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                      htif_symbol_callback);
      }
 +    /* Load kernel */
      if (machine->kernel_filename) {
          kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                           firmware_end_addr);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                           kernel_start_addr,
                                           htif_symbol_callback);
 -
 -        if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(s->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 -                                  end);
 -        }
      } else {
         /*
          * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          kernel_entry = 0;
      }
 +    /* Create device tree */
 +    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 +               riscv_is_32bit(&s->soc[0]));
 +
 +    /* Load initrd */
 +    if (machine->kernel_filename && machine->initrd_filename) {
 +        hwaddr start;
 +        hwaddr end = riscv_load_initrd(machine->initrd_filename,
 +                                       machine->ram_size, kernel_entry,
 +                                       &start);
 +        qemu_fdt_setprop_cell(s->fdt, "/chosen",
 +                              "linux,initrd-start", start);
 +        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 +                              end);
 +    }
 +
      /* Compute the fdt load address in dram */
      fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
                                     machine->ram_size, s->fdt);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      /* initialize HTIF using symbols found in load_kernel */
      htif_mm_init(system_memory, mask_rom,
 -                 &s->soc[0].harts[0].env, serial_hd(0));
 +                 &s->soc[0].harts[0].env, serial_hd(0),
 +                 memmap[SPIKE_HTIF].base);
  }
  static void spike_machine_instance_init(Object *obj)
 --
 .31.1

-New patch
+[PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names
+From: Anup Patel <apatel@ventanamicro.com>
+Now that RISC-V Spike machine can use BIN BIOS images, we remove
+the macros used for ELF BIOS image names.
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/boot.h | 2 --
+ hw/riscv/spike.c        | 4 ++--
+files changed, 2 insertions(+), 4 deletions(-)
+diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/boot.h
++++ b/include/hw/riscv/boot.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/riscv/riscv_hart.h"
+ #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
+-#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
+ #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
+-#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
+ bool riscv_is_32bit(RISCVHartArrayState *harts);
+diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/spike.c
++++ b/hw/riscv/spike.c
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+      */
+     if (riscv_is_32bit(&s->soc[0])) {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
++                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
+                                     htif_symbol_callback);
+     } else {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
++                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
+                                     htif_symbol_callback);
+     }
+--
+.31.1

-New patch
+[PULL 38/61] roms/opensbi: Remove ELF images
+From: Anup Patel <apatel@ventanamicro.com>
+Now that all RISC-V machines can use OpenSBI BIN images, we remove
+OpenSBI ELF images and also exclude these images from BIOS build.
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ .gitlab-ci.d/opensbi.yml                       |   2 --
+ pc-bios/meson.build                            |   2 --
+ pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
+ pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
+ roms/Makefile                                  |   2 --
+files changed, 6 deletions(-)
+ delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
+ delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
+diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml
+index XXXXXXX..XXXXXXX 100644
+--- a/.gitlab-ci.d/opensbi.yml
++++ b/.gitlab-ci.d/opensbi.yml
+@@ -XXX,XX +XXX,XX @@ build-opensbi:
+  artifacts:
+    paths: # 'artifacts.zip' will contains the following files:
+    - pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
+-   - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
+    - pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
+-   - pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
+    - opensbi32-generic-stdout.log
+    - opensbi32-generic-stderr.log
+    - opensbi64-generic-stdout.log
+diff --git a/pc-bios/meson.build b/pc-bios/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/pc-bios/meson.build
++++ b/pc-bios/meson.build
+@@ -XXX,XX +XXX,XX @@ blobs = files(
+   'hppa-firmware.img',
+   'opensbi-riscv32-generic-fw_dynamic.bin',
+   'opensbi-riscv64-generic-fw_dynamic.bin',
+-  'opensbi-riscv32-generic-fw_dynamic.elf',
+-  'opensbi-riscv64-generic-fw_dynamic.elf',
+   'npcm7xx_bootrom.bin',
+ )
+diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf and /dev/null differ
+diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf and /dev/null differ
+diff --git a/roms/Makefile b/roms/Makefile
+index XXXXXXX..XXXXXXX 100644
+--- a/roms/Makefile
++++ b/roms/Makefile
+@@ -XXX,XX +XXX,XX @@ opensbi32-generic:
+         CROSS_COMPILE=$(riscv32_cross_prefix) \
+         PLATFORM="generic"
+     cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
+-    cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
+ opensbi64-generic:
+     $(MAKE) -C opensbi \
+         CROSS_COMPILE=$(riscv64_cross_prefix) \
+         PLATFORM="generic"
+     cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
+-    cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
+ MESON = meson
+ NINJA = ninja
+--
+.31.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL 39/61] target/riscv: Adjust pmpcfg access with mxl
-From: Jim Shu <cwshu@andestech.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-If PMP permission of any address has been changed by updating PMP entry,
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-flush all TLB pages to prevent from getting old permission.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Jim Shu <cwshu@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
+Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ target/riscv/csr.c | 19 +++++++++++++++++++
-file changed, 4 insertions(+)
+ target/riscv/pmp.c | 12 ++++--------
 files changed, 23 insertions(+), 8 deletions(-)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
+     return RISCV_EXCP_NONE;
+ }
++static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
++{
++    /* TODO: RV128 restriction check */
++    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
++        return false;
++    }
++    return true;
++}
++
+ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+ {
++    uint32_t reg_index = csrno - CSR_PMPCFG0;
++
++    if (!check_pmp_reg_index(env, reg_index)) {
++        return RISCV_EXCP_ILLEGAL_INST;
++    }
+     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
+     return RISCV_EXCP_NONE;
+ }
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
+ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+ {
++    uint32_t reg_index = csrno - CSR_PMPCFG0;
++
++    if (!check_pmp_reg_index(env, reg_index)) {
++        return RISCV_EXCP_ILLEGAL_INST;
++    }
+     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+     return RISCV_EXCP_NONE;
+ }
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "cpu.h"
- #include "trace.h"
-+#include "exec/exec-all.h"
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
-     uint8_t val);
 @@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
+ {
+     int i;
+     uint8_t cfg_val;
++    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
+     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
+-    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
+-        qemu_log_mask(LOG_GUEST_ERROR,
+-                      "ignoring pmpcfg write - incorrect address\n");
+-        return;
+-    }
+-
+-    for (i = 0; i < sizeof(target_ulong); i++) {
++    for (i = 0; i < pmpcfg_nums; i++) {
          cfg_val = (val >> 8 * i)  & 0xff;
          pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
      }
-+
+@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
-+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+     int i;
-+    tlb_flush(env_cpu(env));
+     target_ulong cfg_val = 0;
- }
+     target_ulong val = 0;
++    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 -    for (i = 0; i < sizeof(target_ulong); i++) {
 +    for (i = 0; i < pmpcfg_nums; i++) {
          val = pmp_read_cfg(env, (reg_index * 4) + i);
          cfg_val |= (val << (i * 8));
      }
 --
-.30.1
+.31.1

-New patch
+[PULL 40/61] target/riscv: Don't save pc when exception return
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+As pc will be written by the xepc in exception return, just ignore
+pc in translation.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/helper.h                          | 4 ++--
+ target/riscv/op_helper.c                       | 4 ++--
+ target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
+files changed, 6 insertions(+), 9 deletions(-)
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/helper.h
++++ b/target/riscv/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(csrr_i128, tl, env, int)
+ DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
+ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
+ #ifndef CONFIG_USER_ONLY
+-DEF_HELPER_2(sret, tl, env, tl)
+-DEF_HELPER_2(mret, tl, env, tl)
++DEF_HELPER_1(sret, tl, env)
++DEF_HELPER_1(mret, tl, env)
+ DEF_HELPER_1(wfi, void, env)
+ DEF_HELPER_1(tlb_flush, void, env)
+ #endif
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/op_helper.c
++++ b/target/riscv/op_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
+ #ifndef CONFIG_USER_ONLY
+-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
++target_ulong helper_sret(CPURISCVState *env)
+ {
+     uint64_t mstatus;
+     target_ulong prev_priv, prev_virt;
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+     return retpc;
+ }
+-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
++target_ulong helper_mret(CPURISCVState *env)
+ {
+     if (!(env->priv >= PRV_M)) {
+         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
+ static bool trans_sret(DisasContext *ctx, arg_sret *a)
+ {
+ #ifndef CONFIG_USER_ONLY
+-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+-
+     if (has_ext(ctx, RVS)) {
+-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
++        gen_helper_sret(cpu_pc, cpu_env);
+         tcg_gen_exit_tb(NULL, 0); /* no chaining */
+         ctx->base.is_jmp = DISAS_NORETURN;
+     } else {
+@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
+ static bool trans_mret(DisasContext *ctx, arg_mret *a)
+ {
+ #ifndef CONFIG_USER_ONLY
+-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
++    gen_helper_mret(cpu_pc, cpu_env);
+     tcg_gen_exit_tb(NULL, 0); /* no chaining */
+     ctx->base.is_jmp = DISAS_NORETURN;
+     return true;
+--
+.31.1

-New patch
+[PULL 41/61] target/riscv: Sign extend link reg for jal and jalr
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/translate.c                | 4 +---
+ target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
+files changed, 2 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+             return;
+         }
+     }
+-    if (rd != 0) {
+-        tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
+-    }
++    gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
+     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
+     ctx->base.is_jmp = DISAS_NORETURN;
+ }
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+         tcg_temp_free(t0);
+     }
+-    if (a->rd != 0) {
+-        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+-    }
++    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
+     tcg_gen_lookup_and_goto_ptr();
+     if (misaligned) {
+--
+.31.1

-New patch
+[PULL 42/61] target/riscv: Sign extend pc for different XLEN
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+When pc is written, it is sign-extended to fill the widest supported XLEN.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/translate.c                      | 25 ++++++++++++++++---
+ .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
+ target/riscv/insn_trans/trans_rvi.c.inc       |  5 ++--
+ target/riscv/insn_trans/trans_rvv.c.inc       |  4 +--
+files changed, 27 insertions(+), 9 deletions(-)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
+     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+ }
++static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
++{
++    if (get_xl(ctx) == MXL_RV32) {
++        dest = (int32_t)dest;
++    }
++    tcg_gen_movi_tl(cpu_pc, dest);
++}
++
++static void gen_set_pc(DisasContext *ctx, TCGv dest)
++{
++    if (get_xl(ctx) == MXL_RV32) {
++        tcg_gen_ext32s_tl(cpu_pc, dest);
++    } else {
++        tcg_gen_mov_tl(cpu_pc, dest);
++    }
++}
++
+ static void generate_exception(DisasContext *ctx, int excp)
+ {
+-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
++    gen_set_pc_imm(ctx, ctx->base.pc_next);
+     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+     ctx->base.is_jmp = DISAS_NORETURN;
+ }
+ static void generate_exception_mtval(DisasContext *ctx, int excp)
+ {
+-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
++    gen_set_pc_imm(ctx, ctx->base.pc_next);
+     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+     ctx->base.is_jmp = DISAS_NORETURN;
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+ {
+     if (translator_use_goto_tb(&ctx->base, dest)) {
+         tcg_gen_goto_tb(n);
+-        tcg_gen_movi_tl(cpu_pc, dest);
++        gen_set_pc_imm(ctx, dest);
+         tcg_gen_exit_tb(ctx->base.tb, n);
+     } else {
+-        tcg_gen_movi_tl(cpu_pc, dest);
++        gen_set_pc_imm(ctx, dest);
+         tcg_gen_lookup_and_goto_ptr();
+     }
+ }
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
+ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+ {
+ #ifndef CONFIG_USER_ONLY
+-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
++    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+     gen_helper_wfi(cpu_env);
+     return true;
+ #else
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+     tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
+     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
++    gen_set_pc(ctx, cpu_pc);
+     if (!has_ext(ctx, RVC)) {
+         TCGv t0 = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+      * FENCE_I is a no-op in QEMU,
+      * however we need to end the translation block
+      */
+-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
++    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+     tcg_gen_exit_tb(NULL, 0);
+     ctx->base.is_jmp = DISAS_NORETURN;
+     return true;
+@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+ static bool do_csr_post(DisasContext *ctx)
+ {
+     /* We may have changed important cpu state -- exit to main loop. */
+-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
++    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+     tcg_gen_exit_tb(NULL, 0);
+     ctx->base.is_jmp = DISAS_NORETURN;
+     return true;
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
+     gen_set_gpr(s, rd, dst);
+     mark_vs_dirty(s);
+-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
++    gen_set_pc_imm(s, s->pc_succ_insn);
+     tcg_gen_lookup_and_goto_ptr();
+     s->base.is_jmp = DISAS_NORETURN;
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+     gen_helper_vsetvl(dst, cpu_env, s1, s2);
+     gen_set_gpr(s, rd, dst);
+     mark_vs_dirty(s);
+-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
++    gen_set_pc_imm(s, s->pc_succ_insn);
+     tcg_gen_lookup_and_goto_ptr();
+     s->base.is_jmp = DISAS_NORETURN;
+--
+.31.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+[PULL 43/61] target/riscv: Create xl field in env
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-According to the specification the "field SPVP of hstatus controls the
+Current xlen has been used in helper functions and many other places.
-privilege level of the access" for the hypervisor virtual-machine load
+The computation of current xlen is not so trivial, so that we should
-and store instructions HLV, HLVX and HSV.
+recompute it as little as possible.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Fortunately, xlen only changes in very seldom cases, such as exception,
 misa write, mstatus write, cpu reset, migration load. So that we can only
 recompute xlen in this places and cache it into CPURISCVState.
 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
+Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
+ target/riscv/cpu.h        | 31 +++++++++++++++++++++++++++++++
-file changed, 14 insertions(+), 11 deletions(-)
+ target/riscv/cpu.c        |  1 +
  target/riscv/cpu_helper.c | 34 ++--------------------------------
  target/riscv/csr.c        |  2 ++
  target/riscv/machine.c    | 10 ++++++++++
 files changed, 46 insertions(+), 32 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     uint32_t misa_mxl_max;  /* max mxl for this cpu */
+     uint32_t misa_ext;      /* current extensions */
+     uint32_t misa_ext_mask; /* max ext for this cpu */
++    uint32_t xl;            /* current xlen */
+     /* 128-bit helpers upper part return value */
+     target_ulong retxh;
+@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+ }
+ #endif
++#if defined(TARGET_RISCV32)
++#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
++#else
++static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
++{
++    RISCVMXL xl = env->misa_mxl;
++#if !defined(CONFIG_USER_ONLY)
++    /*
++     * When emulating a 32-bit-only cpu, use RV32.
++     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
++     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
++     * back to RV64 for lower privs.
++     */
++    if (xl != MXL_RV32) {
++        switch (env->priv) {
++        case PRV_M:
++            break;
++        case PRV_U:
++            xl = get_field(env->mstatus, MSTATUS64_UXL);
++            break;
++        default: /* PRV_S | PRV_H */
++            xl = get_field(env->mstatus, MSTATUS64_SXL);
++            break;
++        }
++    }
++#endif
++    return xl;
++}
++#endif
++
+ /*
+  * Encode LMUL to lmul as follows:
+  *     LMUL    vlmul    lmul
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+     /* mmte is supposed to have pm.current hardwired to 1 */
+     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
+ #endif
++    env->xl = riscv_cpu_mxl(env);
+     cs->exception_index = RISCV_EXCP_NONE;
+     env->load_res = -1;
+     set_default_nan_mode(1, &env->fp_status);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
-         use_background = true;
+ #endif
  }
 -static RISCVMXL cpu_get_xl(CPURISCVState *env)
 -{
 -#if defined(TARGET_RISCV32)
 -    return MXL_RV32;
 -#elif defined(CONFIG_USER_ONLY)
 -    return MXL_RV64;
 -#else
 -    RISCVMXL xl = riscv_cpu_mxl(env);
 -
 -    /*
 -     * When emulating a 32-bit-only cpu, use RV32.
 -     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 -     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 -     * back to RV64 for lower privs.
 -     */
 -    if (xl != MXL_RV32) {
 -        switch (env->priv) {
 -        case PRV_M:
 -            break;
 -        case PRV_U:
 -            xl = get_field(env->mstatus, MSTATUS64_UXL);
 -            break;
 -        default: /* PRV_S | PRV_H */
 -            xl = get_field(env->mstatus, MSTATUS64_SXL);
 -            break;
 -        }
 -    }
 -    return xl;
 -#endif
 -}
 -
  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags)
  {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
      }
+ #endif
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-+    /* MPRV does not affect the virtual-machine load/store
+-    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
-+       instructions, HLV, HLVX, and HSV. */
++    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+     *pflags = flags;
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+ }
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
              mode = get_field(env->mstatus, MSTATUS_MPP);
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                    __func__, address, access_type, mmu_idx);
 -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 -        if (get_field(env->mstatus, MSTATUS_MPRV)) {
 -            mode = get_field(env->mstatus, MSTATUS_MPP);
 +    /* MPRV does not affect the virtual-machine load/store
 +       instructions, HLV, HLVX, and HSV. */
 +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
 +        mode = get_field(env->hstatus, HSTATUS_SPVP);
 +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
 +               get_field(env->mstatus, MSTATUS_MPRV)) {
 +        mode = get_field(env->mstatus, MSTATUS_MPP);
 +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
 +            two_stage_lookup = true;
          }
      }
+     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+     env->priv = newpriv;
--        access_type != MMU_INST_FETCH &&
++    env->xl = cpu_recompute_xl(env);
--        get_field(env->mstatus, MSTATUS_MPRV) &&
--        get_field(env->mstatus, MSTATUS_MPV)) {
+     /*
--        two_stage_lookup = true;
+      * Clear the load reservation - otherwise a reservation placed in one
--    }
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
--
+index XXXXXXX..XXXXXXX 100644
-     if (riscv_cpu_virt_enabled(env) ||
+--- a/target/riscv/csr.c
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
++++ b/target/riscv/csr.c
-          access_type != MMU_INST_FETCH)) {
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
      }
      env->mstatus = mstatus;
 +    env->xl = cpu_recompute_xl(env);
      return RISCV_EXCP_NONE;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
      /* flush translation cache */
      tb_flush(env_cpu(env));
      env->misa_ext = val;
 +    env->xl = riscv_cpu_mxl(env);
      return RISCV_EXCP_NONE;
  }
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kvmtimer = {
      }
  };
 +static int riscv_cpu_post_load(void *opaque, int version_id)
 +{
 +    RISCVCPU *cpu = opaque;
 +    CPURISCVState *env = &cpu->env;
 +
 +    env->xl = cpu_recompute_xl(env);
 +    return 0;
 +}
 +
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
      .version_id = 3,
      .minimum_version_id = 3,
 +    .post_load = riscv_cpu_post_load,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
 --
-.30.1
+.31.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL 44/61] target/riscv: Ignore the pc bits above XLEN
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-The current condition for the use of background registers only
+The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
 considers the hypervisor load and store instructions,
 but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu_helper.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
+     uint32_t flags = 0;
-      */
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+-    *pc = env->pc;
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
++    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
-         use_background = true;
+     *cs_base = 0;
-     }
+     if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 --
-.30.1
+.31.1

-New patch
+[PULL 45/61] target/riscv: Extend pc for runtime pc write
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+In some cases, we must restore the guest PC to the address of the start of
+the TB, such as when the instruction counter hits zero. So extend pc register
+according to current xlen for these cases.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 22 +++++++++++++++++++---
+file changed, 19 insertions(+), 3 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     CPURISCVState *env = &cpu->env;
+-    env->pc = value;
++
++    if (env->xl == MXL_RV32) {
++        env->pc = (int32_t)value;
++    } else {
++        env->pc = value;
++    }
+ }
+ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     CPURISCVState *env = &cpu->env;
+-    env->pc = tb->pc;
++    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
++
++    if (xl == MXL_RV32) {
++        env->pc = (int32_t)tb->pc;
++    } else {
++        env->pc = tb->pc;
++    }
+ }
+ static bool riscv_cpu_has_work(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
+ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
+                           target_ulong *data)
+ {
+-    env->pc = data[0];
++    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
++    if (xl == MXL_RV32) {
++        env->pc = (int32_t)data[0];
++    } else {
++        env->pc = data[0];
++    }
+ }
+ static void riscv_cpu_reset(DeviceState *dev)
+--
+.31.1

-New patch
+[PULL 46/61] target/riscv: Use gdb xml according to max mxlen
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c     |  8 ++---
+ target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++-----------
+files changed, 55 insertions(+), 24 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+     RISCVCPU *cpu = RISCV_CPU(dev);
+     CPURISCVState *env = &cpu->env;
+     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
++    CPUClass *cc = CPU_CLASS(mcc);
+     int priv_version = 0;
+     Error *local_err = NULL;
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+     switch (env->misa_mxl_max) {
+ #ifdef TARGET_RISCV64
+     case MXL_RV64:
++        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+         break;
+     case MXL_RV128:
+         break;
+ #endif
+     case MXL_RV32:
++        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+         break;
+     default:
+         g_assert_not_reached();
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
+     cc->gdb_read_register = riscv_cpu_gdb_read_register;
+     cc->gdb_write_register = riscv_cpu_gdb_write_register;
+     cc->gdb_num_core_regs = 33;
+-#if defined(TARGET_RISCV32)
+-    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+-#elif defined(TARGET_RISCV64)
+-    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+-#endif
+     cc->gdb_stop_before_watchpoint = true;
+     cc->disas_set_info = riscv_cpu_disas_set_info;
+ #ifndef CONFIG_USER_ONLY
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/gdbstub.c
++++ b/target/riscv/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     CPURISCVState *env = &cpu->env;
++    target_ulong tmp;
+     if (n < 32) {
+-        return gdb_get_regl(mem_buf, env->gpr[n]);
++        tmp = env->gpr[n];
+     } else if (n == 32) {
+-        return gdb_get_regl(mem_buf, env->pc);
++        tmp = env->pc;
++    } else {
++        return 0;
++    }
++
++    switch (env->misa_mxl_max) {
++    case MXL_RV32:
++        return gdb_get_reg32(mem_buf, tmp);
++    case MXL_RV64:
++        return gdb_get_reg64(mem_buf, tmp);
++    default:
++        g_assert_not_reached();
+     }
+     return 0;
+ }
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     CPURISCVState *env = &cpu->env;
+-
+-    if (n == 0) {
+-        /* discard writes to x0 */
+-        return sizeof(target_ulong);
+-    } else if (n < 32) {
+-        env->gpr[n] = ldtul_p(mem_buf);
+-        return sizeof(target_ulong);
++    int length = 0;
++    target_ulong tmp;
++
++    switch (env->misa_mxl_max) {
++    case MXL_RV32:
++        tmp = (int32_t)ldl_p(mem_buf);
++        length = 4;
++        break;
++    case MXL_RV64:
++        if (env->xl < MXL_RV64) {
++            tmp = (int32_t)ldq_p(mem_buf);
++        } else {
++            tmp = ldq_p(mem_buf);
++        }
++        length = 8;
++        break;
++    default:
++        g_assert_not_reached();
++    }
++    if (n > 0 && n < 32) {
++        env->gpr[n] = tmp;
+     } else if (n == 32) {
+-        env->pc = ldtul_p(mem_buf);
+-        return sizeof(target_ulong);
++        env->pc = tmp;
+     }
+-    return 0;
++
++    return length;
+ }
+ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+                                                               cs->gdb_num_regs),
+                                  "riscv-vector.xml", 0);
+     }
+-#if defined(TARGET_RISCV32)
+-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
+-                             1, "riscv-32bit-virtual.xml", 0);
+-#elif defined(TARGET_RISCV64)
+-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
+-                             1, "riscv-64bit-virtual.xml", 0);
+-#endif
++    switch (env->misa_mxl_max) {
++    case MXL_RV32:
++        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
++                                 riscv_gdb_set_virtual,
++                                 1, "riscv-32bit-virtual.xml", 0);
++        break;
++    case MXL_RV64:
++        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
++                                 riscv_gdb_set_virtual,
++                                 1, "riscv-64bit-virtual.xml", 0);
++        break;
++    default:
++        g_assert_not_reached();
++    }
+     gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+                              riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
+--
+.31.1

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL 47/61] target/riscv: Relax debug check for pm write
-From: Frank Chang <frank.chang@sifive.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 is not enabled.
 If -1 is returned, exception will be raised and cs->exception_index will
 be set to the negative return value. The exception will then be treated
 as an instruction access fault instead of illegal instruction fault.
 Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/csr.c | 3 +++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 3 insertions(+)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
-     if (env->misa & RVV) {
+     int csr_priv = get_field(csrno, 0x300);
-         return 0;
+     int pm_current;
-     }
--    return -1;
++    if (env->debugger) {
-+    return -RISCV_EXCP_ILLEGAL_INST;
++        return false;
- }
++    }
+     /*
- static int ctr(CPURISCVState *env, int csrno)
+      * If priv lvls differ that means we're accessing csr from higher priv lvl,
       * so allow the access
 --
-.30.1
+.31.1

-New patch
+[PULL 48/61] target/riscv: Adjust csr write mask with XLEN
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Write mask is representing the bits we care about.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/op_helper.c                |  3 ++-
+ target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++----
+files changed, 10 insertions(+), 5 deletions(-)
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/op_helper.c
++++ b/target/riscv/op_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
+ void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
+ {
+-    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
++    target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
++    RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
+     if (ret != RISCV_EXCP_NONE) {
+         riscv_raise_exception(env, ret, GETPC());
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
+ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+ {
+-    if (get_xl(ctx) < MXL_RV128) {
++    RISCVMXL xl = get_xl(ctx);
++    if (xl < MXL_RV128) {
+         TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+         /*
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+             return do_csrw(ctx, a->csr, src);
+         }
+-        TCGv mask = tcg_constant_tl(-1);
++        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
++                                                     (target_ulong)-1);
+         return do_csrrw(ctx, a->rd, a->csr, src, mask);
+     } else {
+         TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+ {
+-    if (get_xl(ctx) < MXL_RV128) {
++    RISCVMXL xl = get_xl(ctx);
++    if (xl < MXL_RV128) {
+         TCGv src = tcg_constant_tl(a->rs1);
+         /*
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+             return do_csrw(ctx, a->csr, src);
+         }
+-        TCGv mask = tcg_constant_tl(-1);
++        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
++                                                     (target_ulong)-1);
+         return do_csrrw(ctx, a->rd, a->csr, src, mask);
+     } else {
+         TCGv src = tcg_constant_tl(a->rs1);
+--
+.31.1

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 49/61] target/riscv: Create current pm fields in env
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 short of its purpose, as all it checks is whether two-stage address
 translation either via the hypervisor-load store instructions or the
 MPRV feature would be allowed.
 What we really need instead is whether two-stage address translation was
 active when the exception was raised. However, in riscv_cpu_do_interrupt
 we do not have the information to reliably detect this. Therefore, when
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.h        |  4 ++++
  target/riscv/cpu.c        |  1 +
- target/riscv/cpu_helper.c | 21 ++++++++-------------
+ target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
-files changed, 13 insertions(+), 13 deletions(-)
+ target/riscv/csr.c        | 19 +++++++++++++++++
  target/riscv/machine.c    |  1 +
 files changed, 68 insertions(+)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
 @@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     target_ulong satp_hs;
+     target_ulong upmmask;
-     uint64_t mstatus_hs;
+     target_ulong upmbase;
+ #endif
-+    /* Signals whether the current exception occurred with two-stage address
++    target_ulong cur_pmmask;
-+       translation active. */
++    target_ulong cur_pmbase;
-+    bool two_stage_lookup;
      float_status fp_status;
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags);
 +void riscv_cpu_update_mask(CPURISCVState *env);
 +
-     target_ulong scounteren;
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-     target_ulong mcounteren;
+                            target_ulong *ret_value,
+                            target_ulong new_value, target_ulong write_mask);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
 @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
      env->mcause = 0;
      env->pc = env->resetvec;
 +    env->two_stage_lookup = false;
  #endif
-     cs->exception_index = EXCP_NONE;
+     env->xl = riscv_cpu_mxl(env);
 +    riscv_cpu_update_mask(env);
      cs->exception_index = RISCV_EXCP_NONE;
      env->load_res = -1;
+     set_default_nan_mode(1, &env->fp_status);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-         g_assert_not_reached();
+     *pflags = flags;
  }
 +void riscv_cpu_update_mask(CPURISCVState *env)
 +{
 +    target_ulong mask = -1, base = 0;
 +    /*
 +     * TODO: Current RVJ spec does not specify
 +     * how the extension interacts with XLEN.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    if (riscv_has_ext(env, RVJ)) {
 +        switch (env->priv) {
 +        case PRV_M:
 +            if (env->mmte & M_PM_ENABLE) {
 +                mask = env->mpmmask;
 +                base = env->mpmbase;
 +            }
 +            break;
 +        case PRV_S:
 +            if (env->mmte & S_PM_ENABLE) {
 +                mask = env->spmmask;
 +                base = env->spmbase;
 +            }
 +            break;
 +        case PRV_U:
 +            if (env->mmte & U_PM_ENABLE) {
 +                mask = env->upmmask;
 +                base = env->upmbase;
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    }
 +#endif
 +    if (env->xl == MXL_RV32) {
 +        env->cur_pmmask = mask & UINT32_MAX;
 +        env->cur_pmbase = base & UINT32_MAX;
 +    } else {
 +        env->cur_pmmask = mask;
 +        env->cur_pmbase = base;
 +    }
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static int riscv_cpu_local_irq_pending(CPURISCVState *env)
  {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
      /* tlb_flush is unnecessary as mode is contained in mmu_idx */
      env->priv = newpriv;
      env->xl = cpu_recompute_xl(env);
 +    riscv_cpu_update_mask(env);
      /*
       * Clear the load reservation - otherwise a reservation placed in one
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
      /* hardwiring pm.instruction bit to 0, since it's not supported yet */
      wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
      env->mmte = wpri_val | PM_EXT_DIRTY;
 +    riscv_cpu_update_mask(env);
      /* Set XS and SD bits, since PM CSRs are dirty */
      mstatus = env->mstatus | MSTATUS_XS;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
      uint64_t mstatus;
      env->mpmmask = val;
 +    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
 +        env->cur_pmmask = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
-     env->badaddr = address;
+     env->spmmask = val;
-+    env->two_stage_lookup = two_stage;
++    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
 +        env->cur_pmmask = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->upmmask = val;
 +    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
 +        env->cur_pmmask = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
      uint64_t mstatus;
      env->mpmbase = val;
 +    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->spmbase = val;
 +    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
      env->upmbase = val;
 +    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
 +        env->cur_pmbase = val;
 +    }
      env->mmte |= PM_EXT_DIRTY;
      /* Set XS and SD bits, since PM CSRs are dirty */
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
      CPURISCVState *env = &cpu->env;
      env->xl = cpu_recompute_xl(env);
 +    riscv_cpu_update_mask(env);
      return 0;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-     }
-     env->badaddr = addr;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
-     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
- }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
-         g_assert_not_reached();
-     }
-     env->badaddr = addr;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
-     riscv_raise_exception(env, cs->exception_index, retaddr);
- }
- #endif /* !CONFIG_USER_ONLY */
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         /* handle the trap in S-mode */
-         if (riscv_has_ext(env, RVH)) {
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
--            bool two_stage_lookup = false;
--            if (env->priv == PRV_M ||
--                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
--                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
--                    get_field(env->hstatus, HSTATUS_HU))) {
--                    two_stage_lookup = true;
--            }
--
--            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
-+            if (env->two_stage_lookup && write_tval) {
-                 /*
-                  * If we are writing a guest virtual address to stval, set
-                  * this to 1. If we are trapping to VS we will set this to 0
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-                 riscv_cpu_set_force_hs_excep(env, 0);
-             } else {
-                 /* Trap into HS mode */
--                if (!two_stage_lookup) {
--                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
--                                             riscv_cpu_virt_enabled(env));
--                }
-+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
-                 htval = env->guest_phys_fault_addr;
-             }
-         }
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-      * RISC-V ISA Specification.
-      */
-+    env->two_stage_lookup = false;
- #endif
-     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
- }
 --
-.30.1
+.31.1

-New patch
+[PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base]
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Replace the array of pm_mask/pm_base with scalar variables.
+Remove the cached array value in DisasContext.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/translate.c | 32 ++++++++------------------------
+file changed, 8 insertions(+), 24 deletions(-)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
+ static TCGv load_res;
+ static TCGv load_val;
+ /* globals for PM CSRs */
+-static TCGv pm_mask[4];
+-static TCGv pm_base[4];
++static TCGv pm_mask;
++static TCGv pm_base;
+ #include "exec/gen-icount.h"
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     TCGv temp[4];
+     /* PointerMasking extension */
+     bool pm_enabled;
+-    TCGv pm_mask;
+-    TCGv pm_base;
+ } DisasContext;
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
+         return src;
+     } else {
+         temp = temp_new(s);
+-        tcg_gen_andc_tl(temp, src, s->pm_mask);
+-        tcg_gen_or_tl(temp, temp, s->pm_base);
++        tcg_gen_andc_tl(temp, src, pm_mask);
++        tcg_gen_or_tl(temp, temp, pm_base);
+         return temp;
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     ctx->ntemp = 0;
+     memset(ctx->temp, 0, sizeof(ctx->temp));
+     ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+-    int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
+-    ctx->pm_mask = pm_mask[priv];
+-    ctx->pm_base = pm_base[priv];
+-
+     ctx->zero = tcg_constant_tl(0);
+ }
+@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
+                              "load_res");
+     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
+                              "load_val");
+-#ifndef CONFIG_USER_ONLY
+     /* Assign PM CSRs to tcg globals */
+-    pm_mask[PRV_U] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+-    pm_base[PRV_U] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+-    pm_mask[PRV_S] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+-    pm_base[PRV_S] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+-    pm_mask[PRV_M] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+-    pm_base[PRV_M] =
+-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+-#endif
++    pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
++                                 "pmmask");
++    pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
++                                 "pmbase");
+ }
+--
+.31.1

-New patch
+[PULL 51/61] target/riscv: Calculate address according to XLEN
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Define one common function to compute a canonical address from a register
 plus offset. Merge gen_pm_adjust_address into this function.
 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/translate.c                | 25 ++++++++++++-------------
  target/riscv/insn_trans/trans_rva.c.inc |  9 +++------
  target/riscv/insn_trans/trans_rvd.c.inc | 19 ++-----------------
  target/riscv/insn_trans/trans_rvf.c.inc | 19 ++-----------------
  target/riscv/insn_trans/trans_rvi.c.inc | 18 ++----------------
 files changed, 21 insertions(+), 69 deletions(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
 -/*
 - * Generates address adjustment for PointerMasking
 - */
 -static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
 +/* Compute a canonical address from a register plus offset. */
 +static TCGv get_address(DisasContext *ctx, int rs1, int imm)
  {
 -    TCGv temp;
 -    if (!s->pm_enabled) {
 -        /* Load unmodified address */
 -        return src;
 -    } else {
 -        temp = temp_new(s);
 -        tcg_gen_andc_tl(temp, src, pm_mask);
 -        tcg_gen_or_tl(temp, temp, pm_base);
 -        return temp;
 +    TCGv addr = temp_new(ctx);
 +    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 +
 +    tcg_gen_addi_tl(addr, src1, imm);
 +    if (ctx->pm_enabled) {
 +        tcg_gen_and_tl(addr, addr, pm_mask);
 +        tcg_gen_or_tl(addr, addr, pm_base);
 +    } else if (get_xl(ctx) == MXL_RV32) {
 +        tcg_gen_ext32u_tl(addr, addr);
      }
 +    return addr;
  }
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rva.c.inc
 +++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
  static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
  {
 -    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 +    TCGv src1 = get_address(ctx, a->rs1, 0);
      if (a->rl) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
      }
 -    src1 = gen_pm_adjust_address(ctx, src1);
      tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
      if (a->aq) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      TCGLabel *l1 = gen_new_label();
      TCGLabel *l2 = gen_new_label();
 -    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 -    src1 = gen_pm_adjust_address(ctx, src1);
 +    src1 = get_address(ctx, a->rs1, 0);
      tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
      /*
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                      MemOp mop)
  {
      TCGv dest = dest_gpr(ctx, a->rd);
 -    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +    TCGv src1 = get_address(ctx, a->rs1, 0);
      TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 -    src1 = gen_pm_adjust_address(ctx, src1);
      func(dest, src1, src2, ctx->mem_idx, mop);
      gen_set_gpr(ctx, a->rd, dest);
 diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvd.c.inc
 +++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
      mark_fs_dirty(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
 -
      return true;
  }
 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvf.c.inc
 +++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      dest = cpu_fpr[a->rd];
      tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
      gen_nanbox_s(dest, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = tcg_temp_new();
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
 +    addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
 -
      return true;
  }
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
  static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
  {
      TCGv dest = dest_gpr(ctx, a->rd);
 -    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 -
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 +    TCGv addr = get_address(ctx, a->rs1, a->imm);
      tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
      gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
  static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
  {
 -    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +    TCGv addr = get_address(ctx, a->rs1, a->imm);
      TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 -    if (a->imm) {
 -        TCGv temp = temp_new(ctx);
 -        tcg_gen_addi_tl(temp, addr, a->imm);
 -        addr = temp;
 -    }
 -    addr = gen_pm_adjust_address(ctx, addr);
 -
      tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
      return true;
  }
 --
 .31.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 52/61] target/riscv: Split pm_enabled into mask and base
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+Use cached cur_pmmask and cur_pmbase to infer the
-further compressed instruction decoding. However, prior to this change,
+current PM mode.
 we did not raise an illegal instruction exception, if decode_RV32_64C()
 fails to decode the instruction. This means that we skipped illegal
 compressed instructions instead of raising an illegal instruction
 exception.
-Instead of patching decode_RV32_64C(), we can just remove it,
+This may decrease the TCG IR by one when pm_enabled
-as it is dead code since f330433b363 anyway.
+is true and pm_base_enabled is false.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ target/riscv/cpu.h        |  3 ++-
-file changed, 1 insertion(+), 178 deletions(-)
+ target/riscv/cpu_helper.c | 24 ++++++------------------
  target/riscv/translate.c  | 12 ++++++++----
 files changed, 16 insertions(+), 23 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
+ /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
+ FIELD(TB_FLAGS, XL, 20, 2)
+ /* If PointerMasking should be applied */
+-FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
++FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
++FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
+ #ifdef TARGET_RISCV32
+ #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
+                            get_field(env->mstatus_hs, MSTATUS_VS));
+     }
+-    if (riscv_has_ext(env, RVJ)) {
+-        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
+-        bool pm_enabled = false;
+-        switch (priv) {
+-        case PRV_U:
+-            pm_enabled = env->mmte & U_PM_ENABLE;
+-            break;
+-        case PRV_S:
+-            pm_enabled = env->mmte & S_PM_ENABLE;
+-            break;
+-        case PRV_M:
+-            pm_enabled = env->mmte & M_PM_ENABLE;
+-            break;
+-        default:
+-            g_assert_not_reached();
+-        }
+-        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+-    }
+ #endif
+     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
++    if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
++        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
++    }
++    if (env->cur_pmbase != 0) {
++        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
++    }
+     *pflags = flags;
+ }
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     CPUState *cs;
+     /* Space for 3 operands plus 1 extra for address computation. */
      TCGv temp[4];
      /* PointerMasking extension */
 -    bool pm_enabled;
 +    bool pm_mask_enabled;
 +    bool pm_base_enabled;
  } DisasContext;
--#ifdef TARGET_RISCV64
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
--/* convert riscv funct3 to qemu memop for load/store */
+@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
--static const int tcg_memop_lookup[8] = {
+     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
--    [0 ... 7] = -1,
--    [0] = MO_SB,
+     tcg_gen_addi_tl(addr, src1, imm);
--    [1] = MO_TESW,
+-    if (ctx->pm_enabled) {
--    [2] = MO_TESL,
++    if (ctx->pm_mask_enabled) {
--    [3] = MO_TEQ,
+         tcg_gen_and_tl(addr, addr, pm_mask);
--    [4] = MO_UB,
+-        tcg_gen_or_tl(addr, addr, pm_base);
--    [5] = MO_TEUW,
+     } else if (get_xl(ctx) == MXL_RV32) {
--    [6] = MO_TEUL,
+         tcg_gen_ext32u_tl(addr, addr);
--};
+     }
--#endif
++    if (ctx->pm_base_enabled) {
--
++        tcg_gen_or_tl(addr, addr, pm_base);
- #ifdef TARGET_RISCV64
++    }
- #define CASE_OP_32_64(X) case X: case glue(X, W)
+     return addr;
  #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
--#ifdef TARGET_RISCV64
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+     ctx->cs = cs;
--        target_long imm)
+     ctx->ntemp = 0;
--{
+     memset(ctx->temp, 0, sizeof(ctx->temp));
--    TCGv t0 = tcg_temp_new();
+-    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
--    TCGv t1 = tcg_temp_new();
++    ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
--    gen_get_gpr(t0, rs1);
++    ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
--    tcg_gen_addi_tl(t0, t0, imm);
+     ctx->zero = tcg_constant_tl(0);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
 -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
 -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
      tcg_temp_free_i32(t0);
  }
--static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
--{
--    uint8_t funct3 = extract16(opcode, 13, 3);
--    uint8_t rd_rs2 = GET_C_RS2S(opcode);
--    uint8_t rs1s = GET_C_RS1S(opcode);
--
--    switch (funct3) {
--    case 3:
--#if defined(TARGET_RISCV64)
--        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
--        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
--                 GET_C_LD_IMM(opcode));
--#else
--        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
--        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
--                    GET_C_LW_IMM(opcode));
--#endif
--        break;
--    case 7:
--#if defined(TARGET_RISCV64)
--        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
--        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
--                  GET_C_LD_IMM(opcode));
--#else
--        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
--        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
--                     GET_C_LW_IMM(opcode));
--#endif
--        break;
--    }
--}
--
--static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
--{
--    uint8_t op = extract16(opcode, 0, 2);
--
--    switch (op) {
--    case 0:
--        decode_RV32_64C0(ctx, opcode);
--        break;
--    }
--}
--
- static int ex_plus_1(DisasContext *ctx, int nf)
- {
-     return nf + 1;
-@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
-         } else {
-             ctx->pc_succ_insn = ctx->base.pc_next + 2;
-             if (!decode_insn16(ctx, opcode)) {
--                /* fall back to old decoder */
--                decode_RV32_64C(ctx, opcode);
-+                gen_exception_illegal(ctx);
-             }
-         }
-     } else {
 --
-.30.1
+.31.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+[PULL 53/61] target/riscv: Split out the vill from vtype
-From: Jim Shu <cwshu@andestech.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Like MMU translation, add qemu log of PMP permission checking for
+We need not specially process vtype when XLEN changes.
 debugging.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
+Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++++++++
+ target/riscv/cpu.h           |  1 +
-file changed, 12 insertions(+)
+ target/riscv/cpu_helper.c    |  3 +--
  target/riscv/csr.c           | 13 ++++++++++++-
  target/riscv/machine.c       |  5 +++--
  target/riscv/vector_helper.c |  3 ++-
 files changed, 19 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     target_ulong vl;
+     target_ulong vstart;
+     target_ulong vtype;
++    bool vill;
+     target_ulong pc;
+     target_ulong load_res;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-             if (ret == TRANSLATE_SUCCESS) {
+         uint32_t maxsz = vlmax << sew;
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+         bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
-                                                size, access_type, mode);
+                            (maxsz >= 8);
-+
+-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-+                qemu_log_mask(CPU_LOG_MMU,
+-                    FIELD_EX64(env->vtype, VTYPE, VILL));
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
++        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
+         flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
-+                              __func__, pa, ret, prot_pmp, tlb_size);
+         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-+
+                     FIELD_EX64(env->vtype, VTYPE, VLMUL));
-                 prot &= prot_pmp;
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-             }
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++++ b/target/riscv/csr.c
-         if (ret == TRANSLATE_SUCCESS) {
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ static RISCVException read_vtype(CPURISCVState *env, int csrno,
-                                            size, access_type, mode);
+                                  target_ulong *val)
-+
+ {
-+            qemu_log_mask(CPU_LOG_MMU,
+-    *val = env->vtype;
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
++    uint64_t vill;
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
++    switch (env->xl) {
-+                          __func__, pa, ret, prot_pmp, tlb_size);
++    case MXL_RV32:
-+
++        vill = (uint32_t)env->vill << 31;
-             prot &= prot_pmp;
++        break;
 +    case MXL_RV64:
 +        vill = (uint64_t)env->vill << 63;
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    *val = (target_ulong)vill | env->vtype;
      return RISCV_EXCP_NONE;
  }
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static bool vector_needed(void *opaque)
  static const VMStateDescription vmstate_vector = {
      .name = "cpu/vector",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .needed = vector_needed,
      .fields = (VMStateField[]) {
              VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
              VMSTATE_UINTTL(env.vl, RISCVCPU),
              VMSTATE_UINTTL(env.vstart, RISCVCPU),
              VMSTATE_UINTTL(env.vtype, RISCVCPU),
 +            VMSTATE_BOOL(env.vill, RISCVCPU),
              VMSTATE_END_OF_LIST()
          }
-     }
+ };
 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
          || (ediv != 0)
          || (reserved != 0)) {
          /* only set vill bit. */
 -        env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
 +        env->vill = 1;
 +        env->vtype = 0;
          env->vl = 0;
          env->vstart = 0;
          return 0;
 --
-.30.1
+.31.1

-New patch
+[PULL 54/61] target/riscv: Adjust vsetvl according to XLEN
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h           | 5 +++++
+ target/riscv/vector_helper.c | 7 +++++--
+files changed, 10 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+ }
+ #endif
++static inline int riscv_cpu_xlen(CPURISCVState *env)
++{
++    return 16 << env->xl;
++}
++
+ /*
+  * Encode LMUL to lmul as follows:
+  *     LMUL    vlmul    lmul
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
+     uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
+     uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
+     uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
+-    bool vill = FIELD_EX64(s2, VTYPE, VILL);
+-    target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
++    int xlen = riscv_cpu_xlen(env);
++    bool vill = (s2 >> (xlen - 1)) & 0x1;
++    target_ulong reserved = s2 &
++                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
++                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+     if (lmul & 4) {
+         /* Fractional LMUL. */
+--
+.31.1

-New patch
+[PULL 55/61] target/riscv: Remove VILL field in VTYPE
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 1 -
+file changed, 1 deletion(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(VTYPE, VTA, 6, 1)
+ FIELD(VTYPE, VMA, 7, 1)
+ FIELD(VTYPE, VEDIV, 8, 2)
+ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
+-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
+ struct CPURISCVState {
+     target_ulong gpr[32];
+--
+.31.1

-New patch
+[PULL 56/61] target/riscv: Fix check range for first fault only
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Only check the range that has passed the address translation.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_helper.c
++++ b/target/riscv/vector_helper.c
+@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
+                                          cpu_mmu_index(env, false));
+                 if (host) {
+ #ifdef CONFIG_USER_ONLY
+-                    if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
++                    if (page_check_range(addr, offset, PAGE_READ) < 0) {
+                         vl = i;
+                         goto ProbeSuccess;
+                     }
+ #else
+-                    probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
++                    probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
+ #endif
+                 } else {
+                     vl = i;
+--
+.31.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL 57/61] target/riscv: Adjust vector address with mask
-From: Asherah Connor <ashe@kivikakk.ee>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Provides fw_cfg for the virt machine on riscv.  This enables
+The mask comes from the pointer masking extension, or the max value
-using e.g.  ramfb later.
+corresponding to XLEN bits.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ target/riscv/vector_helper.c | 25 +++++++++++++++----------
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+file changed, 15 insertions(+), 10 deletions(-)
  hw/riscv/Kconfig        |  1 +
 files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/target/riscv/vector_helper.c
-+++ b/include/hw/riscv/virt.h
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+     return scale < 0 ? vlenb >> -scale : vlenb << scale;
      DeviceState *plic[VIRT_SOCKETS_MAX];
      PFlashCFI01 *flash[2];
 +    FWCfgState *fw_cfg;
      int fdt_size;
  };
@@ -XXX,XX +XXX,XX @@ enum {
      VIRT_PLIC,
      VIRT_UART0,
      VIRT_VIRTIO,
 +    VIRT_FW_CFG,
      VIRT_FLASH,
      VIRT_DRAM,
      VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
      [VIRT_UART0] =       { 0x10000000,         0x100 },
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
 +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
      return dev;
  }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
++static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 +{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
++    return (addr & env->cur_pmmask) | env->cur_pmbase;
 +    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
 +    FWCfgState *fw_cfg;
 +    char *nodename;
 +
 +    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
 +                                  &address_space_memory);
 +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
 +
 +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
 +    qemu_fdt_add_subnode(mc->fdt, nodename);
 +    qemu_fdt_setprop_string(mc->fdt, nodename,
 +                            "compatible", "qemu,fw-cfg-mmio");
 +    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
 +                                 2, base, 2, size);
 +    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 +    g_free(nodename);
 +    return fw_cfg;
 +}
 +
- static void virt_machine_init(MachineState *machine)
+ /*
- {
+  * This function checks watchpoint before real load operation.
-     const MemMapEntry *memmap = virt_memmap;
+  *
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
-         start_addr = virt_memmap[VIRT_FLASH].base;
+     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
      target_ulong curlen = MIN(pagelen, len);
 -    probe_access(env, addr, curlen, access_type,
 +    probe_access(env, adjust_addr(env, addr), curlen, access_type,
                   cpu_mmu_index(env, false), ra);
      if (len > curlen) {
          addr += curlen;
          curlen = len - curlen;
 -        probe_access(env, addr, curlen, access_type,
 +        probe_access(env, adjust_addr(env, addr), curlen, access_type,
                       cpu_mmu_index(env, false), ra);
      }
+ }
-+    /*
+@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+         k = 0;
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+         while (k < nf) {
-+     */
+             target_ulong addr = base + stride * i + (k << esz);
-+    s->fw_cfg = create_fw_cfg(machine);
+-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-+    rom_set_fw(s->fw_cfg);
++            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-+
+             k++;
-     /* Compute the fdt load address in dram */
+         }
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+     }
-                                    machine->ram_size, machine->fdt);
+@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+         k = 0;
-index XXXXXXX..XXXXXXX 100644
+         while (k < nf) {
---- a/hw/riscv/Kconfig
+             target_ulong addr = base + ((i * nf + k) << esz);
-+++ b/hw/riscv/Kconfig
+-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
++            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
-     select SIFIVE_PLIC
+             k++;
-     select SIFIVE_TEST
+         }
-     select VIRTIO_MMIO
+     }
-+    select FW_CFG_DMA
+@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
+         k = 0;
- config SIFIVE_E
+         while (k < nf) {
-     bool
+             abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
 -            ldst_elem(env, addr, i + k * max_elems, vd, ra);
 +            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
              k++;
          }
      }
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
          if (!vm && !vext_elem_mask(v0, i)) {
              continue;
          }
 -        addr = base + i * (nf << esz);
 +        addr = adjust_addr(env, base + i * (nf << esz));
          if (i == 0) {
              probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
          } else {
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                      break;
                  }
                  remain -= offset;
 -                addr += offset;
 +                addr = adjust_addr(env, addr + offset);
              }
          }
      }
@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
          }
          while (k < nf) {
              target_ulong addr = base + ((i * nf + k) << esz);
 -            ldst_elem(env, addr, i + k * max_elems, vd, ra);
 +            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
              k++;
          }
      }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
          /* load/store rest of elements of current segment pointed by vstart */
          for (pos = off; pos < max_elems; pos++, env->vstart++) {
              target_ulong addr = base + ((pos + k * max_elems) << esz);
 -            ldst_elem(env, addr, pos + k * max_elems, vd, ra);
 +            ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
          }
          k++;
      }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
      for (; k < nf; k++) {
          for (i = 0; i < max_elems; i++, env->vstart++) {
              target_ulong addr = base + ((i + k * max_elems) << esz);
 -            ldst_elem(env, addr, i + k * max_elems, vd, ra);
 +            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
          }
      }
 --
-.30.1
+.31.1

-New patch
+[PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+When sew <= 32bits, not need to extend scalar reg.
+When sew > 32bits, if xlen is less that sew, we should sign extend
+the scalar register, except explicitly specified by the spec.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
+     dest = tcg_temp_new_ptr();
+     mask = tcg_temp_new_ptr();
+     src2 = tcg_temp_new_ptr();
+-    src1 = get_gpr(s, rs1, EXT_NONE);
++    src1 = get_gpr(s, rs1, EXT_SIGN);
+     data = FIELD_DP32(data, VDATA, VM, vm);
+     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+--
+.31.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 59/61] target/riscv: Set default XLEN for hypervisor
-From: Bin Meng <bin.meng@windriver.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+When swap regs for hypervisor, the value of vsstatus or mstatus_hs
-been updated to use a register mapped at 0x4f000000 instead of a
+should have the right XLEN. Otherwise, it will propagate to mstatus.
 GPIO to control whether eMMC or SD card is to be used. With this
 support the same HSS image can be used for both eMMC and SD card
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ target/riscv/cpu.c | 10 ++++++++++
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+file changed, 10 insertions(+)
 files changed, 7 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/cpu.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
-     MICROCHIP_PFSOC_ENVM_DATA,
+          */
-     MICROCHIP_PFSOC_QSPI_XIP,
+         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
-     MICROCHIP_PFSOC_IOSCB,
+         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
++        if (riscv_has_ext(env, RVH)) {
-     MICROCHIP_PFSOC_DRAM_LO,
++            env->vsstatus = set_field(env->vsstatus,
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
++                                      MSTATUS64_SXL, env->misa_mxl);
-     MICROCHIP_PFSOC_DRAM_HI,
++            env->vsstatus = set_field(env->vsstatus,
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
++                                      MSTATUS64_UXL, env->misa_mxl);
-index XXXXXXX..XXXXXXX 100644
++            env->mstatus_hs = set_field(env->mstatus_hs,
---- a/hw/riscv/microchip_pfsoc.c
++                                        MSTATUS64_SXL, env->misa_mxl);
-+++ b/hw/riscv/microchip_pfsoc.c
++            env->mstatus_hs = set_field(env->mstatus_hs,
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
++                                        MSTATUS64_UXL, env->misa_mxl);
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
++        }
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+     }
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+     env->mcause = 0;
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
+     env->pc = env->resetvec;
      [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                      memmap[MICROCHIP_PFSOC_IOSCB].base);
 +    /* eMMC/SD mux */
 +    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
 +
      /* QSPI Flash */
      memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                             "microchip.pfsoc.qspi_xip",
 --
-.30.1
+.31.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL 60/61] target/riscv: Enable uxl field write
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ target/riscv/cpu_bits.h |  3 +++
-file changed, 4 insertions(+), 3 deletions(-)
+ target/riscv/csr.c      | 28 ++++++++++++++++++++++------
 files changed, 25 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+ #define COUNTEREN_IR         (1 << 2)
+ #define COUNTEREN_HPM3       (1 << 3)
++/* vsstatus CSR bits */
++#define VSSTATUS64_UXL       0x0000000300000000ULL
++
+ /* Privilege modes */
+ #define PRV_U 0
+ #define PRV_S 1
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
        (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+-    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
 +    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
  static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+ static const target_ulong hip_writable_mask = MIP_VSSIP;
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
+ static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
  static const target_ulong vsip_writable_mask = MIP_VSSIP;
  static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+     uint64_t mstatus = env->mstatus;
--                      write_mask & hip_writable_mask);
+     uint64_t mask = 0;
-+                      write_mask & hvip_writable_mask);
++    RISCVMXL xl = riscv_cpu_mxl(env);
--    *ret_value &= hip_writable_mask;
+     /* flush tlb on mstatus fields that affect VM */
-+    *ret_value &= hvip_writable_mask;
+     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
-     return ret;
+         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
          MSTATUS_TW | MSTATUS_VS;
 -    if (riscv_cpu_mxl(env) != MXL_RV32) {
 +    if (xl != MXL_RV32) {
          /*
           * RV32: MPV and GVA are not in mstatus. The current plan is to
           * add them to mstatush. For now, we just don't support it.
           */
          mask |= MSTATUS_MPV | MSTATUS_GVA;
 +        if ((val & MSTATUS64_UXL) != 0) {
 +            mask |= MSTATUS64_UXL;
 +        }
      }
      mstatus = (mstatus & ~mask) | (val & mask);
 -    RISCVMXL xl = riscv_cpu_mxl(env);
      if (xl > MXL_RV32) {
 -        /* SXL and UXL fields are for now read only */
 +        /* SXL field is for now read only */
          mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
 -        mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
      }
      env->mstatus = mstatus;
      env->xl = cpu_recompute_xl(env);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
  {
      uint64_t mask = sstatus_v1_10_mask;
      uint64_t sstatus = env->mstatus & mask;
 +    if (env->xl != MXL_RV32) {
 +        mask |= SSTATUS64_UXL;
 +    }
      *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
      return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -
 +    if (env->xl != MXL_RV32) {
 +        mask |= SSTATUS64_UXL;
 +    }
      /* TODO: Use SXL not MXL. */
      *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
      return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
 +
 +    if (env->xl != MXL_RV32) {
 +        if ((val & SSTATUS64_UXL) != 0) {
 +            mask |= SSTATUS64_UXL;
 +        }
 +    }
      target_ulong newval = (env->mstatus & ~mask) | (val & mask);
      return write_mstatus(env, CSR_MSTATUS, newval);
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
                                       target_ulong val)
  {
      uint64_t mask = (target_ulong)-1;
 +    if ((val & VSSTATUS64_UXL) == 0) {
 +        mask &= ~VSSTATUS64_UXL;
 +    }
      env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
      return RISCV_EXCP_NONE;
  }
 --
-.30.1
+.31.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 61/61] target/riscv: Relax UXL field for debugging
-From: Alexander Wagner <alexander.wagner@ulal.de>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 the newest received byte. The rx_level variable is added to allow the use of
 the existing OpenTitan driver libraries.
 Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
+Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ target/riscv/csr.c | 8 ++++----
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+file changed, 4 insertions(+), 4 deletions(-)
 files changed, 22 insertions(+), 5 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
+--- a/target/riscv/csr.c
-+++ b/include/hw/char/ibex_uart.h
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
+         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
+         MSTATUS_TW | MSTATUS_VS;
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+-    if (xl != MXL_RV32) {
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
++    if (xl != MXL_RV32 || env->debugger) {
- REG32(OVRD, 0x24)
+         /*
- REG32(VAL, 0x28)
+          * RV32: MPV and GVA are not in mstatus. The current plan is to
- REG32(TIMEOUT_CTRL, 0x2c)
+          * add them to mstatush. For now, we just don't support it.
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
      uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
      uint32_t tx_level;
 +    uint32_t rx_level;
 +
      QEMUTimer *fifo_trigger_handle;
      uint64_t char_tx_time;
 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/ibex_uart.c
 +++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
  {
-     IbexUartState *s = opaque;
+     uint64_t mask = sstatus_v1_10_mask;
+     uint64_t sstatus = env->mstatus & mask;
--    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+-    if (env->xl != MXL_RV32) {
-+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
++    if (env->xl != MXL_RV32 || env->debugger) {
-+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
+         mask |= SSTATUS64_UXL;
          return 1;
      }
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
-     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
+ {
-     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+     target_ulong mask = (sstatus_v1_10_mask);
-+    /* The RXFULL is set after receiving a single byte
+-    if (env->xl != MXL_RV32) {
-+     * as the FIFO buffers are not yet implemented.
++    if (env->xl != MXL_RV32 || env->debugger) {
-+     */
+         mask |= SSTATUS64_UXL;
-+    s->uart_status |= R_STATUS_RXFULL_MASK;
+     }
-+    s->rx_level += 1;
+     /* TODO: Use SXL not MXL. */
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
-     if (size > rx_fifo_level) {
+ {
-         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
+     target_ulong mask = (sstatus_v1_10_mask);
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
-     s->uart_timeout_ctrl = 0x00000000;
+-    if (env->xl != MXL_RV32) {
++    if (env->xl != MXL_RV32 || env->debugger) {
-     s->tx_level = 0;
+         if ((val & SSTATUS64_UXL) != 0) {
-+    s->rx_level = 0;
+             mask |= SSTATUS64_UXL;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
          break;
      case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_FIFO_STATUS:
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
 --
-.30.1
+.31.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20 16:13:17 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1

for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:

target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.0

* Fixes for OpenTitan timer
 * Correction of OpenTitan PLIC stride length
 * RISC-V KVM support
 * Device tree code cleanup
 * Support for the Zve64f and Zve32f extensions
 * OpenSBI binary loading support for the Spike machine
 * Removal of OpenSBI ELFs
 * Support for the UXL field in xstatus

----------------------------------------------------------------
Anup Patel (3):
      hw/riscv: spike: Allow using binary firmware as bios
      hw/riscv: Remove macros for ELF BIOS image names
      roms/opensbi: Remove ELF images

Frank Chang (17):
      target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
      target/riscv: rvv-1.0: Add Zve64f support for configuration insns
      target/riscv: rvv-1.0: Add Zve64f support for load and store insns
      target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
      target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
      target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
      target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
      target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
      target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
      target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
      target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
      target/riscv: rvv-1.0: Add Zve32f support for configuration insns
      target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
      target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
      target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
      target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
      target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

LIU Zhiwei (23):
      target/riscv: Adjust pmpcfg access with mxl
      target/riscv: Don't save pc when exception return
      target/riscv: Sign extend link reg for jal and jalr
      target/riscv: Sign extend pc for different XLEN
      target/riscv: Create xl field in env
      target/riscv: Ignore the pc bits above XLEN
      target/riscv: Extend pc for runtime pc write
      target/riscv: Use gdb xml according to max mxlen
      target/riscv: Relax debug check for pm write
      target/riscv: Adjust csr write mask with XLEN
      target/riscv: Create current pm fields in env
      target/riscv: Alloc tcg global for cur_pm[mask|base]
      target/riscv: Calculate address according to XLEN
      target/riscv: Split pm_enabled into mask and base
      target/riscv: Split out the vill from vtype
      target/riscv: Adjust vsetvl according to XLEN
      target/riscv: Remove VILL field in VTYPE
      target/riscv: Fix check range for first fault only
      target/riscv: Adjust vector address with mask
      target/riscv: Adjust scalar reg in vector with XLEN
      target/riscv: Set default XLEN for hypervisor
      target/riscv: Enable uxl field write
      target/riscv: Relax UXL field for debugging

Thomas Huth (1):
      softmmu/device_tree: Silence compiler warning with --enable-sanitizers

Wilfred Mallawa (3):
      hw: timer: ibex_timer: Fixup reading w/o register
      riscv: opentitan: fixup plic stride len
      hw: timer: ibex_timer: update/add reg address

Yanan Wang (1):
      softmmu/device_tree: Remove redundant pointer assignment

Yifei Jiang (13):
      update-linux-headers: Add asm-riscv/kvm.h
      target/riscv: Add target/riscv/kvm.c to place the public kvm interface
      target/riscv: Implement function kvm_arch_init_vcpu
      target/riscv: Implement kvm_arch_get_registers
      target/riscv: Implement kvm_arch_put_registers
      target/riscv: Support start kernel directly by KVM
      target/riscv: Support setting external interrupt by KVM
      target/riscv: Handle KVM_EXIT_RISCV_SBI exit
      target/riscv: Add host cpu type
      target/riscv: Add kvm_riscv_get/put_regs_timer
      target/riscv: Implement virtual time adjusting with vm state changing
      target/riscv: Support virtual time context synchronization
      target/riscv: enable riscv kvm accel

meson.build                                    |   2 +
 include/hw/char/riscv_htif.h                   |   5 +-
 include/hw/riscv/boot.h                        |   3 +-
 include/hw/riscv/spike.h                       |   1 +
 include/hw/timer/ibex_timer.h                  |   1 -
 linux-headers/asm-riscv/kvm.h                  | 128 ++++++
 target/riscv/cpu.h                             |  58 ++-
 target/riscv/cpu_bits.h                        |   3 +
 target/riscv/helper.h                          |   4 +-
 target/riscv/kvm_riscv.h                       |  25 ++
 target/riscv/sbi_ecall_interface.h             |  72 ++++
 hw/char/riscv_htif.c                           |  33 +-
 hw/intc/sifive_plic.c                          |  20 +-
 hw/riscv/boot.c                                |  16 +-
 hw/riscv/opentitan.c                           |   2 +-
 hw/riscv/spike.c                               |  45 ++-
 hw/riscv/virt.c                                |  83 ++--
 hw/timer/ibex_timer.c                          |  25 +-
 softmmu/device_tree.c                          |  11 +-
 target/riscv/cpu.c                             |  77 +++-
 target/riscv/cpu_helper.c                      |  99 ++---
 target/riscv/csr.c                             |  90 ++++-
 target/riscv/gdbstub.c                         |  71 +++-
 target/riscv/kvm-stub.c                        |  30 ++
 target/riscv/kvm.c                             | 535 +++++++++++++++++++++++++
 target/riscv/machine.c                         |  46 ++-
 target/riscv/op_helper.c                       |   7 +-
 target/riscv/pmp.c                             |  12 +-
 target/riscv/translate.c                       |  94 +++--
 target/riscv/vector_helper.c                   |  39 +-
 target/riscv/insn_trans/trans_privileged.c.inc |   9 +-
 target/riscv/insn_trans/trans_rva.c.inc        |   9 +-
 target/riscv/insn_trans/trans_rvd.c.inc        |  19 +-
 target/riscv/insn_trans/trans_rvf.c.inc        |  19 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |  39 +-
 target/riscv/insn_trans/trans_rvv.c.inc        | 225 +++++++++--
 .gitlab-ci.d/opensbi.yml                       |   2 -
 pc-bios/meson.build                            |   2 -
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
 roms/Makefile                                  |   2 -
 target/riscv/meson.build                       |   1 +
 42 files changed, 1608 insertions(+), 356 deletions(-)
 create mode 100644 linux-headers/asm-riscv/kvm.h
 create mode 100644 target/riscv/kvm_riscv.h
 create mode 100644 target/riscv/sbi_ecall_interface.h
 create mode 100644 target/riscv/kvm-stub.c
 create mode 100644 target/riscv/kvm.c
 delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/timer/ibex_timer.h |  1 -
 hw/timer/ibex_timer.c         | 14 +++++---------
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -XXX,XX +XXX,XX @@ struct IbexTimerState {
     uint32_t timer_compare_upper0;
     uint32_t timer_intr_enable;
     uint32_t timer_intr_state;
-    uint32_t timer_intr_test;
 
     uint32_t timebase_freq;
 
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_reset(DeviceState *dev)
     s->timer_compare_upper0 = 0xFFFFFFFF;
     s->timer_intr_enable = 0x00000000;
     s->timer_intr_state = 0x00000000;
-    s->timer_intr_test = 0x00000000;
 
     ibex_timer_update_irqs(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
         retvalue = s->timer_intr_state;
         break;
     case R_INTR_TEST:
-        retvalue = s->timer_intr_test;
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Attempted to read INTR_TEST, a write only register");
         break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
         s->timer_intr_state &= ~val;
         break;
     case R_INTR_TEST:
-        s->timer_intr_test = val;
-        if (s->timer_intr_enable &
-            s->timer_intr_test &
-            R_INTR_ENABLE_IE_0_MASK) {
+        if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
             qemu_set_irq(s->irq, true);
         }
@@ -XXX,XX +XXX,XX @@ static int ibex_timer_post_load(void *opaque, int version_id)
 
 static const VMStateDescription vmstate_ibex_timer = {
     .name = TYPE_IBEX_TIMER,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .post_load = ibex_timer_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(timer_ctrl, IbexTimerState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ibex_timer = {
         VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
         VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
         VMSTATE_UINT32(timer_intr_state, IbexTimerState),
-        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.31.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

The following change was made to rectify incorrectly set stride length
on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
discovered whilst attempting to fix a bug where a timer_interrupt was
not serviced on TockOS-OpenTitan.

[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
-    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
-- 
2.31.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table

The CTRL register is @ 0x04.

This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS-OpenTitan.

2. Adds ALERT_TEST register as documented on [1], adding repective
   switch cases to error handle and later implement functionality.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/timer/ibex_timer.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "migration/vmstate.h"
 
-REG32(CTRL, 0x00)
+REG32(ALERT_TEST, 0x00)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
+REG32(CTRL, 0x04)
     FIELD(CTRL, ACTIVE, 0, 1)
 REG32(CFG0, 0x100)
     FIELD(CFG0, PRESCALE, 0, 12)
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
     uint64_t retvalue = 0;
 
     switch (addr >> 2) {
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                        "Attempted to read ALERT_TEST, a write only register");
+        break;
     case R_CTRL:
         retvalue = s->timer_ctrl;
         break;
@@ -XXX,XX +XXX,XX @@ static void ibex_timer_write(void *opaque, hwaddr addr,
     uint32_t val = val64;
 
     switch (addr >> 2) {
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
+        break;
     case R_CTRL:
         s->timer_ctrl = val;
         break;
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add asm-riscv/kvm.h for RISC-V KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 linux-headers/asm-riscv/kvm.h | 128 ++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 linux-headers/asm-riscv/kvm.h

diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/linux-headers/asm-riscv/kvm.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *     Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __LINUX_KVM_RISCV_H
+#define __LINUX_KVM_RISCV_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#define KVM_INTERRUPT_SET	-1U
+#define KVM_INTERRUPT_UNSET	-2U
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+};
+
+/* KVM Debug exit structure */
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+};
+
+/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_config {
+	unsigned long isa;
+};
+
+/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_core {
+	struct user_regs_struct regs;
+	unsigned long mode;
+};
+
+/* Possible privilege modes for kvm_riscv_core */
+#define KVM_RISCV_MODE_S	1
+#define KVM_RISCV_MODE_U	0
+
+/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_csr {
+	unsigned long sstatus;
+	unsigned long sie;
+	unsigned long stvec;
+	unsigned long sscratch;
+	unsigned long sepc;
+	unsigned long scause;
+	unsigned long stval;
+	unsigned long sip;
+	unsigned long satp;
+	unsigned long scounteren;
+};
+
+/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_timer {
+	__u64 frequency;
+	__u64 time;
+	__u64 compare;
+	__u64 state;
+};
+
+/* Possible states for kvm_riscv_timer */
+#define KVM_RISCV_TIMER_STATE_OFF	0
+#define KVM_RISCV_TIMER_STATE_ON	1
+
+#define KVM_REG_SIZE(id)		\
+	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
+#define KVM_REG_RISCV_TYPE_SHIFT	24
+
+/* Config registers are mapped as type 1 */
+#define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CONFIG_REG(name)	\
+	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
+
+/* Core registers are mapped as type 2 */
+#define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CORE_REG(name)	\
+		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
+
+/* Control and status registers are mapped as type 3 */
+#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_REG(name)	\
+		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
+
+/* Timer registers are mapped as type 4 */
+#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_TIMER_REG(name)	\
+		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
+
+/* F extension registers are mapped as type 5 */
+#define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_F_REG(name)	\
+		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
+
+/* D extension registers are mapped as type 6 */
+#define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_D_REG(name)	\
+		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
+
+#endif
+
+#endif /* __LINUX_KVM_RISCV_H */
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+    return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'translate.c',
   'm128_helper.c'
 ))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get isa info from kvm while kvm init.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+                                 uint64_t idx)
+{
+    uint64_t id = KVM_REG_RISCV | type | idx;
+
+    switch (riscv_cpu_mxl(env)) {
+    case MXL_RV32:
+        id |= KVM_REG_SIZE_U32;
+        break;
+    case MXL_RV64:
+        id |= KVM_REG_SIZE_U64;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -XXX,XX +XXX,XX @@ void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+    target_ulong isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    uint64_t id;
+
+    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+                          KVM_REG_RISCV_CONFIG_REG(isa));
+    ret = kvm_get_one_reg(cs, id, &isa);
+    if (ret) {
+        return ret;
+    }
+    env->misa_ext = isa;
+
+    return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
     return id;
 }
 
+#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
+                 KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
+                 KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
+
+#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
+    do { \
+        int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
+        if (ret) { \
+            return ret; \
+        } \
+    } while (0)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    target_ulong reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->pc = reg;
+
+    for (i = 1; i < 32; i++) {
+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+        ret = kvm_get_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+        env->gpr[i] = reg;
+    }
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
+    KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
+    KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
+    KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
+    KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
+    KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
+    KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
+    KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
+    KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
+    return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_get_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_put_registers(CPUState *cs, int level)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
         } \
     } while (0)
 
+#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
+    do { \
+        int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
+        if (ret) { \
+            return ret; \
+        } \
+    } while (0)
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_core(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    target_ulong reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->pc;
+    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    for (i = 1; i < 32; i++) {
+        uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+        reg = env->gpr[i];
+        ret = kvm_set_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_csr(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
+    KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
+    KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
+    KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
+    KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
+    KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
+    KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
+    KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
+    KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_fp(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
 
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_put_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_release_virq_post(int virq)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.

In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h  |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/kvm_riscv.h | 24 ++++++++++++
 hw/intc/sifive_plic.c    | 20 +++++++---
 hw/riscv/boot.c          | 16 +++++++-
 hw/riscv/virt.c          | 83 ++++++++++++++++++++++++++++------------
 target/riscv/cpu.c       |  8 ++++
 target/riscv/kvm-stub.c  | 25 ++++++++++++
 target/riscv/kvm.c       | 14 +++++++
 target/riscv/meson.build |  2 +-
 10 files changed, 164 insertions(+), 32 deletions(-)
 create mode 100644 target/riscv/kvm_riscv.h
 create mode 100644 target/riscv/kvm-stub.c

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
                                   hwaddr rom_size,
                                   uint32_t reset_vec_size,
                                   uint64_t kernel_entry);
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
 
 #endif /* RISCV_BOOT_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     /* Fields from here on are preserved across CPU reset. */
     QEMUTimer *timer; /* Internal timer */
+
+    hwaddr kernel_addr;
+    hwaddr fdt_addr;
 };
 
 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU KVM support -- RISC-V specific functions.
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_KVM_RISCV_H
+#define QEMU_KVM_RISCV_H
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+
+#endif
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "migration/vmstate.h"
 #include "hw/irq.h"
+#include "sysemu/kvm.h"
 
 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
 {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t context_stride, uint32_t aperture_size)
 {
     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
-    int i;
+    int i, j = 0;
+    SiFivePLICState *plic;
 
     assert(enable_stride == (enable_stride & -enable_stride));
     assert(context_stride == (context_stride & -context_stride));
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 
+    plic = SIFIVE_PLIC(dev);
     for (i = 0; i < num_harts; i++) {
         CPUState *cpu = qemu_get_cpu(hartid_base + i);
 
-        qdev_connect_gpio_out(dev, i,
-                              qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
-        qdev_connect_gpio_out(dev, num_harts + i,
-                              qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+        if (plic->addr_config[j].mode == PLICMode_M) {
+            j++;
+            qdev_connect_gpio_out(dev, num_harts + i,
+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+        }
+
+        if (plic->addr_config[j].mode == PLICMode_S) {
+            j++;
+            qdev_connect_gpio_out(dev, i,
+                                  qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
+        }
     }
 
     return dev;
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "elf.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/qtest.h"
+#include "sysemu/kvm.h"
 
 #include <libfdt.h>
 
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
         CPUState *cs = qemu_get_cpu(i);
         CPURISCVState *env = &RISCV_CPU(cs)->env;
 
-        if (riscv_has_ext(env, RVS)) {
+        if (kvm_enabled()) {
+            vals[i] = "S";
+        } else if (riscv_has_ext(env, RVS)) {
             vals[i] = "MS";
         } else {
             vals[i] = "M";
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
 
     return;
 }
+
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
+{
+    CPUState *cs;
+
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+        riscv_cpu->env.kernel_addr = kernel_addr;
+        riscv_cpu->env.fdt_addr = fdt_addr;
+    }
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
         "sifive,plic-1.0.0", "riscv,plic0"
     };
 
-    plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+    if (kvm_enabled()) {
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+    } else {
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+    }
 
     for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
-        plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
-        plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
-        plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
-        plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+        if (kvm_enabled()) {
+            plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+        } else {
+            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+        }
     }
 
     plic_phandles[socket] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 
         create_fdt_socket_memory(s, memmap, socket);
 
-        if (s->have_aclint) {
-            create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
-        } else {
-            create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+        if (!kvm_enabled()) {
+            if (s->have_aclint) {
+                create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
+            } else {
+                create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+            }
         }
 
         create_fdt_socket_plic(s, memmap, socket, phandle,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                 hart_count, &error_abort);
         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 
-        /* Per-socket CLINT */
-        riscv_aclint_swi_create(
-            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
-            base_hartid, hart_count, false);
-        riscv_aclint_mtimer_create(
-            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
-                RISCV_ACLINT_SWI_SIZE,
-            RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
-            RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
-            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
-
-        /* Per-socket ACLINT SSWI */
-        if (s->have_aclint) {
+        if (!kvm_enabled()) {
+            /* Per-socket CLINT */
             riscv_aclint_swi_create(
-                memmap[VIRT_ACLINT_SSWI].base +
-                    i * memmap[VIRT_ACLINT_SSWI].size,
-                base_hartid, hart_count, true);
+                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+                base_hartid, hart_count, false);
+            riscv_aclint_mtimer_create(
+                memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
+                    RISCV_ACLINT_SWI_SIZE,
+                RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+                RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+                RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+
+            /* Per-socket ACLINT SSWI */
+            if (s->have_aclint) {
+                riscv_aclint_swi_create(
+                    memmap[VIRT_ACLINT_SSWI].base +
+                        i * memmap[VIRT_ACLINT_SSWI].size,
+                    base_hartid, hart_count, true);
+            }
         }
 
         /* Per-socket PLIC hart topology configuration string */
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * so the "-bios" parameter is ignored and treated like "-bios none"
+     * when KVM is enabled.
+     */
+    if (kvm_enabled()) {
+        g_free(machine->firmware);
+        machine->firmware = g_strdup("none");
+    }
+
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
                                     RISCV32_BIOS_BIN, start_addr, NULL);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                               virt_memmap[VIRT_MROM].size, kernel_entry,
                               fdt_load_addr, machine->fdt);
 
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * So here setup kernel start address and fdt address.
+     * TODO:Support firmware loading and integrate to TCG start
+     */
+    if (kvm_enabled()) {
+        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
+    }
+
     /* SiFive Test MMIO device */
     sifive_test_create(memmap[VIRT_TEST].base);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "fpu/softfloat-helpers.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
 
 /* RISC-V CPU definitions */
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+
+#ifndef CONFIG_USER_ONLY
+    if (kvm_enabled()) {
+        kvm_riscv_reset_vcpu(cpu);
+    }
+#endif
 }
 
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU KVM RISC-V specific function stubs
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "kvm_riscv.h"
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
+#include "kvm_riscv.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     return 0;
 }
 
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    CPURISCVState *env = &cpu->env;
+
+    if (!kvm_enabled()) {
+        return;
+    }
+    env->pc = cpu->env.kernel_addr;
+    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
+    env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
+    env->satp = 0;
+}
+
 bool kvm_arch_cpu_check_are_resettable(void)
 {
     return true;
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'translate.c',
   'm128_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

When KVM is enabled, set the S-mode external interrupt through
kvm_riscv_set_irq function.

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #define QEMU_KVM_RISCV_H
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
     case IRQ_S_EXT:
     case IRQ_VS_EXT:
     case IRQ_M_EXT:
-        riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+        if (kvm_enabled()) {
+            kvm_riscv_set_irq(cpu, irq, level);
+        } else {
+            riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+        }
         break;
     default:
         g_assert_not_reached();
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm-stub.c
+++ b/target/riscv/kvm-stub.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 {
     abort();
 }
+
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
     env->satp = 0;
 }
 
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    int ret;
+    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+    if (irq != IRQ_S_EXT) {
+        perror("kvm riscv set irq != IRQ_S_EXT\n");
+        abort();
+    }
+
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+    if (ret < 0) {
+        perror("Set irq failed");
+        abort();
+    }
+}
+
 bool kvm_arch_cpu_check_are_resettable(void)
 {
     return true;
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
 target/riscv/kvm.c                 | 42 ++++++++++++++++-
 2 files changed, 113 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/sbi_ecall_interface.h

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_ECALL_INTERFACE_H__
+#define __SBI_ECALL_INTERFACE_H__
+
+/* clang-format off */
+
+/* SBI Extension IDs */
+#define SBI_EXT_0_1_SET_TIMER           0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR     0x2
+#define SBI_EXT_0_1_CLEAR_IPI           0x3
+#define SBI_EXT_0_1_SEND_IPI            0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I      0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN            0x8
+#define SBI_EXT_BASE                    0x10
+#define SBI_EXT_TIME                    0x54494D45
+#define SBI_EXT_IPI                     0x735049
+#define SBI_EXT_RFENCE                  0x52464E43
+#define SBI_EXT_HSM                     0x48534D
+
+/* SBI function IDs for BASE extension*/
+#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
+#define SBI_EXT_BASE_GET_IMP_ID         0x1
+#define SBI_EXT_BASE_GET_IMP_VERSION    0x2
+#define SBI_EXT_BASE_PROBE_EXT          0x3
+#define SBI_EXT_BASE_GET_MVENDORID      0x4
+#define SBI_EXT_BASE_GET_MARCHID        0x5
+#define SBI_EXT_BASE_GET_MIMPID         0x6
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER          0x0
+
+/* SBI function IDs for IPI extension*/
+#define SBI_EXT_IPI_SEND_IPI            0x0
+
+/* SBI function IDs for RFENCE extension*/
+#define SBI_EXT_RFENCE_REMOTE_FENCE_I       0x0
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA    0x1
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID  0x2
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x3
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x5
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
+
+/* SBI function IDs for HSM extension */
+#define SBI_EXT_HSM_HART_START          0x0
+#define SBI_EXT_HSM_HART_STOP           0x1
+#define SBI_EXT_HSM_HART_GET_STATUS     0x2
+
+#define SBI_HSM_HART_STATUS_STARTED     0x0
+#define SBI_HSM_HART_STATUS_STOPPED     0x1
+#define SBI_HSM_HART_STATUS_START_PENDING   0x2
+#define SBI_HSM_HART_STATUS_STOP_PENDING    0x3
+
+#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
+#define SBI_SPEC_VERSION_MAJOR_MASK     0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK     0xffffff
+#define SBI_EXT_VENDOR_START            0x09000000
+#define SBI_EXT_VENDOR_END              0x09FFFFFF
+/* clang-format on */
+
+#endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
+#include "sbi_ecall_interface.h"
+#include "chardev/char-fe.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+{
+    int ret = 0;
+    unsigned char ch;
+    switch (run->riscv_sbi.extension_id) {
+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+        ch = run->riscv_sbi.args[0];
+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+        break;
+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+        if (ret == sizeof(ch)) {
+            run->riscv_sbi.args[0] = ch;
+        } else {
+            run->riscv_sbi.args[0] = -1;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+                      __func__, run->riscv_sbi.extension_id);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
-    return 0;
+    int ret = 0;
+    switch (run->exit_reason) {
+    case KVM_EXIT_RISCV_SBI:
+        ret = kvm_riscv_handle_sbi(cs, run);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                      __func__, run->exit_reason);
+        ret = -1;
+        break;
+    }
+    return ret;
 }
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 #if defined(TARGET_RISCV32)
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 }
 #endif
 
+#if defined(CONFIG_KVM)
+static void riscv_host_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+#if defined(TARGET_RISCV32)
+    set_misa(env, MXL_RV32, 0);
+#elif defined(TARGET_RISCV64)
+    set_misa(env, MXL_RV64, 0);
+#endif
+}
+#endif
+
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .class_init = riscv_cpu_class_init,
     },
     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
+#if defined(CONFIG_KVM)
+    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
+#endif
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.

To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  7 +++++
 target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     hwaddr kernel_addr;
     hwaddr fdt_addr;
+
+    /* kvm timer */
+    bool kvm_timer_dirty;
+    uint64_t kvm_timer_time;
+    uint64_t kvm_timer_compare;
+    uint64_t kvm_timer_state;
+    uint64_t kvm_timer_frequency;
 };
 
 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "kvm_riscv.h"
 #include "sbi_ecall_interface.h"
 #include "chardev/char-fe.h"
+#include "migration/migration.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
 #define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
                  KVM_REG_RISCV_CSR_REG(name))
 
+#define RISCV_TIMER_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
+                 KVM_REG_RISCV_TIMER_REG(name))
+
 #define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
 
 #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
@@ -XXX,XX +XXX,XX @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
         } \
     } while (0)
 
+#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
+    do { \
+        int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
+        if (ret) { \
+            abort(); \
+        } \
+    } while (0)
+
+#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
+    do { \
+        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
+        if (ret) { \
+            abort(); \
+        } \
+    } while (0)
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
     return ret;
 }
 
+static void kvm_riscv_get_regs_timer(CPUState *cs)
+{
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (env->kvm_timer_dirty) {
+        return;
+    }
+
+    KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
+    KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
+    KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
+    KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
+
+    env->kvm_timer_dirty = true;
+}
+
+static void kvm_riscv_put_regs_timer(CPUState *cs)
+{
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (!env->kvm_timer_dirty) {
+        return;
+    }
+
+    KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
+    KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
+
+    /*
+     * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
+     * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
+     * doesn't matter that adaping in QEMU now.
+     * TODO If KVM changes, adapt here.
+     */
+    if (env->kvm_timer_state) {
+        KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
+    }
+
+    /*
+     * For now, migration will not work between Hosts with different timer
+     * frequency. Therefore, we should check whether they are the same here
+     * during the migration.
+     */
+    if (migration_is_running(migrate_get_current()->state)) {
+        KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
+        if (reg != env->kvm_timer_frequency) {
+            error_report("Dst Hosts timer frequency != Src Hosts");
+        }
+    }
+
+    env->kvm_timer_dirty = false;
+}
 
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

We hope that virtual time adjusts with vm state changing. When a vm
is stopped, guest virtual time should stop counting and kvm_timer
should be stopped. When the vm is resumed, guest virtual time should
continue to count and kvm_timer should be restored.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-12-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "sbi_ecall_interface.h"
 #include "chardev/char-fe.h"
 #include "migration/migration.h"
+#include "sysemu/runstate.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -XXX,XX +XXX,XX @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
+static void kvm_riscv_vm_state_change(void *opaque, bool running,
+                                      RunState state)
+{
+    CPUState *cs = opaque;
+
+    if (running) {
+        kvm_riscv_put_regs_timer(cs);
+    } else {
+        kvm_riscv_get_regs_timer(cs);
+    }
+}
+
 void kvm_arch_init_irq_routing(KVMState *s)
 {
 }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     CPURISCVState *env = &cpu->env;
     uint64_t id;
 
+    qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
+
     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
                           KVM_REG_RISCV_CONFIG_REG(isa));
     ret = kvm_get_one_reg(cs, id, &isa);
-- 
2.31.1

From: Yifei Jiang <jiangyifei@huawei.com>

Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_rv128 = {
     }
 };
 
+static bool kvmtimer_needed(void *opaque)
+{
+    return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->kvm_timer_dirty = true;
+    return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+    .name = "cpu/kvmtimer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = kvmtimer_needed,
+    .post_load = cpu_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_vector,
         &vmstate_pointermasking,
         &vmstate_rv128,
+        &vmstate_kvmtimer,
         NULL
     }
 };
-- 
2.31.1

From: Thomas Huth <thuth@redhat.com>

If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
complains:

.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
 in this function [-Werror=maybe-uninitialized]
     int namelen, retval;
                  ^~~~~~

It's a false warning since the while loop is always executed at least
once (p has to be non-NULL, otherwise the derefence in the if-statement
earlier will crash). Thus let's switch to a do-while loop here instead
to make the compiler happy in all cases.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220107133844.145039-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 softmmu/device_tree.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         return -1;
     }
 
-    while (p) {
+    do {
         name = p + 1;
         p = strchr(name, '/');
         namelen = p != NULL ? p - name : strlen(name);
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         }
 
         parent = retval;
-    }
+    } while (p);
 
     return retval;
 }
-- 
2.31.1

From: Yanan Wang <wangyanan55@huawei.com>

The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20220111032758.27804-1-wangyanan55@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 softmmu/device_tree.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
 int qemu_fdt_add_path(void *fdt, const char *path)
 {
     const char *name;
-    const char *p = path;
     int namelen, retval;
     int parent = 0;
 
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
     }
 
     do {
-        name = p + 1;
-        p = strchr(name, '/');
-        namelen = p != NULL ? p - name : strlen(name);
+        name = path + 1;
+        path = strchr(name, '/');
+        namelen = path != NULL ? path - name : strlen(name);
 
         retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
         if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
@@ -XXX,XX +XXX,XX @@ int qemu_fdt_add_path(void *fdt, const char *path)
         }
 
         parent = retval;
-    } while (p);
+    } while (path);
 
     return retval;
 }
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu.c        | 4 ++++
 target/riscv/cpu_helper.c | 5 ++++-
 target/riscv/csr.c        | 6 +++++-
 target/riscv/translate.c  | 2 ++
 5 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve64f;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
+        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve64f extension depends upon RVF.");
+            return;
+        }
         if (cpu->cfg.ext_j) {
             ext |= RVJ;
         }
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
     uint32_t flags = 0;
 
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV)) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (env->misa_ext & RVV) {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (env->misa_ext & RVV ||
+        cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve64f;
     bool hlsx;
     /* vector extension */
     bool vill;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
 1 file changed, 33 insertions(+), 6 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_32 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVV without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVF without GVEC IR */
@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
-        require_align(a->rd, s->lmul)) {
+        require_align(a->rd, s->lmul) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         TCGv_i64 t1;
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         unsigned int ofs = (8 << s->sew);
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         /* The instructions ignore LMUL and vector register group. */
@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
 static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_zve64f(DisasContext *s)
     return s->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVF with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dd(s, a->rd, a->rs2, a->vm);
+           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -XXX,XX +XXX,XX @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu.c        | 4 ++--
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/translate.c  | 2 ++
 5 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve32f;
         bool ext_zve64f;
 
         char *priv_spec;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
-        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve64f extension depends upon RVF.");
+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
             return;
         }
         if (cpu->cfg.ext_j) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException vs(CPURISCVState *env, int csrno)
     RISCVCPU *cpu = RISCV_CPU(cs);
 
     if (env->misa_ext & RVV ||
-        cpu->cfg.ext_zve64f) {
+        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve32f;
     bool ext_zve64f;
     bool hlsx;
     /* vector extension */
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
     ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Frank Chang <frank.chang@sifive.com>

Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve32f(DisasContext *s)
+{
+    /* RVV + Zve32f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve32f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve32f ? s->sew <= MO_32 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
     /* RVV + Zve64f = RVV. */
@@ -XXX,XX +XXX,XX @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
         require_align(a->rd, s->lmul) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -XXX,XX +XXX,XX @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

From: Anup Patel <apatel@ventanamicro.com>

Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.

The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/riscv_htif.h |  5 ++++-
 include/hw/riscv/spike.h     |  1 +
 hw/char/riscv_htif.c         | 33 +++++++++++++++++++----------
 hw/riscv/spike.c             | 41 ++++++++++++++++++++++--------------
 4 files changed, 52 insertions(+), 28 deletions(-)

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ extern const MemoryRegionOps htif_io_ops;
 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
     uint64_t st_size);
 
+/* Check if HTIF uses ELF symbols */
+bool htif_uses_elf_symbols(void);
+
 /* legacy pre qom */
 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr);
+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
 
 #endif
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -XXX,XX +XXX,XX @@ struct SpikeState {
 
 enum {
     SPIKE_MROM,
+    SPIKE_HTIF,
     SPIKE_CLINT,
     SPIKE_DRAM
 };
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
     .write = htif_mm_write,
 };
 
+bool htif_uses_elf_symbols(void)
+{
+    return (address_symbol_set == 3) ? true : false;
+}
+
 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr)
+    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
 {
-    uint64_t base = MIN(tohost_addr, fromhost_addr);
-    uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
-    uint64_t tohost_offset = tohost_addr - base;
-    uint64_t fromhost_offset = fromhost_addr - base;
+    uint64_t base, size, tohost_offset, fromhost_offset;
+
+    if (!htif_uses_elf_symbols()) {
+        fromhost_addr = nonelf_base;
+        tohost_addr = nonelf_base + 8;
+    }
+
+    base = MIN(tohost_addr, fromhost_addr);
+    size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
+    tohost_offset = tohost_addr - base;
+    fromhost_offset = fromhost_addr - base;
 
     HTIFState *s = g_malloc0(sizeof(HTIFState));
     s->address_space = address_space;
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
         htif_be_change, s, NULL, true);
-    if (address_symbol_set == 3) {
-        memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
-                              TYPE_HTIF_UART, size);
-        memory_region_add_subregion_overlap(address_space, base,
-                                            &s->mmio, 1);
-    }
+
+    memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
+                          TYPE_HTIF_UART, size);
+    memory_region_add_subregion_overlap(address_space, base,
+                                        &s->mmio, 1);
 
     return s;
 }
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 
 static const MemMapEntry spike_memmap[] = {
     [SPIKE_MROM] =     {     0x1000,     0xf000 },
+    [SPIKE_HTIF] =     {  0x1000000,     0x1000 },
     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
 };
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/htif");
     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
+    if (!htif_uses_elf_symbols()) {
+        qemu_fdt_setprop_cells(fdt, "/htif", "reg",
+            0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
+    }
 
     qemu_fdt_add_subnode(fdt, "/soc");
     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     if (cmdline) {
         qemu_fdt_add_subnode(fdt, "/chosen");
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
         machine->ram);
 
-    /* create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]));
-
     /* boot rom */
     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
                            memmap[SPIKE_MROM].size, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                     htif_symbol_callback);
     }
 
+    /* Load kernel */
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                          kernel_start_addr,
                                          htif_symbol_callback);
-
-        if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
-                                  end);
-        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = 0;
     }
 
+    /* Create device tree */
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+               riscv_is_32bit(&s->soc[0]));
+
+    /* Load initrd */
+    if (machine->kernel_filename && machine->initrd_filename) {
+        hwaddr start;
+        hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                       machine->ram_size, kernel_entry,
+                                       &start);
+        qemu_fdt_setprop_cell(s->fdt, "/chosen",
+                              "linux,initrd-start", start);
+        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+                              end);
+    }
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
                                    machine->ram_size, s->fdt);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     /* initialize HTIF using symbols found in load_kernel */
     htif_mm_init(system_memory, mask_rom,
-                 &s->soc[0].harts[0].env, serial_hd(0));
+                 &s->soc[0].harts[0].env, serial_hd(0),
+                 memmap[SPIKE_HTIF].base);
 }
 
 static void spike_machine_instance_init(Object *obj)
-- 
2.31.1

From: Anup Patel <apatel@ventanamicro.com>

Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h | 2 --
 hw/riscv/spike.c        | 4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 
 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
-#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
-#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
 
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     }
 
-- 
2.31.1

From: Anup Patel <apatel@ventanamicro.com>

Now that all RISC-V machines can use OpenSBI BIN images, we remove
OpenSBI ELF images and also exclude these images from BIOS build.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 .gitlab-ci.d/opensbi.yml                       |   2 --
 pc-bios/meson.build                            |   2 --
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
 roms/Makefile                                  |   2 --
 5 files changed, 6 deletions(-)
 delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml
index XXXXXXX..XXXXXXX 100644
--- a/.gitlab-ci.d/opensbi.yml
+++ b/.gitlab-ci.d/opensbi.yml
@@ -XXX,XX +XXX,XX @@ build-opensbi:
  artifacts:
    paths: # 'artifacts.zip' will contains the following files:
    - pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
-   - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    - pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
-   - pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
    - opensbi32-generic-stdout.log
    - opensbi32-generic-stderr.log
    - opensbi64-generic-stdout.log
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -XXX,XX +XXX,XX @@ blobs = files(
   'hppa-firmware.img',
   'opensbi-riscv32-generic-fw_dynamic.bin',
   'opensbi-riscv64-generic-fw_dynamic.bin',
-  'opensbi-riscv32-generic-fw_dynamic.elf',
-  'opensbi-riscv64-generic-fw_dynamic.elf',
   'npcm7xx_bootrom.bin',
 )
 
diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
deleted file mode 100644
index XXXXXXX..XXXXXXX
Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.elf and /dev/null differ
diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf b/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
deleted file mode 100644
index XXXXXXX..XXXXXXX
Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.elf and /dev/null differ
diff --git a/roms/Makefile b/roms/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -XXX,XX +XXX,XX @@ opensbi32-generic:
 		CROSS_COMPILE=$(riscv32_cross_prefix) \
 		PLATFORM="generic"
 	cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
-	cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 
 opensbi64-generic:
 	$(MAKE) -C opensbi \
 		CROSS_COMPILE=$(riscv64_cross_prefix) \
 		PLATFORM="generic"
 	cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
-	cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
 
 MESON = meson
 NINJA = ninja
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
+{
+    /* TODO: RV128 restriction check */
+    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+        return false;
+    }
+    return true;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
                                    target_ulong val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
     return RISCV_EXCP_NONE;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 {
     int i;
     uint8_t cfg_val;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
 
-    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "ignoring pmpcfg write - incorrect address\n");
-        return;
-    }
-
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
     int i;
     target_ulong cfg_val = 0;
     target_ulong val = 0;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         val = pmp_read_cfg(env, (reg_index * 4) + i);
         cfg_val |= (val << (i * 8));
     }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                          | 4 ++--
 target/riscv/op_helper.c                       | 4 ++--
 target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(csrr_i128, tl, env, int)
 DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
 DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
 
 #ifndef CONFIG_USER_ONLY
 
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt;
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
     return retpc;
 }
 
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
 static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
     if (has_ext(ctx, RVS)) {
-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 4 +---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                      | 25 ++++++++++++++++---
 .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |  5 ++--
 target/riscv/insn_trans/trans_rvv.c.inc       |  4 +--
 4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        dest = (int32_t)dest;
+    }
+    tcg_gen_movi_tl(cpu_pc, dest);
+}
+
+static void gen_set_pc(DisasContext *ctx, TCGv dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32s_tl(cpu_pc, dest);
+    } else {
+        tcg_gen_mov_tl(cpu_pc, dest);
+    }
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
         tcg_gen_goto_tb(n);
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_lookup_and_goto_ptr();
     }
 }
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     gen_helper_wfi(cpu_env);
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
+    gen_set_pc(ctx, cpu_pc);
     if (!has_ext(ctx, RVC)) {
         TCGv t0 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * FENCE_I is a no-op in QEMU,
      * however we need to end the translation block
      */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 static bool do_csr_post(DisasContext *ctx)
 {
     /* We may have changed important cpu state -- exit to main loop. */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
 
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.

Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 31 +++++++++++++++++++++++++++++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 34 ++--------------------------------
 target/riscv/csr.c        |  2 ++
 target/riscv/machine.c    | 10 ++++++++++
 5 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint32_t misa_mxl_max;  /* max mxl for this cpu */
     uint32_t misa_ext;      /* current extensions */
     uint32_t misa_ext_mask; /* max ext for this cpu */
+    uint32_t xl;            /* current xlen */
 
     /* 128-bit helpers upper part return value */
     target_ulong retxh;
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 }
 #endif
 
+#if defined(TARGET_RISCV32)
+#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+{
+    RISCVMXL xl = env->misa_mxl;
+#if !defined(CONFIG_USER_ONLY)
+    /*
+     * When emulating a 32-bit-only cpu, use RV32.
+     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
+     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
+     * back to RV64 for lower privs.
+     */
+    if (xl != MXL_RV32) {
+        switch (env->priv) {
+        case PRV_M:
+            break;
+        case PRV_U:
+            xl = get_field(env->mstatus, MSTATUS64_UXL);
+            break;
+        default: /* PRV_S | PRV_H */
+            xl = get_field(env->mstatus, MSTATUS64_SXL);
+            break;
+        }
+    }
+#endif
+    return xl;
+}
+#endif
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     /* mmte is supposed to have pm.current hardwired to 1 */
     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 #endif
+    env->xl = riscv_cpu_mxl(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
-static RISCVMXL cpu_get_xl(CPURISCVState *env)
-{
-#if defined(TARGET_RISCV32)
-    return MXL_RV32;
-#elif defined(CONFIG_USER_ONLY)
-    return MXL_RV64;
-#else
-    RISCVMXL xl = riscv_cpu_mxl(env);
-
-    /*
-     * When emulating a 32-bit-only cpu, use RV32.
-     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
-     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
-     * back to RV64 for lower privs.
-     */
-    if (xl != MXL_RV32) {
-        switch (env->priv) {
-        case PRV_M:
-            break;
-        case PRV_U:
-            xl = get_field(env->mstatus, MSTATUS64_UXL);
-            break;
-        default: /* PRV_S | PRV_H */
-            xl = get_field(env->mstatus, MSTATUS64_SXL);
-            break;
-        }
-    }
-    return xl;
-#endif
-}
-
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     }
 #endif
 
-    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
 
     *pflags = flags;
 }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     }
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
+    env->xl = cpu_recompute_xl(env);
 
     /*
      * Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
     }
     env->mstatus = mstatus;
+    env->xl = cpu_recompute_xl(env);
 
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     /* flush translation cache */
     tb_flush(env_cpu(env));
     env->misa_ext = val;
+    env->xl = riscv_cpu_mxl(env);
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kvmtimer = {
     }
 };
 
+static int riscv_cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->xl = cpu_recompute_xl(env);
+    return 0;
+}
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
     .minimum_version_id = 3,
+    .post_load = riscv_cpu_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    env->pc = value;
+
+    if (env->xl == MXL_RV32) {
+        env->pc = (int32_t)value;
+    } else {
+        env->pc = value;
+    }
 }
 
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    env->pc = tb->pc;
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)tb->pc;
+    } else {
+        env->pc = tb->pc;
+    }
 }
 
 static bool riscv_cpu_has_work(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
                           target_ulong *data)
 {
-    env->pc = data[0];
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)data[0];
+    } else {
+        env->pc = data[0];
+    }
 }
 
 static void riscv_cpu_reset(DeviceState *dev)
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+    CPUClass *cc = CPU_CLASS(mcc);
     int priv_version = 0;
     Error *local_err = NULL;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     switch (env->misa_mxl_max) {
 #ifdef TARGET_RISCV64
     case MXL_RV64:
+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
         break;
     case MXL_RV128:
         break;
 #endif
     case MXL_RV32:
+        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
         break;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
     cc->gdb_write_register = riscv_cpu_gdb_write_register;
     cc->gdb_num_core_regs = 33;
-#if defined(TARGET_RISCV32)
-    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-#elif defined(TARGET_RISCV64)
-    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-#endif
     cc->gdb_stop_before_watchpoint = true;
     cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
+    target_ulong tmp;
 
     if (n < 32) {
-        return gdb_get_regl(mem_buf, env->gpr[n]);
+        tmp = env->gpr[n];
     } else if (n == 32) {
-        return gdb_get_regl(mem_buf, env->pc);
+        tmp = env->pc;
+    } else {
+        return 0;
+    }
+
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        return gdb_get_reg32(mem_buf, tmp);
+    case MXL_RV64:
+        return gdb_get_reg64(mem_buf, tmp);
+    default:
+        g_assert_not_reached();
     }
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-
-    if (n == 0) {
-        /* discard writes to x0 */
-        return sizeof(target_ulong);
-    } else if (n < 32) {
-        env->gpr[n] = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+    int length = 0;
+    target_ulong tmp;
+
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        tmp = (int32_t)ldl_p(mem_buf);
+        length = 4;
+        break;
+    case MXL_RV64:
+        if (env->xl < MXL_RV64) {
+            tmp = (int32_t)ldq_p(mem_buf);
+        } else {
+            tmp = ldq_p(mem_buf);
+        }
+        length = 8;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    if (n > 0 && n < 32) {
+        env->gpr[n] = tmp;
     } else if (n == 32) {
-        env->pc = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+        env->pc = tmp;
     }
-    return 0;
+
+    return length;
 }
 
 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                                               cs->gdb_num_regs),
                                  "riscv-vector.xml", 0);
     }
-#if defined(TARGET_RISCV32)
-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
-                             1, "riscv-32bit-virtual.xml", 0);
-#elif defined(TARGET_RISCV64)
-    gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
-                             1, "riscv-64bit-virtual.xml", 0);
-#endif
+    switch (env->misa_mxl_max) {
+    case MXL_RV32:
+        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+                                 riscv_gdb_set_virtual,
+                                 1, "riscv-32bit-virtual.xml", 0);
+        break;
+    case MXL_RV64:
+        gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+                                 riscv_gdb_set_virtual,
+                                 1, "riscv-64bit-virtual.xml", 0);
+        break;
+    default:
+        g_assert_not_reached();
+    }
 
     gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
                              riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Write mask is representing the bits we care about.

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
 
 void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
 {
-    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+    target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
+    RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
 
 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 {
-    if (get_xl(ctx) < MXL_RV128) {
+    RISCVMXL xl = get_xl(ctx);
+    if (xl < MXL_RV128) {
         TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
 
         /*
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
             return do_csrw(ctx, a->csr, src);
         }
 
-        TCGv mask = tcg_constant_tl(-1);
+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+                                                     (target_ulong)-1);
         return do_csrrw(ctx, a->rd, a->csr, src, mask);
     } else {
         TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 
 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 {
-    if (get_xl(ctx) < MXL_RV128) {
+    RISCVMXL xl = get_xl(ctx);
+    if (xl < MXL_RV128) {
         TCGv src = tcg_constant_tl(a->rs1);
 
         /*
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
             return do_csrw(ctx, a->csr, src);
         }
 
-        TCGv mask = tcg_constant_tl(-1);
+        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+                                                     (target_ulong)-1);
         return do_csrrw(ctx, a->rd, a->csr, src, mask);
     } else {
         TCGv src = tcg_constant_tl(a->rs1);
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
 target/riscv/csr.c        | 19 +++++++++++++++++
 target/riscv/machine.c    |  1 +
 5 files changed, 68 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong upmmask;
     target_ulong upmbase;
 #endif
+    target_ulong cur_pmmask;
+    target_ulong cur_pmbase;
 
     float_status fp_status;
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags);
 
+void riscv_cpu_update_mask(CPURISCVState *env);
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 #endif
     env->xl = riscv_cpu_mxl(env);
+    riscv_cpu_update_mask(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pflags = flags;
 }
 
+void riscv_cpu_update_mask(CPURISCVState *env)
+{
+    target_ulong mask = -1, base = 0;
+    /*
+     * TODO: Current RVJ spec does not specify
+     * how the extension interacts with XLEN.
+     */
+#ifndef CONFIG_USER_ONLY
+    if (riscv_has_ext(env, RVJ)) {
+        switch (env->priv) {
+        case PRV_M:
+            if (env->mmte & M_PM_ENABLE) {
+                mask = env->mpmmask;
+                base = env->mpmbase;
+            }
+            break;
+        case PRV_S:
+            if (env->mmte & S_PM_ENABLE) {
+                mask = env->spmmask;
+                base = env->spmbase;
+            }
+            break;
+        case PRV_U:
+            if (env->mmte & U_PM_ENABLE) {
+                mask = env->upmmask;
+                base = env->upmbase;
+            }
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+#endif
+    if (env->xl == MXL_RV32) {
+        env->cur_pmmask = mask & UINT32_MAX;
+        env->cur_pmbase = base & UINT32_MAX;
+    } else {
+        env->cur_pmmask = mask;
+        env->cur_pmbase = base;
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
 
     /*
      * Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
     env->mmte = wpri_val | PM_EXT_DIRTY;
+    riscv_cpu_update_mask(env);
 
     /* Set XS and SD bits, since PM CSRs are dirty */
     mstatus = env->mstatus | MSTATUS_XS;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmmask = val;
+    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmmask = val;
+    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmmask = val;
+    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+        env->cur_pmmask = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmbase = val;
+    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmbase = val;
+    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmbase = val;
+    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+        env->cur_pmbase = val;
+    }
     env->mmte |= PM_EXT_DIRTY;
 
     /* Set XS and SD bits, since PM CSRs are dirty */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
     CPURISCVState *env = &cpu->env;
 
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
     return 0;
 }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
 /* globals for PM CSRs */
-static TCGv pm_mask[4];
-static TCGv pm_base[4];
+static TCGv pm_mask;
+static TCGv pm_base;
 
 #include "exec/gen-icount.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     TCGv temp[4];
     /* PointerMasking extension */
     bool pm_enabled;
-    TCGv pm_mask;
-    TCGv pm_base;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
         return src;
     } else {
         temp = temp_new(s);
-        tcg_gen_andc_tl(temp, src, s->pm_mask);
-        tcg_gen_or_tl(temp, temp, s->pm_base);
+        tcg_gen_andc_tl(temp, src, pm_mask);
+        tcg_gen_or_tl(temp, temp, pm_base);
         return temp;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
     ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
-    int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
-    ctx->pm_mask = pm_mask[priv];
-    ctx->pm_base = pm_base[priv];
-
     ctx->zero = tcg_constant_tl(0);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
                              "load_res");
     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
                              "load_val");
-#ifndef CONFIG_USER_ONLY
     /* Assign PM CSRs to tcg globals */
-    pm_mask[PRV_U] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
-    pm_base[PRV_U] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
-    pm_mask[PRV_S] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
-    pm_base[PRV_S] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
-    pm_mask[PRV_M] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
-    pm_base[PRV_M] =
-      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
-#endif
+    pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+                                 "pmmask");
+    pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+                                 "pmbase");
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 25 ++++++++++++-------------
 target/riscv/insn_trans/trans_rva.c.inc |  9 +++------
 target/riscv/insn_trans/trans_rvd.c.inc | 19 ++-----------------
 target/riscv/insn_trans/trans_rvf.c.inc | 19 ++-----------------
 target/riscv/insn_trans/trans_rvi.c.inc | 18 ++----------------
 5 files changed, 21 insertions(+), 69 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-/*
- * Generates address adjustment for PointerMasking
- */
-static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
+/* Compute a canonical address from a register plus offset. */
+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 {
-    TCGv temp;
-    if (!s->pm_enabled) {
-        /* Load unmodified address */
-        return src;
-    } else {
-        temp = temp_new(s);
-        tcg_gen_andc_tl(temp, src, pm_mask);
-        tcg_gen_or_tl(temp, temp, pm_base);
-        return temp;
+    TCGv addr = temp_new(ctx);
+    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+    tcg_gen_addi_tl(addr, src1, imm);
+    if (ctx->pm_enabled) {
+        tcg_gen_and_tl(addr, addr, pm_mask);
+        tcg_gen_or_tl(addr, addr, pm_base);
+    } else if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32u_tl(addr, addr);
     }
+    return addr;
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
 
 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+    TCGv src1 = get_address(ctx, a->rs1, 0);
 
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
-    src1 = gen_pm_adjust_address(ctx, src1);
     tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
     if (a->aq) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
-    src1 = gen_pm_adjust_address(ctx, src1);
+    src1 = get_address(ctx, a->rs1, 0);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
     /*
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     MemOp mop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src1 = get_address(ctx, a->rs1, 0);
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    src1 = gen_pm_adjust_address(ctx, src1);
     func(dest, src1, src2, ctx->mem_idx, mop);
 
     gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
 
     mark_fs_dirty(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     dest = cpu_fpr[a->rd];
     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
     gen_nanbox_s(dest, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = tcg_temp_new();
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
+    addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
 
     tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
     gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
 
 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.

This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  3 ++-
 target/riscv/cpu_helper.c | 24 ++++++------------------
 target/riscv/translate.c  | 12 ++++++++----
 3 files changed, 16 insertions(+), 23 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 FIELD(TB_FLAGS, XL, 20, 2)
 /* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
                            get_field(env->mstatus_hs, MSTATUS_VS));
     }
-    if (riscv_has_ext(env, RVJ)) {
-        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
-        bool pm_enabled = false;
-        switch (priv) {
-        case PRV_U:
-            pm_enabled = env->mmte & U_PM_ENABLE;
-            break;
-        case PRV_S:
-            pm_enabled = env->mmte & S_PM_ENABLE;
-            break;
-        case PRV_M:
-            pm_enabled = env->mmte & M_PM_ENABLE;
-            break;
-        default:
-            g_assert_not_reached();
-        }
-        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
-    }
 #endif
 
     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
+    if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
+    }
+    if (env->cur_pmbase != 0) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
+    }
 
     *pflags = flags;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* Space for 3 operands plus 1 extra for address computation. */
     TCGv temp[4];
     /* PointerMasking extension */
-    bool pm_enabled;
+    bool pm_mask_enabled;
+    bool pm_base_enabled;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (ctx->pm_enabled) {
+    if (ctx->pm_mask_enabled) {
         tcg_gen_and_tl(addr, addr, pm_mask);
-        tcg_gen_or_tl(addr, addr, pm_base);
     } else if (get_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }
+    if (ctx->pm_base_enabled) {
+        tcg_gen_or_tl(addr, addr, pm_base);
+    }
     return addr;
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->cs = cs;
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
-    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+    ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
+    ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
     ctx->zero = tcg_constant_tl(0);
 }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

We need not specially process vtype when XLEN changes.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h           |  1 +
 target/riscv/cpu_helper.c    |  3 +--
 target/riscv/csr.c           | 13 ++++++++++++-
 target/riscv/machine.c       |  5 +++--
 target/riscv/vector_helper.c |  3 ++-
 5 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong vl;
     target_ulong vstart;
     target_ulong vtype;
+    bool vill;
 
     target_ulong pc;
     target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         uint32_t maxsz = vlmax << sew;
         bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
                            (maxsz >= 8);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-                    FIELD_EX64(env->vtype, VTYPE, VILL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
         flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                     FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 static RISCVException read_vtype(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
-    *val = env->vtype;
+    uint64_t vill;
+    switch (env->xl) {
+    case MXL_RV32:
+        vill = (uint32_t)env->vill << 31;
+        break;
+    case MXL_RV64:
+        vill = (uint64_t)env->vill << 63;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    *val = (target_ulong)vill | env->vtype;
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static bool vector_needed(void *opaque)
 
 static const VMStateDescription vmstate_vector = {
     .name = "cpu/vector",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .needed = vector_needed,
     .fields = (VMStateField[]) {
             VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
             VMSTATE_UINTTL(env.vl, RISCVCPU),
             VMSTATE_UINTTL(env.vstart, RISCVCPU),
             VMSTATE_UINTTL(env.vtype, RISCVCPU),
+            VMSTATE_BOOL(env.vill, RISCVCPU),
             VMSTATE_END_OF_LIST()
         }
 };
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
         || (ediv != 0)
         || (reserved != 0)) {
         /* only set vill bit. */
-        env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+        env->vill = 1;
+        env->vtype = 0;
         env->vl = 0;
         env->vstart = 0;
         return 0;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 }
 #endif
 
+static inline int riscv_cpu_xlen(CPURISCVState *env)
+{
+    return 16 << env->xl;
+}
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
     uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
     uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
-    bool vill = FIELD_EX64(s2, VTYPE, VILL);
-    target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+    int xlen = riscv_cpu_xlen(env);
+    bool vill = (s2 >> (xlen - 1)) & 0x1;
+    target_ulong reserved = s2 &
+                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
 
     if (lmul & 4) {
         /* Fractional LMUL. */
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Only check the range that has passed the address translation.

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                                          cpu_mmu_index(env, false));
                 if (host) {
 #ifdef CONFIG_USER_ONLY
-                    if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+                    if (page_check_range(addr, offset, PAGE_READ) < 0) {
                         vl = i;
                         goto ProbeSuccess;
                     }
 #else
-                    probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+                    probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
 #endif
                 } else {
                     vl = i;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
 
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+    return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
 /*
  * This function checks watchpoint before real load operation.
  *
@@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
     target_ulong curlen = MIN(pagelen, len);
 
-    probe_access(env, addr, curlen, access_type,
+    probe_access(env, adjust_addr(env, addr), curlen, access_type,
                  cpu_mmu_index(env, false), ra);
     if (len > curlen) {
         addr += curlen;
         curlen = len - curlen;
-        probe_access(env, addr, curlen, access_type,
+        probe_access(env, adjust_addr(env, addr), curlen, access_type,
                      cpu_mmu_index(env, false), ra);
     }
 }
@@ -XXX,XX +XXX,XX @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + stride * i + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         k = 0;
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
         k = 0;
         while (k < nf) {
             abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
         if (!vm && !vext_elem_mask(v0, i)) {
             continue;
         }
-        addr = base + i * (nf << esz);
+        addr = adjust_addr(env, base + i * (nf << esz));
         if (i == 0) {
             probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
         } else {
@@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base,
                     break;
                 }
                 remain -= offset;
-                addr += offset;
+                addr = adjust_addr(env, addr + offset);
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ ProbeSuccess:
         }
         while (k < nf) {
             target_ulong addr = base + ((i * nf + k) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
             k++;
         }
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
         /* load/store rest of elements of current segment pointed by vstart */
         for (pos = off; pos < max_elems; pos++, env->vstart++) {
             target_ulong addr = base + ((pos + k * max_elems) << esz);
-            ldst_elem(env, addr, pos + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
         }
         k++;
     }
@@ -XXX,XX +XXX,XX @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     for (; k < nf; k++) {
         for (i = 0; i < max_elems; i++, env->vstart++) {
             target_ulong addr = base + ((i + k * max_elems) << esz);
-            ldst_elem(env, addr, i + k * max_elems, vd, ra);
+            ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
         }
     }
 
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
          */
         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+        if (riscv_has_ext(env, RVH)) {
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_SXL, env->misa_mxl);
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_UXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_SXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_UXL, env->misa_mxl);
+        }
     }
     env->mcause = 0;
     env->pc = env->resetvec;
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define COUNTEREN_IR         (1 << 2)
 #define COUNTEREN_HPM3       (1 << 3)
 
+/* vsstatus CSR bits */
+#define VSSTATUS64_UXL       0x0000000300000000ULL
+
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
+    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 static const target_ulong hip_writable_mask = MIP_VSSIP;
 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
+    RISCVMXL xl = riscv_cpu_mxl(env);
 
     /* flush tlb on mstatus fields that affect VM */
     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW | MSTATUS_VS;
 
-    if (riscv_cpu_mxl(env) != MXL_RV32) {
+    if (xl != MXL_RV32) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
          */
         mask |= MSTATUS_MPV | MSTATUS_GVA;
+        if ((val & MSTATUS64_UXL) != 0) {
+            mask |= MSTATUS64_UXL;
+        }
     }
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    RISCVMXL xl = riscv_cpu_mxl(env);
     if (xl > MXL_RV32) {
-        /* SXL and UXL fields are for now read only */
+        /* SXL field is for now read only */
         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
-        mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
     }
     env->mstatus = mstatus;
     env->xl = cpu_recompute_xl(env);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 {
     uint64_t mask = sstatus_v1_10_mask;
     uint64_t sstatus = env->mstatus & mask;
+    if (env->xl != MXL_RV32) {
+        mask |= SSTATUS64_UXL;
+    }
 
     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
-
+    if (env->xl != MXL_RV32) {
+        mask |= SSTATUS64_UXL;
+    }
     /* TODO: Use SXL not MXL. */
     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
+
+    if (env->xl != MXL_RV32) {
+        if ((val & SSTATUS64_UXL) != 0) {
+            mask |= SSTATUS64_UXL;
+        }
+    }
     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
     uint64_t mask = (target_ulong)-1;
+    if ((val & VSSTATUS64_UXL) == 0) {
+        mask &= ~VSSTATUS64_UXL;
+    }
     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
     return RISCV_EXCP_NONE;
 }
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW | MSTATUS_VS;
 
-    if (xl != MXL_RV32) {
+    if (xl != MXL_RV32 || env->debugger) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 {
     uint64_t mask = sstatus_v1_10_mask;
     uint64_t sstatus = env->mstatus & mask;
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
     /* TODO: Use SXL not MXL. */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (env->xl != MXL_RV32) {
+    if (env->xl != MXL_RV32 || env->debugger) {
         if ((val & SSTATUS64_UXL) != 0) {
             mask |= SSTATUS64_UXL;
         }
-- 
2.31.1