Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/26] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def:
   Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Third RISC-V PR for QEMU 6.2
-This PR includes:
+ - Add Zb[abcs] instruction support
- - Fix for vector CSR access
+ - Remove RVB support
- - Improvements to the Ibex UART device
+ - Bug fix of setting mstatus_hs.[SD|FS] bits
- - PMP improvements and bug fixes
+ - Mark some UART devices as 'input'
- - Hypervisor extension bug fixes
+ - QOMify PolarFire MMUART
- - ramfb support for the virt machine
+ - Fixes for sifive PDMA
- - Fast read support for SST flash
+ - Mark shakti_c as not user creatable
  - Improvements to the microchip_pfsoc machine
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Alistair Francis (1):
-      hw/char: disable ibex uart receive if the buffer is full
+      hw/riscv: shakti_c: Mark as not user creatable
-Asherah Connor (2):
+Bin Meng (5):
-      hw/riscv: Add fw_cfg support to virt
+      hw/char: ibex_uart: Register device in 'input' category
-      hw/riscv: allow ramfb on virt
+      hw/char: shakti_uart: Register device in 'input' category
+      hw/char: sifive_uart: Register device in 'input' category
-Bin Meng (3):
+      hw/dma: sifive_pdma: Fix Control.claim bit detection
-      hw/block: m25p80: Support fast read for SST flashes
+      hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
       hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
       docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
 Frank Chang (1):
-      target/riscv: fix vs() to return proper error code
+      target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
-Georg Kotheimer (6):
+Philipp Tomsich (16):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+      target/riscv: Introduce temporary in gen_add_uw()
-      target/riscv: Make VSTIP and VSEIP read-only in hip
+      target/riscv: fix clzw implementation to operate on arg1
-      target/riscv: Use background registers also for MSTATUS_MPV
+      target/riscv: clwz must ignore high bits (use shift-left & changed logic)
-      target/riscv: Fix read and write accesses to vsip and vsie
+      target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
-      target/riscv: Add proper two-stage lookup exception detection
+      target/riscv: Reassign instructions to the Zba-extension
-      target/riscv: Prevent lost illegal instruction exceptions
+      target/riscv: Remove the W-form instructions from Zbs
       target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
       target/riscv: Reassign instructions to the Zbs-extension
       target/riscv: Add instructions of the Zbc-extension
       target/riscv: Reassign instructions to the Zbb-extension
       target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
       target/riscv: Add a REQUIRE_32BIT macro
       target/riscv: Add rev8 instruction, removing grev/grevi
       target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
       target/riscv: Remove RVB (replaced by Zb[abcs])
       disas/riscv: Add Zb[abcs] instructions
-Jim Shu (3):
+Philippe Mathieu-Daudé (3):
-      target/riscv: propagate PMP permission to TLB page
+      hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
-      target/riscv: add log of PMP permission checking
+      hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
-      target/riscv: flush TLB pages if PMP permission has been changed
+      hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
+ include/hw/char/mchp_pfsoc_mmuart.h     |  17 +-
- docs/system/target-riscv.rst               |   1 +
+ target/riscv/cpu.h                      |  11 +-
- include/hw/char/ibex_uart.h                |   4 +
+ target/riscv/helper.h                   |   6 +-
- include/hw/riscv/microchip_pfsoc.h         |   1 +
+ target/riscv/insn32.decode              | 115 ++++-----
- include/hw/riscv/virt.h                    |   2 +
+ disas/riscv.c                           | 157 +++++++++++-
- target/riscv/cpu.h                         |   4 +
+ hw/char/ibex_uart.c                     |   1 +
- target/riscv/pmp.h                         |   4 +-
+ hw/char/mchp_pfsoc_mmuart.c             | 116 +++++++--
- hw/block/m25p80.c                          |   3 +
+ hw/char/shakti_uart.c                   |   1 +
- hw/char/ibex_uart.c                        |  23 +++-
+ hw/char/sifive_uart.c                   |   1 +
- hw/riscv/microchip_pfsoc.c                 |   6 +
+ hw/dma/sifive_pdma.c                    |  13 +-
- hw/riscv/virt.c                            |  33 ++++++
+ hw/riscv/shakti_c.c                     |   7 +
- target/riscv/cpu.c                         |   1 +
+ target/riscv/bitmanip_helper.c          |  65 +----
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
+ target/riscv/cpu.c                      |  30 +--
- target/riscv/csr.c                         |  77 +++++++------
+ target/riscv/translate.c                |  36 ++-
- target/riscv/pmp.c                         |  84 ++++++++++----
+ target/riscv/insn_trans/trans_rvb.c.inc | 419 ++++++++++----------------------
- target/riscv/translate.c                   | 179 +----------------------------
+files changed, 516 insertions(+), 479 deletions(-)
  hw/riscv/Kconfig                           |   1 +
 files changed, 367 insertions(+), 289 deletions(-)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

-New patch
+[PULL 01/26] target/riscv: Introduce temporary in gen_add_uw()
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Following the recent changes in translate.c, gen_add_uw() causes
+failures on CF3 and SPEC2017 due to the reuse of arg1.  Fix these
+regressions by introducing a temporary.
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
+Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(3)
+ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+ {
+-    tcg_gen_ext32u_tl(arg1, arg1);
+-    tcg_gen_add_tl(ret, arg1, arg2);
++    TCGv t = tcg_temp_new();
++    tcg_gen_ext32u_tl(t, arg1);
++    tcg_gen_add_tl(ret, t, arg2);
++    tcg_temp_free(t);
+ }
+ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+--
+.31.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-The current condition for the use of background registers only
+The refactored gen_clzw() uses ret as its argument, instead of arg1.
-considers the hypervisor load and store instructions,
+Fix it.
 but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
 Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
+ static void gen_clzw(TCGv ret, TCGv arg1)
-      */
+ {
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+-    tcg_gen_clzi_tl(ret, ret, 64);
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
++    tcg_gen_clzi_tl(ret, arg1, 64);
-         use_background = true;
+     tcg_gen_subi_tl(ret, ret, 32);
-     }
+ }
 --
-.30.1
+.31.1

-New patch
+[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Assume clzw being executed on a register that is not sign-extended, such
+as for the following sequence that uses (1ULL << 63) | 392 as the operand
+to clzw:
+    bseti    a2, zero, 63
+    addi    a2, a2, 392
+    clzw    a3, a2
+The correct result of clzw would be 23, but the current implementation
+returns -32 (as it performs a 64bit clz, which results in 0 leading zero
+bits, and then subtracts 32).
+Fix this by changing the implementation to:
+. shift the original register up by 32
+. performs a target-length (64bit) clz
+. return 32 if no bits are set
+Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
+correctly model the behaviour, as the instruction should not perform
+a zero-extensions on the input (after all, it is not a .uw instruction)
+and the result is always in the range 0..32 (so neither a sign-extension
+nor a zero-extension on the result will ever be needed).  Consequently,
+we do not set ctx->w and mark the instruction as EXT_NONE.
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
+Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
+file changed, 5 insertions(+), 3 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
+ static void gen_clzw(TCGv ret, TCGv arg1)
+ {
+-    tcg_gen_clzi_tl(ret, arg1, 64);
+-    tcg_gen_subi_tl(ret, ret, 32);
++    TCGv t = tcg_temp_new();
++    tcg_gen_shli_tl(t, arg1, 32);
++    tcg_gen_clzi_tl(ret, t, 32);
++    tcg_temp_free(t);
+ }
+ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+ {
+     REQUIRE_64BIT(ctx);
+     REQUIRE_EXT(ctx, RVB);
+-    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
++    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
+ }
+ static void gen_ctzw(TCGv ret, TCGv arg1)
+--
+.31.1

-New patch
+[PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The bitmanipulation ISA extensions will be ratified as individual
+small extension packages instead of a large B-extension.  The first
+new instructions through the door (these have completed public review)
+are Zb[abcs].
+This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
+these in target/riscv/cpu.[ch].
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 4 ++++
+ target/riscv/cpu.c | 4 ++++
+files changed, 8 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+         bool ext_u;
+         bool ext_h;
+         bool ext_v;
++        bool ext_zba;
++        bool ext_zbb;
++        bool ext_zbc;
++        bool ext_zbs;
+         bool ext_counters;
+         bool ext_ifencei;
+         bool ext_icsr;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+     /* This is experimental so mark with 'x-' */
+     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
++    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
++    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
++    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
++    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+--
+.31.1

-New patch
+[PULL 05/26] target/riscv: Reassign instructions to the Zba-extension
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The following instructions are part of Zba:
+ - add.uw (RV64 only)
+ - sh[123]add (RV32 and RV64)
+ - sh[123]add.uw (RV64-only)
+ - slli.uw (RV64-only)
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn32.decode              | 20 ++++++++++++--------
+ target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
+files changed, 23 insertions(+), 13 deletions(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+ vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+ vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
++# *** RV32 Zba Standard Extension ***
++sh1add     0010000 .......... 010 ..... 0110011 @r
++sh2add     0010000 .......... 100 ..... 0110011 @r
++sh3add     0010000 .......... 110 ..... 0110011 @r
++
++# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
++add_uw     0000100 .......... 000 ..... 0111011 @r
++sh1add_uw  0010000 .......... 010 ..... 0111011 @r
++sh2add_uw  0010000 .......... 100 ..... 0111011 @r
++sh3add_uw  0010000 .......... 110 ..... 0111011 @r
++slli_uw    00001 ............ 001 ..... 0011011 @sh
++
+ # *** RV32B Standard Extension ***
+ clz        011000 000000 ..... 001 ..... 0010011 @r2
+ ctz        011000 000001 ..... 001 ..... 0010011 @r2
+@@ -XXX,XX +XXX,XX @@ ror        0110000 .......... 101 ..... 0110011 @r
+ rol        0110000 .......... 001 ..... 0110011 @r
+ grev       0110100 .......... 101 ..... 0110011 @r
+ gorc       0010100 .......... 101 ..... 0110011 @r
+-sh1add     0010000 .......... 010 ..... 0110011 @r
+-sh2add     0010000 .......... 100 ..... 0110011 @r
+-sh3add     0010000 .......... 110 ..... 0110011 @r
+ bseti      00101. ........... 001 ..... 0010011 @sh
+ bclri      01001. ........... 001 ..... 0010011 @sh
+@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
+ rolw       0110000 .......... 001 ..... 0111011 @r
+ grevw      0110100 .......... 101 ..... 0111011 @r
+ gorcw      0010100 .......... 101 ..... 0111011 @r
+-sh1add_uw  0010000 .......... 010 ..... 0111011 @r
+-sh2add_uw  0010000 .......... 100 ..... 0111011 @r
+-sh3add_uw  0010000 .......... 110 ..... 0111011 @r
+-add_uw     0000100 .......... 000 ..... 0111011 @r
+ bsetiw     0010100 .......... 001 ..... 0011011 @sh5
+ bclriw     0100100 .......... 001 ..... 0011011 @sh5
+@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
+ greviw     0110100 .......... 101 ..... 0011011 @sh5
+ gorciw     0010100 .......... 101 ..... 0011011 @sh5
+-slli_uw    00001. ........... 001 ..... 0011011 @sh
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@
+ /*
+- * RISC-V translation routines for the RVB Standard Extension.
++ * RISC-V translation routines for the RVB draft and Zba Standard Extension.
+  *
+  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
++ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms and conditions of the GNU General Public License,
+@@ -XXX,XX +XXX,XX @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
++#define REQUIRE_ZBA(ctx) do {                    \
++    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
++        return false;                            \
++    }                                            \
++} while (0)
+ static void gen_clz(TCGv ret, TCGv arg1)
+ {
+@@ -XXX,XX +XXX,XX @@ GEN_SHADD(3)
+ #define GEN_TRANS_SHADD(SHAMT)                                             \
+ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+ {                                                                          \
+-    REQUIRE_EXT(ctx, RVB);                                                 \
++    REQUIRE_ZBA(ctx);                                                      \
+     return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
+ }
+@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
+                                     arg_sh##SHAMT##add_uw *a) \
+ {                                                             \
+     REQUIRE_64BIT(ctx);                                       \
+-    REQUIRE_EXT(ctx, RVB);                                    \
++    REQUIRE_ZBA(ctx);                                         \
+     return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+ {
+     REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBA(ctx);
+     return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
+ {
+     REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBA(ctx);
+     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
+ }
+--
+.31.1

-New patch
+[PULL 06/26] target/riscv: Remove the W-form instructions from Zbs
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
+instructions for Zbs (single-bit instructions).  Remove them.
+Note that these instructions had already been removed for the 0.93
+version of the draft-B extention and have not been present in the
+binutils patches circulating in January 2021.
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn32.decode              |  7 ----
+ target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
+files changed, 63 deletions(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+ packw      0000100 .......... 100 ..... 0111011 @r
+ packuw     0100100 .......... 100 ..... 0111011 @r
+-bsetw      0010100 .......... 001 ..... 0111011 @r
+-bclrw      0100100 .......... 001 ..... 0111011 @r
+-binvw      0110100 .......... 001 ..... 0111011 @r
+-bextw      0100100 .......... 101 ..... 0111011 @r
+ slow       0010000 .......... 001 ..... 0111011 @r
+ srow       0010000 .......... 101 ..... 0111011 @r
+ rorw       0110000 .......... 101 ..... 0111011 @r
+@@ -XXX,XX +XXX,XX @@ rolw       0110000 .......... 001 ..... 0111011 @r
+ grevw      0110100 .......... 101 ..... 0111011 @r
+ gorcw      0010100 .......... 101 ..... 0111011 @r
+-bsetiw     0010100 .......... 001 ..... 0011011 @sh5
+-bclriw     0100100 .......... 001 ..... 0011011 @sh5
+-binviw     0110100 .......... 001 ..... 0011011 @sh5
+ sloiw      0010000 .......... 001 ..... 0011011 @sh5
+ sroiw      0010000 .......... 101 ..... 0011011 @sh5
+ roriw      0110000 .......... 101 ..... 0011011 @sh5
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+     return gen_arith(ctx, a, EXT_NONE, gen_packuw);
+ }
+-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_NONE, gen_bset);
+-}
+-
+-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
+-}
+-
+-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+-}
+-
+-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
+-}
+-
+-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_NONE, gen_binv);
+-}
+-
+-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
+-}
+-
+-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_NONE, gen_bext);
+-}
+-
+ static bool trans_slow(DisasContext *ctx, arg_slow *a)
+ {
+     REQUIRE_64BIT(ctx);
+--
+.31.1

-New patch
+[PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The Zb[abcs] ratification package does not include the proposed
+shift-one instructions. There currently is no clear plan to whether
+these (or variants of them) will be ratified as Zbo (or a different
+extension) or what the timeframe for such a decision could be.
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn32.decode              |  8 ---
+ target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
+files changed, 78 deletions(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ bset       0010100 .......... 001 ..... 0110011 @r
+ bclr       0100100 .......... 001 ..... 0110011 @r
+ binv       0110100 .......... 001 ..... 0110011 @r
+ bext       0100100 .......... 101 ..... 0110011 @r
+-slo        0010000 .......... 001 ..... 0110011 @r
+-sro        0010000 .......... 101 ..... 0110011 @r
+ ror        0110000 .......... 101 ..... 0110011 @r
+ rol        0110000 .......... 001 ..... 0110011 @r
+ grev       0110100 .......... 101 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ bseti      00101. ........... 001 ..... 0010011 @sh
+ bclri      01001. ........... 001 ..... 0010011 @sh
+ binvi      01101. ........... 001 ..... 0010011 @sh
+ bexti      01001. ........... 101 ..... 0010011 @sh
+-sloi       00100. ........... 001 ..... 0010011 @sh
+-sroi       00100. ........... 101 ..... 0010011 @sh
+ rori       01100. ........... 101 ..... 0010011 @sh
+ grevi      01101. ........... 101 ..... 0010011 @sh
+ gorci      00101. ........... 101 ..... 0010011 @sh
+@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+ packw      0000100 .......... 100 ..... 0111011 @r
+ packuw     0100100 .......... 100 ..... 0111011 @r
+-slow       0010000 .......... 001 ..... 0111011 @r
+-srow       0010000 .......... 101 ..... 0111011 @r
+ rorw       0110000 .......... 101 ..... 0111011 @r
+ rolw       0110000 .......... 001 ..... 0111011 @r
+ grevw      0110100 .......... 101 ..... 0111011 @r
+ gorcw      0010100 .......... 101 ..... 0111011 @r
+-sloiw      0010000 .......... 001 ..... 0011011 @sh5
+-sroiw      0010000 .......... 101 ..... 0011011 @sh5
+ roriw      0110000 .......... 101 ..... 0011011 @sh5
+ greviw     0110100 .......... 101 ..... 0011011 @sh5
+ gorciw     0010100 .......... 101 ..... 0011011 @sh5
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
+     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
+ }
+-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+-{
+-    tcg_gen_not_tl(ret, arg1);
+-    tcg_gen_shl_tl(ret, ret, arg2);
+-    tcg_gen_not_tl(ret, ret);
+-}
+-
+-static bool trans_slo(DisasContext *ctx, arg_slo *a)
+-{
+-    REQUIRE_EXT(ctx, RVB);
+-    return gen_shift(ctx, a, EXT_NONE, gen_slo);
+-}
+-
+-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+-{
+-    REQUIRE_EXT(ctx, RVB);
+-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
+-}
+-
+-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+-{
+-    tcg_gen_not_tl(ret, arg1);
+-    tcg_gen_shr_tl(ret, ret, arg2);
+-    tcg_gen_not_tl(ret, ret);
+-}
+-
+-static bool trans_sro(DisasContext *ctx, arg_sro *a)
+-{
+-    REQUIRE_EXT(ctx, RVB);
+-    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+-}
+-
+-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+-{
+-    REQUIRE_EXT(ctx, RVB);
+-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
+-}
+-
+ static bool trans_ror(DisasContext *ctx, arg_ror *a)
+ {
+     REQUIRE_EXT(ctx, RVB);
+@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+     return gen_arith(ctx, a, EXT_NONE, gen_packuw);
+ }
+-static bool trans_slow(DisasContext *ctx, arg_slow *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_NONE, gen_slo);
+-}
+-
+-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
+-}
+-
+-static bool trans_srow(DisasContext *ctx, arg_srow *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+-}
+-
+-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+-{
+-    REQUIRE_64BIT(ctx);
+-    REQUIRE_EXT(ctx, RVB);
+-    ctx->w = true;
+-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
+-}
+-
+ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+ {
+     TCGv_i32 t1 = tcg_temp_new_i32();
+--
+.31.1

-New patch
+[PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The following instructions are part of Zbs:
+ - b{set,clr,ext,inv}
+ - b{set,clr,ext,inv}i
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn32.decode              | 17 +++++++++--------
+ target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
+files changed, 24 insertions(+), 18 deletions(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
+ minu       0000101 .......... 101 ..... 0110011 @r
+ max        0000101 .......... 110 ..... 0110011 @r
+ maxu       0000101 .......... 111 ..... 0110011 @r
+-bset       0010100 .......... 001 ..... 0110011 @r
+-bclr       0100100 .......... 001 ..... 0110011 @r
+-binv       0110100 .......... 001 ..... 0110011 @r
+-bext       0100100 .......... 101 ..... 0110011 @r
+ ror        0110000 .......... 101 ..... 0110011 @r
+ rol        0110000 .......... 001 ..... 0110011 @r
+ grev       0110100 .......... 101 ..... 0110011 @r
+ gorc       0010100 .......... 101 ..... 0110011 @r
+-bseti      00101. ........... 001 ..... 0010011 @sh
+-bclri      01001. ........... 001 ..... 0010011 @sh
+-binvi      01101. ........... 001 ..... 0010011 @sh
+-bexti      01001. ........... 101 ..... 0010011 @sh
+ rori       01100. ........... 101 ..... 0010011 @sh
+ grevi      01101. ........... 101 ..... 0010011 @sh
+ gorci      00101. ........... 101 ..... 0010011 @sh
+@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
+ greviw     0110100 .......... 101 ..... 0011011 @sh5
+ gorciw     0010100 .......... 101 ..... 0011011 @sh5
++# *** RV32 Zbs Standard Extension ***
++bclr       0100100 .......... 001 ..... 0110011 @r
++bclri      01001. ........... 001 ..... 0010011 @sh
++bext       0100100 .......... 101 ..... 0110011 @r
++bexti      01001. ........... 101 ..... 0010011 @sh
++binv       0110100 .......... 001 ..... 0110011 @r
++binvi      01101. ........... 001 ..... 0010011 @sh
++bset       0010100 .......... 001 ..... 0110011 @r
++bseti      00101. ........... 001 ..... 0010011 @sh
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@
+ /*
+- * RISC-V translation routines for the RVB draft and Zba Standard Extension.
++ * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+  *
+  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+@@ -XXX,XX +XXX,XX @@
+     }                                            \
+ } while (0)
++#define REQUIRE_ZBS(ctx) do {                    \
++    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
++        return false;                            \
++    }                                            \
++} while (0)
++
+ static void gen_clz(TCGv ret, TCGv arg1)
+ {
+     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+ }
+-
+ static bool trans_clz(DisasContext *ctx, arg_clz *a)
+ {
+     REQUIRE_EXT(ctx, RVB);
+@@ -XXX,XX +XXX,XX @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+ static bool trans_bset(DisasContext *ctx, arg_bset *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift(ctx, a, EXT_NONE, gen_bset);
+ }
+ static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
+ static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+ }
+ static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
+ static bool trans_binv(DisasContext *ctx, arg_binv *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift(ctx, a, EXT_NONE, gen_binv);
+ }
+ static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
+ static bool trans_bext(DisasContext *ctx, arg_bext *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift(ctx, a, EXT_NONE, gen_bext);
+ }
+ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
+ {
+-    REQUIRE_EXT(ctx, RVB);
++    REQUIRE_ZBS(ctx);
+     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
+ }
+--
+.31.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 09/26] target/riscv: Add instructions of the Zbc-extension
-From: Jim Shu <cwshu@andestech.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+The following instructions are part of Zbc:
-Fix it by propagating PMP permission to TLB page permission.
+ - clmul
  - clmulh
  - clmulr
-PMP permission checking also use MMU-style API to change TLB permission
+Note that these instructions were already defined in the pre-0.93 and
-and size.
+the 0.93 draft-B proposals, but had not been omitted in the earlier
 addition of draft-B to QEmu.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/helper.h                   |  2 ++
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+ target/riscv/insn32.decode              |  5 ++++
- target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
+ target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++
-files changed, 125 insertions(+), 43 deletions(-)
+ target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
 files changed, 65 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
+--- a/target/riscv/helper.h
-+++ b/target/riscv/pmp.h
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-     target_ulong val);
+ DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+ DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
++DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
++DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+    target_ulong mode);
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+ /* Special functions */
-                          target_ulong *tlb_size);
+ DEF_HELPER_2(csrr, tl, env, int)
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  void pmp_update_rule_nums(CPURISCVState *env);
  uint32_t pmp_get_num_rules(CPURISCVState *env);
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
  #endif
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/insn32.decode
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
+@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
-     env->load_res = -1;
+ greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 +# *** RV32 Zbc Standard Extension ***
 +clmul      0000101 .......... 001 ..... 0110011 @r
 +clmulh     0000101 .......... 011 ..... 0110011 @r
 +clmulr     0000101 .......... 010 ..... 0110011 @r
 +
  # *** RV32 Zbs Standard Extension ***
  bclr       0100100 .......... 001 ..... 0110011 @r
  bclri      01001. ........... 001 ..... 0010011 @sh
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
 + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
  {
      return do_gorc(rs1, rs2, 32);
  }
++
-+/*
++target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
 + * get_physical_address_pmp - check PMP permission for this physical address
 + *
 + * Match the PMP region and check permission for this physical address and it's
 + * TLB page. Returns 0 if the permission checking was successful
 + *
 + * @env: CPURISCVState
 + * @prot: The returned protection attributes
 + * @tlb_size: TLB page size containing addr. It could be modified after PMP
 + *            permission checking. NULL if not set TLB page for addr.
 + * @addr: The physical address to be checked permission
 + * @access_type: The type of MMU access
 + * @mode: Indicates current privilege level.
 + */
 +static int get_physical_address_pmp(CPURISCVState *env, int *prot,
 +                                    target_ulong *tlb_size, hwaddr addr,
 +                                    int size, MMUAccessType access_type,
 +                                    int mode)
 +{
-+    pmp_priv_t pmp_priv;
++    target_ulong result = 0;
 +    target_ulong tlb_size_pmp = 0;
 +
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
++    for (int i = 0; i < TARGET_LONG_BITS; i++) {
-+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
++        if ((rs2 >> i) & 1) {
-+        return TRANSLATE_SUCCESS;
++            result ^= (rs1 << i);
 +    }
 +
 +    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 +                            mode)) {
 +        *prot = 0;
 +        return TRANSLATE_PMP_FAIL;
 +    }
 +
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
 +    }
 +
-+    return TRANSLATE_SUCCESS;
++    return result;
 +}
 +
- /* get_physical_address - get the physical address for this virtual address
++target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
-  *
++{
-  * Do a page table walk to obtain the physical address corresponding to a
++    target_ulong result = 0;
-@@ -XXX,XX +XXX,XX @@ restart:
++
-             pte_addr = base + idx * ptesize;
++    for (int i = 0; i < TARGET_LONG_BITS; i++) {
-         }
++        if ((rs2 >> i) & 1) {
++            result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
 -        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 -            1 << MMU_DATA_LOAD, PRV_S)) {
 +        int pmp_prot;
 +        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
 +                                               sizeof(target_ulong),
 +                                               MMU_DATA_LOAD, PRV_S);
 +        if (pmp_ret != TRANSLATE_SUCCESS) {
              return TRANSLATE_PMP_FAIL;
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
  #ifndef CONFIG_USER_ONLY
      vaddr im_address;
      hwaddr pa = 0;
 -    int prot, prot2;
 +    int prot, prot2, prot_pmp;
      bool pmp_violation = false;
      bool first_stage_error = true;
      bool two_stage_lookup = false;
      int ret = TRANSLATE_FAIL;
      int mode = mmu_idx;
 -    target_ulong tlb_size = 0;
 +    /* default TLB page size */
 +    target_ulong tlb_size = TARGET_PAGE_SIZE;
      env->guest_phys_fault_addr = 0;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
              prot &= prot2;
 -            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -                (ret == TRANSLATE_SUCCESS) &&
 -                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -                ret = TRANSLATE_PMP_FAIL;
 +            if (ret == TRANSLATE_SUCCESS) {
 +                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                               size, access_type, mode);
 +                prot &= prot_pmp;
              }
              if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        "%s address=%" VADDR_PRIx " ret %d physical "
                        TARGET_FMT_plx " prot %d\n",
                        __func__, address, ret, pa, prot);
 -    }
 -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -        (ret == TRANSLATE_SUCCESS) &&
 -        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -        ret = TRANSLATE_PMP_FAIL;
 +        if (ret == TRANSLATE_SUCCESS) {
 +            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                           size, access_type, mode);
 +            prot &= prot_pmp;
 +        }
-     }
-+
-     if (ret == TRANSLATE_PMP_FAIL) {
-         pmp_violation = true;
-     }
-     if (ret == TRANSLATE_SUCCESS) {
--        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
--            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
--                         prot, mmu_idx, tlb_size);
--        } else {
--            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--                         prot, mmu_idx, TARGET_PAGE_SIZE);
--        }
-+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-+                     prot, mmu_idx, tlb_size);
-         return true;
-     } else if (probe) {
-         return false;
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
-     return result;
- }
-+/*
-+ * Check if the address has required RWX privs when no PMP entry is matched.
-+ */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode)
-+{
-+    bool ret;
-+
-+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-+        /*
-+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
-+         * or no PMP entry matches an M-Mode access, the access succeeds.
-+         */
-+        ret = true;
-+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-+    } else {
-+        /*
-+         * Other modes are not allowed to succeed if they don't * match a rule,
-+         * but there are rules. We've checked for no rule earlier in this
-+         * function.
-+         */
-+        ret = false;
-+        *allowed_privs = 0;
 +    }
 +
-+    return ret;
++    return result;
 +}
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
 + * RISC-V translation routines for the Zb[acs] Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBC(ctx) do {                    \
 +    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_ZBS(ctx) do {                    \
      if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
      REQUIRE_ZBA(ctx);
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
  }
 +
 +static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
 +{
 +    REQUIRE_ZBC(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
 +}
 +
++static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
- /*
++{
-  * Public Interface
++     gen_helper_clmulr(dst, src1, src2);
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
++     tcg_gen_shri_tl(dst, dst, 1);
-  * Check if the address has required RWX privs to complete desired operation
++}
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
      int i = 0;
      int ret = -1;
      int pmp_size = 0;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
      /* No rule matched */
      if (ret == -1) {
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
 -
  /*
   * Handle a write to a pmpcfg CSP
   */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
      return false;
  }
 +
-+/*
++static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
 + * Convert PMP privilege to TLB page privilege.
 + */
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
 +{
-+    int prot = 0;
++    REQUIRE_ZBC(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
 +}
 +
-+    if (pmp_priv & PMP_READ) {
++static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
-+        prot |= PAGE_READ;
++{
-+    }
++    REQUIRE_ZBC(ctx);
-+    if (pmp_priv & PMP_WRITE) {
++    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
 +        prot |= PAGE_WRITE;
 +    }
 +    if (pmp_priv & PMP_EXEC) {
 +        prot |= PAGE_EXEC;
 +    }
 +
 +    return prot;
 +}
 --
-.30.1
+.31.1

-New patch
+[PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
 This reassigns the instructions that are part of Zbb into it, with the
 notable exceptions of the instructions (rev8, zext.w and orc.b) that
 changed due to gorci, grevi and pack not being part of Zb[abcs].
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Acked-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/insn32.decode              | 40 ++++++++++---------
  target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
 files changed, 50 insertions(+), 41 deletions(-)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
  sh3add_uw  0010000 .......... 110 ..... 0111011 @r
  slli_uw    00001 ............ 001 ..... 0011011 @sh
 -# *** RV32B Standard Extension ***
 +# *** RV32 Zbb Standard Extension ***
 +andn       0100000 .......... 111 ..... 0110011 @r
  clz        011000 000000 ..... 001 ..... 0010011 @r2
 -ctz        011000 000001 ..... 001 ..... 0010011 @r2
  cpop       011000 000010 ..... 001 ..... 0010011 @r2
 +ctz        011000 000001 ..... 001 ..... 0010011 @r2
 +max        0000101 .......... 110 ..... 0110011 @r
 +maxu       0000101 .......... 111 ..... 0110011 @r
 +min        0000101 .......... 100 ..... 0110011 @r
 +minu       0000101 .......... 101 ..... 0110011 @r
 +orn        0100000 .......... 110 ..... 0110011 @r
 +rol        0110000 .......... 001 ..... 0110011 @r
 +ror        0110000 .......... 101 ..... 0110011 @r
 +rori       01100 ............ 101 ..... 0010011 @sh
  sext_b     011000 000100 ..... 001 ..... 0010011 @r2
  sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 -
 -andn       0100000 .......... 111 ..... 0110011 @r
 -orn        0100000 .......... 110 ..... 0110011 @r
  xnor       0100000 .......... 100 ..... 0110011 @r
 +
 +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 +clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 +ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 +cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 +rolw       0110000 .......... 001 ..... 0111011 @r
 +roriw      0110000 .......... 101 ..... 0011011 @sh5
 +rorw       0110000 .......... 101 ..... 0111011 @r
 +
 +# *** RV32B Standard Extension ***
  pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
 -min        0000101 .......... 100 ..... 0110011 @r
 -minu       0000101 .......... 101 ..... 0110011 @r
 -max        0000101 .......... 110 ..... 0110011 @r
 -maxu       0000101 .......... 111 ..... 0110011 @r
 -ror        0110000 .......... 101 ..... 0110011 @r
 -rol        0110000 .......... 001 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
  gorc       0010100 .......... 101 ..... 0110011 @r
 -rori       01100. ........... 101 ..... 0010011 @sh
  grevi      01101. ........... 101 ..... 0010011 @sh
  gorci      00101. ........... 101 ..... 0010011 @sh
  # *** RV64B Standard Extension (in addition to RV32B) ***
 -clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 -ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 -cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 -
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
 -rorw       0110000 .......... 101 ..... 0111011 @r
 -rolw       0110000 .......... 001 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
  gorcw      0010100 .......... 101 ..... 0111011 @r
 -roriw      0110000 .......... 101 ..... 0011011 @sh5
  greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the Zb[acs] Standard Extension.
 + * RISC-V translation routines for the Zb[abcs] Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBB(ctx) do {                    \
 +    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_ZBC(ctx) do {                    \
      if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
  {
      tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
  }
 +
  static bool trans_clz(DisasContext *ctx, arg_clz *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_ZERO, gen_clz);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
  static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
  }
  static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
  static bool trans_andn(DisasContext *ctx, arg_andn *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
  }
  static bool trans_orn(DisasContext *ctx, arg_orn *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
  }
  static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
  static bool trans_min(DisasContext *ctx, arg_min *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
  }
  static bool trans_max(DisasContext *ctx, arg_max *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
  }
  static bool trans_minu(DisasContext *ctx, arg_minu *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
  }
  static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
  }
  static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
  }
  static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
  }
  static bool trans_rori(DisasContext *ctx, arg_rori *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
  }
  static bool trans_rol(DisasContext *ctx, arg_rol *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
  static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, gen_clzw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_ctzw(TCGv ret, TCGv arg1)
  static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
  }
  static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift(ctx, a, EXT_NONE, gen_rolw);
  }
 --
 .31.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+The 1.0.0 version of Zbb does not contain gorc/gorci.  Instead, a
-further compressed instruction decoding. However, prior to this change,
+orc.b instruction (equivalent to the orc.b pseudo-instruction built on
-we did not raise an illegal instruction exception, if decode_RV32_64C()
+gorci from pre-0.93 draft-B) is available, mainly targeting
-fails to decode the instruction. This means that we skipped illegal
+string-processing workloads.
 compressed instructions instead of raising an illegal instruction
 exception.
-Instead of patching decode_RV32_64C(), we can just remove it,
+This commit adds the new orc.b instruction and removed gorc/gorci.
 as it is dead code since f330433b363 anyway.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ target/riscv/helper.h                   |  2 --
-file changed, 1 insertion(+), 178 deletions(-)
+ target/riscv/insn32.decode              |  6 +---
  target/riscv/bitmanip_helper.c          | 26 -----------------
  target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
 files changed, 18 insertions(+), 55 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/helper.h
-+++ b/target/riscv/translate.c
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
-     CPUState *cs;
+ /* Bitmanip */
- } DisasContext;
+ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--#ifdef TARGET_RISCV64
+-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--/* convert riscv funct3 to qemu memop for load/store */
+-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--static const int tcg_memop_lookup[8] = {
+ DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--    [0 ... 7] = -1,
+ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
--    [0] = MO_SB,
--    [1] = MO_TESW,
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
--    [2] = MO_TESL,
+index XXXXXXX..XXXXXXX 100644
--    [3] = MO_TEQ,
+--- a/target/riscv/insn32.decode
--    [4] = MO_UB,
++++ b/target/riscv/insn32.decode
--    [5] = MO_TEUW,
+@@ -XXX,XX +XXX,XX @@ max        0000101 .......... 110 ..... 0110011 @r
--    [6] = MO_TEUL,
+ maxu       0000101 .......... 111 ..... 0110011 @r
--};
+ min        0000101 .......... 100 ..... 0110011 @r
--#endif
+ minu       0000101 .......... 101 ..... 0110011 @r
 +orc_b      001010 000111 ..... 101 ..... 0010011 @r2
  orn        0100000 .......... 110 ..... 0110011 @r
  rol        0110000 .......... 001 ..... 0110011 @r
  ror        0110000 .......... 101 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
 -gorc       0010100 .......... 101 ..... 0110011 @r
 -
- #ifdef TARGET_RISCV64
+ grevi      01101. ........... 101 ..... 0010011 @sh
- #define CASE_OP_32_64(X) case X: case glue(X, W)
+-gorci      00101. ........... 101 ..... 0010011 @sh
- #else
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+ # *** RV64B Standard Extension (in addition to RV32B) ***
-     ctx->base.is_jmp = DISAS_NORETURN;
+ packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
 -gorcw      0010100 .......... 101 ..... 0111011 @r
  greviw     0110100 .......... 101 ..... 0011011 @sh5
 -gorciw     0010100 .......... 101 ..... 0011011 @sh5
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
      return do_grev(rs1, rs2, 32);
  }
--#ifdef TARGET_RISCV64
+-static target_ulong do_gorc(target_ulong rs1,
--static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+-                            target_ulong rs2,
--        target_long imm)
+-                            int bits)
 -{
--    TCGv t0 = tcg_temp_new();
+-    target_ulong x = rs1;
--    TCGv t1 = tcg_temp_new();
+-    int i, shift;
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
--    if (memop < 0) {
+-    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
--        gen_exception_illegal(ctx);
+-        if (rs2 & shift) {
--        return;
+-            x |= do_swap(x, adjacent_masks[i], shift);
 -        }
 -    }
 -
--    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+-    return x;
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
--static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
 -        target_long imm)
 -{
--    TCGv t0 = tcg_temp_new();
+-    return do_gorc(rs1, rs2, TARGET_LONG_BITS);
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
--static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
+-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
 -        int rs2, target_long imm)
 -{
--    TCGv t0;
+-    return do_gorc(rs1, rs2, 32);
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
      tcg_temp_free_i32(t0);
  }
 -static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t funct3 = extract16(opcode, 13, 3);
 -    uint8_t rd_rs2 = GET_C_RS2S(opcode);
 -    uint8_t rs1s = GET_C_RS1S(opcode);
 -
 -    switch (funct3) {
 -    case 3:
 -#if defined(TARGET_RISCV64)
 -        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 -        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 -                 GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 -        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 -                    GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    case 7:
 -#if defined(TARGET_RISCV64)
 -        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 -        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 -                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
--static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
+ target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  {
      target_ulong result = 0;
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
  }
 -static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
 +static void gen_orc_b(TCGv ret, TCGv source1)
  {
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
 +    TCGv  tmp = tcg_temp_new();
 +    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
 +
 +    /* Set lsb in each byte if the byte was zero. */
 +    tcg_gen_sub_tl(tmp, source1, ones);
 +    tcg_gen_andc_tl(tmp, tmp, source1);
 +    tcg_gen_shri_tl(tmp, tmp, 7);
 +    tcg_gen_andc_tl(tmp, ones, tmp);
 +
 +    /* Replicate the lsb of each byte across the byte. */
 +    tcg_gen_muli_tl(ret, tmp, 0xff);
 +
 +    tcg_temp_free(tmp);
  }
 -static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
 +static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 +    REQUIRE_ZBB(ctx);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
  }
  #define GEN_SHADD(SHAMT)                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
      return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
  }
 -static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
 -{
--    uint8_t op = extract16(opcode, 0, 2);
+-    REQUIRE_64BIT(ctx);
--
+-    REQUIRE_EXT(ctx, RVB);
--    switch (op) {
+-    ctx->w = true;
--    case 0:
+-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
- static int ex_plus_1(DisasContext *ctx, int nf)
+-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
- {
+-{
-     return nf + 1;
+-    REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+-    REQUIRE_EXT(ctx, RVB);
-         } else {
+-    ctx->w = true;
-             ctx->pc_succ_insn = ctx->base.pc_next + 2;
+-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-             if (!decode_insn16(ctx, opcode)) {
+-}
--                /* fall back to old decoder */
+-
--                decode_RV32_64C(ctx, opcode);
+ #define GEN_SHADD_UW(SHAMT)                                       \
-+                gen_exception_illegal(ctx);
+ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
-             }
+ {                                                                 \
          }
      } else {
 --
-.30.1
+.31.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro
-From: Bin Meng <bin.meng@windriver.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-This adds the documentation to describe what is supported for the
+With the changes to Zb[abcs], there's some encodings that are
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
 we'll need a helper macro allowing us to select on RV32, as well.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ target/riscv/translate.c | 6 ++++++
- docs/system/target-riscv.rst               |  1 +
+file changed, 6 insertions(+)
 files changed, 90 insertions(+)
  create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/translate.c
---- /dev/null
++++ b/target/riscv/translate.c
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
+@@ -XXX,XX +XXX,XX @@ EX_SH(12)
-@@ -XXX,XX +XXX,XX @@
+     }                              \
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+ } while (0)
-+=============================================================
 +#define REQUIRE_32BIT(ctx) do { \
 +    if (!is_32bit(ctx)) {       \
 +        return false;           \
 +    }                           \
 +} while (0)
 +
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+ #define REQUIRE_64BIT(ctx) do { \
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+     if (is_32bit(ctx)) {        \
-+
+         return false;           \
 +For more details about Microchip PolarFire SoC, please see:
 +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
 +
 +The Icicle Kit board information can be found here:
 +https://www.microsemi.com/existing-parts/parts/152514
 +
 +Supported devices
 +-----------------
 +
 +The ``microchip-icicle-kit`` machine supports the following devices:
 +
 + * 1 E51 core
 + * 4 U54 cores
 + * Core Level Interruptor (CLINT)
 + * Platform-Level Interrupt Controller (PLIC)
 + * L2 Loosely Integrated Memory (L2-LIM)
 + * DDR memory controller
 + * 5 MMUARTs
 + * 1 DMA controller
 + * 2 GEM Ethernet controllers
 + * 1 SDHC storage controller
 +
 +Boot options
 +------------
 +
 +The ``microchip-icicle-kit`` machine can start using the standard -bios
 +functionality for loading its BIOS image, aka Hart Software Services (HSS_).
 +HSS loads the second stage bootloader U-Boot from an SD card. It does not
 +support direct kernel loading via the -kernel option. One has to load kernel
 +from U-Boot.
 +
 +The memory is set to 1537 MiB by default which is the minimum required high
 +memory size by HSS. A sanity check on ram size is performed in the machine
 +init routine to prompt user to increase the RAM size to > 1537 MiB when less
 +than 1537 MiB ram is detected.
 +
 +Boot the machine
 +----------------
 +
 +HSS 2020.12 release is tested at the time of writing. To build an HSS image
 +that can be booted by the ``microchip-icicle-kit`` machine, type the following
 +in the HSS source tree:
 +
 +.. code-block:: bash
 +
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ cp boards/mpfs-icicle-kit-es/def_config .config
 +  $ make BOARD=mpfs-icicle-kit-es
 +
 +Download the official SD card image released by Microchip and prepare it for
 +QEMU usage:
 +
 +.. code-block:: bash
 +
 +  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 +  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
 +
 +Then we can boot the machine by:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
 +      -bios path/to/hss.bin -sd path/to/sdcard.img \
 +      -nic user,model=cadence_gem \
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
 +      -serial chardev:serial1
 +
 +With above command line, current terminal session will be used for the first
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
 +  $ minicom -D unix\#serial1.sock
 +
 +HSS output is on the first serial port (stdio) and U-Boot outputs on the
 +second serial port. U-Boot will automatically load the Linux kernel from
 +the SD card image.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/target-riscv.rst
 +++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
  .. toctree::
     :maxdepth: 1
 +   riscv/microchip-icicle-kit
     riscv/sifive_u
  RISC-V CPU features
 --
-.30.1
+.31.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi
-From: Bin Meng <bin.meng@windriver.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
-been updated to use a register mapped at 0x4f000000 instead of a
+rev8 instruction (equivalent to the rev8 pseudo-instruction built on
-GPIO to control whether eMMC or SD card is to be used. With this
+grevi from pre-0.93 draft-B) is available.
 support the same HSS image can be used for both eMMC and SD card
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
+This commit adds the new rev8 instruction and removes grev/grevi.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Note that there is no W-form of this instruction (both a
 sign-extending and zero-extending 32-bit version can easily be
 synthesized by following rev8 with either a srai or srli instruction
 on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
 different.
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ target/riscv/helper.h                   |  2 --
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+ target/riscv/insn32.decode              | 12 ++++----
-files changed, 7 insertions(+)
+ target/riscv/bitmanip_helper.c          | 40 -------------------------
  target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
 files changed, 15 insertions(+), 79 deletions(-)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/helper.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
-     MICROCHIP_PFSOC_ENVM_DATA,
+ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
-     MICROCHIP_PFSOC_QSPI_XIP,
-     MICROCHIP_PFSOC_IOSCB,
+ /* Bitmanip */
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
+-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-     MICROCHIP_PFSOC_DRAM_LO,
+-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+ DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-     MICROCHIP_PFSOC_DRAM_HI,
+ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/insn32.decode
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+ minu       0000101 .......... 101 ..... 0110011 @r
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+ orc_b      001010 000111 ..... 101 ..... 0010011 @r2
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+ orn        0100000 .......... 110 ..... 0110011 @r
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
++# The encoding for rev8 differs between RV32 and RV64.
-     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
++# rev8_32 denotes the RV32 variant.
-     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
++rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
-     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+ rol        0110000 .......... 001 ..... 0110011 @r
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+ ror        0110000 .......... 101 ..... 0110011 @r
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+ rori       01100 ............ 101 ..... 0010011 @sh
-                     memmap[MICROCHIP_PFSOC_IOSCB].base);
+@@ -XXX,XX +XXX,XX @@ xnor       0100000 .......... 100 ..... 0110011 @r
+ clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-+    /* eMMC/SD mux */
+ ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
++# The encoding for rev8 differs between RV32 and RV64.
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
++# When executing on RV64, the encoding used in RV32 is an illegal
-+
++# instruction, so we use different handler functions to differentiate.
-     /* QSPI Flash */
++rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
+ rolw       0110000 .......... 001 ..... 0111011 @r
-                            "microchip.pfsoc.qspi_xip",
+ roriw      0110000 .......... 101 ..... 0011011 @sh5
  rorw       0110000 .......... 101 ..... 0111011 @r
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
  pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
 -grev       0110100 .......... 101 ..... 0110011 @r
 -grevi      01101. ........... 101 ..... 0010011 @sh
  # *** RV64B Standard Extension (in addition to RV32B) ***
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
 -grevw      0110100 .......... 101 ..... 0111011 @r
 -
 -greviw     0110100 .......... 101 ..... 0011011 @sh5
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-proto.h"
  #include "tcg/tcg.h"
 -static const uint64_t adjacent_masks[] = {
 -    dup_const(MO_8, 0x55),
 -    dup_const(MO_8, 0x33),
 -    dup_const(MO_8, 0x0f),
 -    dup_const(MO_16, 0xff),
 -    dup_const(MO_32, 0xffff),
 -    UINT32_MAX
 -};
 -
 -static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
 -{
 -    return ((x & mask) << shift) | ((x & ~mask) >> shift);
 -}
 -
 -static target_ulong do_grev(target_ulong rs1,
 -                            target_ulong rs2,
 -                            int bits)
 -{
 -    target_ulong x = rs1;
 -    int i, shift;
 -
 -    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
 -        if (rs2 & shift) {
 -            x = do_swap(x, adjacent_masks[i], shift);
 -        }
 -    }
 -
 -    return x;
 -}
 -
 -target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
 -{
 -    return do_grev(rs1, rs2, TARGET_LONG_BITS);
 -}
 -
 -target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
 -{
 -    return do_grev(rs1, rs2, 32);
 -}
 -
  target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  {
      target_ulong result = 0;
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }
 -static bool trans_grev(DisasContext *ctx, arg_grev *a)
 +static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
 -}
 -
 -static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
 -{
 -    if (shamt == TARGET_LONG_BITS - 8) {
 -        /* rev8, byte swaps */
 -        tcg_gen_bswap_tl(dest, src);
 -    } else {
 -        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
 -    }
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZBB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
  }
 -static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
 +static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_ZBB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
  }
  static void gen_orc_b(TCGv ret, TCGv source1)
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
      return gen_shift(ctx, a, EXT_NONE, gen_rolw);
  }
 -static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
 -}
 -
 -static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
 -}
 -
  #define GEN_SHADD_UW(SHAMT)                                       \
  static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
  {                                                                 \
 --
-.30.1
+.31.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-The previous implementation was broken in many ways:
+The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
- - Used mideleg instead of hideleg to mask accesses
+zext.h instruction is provided (built on pack/packh from pre-0.93
- - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
+draft-B) is available.
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+This commit adds zext.h and removes the pack* instructions.
 Note that the encodings for zext.h are different between RV32 and
 RV64, which is handled through REQUIRE_32BIT.
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/insn32.decode              | 12 ++--
-file changed, 34 insertions(+), 34 deletions(-)
+ target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
 files changed, 21 insertions(+), 77 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/insn32.decode
-+++ b/target/riscv/csr.c
++++ b/target/riscv/insn32.decode
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ rori       01100 ............ 101 ..... 0010011 @sh
-     return write_mstatus(env, CSR_MSTATUS, newval);
+ sext_b     011000 000100 ..... 001 ..... 0010011 @r2
  sext_h     011000 000101 ..... 001 ..... 0010011 @r2
  xnor       0100000 .......... 100 ..... 0110011 @r
 +# The encoding for zext.h differs between RV32 and RV64.
 +# zext_h_32 denotes the RV32 variant.
 +zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
  # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
  clzw       0110000 00000 ..... 001 ..... 0011011 @r2
@@ -XXX,XX +XXX,XX @@ rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
  rolw       0110000 .......... 001 ..... 0111011 @r
  roriw      0110000 .......... 101 ..... 0011011 @sh5
  rorw       0110000 .......... 101 ..... 0111011 @r
 +# The encoding for zext.h differs between RV32 and RV64.
 +# When executing on RV64, the encoding used in RV32 is an illegal
 +# instruction, so we use different handler functions to differentiate.
 +zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
  # *** RV32B Standard Extension ***
 -pack       0000100 .......... 100 ..... 0110011 @r
 -packu      0100100 .......... 100 ..... 0110011 @r
 -packh      0000100 .......... 111 ..... 0110011 @r
  # *** RV64B Standard Extension (in addition to RV32B) ***
 -packw      0000100 .......... 100 ..... 0111011 @r
 -packuw     0100100 .......... 100 ..... 0111011 @r
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_deposit_tl(ret, arg1, arg2,
 -                       TARGET_LONG_BITS / 2,
 -                       TARGET_LONG_BITS / 2);
 -}
 -
 -static bool trans_pack(DisasContext *ctx, arg_pack *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_pack);
 -}
 -
 -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
 -    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
 -    tcg_temp_free(t);
 -}
 -
 -static bool trans_packu(DisasContext *ctx, arg_packu *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packu);
 -}
 -
 -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_ext8u_tl(t, arg2);
 -    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
 -    tcg_temp_free(t);
 -}
 -
 -static bool trans_packh(DisasContext *ctx, arg_packh *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packh);
 -}
 -
  static bool trans_min(DisasContext *ctx, arg_min *a)
  {
      REQUIRE_ZBB(ctx);
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(1)
  GEN_TRANS_SHADD(2)
  GEN_TRANS_SHADD(3)
 +static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    REQUIRE_32BIT(ctx);
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    REQUIRE_ZBB(ctx);
-+    return 0;
++    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
++static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
  {
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Tell the guest the VS bits, shifted to the S bit locations */
 -        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
 +        read_vsie(env, CSR_VSIE, val);
      } else {
          *val = env->mie & env->mideleg;
      }
      return 0;
  }
 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    target_ulong newval;
 +    /* Shift the S bits to their VS bit location in mie */
 +    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 +                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 +    return write_mie(env, CSR_MIE, newval);
 +}
 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +{
-     if (riscv_cpu_virt_enabled(env)) {
++    REQUIRE_64BIT(ctx);
--        /* Shift the guests S bits to VS */
++    REQUIRE_ZBB(ctx);
--        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
++    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
 -                 ((val << 1) & VS_MODE_INTERRUPTS);
 +        write_vsie(env, CSR_VSIE, val);
      } else {
 -        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 +        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 +                              (val & S_MODE_INTERRUPTS);
 +        write_mie(env, CSR_MIE, newval);
      }
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
  static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +                    target_ulong new_value, target_ulong write_mask)
 +{
 +    /* Shift the S bits to their VS bit location in mip */
 +    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
- static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ static void gen_clzw(TCGv ret, TCGv arg1)
                     target_ulong new_value, target_ulong write_mask)
  {
-     int ret;
+     TCGv t = tcg_temp_new();
+@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-     if (riscv_cpu_virt_enabled(env)) {
+     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 -        /* Shift the new values to line up with the VS bits */
 -        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 -                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
 -        ret &= vsip_writable_mask;
 -        ret >>= 1;
 +        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
      } else {
          ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                        write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
 -                    target_ulong new_value, target_ulong write_mask)
 -{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
+-    TCGv t = tcg_temp_new();
--                      write_mask & env->mideleg & vsip_writable_mask);
+-    tcg_gen_ext16s_tl(t, arg2);
--    return ret;
+-    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
 -    tcg_temp_free(t);
 -}
 -
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+-static bool trans_packw(DisasContext *ctx, arg_packw *a)
 -{
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
+-    REQUIRE_64BIT(ctx);
--    return 0;
+-    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packw);
 -}
 -
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
+-    TCGv t = tcg_temp_new();
--    return write_mie(env, CSR_MIE, newval);
+-    tcg_gen_shri_tl(t, arg1, 16);
 -    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
 -    tcg_gen_ext32s_tl(ret, ret);
 -    tcg_temp_free(t);
 -}
 -
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
+-static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
 -}
 -
  static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  {
-     *val = env->vstvec;
+     TCGv_i32 t1 = tcg_temp_new_i32();
 --
-.30.1
+.31.1

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs])
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+With everything classified as Zb[abcs] and pre-0.93 draft-B
-short of its purpose, as all it checks is whether two-stage address
+instructions that are not part of Zb[abcs] removed, we can remove the
-translation either via the hypervisor-load store instructions or the
+remaining support code for RVB.
 MPRV feature would be allowed.
-What we really need instead is whether two-stage address translation was
+Note that RVB has been retired for good and misa.B will neither mean
-active when the exception was raised. However, in riscv_cpu_do_interrupt
+'some' or 'all of' Zb*:
-we do not have the information to reliably detect this. Therefore, when
+  https://lists.riscv.org/g/tech-bitmanip/message/532
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/cpu.h         |  3 ---
- target/riscv/cpu.c        |  1 +
+ target/riscv/insn32.decode |  4 ----
- target/riscv/cpu_helper.c | 21 ++++++++-------------
+ target/riscv/cpu.c         | 26 --------------------------
-files changed, 13 insertions(+), 13 deletions(-)
+files changed, 33 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@
-     target_ulong satp_hs;
+ #define RVS RV('S')
-     uint64_t mstatus_hs;
+ #define RVU RV('U')
+ #define RVH RV('H')
-+    /* Signals whether the current exception occurred with two-stage address
+-#define RVB RV('B')
-+       translation active. */
-+    bool two_stage_lookup;
+ /* S extension denotes that Supervisor mode exists, however it is possible
-+
+    to have a core that support S mode but does not have an MMU and there
-     target_ulong scounteren;
+@@ -XXX,XX +XXX,XX @@ enum {
-     target_ulong mcounteren;
+ #define PRIV_VERSION_1_10_0 0x00011000
+ #define PRIV_VERSION_1_11_0 0x00011100
 -#define BEXT_VERSION_0_93_0 0x00009300
  #define VEXT_VERSION_0_07_1 0x00000701
  enum {
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
          bool ext_f;
          bool ext_d;
          bool ext_c;
 -        bool ext_b;
          bool ext_s;
          bool ext_u;
          bool ext_h;
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
  # instruction, so we use different handler functions to differentiate.
  zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 -# *** RV32B Standard Extension ***
 -
 -# *** RV64B Standard Extension (in addition to RV32B) ***
 -
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
  clmulh     0000101 .......... 011 ..... 0110011 @r
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+     env->priv_ver = priv_ver;
      env->mcause = 0;
      env->pc = env->resetvec;
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE;
      env->load_res = -1;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
          g_assert_not_reached();
      }
      env->badaddr = address;
 +    env->two_stage_lookup = two_stage;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+-static void set_bext_version(CPURISCVState *env, int bext_ver)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+-{
-     }
+-    env->bext_ver = bext_ver;
+-}
-     env->badaddr = addr;
+-
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+ static void set_vext_version(CPURISCVState *env, int vext_ver)
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
+ {
-     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
+     env->vext_ver = vext_ver;
- }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+         if (cpu->cfg.ext_h) {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+             target_misa |= RVH;
-         g_assert_not_reached();
+         }
-     }
+-        if (cpu->cfg.ext_b) {
-     env->badaddr = addr;
+-            int bext_version = BEXT_VERSION_0_93_0;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+-            target_misa |= RVB;
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
+-
-     riscv_raise_exception(env, cs->exception_index, retaddr);
+-            if (cpu->cfg.bext_spec) {
- }
+-                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
- #endif /* !CONFIG_USER_ONLY */
+-                    bext_version = BEXT_VERSION_0_93_0;
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+-                } else {
-         /* handle the trap in S-mode */
+-                    error_setg(errp,
-         if (riscv_has_ext(env, RVH)) {
+-                           "Unsupported bitmanip spec version '%s'",
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+-                           cpu->cfg.bext_spec);
--            bool two_stage_lookup = false;
+-                    return;
+-                }
--            if (env->priv == PRV_M ||
+-            } else {
--                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+-                qemu_log("bitmanip version is not specified, "
--                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+-                         "use the default value v0.93\n");
 -                    get_field(env->hstatus, HSTATUS_HU))) {
 -                    two_stage_lookup = true;
 -            }
--
+-            set_bext_version(env, bext_version);
--            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+-        }
-+            if (env->two_stage_lookup && write_tval) {
+         if (cpu->cfg.ext_v) {
-                 /*
+             int vext_version = VEXT_VERSION_0_07_1;
-                  * If we are writing a guest virtual address to stval, set
+             target_misa |= RVV;
-                  * this to 1. If we are trapping to VS we will set this to 0
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
-                 riscv_cpu_set_force_hs_excep(env, 0);
+     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
-             } else {
+     /* This is experimental so mark with 'x-' */
-                 /* Trap into HS mode */
+-    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
--                if (!two_stage_lookup) {
+     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
--                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
--                                             riscv_cpu_virt_enabled(env));
+     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
--                }
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
-+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
+     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-                 htval = env->guest_phys_fault_addr;
+     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-             }
+     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-         }
+-    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
-      * RISC-V ISA Specification.
+     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-      */
+     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.31.1

-New patch
+[PULL 16/26] disas/riscv: Add Zb[abcs] instructions
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
 With the addition of Zb[abcs], we also need to add disassembler
 support for these new instructions.
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
 file changed, 154 insertions(+), 3 deletions(-)
 diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas/riscv.c
 +++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
      rv_op_fsflags = 316,
      rv_op_fsrmi = 317,
      rv_op_fsflagsi = 318,
 +    rv_op_bseti = 319,
 +    rv_op_bclri = 320,
 +    rv_op_binvi = 321,
 +    rv_op_bexti = 322,
 +    rv_op_rori = 323,
 +    rv_op_clz = 324,
 +    rv_op_ctz = 325,
 +    rv_op_cpop = 326,
 +    rv_op_sext_h = 327,
 +    rv_op_sext_b = 328,
 +    rv_op_xnor = 329,
 +    rv_op_orn = 330,
 +    rv_op_andn = 331,
 +    rv_op_rol = 332,
 +    rv_op_ror = 333,
 +    rv_op_sh1add = 334,
 +    rv_op_sh2add = 335,
 +    rv_op_sh3add = 336,
 +    rv_op_sh1add_uw = 337,
 +    rv_op_sh2add_uw = 338,
 +    rv_op_sh3add_uw = 339,
 +    rv_op_clmul = 340,
 +    rv_op_clmulr = 341,
 +    rv_op_clmulh = 342,
 +    rv_op_min = 343,
 +    rv_op_minu = 344,
 +    rv_op_max = 345,
 +    rv_op_maxu = 346,
 +    rv_op_clzw = 347,
 +    rv_op_ctzw = 348,
 +    rv_op_cpopw = 349,
 +    rv_op_slli_uw = 350,
 +    rv_op_add_uw = 351,
 +    rv_op_rolw = 352,
 +    rv_op_rorw = 353,
 +    rv_op_rev8 = 354,
 +    rv_op_zext_h = 355,
 +    rv_op_roriw = 356,
 +    rv_op_orc_b = 357,
 +    rv_op_bset = 358,
 +    rv_op_bclr = 359,
 +    rv_op_binv = 360,
 +    rv_op_bext = 361,
  } rv_op;
  /* structures */
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
      { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
      { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
      { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
 +    { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
  };
  /* CSR names */
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 0: op = rv_op_addi; break;
              case 1:
                  switch (((inst >> 27) & 0b11111)) {
 -                case 0: op = rv_op_slli; break;
 +                case 0b00000: op = rv_op_slli; break;
 +                case 0b00101: op = rv_op_bseti; break;
 +                case 0b01001: op = rv_op_bclri; break;
 +                case 0b01101: op = rv_op_binvi; break;
 +                case 0b01100:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0000000: op = rv_op_clz; break;
 +                    case 0b0000001: op = rv_op_ctz; break;
 +                    case 0b0000010: op = rv_op_cpop; break;
 +                      /* 0b0000011 */
 +                    case 0b0000100: op = rv_op_sext_b; break;
 +                    case 0b0000101: op = rv_op_sext_h; break;
 +                    }
 +                    break;
                  }
                  break;
              case 2: op = rv_op_slti; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 4: op = rv_op_xori; break;
              case 5:
                  switch (((inst >> 27) & 0b11111)) {
 -                case 0: op = rv_op_srli; break;
 -                case 8: op = rv_op_srai; break;
 +                case 0b00000: op = rv_op_srli; break;
 +                case 0b00101: op = rv_op_orc_b; break;
 +                case 0b01000: op = rv_op_srai; break;
 +                case 0b01001: op = rv_op_bexti; break;
 +                case 0b01100: op = rv_op_rori; break;
 +                case 0b01101:
 +                    switch ((inst >> 20) & 0b1111111) {
 +                    case 0b0111000: op = rv_op_rev8; break;
 +                    }
 +                    break;
                  }
                  break;
              case 6: op = rv_op_ori; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 1:
                  switch (((inst >> 25) & 0b1111111)) {
                  case 0: op = rv_op_slliw; break;
 +                case 4: op = rv_op_slli_uw; break;
 +                case 48:
 +                    switch ((inst >> 20) & 0b11111) {
 +                    case 0b00000: op = rv_op_clzw; break;
 +                    case 0b00001: op = rv_op_ctzw; break;
 +                    case 0b00010: op = rv_op_cpopw; break;
 +                    }
 +                    break;
                  }
                  break;
              case 5:
                  switch (((inst >> 25) & 0b1111111)) {
                  case 0: op = rv_op_srliw; break;
                  case 32: op = rv_op_sraiw; break;
 +                case 48: op = rv_op_roriw; break;
                  }
                  break;
              }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 13: op = rv_op_divu; break;
              case 14: op = rv_op_rem; break;
              case 15: op = rv_op_remu; break;
 +            case 36:
 +                switch ((inst >> 20) & 0b11111) {
 +                case 0: op = rv_op_zext_h; break;
 +                }
 +                break;
 +            case 41: op = rv_op_clmul; break;
 +            case 42: op = rv_op_clmulr; break;
 +            case 43: op = rv_op_clmulh; break;
 +            case 44: op = rv_op_min; break;
 +            case 45: op = rv_op_minu; break;
 +            case 46: op = rv_op_max; break;
 +            case 47: op = rv_op_maxu; break;
 +            case 130: op = rv_op_sh1add; break;
 +            case 132: op = rv_op_sh2add; break;
 +            case 134: op = rv_op_sh3add; break;
 +            case 161: op = rv_op_bset; break;
              case 256: op = rv_op_sub; break;
 +            case 260: op = rv_op_xnor; break;
              case 261: op = rv_op_sra; break;
 +            case 262: op = rv_op_orn; break;
 +            case 263: op = rv_op_andn; break;
 +            case 289: op = rv_op_bclr; break;
 +            case 293: op = rv_op_bext; break;
 +            case 385: op = rv_op_rol; break;
 +            case 386: op = rv_op_ror; break;
 +            case 417: op = rv_op_binv; break;
              }
              break;
          case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 13: op = rv_op_divuw; break;
              case 14: op = rv_op_remw; break;
              case 15: op = rv_op_remuw; break;
 +            case 32: op = rv_op_add_uw; break;
 +            case 36:
 +                switch ((inst >> 20) & 0b11111) {
 +                case 0: op = rv_op_zext_h; break;
 +                }
 +                break;
 +            case 130: op = rv_op_sh1add_uw; break;
 +            case 132: op = rv_op_sh2add_uw; break;
 +            case 134: op = rv_op_sh3add_uw; break;
              case 256: op = rv_op_subw; break;
              case 261: op = rv_op_sraw; break;
 +            case 385: op = rv_op_rolw; break;
 +            case 389: op = rv_op_rorw; break;
              }
              break;
          case 16:
 --
 .31.1

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
 From: Frank Chang <frank.chang@sifive.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
-is not enabled.
+Modifying the floating-point state when V=1 causes both fields to
 be set to 3 (Dirty).
-If -1 is returned, exception will be raised and cs->exception_index will
+However, it's possible that HS-level sstatus.FS is Clean and VS-level
-be set to the negative return value. The exception will then be treated
+vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1.
-as an instruction access fault instead of illegal instruction fault.
+We can't early return for this case because we still need to set
 sstatus.FS to Dirty according to spec.
 Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
+Tested-by: Vincent Chen <vincent.chen@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Message-id: 20210921020234.123448-1-frank.chang@sifive.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/cpu.h       |  4 ++++
-file changed, 1 insertion(+), 1 deletion(-)
+ target/riscv/translate.c | 30 +++++++++++++++++-------------
 files changed, 21 insertions(+), 13 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/csr.c
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, SEW, 5, 3)
-     if (env->misa & RVV) {
+ FIELD(TB_FLAGS, VILL, 8, 1)
-         return 0;
+ /* Is a Hypervisor instruction load/store allowed? */
  FIELD(TB_FLAGS, HLSX, 9, 1)
 +FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
  bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                  get_field(env->hstatus, HSTATUS_HU))) {
              flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
          }
 +
 +        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
 +                           get_field(env->mstatus_hs, MSTATUS_FS));
      }
--    return -1;
+ #endif
-+    return -RISCV_EXCP_ILLEGAL_INST;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      target_ulong misa;
      uint32_t opcode;
      uint32_t mstatus_fs;
 +    uint32_t mstatus_hs_fs;
      uint32_t mem_idx;
      /* Remember the rounding mode encoded in the previous fp instruction,
         which we have already installed into env->fp_status.  Or -1 for
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
  static void mark_fs_dirty(DisasContext *ctx)
  {
      TCGv tmp;
 -    target_ulong sd;
 +    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 -    if (ctx->mstatus_fs == MSTATUS_FS) {
 -        return;
 -    }
 -    /* Remember the state change for the rest of the TB.  */
 -    ctx->mstatus_fs = MSTATUS_FS;
 +    if (ctx->mstatus_fs != MSTATUS_FS) {
 +        /* Remember the state change for the rest of the TB. */
 +        ctx->mstatus_fs = MSTATUS_FS;
 -    tmp = tcg_temp_new();
 -    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 +        tmp = tcg_temp_new();
 +        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +        tcg_temp_free(tmp);
 +    }
 -    tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 -    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 -    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +    if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
 +        /* Remember the stage change for the rest of the TB. */
 +        ctx->mstatus_hs_fs = MSTATUS_FS;
 -    if (ctx->virt_enabled) {
 +        tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
          tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 +        tcg_temp_free(tmp);
      }
 -    tcg_temp_free(tmp);
  }
+ #else
- static int ctr(CPURISCVState *env, int csrno)
+ static inline void mark_fs_dirty(DisasContext *ctx) { }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
      ctx->vlen = cpu->cfg.vlen;
 +    ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
      ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
      ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
      ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 --
-.30.1
+.31.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 18/26] hw/char: ibex_uart: Register device in 'input' category
-From: Alexander Wagner <alexander.wagner@ulal.de>
+From: Bin Meng <bmeng.cn@gmail.com>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+The category of ibex_uart device is not set. Put it into the
-the newest received byte. The rx_level variable is added to allow the use of
+'input' category.
 the existing OpenTitan driver libraries.
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
+Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ hw/char/ibex_uart.c | 1 +
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+file changed, 1 insertion(+)
 files changed, 22 insertions(+), 5 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
-+++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
- REG32(OVRD, 0x24)
- REG32(VAL, 0x28)
- REG32(TIMEOUT_CTRL, 0x2c)
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
-     uint32_t tx_level;
-+    uint32_t rx_level;
-+
-     QEMUTimer *fifo_trigger_handle;
-     uint64_t char_tx_time;
 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/ibex_uart.c
 +++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void ibex_uart_class_init(ObjectClass *klass, void *data)
- {
+     dc->realize = ibex_uart_realize;
-     IbexUartState *s = opaque;
+     dc->vmsd = &vmstate_ibex_uart;
+     device_class_set_props(dc, ibex_uart_properties);
--    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
++    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
-+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+ }
-+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
-         return 1;
+ static const TypeInfo ibex_uart_info = {
      }
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
      s->uart_status &= ~R_STATUS_RXIDLE_MASK;
      s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
 +    /* The RXFULL is set after receiving a single byte
 +     * as the FIFO buffers are not yet implemented.
 +     */
 +    s->uart_status |= R_STATUS_RXFULL_MASK;
 +    s->rx_level += 1;
      if (size > rx_fifo_level) {
          s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
      s->uart_timeout_ctrl = 0x00000000;
      s->tx_level = 0;
 +    s->rx_level = 0;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
          break;
      case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_FIFO_STATUS:
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
 --
-.30.1
+.31.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+[PULL 19/26] hw/char: shakti_uart: Register device in 'input' category
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Bin Meng <bmeng.cn@gmail.com>
-Allow ramfb on virt.  This lets `-device ramfb' work.
+The category of shakti_uart device is not set. Put it into the
 'input' category.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
+Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 3 +++
+ hw/char/shakti_uart.c | 1 +
-file changed, 3 insertions(+)
+file changed, 1 insertion(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/hw/char/shakti_uart.c
-+++ b/hw/riscv/virt.c
++++ b/hw/char/shakti_uart.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void shakti_uart_class_init(ObjectClass *klass, void *data)
- #include "sysemu/sysemu.h"
+     dc->reset = shakti_uart_reset;
- #include "hw/pci/pci.h"
+     dc->realize = shakti_uart_realize;
- #include "hw/pci-host/gpex.h"
+     device_class_set_props(dc, shakti_uart_properties);
-+#include "hw/display/ramfb.h"
++    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  static const MemMapEntry virt_memmap[] = {
      [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
      mc->numa_mem_supported = true;
 +
 +    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
  }
- static const TypeInfo virt_machine_typeinfo = {
+ static const TypeInfo shakti_uart_info = {
 --
-.30.1
+.31.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL 20/26] hw/char: sifive_uart: Register device in 'input' category
-From: Jim Shu <cwshu@andestech.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-If PMP permission of any address has been changed by updating PMP entry,
+The category of sifive_uart device is not set. Put it into the
-flush all TLB pages to prevent from getting old permission.
+'input' category.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
+Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ hw/char/sifive_uart.c | 1 +
-file changed, 4 insertions(+)
+file changed, 1 insertion(+)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/hw/char/sifive_uart.c
-+++ b/target/riscv/pmp.c
++++ b/hw/char/sifive_uart.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void sifive_uart_class_init(ObjectClass *oc, void *data)
- #include "qapi/error.h"
+     rc->phases.enter = sifive_uart_reset_enter;
- #include "cpu.h"
+     rc->phases.hold  = sifive_uart_reset_hold;
- #include "trace.h"
+     device_class_set_props(dc, sifive_uart_properties);
-+#include "exec/exec-all.h"
++    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
      uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
          cfg_val = (val >> 8 * i)  & 0xff;
          pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
      }
 +
 +    /* If PMP permission of any addr has been changed, flush TLB pages. */
 +    tlb_flush(env_cpu(env));
  }
+ static const TypeInfo sifive_uart_info = {
 --
-.30.1
+.31.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+[PULL 21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-According to the specification the "field SPVP of hstatus controls the
+The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
-privilege level of the access" for the hypervisor virtual-machine load
+size occupied by all the registers. However all registers are
-and store instructions HLV, HLVX and HSV.
+-bit wide, and the MemoryRegionOps handlers are restricted to
 -bit:
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+  static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
       .read = mchp_pfsoc_mmuart_read,
       .write = mchp_pfsoc_mmuart_write,
       .impl = {
           .min_access_size = 4,
           .max_access_size = 4,
       },
 Avoid being triskaidekaphobic, simplify by using the number of
 registers.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Tested-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210925133407.1259392-2-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
+ include/hw/char/mchp_pfsoc_mmuart.h |  4 ++--
-file changed, 14 insertions(+), 11 deletions(-)
+ hw/char/mchp_pfsoc_mmuart.c         | 14 ++++++++------
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/include/hw/char/mchp_pfsoc_mmuart.h
-+++ b/target/riscv/cpu_helper.c
++++ b/include/hw/char/mchp_pfsoc_mmuart.h
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@
-         use_background = true;
  #include "hw/char/serial.h"
 -#define MCHP_PFSOC_MMUART_REG_SIZE  52
 +#define MCHP_PFSOC_MMUART_REG_COUNT 13
  typedef struct MchpPfSoCMMUartState {
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCMMUartState {
      SerialMM *serial;
 -    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
 +    uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
  } MchpPfSoCMMUartState;
  /**
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/mchp_pfsoc_mmuart.c
 +++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@ static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
  {
      MchpPfSoCMMUartState *s = opaque;
 -    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
 +    addr >>= 2;
 +    if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
          qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
 -                      __func__, addr);
 +                      __func__, addr << 2);
          return 0;
      }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+-    return s->reg[addr / sizeof(uint32_t)];
-+    /* MPRV does not affect the virtual-machine load/store
++    return s->reg[addr];
-+       instructions, HLV, HLVX, and HSV. */
+ }
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+ static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
+     MchpPfSoCMMUartState *s = opaque;
-             mode = get_field(env->mstatus, MSTATUS_MPP);
+     uint32_t val32 = (uint32_t)value;
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+-    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
-     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
++    addr >>= 2;
-                   __func__, address, access_type, mmu_idx);
++    if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
+         qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+-                      " v=0x%x\n", __func__, addr, val32);
--        if (get_field(env->mstatus, MSTATUS_MPRV)) {
++                      " v=0x%x\n", __func__, addr << 2, val32);
--            mode = get_field(env->mstatus, MSTATUS_MPP);
+         return;
 +    /* MPRV does not affect the virtual-machine load/store
 +       instructions, HLV, HLVX, and HSV. */
 +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
 +        mode = get_field(env->hstatus, HSTATUS_SPVP);
 +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
 +               get_field(env->mstatus, MSTATUS_MPRV)) {
 +        mode = get_field(env->mstatus, MSTATUS_MPP);
 +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
 +            two_stage_lookup = true;
          }
      }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+-    s->reg[addr / sizeof(uint32_t)] = val32;
--        access_type != MMU_INST_FETCH &&
++    s->reg[addr] = val32;
--        get_field(env->mstatus, MSTATUS_MPRV) &&
+ }
--        get_field(env->mstatus, MSTATUS_MPV)) {
--        two_stage_lookup = true;
+ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
 -    }
 -
      if (riscv_cpu_virt_enabled(env) ||
          ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
           access_type != MMU_INST_FETCH)) {
 --
-.30.1
+.31.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL 22/26] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Our device have 2 different I/O regions:
 - a 16550 UART mapped for 32-bit accesses
 - 13 extra registers
 Instead of mapping each region on the main bus, introduce
 a container, map the 2 devices regions on the container,
 and map the container on the main bus.
 Before:
   (qemu) info mtree
     ...
     0000000020100000-000000002010001f (prio 0, i/o): serial
     0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020102000-000000002010201f (prio 0, i/o): serial
     0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020104000-000000002010401f (prio 0, i/o): serial
     0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020106000-000000002010601f (prio 0, i/o): serial
     0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart
 After:
   (qemu) info mtree
     ...
     0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020100000-000000002010001f (prio 0, i/o): serial
       0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020102000-000000002010201f (prio 0, i/o): serial
       0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020104000-000000002010401f (prio 0, i/o): serial
       0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020106000-000000002010601f (prio 0, i/o): serial
       0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Tested-by: Bin Meng <bin.meng@windriver.com>
 Message-id: 20210925133407.1259392-3-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ include/hw/char/mchp_pfsoc_mmuart.h |  1 +
-file changed, 4 insertions(+), 3 deletions(-)
+ hw/char/mchp_pfsoc_mmuart.c         | 11 ++++++++---
 files changed, 9 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/include/hw/char/mchp_pfsoc_mmuart.h
-+++ b/target/riscv/csr.c
++++ b/include/hw/char/mchp_pfsoc_mmuart.h
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+ #define MCHP_PFSOC_MMUART_REG_COUNT 13
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+ typedef struct MchpPfSoCMMUartState {
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
++    MemoryRegion container;
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
+     MemoryRegion iomem;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+     hwaddr base;
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
+     qemu_irq irq;
+diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
- static const char valid_vm_1_10_32[16] = {
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+--- a/hw/char/mchp_pfsoc_mmuart.c
-                    target_ulong new_value, target_ulong write_mask)
++++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char.h"
  #include "hw/char/mchp_pfsoc_mmuart.h"
 +#define REGS_OFFSET 0x20
 +
  static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
  {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+     MchpPfSoCMMUartState *s = opaque;
--                      write_mask & hip_writable_mask);
+@@ -XXX,XX +XXX,XX @@ MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
-+                      write_mask & hvip_writable_mask);
+     s = g_new0(MchpPfSoCMMUartState, 1);
--    *ret_value &= hip_writable_mask;
-+    *ret_value &= hvip_writable_mask;
++    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
++
-     return ret;
+     memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
 -                          "mchp.pfsoc.mmuart", 0x1000);
 +                          "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
 +    memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
      s->base = base;
      s->irq = irq;
 -    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
 +    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
                                 DEVICE_LITTLE_ENDIAN);
 -    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
 +    memory_region_add_subregion(sysmem, base, &s->container);
      return s;
  }
 --
-.30.1
+.31.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL 23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Provides fw_cfg for the virt machine on riscv.  This enables
+- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
-using e.g.  ramfb later.
+- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
 - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
 - Add DeviceReset() method
 - Add vmstate structure for migration
 - Register device in 'input' category
 - Keep mchp_pfsoc_mmuart_create() behavior
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Note, serial_mm_init() calls qdev_set_legacy_instance_id().
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+This call is only needed for backwards-compatibility of incoming
 migration data with old versions of QEMU which implemented migration
 of devices with hand-rolled code. Since this device didn't previously
 handle migration at all, then it doesn't need to set the legacy
 instance ID.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Tested-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-id: 20210925133407.1259392-4-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ include/hw/char/mchp_pfsoc_mmuart.h | 12 +++-
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+ hw/char/mchp_pfsoc_mmuart.c         | 97 +++++++++++++++++++++++++----
- hw/riscv/Kconfig        |  1 +
+files changed, 93 insertions(+), 16 deletions(-)
 files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/include/hw/char/mchp_pfsoc_mmuart.h
-+++ b/include/hw/riscv/virt.h
++++ b/include/hw/char/mchp_pfsoc_mmuart.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+ #ifndef HW_MCHP_PFSOC_MMUART_H
-     DeviceState *plic[VIRT_SOCKETS_MAX];
+ #define HW_MCHP_PFSOC_MMUART_H
-     PFlashCFI01 *flash[2];
-+    FWCfgState *fw_cfg;
++#include "hw/sysbus.h"
+ #include "hw/char/serial.h"
-     int fdt_size;
  #define MCHP_PFSOC_MMUART_REG_COUNT 13
 +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
 +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
 +
  typedef struct MchpPfSoCMMUartState {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
      MemoryRegion container;
      MemoryRegion iomem;
 -    hwaddr base;
 -    qemu_irq irq;
 -    SerialMM *serial;
 +    SerialMM serial_mm;
      uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
  } MchpPfSoCMMUartState;
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/mchp_pfsoc_mmuart.c
 +++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qemu/log.h"
 -#include "chardev/char.h"
 +#include "qapi/error.h"
 +#include "migration/vmstate.h"
  #include "hw/char/mchp_pfsoc_mmuart.h"
 +#include "hw/qdev-properties.h"
  #define REGS_OFFSET 0x20
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
      },
  };
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_PLIC,
+-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
-     VIRT_UART0,
+-    hwaddr base, qemu_irq irq, Chardev *chr)
-     VIRT_VIRTIO,
++static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
 +    VIRT_FW_CFG,
      VIRT_FLASH,
      VIRT_DRAM,
      VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
      [VIRT_UART0] =       { 0x10000000,         0x100 },
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
 +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
      return dev;
  }
 +static FWCfgState *create_fw_cfg(const MachineState *mc)
 +{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
++    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
 +    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
 +    FWCfgState *fw_cfg;
 +    char *nodename;
 +
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
++    memset(s->reg, 0, sizeof(s->reg));
-+                                  &address_space_memory);
++    device_cold_reset(DEVICE(&s->serial_mm));
 +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
 +
 +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
 +    qemu_fdt_add_subnode(mc->fdt, nodename);
 +    qemu_fdt_setprop_string(mc->fdt, nodename,
 +                            "compatible", "qemu,fw-cfg-mmio");
 +    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
 +                                 2, base, 2, size);
 +    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 +    g_free(nodename);
 +    return fw_cfg;
 +}
 +
- static void virt_machine_init(MachineState *machine)
++static void mchp_pfsoc_mmuart_init(Object *obj)
  {
-     const MemMapEntry *memmap = virt_memmap;
+-    MchpPfSoCMMUartState *s;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
++    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
-         start_addr = virt_memmap[VIRT_FLASH].base;
-     }
+-    s = g_new0(MchpPfSoCMMUartState, 1);
++    object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
-+    /*
++    object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
++}
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-+     */
+-    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
-+    s->fw_cfg = create_fw_cfg(machine);
++static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
-+    rom_set_fw(s->fw_cfg);
++{
 +    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
 -    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
 +    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
 +    qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
 +    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
 +                        DEVICE_LITTLE_ENDIAN);
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
 +        return;
 +    }
 +
-     /* Compute the fdt load address in dram */
++    sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
++
-                                    machine->ram_size, machine->fdt);
++    memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
++    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/riscv/Kconfig
++    memory_region_add_subregion(&s->container, 0,
-+++ b/hw/riscv/Kconfig
++                    sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
++
-     select SIFIVE_PLIC
++    memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
-     select SIFIVE_TEST
+                           "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
-     select VIRTIO_MMIO
+     memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
-+    select FW_CFG_DMA
++}
- config SIFIVE_E
+-    s->base = base;
-     bool
+-    s->irq = irq;
 +static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
 +    .name = "mchp.pfsoc.uart",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
 +                             MCHP_PFSOC_MMUART_REG_COUNT),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = mchp_pfsoc_mmuart_realize;
 +    dc->reset = mchp_pfsoc_mmuart_reset;
 +    dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
 +    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 +}
 +
 +static const TypeInfo mchp_pfsoc_mmuart_info = {
 +    .name          = TYPE_MCHP_PFSOC_UART,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MchpPfSoCMMUartState),
 +    .instance_init = mchp_pfsoc_mmuart_init,
 +    .class_init    = mchp_pfsoc_mmuart_class_init,
 +};
 +
 +static void mchp_pfsoc_mmuart_register_types(void)
 +{
 +    type_register_static(&mchp_pfsoc_mmuart_info);
 +}
 +
 +type_init(mchp_pfsoc_mmuart_register_types)
 +
 +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
 +                                               hwaddr base,
 +                                               qemu_irq irq, Chardev *chr)
 +{
 +    DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 -    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
 -                               DEVICE_LITTLE_ENDIAN);
 +    qdev_prop_set_chr(dev, "chardev", chr);
 +    sysbus_realize(sbd, &error_fatal);
 -    memory_region_add_subregion(sysmem, base, &s->container);
 +    memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
 +    sysbus_connect_irq(sbd, 0, irq);
 -    return s;
 +    return MCHP_PFSOC_UART(dev);
  }
 --
-.30.1
+.31.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL 24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+At present the codes detect whether the DMA channel is claimed by:
 the address bytes. Note only SPI mode is supported by SST flashes.
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+  claimed = !!s->chan[ch].control & CONTROL_CLAIM;
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+As ! has higher precedence over & (bitwise and), this is essentially
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
+  claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;
 which is wrong, as any non-zero bit set in the control register will
 produce a result of a claimed channel.
 Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ hw/dma/sifive_pdma.c | 2 +-
-file changed, 3 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/dma/sifive_pdma.c
-+++ b/hw/block/m25p80.c
++++ b/hw/dma/sifive_pdma.c
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
-     s->needed_bytes = get_addr_length(s);
+     offset &= 0xfff;
-     switch (get_man(s)) {
+     switch (offset) {
-     /* Dummy cycles - modeled with bytes writes instead of bits */
+     case DMA_CONTROL:
-+    case MAN_SST:
+-        claimed = !!s->chan[ch].control & CONTROL_CLAIM;
-+        s->needed_bytes += 1;
++        claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
-+        break;
-     case MAN_WINBOND:
+         if (!claimed && (value & CONTROL_CLAIM)) {
-         s->needed_bytes += 8;
+             /* reset Next* registers */
          break;
 --
-.30.1
+.31.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+[PULL 25/26] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
-From: Jim Shu <cwshu@andestech.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Like MMU translation, add qemu log of PMP permission checking for
+If Control.run bit is set while not preserving the Control.claim
-debugging.
+bit, the DMA transfer shall not be started.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+The following result is PDMA tested in U-Boot on Unleashed board:
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
+=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
 => mw.l 0x3000000 0x1                      <= Claim channel 0
 => mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
 => mw.q 0x3000008 0x2                      <= NextBytes = 2
 => mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
 => mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
 => mw.l 0x84000000 0x87654321              <= Fill test data to dst
 => mw.l 0x84001000 0x12345678              <= Fill test data to src
 => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
 84000000: 87654321                               !Ce.
 84001000: 12345678                               xV4.
 => md.l 0x3000000 8                        <= Dump PDMA status
 03000000: 00000001 55000000 00000002 00000000    .......U........
 03000010: 84000000 00000000 84001000 00000000    ................
 => mw.l 0x3000000 0x2                      <= Set channel 0 run bit only
 => md.l 0x3000000 8                        <= Dump PDMA status
 03000000: 00000000 55000000 00000002 00000000    .......U........
 03000010: 84000000 00000000 84001000 00000000    ................
 => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
 84000000: 87654321                               !Ce.
 84001000: 12345678                               xV4.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++++++++
+ hw/dma/sifive_pdma.c | 11 +++++++++--
-file changed, 12 insertions(+)
+file changed, 9 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/hw/dma/sifive_pdma.c
-+++ b/target/riscv/cpu_helper.c
++++ b/hw/dma/sifive_pdma.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
-             if (ret == TRANSLATE_SUCCESS) {
+ {
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+     SiFivePDMAState *s = opaque;
-                                                size, access_type, mode);
+     int ch = SIFIVE_PDMA_CHAN_NO(offset);
 -    bool claimed;
 +    bool claimed, run;
      if (ch >= SIFIVE_PDMA_CHANS) {
          qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
      switch (offset) {
      case DMA_CONTROL:
          claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
 +        run = !!(s->chan[ch].control & CONTROL_RUN);
          if (!claimed && (value & CONTROL_CLAIM)) {
              /* reset Next* registers */
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
              s->chan[ch].next_src = 0;
          }
 +        /* claim bit can only be cleared when run is low */
 +        if (run && !(value & CONTROL_CLAIM)) {
 +            value |= CONTROL_CLAIM;
 +        }
 +
-+                qemu_log_mask(CPU_LOG_MMU,
+         s->chan[ch].control = value;
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
+         /*
-+                              __func__, pa, ret, prot_pmp, tlb_size);
+          * If channel was not claimed before run bit is set,
-+
++         * or if the channel is disclaimed when run was low,
-                 prot &= prot_pmp;
+          * DMA won't run.
-             }
+          */
+-        if (!claimed) {
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++        if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
-         if (ret == TRANSLATE_SUCCESS) {
+             s->chan[ch].control &= ~CONTROL_RUN;
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+             return;
                                             size, access_type, mode);
 +
 +            qemu_log_mask(CPU_LOG_MMU,
 +                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
 +                          " %d tlb_size " TARGET_FMT_lu "\n",
 +                          __func__, pa, ret, prot_pmp, tlb_size);
 +
              prot &= prot_pmp;
          }
-     }
 --
-.30.1
+.31.1

-New patch
+[PULL 26/26] hw/riscv: shakti_c: Mark as not user creatable
+From: Alistair Francis <alistair.francis@wdc.com>
+Mark the shakti_c machine as not user creatable.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
+---
+ hw/riscv/shakti_c.c | 7 +++++++
+file changed, 7 insertions(+)
+diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/shakti_c.c
++++ b/hw/riscv/shakti_c.c
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+ {
+     DeviceClass *dc = DEVICE_CLASS(klass);
+     dc->realize = shakti_c_soc_state_realize;
++    /*
++     * Reasons:
++     *     - Creates CPUS in riscv_hart_realize(), and can create unintended
++     *       CPUs
++     *     - Uses serial_hds in realize function, thus can't be used twice
++     */
++    dc->user_creatable = false;
+ }
+ static void shakti_c_soc_instance_init(Object *obj)
+--
+.31.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def:

Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007

for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07:

hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 6.2

- Add Zb[abcs] instruction support
 - Remove RVB support
 - Bug fix of setting mstatus_hs.[SD|FS] bits
 - Mark some UART devices as 'input'
 - QOMify PolarFire MMUART
 - Fixes for sifive PDMA
 - Mark shakti_c as not user creatable

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: shakti_c: Mark as not user creatable

Bin Meng (5):
      hw/char: ibex_uart: Register device in 'input' category
      hw/char: shakti_uart: Register device in 'input' category
      hw/char: sifive_uart: Register device in 'input' category
      hw/dma: sifive_pdma: Fix Control.claim bit detection
      hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed

Frank Chang (1):
      target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

Philipp Tomsich (16):
      target/riscv: Introduce temporary in gen_add_uw()
      target/riscv: fix clzw implementation to operate on arg1
      target/riscv: clwz must ignore high bits (use shift-left & changed logic)
      target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
      target/riscv: Reassign instructions to the Zba-extension
      target/riscv: Remove the W-form instructions from Zbs
      target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
      target/riscv: Reassign instructions to the Zbs-extension
      target/riscv: Add instructions of the Zbc-extension
      target/riscv: Reassign instructions to the Zbb-extension
      target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
      target/riscv: Add a REQUIRE_32BIT macro
      target/riscv: Add rev8 instruction, removing grev/grevi
      target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
      target/riscv: Remove RVB (replaced by Zb[abcs])
      disas/riscv: Add Zb[abcs] instructions

Philippe Mathieu-Daudé (3):
      hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
      hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
      hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1.  Fix these
regressions by introducing a temporary.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(3)
 
 static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
 {
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_add_tl(ret, arg1, arg2);
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext32u_tl(t, arg1);
+    tcg_gen_add_tl(ret, t, arg2);
+    tcg_temp_free(t);
 }
 
 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
	bseti	a2, zero, 63
	addi	a2, a2, 392
	clzw    a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).

Fix this by changing the implementation to:
 1. shift the original register up by 32
 2. performs a target-length (64bit) clz
 3. return 32 if no bits are set

Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed).  Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-    tcg_gen_clzi_tl(ret, arg1, 64);
-    tcg_gen_subi_tl(ret, ret, 32);
+    TCGv t = tcg_temp_new();
+    tcg_gen_shli_tl(t, arg1, 32);
+    tcg_gen_clzi_tl(ret, t, 32);
+    tcg_temp_free(t);
 }
 
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
+    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
 static void gen_ctzw(TCGv ret, TCGv arg1)
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension.  The first
new instructions through the door (these have completed public review)
are Zb[abcs].

This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 4 ++++
 target/riscv/cpu.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_u;
         bool ext_h;
         bool ext_v;
+        bool ext_zba;
+        bool ext_zbb;
+        bool ext_zbc;
+        bool ext_zbs;
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zba:
 - add.uw (RV64 only)
 - sh[123]add (RV32 and RV64)
 - sh[123]add.uw (RV64-only)
 - slli.uw (RV64-only)

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 20 ++++++++++++--------
 target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
 2 files changed, 23 insertions(+), 13 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
instructions for Zbs (single-bit instructions).  Remove them.

Note that these instructions had already been removed for the 0.93
version of the draft-B extention and have not been present in the
binutils patches circulating in January 2021.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  7 ----
 target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
 2 files changed, 63 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  8 ---
 target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
 2 files changed, 78 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zbs:
 - b{set,clr,ext,inv}
 - b{set,clr,ext,inv}i

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 17 +++++++++--------
 target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
 2 files changed, 24 insertions(+), 18 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zbc:
 - clmul
 - clmulh
 - clmulr

Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 ++
 target/riscv/insn32.decode              |  5 ++++
 target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
 4 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
+# *** RV32 Zbc Standard Extension ***
+clmul      0000101 .......... 001 ..... 0110011 @r
+clmulh     0000101 .......... 011 ..... 0110011 @r
+clmulr     0000101 .......... 010 ..... 0110011 @r
+
 # *** RV32 Zbs Standard Extension ***
 bclr       0100100 .......... 001 ..... 0110011 @r
 bclri      01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
 {
     return do_gorc(rs1, rs2, 32);
 }
+
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
+{
+    target_ulong result = 0;
+
+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
+        if ((rs2 >> i) & 1) {
+            result ^= (rs1 << i);
+        }
+    }
+
+    return result;
+}
+
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+{
+    target_ulong result = 0;
+
+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
+        if ((rs2 >> i) & 1) {
+            result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
+        }
+    }
+
+    return result;
+}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
 /*
- * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+ * RISC-V translation routines for the Zb[acs] Standard Extension.
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBC(ctx) do {                    \
+    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_ZBS(ctx) do {                    \
     if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
         return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
     REQUIRE_ZBA(ctx);
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
 }
+
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
+}
+
+static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
+{
+     gen_helper_clmulr(dst, src1, src2);
+     tcg_gen_shri_tl(dst, dst, 1);
+}
+
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
+}
+
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
+}
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 40 ++++++++++---------
 target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
 2 files changed, 50 insertions(+), 41 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 slli_uw    00001 ............ 001 ..... 0011011 @sh
 
-# *** RV32B Standard Extension ***
+# *** RV32 Zbb Standard Extension ***
+andn       0100000 .......... 111 ..... 0110011 @r
 clz        011000 000000 ..... 001 ..... 0010011 @r2
-ctz        011000 000001 ..... 001 ..... 0010011 @r2
 cpop       011000 000010 ..... 001 ..... 0010011 @r2
+ctz        011000 000001 ..... 001 ..... 0010011 @r2
+max        0000101 .......... 110 ..... 0110011 @r
+maxu       0000101 .......... 111 ..... 0110011 @r
+min        0000101 .......... 100 ..... 0110011 @r
+minu       0000101 .......... 101 ..... 0110011 @r
+orn        0100000 .......... 110 ..... 0110011 @r
+rol        0110000 .......... 001 ..... 0110011 @r
+ror        0110000 .......... 101 ..... 0110011 @r
+rori       01100 ............ 101 ..... 0010011 @sh
 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
-
-andn       0100000 .......... 111 ..... 0110011 @r
-orn        0100000 .......... 110 ..... 0110011 @r
 xnor       0100000 .......... 100 ..... 0110011 @r
+
+# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw       0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+rolw       0110000 .......... 001 ..... 0111011 @r
+roriw      0110000 .......... 101 ..... 0011011 @sh5
+rorw       0110000 .......... 101 ..... 0111011 @r
+
+# *** RV32B Standard Extension ***
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
-min        0000101 .......... 100 ..... 0110011 @r
-minu       0000101 .......... 101 ..... 0110011 @r
-max        0000101 .......... 110 ..... 0110011 @r
-maxu       0000101 .......... 111 ..... 0110011 @r
-ror        0110000 .......... 101 ..... 0110011 @r
-rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
 gorc       0010100 .......... 101 ..... 0110011 @r
 
-rori       01100. ........... 101 ..... 0010011 @sh
 grevi      01101. ........... 101 ..... 0010011 @sh
 gorci      00101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
-clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
-
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
-rorw       0110000 .......... 101 ..... 0111011 @r
-rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
 
-roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
 /*
- * RISC-V translation routines for the Zb[acs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] Standard Extension.
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBB(ctx) do {                    \
+    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_ZBC(ctx) do {                    \
     if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
         return false;                            \
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
 {
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, gen_clz);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
 
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
 static bool trans_andn(DisasContext *ctx, arg_andn *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
 }
 
 static bool trans_orn(DisasContext *ctx, arg_orn *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
 }
 
 static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
 
 static bool trans_min(DisasContext *ctx, arg_min *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
 }
 
 static bool trans_max(DisasContext *ctx, arg_max *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
 }
 
 static bool trans_minu(DisasContext *ctx, arg_minu *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
 }
 
 static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
 }
 
 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
 }
 
 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
 
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
 }
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
 }
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_ctzw(TCGv ret, TCGv arg1)
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift(ctx, a, EXT_NONE, gen_rorw);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain gorc/gorci.  Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.

This commit adds the new orc.b instruction and removed gorc/gorci.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 --
 target/riscv/insn32.decode              |  6 +---
 target/riscv/bitmanip_helper.c          | 26 -----------------
 target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
 4 files changed, 18 insertions(+), 55 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ max        0000101 .......... 110 ..... 0110011 @r
 maxu       0000101 .......... 111 ..... 0110011 @r
 min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
+orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 orn        0100000 .......... 110 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
-gorc       0010100 .......... 101 ..... 0110011 @r
-
 grevi      01101. ........... 101 ..... 0010011 @sh
-gorci      00101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
-gorcw      0010100 .......... 101 ..... 0111011 @r
 
 greviw     0110100 .......... 101 ..... 0011011 @sh5
-gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
     return do_grev(rs1, rs2, 32);
 }
 
-static target_ulong do_gorc(target_ulong rs1,
-                            target_ulong rs2,
-                            int bits)
-{
-    target_ulong x = rs1;
-    int i, shift;
-
-    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-        if (rs2 & shift) {
-            x |= do_swap(x, adjacent_masks[i], shift);
-        }
-    }
-
-    return x;
-}
-
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-{
-    return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-{
-    return do_gorc(rs1, rs2, 32);
-}
-
 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
 {
     target_ulong result = 0;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
 }
 
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+static void gen_orc_b(TCGv ret, TCGv source1)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+    TCGv  tmp = tcg_temp_new();
+    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+
+    /* Set lsb in each byte if the byte was zero. */
+    tcg_gen_sub_tl(tmp, source1, ones);
+    tcg_gen_andc_tl(tmp, tmp, source1);
+    tcg_gen_shri_tl(tmp, tmp, 7);
+    tcg_gen_andc_tl(tmp, ones, tmp);
+
+    /* Replicate the lsb of each byte across the byte. */
+    tcg_gen_muli_tl(ret, tmp, 0xff);
+
+    tcg_temp_free(tmp);
 }
 
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
 }
 
 #define GEN_SHADD(SHAMT)                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
     return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
 }
 
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
 #define GEN_SHADD_UW(SHAMT)                                       \
 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 {                                                                 \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
+#define REQUIRE_32BIT(ctx) do { \
+    if (!is_32bit(ctx)) {       \
+        return false;           \
+    }                           \
+} while (0)
+
 #define REQUIRE_64BIT(ctx) do { \
     if (is_32bit(ctx)) {        \
         return false;           \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.

This commit adds the new rev8 instruction and removes grev/grevi.

Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 --
 target/riscv/insn32.decode              | 12 ++++----
 target/riscv/bitmanip_helper.c          | 40 -------------------------
 target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
 4 files changed, 15 insertions(+), 79 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Bitmanip */
-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 orn        0100000 .......... 110 ..... 0110011 @r
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 rol        0110000 .......... 001 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rori       01100 ............ 101 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ xnor       0100000 .......... 100 ..... 0110011 @r
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+# The encoding for rev8 differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
 rolw       0110000 .......... 001 ..... 0111011 @r
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 rorw       0110000 .......... 101 ..... 0111011 @r
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
-grev       0110100 .......... 101 ..... 0110011 @r
-grevi      01101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
-grevw      0110100 .......... 101 ..... 0111011 @r
-
-greviw     0110100 .......... 101 ..... 0011011 @sh5
 
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg.h"
 
-static const uint64_t adjacent_masks[] = {
-    dup_const(MO_8, 0x55),
-    dup_const(MO_8, 0x33),
-    dup_const(MO_8, 0x0f),
-    dup_const(MO_16, 0xff),
-    dup_const(MO_32, 0xffff),
-    UINT32_MAX
-};
-
-static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
-{
-    return ((x & mask) << shift) | ((x & ~mask) >> shift);
-}
-
-static target_ulong do_grev(target_ulong rs1,
-                            target_ulong rs2,
-                            int bits)
-{
-    target_ulong x = rs1;
-    int i, shift;
-
-    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-        if (rs2 & shift) {
-            x = do_swap(x, adjacent_masks[i], shift);
-        }
-    }
-
-    return x;
-}
-
-target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
-{
-    return do_grev(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
-{
-    return do_grev(rs1, rs2, 32);
-}
-
 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
 {
     target_ulong result = 0;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
-static bool trans_grev(DisasContext *ctx, arg_grev *a)
+static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
-}
-
-static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
-{
-    if (shamt == TARGET_LONG_BITS - 8) {
-        /* rev8, byte swaps */
-        tcg_gen_bswap_tl(dest, src);
-    } else {
-        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
-    }
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
 }
 
-static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
 }
 
 static void gen_orc_b(TCGv ret, TCGv source1)
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
 
-static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
-static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
 #define GEN_SHADD_UW(SHAMT)                                       \
 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 {                                                                 \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.

This commit adds zext.h and removes the pack* instructions.

Note that the encodings for zext.h are different between RV32 and
RV64, which is handled through REQUIRE_32BIT.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 12 ++--
 target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
 2 files changed, 21 insertions(+), 77 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.

Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
  https://lists.riscv.org/g/tech-bitmanip/message/532

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 ---
 target/riscv/insn32.decode |  4 ----
 target/riscv/cpu.c         | 26 --------------------------
 3 files changed, 33 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
-#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
@@ -XXX,XX +XXX,XX @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
-#define BEXT_VERSION_0_93_0 0x00009300
 #define VEXT_VERSION_0_07_1 0x00000701
 
 enum {
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
-        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 # instruction, so we use different handler functions to differentiate.
 zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 
-# *** RV32B Standard Extension ***
-
-# *** RV64B Standard Extension (in addition to RV32B) ***
-
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
 clmulh     0000101 .......... 011 ..... 0110011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
     env->priv_ver = priv_ver;
 }
 
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
-    env->bext_ver = bext_ver;
-}
-
 static void set_vext_version(CPURISCVState *env, int vext_ver)
 {
     env->vext_ver = vext_ver;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
-        if (cpu->cfg.ext_b) {
-            int bext_version = BEXT_VERSION_0_93_0;
-            target_misa |= RVB;
-
-            if (cpu->cfg.bext_spec) {
-                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
-                    bext_version = BEXT_VERSION_0_93_0;
-                } else {
-                    error_setg(errp,
-                           "Unsupported bitmanip spec version '%s'",
-                           cpu->cfg.bext_spec);
-                    return;
-                }
-            } else {
-                qemu_log("bitmanip version is not specified, "
-                         "use the default value v0.93\n");
-            }
-            set_bext_version(env, bext_version);
-        }
         if (cpu->cfg.ext_v) {
             int vext_version = VEXT_VERSION_0_07_1;
             target_misa |= RVV;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 154 insertions(+), 3 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_op_fsflags = 316,
     rv_op_fsrmi = 317,
     rv_op_fsflagsi = 318,
+    rv_op_bseti = 319,
+    rv_op_bclri = 320,
+    rv_op_binvi = 321,
+    rv_op_bexti = 322,
+    rv_op_rori = 323,
+    rv_op_clz = 324,
+    rv_op_ctz = 325,
+    rv_op_cpop = 326,
+    rv_op_sext_h = 327,
+    rv_op_sext_b = 328,
+    rv_op_xnor = 329,
+    rv_op_orn = 330,
+    rv_op_andn = 331,
+    rv_op_rol = 332,
+    rv_op_ror = 333,
+    rv_op_sh1add = 334,
+    rv_op_sh2add = 335,
+    rv_op_sh3add = 336,
+    rv_op_sh1add_uw = 337,
+    rv_op_sh2add_uw = 338,
+    rv_op_sh3add_uw = 339,
+    rv_op_clmul = 340,
+    rv_op_clmulr = 341,
+    rv_op_clmulh = 342,
+    rv_op_min = 343,
+    rv_op_minu = 344,
+    rv_op_max = 345,
+    rv_op_maxu = 346,
+    rv_op_clzw = 347,
+    rv_op_ctzw = 348,
+    rv_op_cpopw = 349,
+    rv_op_slli_uw = 350,
+    rv_op_add_uw = 351,
+    rv_op_rolw = 352,
+    rv_op_rorw = 353,
+    rv_op_rev8 = 354,
+    rv_op_zext_h = 355,
+    rv_op_roriw = 356,
+    rv_op_orc_b = 357,
+    rv_op_bset = 358,
+    rv_op_bclr = 359,
+    rv_op_binv = 360,
+    rv_op_bext = 361,
 } rv_op;
 
 /* structures */
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
+    { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 };
 
 /* CSR names */
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 0: op = rv_op_addi; break;
             case 1:
                 switch (((inst >> 27) & 0b11111)) {
-                case 0: op = rv_op_slli; break;
+                case 0b00000: op = rv_op_slli; break;
+                case 0b00101: op = rv_op_bseti; break;
+                case 0b01001: op = rv_op_bclri; break;
+                case 0b01101: op = rv_op_binvi; break;
+                case 0b01100:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0000000: op = rv_op_clz; break;
+                    case 0b0000001: op = rv_op_ctz; break;
+                    case 0b0000010: op = rv_op_cpop; break;
+                      /* 0b0000011 */
+                    case 0b0000100: op = rv_op_sext_b; break;
+                    case 0b0000101: op = rv_op_sext_h; break;
+                    }
+                    break;
                 }
                 break;
             case 2: op = rv_op_slti; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 4: op = rv_op_xori; break;
             case 5:
                 switch (((inst >> 27) & 0b11111)) {
-                case 0: op = rv_op_srli; break;
-                case 8: op = rv_op_srai; break;
+                case 0b00000: op = rv_op_srli; break;
+                case 0b00101: op = rv_op_orc_b; break;
+                case 0b01000: op = rv_op_srai; break;
+                case 0b01001: op = rv_op_bexti; break;
+                case 0b01100: op = rv_op_rori; break;
+                case 0b01101:
+                    switch ((inst >> 20) & 0b1111111) {
+                    case 0b0111000: op = rv_op_rev8; break;
+                    }
+                    break;
                 }
                 break;
             case 6: op = rv_op_ori; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 1:
                 switch (((inst >> 25) & 0b1111111)) {
                 case 0: op = rv_op_slliw; break;
+                case 4: op = rv_op_slli_uw; break;
+                case 48:
+                    switch ((inst >> 20) & 0b11111) {
+                    case 0b00000: op = rv_op_clzw; break;
+                    case 0b00001: op = rv_op_ctzw; break;
+                    case 0b00010: op = rv_op_cpopw; break;
+                    }
+                    break;
                 }
                 break;
             case 5:
                 switch (((inst >> 25) & 0b1111111)) {
                 case 0: op = rv_op_srliw; break;
                 case 32: op = rv_op_sraiw; break;
+                case 48: op = rv_op_roriw; break;
                 }
                 break;
             }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 13: op = rv_op_divu; break;
             case 14: op = rv_op_rem; break;
             case 15: op = rv_op_remu; break;
+            case 36:
+                switch ((inst >> 20) & 0b11111) {
+                case 0: op = rv_op_zext_h; break;
+                }
+                break;
+            case 41: op = rv_op_clmul; break;
+            case 42: op = rv_op_clmulr; break;
+            case 43: op = rv_op_clmulh; break;
+            case 44: op = rv_op_min; break;
+            case 45: op = rv_op_minu; break;
+            case 46: op = rv_op_max; break;
+            case 47: op = rv_op_maxu; break;
+            case 130: op = rv_op_sh1add; break;
+            case 132: op = rv_op_sh2add; break;
+            case 134: op = rv_op_sh3add; break;
+            case 161: op = rv_op_bset; break;
             case 256: op = rv_op_sub; break;
+            case 260: op = rv_op_xnor; break;
             case 261: op = rv_op_sra; break;
+            case 262: op = rv_op_orn; break;
+            case 263: op = rv_op_andn; break;
+            case 289: op = rv_op_bclr; break;
+            case 293: op = rv_op_bext; break;
+            case 385: op = rv_op_rol; break;
+            case 386: op = rv_op_ror; break;
+            case 417: op = rv_op_binv; break;
             }
             break;
         case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 13: op = rv_op_divuw; break;
             case 14: op = rv_op_remw; break;
             case 15: op = rv_op_remuw; break;
+            case 32: op = rv_op_add_uw; break;
+            case 36:
+                switch ((inst >> 20) & 0b11111) {
+                case 0: op = rv_op_zext_h; break;
+                }
+                break;
+            case 130: op = rv_op_sh1add_uw; break;
+            case 132: op = rv_op_sh2add_uw; break;
+            case 134: op = rv_op_sh3add_uw; break;
             case 256: op = rv_op_subw; break;
             case 261: op = rv_op_sraw; break;
+            case 385: op = rv_op_rolw; break;
+            case 389: op = rv_op_rorw; break;
             }
             break;
         case 16:
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
Modifying the floating-point state when V=1 causes both fields to
be set to 3 (Dirty).

However, it's possible that HS-level sstatus.FS is Clean and VS-level
vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1.
We can't early return for this case because we still need to set
sstatus.FS to Dirty according to spec.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210921020234.123448-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/translate.c | 30 +++++++++++++++++-------------
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, SEW, 5, 3)
 FIELD(TB_FLAGS, VILL, 8, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env);
 
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                 get_field(env->hstatus, HSTATUS_HU))) {
             flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
         }
+
+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+                           get_field(env->mstatus_hs, MSTATUS_FS));
     }
 #endif
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     target_ulong misa;
     uint32_t opcode;
     uint32_t mstatus_fs;
+    uint32_t mstatus_hs_fs;
     uint32_t mem_idx;
     /* Remember the rounding mode encoded in the previous fp instruction,
        which we have already installed into env->fp_status.  Or -1 for
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd;
+    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 
-    if (ctx->mstatus_fs == MSTATUS_FS) {
-        return;
-    }
-    /* Remember the state change for the rest of the TB.  */
-    ctx->mstatus_fs = MSTATUS_FS;
+    if (ctx->mstatus_fs != MSTATUS_FS) {
+        /* Remember the state change for the rest of the TB. */
+        ctx->mstatus_fs = MSTATUS_FS;
 
-    tmp = tcg_temp_new();
-    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+        tmp = tcg_temp_new();
+        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+        tcg_temp_free(tmp);
+    }
 
-    tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
-    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+    if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
+        /* Remember the stage change for the rest of the TB. */
+        ctx->mstatus_hs_fs = MSTATUS_FS;
 
-    if (ctx->virt_enabled) {
+        tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        tcg_temp_free(tmp);
     }
-    tcg_temp_free(tmp);
 }
 #else
 static inline void mark_fs_dirty(DisasContext *ctx) { }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->vlen = cpu->cfg.vlen;
+    ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
size occupied by all the registers. However all registers are
32-bit wide, and the MemoryRegionOps handlers are restricted to
32-bit:

static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
      .read = mchp_pfsoc_mmuart_read,
      .write = mchp_pfsoc_mmuart_write,
      .impl = {
          .min_access_size = 4,
          .max_access_size = 4,
      },

Avoid being triskaidekaphobic, simplify by using the number of
registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-2-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h |  4 ++--
 hw/char/mchp_pfsoc_mmuart.c         | 14 ++++++++------
 2 files changed, 10 insertions(+), 8 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Our device have 2 different I/O regions:
- a 16550 UART mapped for 32-bit accesses
- 13 extra registers

Instead of mapping each region on the main bus, introduce
a container, map the 2 devices regions on the container,
and map the container on the main bus.

Before:

(qemu) info mtree
    ...
    0000000020100000-000000002010001f (prio 0, i/o): serial
    0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020102000-000000002010201f (prio 0, i/o): serial
    0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020104000-000000002010401f (prio 0, i/o): serial
    0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020106000-000000002010601f (prio 0, i/o): serial
    0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart

After:

(qemu) info mtree
    ...
    0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020100000-000000002010001f (prio 0, i/o): serial
      0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020102000-000000002010201f (prio 0, i/o): serial
      0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020104000-000000002010401f (prio 0, i/o): serial
      0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020106000-000000002010601f (prio 0, i/o): serial
      0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210925133407.1259392-3-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h |  1 +
 hw/char/mchp_pfsoc_mmuart.c         | 11 ++++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
- Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
- Add DeviceReset() method
- Add vmstate structure for migration
- Register device in 'input' category
- Keep mchp_pfsoc_mmuart_create() behavior

Note, serial_mm_init() calls qdev_set_legacy_instance_id().
This call is only needed for backwards-compatibility of incoming
migration data with old versions of QEMU which implemented migration
of devices with hand-rolled code. Since this device didn't previously
handle migration at all, then it doesn't need to set the legacy
instance ID.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-4-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h | 12 +++-
 hw/char/mchp_pfsoc_mmuart.c         | 97 +++++++++++++++++++++++++----
 2 files changed, 93 insertions(+), 16 deletions(-)

diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/mchp_pfsoc_mmuart.h
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_MCHP_PFSOC_MMUART_H
 #define HW_MCHP_PFSOC_MMUART_H
 
+#include "hw/sysbus.h"
 #include "hw/char/serial.h"
 
 #define MCHP_PFSOC_MMUART_REG_COUNT 13
 
+#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
+OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
+
 typedef struct MchpPfSoCMMUartState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
     MemoryRegion container;
     MemoryRegion iomem;
-    hwaddr base;
-    qemu_irq irq;
 
-    SerialMM *serial;
+    SerialMM serial_mm;
 
     uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
 } MchpPfSoCMMUartState;
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/mchp_pfsoc_mmuart.c
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
-#include "chardev/char.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/qdev-properties.h"
 
 #define REGS_OFFSET 0x20
 
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
     },
 };
 
-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
-    hwaddr base, qemu_irq irq, Chardev *chr)
+static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
+{
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
+
+    memset(s->reg, 0, sizeof(s->reg));
+    device_cold_reset(DEVICE(&s->serial_mm));
+}
+
+static void mchp_pfsoc_mmuart_init(Object *obj)
 {
-    MchpPfSoCMMUartState *s;
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
 
-    s = g_new0(MchpPfSoCMMUartState, 1);
+    object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
+    object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
+}
 
-    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
+static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
 
-    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
+    qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
+                        DEVICE_LITTLE_ENDIAN);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
+        return;
+    }
+
+    sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
+
+    memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
+
+    memory_region_add_subregion(&s->container, 0,
+                    sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
                           "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
     memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
+}
 
-    s->base = base;
-    s->irq = irq;
+static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
+    .name = "mchp.pfsoc.uart",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
+                             MCHP_PFSOC_MMUART_REG_COUNT),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = mchp_pfsoc_mmuart_realize;
+    dc->reset = mchp_pfsoc_mmuart_reset;
+    dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
+static const TypeInfo mchp_pfsoc_mmuart_info = {
+    .name          = TYPE_MCHP_PFSOC_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCMMUartState),
+    .instance_init = mchp_pfsoc_mmuart_init,
+    .class_init    = mchp_pfsoc_mmuart_class_init,
+};
+
+static void mchp_pfsoc_mmuart_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_mmuart_info);
+}
+
+type_init(mchp_pfsoc_mmuart_register_types)
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+                                               hwaddr base,
+                                               qemu_irq irq, Chardev *chr)
+{
+    DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
-    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
-                               DEVICE_LITTLE_ENDIAN);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize(sbd, &error_fatal);
 
-    memory_region_add_subregion(sysmem, base, &s->container);
+    memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
+    sysbus_connect_irq(sbd, 0, irq);
 
-    return s;
+    return MCHP_PFSOC_UART(dev);
 }
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

At present the codes detect whether the DMA channel is claimed by:

claimed = !!s->chan[ch].control & CONTROL_CLAIM;

As ! has higher precedence over & (bitwise and), this is essentially

claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;

which is wrong, as any non-zero bit set in the control register will
produce a result of a claimed channel.

Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/dma/sifive_pdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
     offset &= 0xfff;
     switch (offset) {
     case DMA_CONTROL:
-        claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+        claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
 
         if (!claimed && (value & CONTROL_CLAIM)) {
             /* reset Next* registers */
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

If Control.run bit is set while not preserving the Control.claim
bit, the DMA transfer shall not be started.

The following result is PDMA tested in U-Boot on Unleashed board:

=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
=> mw.l 0x3000000 0x1                      <= Claim channel 0
=> mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2                      <= NextBytes = 2
=> mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321              <= Fill test data to dst
=> mw.l 0x84001000 0x12345678              <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000001 55000000 00000002 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> mw.l 0x3000000 0x2                      <= Set channel 0 run bit only
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/dma/sifive_pdma.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
 {
     SiFivePDMAState *s = opaque;
     int ch = SIFIVE_PDMA_CHAN_NO(offset);
-    bool claimed;
+    bool claimed, run;
 
     if (ch >= SIFIVE_PDMA_CHANS) {
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
     switch (offset) {
     case DMA_CONTROL:
         claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
+        run = !!(s->chan[ch].control & CONTROL_RUN);
 
         if (!claimed && (value & CONTROL_CLAIM)) {
             /* reset Next* registers */
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
             s->chan[ch].next_src = 0;
         }
 
+        /* claim bit can only be cleared when run is low */
+        if (run && !(value & CONTROL_CLAIM)) {
+            value |= CONTROL_CLAIM;
+        }
+
         s->chan[ch].control = value;
 
         /*
          * If channel was not claimed before run bit is set,
+         * or if the channel is disclaimed when run was low,
          * DMA won't run.
          */
-        if (!claimed) {
+        if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
             s->chan[ch].control &= ~CONTROL_RUN;
             return;
         }
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Mark the shakti_c machine as not user creatable.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
---
 hw/riscv/shakti_c.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     dc->realize = shakti_c_soc_state_realize;
+    /*
+     * Reasons:
+     *     - Creates CPUS in riscv_hart_realize(), and can create unintended
+     *       CPUs
+     *     - Uses serial_hds in realize function, thus can't be used twice
+     */
+    dc->user_creatable = false;
 }
 
 static void shakti_c_soc_instance_init(Object *obj)
-- 
2.31.1