Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 00/11] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+  Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into staging (2021-07-12 19:15:11 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Fourth RISC-V PR for 6.1 release
-This PR includes:
+ - Code cleanups
- - Fix for vector CSR access
+ - Documentation improvements
- - Improvements to the Ibex UART device
+ - Hypervisor extension improvements with hideleg and hedeleg
- - PMP improvements and bug fixes
+ - sifive_u fixes
- - Hypervisor extension bug fixes
+ - OpenTitan register layout updates
  - ramfb support for the virt machine
  - Fast read support for SST flash
  - Improvements to the microchip_pfsoc machine
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Alistair Francis (3):
-      hw/char: disable ibex uart receive if the buffer is full
+      char: ibex_uart: Update the register layout
       hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
       hw/riscv: opentitan: Add the flash alias
-Asherah Connor (2):
+Bin Meng (7):
-      hw/riscv: Add fw_cfg support to virt
+      target/riscv: pmp: Fix some typos
-      hw/riscv: allow ramfb on virt
+      target/riscv: csr: Remove redundant check in fp csr read/write routines
       docs/system: riscv: Fix CLINT name in the sifive_u doc
       docs/system: riscv: Add documentation for virt machine
       docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
       hw/riscv: sifive_u: Correct the CLINT timebase frequency
       hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
-Bin Meng (3):
+Jose Martins (1):
-      hw/block: m25p80: Support fast read for SST flashes
+      target/riscv: hardwire bits in hideleg and hedeleg
       hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
       docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
-Frank Chang (1):
+ docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
-      target/riscv: fix vs() to return proper error code
+ docs/system/riscv/sifive_u.rst             |   2 +-
  docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
  docs/system/target-riscv.rst               |   1 +
  include/hw/riscv/opentitan.h               |   3 +
  hw/char/ibex_uart.c                        |  19 ++--
  hw/riscv/opentitan.c                       |   9 ++
  hw/riscv/sifive_u.c                        |  12 ++-
  target/riscv/csr.c                         |  37 +++-----
  target/riscv/pmp.c                         |  10 +--
 files changed, 233 insertions(+), 52 deletions(-)
  create mode 100644 docs/system/riscv/virt.rst
-Georg Kotheimer (6):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
-      target/riscv: Make VSTIP and VSEIP read-only in hip
-      target/riscv: Use background registers also for MSTATUS_MPV
-      target/riscv: Fix read and write accesses to vsip and vsie
-      target/riscv: Add proper two-stage lookup exception detection
-      target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
-      target/riscv: propagate PMP permission to TLB page
-      target/riscv: add log of PMP permission checking
-      target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
- docs/system/target-riscv.rst               |   1 +
- include/hw/char/ibex_uart.h                |   4 +
- include/hw/riscv/microchip_pfsoc.h         |   1 +
- include/hw/riscv/virt.h                    |   2 +
- target/riscv/cpu.h                         |   4 +
- target/riscv/pmp.h                         |   4 +-
- hw/block/m25p80.c                          |   3 +
- hw/char/ibex_uart.c                        |  23 +++-
- hw/riscv/microchip_pfsoc.c                 |   6 +
- hw/riscv/virt.c                            |  33 ++++++
- target/riscv/cpu.c                         |   1 +
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
- target/riscv/csr.c                         |  77 +++++++------
- target/riscv/pmp.c                         |  84 ++++++++++----
- target/riscv/translate.c                   | 179 +----------------------------
- hw/riscv/Kconfig                           |   1 +
-files changed, 367 insertions(+), 289 deletions(-)
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
-is not enabled.
-If -1 is returned, exception will be raised and cs->exception_index will
-be set to the negative return value. The exception will then be treated
-as an instruction access fault instead of illegal instruction fault.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
-     if (env->misa & RVV) {
-         return 0;
-     }
--    return -1;
-+    return -RISCV_EXCP_ILLEGAL_INST;
- }
- static int ctr(CPURISCVState *env, int csrno)
---
-.30.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 01/11] target/riscv: pmp: Fix some typos
-From: Jim Shu <cwshu@andestech.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+%s/CSP/CSR
-Fix it by propagating PMP permission to TLB page permission.
+%s/thie/the
-PMP permission checking also use MMU-style API to change TLB permission
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-and size.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Jim Shu <cwshu@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/pmp.c | 10 +++++-----
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+file changed, 5 insertions(+), 5 deletions(-)
  target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 files changed, 125 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
-+++ b/target/riscv/pmp.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
-     target_ulong val);
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode);
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-                          target_ulong *tlb_size);
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
- void pmp_update_rule_nums(CPURISCVState *env);
- uint32_t pmp_get_num_rules(CPURISCVState *env);
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
- #endif
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
-     env->load_res = -1;
- }
-+/*
-+ * get_physical_address_pmp - check PMP permission for this physical address
-+ *
-+ * Match the PMP region and check permission for this physical address and it's
-+ * TLB page. Returns 0 if the permission checking was successful
-+ *
-+ * @env: CPURISCVState
-+ * @prot: The returned protection attributes
-+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
-+ *            permission checking. NULL if not set TLB page for addr.
-+ * @addr: The physical address to be checked permission
-+ * @access_type: The type of MMU access
-+ * @mode: Indicates current privilege level.
-+ */
-+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
-+                                    target_ulong *tlb_size, hwaddr addr,
-+                                    int size, MMUAccessType access_type,
-+                                    int mode)
-+{
-+    pmp_priv_t pmp_priv;
-+    target_ulong tlb_size_pmp = 0;
-+
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
-+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-+        return TRANSLATE_SUCCESS;
-+    }
-+
-+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
-+                            mode)) {
-+        *prot = 0;
-+        return TRANSLATE_PMP_FAIL;
-+    }
-+
-+    *prot = pmp_priv_to_page_prot(pmp_priv);
-+    if (tlb_size != NULL) {
-+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
-+            *tlb_size = tlb_size_pmp;
-+        }
-+    }
-+
-+    return TRANSLATE_SUCCESS;
-+}
-+
- /* get_physical_address - get the physical address for this virtual address
-  *
-  * Do a page table walk to obtain the physical address corresponding to a
-@@ -XXX,XX +XXX,XX @@ restart:
-             pte_addr = base + idx * ptesize;
-         }
--        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
--            1 << MMU_DATA_LOAD, PRV_S)) {
-+        int pmp_prot;
-+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
-+                                               sizeof(target_ulong),
-+                                               MMU_DATA_LOAD, PRV_S);
-+        if (pmp_ret != TRANSLATE_SUCCESS) {
-             return TRANSLATE_PMP_FAIL;
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- #ifndef CONFIG_USER_ONLY
-     vaddr im_address;
-     hwaddr pa = 0;
--    int prot, prot2;
-+    int prot, prot2, prot_pmp;
-     bool pmp_violation = false;
-     bool first_stage_error = true;
-     bool two_stage_lookup = false;
-     int ret = TRANSLATE_FAIL;
-     int mode = mmu_idx;
--    target_ulong tlb_size = 0;
-+    /* default TLB page size */
-+    target_ulong tlb_size = TARGET_PAGE_SIZE;
-     env->guest_phys_fault_addr = 0;
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             prot &= prot2;
--            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--                (ret == TRANSLATE_SUCCESS) &&
--                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--                ret = TRANSLATE_PMP_FAIL;
-+            if (ret == TRANSLATE_SUCCESS) {
-+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                               size, access_type, mode);
-+                prot &= prot_pmp;
-             }
-             if (ret != TRANSLATE_SUCCESS) {
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                       "%s address=%" VADDR_PRIx " ret %d physical "
-                       TARGET_FMT_plx " prot %d\n",
-                       __func__, address, ret, pa, prot);
--    }
--    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
--        (ret == TRANSLATE_SUCCESS) &&
--        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--        ret = TRANSLATE_PMP_FAIL;
-+        if (ret == TRANSLATE_SUCCESS) {
-+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                           size, access_type, mode);
-+            prot &= prot_pmp;
-+        }
-     }
-+
-     if (ret == TRANSLATE_PMP_FAIL) {
-         pmp_violation = true;
-     }
-     if (ret == TRANSLATE_SUCCESS) {
--        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
--            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
--                         prot, mmu_idx, tlb_size);
--        } else {
--            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--                         prot, mmu_idx, TARGET_PAGE_SIZE);
--        }
-+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-+                     prot, mmu_idx, tlb_size);
-         return true;
-     } else if (probe) {
-         return false;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
+@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
      return result;
  }
-+/*
-+ * Check if the address has required RWX privs when no PMP entry is matched.
-+ */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
-+    target_ulong mode)
-+{
-+    bool ret;
-+
-+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-+        /*
-+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
-+         * or no PMP entry matches an M-Mode access, the access succeeds.
-+         */
-+        ret = true;
-+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-+    } else {
-+        /*
-+         * Other modes are not allowed to succeed if they don't * match a rule,
-+         * but there are rules. We've checked for no rule earlier in this
-+         * function.
-+         */
-+        ret = false;
-+        *allowed_privs = 0;
-+    }
-+
-+    return ret;
-+}
-+
  /*
-  * Public Interface
+- * Handle a write to a pmpcfg CSP
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
++ * Handle a write to a pmpcfg CSR
   * Check if the address has required RWX privs to complete desired operation
   */
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
--    target_ulong size, pmp_priv_t privs, target_ulong mode)
+     target_ulong val)
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
-+    target_ulong mode)
  /*
 - * Handle a read from a pmpcfg CSP
 + * Handle a read from a pmpcfg CSR
   */
  target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
  {
-     int i = 0;
+@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
-     int ret = -1;
-     int pmp_size = 0;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
      /* No rule matched */
      if (ret == -1) {
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
 -
  /*
-  * Handle a write to a pmpcfg CSP
+- * Handle a write to a pmpaddr CSP
 + * Handle a write to a pmpaddr CSR
   */
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+     target_ulong val)
-     return false;
+@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
- }
-+
-+/*
+ /*
-+ * Convert PMP privilege to TLB page privilege.
+- * Handle a read from a pmpaddr CSP
-+ */
++ * Handle a read from a pmpaddr CSR
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+  */
-+{
+ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
-+    int prot = 0;
+ {
-+
+@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
-+    if (pmp_priv & PMP_READ) {
-+        prot |= PAGE_READ;
+ /*
-+    }
+  * Calculate the TLB size if the start address or the end address of
-+    if (pmp_priv & PMP_WRITE) {
+- * PMP entry is presented in thie TLB page.
-+        prot |= PAGE_WRITE;
++ * PMP entry is presented in the TLB page.
-+    }
+  */
-+    if (pmp_priv & PMP_EXEC) {
+ static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
-+        prot |= PAGE_EXEC;
+                                      target_ulong tlb_sa, target_ulong tlb_ea)
 +    }
 +
 +    return prot;
 +}
 --
-.30.1
+.31.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+The following check:
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
         return -RISCV_EXCP_ILLEGAL_INST;
     }
 is redundant in fflags/frm/fcsr read/write routines, as the check was
 already done in fs().
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ target/riscv/csr.c | 24 ------------------------
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 24 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@ static RISCVException epmp(CPURISCVState *env, int csrno)
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+ static RISCVException read_fflags(CPURISCVState *env, int csrno,
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+                                   target_ulong *val)
  static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 -static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 +static const target_ulong hip_writable_mask = MIP_VSSIP;
 +static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
  static const target_ulong vsip_writable_mask = MIP_VSSIP;
  static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+-#if !defined(CONFIG_USER_ONLY)
--                      write_mask & hip_writable_mask);
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-+                      write_mask & hvip_writable_mask);
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
--    *ret_value &= hip_writable_mask;
+-#endif
-+    *ret_value &= hvip_writable_mask;
+     *val = riscv_cpu_get_fflags(env);
+     return RISCV_EXCP_NONE;
      return ret;
  }
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
+ static RISCVException read_frm(CPURISCVState *env, int csrno,
+                                target_ulong *val)
+ {
+-#if !defined(CONFIG_USER_ONLY)
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
+-#endif
+     *val = env->frm;
+     return RISCV_EXCP_NONE;
+ }
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
+                                 target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
+ static RISCVException read_fcsr(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
+ {
+-#if !defined(CONFIG_USER_ONLY)
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
+-#endif
+     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
+         | (env->frm << FSR_RD_SHIFT);
+     if (vs(env, csrno) >= 0) {
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
+                                  target_ulong val)
+ {
+ #if !defined(CONFIG_USER_ONLY)
+-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-        return RISCV_EXCP_ILLEGAL_INST;
+-    }
+     env->mstatus |= MSTATUS_FS;
+ #endif
+     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 --
-.30.1
+.31.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-The current condition for the use of background registers only
+It's Core *Local* Interruptor, not 'Level'.
 considers the hypervisor load and store instructions,
 but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ docs/system/riscv/sifive_u.rst | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/docs/system/riscv/sifive_u.rst
-+++ b/target/riscv/cpu_helper.c
++++ b/docs/system/riscv/sifive_u.rst
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ The ``sifive_u`` machine supports the following devices:
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
+ * 1 E51 / E31 core
-      */
+ * Up to 4 U54 / U34 cores
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+-* Core Level Interruptor (CLINT)
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
++* Core Local Interruptor (CLINT)
-         use_background = true;
+ * Platform-Level Interrupt Controller (PLIC)
-     }
+ * Power, Reset, Clock, Interrupt (PRCI)
+ * L2 Loosely Integrated Memory (L2-LIM)
 --
-.30.1
+.31.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 04/11] docs/system: riscv: Add documentation for virt machine
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-This adds the documentation to describe what is supported for the
+This adds detailed documentation for RISC-V `virt` machine,
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+including the following information:
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+  - Supported devices
   - Hardware configuration information
   - Boot options
   - Running Linux kernel
   - Running U-Boot
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ docs/system/riscv/virt.rst   | 138 +++++++++++++++++++++++++++++++++++
- docs/system/target-riscv.rst               |  1 +
+ docs/system/target-riscv.rst |   1 +
-files changed, 90 insertions(+)
+files changed, 139 insertions(+)
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ create mode 100644 docs/system/riscv/virt.rst
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
++++ b/docs/system/riscv/virt.rst
 @@ -XXX,XX +XXX,XX @@
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
++'virt' Generic Virtual Platform (``virt``)
-+=============================================================
++==========================================
 +
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
++The `virt` board is a platform which does not correspond to any real hardware;
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
++it is designed for use in virtual machines. It is the recommended board type
-+
++if you simply want to run a guest such as Linux and do not care about
-+For more details about Microchip PolarFire SoC, please see:
++reproducing the idiosyncrasies and limitations of a particular bit of
-+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
++real-world hardware.
 +
 +The Icicle Kit board information can be found here:
 +https://www.microsemi.com/existing-parts/parts/152514
 +
 +Supported devices
 +-----------------
 +
-+The ``microchip-icicle-kit`` machine supports the following devices:
++The ``virt`` machine supports the following devices:
 +
-+ * 1 E51 core
++* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
-+ * 4 U54 cores
++* Core Local Interruptor (CLINT)
-+ * Core Level Interruptor (CLINT)
++* Platform-Level Interrupt Controller (PLIC)
-+ * Platform-Level Interrupt Controller (PLIC)
++* CFI parallel NOR flash memory
-+ * L2 Loosely Integrated Memory (L2-LIM)
++* 1 NS16550 compatible UART
-+ * DDR memory controller
++* 1 Google Goldfish RTC
-+ * 5 MMUARTs
++* 1 SiFive Test device
-+ * 1 DMA controller
++* 8 virtio-mmio transport devices
-+ * 2 GEM Ethernet controllers
++* 1 generic PCIe host bridge
-+ * 1 SDHC storage controller
++* The fw_cfg device that allows a guest to obtain data from QEMU
 +
 +Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
 +can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
 +enables the hypervisor extension for RV64.
 +
 +Hardware configuration information
 +----------------------------------
 +
 +The ``virt`` machine automatically generates a device tree blob ("dtb")
 +which it passes to the guest, if there is no ``-dtb`` option. This provides
 +information about the addresses, interrupt lines and other configuration of
 +the various devices in the system. Guest software should discover the devices
 +that are present in the generated DTB.
 +
 +If users want to provide their own DTB, they can use the ``-dtb`` option.
 +These DTBs should have the following requirements:
 +
 +* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
 +* The /memory reg size should match QEMU’s selected ram_size via ``-m``
 +* Should contain a node for the CLINT device with a compatible string
 +  "riscv,clint0" if using with OpenSBI BIOS images
 +
 +Boot options
 +------------
 +
-+The ``microchip-icicle-kit`` machine can start using the standard -bios
++The ``virt`` machine can start using the standard -kernel functionality
-+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
++for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader
-+HSS loads the second stage bootloader U-Boot from an SD card. It does not
++with the default OpenSBI firmware image as the -bios. It also supports
-+support direct kernel loading via the -kernel option. One has to load kernel
++the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
-+from U-Boot.
++firmware and U-Boot proper (S-mode), using the standard -bios functionality.
 +
-+The memory is set to 1537 MiB by default which is the minimum required high
++Running Linux kernel
-+memory size by HSS. A sanity check on ram size is performed in the machine
++--------------------
 +init routine to prompt user to increase the RAM size to > 1537 MiB when less
 +than 1537 MiB ram is detected.
 +
-+Boot the machine
++Linux mainline v5.12 release is tested at the time of writing. To build a
-+----------------
++Linux mainline kernel that can be booted by the ``virt`` machine in
 +64-bit mode, simply configure the kernel using the defconfig configuration:
 +
-+HSS 2020.12 release is tested at the time of writing. To build an HSS image
++.. code-block:: bash
-+that can be booted by the ``microchip-icicle-kit`` machine, type the following
++
-+in the HSS source tree:
++  $ export ARCH=riscv
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ make defconfig
 +  $ make
 +
 +To boot the newly built Linux kernel in QEMU with the ``virt`` machine:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
 +      -display none -serial stdio \
 +      -kernel arch/riscv/boot/Image \
 +      -initrd /path/to/rootfs.cpio \
 +      -append "root=/dev/ram"
 +
 +To build a Linux mainline kernel that can be booted by the ``virt`` machine
 +in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
 +fix the 32-bit boot issue for Linux kernel v5.12.
 +
 +.. code-block:: bash
 +
 +  $ export ARCH=riscv
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch
 +  $ git am riscv.patch
 +  $ make rv32_defconfig
 +  $ make
 +
 +Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command
 +line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit
 +applications shall be used in order for kernel to boot to user space.
 +
 +Running U-Boot
 +--------------
 +
 +U-Boot mainline v2021.04 release is tested at the time of writing. To build an
 +S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use
 +the qemu-riscv64_smode_defconfig with similar commands as described above for Linux:
 +
 +.. code-block:: bash
 +
 +  $ export CROSS_COMPILE=riscv64-linux-
-+  $ cp boards/mpfs-icicle-kit-es/def_config .config
++  $ make qemu-riscv64_smode_defconfig
 +  $ make BOARD=mpfs-icicle-kit-es
 +
-+Download the official SD card image released by Microchip and prepare it for
++Boot the 64-bit U-Boot S-mode image directly:
 +QEMU usage:
 +
 +.. code-block:: bash
 +
-+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
-+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++      -display none -serial stdio \
-+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
++      -kernel /path/to/u-boot.bin
 +
-+Then we can boot the machine by:
++To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image
 +that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together,
 +build the U-Boot images using riscv64_spl_defconfig:
 +
 +.. code-block:: bash
 +
-+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
++  $ export CROSS_COMPILE=riscv64-linux-
-+      -bios path/to/hss.bin -sd path/to/sdcard.img \
++  $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
-+      -nic user,model=cadence_gem \
++  $ make qemu-riscv64_spl_defconfig
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
 +      -serial chardev:serial1
 +
-+With above command line, current terminal session will be used for the first
++The minimal QEMU commands to run U-Boot SPL are:
 +serial port. Open another terminal window, and use `minicom` to connect the
 +second serial port.
 +
 +.. code-block:: bash
 +
-+  $ minicom -D unix\#serial1.sock
++  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
 +      -display none -serial stdio \
 +      -bios /path/to/u-boot-spl \
 +      -device loader,file=/path/to/u-boot.itb,addr=0x80200000
 +
-+HSS output is on the first serial port (stdio) and U-Boot outputs on the
++To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
-+second serial port. U-Boot will automatically load the Linux kernel from
++riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
-+the SD card image.
++``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
 +
 +.. _HSS: https://github.com/polarfire-soc/hart-software-services
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/target-riscv.rst
 +++ b/docs/system/target-riscv.rst
 @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
- .. toctree::
+    riscv/microchip-icicle-kit
-    :maxdepth: 1
+    riscv/shakti-c
 +   riscv/microchip-icicle-kit
     riscv/sifive_u
++   riscv/virt
- RISC-V CPU features
  RISC-V CPU firmware
  -------------------
 --
-.30.1
+.31.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Jose Martins <josemartins90@gmail.com>
-The previous implementation was broken in many ways:
+The specification mandates for certain bits to be hardwired in the
- - Used mideleg instead of hideleg to mask accesses
+hypervisor delegation registers. This was not being enforced.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Jose Martins <josemartins90@gmail.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210522155902.374439-1-josemartins90@gmail.com
 [ Changes by AF:
  - Improve indentation
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/csr.c | 13 +++++++++++--
-file changed, 34 insertions(+), 34 deletions(-)
+file changed, 11 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
-     return write_mstatus(env, CSR_MSTATUS, newval);
  static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                             VS_MODE_INTERRUPTS;
 +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
  static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
                                       VS_MODE_INTERRUPTS;
  static const target_ulong delegable_excps =
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 +static const target_ulong vs_delegable_excps = delegable_excps &
 +    ~((1ULL << (RISCV_EXCP_S_ECALL)) |
 +      (1ULL << (RISCV_EXCP_VS_ECALL)) |
 +      (1ULL << (RISCV_EXCP_M_ECALL)) |
 +      (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 +      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 +      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 +      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
      SSTATUS_SUM | SSTATUS_MXR;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
  static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
                                      target_ulong val)
  {
 -    env->hedeleg = val;
 +    env->hedeleg = val & vs_delegable_excps;
      return RISCV_EXCP_NONE;
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno,
-+{
+ static RISCVException write_hideleg(CPURISCVState *env, int csrno,
-+    /* Shift the VS bits to their S bit location in vsie */
+                                     target_ulong val)
 +    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 +    return 0;
 +}
 +
  static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
  {
-     if (riscv_cpu_virt_enabled(env)) {
+-    env->hideleg = val;
--        /* Tell the guest the VS bits, shifted to the S bit locations */
++    env->hideleg = val & vs_delegable_ints;
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+     return RISCV_EXCP_NONE;
 +        read_vsie(env, CSR_VSIE, val);
      } else {
          *val = env->mie & env->mideleg;
      }
      return 0;
  }
--static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
-+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
- {
--    target_ulong newval;
-+    /* Shift the S bits to their VS bit location in mie */
-+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
-+    return write_mie(env, CSR_MIE, newval);
-+}
-+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
-+{
-     if (riscv_cpu_virt_enabled(env)) {
--        /* Shift the guests S bits to VS */
--        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
--                 ((val << 1) & VS_MODE_INTERRUPTS);
-+        write_vsie(env, CSR_VSIE, val);
-     } else {
--        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
-+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
-+                              (val & S_MODE_INTERRUPTS);
-+        write_mie(env, CSR_MIE, newval);
-     }
--    return write_mie(env, CSR_MIE, newval);
-+    return 0;
- }
- static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
-@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
-     return 0;
- }
-+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-+                    target_ulong new_value, target_ulong write_mask)
-+{
-+    /* Shift the S bits to their VS bit location in mip */
-+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
-+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
-+    *ret_value &= VS_MODE_INTERRUPTS;
-+    /* Shift the VS bits to their S bit location in vsip */
-+    *ret_value >>= 1;
-+    return ret;
-+}
-+
- static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
- {
-     int ret;
-     if (riscv_cpu_virt_enabled(env)) {
--        /* Shift the new values to line up with the VS bits */
--        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
--                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
--        ret &= vsip_writable_mask;
--        ret >>= 1;
-+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
-     } else {
-         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
-                       write_mask & env->mideleg & sip_writable_mask);
-@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
-     return 0;
- }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
--                    target_ulong new_value, target_ulong write_mask)
--{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & env->mideleg & vsip_writable_mask);
--    return ret;
--}
--
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
--{
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
--    return 0;
--}
--
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
--{
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
--    return write_mie(env, CSR_MIE, newval);
--}
--
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
- {
-     *val = env->vstvec;
 --
-.30.1
+.31.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
 From: Bin Meng <bin.meng@windriver.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+This adds a new section in the documentation to demonstrate how to
-the address bytes. Note only SPI mode is supported by SST flashes.
+use the new direct kernel boot feature for Microchip Icicle Kit,
 other than the HSS bootflow, using an upstream U-Boot v2021.07 image
 as an example.
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+It also updates the truth table to have a new '-dtb' column which is
 required by direct kernel boot.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
+Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++---
-file changed, 3 insertions(+)
+file changed, 47 insertions(+), 7 deletions(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/docs/system/riscv/microchip-icicle-kit.rst
-+++ b/hw/block/m25p80.c
++++ b/docs/system/riscv/microchip-icicle-kit.rst
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@ The user provided DTB should have the following requirements:
-     s->needed_bytes = get_addr_length(s);
-     switch (get_man(s)) {
+ QEMU follows below truth table to select which payload to execute:
-     /* Dummy cycles - modeled with bytes writes instead of bits */
-+    case MAN_SST:
+-=====  ========== =======
-+        s->needed_bytes += 1;
+--bios     -kernel payload
-+        break;
+-=====  ========== =======
-     case MAN_WINBOND:
+-    N           N     HSS
-         s->needed_bytes += 8;
+-    Y  don't care     HSS
-         break;
+-    N           Y  kernel
 -=====  ========== =======
 +===== ========== ========== =======
 +-bios    -kernel       -dtb payload
 +===== ========== ========== =======
 +    N          N don't care     HSS
 +    Y don't care don't care     HSS
 +    N          Y          Y  kernel
 +===== ========== ========== =======
  The memory is set to 1537 MiB by default which is the minimum required high
  memory size by HSS. A sanity check on ram size is performed in the machine
@@ -XXX,XX +XXX,XX @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the
  second serial port. U-Boot will automatically load the Linux kernel from
  the SD card image.
 +Direct Kernel Boot
 +------------------
 +
 +Sometimes we just want to test booting a new kernel, and transforming the
 +kernel image to the format required by the HSS bootflow is tedious. We can
 +use '-kernel' for direct kernel booting just like other RISC-V machines do.
 +
 +In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
 +used to boot an S-mode payload like U-Boot or OS kernel directly.
 +
 +For example, the following commands show building a U-Boot image from U-Boot
 +mainline v2021.07 for the Microchip Icicle Kit board:
 +
 +.. code-block:: bash
 +
 +  $ export CROSS_COMPILE=riscv64-linux-
 +  $ make microchip_mpfs_icicle_defconfig
 +
 +Then we can boot the machine by:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \
 +      -sd path/to/sdcard.img \
 +      -nic user,model=cadence_gem \
 +      -nic tap,ifname=tap,model=cadence_gem,script=no \
 +      -display none -serial stdio \
 +      -kernel path/to/u-boot/build/dir/u-boot.bin \
 +      -dtb path/to/u-boot/build/dir/u-boot.dtb
 +
 +CAVEATS:
 +
 +* Check the "stdout-path" property in the /chosen node in the DTB to determine
 +  which serial port is used for the serial console, e.g.: if the console is set
 +  to the second serial port, change to use "-serial null -serial stdio".
 +* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image
 +  ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence
 +  ``u-boot.bin`` has to be used which does contain one. To use the ELF image,
 +  we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
 +
  .. _HSS: https://github.com/polarfire-soc/hart-software-services
 --
-.30.1
+.31.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency
 From: Bin Meng <bin.meng@windriver.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+At present the CLINT timebase frequency is set to 10MHz on sifive_u,
-been updated to use a register mapped at 0x4f000000 instead of a
+but on the real hardware the timebase frequency is 1Mhz.
 GPIO to control whether eMMC or SD card is to be used. With this
 support the same HSS image can be used for both eMMC and SD card
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
 With this commit, HSS image built from 2020.12 release boots again.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ hw/riscv/sifive_u.c | 7 +++++--
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+file changed, 5 insertions(+), 2 deletions(-)
 files changed, 7 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/hw/riscv/sifive_u.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@
-     MICROCHIP_PFSOC_ENVM_DATA,
-     MICROCHIP_PFSOC_QSPI_XIP,
+ #include <libfdt.h>
-     MICROCHIP_PFSOC_IOSCB,
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
++/* CLINT timebase frequency */
-     MICROCHIP_PFSOC_DRAM_LO,
++#define CLINT_TIMEBASE_FREQ 1000000
      MICROCHIP_PFSOC_DRAM_LO_ALIAS,
      MICROCHIP_PFSOC_DRAM_HI,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
      [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
 +    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
      [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                      memmap[MICROCHIP_PFSOC_IOSCB].base);
 +    /* eMMC/SD mux */
 +    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
 +
-     /* QSPI Flash */
+ static const MemMapEntry sifive_u_memmap[] = {
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
+     [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
-                            "microchip.pfsoc.qspi_xip",
+     [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
      qemu_fdt_add_subnode(fdt, "/cpus");
      qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 -        SIFIVE_CLINT_TIMEBASE_FREQ);
 +        CLINT_TIMEBASE_FREQ);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
      sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
          memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 -        SIFIVE_CLINT_TIMEBASE_FREQ, false);
 +        CLINT_TIMEBASE_FREQ, false);
      if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
          return;
 --
-.30.1
+.31.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Bin Meng <bmeng.cn@gmail.com>
-Provides fw_cfg for the virt machine on riscv.  This enables
+Currently the firmware dynamic info (fw_dyn) is put right after
-using e.g.  ramfb later.
+the reset vector, which is not 8-byte aligned on RV64. OpenSBI
 fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
 which expects fw_dyn to be on the 8-byte boundary, otherwise the
 misaligned load exception may happen. Fortunately this does not
 cause any issue on QEMU, as QEMU does support misaligned load.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+RV32 does not have any issue as it is 4-byte aligned already.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Change to make sure it is 8-byte aligned which works for both
 RV32 and RV64.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ hw/riscv/sifive_u.c | 5 +++--
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+file changed, 3 insertions(+), 2 deletions(-)
  hw/riscv/Kconfig        |  1 +
 files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/hw/riscv/sifive_u.c
-+++ b/include/hw/riscv/virt.h
++++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
      DeviceState *plic[VIRT_SOCKETS_MAX];
      PFlashCFI01 *flash[2];
 +    FWCfgState *fw_cfg;
      int fdt_size;
  };
@@ -XXX,XX +XXX,XX @@ enum {
      VIRT_PLIC,
      VIRT_UART0,
      VIRT_VIRTIO,
 +    VIRT_FW_CFG,
      VIRT_FLASH,
      VIRT_DRAM,
      VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
      [VIRT_UART0] =       { 0x10000000,         0x100 },
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
 +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
      return dev;
  }
 +static FWCfgState *create_fw_cfg(const MachineState *mc)
 +{
 +    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
 +    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
 +    FWCfgState *fw_cfg;
 +    char *nodename;
 +
 +    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
 +                                  &address_space_memory);
 +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
 +
 +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
 +    qemu_fdt_add_subnode(mc->fdt, nodename);
 +    qemu_fdt_setprop_string(mc->fdt, nodename,
 +                            "compatible", "qemu,fw-cfg-mmio");
 +    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
 +                                 2, base, 2, size);
 +    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 +    g_free(nodename);
 +    return fw_cfg;
 +}
 +
  static void virt_machine_init(MachineState *machine)
  {
      const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          start_addr = virt_memmap[VIRT_FLASH].base;
      }
-+    /*
+     /* reset vector */
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+-    uint32_t reset_vec[11] = {
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
++    uint32_t reset_vec[12] = {
-+     */
+         s->msel,                       /* MSEL pin state */
-+    s->fw_cfg = create_fw_cfg(machine);
+x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-+    rom_set_fw(s->fw_cfg);
+-        0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
-+
++        0x02c28613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
-     /* Compute the fdt load address in dram */
+xf1402573,                    /*     csrr   a0, mhartid  */
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+,
-                                    machine->ram_size, machine->fdt);
+,
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-index XXXXXXX..XXXXXXX 100644
+         start_addr,                    /* start: .dword */
---- a/hw/riscv/Kconfig
+         start_addr_hi32,
-+++ b/hw/riscv/Kconfig
+         fdt_load_addr,                 /* fdt_laddr: .dword */
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
++        0x00000000,
-     select SIFIVE_PLIC
+x00000000,
-     select SIFIVE_TEST
+                                        /* fw_dyn: */
-     select VIRTIO_MMIO
+     };
 +    select FW_CFG_DMA
  config SIFIVE_E
      bool
 --
-.30.1
+.31.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 09/11] char: ibex_uart: Update the register layout
-From: Alexander Wagner <alexander.wagner@ulal.de>
+Update the register layout to match the latest OpenTitan bitstream.
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-the newest received byte. The rx_level variable is added to allow the use of
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-the existing OpenTitan driver libraries.
+Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
 ---
  hw/char/ibex_uart.c | 19 ++++++++++---------
 file changed, 10 insertions(+), 9 deletions(-)
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/ibex_uart.h |  4 ++++
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
-files changed, 22 insertions(+), 5 deletions(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
-+++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
- REG32(OVRD, 0x24)
- REG32(VAL, 0x28)
- REG32(TIMEOUT_CTRL, 0x2c)
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
-     uint32_t tx_level;
-+    uint32_t rx_level;
-+
-     QEMUTimer *fifo_trigger_handle;
-     uint64_t char_tx_time;
 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/ibex_uart.c
 +++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
+@@ -XXX,XX +XXX,XX @@ REG32(INTR_STATE, 0x00)
      FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
  REG32(INTR_ENABLE, 0x04)
  REG32(INTR_TEST, 0x08)
 -REG32(CTRL, 0x0C)
 +REG32(ALERT_TEST, 0x0C)
 +REG32(CTRL, 0x10)
      FIELD(CTRL, TX_ENABLE, 0, 1)
      FIELD(CTRL, RX_ENABLE, 1, 1)
      FIELD(CTRL, NF, 2, 1)
@@ -XXX,XX +XXX,XX @@ REG32(CTRL, 0x0C)
      FIELD(CTRL, PARITY_ODD, 7, 1)
      FIELD(CTRL, RXBLVL, 8, 2)
      FIELD(CTRL, NCO, 16, 16)
 -REG32(STATUS, 0x10)
 +REG32(STATUS, 0x14)
      FIELD(STATUS, TXFULL, 0, 1)
      FIELD(STATUS, RXFULL, 1, 1)
      FIELD(STATUS, TXEMPTY, 2, 1)
      FIELD(STATUS, RXIDLE, 4, 1)
      FIELD(STATUS, RXEMPTY, 5, 1)
 -REG32(RDATA, 0x14)
 -REG32(WDATA, 0x18)
 -REG32(FIFO_CTRL, 0x1c)
 +REG32(RDATA, 0x18)
 +REG32(WDATA, 0x1C)
 +REG32(FIFO_CTRL, 0x20)
      FIELD(FIFO_CTRL, RXRST, 0, 1)
      FIELD(FIFO_CTRL, TXRST, 1, 1)
      FIELD(FIFO_CTRL, RXILVL, 2, 3)
      FIELD(FIFO_CTRL, TXILVL, 5, 2)
 -REG32(FIFO_STATUS, 0x20)
 +REG32(FIFO_STATUS, 0x24)
      FIELD(FIFO_STATUS, TXLVL, 0, 5)
      FIELD(FIFO_STATUS, RXLVL, 16, 5)
 -REG32(OVRD, 0x24)
 -REG32(VAL, 0x28)
 -REG32(TIMEOUT_CTRL, 0x2c)
 +REG32(OVRD, 0x28)
 +REG32(VAL, 0x2C)
 +REG32(TIMEOUT_CTRL, 0x30)
  static void ibex_uart_update_irqs(IbexUartState *s)
  {
-     IbexUartState *s = opaque;
--    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
-+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
-         return 1;
-     }
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
-     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
-     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
-+    /* The RXFULL is set after receiving a single byte
-+     * as the FIFO buffers are not yet implemented.
-+     */
-+    s->uart_status |= R_STATUS_RXFULL_MASK;
-+    s->rx_level += 1;
-     if (size > rx_fifo_level) {
-         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
-     s->uart_timeout_ctrl = 0x00000000;
-     s->tx_level = 0;
-+    s->rx_level = 0;
-     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-     case R_RDATA:
-         retvalue = s->uart_rdata;
--        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
-+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
-             qemu_chr_fe_accept_input(&s->chr);
--            s->uart_status |= R_STATUS_RXIDLE_MASK;
--            s->uart_status |= R_STATUS_RXEMPTY_MASK;
-+            s->rx_level -= 1;
-+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
-+            if (s->rx_level == 0) {
-+                s->uart_status |= R_STATUS_RXIDLE_MASK;
-+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
-+            }
-         }
-         break;
-     case R_WDATA:
-@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
-     case R_FIFO_STATUS:
-         retvalue = s->uart_fifo_status;
--        retvalue |= s->tx_level & 0x1F;
-+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
-+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: RX fifos are not supported\n", __func__);
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
-         s->uart_fifo_ctrl = value;
-         if (value & R_FIFO_CTRL_RXRST_MASK) {
-+            s->rx_level = 0;
-             qemu_log_mask(LOG_UNIMP,
-                           "%s: RX fifos are not supported\n", __func__);
-         }
 --
-.30.1
+.31.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-Like MMU translation, add qemu log of PMP permission checking for
-debugging.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 12 ++++++++++++
-file changed, 12 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             if (ret == TRANSLATE_SUCCESS) {
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                                size, access_type, mode);
-+
-+                qemu_log_mask(CPU_LOG_MMU,
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
-+                              __func__, pa, ret, prot_pmp, tlb_size);
-+
-                 prot &= prot_pmp;
-             }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-         if (ret == TRANSLATE_SUCCESS) {
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                            size, access_type, mode);
-+
-+            qemu_log_mask(CPU_LOG_MMU,
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
-+                          __func__, pa, ret, prot_pmp, tlb_size);
-+
-             prot &= prot_pmp;
-         }
-     }
---
-.30.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-If PMP permission of any address has been changed by updating PMP entry,
-flush all TLB pages to prevent from getting old permission.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/pmp.c | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "cpu.h"
- #include "trace.h"
-+#include "exec/exec-all.h"
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
-     uint8_t val);
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
-         cfg_val = (val >> 8 * i)  & 0xff;
-         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
-     }
-+
-+    /* If PMP permission of any addr has been changed, flush TLB pages. */
-+    tlb_flush(env_cpu(env));
- }
---
-.30.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-According to the specification the "field SPVP of hstatus controls the
-privilege level of the access" for the hypervisor virtual-machine load
-and store instructions HLV, HLVX and HSV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
-file changed, 14 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-         use_background = true;
-     }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
-             mode = get_field(env->mstatus, MSTATUS_MPP);
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
-                   __func__, address, access_type, mmu_idx);
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
--        if (get_field(env->mstatus, MSTATUS_MPRV)) {
--            mode = get_field(env->mstatus, MSTATUS_MPP);
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
-+               get_field(env->mstatus, MSTATUS_MPRV)) {
-+        mode = get_field(env->mstatus, MSTATUS_MPP);
-+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
-+            two_stage_lookup = true;
-         }
-     }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
--        access_type != MMU_INST_FETCH &&
--        get_field(env->mstatus, MSTATUS_MPRV) &&
--        get_field(env->mstatus, MSTATUS_MPV)) {
--        two_stage_lookup = true;
--    }
--
-     if (riscv_cpu_virt_enabled(env) ||
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-          access_type != MMU_INST_FETCH)) {
---
-.30.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+Deleted patch
-From: Asherah Connor <ashe@kivikakk.ee>
-Allow ramfb on virt.  This lets `-device ramfb' work.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/sysemu.h"
- #include "hw/pci/pci.h"
- #include "hw/pci-host/gpex.h"
-+#include "hw/display/ramfb.h"
- static const MemMapEntry virt_memmap[] = {
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
-     mc->numa_mem_supported = true;
-+
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
- }
- static const TypeInfo virt_machine_typeinfo = {
---
-.30.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
 ---
  include/hw/riscv/opentitan.h | 1 +
  hw/riscv/opentitan.c         | 3 +++
 files changed, 4 insertions(+)
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
 further compressed instruction decoding. However, prior to this change,
 we did not raise an illegal instruction exception, if decode_RV32_64C()
 fails to decode the instruction. This means that we skipped illegal
 compressed instructions instead of raising an illegal instruction
 exception.
 Instead of patching decode_RV32_64C(), we can just remove it,
 as it is dead code since f330433b363 anyway.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/translate.c | 179 +--------------------------------------
 file changed, 1 insertion(+), 178 deletions(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/include/hw/riscv/opentitan.h
-+++ b/target/riscv/translate.c
++++ b/include/hw/riscv/opentitan.h
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ enum {
-     CPUState *cs;
+     IBEX_DEV_ALERT_HANDLER,
- } DisasContext;
+     IBEX_DEV_NMI_GEN,
+     IBEX_DEV_OTBN,
--#ifdef TARGET_RISCV64
++    IBEX_DEV_PERI,
--/* convert riscv funct3 to qemu memop for load/store */
+ };
--static const int tcg_memop_lookup[8] = {
--    [0 ... 7] = -1,
+ enum {
--    [0] = MO_SB,
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
--    [1] = MO_TESW,
+index XXXXXXX..XXXXXXX 100644
--    [2] = MO_TESL,
+--- a/hw/riscv/opentitan.c
--    [3] = MO_TEQ,
++++ b/hw/riscv/opentitan.c
--    [4] = MO_UB,
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
--    [5] = MO_TEUW,
+     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
--    [6] = MO_TEUL,
+     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
--};
+     [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
--#endif
++    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
--
+ };
- #ifdef TARGET_RISCV64
- #define CASE_OP_32_64(X) case X: case glue(X, W)
+ static void opentitan_board_init(MachineState *machine)
- #else
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+         memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
-     ctx->base.is_jmp = DISAS_NORETURN;
+     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
          memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
 +    create_unimplemented_device("riscv.lowrisc.ibex.peri",
 +        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
  }
--#ifdef TARGET_RISCV64
+ static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
 -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
 -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
      tcg_temp_free_i32(t0);
  }
 -static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t funct3 = extract16(opcode, 13, 3);
 -    uint8_t rd_rs2 = GET_C_RS2S(opcode);
 -    uint8_t rs1s = GET_C_RS1S(opcode);
 -
 -    switch (funct3) {
 -    case 3:
 -#if defined(TARGET_RISCV64)
 -        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 -        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 -                 GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 -        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 -                    GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    case 7:
 -#if defined(TARGET_RISCV64)
 -        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 -        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 -                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.31.1

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 11/11] hw/riscv: opentitan: Add the flash alias
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+OpenTitan has an alias of flash avaliable which is called virtual flash.
 Add support for that in the QEMU model.
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-short of its purpose, as all it checks is whether two-stage address
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-translation either via the hypervisor-load store instructions or the
+Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
-MPRV feature would be allowed.
+---
  include/hw/riscv/opentitan.h | 2 ++
  hw/riscv/opentitan.c         | 6 ++++++
 files changed, 8 insertions(+)
-What we really need instead is whether two-stage address translation was
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
 active when the exception was raised. However, in riscv_cpu_do_interrupt
 we do not have the information to reliably detect this. Therefore, when
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.h        |  4 ++++
  target/riscv/cpu.c        |  1 +
  target/riscv/cpu_helper.c | 21 ++++++++-------------
 files changed, 13 insertions(+), 13 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/include/hw/riscv/opentitan.h
-+++ b/target/riscv/cpu.h
++++ b/include/hw/riscv/opentitan.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
-     target_ulong satp_hs;
-     uint64_t mstatus_hs;
+     MemoryRegion flash_mem;
+     MemoryRegion rom;
-+    /* Signals whether the current exception occurred with two-stage address
++    MemoryRegion flash_alias;
-+       translation active. */
+ };
-+    bool two_stage_lookup;
-+
+ typedef struct OpenTitanState {
-     target_ulong scounteren;
+@@ -XXX,XX +XXX,XX @@ enum {
-     target_ulong mcounteren;
+     IBEX_DEV_ROM,
+     IBEX_DEV_RAM,
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+     IBEX_DEV_FLASH,
 +    IBEX_DEV_FLASH_VIRTUAL,
      IBEX_DEV_UART,
      IBEX_DEV_GPIO,
      IBEX_DEV_SPI,
 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/hw/riscv/opentitan.c
-+++ b/target/riscv/cpu.c
++++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-     env->mcause = 0;
+     [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
-     env->pc = env->resetvec;
+     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
-+    env->two_stage_lookup = false;
++    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
- #endif
+ };
-     cs->exception_index = EXCP_NONE;
-     env->load_res = -1;
+ static void opentitan_board_init(MachineState *machine)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-index XXXXXXX..XXXXXXX 100644
+     /* Flash memory */
---- a/target/riscv/cpu_helper.c
+     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
-+++ b/target/riscv/cpu_helper.c
+                            memmap[IBEX_DEV_FLASH].size, &error_fatal);
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
++    memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
-         g_assert_not_reached();
++                             "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
-     }
++                             memmap[IBEX_DEV_FLASH_VIRTUAL].size);
-     env->badaddr = address;
+     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
-+    env->two_stage_lookup = two_stage;
+                                 &s->flash_mem);
- }
++    memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
++                                &s->flash_alias);
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+     /* PLIC */
-     }
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
      env->badaddr = addr;
 +    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
 +                            riscv_cpu_two_stage_lookup(mmu_idx);
      riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
  }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
          g_assert_not_reached();
      }
      env->badaddr = addr;
 +    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
 +                            riscv_cpu_two_stage_lookup(mmu_idx);
      riscv_raise_exception(env, cs->exception_index, retaddr);
  }
  #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          /* handle the trap in S-mode */
          if (riscv_has_ext(env, RVH)) {
              target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 -            bool two_stage_lookup = false;
 -            if (env->priv == PRV_M ||
 -                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                    get_field(env->hstatus, HSTATUS_HU))) {
 -                    two_stage_lookup = true;
 -            }
 -
 -            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
 +            if (env->two_stage_lookup && write_tval) {
                  /*
                   * If we are writing a guest virtual address to stval, set
                   * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  riscv_cpu_set_force_hs_excep(env, 0);
              } else {
                  /* Trap into HS mode */
 -                if (!two_stage_lookup) {
 -                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 -                                             riscv_cpu_virt_enabled(env));
 -                }
 +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                  htval = env->guest_phys_fault_addr;
              }
          }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
       * RISC-V ISA Specification.
       */
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.31.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:

Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into staging (2021-07-12 19:15:11 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712

for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:

hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 6.1 release

- Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates

----------------------------------------------------------------
Alistair Francis (3):
      char: ibex_uart: Update the register layout
      hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
      hw/riscv: opentitan: Add the flash alias

Bin Meng (7):
      target/riscv: pmp: Fix some typos
      target/riscv: csr: Remove redundant check in fp csr read/write routines
      docs/system: riscv: Fix CLINT name in the sifive_u doc
      docs/system: riscv: Add documentation for virt machine
      docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
      hw/riscv: sifive_u: Correct the CLINT timebase frequency
      hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Jose Martins (1):
      target/riscv: hardwire bits in hideleg and hedeleg

docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
 docs/system/riscv/sifive_u.rst             |   2 +-
 docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
 docs/system/target-riscv.rst               |   1 +
 include/hw/riscv/opentitan.h               |   3 +
 hw/char/ibex_uart.c                        |  19 ++--
 hw/riscv/opentitan.c                       |   9 ++
 hw/riscv/sifive_u.c                        |  12 ++-
 target/riscv/csr.c                         |  37 +++-----
 target/riscv/pmp.c                         |  10 +--
 10 files changed, 233 insertions(+), 52 deletions(-)
 create mode 100644 docs/system/riscv/virt.rst

From: Bin Meng <bmeng.cn@gmail.com>

%s/CSP/CSR
%s/thie/the

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 }
 
 /*
- * Handle a write to a pmpcfg CSP
+ * Handle a write to a pmpcfg CSR
  */
 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
     target_ulong val)
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 
 
 /*
- * Handle a read from a pmpcfg CSP
+ * Handle a read from a pmpcfg CSR
  */
 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
 {
@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
 
 
 /*
- * Handle a write to a pmpaddr CSP
+ * Handle a write to a pmpaddr CSR
  */
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val)
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
 
 
 /*
- * Handle a read from a pmpaddr CSP
+ * Handle a read from a pmpaddr CSR
  */
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
 {
@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
 
 /*
  * Calculate the TLB size if the start address or the end address of
- * PMP entry is presented in thie TLB page.
+ * PMP entry is presented in the TLB page.
  */
 static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
                                      target_ulong tlb_sa, target_ulong tlb_ea)
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

The following check:

if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
        return -RISCV_EXCP_ILLEGAL_INST;
    }

is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException epmp(CPURISCVState *env, int csrno)
 static RISCVException read_fflags(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = riscv_cpu_get_fflags(env);
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
                                    target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
 static RISCVException read_frm(CPURISCVState *env, int csrno,
                                target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = env->frm;
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
                                 target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
                                 target_ulong *val)
 {
-#if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-#endif
     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
         | (env->frm << FSR_RD_SHIFT);
     if (vs(env, csrno) >= 0) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
                                  target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

This adds detailed documentation for RISC-V `virt` machine,
including the following information:

- Supported devices
  - Hardware configuration information
  - Boot options
  - Running Linux kernel
  - Running U-Boot

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/virt.rst   | 138 +++++++++++++++++++++++++++++++++++
 docs/system/target-riscv.rst |   1 +
 2 files changed, 139 insertions(+)
 create mode 100644 docs/system/riscv/virt.rst

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@
+'virt' Generic Virtual Platform (``virt``)
+==========================================
+
+The `virt` board is a platform which does not correspond to any real hardware;
+it is designed for use in virtual machines. It is the recommended board type
+if you simply want to run a guest such as Linux and do not care about
+reproducing the idiosyncrasies and limitations of a particular bit of
+real-world hardware.
+
+Supported devices
+-----------------
+
+The ``virt`` machine supports the following devices:
+
+* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
+* Core Local Interruptor (CLINT)
+* Platform-Level Interrupt Controller (PLIC)
+* CFI parallel NOR flash memory
+* 1 NS16550 compatible UART
+* 1 Google Goldfish RTC
+* 1 SiFive Test device
+* 8 virtio-mmio transport devices
+* 1 generic PCIe host bridge
+* The fw_cfg device that allows a guest to obtain data from QEMU
+
+Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
+can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
+enables the hypervisor extension for RV64.
+
+Hardware configuration information
+----------------------------------
+
+The ``virt`` machine automatically generates a device tree blob ("dtb")
+which it passes to the guest, if there is no ``-dtb`` option. This provides
+information about the addresses, interrupt lines and other configuration of
+the various devices in the system. Guest software should discover the devices
+that are present in the generated DTB.
+
+If users want to provide their own DTB, they can use the ``-dtb`` option.
+These DTBs should have the following requirements:
+
+* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
+* The /memory reg size should match QEMU’s selected ram_size via ``-m``
+* Should contain a node for the CLINT device with a compatible string
+  "riscv,clint0" if using with OpenSBI BIOS images
+
+Boot options
+------------
+
+The ``virt`` machine can start using the standard -kernel functionality
+for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader
+with the default OpenSBI firmware image as the -bios. It also supports
+the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
+firmware and U-Boot proper (S-mode), using the standard -bios functionality.
+
+Running Linux kernel
+--------------------
+
+Linux mainline v5.12 release is tested at the time of writing. To build a
+Linux mainline kernel that can be booted by the ``virt`` machine in
+64-bit mode, simply configure the kernel using the defconfig configuration:
+
+.. code-block:: bash
+
+  $ export ARCH=riscv
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ make defconfig
+  $ make
+
+To boot the newly built Linux kernel in QEMU with the ``virt`` machine:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
+      -display none -serial stdio \
+      -kernel arch/riscv/boot/Image \
+      -initrd /path/to/rootfs.cpio \
+      -append "root=/dev/ram"
+
+To build a Linux mainline kernel that can be booted by the ``virt`` machine
+in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
+fix the 32-bit boot issue for Linux kernel v5.12.
+
+.. code-block:: bash
+
+  $ export ARCH=riscv
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch
+  $ git am riscv.patch
+  $ make rv32_defconfig
+  $ make
+
+Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command
+line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit
+applications shall be used in order for kernel to boot to user space.
+
+Running U-Boot
+--------------
+
+U-Boot mainline v2021.04 release is tested at the time of writing. To build an
+S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use
+the qemu-riscv64_smode_defconfig with similar commands as described above for Linux:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ make qemu-riscv64_smode_defconfig
+
+Boot the 64-bit U-Boot S-mode image directly:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
+      -display none -serial stdio \
+      -kernel /path/to/u-boot.bin
+
+To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image
+that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together,
+build the U-Boot images using riscv64_spl_defconfig:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
+  $ make qemu-riscv64_spl_defconfig
+
+The minimal QEMU commands to run U-Boot SPL are:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt -smp 4 -m 2G \
+      -display none -serial stdio \
+      -bios /path/to/u-boot-spl \
+      -device loader,file=/path/to/u-boot.itb,addr=0x80200000
+
+To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
+riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
+``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    riscv/microchip-icicle-kit
    riscv/shakti-c
    riscv/sifive_u
+   riscv/virt
 
 RISC-V CPU firmware
 -------------------
-- 
2.31.1

From: Jose Martins <josemartins90@gmail.com>

The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
 - Improve indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
 
 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                            VS_MODE_INTERRUPTS;
+static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
                                      VS_MODE_INTERRUPTS;
 static const target_ulong delegable_excps =
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
+static const target_ulong vs_delegable_excps = delegable_excps &
+    ~((1ULL << (RISCV_EXCP_S_ECALL)) |
+      (1ULL << (RISCV_EXCP_VS_ECALL)) |
+      (1ULL << (RISCV_EXCP_M_ECALL)) |
+      (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
+      (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+      (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
+      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
-    env->hedeleg = val;
+    env->hedeleg = val & vs_delegable_excps;
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno,
 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
-    env->hideleg = val;
+    env->hideleg = val & vs_delegable_ints;
     return RISCV_EXCP_NONE;
 }
 
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.

It also updates the truth table to have a new '-dtb' column which is
required by direct kernel boot.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++---
 1 file changed, 47 insertions(+), 7 deletions(-)

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/microchip-icicle-kit.rst
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@ The user provided DTB should have the following requirements:
 
 QEMU follows below truth table to select which payload to execute:
 
-=====  ========== =======
--bios     -kernel payload
-=====  ========== =======
-    N           N     HSS
-    Y  don't care     HSS
-    N           Y  kernel
-=====  ========== =======
+===== ========== ========== =======
+-bios    -kernel       -dtb payload
+===== ========== ========== =======
+    N          N don't care     HSS
+    Y don't care don't care     HSS
+    N          Y          Y  kernel
+===== ========== ========== =======
 
 The memory is set to 1537 MiB by default which is the minimum required high
 memory size by HSS. A sanity check on ram size is performed in the machine
@@ -XXX,XX +XXX,XX @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the
 second serial port. U-Boot will automatically load the Linux kernel from
 the SD card image.
 
+Direct Kernel Boot
+------------------
+
+Sometimes we just want to test booting a new kernel, and transforming the
+kernel image to the format required by the HSS bootflow is tedious. We can
+use '-kernel' for direct kernel booting just like other RISC-V machines do.
+
+In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
+used to boot an S-mode payload like U-Boot or OS kernel directly.
+
+For example, the following commands show building a U-Boot image from U-Boot
+mainline v2021.07 for the Microchip Icicle Kit board:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ make microchip_mpfs_icicle_defconfig
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \
+      -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -kernel path/to/u-boot/build/dir/u-boot.bin \
+      -dtb path/to/u-boot/build/dir/u-boot.dtb
+
+CAVEATS:
+
+* Check the "stdout-path" property in the /chosen node in the DTB to determine
+  which serial port is used for the serial console, e.g.: if the console is set
+  to the second serial port, change to use "-serial null -serial stdio".
+* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image
+  ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence
+  ``u-boot.bin`` has to be used which does contain one. To use the ELF image,
+  we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
+
 .. _HSS: https://github.com/polarfire-soc/hart-software-services
-- 
2.31.1

From: Bin Meng <bin.meng@windriver.com>

At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 
 #include <libfdt.h>
 
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
 static const MemMapEntry sifive_u_memmap[] = {
     [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
     [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
-        SIFIVE_CLINT_TIMEBASE_FREQ);
+        CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
         memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+        CLINT_TIMEBASE_FREQ, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
         return;
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Currently the firmware dynamic info (fw_dyn) is put right after
the reset vector, which is not 8-byte aligned on RV64. OpenSBI
fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
which expects fw_dyn to be on the 8-byte boundary, otherwise the
misaligned load exception may happen. Fortunately this does not
cause any issue on QEMU, as QEMU does support misaligned load.

RV32 does not have any issue as it is 4-byte aligned already.
Change to make sure it is 8-byte aligned which works for both
RV32 and RV64.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     }
 
     /* reset vector */
-    uint32_t reset_vec[11] = {
+    uint32_t reset_vec[12] = {
         s->msel,                       /* MSEL pin state */
         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-        0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
+        0x02c28613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
         0xf1402573,                    /*     csrr   a0, mhartid  */
         0,
         0,
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         start_addr,                    /* start: .dword */
         start_addr_hi32,
         fdt_load_addr,                 /* fdt_laddr: .dword */
+        0x00000000,
         0x00000000,
                                        /* fw_dyn: */
     };
-- 
2.31.1

Update the register layout to match the latest OpenTitan bitstream.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
---
 hw/char/ibex_uart.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ REG32(INTR_STATE, 0x00)
     FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
 REG32(INTR_ENABLE, 0x04)
 REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
+REG32(ALERT_TEST, 0x0C)
+REG32(CTRL, 0x10)
     FIELD(CTRL, TX_ENABLE, 0, 1)
     FIELD(CTRL, RX_ENABLE, 1, 1)
     FIELD(CTRL, NF, 2, 1)
@@ -XXX,XX +XXX,XX @@ REG32(CTRL, 0x0C)
     FIELD(CTRL, PARITY_ODD, 7, 1)
     FIELD(CTRL, RXBLVL, 8, 2)
     FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
+REG32(STATUS, 0x14)
     FIELD(STATUS, TXFULL, 0, 1)
     FIELD(STATUS, RXFULL, 1, 1)
     FIELD(STATUS, TXEMPTY, 2, 1)
     FIELD(STATUS, RXIDLE, 4, 1)
     FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
+REG32(RDATA, 0x18)
+REG32(WDATA, 0x1C)
+REG32(FIFO_CTRL, 0x20)
     FIELD(FIFO_CTRL, RXRST, 0, 1)
     FIELD(FIFO_CTRL, TXRST, 1, 1)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
+REG32(FIFO_STATUS, 0x24)
     FIELD(FIFO_STATUS, TXLVL, 0, 5)
     FIELD(FIFO_STATUS, RXLVL, 16, 5)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
+REG32(OVRD, 0x28)
+REG32(VAL, 0x2C)
+REG32(TIMEOUT_CTRL, 0x30)
 
 static void ibex_uart_update_irqs(IbexUartState *s)
 {
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h | 1 +
 hw/riscv/opentitan.c         | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_DEV_ALERT_HANDLER,
     IBEX_DEV_NMI_GEN,
     IBEX_DEV_OTBN,
+    IBEX_DEV_PERI,
 };
 
 enum {
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
     [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
+    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
 };
 
 static void opentitan_board_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.peri",
+        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
 }
 
 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
-- 
2.31.1

OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h | 2 ++
 hw/riscv/opentitan.c         | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
 
     MemoryRegion flash_mem;
     MemoryRegion rom;
+    MemoryRegion flash_alias;
 };
 
 typedef struct OpenTitanState {
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_DEV_ROM,
     IBEX_DEV_RAM,
     IBEX_DEV_FLASH,
+    IBEX_DEV_FLASH_VIRTUAL,
     IBEX_DEV_UART,
     IBEX_DEV_GPIO,
     IBEX_DEV_SPI,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
     [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
+    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
 };
 
 static void opentitan_board_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     /* Flash memory */
     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
                            memmap[IBEX_DEV_FLASH].size, &error_fatal);
+    memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
+                             "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
+                             memmap[IBEX_DEV_FLASH_VIRTUAL].size);
     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
                                 &s->flash_mem);
+    memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
+                                &s->flash_alias);
 
     /* PLIC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
-- 
2.31.1