Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL 0/7] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+  Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24 09:31:26 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24 05:00:13 -0700)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+Third RISC-V PR for 6.1 release
-This PR includes:
+ - Fix MISA in the DisasContext
- - Fix for vector CSR access
+ - Fix GDB CSR XML generation
- - Improvements to the Ibex UART device
+ - QOMify the SiFive UART
- - PMP improvements and bug fixes
+ - Add support for the OpenTitan timer
  - Hypervisor extension bug fixes
  - ramfb support for the virt machine
  - Fast read support for SST flash
  - Improvements to the microchip_pfsoc machine
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Alistair Francis (4):
-      hw/char: disable ibex uart receive if the buffer is full
+      target/riscv: Use target_ulong for the DisasContext misa
       hw/char/ibex_uart: Make the register layout private
       hw/timer: Initial commit of Ibex Timer
       hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
-Asherah Connor (2):
+Bin Meng (1):
-      hw/riscv: Add fw_cfg support to virt
+      target/riscv: gdbstub: Fix dynamic CSR XML generation
       hw/riscv: allow ramfb on virt
-Bin Meng (3):
+Lukas Jünger (2):
-      hw/block: m25p80: Support fast read for SST flashes
+      hw/char: Consistent function names for sifive_uart
-      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+      hw/char: QOMify sifive_uart
       docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
-Frank Chang (1):
+ include/hw/char/ibex_uart.h   |  37 -----
-      target/riscv: fix vs() to return proper error code
+ include/hw/char/sifive_uart.h |  11 +-
  include/hw/riscv/opentitan.h  |   5 +-
  include/hw/timer/ibex_timer.h |  52 +++++++
  hw/char/ibex_uart.c           |  37 +++++
  hw/char/sifive_uart.c         | 152 +++++++++++++++++----
  hw/riscv/opentitan.c          |  14 +-
  hw/timer/ibex_timer.c         | 305 ++++++++++++++++++++++++++++++++++++++++++
  target/riscv/gdbstub.c        |   2 +-
  target/riscv/translate.c      |   2 +-
  MAINTAINERS                   |   6 +-
  hw/timer/meson.build          |   1 +
 files changed, 543 insertions(+), 81 deletions(-)
  create mode 100644 include/hw/timer/ibex_timer.h
  create mode 100644 hw/timer/ibex_timer.c
-Georg Kotheimer (6):
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
-      target/riscv: Make VSTIP and VSEIP read-only in hip
-      target/riscv: Use background registers also for MSTATUS_MPV
-      target/riscv: Fix read and write accesses to vsip and vsie
-      target/riscv: Add proper two-stage lookup exception detection
-      target/riscv: Prevent lost illegal instruction exceptions
-Jim Shu (3):
-      target/riscv: propagate PMP permission to TLB page
-      target/riscv: add log of PMP permission checking
-      target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
- docs/system/target-riscv.rst               |   1 +
- include/hw/char/ibex_uart.h                |   4 +
- include/hw/riscv/microchip_pfsoc.h         |   1 +
- include/hw/riscv/virt.h                    |   2 +
- target/riscv/cpu.h                         |   4 +
- target/riscv/pmp.h                         |   4 +-
- hw/block/m25p80.c                          |   3 +
- hw/char/ibex_uart.c                        |  23 +++-
- hw/riscv/microchip_pfsoc.c                 |   6 +
- hw/riscv/virt.c                            |  33 ++++++
- target/riscv/cpu.c                         |   1 +
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
- target/riscv/csr.c                         |  77 +++++++------
- target/riscv/pmp.c                         |  84 ++++++++++----
- target/riscv/translate.c                   | 179 +----------------------------
- hw/riscv/Kconfig                           |   1 +
-files changed, 367 insertions(+), 289 deletions(-)
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+Deleted patch
-From: Frank Chang <frank.chang@sifive.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
-is not enabled.
-If -1 is returned, exception will be raised and cs->exception_index will
-be set to the negative return value. The exception will then be treated
-as an instruction access fault instead of illegal instruction fault.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
-     if (env->misa & RVV) {
-         return 0;
-     }
--    return -1;
-+    return -RISCV_EXCP_ILLEGAL_INST;
- }
- static int ctr(CPURISCVState *env, int csrno)
---
-.30.1

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+The is_32bit() check in translate.c expects a 64-bit guest to have a
 -bit misa value otherwise the macro check won't work. This patches
 fixes that and fixes a Coverity issue at the same time.
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+Fixes: CID 1453107
 further compressed instruction decoding. However, prior to this change,
 we did not raise an illegal instruction exception, if decode_RV32_64C()
 fails to decode the instruction. This means that we skipped illegal
 compressed instructions instead of raising an illegal instruction
 exception.
 Instead of patching decode_RV32_64C(), we can just remove it,
 as it is dead code since f330433b363 anyway.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ target/riscv/translate.c | 2 +-
-file changed, 1 insertion(+), 178 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     CPUState *cs;
+     bool virt_enabled;
- } DisasContext;
+     uint32_t opcode;
+     uint32_t mstatus_fs;
--#ifdef TARGET_RISCV64
+-    uint32_t misa;
--/* convert riscv funct3 to qemu memop for load/store */
++    target_ulong misa;
--static const int tcg_memop_lookup[8] = {
+     uint32_t mem_idx;
--    [0 ... 7] = -1,
+     /* Remember the rounding mode encoded in the previous fp instruction,
--    [0] = MO_SB,
+        which we have already installed into env->fp_status.  Or -1 for
 -    [1] = MO_TESW,
 -    [2] = MO_TESL,
 -    [3] = MO_TEQ,
 -    [4] = MO_UB,
 -    [5] = MO_TEUW,
 -    [6] = MO_TEUL,
 -};
 -#endif
 -
  #ifdef TARGET_RISCV64
  #define CASE_OP_32_64(X) case X: case glue(X, W)
  #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
      ctx->base.is_jmp = DISAS_NORETURN;
  }
 -#ifdef TARGET_RISCV64
 -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -}
 -
 -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
 -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
      tcg_temp_free_i32(t0);
  }
 -static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t funct3 = extract16(opcode, 13, 3);
 -    uint8_t rd_rs2 = GET_C_RS2S(opcode);
 -    uint8_t rs1s = GET_C_RS1S(opcode);
 -
 -    switch (funct3) {
 -    case 3:
 -#if defined(TARGET_RISCV64)
 -        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 -        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 -                 GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 -        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 -                    GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    case 7:
 -#if defined(TARGET_RISCV64)
 -        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 -        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 -                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.31.1

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation
 From: Bin Meng <bin.meng@windriver.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
-been updated to use a register mapped at 0x4f000000 instead of a
+the CSR predicate() function was changed to return RISCV_EXCP_NONE
-GPIO to control whether eMMC or SD card is to be used. With this
+instead of 0 for a valid CSR, but it forgot to update the dynamic
-support the same HSS image can be used for both eMMC and SD card
+CSR XML generation codes in gdbstub.
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
+Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
+Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 1 +
+ target/riscv/gdbstub.c | 2 +-
- hw/riscv/microchip_pfsoc.c         | 6 ++++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 7 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/gdbstub.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
-     MICROCHIP_PFSOC_ENVM_DATA,
-     MICROCHIP_PFSOC_QSPI_XIP,
+     for (i = 0; i < CSR_TABLE_SIZE; i++) {
-     MICROCHIP_PFSOC_IOSCB,
+         predicate = csr_ops[i].predicate;
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
+-        if (predicate && !predicate(env, i)) {
-     MICROCHIP_PFSOC_DRAM_LO,
++        if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+             if (csr_ops[i].name) {
-     MICROCHIP_PFSOC_DRAM_HI,
+                 g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+             } else {
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
      [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
 +    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
      [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
      [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                      memmap[MICROCHIP_PFSOC_IOSCB].base);
 +    /* eMMC/SD mux */
 +    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
 +        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
 +
      /* QSPI Flash */
      memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                             "microchip.pfsoc.qspi_xip",
 --
-.30.1
+.31.1

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL 3/7] hw/char: Consistent function names for sifive_uart
-From: Jim Shu <cwshu@andestech.com>
+From: Lukas Jünger <lukas.juenger@greensocs.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+This cleans up function names in the SiFive UART model.
 Fix it by propagating PMP permission to TLB page permission.
-PMP permission checking also use MMU-style API to change TLB permission
+Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
 and size.
 Signed-off-by: Jim Shu <cwshu@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ hw/char/sifive_uart.c | 46 ++++++++++++++++++++++---------------------
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+file changed, 24 insertions(+), 22 deletions(-)
  target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 files changed, 125 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
+diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.h
+--- a/hw/char/sifive_uart.c
-+++ b/target/riscv/pmp.h
++++ b/hw/char/sifive_uart.c
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@
-     target_ulong val);
+  */
- target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
- bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+ /* Returns the state of the IP (interrupt pending) register */
--    target_ulong size, pmp_priv_t priv, target_ulong mode);
+-static uint64_t uart_ip(SiFiveUARTState *s)
-+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
++static uint64_t sifive_uart_ip(SiFiveUARTState *s)
-+    target_ulong mode);
+ {
- bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+     uint64_t ret = 0;
-                          target_ulong *tlb_size);
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+@@ -XXX,XX +XXX,XX @@ static uint64_t uart_ip(SiFiveUARTState *s)
- void pmp_update_rule_nums(CPURISCVState *env);
+     return ret;
  uint32_t pmp_get_num_rules(CPURISCVState *env);
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
  #endif
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
      env->load_res = -1;
  }
-+/*
+-static void update_irq(SiFiveUARTState *s)
-+ * get_physical_address_pmp - check PMP permission for this physical address
++static void sifive_uart_update_irq(SiFiveUARTState *s)
-+ *
+ {
-+ * Match the PMP region and check permission for this physical address and it's
+     int cond = 0;
-+ * TLB page. Returns 0 if the permission checking was successful
+     if ((s->ie & SIFIVE_UART_IE_TXWM) ||
-+ *
+@@ -XXX,XX +XXX,XX @@ static void update_irq(SiFiveUARTState *s)
-+ * @env: CPURISCVState
+ }
-+ * @prot: The returned protection attributes
-+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ static uint64_t
-+ *            permission checking. NULL if not set TLB page for addr.
+-uart_read(void *opaque, hwaddr addr, unsigned int size)
-+ * @addr: The physical address to be checked permission
++sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
-+ * @access_type: The type of MMU access
+ {
-+ * @mode: Indicates current privilege level.
+     SiFiveUARTState *s = opaque;
-+ */
+     unsigned char r;
-+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
-+                                    target_ulong *tlb_size, hwaddr addr,
+             memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
-+                                    int size, MMUAccessType access_type,
+             s->rx_fifo_len--;
-+                                    int mode)
+             qemu_chr_fe_accept_input(&s->chr);
-+{
+-            update_irq(s);
-+    pmp_priv_t pmp_priv;
++            sifive_uart_update_irq(s);
-+    target_ulong tlb_size_pmp = 0;
+             return r;
 +
 +    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
 +        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +        return TRANSLATE_SUCCESS;
 +    }
 +
 +    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 +                            mode)) {
 +        *prot = 0;
 +        return TRANSLATE_PMP_FAIL;
 +    }
 +
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
 +    }
 +
 +    return TRANSLATE_SUCCESS;
 +}
 +
  /* get_physical_address - get the physical address for this virtual address
   *
   * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
              pte_addr = base + idx * ptesize;
          }
+         return 0x80000000;
--        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
--            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+     case SIFIVE_UART_IE:
--            1 << MMU_DATA_LOAD, PRV_S)) {
+         return s->ie;
-+        int pmp_prot;
+     case SIFIVE_UART_IP:
-+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+-        return uart_ip(s);
-+                                               sizeof(target_ulong),
++        return sifive_uart_ip(s);
-+                                               MMU_DATA_LOAD, PRV_S);
+     case SIFIVE_UART_TXCTRL:
-+        if (pmp_ret != TRANSLATE_SUCCESS) {
+         return s->txctrl;
-             return TRANSLATE_PMP_FAIL;
+     case SIFIVE_UART_RXCTRL:
-         }
+@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
+ }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- #ifndef CONFIG_USER_ONLY
+ static void
-     vaddr im_address;
+-uart_write(void *opaque, hwaddr addr,
-     hwaddr pa = 0;
+-           uint64_t val64, unsigned int size)
--    int prot, prot2;
++sifive_uart_write(void *opaque, hwaddr addr,
-+    int prot, prot2, prot_pmp;
++                  uint64_t val64, unsigned int size)
-     bool pmp_violation = false;
+ {
-     bool first_stage_error = true;
+     SiFiveUARTState *s = opaque;
-     bool two_stage_lookup = false;
+     uint32_t value = val64;
-     int ret = TRANSLATE_FAIL;
+@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
-     int mode = mmu_idx;
+     switch (addr) {
--    target_ulong tlb_size = 0;
+     case SIFIVE_UART_TXFIFO:
-+    /* default TLB page size */
+         qemu_chr_fe_write(&s->chr, &ch, 1);
-+    target_ulong tlb_size = TARGET_PAGE_SIZE;
+-        update_irq(s);
++        sifive_uart_update_irq(s);
-     env->guest_phys_fault_addr = 0;
+         return;
+     case SIFIVE_UART_IE:
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+         s->ie = val64;
+-        update_irq(s);
-             prot &= prot2;
++        sifive_uart_update_irq(s);
+         return;
--            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+     case SIFIVE_UART_TXCTRL:
--                (ret == TRANSLATE_SUCCESS) &&
+         s->txctrl = val64;
--                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
+@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
--                ret = TRANSLATE_PMP_FAIL;
+                   __func__, (int)addr, (int)value);
-+            if (ret == TRANSLATE_SUCCESS) {
+ }
-+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-+                                               size, access_type, mode);
+-static const MemoryRegionOps uart_ops = {
-+                prot &= prot_pmp;
+-    .read = uart_read,
-             }
+-    .write = uart_write,
++static const MemoryRegionOps sifive_uart_ops = {
-             if (ret != TRANSLATE_SUCCESS) {
++    .read = sifive_uart_read,
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++    .write = sifive_uart_write,
-                       "%s address=%" VADDR_PRIx " ret %d physical "
+     .endianness = DEVICE_NATIVE_ENDIAN,
-                       TARGET_FMT_plx " prot %d\n",
+     .valid = {
-                       __func__, address, ret, pa, prot);
+         .min_access_size = 4,
--    }
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
 -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -        (ret == TRANSLATE_SUCCESS) &&
 -        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -        ret = TRANSLATE_PMP_FAIL;
 +        if (ret == TRANSLATE_SUCCESS) {
 +            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                           size, access_type, mode);
 +            prot &= prot_pmp;
 +        }
      }
-+
+ };
-     if (ret == TRANSLATE_PMP_FAIL) {
-         pmp_violation = true;
+-static void uart_rx(void *opaque, const uint8_t *buf, int size)
 +static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)
  {
      SiFiveUARTState *s = opaque;
@@ -XXX,XX +XXX,XX @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
      }
+     s->rx_fifo[s->rx_fifo_len++] = *buf;
-     if (ret == TRANSLATE_SUCCESS) {
--        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
+-    update_irq(s);
--            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
++    sifive_uart_update_irq(s);
 -                         prot, mmu_idx, tlb_size);
 -        } else {
 -            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 -                         prot, mmu_idx, TARGET_PAGE_SIZE);
 -        }
 +        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 +                     prot, mmu_idx, tlb_size);
          return true;
      } else if (probe) {
          return false;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
      return result;
  }
-+/*
+-static int uart_can_rx(void *opaque)
-+ * Check if the address has required RWX privs when no PMP entry is matched.
++static int sifive_uart_can_rx(void *opaque)
 + */
 +static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
 +{
 +    bool ret;
 +
 +    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
 +        /*
 +         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
 +         * or no PMP entry matches an M-Mode access, the access succeeds.
 +         */
 +        ret = true;
 +        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +    } else {
 +        /*
 +         * Other modes are not allowed to succeed if they don't * match a rule,
 +         * but there are rules. We've checked for no rule earlier in this
 +         * function.
 +         */
 +        ret = false;
 +        *allowed_privs = 0;
 +    }
 +
 +    return ret;
 +}
 +
  /*
   * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
   * Check if the address has required RWX privs to complete desired operation
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
-     int i = 0;
+     SiFiveUARTState *s = opaque;
-     int ret = -1;
-     int pmp_size = 0;
+     return s->rx_fifo_len < sizeof(s->rx_fifo);
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
      /* No rule matched */
      if (ret == -1) {
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
--
+-static void uart_event(void *opaque, QEMUChrEvent event)
- /*
++static void sifive_uart_event(void *opaque, QEMUChrEvent event)
-  * Handle a write to a pmpcfg CSP
+ {
   */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
      return false;
  }
-+
-+/*
+-static int uart_be_change(void *opaque)
-+ * Convert PMP privilege to TLB page privilege.
++static int sifive_uart_be_change(void *opaque)
-+ */
+ {
-+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+     SiFiveUARTState *s = opaque;
-+{
-+    int prot = 0;
+-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-+
+-        uart_be_change, s, NULL, true);
-+    if (pmp_priv & PMP_READ) {
++    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
-+        prot |= PAGE_READ;
++                             sifive_uart_event, sifive_uart_be_change, s,
-+    }
++                             NULL, true);
-+    if (pmp_priv & PMP_WRITE) {
-+        prot |= PAGE_WRITE;
+     return 0;
-+    }
+ }
-+    if (pmp_priv & PMP_EXEC) {
+@@ -XXX,XX +XXX,XX @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
-+        prot |= PAGE_EXEC;
+     SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-+    }
+     s->irq = irq;
-+
+     qemu_chr_fe_init(&s->chr, chr, &error_abort);
-+    return prot;
+-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-+}
+-        uart_be_change, s, NULL, true);
 -    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
 +    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
 +                             sifive_uart_event, sifive_uart_be_change, s,
 +                             NULL, true);
 +    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
                            TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
      memory_region_add_subregion(address_space, base, &s->mmio);
      return s;
 --
-.30.1
+.31.1

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL 4/7] hw/char: QOMify sifive_uart
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Lukas Jünger <lukas.juenger@greensocs.com>
-The previous implementation was broken in many ways:
+This QOMifies the SiFive UART model. Migration and reset have been
- - Used mideleg instead of hideleg to mask accesses
+implemented.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-id: 20210616092326.59639-3-lukas.juenger@greensocs.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ include/hw/char/sifive_uart.h |  11 ++--
-file changed, 34 insertions(+), 34 deletions(-)
+ hw/char/sifive_uart.c         | 114 +++++++++++++++++++++++++++++++---
 files changed, 109 insertions(+), 16 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/include/hw/char/sifive_uart.h
-+++ b/target/riscv/csr.c
++++ b/include/hw/char/sifive_uart.h
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@
-     return write_mstatus(env, CSR_MSTATUS, newval);
+ #define HW_SIFIVE_UART_H
  #include "chardev/char-fe.h"
 +#include "hw/qdev-properties.h"
  #include "hw/sysbus.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ enum {
  #define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
  #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
 +#define SIFIVE_UART_RX_FIFO_SIZE 8
  #define TYPE_SIFIVE_UART "riscv.sifive.uart"
 -
 -typedef struct SiFiveUARTState SiFiveUARTState;
 -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
 -                         TYPE_SIFIVE_UART)
 +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
  struct SiFiveUARTState {
      /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct SiFiveUARTState {
      qemu_irq irq;
      MemoryRegion mmio;
      CharBackend chr;
 -    uint8_t rx_fifo[8];
 -    unsigned int rx_fifo_len;
 +    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
 +    uint8_t rx_fifo_len;
      uint32_t ie;
      uint32_t ip;
      uint32_t txctrl;
 diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/sifive_uart.c
 +++ b/hw/char/sifive_uart.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
  #include "qemu/log.h"
 +#include "migration/vmstate.h"
  #include "chardev/char.h"
  #include "chardev/char-fe.h"
  #include "hw/irq.h"
  #include "hw/char/sifive_uart.h"
 +#include "hw/qdev-properties-system.h"
  /*
   * Not yet implemented:
@@ -XXX,XX +XXX,XX @@ static int sifive_uart_be_change(void *opaque)
      return 0;
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static Property sifive_uart_properties[] = {
 +    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void sifive_uart_init(Object *obj)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    SiFiveUARTState *s = SIFIVE_UART(obj);
-+    return 0;
++
 +    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
 +                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
 +    sysbus_init_mmio(sbd, &s->mmio);
 +    sysbus_init_irq(sbd, &s->irq);
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
++static void sifive_uart_realize(DeviceState *dev, Error **errp)
  {
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Tell the guest the VS bits, shifted to the S bit locations */
 -        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
 +        read_vsie(env, CSR_VSIE, val);
      } else {
          *val = env->mie & env->mideleg;
      }
      return 0;
  }
 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    target_ulong newval;
 +    /* Shift the S bits to their VS bit location in mie */
 +    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 +                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 +    return write_mie(env, CSR_MIE, newval);
 +}
 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +{
-     if (riscv_cpu_virt_enabled(env)) {
++    SiFiveUARTState *s = SIFIVE_UART(dev);
--        /* Shift the guests S bits to VS */
++
--        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
++    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
--                 ((val << 1) & VS_MODE_INTERRUPTS);
++                             sifive_uart_event, sifive_uart_be_change, s,
-+        write_vsie(env, CSR_VSIE, val);
++                             NULL, true);
-     } else {
++
 -        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 +        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 +                              (val & S_MODE_INTERRUPTS);
 +        write_mie(env, CSR_MIE, newval);
      }
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
  static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +                    target_ulong new_value, target_ulong write_mask)
 +{
 +    /* Shift the S bits to their VS bit location in mip */
 +    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
- static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
++static void sifive_uart_reset_enter(Object *obj, ResetType type)
-                    target_ulong new_value, target_ulong write_mask)
++{
 +    SiFiveUARTState *s = SIFIVE_UART(obj);
 +    s->ie = 0;
 +    s->ip = 0;
 +    s->txctrl = 0;
 +    s->rxctrl = 0;
 +    s->div = 0;
 +    s->rx_fifo_len = 0;
 +}
 +
 +static void sifive_uart_reset_hold(Object *obj)
 +{
 +    SiFiveUARTState *s = SIFIVE_UART(obj);
 +    qemu_irq_lower(s->irq);
 +}
 +
 +static const VMStateDescription vmstate_sifive_uart = {
 +    .name = TYPE_SIFIVE_UART,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
 +                            SIFIVE_UART_RX_FIFO_SIZE),
 +        VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
 +        VMSTATE_UINT32(ie, SiFiveUARTState),
 +        VMSTATE_UINT32(ip, SiFiveUARTState),
 +        VMSTATE_UINT32(txctrl, SiFiveUARTState),
 +        VMSTATE_UINT32(rxctrl, SiFiveUARTState),
 +        VMSTATE_UINT32(div, SiFiveUARTState),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +
 +static void sifive_uart_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +    ResettableClass *rc = RESETTABLE_CLASS(oc);
 +
 +    dc->realize = sifive_uart_realize;
 +    dc->vmsd = &vmstate_sifive_uart;
 +    rc->phases.enter = sifive_uart_reset_enter;
 +    rc->phases.hold  = sifive_uart_reset_hold;
 +    device_class_set_props(dc, sifive_uart_properties);
 +}
 +
 +static const TypeInfo sifive_uart_info = {
 +    .name          = TYPE_SIFIVE_UART,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(SiFiveUARTState),
 +    .instance_init = sifive_uart_init,
 +    .class_init    = sifive_uart_class_init,
 +};
 +
 +static void sifive_uart_register_types(void)
 +{
 +    type_register_static(&sifive_uart_info);
 +}
 +
 +type_init(sifive_uart_register_types)
 +
  /*
   * Create UART device.
   */
  SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
      Chardev *chr, qemu_irq irq)
  {
-     int ret;
+-    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
+-    s->irq = irq;
-     if (riscv_cpu_virt_enabled(env)) {
+-    qemu_chr_fe_init(&s->chr, chr, &error_abort);
--        /* Shift the new values to line up with the VS bits */
+-    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
--        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
+-                             sifive_uart_event, sifive_uart_be_change, s,
--                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
+-                             NULL, true);
--        ret &= vsip_writable_mask;
+-    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
--        ret >>= 1;
+-                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
+-    memory_region_add_subregion(address_space, base, &s->mmio);
-     } else {
+-    return s;
-         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
++    DeviceState *dev;
-                       write_mask & env->mideleg & sip_writable_mask);
++    SysBusDevice *s;
-@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
++    SiFiveUARTState *r;
-     return 0;
++
 +    dev = qdev_new("riscv.sifive.uart");
 +    s = SYS_BUS_DEVICE(dev);
 +    qdev_prop_set_chr(dev, "chardev", chr);
 +    sysbus_realize_and_unref(s, &error_fatal);
 +    memory_region_add_subregion(address_space, base,
 +                                sysbus_mmio_get_region(s, 0));
 +    sysbus_connect_irq(s, 0, irq);
 +
 +    r = SIFIVE_UART(dev);
 +    return r;
  }
--static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
--                    target_ulong new_value, target_ulong write_mask)
--{
--    int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & env->mideleg & vsip_writable_mask);
--    return ret;
--}
--
--static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
--{
--    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
--    return 0;
--}
--
--static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
--{
--    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
--    return write_mie(env, CSR_MIE, newval);
--}
--
- static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
- {
-     *val = env->vstvec;
 --
-.30.1
+.31.1

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL 5/7] hw/char/ibex_uart: Make the register layout private
-From: Alexander Wagner <alexander.wagner@ulal.de>
+We don't need to expose the register layout in the public header, so
 don't.
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
-the newest received byte. The rx_level variable is added to allow the use of
-the existing OpenTitan driver libraries.
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: c437f570b2b30ab4170387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ include/hw/char/ibex_uart.h | 37 -------------------------------------
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+ hw/char/ibex_uart.c         | 37 +++++++++++++++++++++++++++++++++++++
-files changed, 22 insertions(+), 5 deletions(-)
+files changed, 37 insertions(+), 37 deletions(-)
 diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/char/ibex_uart.h
 +++ b/include/hw/char/ibex_uart.h
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
+@@ -XXX,XX +XXX,XX @@
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
+ #include "qemu/timer.h"
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
+ #include "qom/object.h"
- REG32(FIFO_STATUS, 0x20)
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+-REG32(INTR_STATE, 0x00)
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
+-    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
- REG32(OVRD, 0x24)
+-    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
- REG32(VAL, 0x28)
+-    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
- REG32(TIMEOUT_CTRL, 0x2c)
+-    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
+-REG32(INTR_ENABLE, 0x04)
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
+-REG32(INTR_TEST, 0x08)
-     uint32_t tx_level;
+-REG32(CTRL, 0x0C)
+-    FIELD(CTRL, TX_ENABLE, 0, 1)
-+    uint32_t rx_level;
+-    FIELD(CTRL, RX_ENABLE, 1, 1)
-+
+-    FIELD(CTRL, NF, 2, 1)
-     QEMUTimer *fifo_trigger_handle;
+-    FIELD(CTRL, SLPBK, 4, 1)
-     uint64_t char_tx_time;
+-    FIELD(CTRL, LLPBK, 5, 1)
 -    FIELD(CTRL, PARITY_EN, 6, 1)
 -    FIELD(CTRL, PARITY_ODD, 7, 1)
 -    FIELD(CTRL, RXBLVL, 8, 2)
 -    FIELD(CTRL, NCO, 16, 16)
 -REG32(STATUS, 0x10)
 -    FIELD(STATUS, TXFULL, 0, 1)
 -    FIELD(STATUS, RXFULL, 1, 1)
 -    FIELD(STATUS, TXEMPTY, 2, 1)
 -    FIELD(STATUS, RXIDLE, 4, 1)
 -    FIELD(STATUS, RXEMPTY, 5, 1)
 -REG32(RDATA, 0x14)
 -REG32(WDATA, 0x18)
 -REG32(FIFO_CTRL, 0x1c)
 -    FIELD(FIFO_CTRL, RXRST, 0, 1)
 -    FIELD(FIFO_CTRL, TXRST, 1, 1)
 -    FIELD(FIFO_CTRL, RXILVL, 2, 3)
 -    FIELD(FIFO_CTRL, TXILVL, 5, 2)
 -REG32(FIFO_STATUS, 0x20)
 -    FIELD(FIFO_STATUS, TXLVL, 0, 5)
 -    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 -REG32(OVRD, 0x24)
 -REG32(VAL, 0x28)
 -REG32(TIMEOUT_CTRL, 0x2c)
 -
  #define IBEX_UART_TX_FIFO_SIZE 16
  #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/ibex_uart.c
 +++ b/hw/char/ibex_uart.c
-@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
+@@ -XXX,XX +XXX,XX @@
  #include "qemu/log.h"
  #include "qemu/module.h"
 +REG32(INTR_STATE, 0x00)
 +    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
 +    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
 +    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
 +    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
 +REG32(INTR_ENABLE, 0x04)
 +REG32(INTR_TEST, 0x08)
 +REG32(CTRL, 0x0C)
 +    FIELD(CTRL, TX_ENABLE, 0, 1)
 +    FIELD(CTRL, RX_ENABLE, 1, 1)
 +    FIELD(CTRL, NF, 2, 1)
 +    FIELD(CTRL, SLPBK, 4, 1)
 +    FIELD(CTRL, LLPBK, 5, 1)
 +    FIELD(CTRL, PARITY_EN, 6, 1)
 +    FIELD(CTRL, PARITY_ODD, 7, 1)
 +    FIELD(CTRL, RXBLVL, 8, 2)
 +    FIELD(CTRL, NCO, 16, 16)
 +REG32(STATUS, 0x10)
 +    FIELD(STATUS, TXFULL, 0, 1)
 +    FIELD(STATUS, RXFULL, 1, 1)
 +    FIELD(STATUS, TXEMPTY, 2, 1)
 +    FIELD(STATUS, RXIDLE, 4, 1)
 +    FIELD(STATUS, RXEMPTY, 5, 1)
 +REG32(RDATA, 0x14)
 +REG32(WDATA, 0x18)
 +REG32(FIFO_CTRL, 0x1c)
 +    FIELD(FIFO_CTRL, RXRST, 0, 1)
 +    FIELD(FIFO_CTRL, TXRST, 1, 1)
 +    FIELD(FIFO_CTRL, RXILVL, 2, 3)
 +    FIELD(FIFO_CTRL, TXILVL, 5, 2)
 +REG32(FIFO_STATUS, 0x20)
 +    FIELD(FIFO_STATUS, TXLVL, 0, 5)
 +    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 +REG32(OVRD, 0x24)
 +REG32(VAL, 0x28)
 +REG32(TIMEOUT_CTRL, 0x2c)
 +
  static void ibex_uart_update_irqs(IbexUartState *s)
  {
-     IbexUartState *s = opaque;
+     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
 -    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
 +           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
          return 1;
      }
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
      s->uart_status &= ~R_STATUS_RXIDLE_MASK;
      s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
 +    /* The RXFULL is set after receiving a single byte
 +     * as the FIFO buffers are not yet implemented.
 +     */
 +    s->uart_status |= R_STATUS_RXFULL_MASK;
 +    s->rx_level += 1;
      if (size > rx_fifo_level) {
          s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
      s->uart_timeout_ctrl = 0x00000000;
      s->tx_level = 0;
 +    s->rx_level = 0;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
          break;
      case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_FIFO_STATUS:
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
 --
-.30.1
+.31.1

-[PULL 04/16] target/riscv: add log of PMP permission checking
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-Like MMU translation, add qemu log of PMP permission checking for
-debugging.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 12 ++++++++++++
-file changed, 12 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             if (ret == TRANSLATE_SUCCESS) {
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                                size, access_type, mode);
-+
-+                qemu_log_mask(CPU_LOG_MMU,
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
-+                              __func__, pa, ret, prot_pmp, tlb_size);
-+
-                 prot &= prot_pmp;
-             }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-         if (ret == TRANSLATE_SUCCESS) {
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
-                                            size, access_type, mode);
-+
-+            qemu_log_mask(CPU_LOG_MMU,
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
-+                          __func__, pa, ret, prot_pmp, tlb_size);
-+
-             prot &= prot_pmp;
-         }
-     }
---
-.30.1

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+Deleted patch
-From: Jim Shu <cwshu@andestech.com>
-If PMP permission of any address has been changed by updating PMP entry,
-flush all TLB pages to prevent from getting old permission.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/pmp.c | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
-+++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "cpu.h"
- #include "trace.h"
-+#include "exec/exec-all.h"
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
-     uint8_t val);
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
-         cfg_val = (val >> 8 * i)  & 0xff;
-         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
-     }
-+
-+    /* If PMP permission of any addr has been changed, flush TLB pages. */
-+    tlb_flush(env_cpu(env));
- }
---
-.30.1

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-According to the specification the "field SPVP of hstatus controls the
-privilege level of the access" for the hypervisor virtual-machine load
-and store instructions HLV, HLVX and HSV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
-file changed, 14 insertions(+), 11 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-         use_background = true;
-     }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
-             mode = get_field(env->mstatus, MSTATUS_MPP);
-         }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
-                   __func__, address, access_type, mmu_idx);
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
--        if (get_field(env->mstatus, MSTATUS_MPRV)) {
--            mode = get_field(env->mstatus, MSTATUS_MPP);
-+    /* MPRV does not affect the virtual-machine load/store
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
-+               get_field(env->mstatus, MSTATUS_MPRV)) {
-+        mode = get_field(env->mstatus, MSTATUS_MPP);
-+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
-+            two_stage_lookup = true;
-         }
-     }
--    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
--        access_type != MMU_INST_FETCH &&
--        get_field(env->mstatus, MSTATUS_MPRV) &&
--        get_field(env->mstatus, MSTATUS_MPV)) {
--        two_stage_lookup = true;
--    }
--
-     if (riscv_cpu_virt_enabled(env) ||
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-          access_type != MMU_INST_FETCH)) {
---
-.30.1

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/csr.c | 7 ++++---
-file changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
-+++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
- static const char valid_vm_1_10_32[16] = {
-@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
- {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
--                      write_mask & hip_writable_mask);
-+                      write_mask & hvip_writable_mask);
--    *ret_value &= hip_writable_mask;
-+    *ret_value &= hvip_writable_mask;
-     return ret;
- }
---
-.30.1

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+Deleted patch
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-The current condition for the use of background registers only
-considers the hypervisor load and store instructions,
-but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu_helper.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
-      */
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
-         use_background = true;
-     }
---
-.30.1

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+Deleted patch
-From: Asherah Connor <ashe@kivikakk.ee>
-Provides fw_cfg for the virt machine on riscv.  This enables
-using e.g.  ramfb later.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/virt.h |  2 ++
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
- hw/riscv/Kconfig        |  1 +
-files changed, 33 insertions(+)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
-+++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
-     DeviceState *plic[VIRT_SOCKETS_MAX];
-     PFlashCFI01 *flash[2];
-+    FWCfgState *fw_cfg;
-     int fdt_size;
- };
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_PLIC,
-     VIRT_UART0,
-     VIRT_VIRTIO,
-+    VIRT_FW_CFG,
-     VIRT_FLASH,
-     VIRT_DRAM,
-     VIRT_PCIE_MMIO,
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
-+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
-     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
-     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
-     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
-@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-     return dev;
- }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
-+{
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
-+    FWCfgState *fw_cfg;
-+    char *nodename;
-+
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
-+                                  &address_space_memory);
-+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-+
-+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-+    qemu_fdt_add_subnode(mc->fdt, nodename);
-+    qemu_fdt_setprop_string(mc->fdt, nodename,
-+                            "compatible", "qemu,fw-cfg-mmio");
-+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
-+                                 2, base, 2, size);
-+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
-+    g_free(nodename);
-+    return fw_cfg;
-+}
-+
- static void virt_machine_init(MachineState *machine)
- {
-     const MemMapEntry *memmap = virt_memmap;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-         start_addr = virt_memmap[VIRT_FLASH].base;
-     }
-+    /*
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-+     */
-+    s->fw_cfg = create_fw_cfg(machine);
-+    rom_set_fw(s->fw_cfg);
-+
-     /* Compute the fdt load address in dram */
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
-                                    machine->ram_size, machine->fdt);
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
-+++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
-     select SIFIVE_PLIC
-     select SIFIVE_TEST
-     select VIRTIO_MMIO
-+    select FW_CFG_DMA
- config SIFIVE_E
-     bool
---
-.30.1

-[PULL 10/16] hw/riscv: allow ramfb on virt
+Deleted patch
-From: Asherah Connor <ashe@kivikakk.ee>
-Allow ramfb on virt.  This lets `-device ramfb' work.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/sysemu.h"
- #include "hw/pci/pci.h"
- #include "hw/pci-host/gpex.h"
-+#include "hw/display/ramfb.h"
- static const MemMapEntry virt_memmap[] = {
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
-     mc->numa_mem_supported = true;
-+
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
- }
- static const TypeInfo virt_machine_typeinfo = {
---
-.30.1

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL 6/7] hw/timer: Initial commit of Ibex Timer
-From: Bin Meng <bin.meng@windriver.com>
+Add support for the Ibex timer. This is used with the RISC-V
 mtime/mtimecmp similar to the SiFive CLINT.
-This adds the documentation to describe what is supported for the
+We currently don't support changing the prescale or the timervalue.
 'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ include/hw/timer/ibex_timer.h |  52 ++++++
- docs/system/target-riscv.rst               |  1 +
+ hw/timer/ibex_timer.c         | 305 ++++++++++++++++++++++++++++++++++
-files changed, 90 insertions(+)
+ MAINTAINERS                   |   6 +-
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ hw/timer/meson.build          |   1 +
 files changed, 360 insertions(+), 4 deletions(-)
  create mode 100644 include/hw/timer/ibex_timer.h
  create mode 100644 hw/timer/ibex_timer.c
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
++++ b/include/hw/timer/ibex_timer.h
 @@ -XXX,XX +XXX,XX @@
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
++/*
-+=============================================================
++ * QEMU lowRISC Ibex Timer device
-+
++ *
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
++ * Copyright (c) 2021 Western Digital
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
++ *
-+
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+For more details about Microchip PolarFire SoC, please see:
++ * of this software and associated documentation files (the "Software"), to deal
-+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
++ * in the Software without restriction, including without limitation the rights
-+
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-+The Icicle Kit board information can be found here:
++ * copies of the Software, and to permit persons to whom the Software is
-+https://www.microsemi.com/existing-parts/parts/152514
++ * furnished to do so, subject to the following conditions:
-+
++ *
-+Supported devices
++ * The above copyright notice and this permission notice shall be included in
-+-----------------
++ * all copies or substantial portions of the Software.
-+
++ *
-+The ``microchip-icicle-kit`` machine supports the following devices:
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * 1 E51 core
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * 4 U54 cores
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * Core Level Interruptor (CLINT)
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-+ * Platform-Level Interrupt Controller (PLIC)
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-+ * L2 Loosely Integrated Memory (L2-LIM)
++ * THE SOFTWARE.
-+ * DDR memory controller
++ */
-+ * 5 MMUARTs
++
-+ * 1 DMA controller
++#ifndef HW_IBEX_TIMER_H
-+ * 2 GEM Ethernet controllers
++#define HW_IBEX_TIMER_H
-+ * 1 SDHC storage controller
++
-+
++#include "hw/sysbus.h"
-+Boot options
++
-+------------
++#define TYPE_IBEX_TIMER "ibex-timer"
-+
++OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
-+The ``microchip-icicle-kit`` machine can start using the standard -bios
++
-+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
++struct IbexTimerState {
-+HSS loads the second stage bootloader U-Boot from an SD card. It does not
++    /* <private> */
-+support direct kernel loading via the -kernel option. One has to load kernel
++    SysBusDevice parent_obj;
-+from U-Boot.
++
-+
++    /* <public> */
-+The memory is set to 1537 MiB by default which is the minimum required high
++    MemoryRegion mmio;
-+memory size by HSS. A sanity check on ram size is performed in the machine
++
-+init routine to prompt user to increase the RAM size to > 1537 MiB when less
++    uint32_t timer_ctrl;
-+than 1537 MiB ram is detected.
++    uint32_t timer_cfg0;
-+
++    uint32_t timer_compare_lower0;
-+Boot the machine
++    uint32_t timer_compare_upper0;
-+----------------
++    uint32_t timer_intr_enable;
-+
++    uint32_t timer_intr_state;
-+HSS 2020.12 release is tested at the time of writing. To build an HSS image
++    uint32_t timer_intr_test;
-+that can be booted by the ``microchip-icicle-kit`` machine, type the following
++
-+in the HSS source tree:
++    uint32_t timebase_freq;
 +
-+.. code-block:: bash
++    qemu_irq irq;
-+
++};
-+  $ export CROSS_COMPILE=riscv64-linux-
++#endif /* HW_IBEX_TIMER_H */
-+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
-+  $ make BOARD=mpfs-icicle-kit-es
+new file mode 100644
-+
+index XXXXXXX..XXXXXXX
-+Download the official SD card image released by Microchip and prepare it for
+--- /dev/null
-+QEMU usage:
++++ b/hw/timer/ibex_timer.c
-+
+@@ -XXX,XX +XXX,XX @@
-+.. code-block:: bash
++/*
-+
++ * QEMU lowRISC Ibex Timer device
-+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++ *
-+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++ * Copyright (c) 2021 Western Digital
-+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
++ *
-+
++ * For details check the documentation here:
-+Then we can boot the machine by:
++ *    https://docs.opentitan.org/hw/ip/rv_timer/doc/
-+
++ *
-+.. code-block:: bash
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+
++ * of this software and associated documentation files (the "Software"), to deal
-+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
++ * in the Software without restriction, including without limitation the rights
-+      -bios path/to/hss.bin -sd path/to/sdcard.img \
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-+      -nic user,model=cadence_gem \
++ * copies of the Software, and to permit persons to whom the Software is
-+      -nic tap,ifname=tap,model=cadence_gem,script=no \
++ * furnished to do so, subject to the following conditions:
-+      -display none -serial stdio \
++ *
-+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
++ * The above copyright notice and this permission notice shall be included in
-+      -serial chardev:serial1
++ * all copies or substantial portions of the Software.
-+
++ *
-+With above command line, current terminal session will be used for the first
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+serial port. Open another terminal window, and use `minicom` to connect the
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+second serial port.
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+.. code-block:: bash
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-+
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-+  $ minicom -D unix\#serial1.sock
++ * THE SOFTWARE.
-+
++ */
-+HSS output is on the first serial port (stdio) and U-Boot outputs on the
++
-+second serial port. U-Boot will automatically load the Linux kernel from
++#include "qemu/osdep.h"
-+the SD card image.
++#include "qemu/log.h"
-+
++#include "qemu/timer.h"
-+.. _HSS: https://github.com/polarfire-soc/hart-software-services
++#include "hw/timer/ibex_timer.h"
-diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
++#include "hw/irq.h"
 +#include "hw/qdev-properties.h"
 +#include "target/riscv/cpu.h"
 +#include "migration/vmstate.h"
 +
 +REG32(CTRL, 0x00)
 +    FIELD(CTRL, ACTIVE, 0, 1)
 +REG32(CFG0, 0x100)
 +    FIELD(CFG0, PRESCALE, 0, 12)
 +    FIELD(CFG0, STEP, 16, 8)
 +REG32(LOWER0, 0x104)
 +REG32(UPPER0, 0x108)
 +REG32(COMPARE_LOWER0, 0x10C)
 +REG32(COMPARE_UPPER0, 0x110)
 +REG32(INTR_ENABLE, 0x114)
 +    FIELD(INTR_ENABLE, IE_0, 0, 1)
 +REG32(INTR_STATE, 0x118)
 +    FIELD(INTR_STATE, IS_0, 0, 1)
 +REG32(INTR_TEST, 0x11C)
 +    FIELD(INTR_TEST, T_0, 0, 1)
 +
 +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 +{
 +    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 +                    timebase_freq, NANOSECONDS_PER_SECOND);
 +}
 +
 +static void ibex_timer_update_irqs(IbexTimerState *s)
 +{
 +    CPUState *cs = qemu_get_cpu(0);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    uint64_t value = s->timer_compare_lower0 |
 +                         ((uint64_t)s->timer_compare_upper0 << 32);
 +    uint64_t next, diff;
 +    uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
 +
 +    if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
 +        /* Timer isn't active */
 +        return;
 +    }
 +
 +    /* Update the CPUs mtimecmp */
 +    cpu->env.timecmp = value;
 +
 +    if (cpu->env.timecmp <= now) {
 +        /*
 +         * If the mtimecmp was in the past raise the interrupt now.
 +         */
 +        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
 +        if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
 +            s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
 +            qemu_set_irq(s->irq, true);
 +        }
 +        return;
 +    }
 +
 +    /* Setup a timer to trigger the interrupt in the future */
 +    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
 +    qemu_set_irq(s->irq, false);
 +
 +    diff = cpu->env.timecmp - now;
 +    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 +                                 muldiv64(diff,
 +                                          NANOSECONDS_PER_SECOND,
 +                                          s->timebase_freq);
 +
 +    if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
 +        /* We overflowed the timer, just set it as large as we can */
 +        timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
 +    } else {
 +        timer_mod(cpu->env.timer, next);
 +    }
 +}
 +
 +static void ibex_timer_cb(void *opaque)
 +{
 +    IbexTimerState *s = opaque;
 +    CPUState *cs = qemu_get_cpu(0);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
 +    if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
 +        s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
 +        qemu_set_irq(s->irq, true);
 +    }
 +}
 +
 +static void ibex_timer_reset(DeviceState *dev)
 +{
 +    IbexTimerState *s = IBEX_TIMER(dev);
 +
 +    CPUState *cpu = qemu_get_cpu(0);
 +    CPURISCVState *env = cpu->env_ptr;
 +    env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 +                              &ibex_timer_cb, s);
 +    env->timecmp = 0;
 +
 +    s->timer_ctrl = 0x00000000;
 +    s->timer_cfg0 = 0x00010000;
 +    s->timer_compare_lower0 = 0xFFFFFFFF;
 +    s->timer_compare_upper0 = 0xFFFFFFFF;
 +    s->timer_intr_enable = 0x00000000;
 +    s->timer_intr_state = 0x00000000;
 +    s->timer_intr_test = 0x00000000;
 +
 +    ibex_timer_update_irqs(s);
 +}
 +
 +static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
 +                                       unsigned int size)
 +{
 +    IbexTimerState *s = opaque;
 +    uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
 +    uint64_t retvalue = 0;
 +
 +    switch (addr >> 2) {
 +    case R_CTRL:
 +        retvalue = s->timer_ctrl;
 +        break;
 +    case R_CFG0:
 +        retvalue = s->timer_cfg0;
 +        break;
 +    case R_LOWER0:
 +        retvalue = now;
 +        break;
 +    case R_UPPER0:
 +        retvalue = now >> 32;
 +        break;
 +    case R_COMPARE_LOWER0:
 +        retvalue = s->timer_compare_lower0;
 +        break;
 +    case R_COMPARE_UPPER0:
 +        retvalue = s->timer_compare_upper0;
 +        break;
 +    case R_INTR_ENABLE:
 +        retvalue = s->timer_intr_enable;
 +        break;
 +    case R_INTR_STATE:
 +        retvalue = s->timer_intr_state;
 +        break;
 +    case R_INTR_TEST:
 +        retvalue = s->timer_intr_test;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +        return 0;
 +    }
 +
 +    return retvalue;
 +}
 +
 +static void ibex_timer_write(void *opaque, hwaddr addr,
 +                             uint64_t val64, unsigned int size)
 +{
 +    IbexTimerState *s = opaque;
 +    uint32_t val = val64;
 +
 +    switch (addr >> 2) {
 +    case R_CTRL:
 +        s->timer_ctrl = val;
 +        break;
 +    case R_CFG0:
 +        qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
 +        s->timer_cfg0 = val;
 +        break;
 +    case R_LOWER0:
 +        qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
 +        break;
 +    case R_UPPER0:
 +        qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
 +        break;
 +    case R_COMPARE_LOWER0:
 +        s->timer_compare_lower0 = val;
 +        ibex_timer_update_irqs(s);
 +        break;
 +    case R_COMPARE_UPPER0:
 +        s->timer_compare_upper0 = val;
 +        ibex_timer_update_irqs(s);
 +        break;
 +    case R_INTR_ENABLE:
 +        s->timer_intr_enable = val;
 +        break;
 +    case R_INTR_STATE:
 +        /* Write 1 to clear */
 +        s->timer_intr_state &= ~val;
 +        break;
 +    case R_INTR_TEST:
 +        s->timer_intr_test = val;
 +        if (s->timer_intr_enable &
 +            s->timer_intr_test &
 +            R_INTR_ENABLE_IE_0_MASK) {
 +            s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
 +            qemu_set_irq(s->irq, true);
 +        }
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +}
 +
 +static const MemoryRegionOps ibex_timer_ops = {
 +    .read = ibex_timer_read,
 +    .write = ibex_timer_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +};
 +
 +static int ibex_timer_post_load(void *opaque, int version_id)
 +{
 +    IbexTimerState *s = opaque;
 +
 +    ibex_timer_update_irqs(s);
 +    return 0;
 +}
 +
 +static const VMStateDescription vmstate_ibex_timer = {
 +    .name = TYPE_IBEX_TIMER,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .post_load = ibex_timer_post_load,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(timer_ctrl, IbexTimerState),
 +        VMSTATE_UINT32(timer_cfg0, IbexTimerState),
 +        VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
 +        VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
 +        VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
 +        VMSTATE_UINT32(timer_intr_state, IbexTimerState),
 +        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static Property ibex_timer_properties[] = {
 +    DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void ibex_timer_init(Object *obj)
 +{
 +    IbexTimerState *s = IBEX_TIMER(obj);
 +
 +    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 +
 +    memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
 +                          TYPE_IBEX_TIMER, 0x400);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 +}
 +
 +static void ibex_timer_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = ibex_timer_reset;
 +    dc->vmsd = &vmstate_ibex_timer;
 +    device_class_set_props(dc, ibex_timer_properties);
 +}
 +
 +static const TypeInfo ibex_timer_info = {
 +    .name          = TYPE_IBEX_TIMER,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IbexTimerState),
 +    .instance_init = ibex_timer_init,
 +    .class_init    = ibex_timer_class_init,
 +};
 +
 +static void ibex_timer_register_types(void)
 +{
 +    type_register_static(&ibex_timer_info);
 +}
 +
 +type_init(ibex_timer_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-riscv.rst
+--- a/MAINTAINERS
-+++ b/docs/system/target-riscv.rst
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ M: Alistair Francis <Alistair.Francis@wdc.com>
- .. toctree::
+ L: qemu-riscv@nongnu.org
-    :maxdepth: 1
+ S: Supported
+ F: hw/riscv/opentitan.c
-+   riscv/microchip-icicle-kit
+-F: hw/char/ibex_uart.c
-    riscv/sifive_u
+-F: hw/intc/ibex_plic.c
++F: hw/*/ibex_*.c
- RISC-V CPU features
+ F: include/hw/riscv/opentitan.h
 -F: include/hw/char/ibex_uart.h
 -F: include/hw/intc/ibex_plic.h
 +F: include/hw/*/ibex_*.h
  Microchip PolarFire SoC Icicle Kit
  M: Bin Meng <bin.meng@windriver.com>
 diff --git a/hw/timer/meson.build b/hw/timer/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/meson.build
 +++ b/hw/timer/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
  softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
  softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
 +specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
  specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))
 --
-.30.1
+.31.1

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Connect the Ibex timer to the OpenTitan machine. The timer can trigger
 the RISC-V MIE interrupt as well as a custom device interrupt.
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-short of its purpose, as all it checks is whether two-stage address
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-translation either via the hypervisor-load store instructions or the
+Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
-MPRV feature would be allowed.
+---
  include/hw/riscv/opentitan.h |  5 ++++-
  hw/riscv/opentitan.c         | 14 +++++++++++---
 files changed, 15 insertions(+), 4 deletions(-)
-What we really need instead is whether two-stage address translation was
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
 active when the exception was raised. However, in riscv_cpu_do_interrupt
 we do not have the information to reliably detect this. Therefore, when
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.h        |  4 ++++
  target/riscv/cpu.c        |  1 +
  target/riscv/cpu_helper.c | 21 ++++++++-------------
 files changed, 13 insertions(+), 13 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/include/hw/riscv/opentitan.h
-+++ b/target/riscv/cpu.h
++++ b/include/hw/riscv/opentitan.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@
-     target_ulong satp_hs;
+ #include "hw/riscv/riscv_hart.h"
-     uint64_t mstatus_hs;
+ #include "hw/intc/ibex_plic.h"
+ #include "hw/char/ibex_uart.h"
-+    /* Signals whether the current exception occurred with two-stage address
++#include "hw/timer/ibex_timer.h"
-+       translation active. */
+ #include "qom/object.h"
-+    bool two_stage_lookup;
  #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
      RISCVHartArrayState cpus;
      IbexPlicState plic;
      IbexUartState uart;
 +    IbexTimerState timer;
      MemoryRegion flash_mem;
      MemoryRegion rom;
@@ -XXX,XX +XXX,XX @@ enum {
      IBEX_DEV_SPI,
      IBEX_DEV_I2C,
      IBEX_DEV_PATTGEN,
 -    IBEX_DEV_RV_TIMER,
 +    IBEX_DEV_TIMER,
      IBEX_DEV_SENSOR_CTRL,
      IBEX_DEV_OTP_CTRL,
      IBEX_DEV_PWRMGR,
@@ -XXX,XX +XXX,XX @@ enum {
  };
  enum {
 +    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
      IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
      IBEX_UART0_RX_TIMEOUT_IRQ = 7,
      IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/opentitan.c
 +++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
      [IBEX_DEV_SPI] =            {  0x40050000,  0x1000  },
      [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
      [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
 -    [IBEX_DEV_RV_TIMER] =       {  0x40100000,  0x1000  },
 +    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
      [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
      [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
      [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
      object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
      object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 +
-     target_ulong scounteren;
++    object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
      target_ulong mcounteren;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
      env->mcause = 0;
      env->pc = env->resetvec;
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE;
      env->load_res = -1;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
          g_assert_not_reached();
      }
      env->badaddr = address;
 +    env->two_stage_lookup = two_stage;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-     }
+, qdev_get_gpio_in(DEVICE(&s->plic),
+                        IBEX_UART0_RX_OVERFLOW_IRQ));
-     env->badaddr = addr;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
++    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
++        return;
-     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
++    }
- }
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
++                       0, qdev_get_gpio_in(DEVICE(&s->plic),
-         g_assert_not_reached();
++                       IBEX_TIMER_TIMEREXPIRED0_0));
-     }
++
-     env->badaddr = addr;
+     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
+     create_unimplemented_device("riscv.lowrisc.ibex.spi",
-     riscv_raise_exception(env, cs->exception_index, retaddr);
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
- }
+         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
- #endif /* !CONFIG_USER_ONLY */
+     create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
-         /* handle the trap in S-mode */
+-    create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
-         if (riscv_has_ext(env, RVH)) {
+-        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+     create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
--            bool two_stage_lookup = false;
+         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
 -            if (env->priv == PRV_M ||
 -                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                    get_field(env->hstatus, HSTATUS_HU))) {
 -                    two_stage_lookup = true;
 -            }
 -
 -            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
 +            if (env->two_stage_lookup && write_tval) {
                  /*
                   * If we are writing a guest virtual address to stval, set
                   * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  riscv_cpu_set_force_hs_excep(env, 0);
              } else {
                  /* Trap into HS mode */
 -                if (!two_stage_lookup) {
 -                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 -                                             riscv_cpu_virt_enabled(env));
 -                }
 +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                  htval = env->guest_phys_fault_addr;
              }
          }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
       * RISC-V ISA Specification.
       */
 +    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.31.1

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+Deleted patch
-From: Bin Meng <bin.meng@windriver.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
-the address bytes. Note only SPI mode is supported by SST flashes.
-[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/block/m25p80.c | 3 +++
-file changed, 3 insertions(+)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
-     s->needed_bytes = get_addr_length(s);
-     switch (get_man(s)) {
-     /* Dummy cycles - modeled with bytes writes instead of bits */
-+    case MAN_SST:
-+        s->needed_bytes += 1;
-+        break;
-     case MAN_WINBOND:
-         s->needed_bytes += 8;
-         break;
---
-.30.1

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_EMMC_SD_MUX,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
     MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
 
+    /* eMMC/SD mux */
+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
                            "microchip.pfsoc.qspi_xip",
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:

Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24 09:31:26 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2

for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:

hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24 05:00:13 -0700)

----------------------------------------------------------------
Third RISC-V PR for 6.1 release

- Fix MISA in the DisasContext
 - Fix GDB CSR XML generation
 - QOMify the SiFive UART
 - Add support for the OpenTitan timer

----------------------------------------------------------------
Alistair Francis (4):
      target/riscv: Use target_ulong for the DisasContext misa
      hw/char/ibex_uart: Make the register layout private
      hw/timer: Initial commit of Ibex Timer
      hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

Bin Meng (1):
      target/riscv: gdbstub: Fix dynamic CSR XML generation

Lukas Jünger (2):
      hw/char: Consistent function names for sifive_uart
      hw/char: QOMify sifive_uart

include/hw/char/ibex_uart.h   |  37 -----
 include/hw/char/sifive_uart.h |  11 +-
 include/hw/riscv/opentitan.h  |   5 +-
 include/hw/timer/ibex_timer.h |  52 +++++++
 hw/char/ibex_uart.c           |  37 +++++
 hw/char/sifive_uart.c         | 152 +++++++++++++++++----
 hw/riscv/opentitan.c          |  14 +-
 hw/timer/ibex_timer.c         | 305 ++++++++++++++++++++++++++++++++++++++++++
 target/riscv/gdbstub.c        |   2 +-
 target/riscv/translate.c      |   2 +-
 MAINTAINERS                   |   6 +-
 hw/timer/meson.build          |   1 +
 12 files changed, 543 insertions(+), 81 deletions(-)
 create mode 100644 include/hw/timer/ibex_timer.h
 create mode 100644 hw/timer/ibex_timer.c

From: Bin Meng <bin.meng@windriver.com>

Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.

Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
 
     for (i = 0; i < CSR_TABLE_SIZE; i++) {
         predicate = csr_ops[i].predicate;
-        if (predicate && !predicate(env, i)) {
+        if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
             if (csr_ops[i].name) {
                 g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
             } else {
-- 
2.31.1

From: Lukas Jünger <lukas.juenger@greensocs.com>

This cleans up function names in the SiFive UART model.

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/sifive_uart.c | 46 ++++++++++++++++++++++---------------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -XXX,XX +XXX,XX @@
  */
 
 /* Returns the state of the IP (interrupt pending) register */
-static uint64_t uart_ip(SiFiveUARTState *s)
+static uint64_t sifive_uart_ip(SiFiveUARTState *s)
 {
     uint64_t ret = 0;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t uart_ip(SiFiveUARTState *s)
     return ret;
 }
 
-static void update_irq(SiFiveUARTState *s)
+static void sifive_uart_update_irq(SiFiveUARTState *s)
 {
     int cond = 0;
     if ((s->ie & SIFIVE_UART_IE_TXWM) ||
@@ -XXX,XX +XXX,XX @@ static void update_irq(SiFiveUARTState *s)
 }
 
 static uint64_t
-uart_read(void *opaque, hwaddr addr, unsigned int size)
+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     unsigned char r;
@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
             memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
             s->rx_fifo_len--;
             qemu_chr_fe_accept_input(&s->chr);
-            update_irq(s);
+            sifive_uart_update_irq(s);
             return r;
         }
         return 0x80000000;
@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
     case SIFIVE_UART_IE:
         return s->ie;
     case SIFIVE_UART_IP:
-        return uart_ip(s);
+        return sifive_uart_ip(s);
     case SIFIVE_UART_TXCTRL:
         return s->txctrl;
     case SIFIVE_UART_RXCTRL:
@@ -XXX,XX +XXX,XX @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
 }
 
 static void
-uart_write(void *opaque, hwaddr addr,
-           uint64_t val64, unsigned int size)
+sifive_uart_write(void *opaque, hwaddr addr,
+                  uint64_t val64, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     uint32_t value = val64;
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
     switch (addr) {
     case SIFIVE_UART_TXFIFO:
         qemu_chr_fe_write(&s->chr, &ch, 1);
-        update_irq(s);
+        sifive_uart_update_irq(s);
         return;
     case SIFIVE_UART_IE:
         s->ie = val64;
-        update_irq(s);
+        sifive_uart_update_irq(s);
         return;
     case SIFIVE_UART_TXCTRL:
         s->txctrl = val64;
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
                   __func__, (int)addr, (int)value);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
+static const MemoryRegionOps sifive_uart_ops = {
+    .read = sifive_uart_read,
+    .write = sifive_uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 4,
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
     }
 };
 
-static void uart_rx(void *opaque, const uint8_t *buf, int size)
+static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)
 {
     SiFiveUARTState *s = opaque;
 
@@ -XXX,XX +XXX,XX @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
     }
     s->rx_fifo[s->rx_fifo_len++] = *buf;
 
-    update_irq(s);
+    sifive_uart_update_irq(s);
 }
 
-static int uart_can_rx(void *opaque)
+static int sifive_uart_can_rx(void *opaque)
 {
     SiFiveUARTState *s = opaque;
 
     return s->rx_fifo_len < sizeof(s->rx_fifo);
 }
 
-static void uart_event(void *opaque, QEMUChrEvent event)
+static void sifive_uart_event(void *opaque, QEMUChrEvent event)
 {
 }
 
-static int uart_be_change(void *opaque)
+static int sifive_uart_be_change(void *opaque)
 {
     SiFiveUARTState *s = opaque;
 
-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-        uart_be_change, s, NULL, true);
+    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+                             sifive_uart_event, sifive_uart_be_change, s,
+                             NULL, true);
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
     s->irq = irq;
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-        uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
+    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+                             sifive_uart_event, sifive_uart_be_change, s,
+                             NULL, true);
+    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
                           TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
     memory_region_add_subregion(address_space, base, &s->mmio);
     return s;
-- 
2.31.1

From: Lukas Jünger <lukas.juenger@greensocs.com>

This QOMifies the SiFive UART model. Migration and reset have been
implemented.

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210616092326.59639-3-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/sifive_uart.h |  11 ++--
 hw/char/sifive_uart.c         | 114 +++++++++++++++++++++++++++++++---
 2 files changed, 109 insertions(+), 16 deletions(-)

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -XXX,XX +XXX,XX @@
 #define HW_SIFIVE_UART_H
 
 #include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@ enum {
 
 #define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
 #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
+#define SIFIVE_UART_RX_FIFO_SIZE 8
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
-                         TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
 
 struct SiFiveUARTState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct SiFiveUARTState {
     qemu_irq irq;
     MemoryRegion mmio;
     CharBackend chr;
-    uint8_t rx_fifo[8];
-    unsigned int rx_fifo_len;
+    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
+    uint8_t rx_fifo_len;
     uint32_t ie;
     uint32_t ip;
     uint32_t txctrl;
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/log.h"
+#include "migration/vmstate.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
 #include "hw/irq.h"
 #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
 
 /*
  * Not yet implemented:
@@ -XXX,XX +XXX,XX @@ static int sifive_uart_be_change(void *opaque)
     return 0;
 }
 
+static Property sifive_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
+                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+    SiFiveUARTState *s = SIFIVE_UART(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+                             sifive_uart_event, sifive_uart_be_change, s,
+                             NULL, true);
+
+}
+
+static void sifive_uart_reset_enter(Object *obj, ResetType type)
+{
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+    s->ie = 0;
+    s->ip = 0;
+    s->txctrl = 0;
+    s->rxctrl = 0;
+    s->div = 0;
+    s->rx_fifo_len = 0;
+}
+
+static void sifive_uart_reset_hold(Object *obj)
+{
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+    qemu_irq_lower(s->irq);
+}
+
+static const VMStateDescription vmstate_sifive_uart = {
+    .name = TYPE_SIFIVE_UART,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
+                            SIFIVE_UART_RX_FIFO_SIZE),
+        VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
+        VMSTATE_UINT32(ie, SiFiveUARTState),
+        VMSTATE_UINT32(ip, SiFiveUARTState),
+        VMSTATE_UINT32(txctrl, SiFiveUARTState),
+        VMSTATE_UINT32(rxctrl, SiFiveUARTState),
+        VMSTATE_UINT32(div, SiFiveUARTState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    dc->realize = sifive_uart_realize;
+    dc->vmsd = &vmstate_sifive_uart;
+    rc->phases.enter = sifive_uart_reset_enter;
+    rc->phases.hold  = sifive_uart_reset_hold;
+    device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+    .name          = TYPE_SIFIVE_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFiveUARTState),
+    .instance_init = sifive_uart_init,
+    .class_init    = sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+    type_register_static(&sifive_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
 /*
  * Create UART device.
  */
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     Chardev *chr, qemu_irq irq)
 {
-    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-    s->irq = irq;
-    qemu_chr_fe_init(&s->chr, chr, &error_abort);
-    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
-                             sifive_uart_event, sifive_uart_be_change, s,
-                             NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
-                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-    memory_region_add_subregion(address_space, base, &s->mmio);
-    return s;
+    DeviceState *dev;
+    SysBusDevice *s;
+    SiFiveUARTState *r;
+
+    dev = qdev_new("riscv.sifive.uart");
+    s = SYS_BUS_DEVICE(dev);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize_and_unref(s, &error_fatal);
+    memory_region_add_subregion(address_space, base,
+                                sysbus_mmio_get_region(s, 0));
+    sysbus_connect_irq(s, 0, irq);
+
+    r = SIFIVE_UART(dev);
+    return r;
 }
-- 
2.31.1

We don't need to expose the register layout in the public header, so
don't.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: c437f570b2b30ab4170387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
---
 include/hw/char/ibex_uart.h | 37 -------------------------------------
 hw/char/ibex_uart.c         | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qom/object.h"
 
-REG32(INTR_STATE, 0x00)
-    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
-    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
-    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
-    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
-REG32(INTR_ENABLE, 0x04)
-REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
-    FIELD(CTRL, TX_ENABLE, 0, 1)
-    FIELD(CTRL, RX_ENABLE, 1, 1)
-    FIELD(CTRL, NF, 2, 1)
-    FIELD(CTRL, SLPBK, 4, 1)
-    FIELD(CTRL, LLPBK, 5, 1)
-    FIELD(CTRL, PARITY_EN, 6, 1)
-    FIELD(CTRL, PARITY_ODD, 7, 1)
-    FIELD(CTRL, RXBLVL, 8, 2)
-    FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
-    FIELD(STATUS, TXFULL, 0, 1)
-    FIELD(STATUS, RXFULL, 1, 1)
-    FIELD(STATUS, TXEMPTY, 2, 1)
-    FIELD(STATUS, RXIDLE, 4, 1)
-    FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
-    FIELD(FIFO_CTRL, RXRST, 0, 1)
-    FIELD(FIFO_CTRL, TXRST, 1, 1)
-    FIELD(FIFO_CTRL, RXILVL, 2, 3)
-    FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
-    FIELD(FIFO_STATUS, TXLVL, 0, 5)
-    FIELD(FIFO_STATUS, RXLVL, 16, 5)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
-
 #define IBEX_UART_TX_FIFO_SIZE 16
 #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 
+REG32(INTR_STATE, 0x00)
+    FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
+    FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
+    FIELD(INTR_STATE, TX_EMPTY, 2, 1)
+    FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
+REG32(INTR_ENABLE, 0x04)
+REG32(INTR_TEST, 0x08)
+REG32(CTRL, 0x0C)
+    FIELD(CTRL, TX_ENABLE, 0, 1)
+    FIELD(CTRL, RX_ENABLE, 1, 1)
+    FIELD(CTRL, NF, 2, 1)
+    FIELD(CTRL, SLPBK, 4, 1)
+    FIELD(CTRL, LLPBK, 5, 1)
+    FIELD(CTRL, PARITY_EN, 6, 1)
+    FIELD(CTRL, PARITY_ODD, 7, 1)
+    FIELD(CTRL, RXBLVL, 8, 2)
+    FIELD(CTRL, NCO, 16, 16)
+REG32(STATUS, 0x10)
+    FIELD(STATUS, TXFULL, 0, 1)
+    FIELD(STATUS, RXFULL, 1, 1)
+    FIELD(STATUS, TXEMPTY, 2, 1)
+    FIELD(STATUS, RXIDLE, 4, 1)
+    FIELD(STATUS, RXEMPTY, 5, 1)
+REG32(RDATA, 0x14)
+REG32(WDATA, 0x18)
+REG32(FIFO_CTRL, 0x1c)
+    FIELD(FIFO_CTRL, RXRST, 0, 1)
+    FIELD(FIFO_CTRL, TXRST, 1, 1)
+    FIELD(FIFO_CTRL, RXILVL, 2, 3)
+    FIELD(FIFO_CTRL, TXILVL, 5, 2)
+REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
+REG32(OVRD, 0x24)
+REG32(VAL, 0x28)
+REG32(TIMEOUT_CTRL, 0x2c)
+
 static void ibex_uart_update_irqs(IbexUartState *s)
 {
     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
-- 
2.31.1

Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.

We currently don't support changing the prescale or the timervalue.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
---
 include/hw/timer/ibex_timer.h |  52 ++++++
 hw/timer/ibex_timer.c         | 305 ++++++++++++++++++++++++++++++++++
 MAINTAINERS                   |   6 +-
 hw/timer/meson.build          |   1 +
 4 files changed, 360 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/timer/ibex_timer.h
 create mode 100644 hw/timer/ibex_timer.c

diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/timer/ibex_timer.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU lowRISC Ibex Timer device
+ *
+ * Copyright (c) 2021 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IBEX_TIMER_H
+#define HW_IBEX_TIMER_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IBEX_TIMER "ibex-timer"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
+
+struct IbexTimerState {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t timer_ctrl;
+    uint32_t timer_cfg0;
+    uint32_t timer_compare_lower0;
+    uint32_t timer_compare_upper0;
+    uint32_t timer_intr_enable;
+    uint32_t timer_intr_state;
+    uint32_t timer_intr_test;
+
+    uint32_t timebase_freq;
+
+    qemu_irq irq;
+};
+#endif /* HW_IBEX_TIMER_H */
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/timer/ibex_timer.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU lowRISC Ibex Timer device
+ *
+ * Copyright (c) 2021 Western Digital
+ *
+ * For details check the documentation here:
+ *    https://docs.opentitan.org/hw/ip/rv_timer/doc/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "hw/timer/ibex_timer.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "target/riscv/cpu.h"
+#include "migration/vmstate.h"
+
+REG32(CTRL, 0x00)
+    FIELD(CTRL, ACTIVE, 0, 1)
+REG32(CFG0, 0x100)
+    FIELD(CFG0, PRESCALE, 0, 12)
+    FIELD(CFG0, STEP, 16, 8)
+REG32(LOWER0, 0x104)
+REG32(UPPER0, 0x108)
+REG32(COMPARE_LOWER0, 0x10C)
+REG32(COMPARE_UPPER0, 0x110)
+REG32(INTR_ENABLE, 0x114)
+    FIELD(INTR_ENABLE, IE_0, 0, 1)
+REG32(INTR_STATE, 0x118)
+    FIELD(INTR_STATE, IS_0, 0, 1)
+REG32(INTR_TEST, 0x11C)
+    FIELD(INTR_TEST, T_0, 0, 1)
+
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
+{
+    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+                    timebase_freq, NANOSECONDS_PER_SECOND);
+}
+
+static void ibex_timer_update_irqs(IbexTimerState *s)
+{
+    CPUState *cs = qemu_get_cpu(0);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    uint64_t value = s->timer_compare_lower0 |
+                         ((uint64_t)s->timer_compare_upper0 << 32);
+    uint64_t next, diff;
+    uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
+
+    if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
+        /* Timer isn't active */
+        return;
+    }
+
+    /* Update the CPUs mtimecmp */
+    cpu->env.timecmp = value;
+
+    if (cpu->env.timecmp <= now) {
+        /*
+         * If the mtimecmp was in the past raise the interrupt now.
+         */
+        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+        if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
+            s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+            qemu_set_irq(s->irq, true);
+        }
+        return;
+    }
+
+    /* Setup a timer to trigger the interrupt in the future */
+    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
+    qemu_set_irq(s->irq, false);
+
+    diff = cpu->env.timecmp - now;
+    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+                                 muldiv64(diff,
+                                          NANOSECONDS_PER_SECOND,
+                                          s->timebase_freq);
+
+    if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
+        /* We overflowed the timer, just set it as large as we can */
+        timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
+    } else {
+        timer_mod(cpu->env.timer, next);
+    }
+}
+
+static void ibex_timer_cb(void *opaque)
+{
+    IbexTimerState *s = opaque;
+    CPUState *cs = qemu_get_cpu(0);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+    if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
+        s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+        qemu_set_irq(s->irq, true);
+    }
+}
+
+static void ibex_timer_reset(DeviceState *dev)
+{
+    IbexTimerState *s = IBEX_TIMER(dev);
+
+    CPUState *cpu = qemu_get_cpu(0);
+    CPURISCVState *env = cpu->env_ptr;
+    env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                              &ibex_timer_cb, s);
+    env->timecmp = 0;
+
+    s->timer_ctrl = 0x00000000;
+    s->timer_cfg0 = 0x00010000;
+    s->timer_compare_lower0 = 0xFFFFFFFF;
+    s->timer_compare_upper0 = 0xFFFFFFFF;
+    s->timer_intr_enable = 0x00000000;
+    s->timer_intr_state = 0x00000000;
+    s->timer_intr_test = 0x00000000;
+
+    ibex_timer_update_irqs(s);
+}
+
+static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
+                                       unsigned int size)
+{
+    IbexTimerState *s = opaque;
+    uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
+    uint64_t retvalue = 0;
+
+    switch (addr >> 2) {
+    case R_CTRL:
+        retvalue = s->timer_ctrl;
+        break;
+    case R_CFG0:
+        retvalue = s->timer_cfg0;
+        break;
+    case R_LOWER0:
+        retvalue = now;
+        break;
+    case R_UPPER0:
+        retvalue = now >> 32;
+        break;
+    case R_COMPARE_LOWER0:
+        retvalue = s->timer_compare_lower0;
+        break;
+    case R_COMPARE_UPPER0:
+        retvalue = s->timer_compare_upper0;
+        break;
+    case R_INTR_ENABLE:
+        retvalue = s->timer_intr_enable;
+        break;
+    case R_INTR_STATE:
+        retvalue = s->timer_intr_state;
+        break;
+    case R_INTR_TEST:
+        retvalue = s->timer_intr_test;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+        return 0;
+    }
+
+    return retvalue;
+}
+
+static void ibex_timer_write(void *opaque, hwaddr addr,
+                             uint64_t val64, unsigned int size)
+{
+    IbexTimerState *s = opaque;
+    uint32_t val = val64;
+
+    switch (addr >> 2) {
+    case R_CTRL:
+        s->timer_ctrl = val;
+        break;
+    case R_CFG0:
+        qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
+        s->timer_cfg0 = val;
+        break;
+    case R_LOWER0:
+        qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
+        break;
+    case R_UPPER0:
+        qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
+        break;
+    case R_COMPARE_LOWER0:
+        s->timer_compare_lower0 = val;
+        ibex_timer_update_irqs(s);
+        break;
+    case R_COMPARE_UPPER0:
+        s->timer_compare_upper0 = val;
+        ibex_timer_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        s->timer_intr_enable = val;
+        break;
+    case R_INTR_STATE:
+        /* Write 1 to clear */
+        s->timer_intr_state &= ~val;
+        break;
+    case R_INTR_TEST:
+        s->timer_intr_test = val;
+        if (s->timer_intr_enable &
+            s->timer_intr_test &
+            R_INTR_ENABLE_IE_0_MASK) {
+            s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+            qemu_set_irq(s->irq, true);
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps ibex_timer_ops = {
+    .read = ibex_timer_read,
+    .write = ibex_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static int ibex_timer_post_load(void *opaque, int version_id)
+{
+    IbexTimerState *s = opaque;
+
+    ibex_timer_update_irqs(s);
+    return 0;
+}
+
+static const VMStateDescription vmstate_ibex_timer = {
+    .name = TYPE_IBEX_TIMER,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .post_load = ibex_timer_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(timer_ctrl, IbexTimerState),
+        VMSTATE_UINT32(timer_cfg0, IbexTimerState),
+        VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
+        VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
+        VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
+        VMSTATE_UINT32(timer_intr_state, IbexTimerState),
+        VMSTATE_UINT32(timer_intr_test, IbexTimerState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property ibex_timer_properties[] = {
+    DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ibex_timer_init(Object *obj)
+{
+    IbexTimerState *s = IBEX_TIMER(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
+                          TYPE_IBEX_TIMER, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ibex_timer_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = ibex_timer_reset;
+    dc->vmsd = &vmstate_ibex_timer;
+    device_class_set_props(dc, ibex_timer_properties);
+}
+
+static const TypeInfo ibex_timer_info = {
+    .name          = TYPE_IBEX_TIMER,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexTimerState),
+    .instance_init = ibex_timer_init,
+    .class_init    = ibex_timer_class_init,
+};
+
+static void ibex_timer_register_types(void)
+{
+    type_register_static(&ibex_timer_info);
+}
+
+type_init(ibex_timer_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alistair Francis <Alistair.Francis@wdc.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/opentitan.c
-F: hw/char/ibex_uart.c
-F: hw/intc/ibex_plic.c
+F: hw/*/ibex_*.c
 F: include/hw/riscv/opentitan.h
-F: include/hw/char/ibex_uart.h
-F: include/hw/intc/ibex_plic.h
+F: include/hw/*/ibex_*.h
 
 Microchip PolarFire SoC Icicle Kit
 M: Bin Meng <bin.meng@windriver.com>
diff --git a/hw/timer/meson.build b/hw/timer/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/meson.build
+++ b/hw/timer/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
 softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
 softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
+specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
 
 specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))
-- 
2.31.1

Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h |  5 ++++-
 hw/riscv/opentitan.c         | 14 +++++++++++---
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/intc/ibex_plic.h"
 #include "hw/char/ibex_uart.h"
+#include "hw/timer/ibex_timer.h"
 #include "qom/object.h"
 
 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
     RISCVHartArrayState cpus;
     IbexPlicState plic;
     IbexUartState uart;
+    IbexTimerState timer;
 
     MemoryRegion flash_mem;
     MemoryRegion rom;
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_DEV_SPI,
     IBEX_DEV_I2C,
     IBEX_DEV_PATTGEN,
-    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_TIMER,
     IBEX_DEV_SENSOR_CTRL,
     IBEX_DEV_OTP_CTRL,
     IBEX_DEV_PWRMGR,
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
+    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_SPI] =            {  0x40050000,  0x1000  },
     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
-    [IBEX_DEV_RV_TIMER] =       {  0x40100000,  0x1000  },
+    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
     [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
     object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
 
     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
+
+    object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
 }
 
 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                        3, qdev_get_gpio_in(DEVICE(&s->plic),
                        IBEX_UART0_RX_OVERFLOW_IRQ));
 
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
+                       0, qdev_get_gpio_in(DEVICE(&s->plic),
+                       IBEX_TIMER_TIMEREXPIRED0_0));
+
     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
     create_unimplemented_device("riscv.lowrisc.ibex.spi",
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
-        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
     create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
-- 
2.31.1