Series comparison

-[PULL 00/16] riscv-to-apply queue
+[PULL v2 00/19] riscv-to-apply queue
-The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
+The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd:
-  Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
+  Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03 12:47:58 +0000)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103
-for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
+for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870:
-  target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
+  target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03 07:17:23 -0800)
 ----------------------------------------------------------------
-RISC-V PR for 6.0
+This series adds support for migration to RISC-V QEMU and expands the
+Microchip PFSoC to allow unmodified HSS and Linux boots.
 This PR includes:
  - Fix for vector CSR access
  - Improvements to the Ibex UART device
  - PMP improvements and bug fixes
  - Hypervisor extension bug fixes
  - ramfb support for the virt machine
  - Fast read support for SST flash
  - Improvements to the microchip_pfsoc machine
 ----------------------------------------------------------------
-Alexander Wagner (1):
+Anup Patel (2):
-      hw/char: disable ibex uart receive if the buffer is full
+      hw/riscv: sifive_u: Allow passing custom DTB
       hw/riscv: virt: Allow passing custom DTB
-Asherah Connor (2):
+Bin Meng (10):
-      hw/riscv: Add fw_cfg support to virt
+      hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
-      hw/riscv: allow ramfb on virt
+      hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
       hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
       hw/misc: Add Microchip PolarFire SoC IOSCB module support
       hw/riscv: microchip_pfsoc: Connect the IOSCB module
       hw/misc: Add Microchip PolarFire SoC SYSREG module support
       hw/riscv: microchip_pfsoc: Connect the SYSREG module
       hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
       hw/riscv: microchip_pfsoc: Correct DDR memory map
       hw/riscv: microchip_pfsoc: Hook the I2C1 controller
-Bin Meng (3):
+Xinhao Zhang (1):
-      hw/block: m25p80: Support fast read for SST flashes
+      target/riscv/csr.c : add space before the open parenthesis '('
       hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
       docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
-Frank Chang (1):
+Yifei Jiang (6):
-      target/riscv: fix vs() to return proper error code
+      target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
       target/riscv: Add basic vmstate description of CPU
       target/riscv: Add PMP state description
       target/riscv: Add H extension state description
       target/riscv: Add V extension state description
       target/riscv: Add sifive_plic vmstate
-Georg Kotheimer (6):
+ include/hw/intc/sifive_plic.h       |   1 +
-      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+ include/hw/misc/mchp_pfsoc_dmc.h    |  56 +++++++++
-      target/riscv: Make VSTIP and VSEIP read-only in hip
+ include/hw/misc/mchp_pfsoc_ioscb.h  |  50 ++++++++
-      target/riscv: Use background registers also for MSTATUS_MPV
+ include/hw/misc/mchp_pfsoc_sysreg.h |  39 ++++++
-      target/riscv: Fix read and write accesses to vsip and vsie
+ include/hw/riscv/microchip_pfsoc.h  |  18 ++-
-      target/riscv: Add proper two-stage lookup exception detection
+ target/riscv/cpu.h                  |  24 ++--
-      target/riscv: Prevent lost illegal instruction exceptions
+ target/riscv/cpu_bits.h             |  19 +--
  target/riscv/internals.h            |   4 +
  target/riscv/pmp.h                  |   2 +
  hw/intc/sifive_plic.c               |  26 +++-
  hw/misc/mchp_pfsoc_dmc.c            | 216 ++++++++++++++++++++++++++++++++
  hw/misc/mchp_pfsoc_ioscb.c          | 242 ++++++++++++++++++++++++++++++++++++
  hw/misc/mchp_pfsoc_sysreg.c         |  99 +++++++++++++++
  hw/riscv/microchip_pfsoc.c          | 125 ++++++++++++++++---
  hw/riscv/sifive_u.c                 |  28 +++--
  hw/riscv/virt.c                     |  27 ++--
  target/riscv/cpu.c                  |  16 +--
  target/riscv/cpu_helper.c           |  35 ++----
  target/riscv/csr.c                  |  20 +--
  target/riscv/machine.c              | 196 +++++++++++++++++++++++++++++
  target/riscv/op_helper.c            |  11 +-
  target/riscv/pmp.c                  |  29 +++--
  MAINTAINERS                         |   6 +
  hw/misc/Kconfig                     |   9 ++
  hw/misc/meson.build                 |   3 +
  hw/riscv/Kconfig                    |   3 +
  target/riscv/meson.build            |   3 +-
 files changed, 1180 insertions(+), 127 deletions(-)
  create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
  create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
  create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
  create mode 100644 hw/misc/mchp_pfsoc_dmc.c
  create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
  create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
  create mode 100644 target/riscv/machine.c
-Jim Shu (3):
-      target/riscv: propagate PMP permission to TLB page
-      target/riscv: add log of PMP permission checking
-      target/riscv: flush TLB pages if PMP permission has been changed
- docs/system/riscv/microchip-icicle-kit.rst |  89 ++++++++++++++
- docs/system/target-riscv.rst               |   1 +
- include/hw/char/ibex_uart.h                |   4 +
- include/hw/riscv/microchip_pfsoc.h         |   1 +
- include/hw/riscv/virt.h                    |   2 +
- target/riscv/cpu.h                         |   4 +
- target/riscv/pmp.h                         |   4 +-
- hw/block/m25p80.c                          |   3 +
- hw/char/ibex_uart.c                        |  23 +++-
- hw/riscv/microchip_pfsoc.c                 |   6 +
- hw/riscv/virt.c                            |  33 ++++++
- target/riscv/cpu.c                         |   1 +
- target/riscv/cpu_helper.c                  | 144 +++++++++++++++--------
- target/riscv/csr.c                         |  77 +++++++------
- target/riscv/pmp.c                         |  84 ++++++++++----
- target/riscv/translate.c                   | 179 +----------------------------
- hw/riscv/Kconfig                           |   1 +
-files changed, 367 insertions(+), 289 deletions(-)
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

-[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
+[PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Anup Patel <anup.patel@wdc.com>
-According to the specification the "field SPVP of hstatus controls the
+Extend sifive_u machine to allow passing custom DTB using "-dtb"
-privilege level of the access" for the hypervisor virtual-machine load
+command-line parameter. This will help users pass modified DTB
-and store instructions HLV, HLVX and HSV.
+or Linux SiFive DTB to sifive_u machine.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Anup Patel <anup.patel@wdc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
+Message-id: 20201022053225.2596110-1-anup.patel@wdc.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
+ hw/riscv/sifive_u.c | 28 ++++++++++++++++++++--------
-file changed, 14 insertions(+), 11 deletions(-)
+file changed, 20 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/hw/riscv/sifive_u.c
-+++ b/target/riscv/cpu_helper.c
++++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
-         use_background = true;
+     int cpu;
      uint32_t *cells;
      char *nodename;
 +    const char *dtb_filename;
      char ethclk_names[] = "pclk\0hclk";
      uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
      uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 -    fdt = s->fdt = create_device_tree(&s->fdt_size);
 -    if (!fdt) {
 -        error_report("create_device_tree() failed");
 -        exit(1);
 +    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
 +    if (dtb_filename) {
 +        fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
 +        if (!fdt) {
 +            error_report("load_device_tree() failed");
 +            exit(1);
 +        }
 +        goto update_bootargs;
 +    } else {
 +        fdt = s->fdt = create_device_tree(&s->fdt_size);
 +        if (!fdt) {
 +            error_report("create_device_tree() failed");
 +            exit(1);
 +        }
      }
--    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
-+    /* MPRV does not affect the virtual-machine load/store
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
-+       instructions, HLV, HLVX, and HSV. */
-+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+     qemu_fdt_add_subnode(fdt, "/chosen");
-+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
-+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+-    if (cmdline) {
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
+-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
              mode = get_field(env->mstatus, MSTATUS_MPP);
          }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                    __func__, address, access_type, mmu_idx);
 -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 -        if (get_field(env->mstatus, MSTATUS_MPRV)) {
 -            mode = get_field(env->mstatus, MSTATUS_MPP);
 +    /* MPRV does not affect the virtual-machine load/store
 +       instructions, HLV, HLVX, and HSV. */
 +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
 +        mode = get_field(env->hstatus, HSTATUS_SPVP);
 +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
 +               get_field(env->mstatus, MSTATUS_MPRV)) {
 +        mode = get_field(env->mstatus, MSTATUS_MPP);
 +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
 +            two_stage_lookup = true;
          }
      }
 -    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
 -        access_type != MMU_INST_FETCH &&
 -        get_field(env->mstatus, MSTATUS_MPRV) &&
 -        get_field(env->mstatus, MSTATUS_MPV)) {
 -        two_stage_lookup = true;
 -    }
 -
-     if (riscv_cpu_virt_enabled(env) ||
+     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
-         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-          access_type != MMU_INST_FETCH)) {
+     g_free(nodename);
 +
 +update_bootargs:
 +    if (cmdline) {
 +        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 +    }
  }
  static void sifive_u_machine_reset(void *opaque, int n, int level)
 --
-.30.1
+.28.0

-[PULL 10/16] hw/riscv: allow ramfb on virt
+[PULL v2 02/19] hw/riscv: virt: Allow passing custom DTB
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Anup Patel <anup.patel@wdc.com>
-Allow ramfb on virt.  This lets `-device ramfb' work.
+Extend virt machine to allow passing custom DTB using "-dtb"
 command-line parameter. This will help users pass modified DTB
 to virt machine.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Signed-off-by: Anup Patel <anup.patel@wdc.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
+Message-id: 20201022053225.2596110-2-anup.patel@wdc.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 3 +++
+ hw/riscv/virt.c | 27 ++++++++++++++++++++-------
-file changed, 3 insertions(+)
+file changed, 20 insertions(+), 7 deletions(-)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
- #include "sysemu/sysemu.h"
+ {
- #include "hw/pci/pci.h"
+     void *fdt;
- #include "hw/pci-host/gpex.h"
+     int i, cpu, socket;
-+#include "hw/display/ramfb.h"
++    const char *dtb_filename;
+     MachineState *mc = MACHINE(s);
- static const MemMapEntry virt_memmap[] = {
+     uint64_t addr, size;
-     [VIRT_DEBUG] =       {        0x0,         0x100 },
+     uint32_t *clint_cells, *plic_cells;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
-     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
-     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
-     mc->numa_mem_supported = true;
 -    fdt = s->fdt = create_device_tree(&s->fdt_size);
 -    if (!fdt) {
 -        error_report("create_device_tree() failed");
 -        exit(1);
 +    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
 +    if (dtb_filename) {
 +        fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
 +        if (!fdt) {
 +            error_report("load_device_tree() failed");
 +            exit(1);
 +        }
 +        goto update_bootargs;
 +    } else {
 +        fdt = s->fdt = create_device_tree(&s->fdt_size);
 +        if (!fdt) {
 +            error_report("create_device_tree() failed");
 +            exit(1);
 +        }
      }
      qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
      qemu_fdt_add_subnode(fdt, "/chosen");
      qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
 -    if (cmdline) {
 -        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 -    }
      g_free(name);
      name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 , flashbase + flashsize, 2, flashsize);
      qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
      g_free(name);
 +
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
++update_bootargs:
 +    if (cmdline) {
 +        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 +    }
  }
- static const TypeInfo virt_machine_typeinfo = {
+ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 --
-.30.1
+.28.0

-[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
+[PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-The current two-stage lookup detection in riscv_cpu_do_interrupt falls
+mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
-short of its purpose, as all it checks is whether two-stage address
+This patch expands mstatus and vsstatus to uint64_t instead of
-translation either via the hypervisor-load store instructions or the
+target_ulong so that it can be saved as one unit and reduce some
-MPRV feature would be allowed.
+ifdefs in the code.
-What we really need instead is whether two-stage address translation was
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-active when the exception was raised. However, in riscv_cpu_do_interrupt
+Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
-we do not have the information to reliably detect this. Therefore, when
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 we raise a memory fault exception we have to record whether two-stage
 address translation is active.
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
+Message-id: 20201026115530.304-2-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  4 ++++
+ target/riscv/cpu.h        | 24 +++++++++++-------------
- target/riscv/cpu.c        |  1 +
+ target/riscv/cpu_bits.h   | 19 ++++---------------
- target/riscv/cpu_helper.c | 21 ++++++++-------------
+ target/riscv/cpu.c        |  8 +++++---
-files changed, 13 insertions(+), 13 deletions(-)
+ target/riscv/cpu_helper.c | 35 +++++++----------------------------
  target/riscv/csr.c        | 18 ++++++++++--------
  target/riscv/op_helper.c  | 11 ++++-------
 files changed, 41 insertions(+), 74 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
 @@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     target_ulong resetvec;
+     target_ulong mhartid;
+-    target_ulong mstatus;
++    /*
++     * For RV32 this is 32-bit mstatus and 32-bit mstatush.
++     * For RV64 this is a 64-bit mstatus.
++     */
++    uint64_t mstatus;
+     target_ulong mip;
+-#ifdef TARGET_RISCV32
+-    target_ulong mstatush;
+-#endif
+-
+     uint32_t miclaim;
+     target_ulong mie;
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     uint64_t htimedelta;
+     /* Virtual CSRs */
+-    target_ulong vsstatus;
++    /*
++     * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
++     * For RV64 this is a 64-bit vsstatus.
++     */
++    uint64_t vsstatus;
+     target_ulong vstvec;
+     target_ulong vsscratch;
+     target_ulong vsepc;
+     target_ulong vscause;
+     target_ulong vstval;
+     target_ulong vsatp;
+-#ifdef TARGET_RISCV32
+-    target_ulong vsstatush;
+-#endif
+     target_ulong mtval2;
+     target_ulong mtinst;
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+     target_ulong scause_hs;
+     target_ulong stval_hs;
      target_ulong satp_hs;
-     uint64_t mstatus_hs;
+-    target_ulong mstatus_hs;
+-#ifdef TARGET_RISCV32
-+    /* Signals whether the current exception occurred with two-stage address
+-    target_ulong mstatush_hs;
-+       translation active. */
+-#endif
-+    bool two_stage_lookup;
++    uint64_t mstatus_hs;
-+
      target_ulong scounteren;
      target_ulong mcounteren;
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
  #define TARGET_RISCV_CPU_BITS_H
  #define get_field(reg, mask) (((reg) & \
 -                 (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
 -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
 -                 (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
 -                 (target_ulong)(mask)))
 +                 (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
 +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
 +                 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
 +                 (uint64_t)(mask)))
  /* Floating point round mode */
  #define FSR_RD_SHIFT        5
@@ -XXX,XX +XXX,XX @@
  #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
  #define MSTATUS_TW          0x20000000 /* since: priv-1.10 */
  #define MSTATUS_TSR         0x40000000 /* since: priv-1.10 */
 -#if defined(TARGET_RISCV64)
  #define MSTATUS_GVA         0x4000000000ULL
  #define MSTATUS_MPV         0x8000000000ULL
 -#elif defined(TARGET_RISCV32)
 -#define MSTATUS_GVA         0x00000040
 -#define MSTATUS_MPV         0x00000080
 -#endif
 -
 -#ifdef TARGET_RISCV32
 -# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatush, MSTATUS_MPV)
 -#else
 -# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatus, MSTATUS_MPV)
 -#endif
  #define MSTATUS64_UXL       0x0000000300000000ULL
  #define MSTATUS64_SXL       0x0000000C00000000ULL
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
-     env->mcause = 0;
+ #ifndef CONFIG_USER_ONLY
-     env->pc = env->resetvec;
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-+    env->two_stage_lookup = false;
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 +    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
  #ifdef TARGET_RISCV32
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
 +    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 +                 (target_ulong)(env->mstatus >> 32));
  #endif
-     cs->exception_index = EXCP_NONE;
+     if (riscv_has_ext(env, RVH)) {
-     env->load_res = -1;
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
 +        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 +                     (target_ulong)env->vsstatus);
      }
      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
-         g_assert_not_reached();
-     }
+ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
-     env->badaddr = address;
+ {
-+    env->two_stage_lookup = two_stage;
+-    target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
 -                                MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
 +    uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
 +                            MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
 +                            MSTATUS64_UXL;
      bool current_virt = riscv_cpu_virt_enabled(env);
      g_assert(riscv_has_ext(env, RVH));
 -#if defined(TARGET_RISCV64)
 -    mstatus_mask |= MSTATUS64_UXL;
 -#endif
 -
      if (current_virt) {
          /* Current V=1 and we are about to change to V=0 */
          env->vsstatus = env->mstatus & mstatus_mask;
          env->mstatus &= ~mstatus_mask;
          env->mstatus |= env->mstatus_hs;
 -#if defined(TARGET_RISCV32)
 -        env->vsstatush = env->mstatush;
 -        env->mstatush |= env->mstatush_hs;
 -#endif
 -
          env->vstvec = env->stvec;
          env->stvec = env->stvec_hs;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
          env->mstatus &= ~mstatus_mask;
          env->mstatus |= env->vsstatus;
 -#if defined(TARGET_RISCV32)
 -        env->mstatush_hs = env->mstatush;
 -        env->mstatush |= env->vsstatush;
 -#endif
 -
          env->stvec_hs = env->stvec;
          env->stvec = env->vstvec;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
          access_type != MMU_INST_FETCH &&
          get_field(env->mstatus, MSTATUS_MPRV) &&
 -        MSTATUS_MPV_ISSET(env)) {
 +        get_field(env->mstatus, MSTATUS_MPV)) {
          riscv_cpu_set_two_stage_lookup(env, true);
      }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
          access_type != MMU_INST_FETCH &&
          get_field(env->mstatus, MSTATUS_MPRV) &&
 -        MSTATUS_MPV_ISSET(env)) {
 +        get_field(env->mstatus, MSTATUS_MPV)) {
          riscv_cpu_set_two_stage_lookup(env, false);
      }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      RISCVCPU *cpu = RISCV_CPU(cs);
      CPURISCVState *env = &cpu->env;
      bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
 -    target_ulong s;
 +    uint64_t s;
      /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
       * so we mask off the MSB and separate into trap type and cause.
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
              if (riscv_cpu_virt_enabled(env)) {
                  riscv_cpu_swap_hypervisor_regs(env);
              }
 -#ifdef TARGET_RISCV32
 -            env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
 -                                       riscv_cpu_virt_enabled(env));
 -            if (riscv_cpu_virt_enabled(env) && tval) {
 -                env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
 -            }
 -#else
              env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
 -                                      riscv_cpu_virt_enabled(env));
 +                                     riscv_cpu_virt_enabled(env));
              if (riscv_cpu_virt_enabled(env) && tval) {
                  env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
              }
 -#endif
              mtval2 = env->guest_phys_fault_addr;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
  static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    target_ulong mstatus = env->mstatus;
 -    target_ulong mask = 0;
 +    uint64_t mstatus = env->mstatus;
 +    uint64_t mask = 0;
      int dirty;
      /* flush tlb on mstatus fields that affect VM */
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
  #ifdef TARGET_RISCV32
  static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
  {
 -    *val = env->mstatush;
 +    *val = env->mstatus >> 32;
      return 0;
  }
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ {
-     }
+-    if ((val ^ env->mstatush) & (MSTATUS_MPV)) {
++    uint64_t valh = (uint64_t)val << 32;
-     env->badaddr = addr;
++    uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
++
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
++    if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
-     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
+         tlb_flush(env_cpu(env));
      }
 -    val &= MSTATUS_MPV | MSTATUS_GVA;
 -
 -    env->mstatush = val;
 +    env->mstatus = (env->mstatus & ~mask) | (valh & mask);
      return 0;
  }
+@@ -XXX,XX +XXX,XX @@ static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
-         g_assert_not_reached();
+ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
-     }
+ {
-     env->badaddr = addr;
+-    env->vsstatus = val;
-+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
++    uint64_t mask = (target_ulong)-1;
-+                            riscv_cpu_two_stage_lookup(mmu_idx);
++    env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
-     riscv_raise_exception(env, cs->exception_index, retaddr);
+     return 0;
  }
- #endif /* !CONFIG_USER_ONLY */
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-         /* handle the trap in S-mode */
+index XXXXXXX..XXXXXXX 100644
-         if (riscv_has_ext(env, RVH)) {
+--- a/target/riscv/op_helper.c
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
++++ b/target/riscv/op_helper.c
--            bool two_stage_lookup = false;
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
--            if (env->priv == PRV_M ||
+ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
--                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ {
--                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+-    target_ulong prev_priv, prev_virt, mstatus;
--                    get_field(env->hstatus, HSTATUS_HU))) {
++    uint64_t mstatus;
--                    two_stage_lookup = true;
++    target_ulong prev_priv, prev_virt;
--            }
--
+     if (!(env->priv >= PRV_S)) {
--            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+            if (env->two_stage_lookup && write_tval) {
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
-                 /*
+         riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
-                  * If we are writing a guest virtual address to stval, set
+     }
-                  * this to 1. If we are trapping to VS we will set this to 0
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+-    target_ulong mstatus = env->mstatus;
-                 riscv_cpu_set_force_hs_excep(env, 0);
++    uint64_t mstatus = env->mstatus;
-             } else {
+     target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
-                 /* Trap into HS mode */
+-    target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
--                if (!two_stage_lookup) {
++    target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
--                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+     mstatus = set_field(mstatus, MSTATUS_MIE,
--                                             riscv_cpu_virt_enabled(env));
+                         get_field(mstatus, MSTATUS_MPIE));
--                }
+     mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
+     mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
-                 htval = env->guest_phys_fault_addr;
+-#ifdef TARGET_RISCV32
-             }
+-    env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
-         }
+-#else
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+     mstatus = set_field(mstatus, MSTATUS_MPV, 0);
-      * RISC-V ISA Specification.
+-#endif
-      */
+     env->mstatus = mstatus;
+     riscv_cpu_set_mode(env, prev_priv);
-+    env->two_stage_lookup = false;
  #endif
      cs->exception_index = EXCP_NONE; /* mark handled to qemu */
  }
 --
-.30.1
+.28.0

-[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
+[PULL v2 04/19] target/riscv: Add basic vmstate description of CPU
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Add basic CPU state description to the newly created machine.c
 Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
+Message-id: 20201026115530.304-3-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 7 ++++---
+ target/riscv/internals.h |  4 +++
-file changed, 4 insertions(+), 3 deletions(-)
+ target/riscv/cpu.c       |  8 +----
  target/riscv/machine.c   | 74 ++++++++++++++++++++++++++++++++++++++++
  target/riscv/meson.build |  3 +-
 files changed, 81 insertions(+), 8 deletions(-)
  create mode 100644 target/riscv/machine.c
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/internals.h b/target/riscv/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/internals.h
-+++ b/target/riscv/csr.c
++++ b/target/riscv/internals.h
-@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
+@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1);
-     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
+ #define SEW32 2
-     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ #define SEW64 3
- static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
--static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
++#ifndef CONFIG_USER_ONLY
-+static const target_ulong hip_writable_mask = MIP_VSSIP;
++extern const VMStateDescription vmstate_riscv_cpu;
-+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
++#endif
- static const target_ulong vsip_writable_mask = MIP_VSSIP;
++
+ static inline uint64_t nanbox_s(float32 f)
  static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+     return f | MAKE_64BIT_MASK(32, 32);
--                      write_mask & hip_writable_mask);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-+                      write_mask & hvip_writable_mask);
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
--    *ret_value &= hip_writable_mask;
++++ b/target/riscv/cpu.c
-+    *ret_value &= hvip_writable_mask;
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/ctype.h"
-     return ret;
+ #include "qemu/log.h"
  #include "cpu.h"
 +#include "internals.h"
  #include "exec/exec-all.h"
  #include "qapi/error.h"
  #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
      cpu_set_cpustate_pointers(cpu);
  }
+-#ifndef CONFIG_USER_ONLY
+-static const VMStateDescription vmstate_riscv_cpu = {
+-    .name = "cpu",
+-    .unmigratable = 1,
+-};
+-#endif
+-
+ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
+     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/target/riscv/machine.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * RISC-V VMState Description
++ *
++ * Copyright (c) 2020 Huawei Technologies Co., Ltd
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2 or later, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "qemu/osdep.h"
++#include "cpu.h"
++#include "qemu/error-report.h"
++#include "sysemu/kvm.h"
++#include "migration/cpu.h"
++
++const VMStateDescription vmstate_riscv_cpu = {
++    .name = "cpu",
++    .version_id = 1,
++    .minimum_version_id = 1,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
++        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
++        VMSTATE_UINTTL(env.pc, RISCVCPU),
++        VMSTATE_UINTTL(env.load_res, RISCVCPU),
++        VMSTATE_UINTTL(env.load_val, RISCVCPU),
++        VMSTATE_UINTTL(env.frm, RISCVCPU),
++        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
++        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
++        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
++        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
++        VMSTATE_UINTTL(env.misa, RISCVCPU),
++        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
++        VMSTATE_UINT32(env.features, RISCVCPU),
++        VMSTATE_UINTTL(env.priv, RISCVCPU),
++        VMSTATE_UINTTL(env.virt, RISCVCPU),
++        VMSTATE_UINTTL(env.resetvec, RISCVCPU),
++        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
++        VMSTATE_UINT64(env.mstatus, RISCVCPU),
++        VMSTATE_UINTTL(env.mip, RISCVCPU),
++        VMSTATE_UINT32(env.miclaim, RISCVCPU),
++        VMSTATE_UINTTL(env.mie, RISCVCPU),
++        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
++        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
++        VMSTATE_UINTTL(env.satp, RISCVCPU),
++        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
++        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
++        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
++        VMSTATE_UINTTL(env.stvec, RISCVCPU),
++        VMSTATE_UINTTL(env.sepc, RISCVCPU),
++        VMSTATE_UINTTL(env.scause, RISCVCPU),
++        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
++        VMSTATE_UINTTL(env.mepc, RISCVCPU),
++        VMSTATE_UINTTL(env.mcause, RISCVCPU),
++        VMSTATE_UINTTL(env.mtval, RISCVCPU),
++        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
++        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
++        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
++        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
++        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
++        VMSTATE_UINT64(env.mtohost, RISCVCPU),
++        VMSTATE_UINT64(env.timecmp, RISCVCPU),
++
++        VMSTATE_END_OF_LIST()
++    }
++};
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+ riscv_softmmu_ss = ss.source_set()
+ riscv_softmmu_ss.add(files(
+   'pmp.c',
+-  'monitor.c'
++  'monitor.c',
++  'machine.c'
+ ))
+ target_arch += {'riscv': riscv_ss}
 --
-.30.1
+.28.0

-[PULL 03/16] target/riscv: propagate PMP permission to TLB page
+[PULL v2 05/19] target/riscv: Add PMP state description
-From: Jim Shu <cwshu@andestech.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-Currently, PMP permission checking of TLB page is bypassed if TLB hits
+In the case of supporting PMP feature, add PMP state description
-Fix it by propagating PMP permission to TLB page permission.
+to vmstate_riscv_cpu.
-PMP permission checking also use MMU-style API to change TLB permission
+'vmstate_pmp_addr' and 'num_rules' could be regenerated by
-and size.
+pmp_update_rule(). But there exists the problem of updating
 num_rules repeatedly in pmp_update_rule(). So here extracts
 pmp_update_rule_addr() and pmp_update_rule_nums() to update
 'vmstate_pmp_addr' and 'num_rules' respectively.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
+Message-id: 20201026115530.304-4-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.h        |  4 +-
+ target/riscv/pmp.h     |  2 ++
- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
+ target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++
- target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
+ target/riscv/pmp.c     | 29 ++++++++++++++----------
-files changed, 125 insertions(+), 43 deletions(-)
+files changed, 70 insertions(+), 11 deletions(-)
 diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.h
 +++ b/target/riscv/pmp.h
-@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
+@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-     target_ulong val);
+     target_ulong size, pmp_priv_t priv, target_ulong mode);
  target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t priv, target_ulong mode);
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode);
  bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                           target_ulong *tlb_size);
- void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
++void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
- void pmp_update_rule_nums(CPURISCVState *env);
++void pmp_update_rule_nums(CPURISCVState *env);
  uint32_t pmp_get_num_rules(CPURISCVState *env);
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
  #endif
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/machine.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/machine.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
+@@ -XXX,XX +XXX,XX @@
-     env->load_res = -1;
+ #include "sysemu/kvm.h"
- }
+ #include "migration/cpu.h"
-+/*
++static bool pmp_needed(void *opaque)
 + * get_physical_address_pmp - check PMP permission for this physical address
 + *
 + * Match the PMP region and check permission for this physical address and it's
 + * TLB page. Returns 0 if the permission checking was successful
 + *
 + * @env: CPURISCVState
 + * @prot: The returned protection attributes
 + * @tlb_size: TLB page size containing addr. It could be modified after PMP
 + *            permission checking. NULL if not set TLB page for addr.
 + * @addr: The physical address to be checked permission
 + * @access_type: The type of MMU access
 + * @mode: Indicates current privilege level.
 + */
 +static int get_physical_address_pmp(CPURISCVState *env, int *prot,
 +                                    target_ulong *tlb_size, hwaddr addr,
 +                                    int size, MMUAccessType access_type,
 +                                    int mode)
 +{
-+    pmp_priv_t pmp_priv;
++    RISCVCPU *cpu = opaque;
-+    target_ulong tlb_size_pmp = 0;
++    CPURISCVState *env = &cpu->env;
 +
-+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
++    return riscv_feature(env, RISCV_FEATURE_PMP);
 +        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +        return TRANSLATE_SUCCESS;
 +    }
 +
 +    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 +                            mode)) {
 +        *prot = 0;
 +        return TRANSLATE_PMP_FAIL;
 +    }
 +
 +    *prot = pmp_priv_to_page_prot(pmp_priv);
 +    if (tlb_size != NULL) {
 +        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 +            *tlb_size = tlb_size_pmp;
 +        }
 +    }
 +
 +    return TRANSLATE_SUCCESS;
 +}
 +
- /* get_physical_address - get the physical address for this virtual address
++static int pmp_post_load(void *opaque, int version_id)
-  *
++{
-  * Do a page table walk to obtain the physical address corresponding to a
++    RISCVCPU *cpu = opaque;
-@@ -XXX,XX +XXX,XX @@ restart:
++    CPURISCVState *env = &cpu->env;
-             pte_addr = base + idx * ptesize;
++    int i;
-         }
++
++    for (i = 0; i < MAX_RISCV_PMPS; i++) {
--        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
++        pmp_update_rule_addr(env, i);
--            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
++    }
--            1 << MMU_DATA_LOAD, PRV_S)) {
++    pmp_update_rule_nums(env);
-+        int pmp_prot;
++
-+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
++    return 0;
-+                                               sizeof(target_ulong),
++}
-+                                               MMU_DATA_LOAD, PRV_S);
++
-+        if (pmp_ret != TRANSLATE_SUCCESS) {
++static const VMStateDescription vmstate_pmp_entry = {
-             return TRANSLATE_PMP_FAIL;
++    .name = "cpu/pmp/entry",
-         }
++    .version_id = 1,
++    .minimum_version_id = 1,
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++    .fields = (VMStateField[]) {
- #ifndef CONFIG_USER_ONLY
++        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
-     vaddr im_address;
++        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
-     hwaddr pa = 0;
++        VMSTATE_END_OF_LIST()
--    int prot, prot2;
++    }
-+    int prot, prot2, prot_pmp;
++};
-     bool pmp_violation = false;
++
-     bool first_stage_error = true;
++static const VMStateDescription vmstate_pmp = {
-     bool two_stage_lookup = false;
++    .name = "cpu/pmp",
-     int ret = TRANSLATE_FAIL;
++    .version_id = 1,
-     int mode = mmu_idx;
++    .minimum_version_id = 1,
--    target_ulong tlb_size = 0;
++    .needed = pmp_needed,
-+    /* default TLB page size */
++    .post_load = pmp_post_load,
-+    target_ulong tlb_size = TARGET_PAGE_SIZE;
++    .fields = (VMStateField[]) {
++        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
-     env->guest_phys_fault_addr = 0;
++                             0, vmstate_pmp_entry, pmp_entry_t),
++        VMSTATE_END_OF_LIST()
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++    }
++};
-             prot &= prot2;
++
+ const VMStateDescription vmstate_riscv_cpu = {
--            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+     .name = "cpu",
--                (ret == TRANSLATE_SUCCESS) &&
+     .version_id = 1,
--                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
+@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
--                ret = TRANSLATE_PMP_FAIL;
+         VMSTATE_UINT64(env.timecmp, RISCVCPU),
-+            if (ret == TRANSLATE_SUCCESS) {
-+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+         VMSTATE_END_OF_LIST()
-+                                               size, access_type, mode);
++    },
-+                prot &= prot_pmp;
++    .subsections = (const VMStateDescription * []) {
-             }
++        &vmstate_pmp,
++        NULL
              if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        "%s address=%" VADDR_PRIx " ret %d physical "
                        TARGET_FMT_plx " prot %d\n",
                        __func__, address, ret, pa, prot);
 -    }
 -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 -        (ret == TRANSLATE_SUCCESS) &&
 -        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 -        ret = TRANSLATE_PMP_FAIL;
 +        if (ret == TRANSLATE_SUCCESS) {
 +            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
 +                                           size, access_type, mode);
 +            prot &= prot_pmp;
 +        }
      }
-+
+ };
      if (ret == TRANSLATE_PMP_FAIL) {
          pmp_violation = true;
      }
      if (ret == TRANSLATE_SUCCESS) {
 -        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
 -            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 -                         prot, mmu_idx, tlb_size);
 -        } else {
 -            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 -                         prot, mmu_idx, TARGET_PAGE_SIZE);
 -        }
 +        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 +                     prot, mmu_idx, tlb_size);
          return true;
      } else if (probe) {
          return false;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
+@@ -XXX,XX +XXX,XX @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
-     return result;
+     }
  }
-+/*
+-
-+ * Check if the address has required RWX privs when no PMP entry is matched.
+-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
 - *   end address values.
 - *   This function is called relatively infrequently whereas the check that
 - *   an address is within a pmp rule is called often, so optimise that one
 - */
 -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
 +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
  {
 -    int i;
 -
 -    env->pmp_state.num_rules = 0;
 -
      uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
      target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
      target_ulong prev_addr = 0u;
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
      env->pmp_state.addr[pmp_index].sa = sa;
      env->pmp_state.addr[pmp_index].ea = ea;
 +}
 +void pmp_update_rule_nums(CPURISCVState *env)
 +{
 +    int i;
 +
 +    env->pmp_state.num_rules = 0;
      for (i = 0; i < MAX_RISCV_PMPS; i++) {
          const uint8_t a_field =
              pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
      }
  }
 +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
 + *   end address values.
 + *   This function is called relatively infrequently whereas the check that
 + *   an address is within a pmp rule is called often, so optimise that one
 + */
-+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
++static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
 +{
-+    bool ret;
++    pmp_update_rule_addr(env, pmp_index);
-+
++    pmp_update_rule_nums(env);
 +    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
 +        /*
 +         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
 +         * or no PMP entry matches an M-Mode access, the access succeeds.
 +         */
 +        ret = true;
 +        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +    } else {
 +        /*
 +         * Other modes are not allowed to succeed if they don't * match a rule,
 +         * but there are rules. We've checked for no rule earlier in this
 +         * function.
 +         */
 +        ret = false;
 +        *allowed_privs = 0;
 +    }
 +
 +    return ret;
 +}
 +
+ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  /*
   * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
   * Check if the address has required RWX privs to complete desired operation
   */
  bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 -    target_ulong size, pmp_priv_t privs, target_ulong mode)
 +    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
 +    target_ulong mode)
  {
-     int i = 0;
+     int result = 0;
      int ret = -1;
      int pmp_size = 0;
      target_ulong s = 0;
      target_ulong e = 0;
 -    pmp_priv_t allowed_privs = 0;
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return (env->priv == PRV_M) ? true : false;
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
           * check
           */
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
              if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
              }
 -            if ((privs & allowed_privs) == privs) {
 -                ret = 1;
 -                break;
 -            } else {
 -                ret = 0;
 -                break;
 -            }
 +            ret = ((privs & *allowed_privs) == privs);
 +            break;
          }
      }
      /* No rule matched */
      if (ret == -1) {
 -        if (mode == PRV_M) {
 -            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 -                      * M-Mode access, the access succeeds */
 -        } else {
 -            ret = 0; /* Other modes are not allowed to succeed if they don't
 -                      * match a rule, but there are rules.  We've checked for
 -                      * no rule earlier in this function. */
 -        }
 +        return pmp_hart_has_privs_default(env, addr, size, privs,
 +                                          allowed_privs, mode);
      }
      return ret == 1 ? true : false;
  }
 -
  /*
   * Handle a write to a pmpcfg CSP
   */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
      return false;
  }
 +
 +/*
 + * Convert PMP privilege to TLB page privilege.
 + */
 +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
 +{
 +    int prot = 0;
 +
 +    if (pmp_priv & PMP_READ) {
 +        prot |= PAGE_READ;
 +    }
 +    if (pmp_priv & PMP_WRITE) {
 +        prot |= PAGE_WRITE;
 +    }
 +    if (pmp_priv & PMP_EXEC) {
 +        prot |= PAGE_EXEC;
 +    }
 +
 +    return prot;
 +}
 --
-.30.1
+.28.0

-New patch
+[PULL v2 06/19] target/riscv: Add H extension state description
+From: Yifei Jiang <jiangyifei@huawei.com>
+In the case of supporting H extension, add H extension description
+to vmstate_riscv_cpu.
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20201026115530.304-5-jiangyifei@huawei.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++
+file changed, 47 insertions(+)
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/machine.c
++++ b/target/riscv/machine.c
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmp = {
+     }
+ };
++static bool hyper_needed(void *opaque)
++{
++    RISCVCPU *cpu = opaque;
++    CPURISCVState *env = &cpu->env;
++
++    return riscv_has_ext(env, RVH);
++}
++
++static const VMStateDescription vmstate_hyper = {
++    .name = "cpu/hyper",
++    .version_id = 1,
++    .minimum_version_id = 1,
++    .needed = hyper_needed,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
++        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
++        VMSTATE_UINTTL(env.hideleg, RISCVCPU),
++        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
++        VMSTATE_UINTTL(env.htval, RISCVCPU),
++        VMSTATE_UINTTL(env.htinst, RISCVCPU),
++        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
++        VMSTATE_UINT64(env.htimedelta, RISCVCPU),
++
++        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
++        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
++        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
++        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
++        VMSTATE_UINTTL(env.vscause, RISCVCPU),
++        VMSTATE_UINTTL(env.vstval, RISCVCPU),
++        VMSTATE_UINTTL(env.vsatp, RISCVCPU),
++
++        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
++        VMSTATE_UINTTL(env.mtinst, RISCVCPU),
++
++        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
++        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
++        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
++        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
++        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
++        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
++        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
++
++        VMSTATE_END_OF_LIST()
++    }
++};
++
+ const VMStateDescription vmstate_riscv_cpu = {
+     .name = "cpu",
+     .version_id = 1,
+@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
+     },
+     .subsections = (const VMStateDescription * []) {
+         &vmstate_pmp,
++        &vmstate_hyper,
+         NULL
+     }
+ };
+--
+.28.0

-[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
+[PULL v2 07/19] target/riscv: Add V extension state description
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-The previous implementation was broken in many ways:
+In the case of supporting V extension, add V extension description
- - Used mideleg instead of hideleg to mask accesses
+to vmstate_riscv_cpu.
  - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
  - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
+Message-id: 20201026115530.304-6-jiangyifei@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
+ target/riscv/machine.c | 25 +++++++++++++++++++++++++
-file changed, 34 insertions(+), 34 deletions(-)
+file changed, 25 insertions(+)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/machine.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/machine.c
-@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
-     return write_mstatus(env, CSR_MSTATUS, newval);
+     return riscv_has_ext(env, RVH);
  }
-+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
++static bool vector_needed(void *opaque)
 +{
-+    /* Shift the VS bits to their S bit location in vsie */
++    RISCVCPU *cpu = opaque;
-+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
++    CPURISCVState *env = &cpu->env;
-+    return 0;
++
 +    return riscv_has_ext(env, RVV);
 +}
 +
- static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
++static const VMStateDescription vmstate_vector = {
- {
++    .name = "cpu/vector",
-     if (riscv_cpu_virt_enabled(env)) {
++    .version_id = 1,
--        /* Tell the guest the VS bits, shifted to the S bit locations */
++    .minimum_version_id = 1,
--        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
++    .needed = vector_needed,
-+        read_vsie(env, CSR_VSIE, val);
++    .fields = (VMStateField[]) {
-     } else {
++            VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
-         *val = env->mie & env->mideleg;
++            VMSTATE_UINTTL(env.vxrm, RISCVCPU),
 +            VMSTATE_UINTTL(env.vxsat, RISCVCPU),
 +            VMSTATE_UINTTL(env.vl, RISCVCPU),
 +            VMSTATE_UINTTL(env.vstart, RISCVCPU),
 +            VMSTATE_UINTTL(env.vtype, RISCVCPU),
 +            VMSTATE_END_OF_LIST()
 +        }
 +};
 +
  static const VMStateDescription vmstate_hyper = {
      .name = "cpu/hyper",
      .version_id = 1,
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
      .subsections = (const VMStateDescription * []) {
          &vmstate_pmp,
          &vmstate_hyper,
 +        &vmstate_vector,
          NULL
      }
-     return 0;
+ };
  }
 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    target_ulong newval;
 +    /* Shift the S bits to their VS bit location in mie */
 +    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 +                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 +    return write_mie(env, CSR_MIE, newval);
 +}
 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 +{
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the guests S bits to VS */
 -        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 -                 ((val << 1) & VS_MODE_INTERRUPTS);
 +        write_vsie(env, CSR_VSIE, val);
      } else {
 -        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 +        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 +                              (val & S_MODE_INTERRUPTS);
 +        write_mie(env, CSR_MIE, newval);
      }
 -    return write_mie(env, CSR_MIE, newval);
 +    return 0;
  }
  static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +                    target_ulong new_value, target_ulong write_mask)
 +{
 +    /* Shift the S bits to their VS bit location in mip */
 +    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 +                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
 +    *ret_value &= VS_MODE_INTERRUPTS;
 +    /* Shift the VS bits to their S bit location in vsip */
 +    *ret_value >>= 1;
 +    return ret;
 +}
 +
  static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                     target_ulong new_value, target_ulong write_mask)
  {
      int ret;
      if (riscv_cpu_virt_enabled(env)) {
 -        /* Shift the new values to line up with the VS bits */
 -        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 -                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
 -        ret &= vsip_writable_mask;
 -        ret >>= 1;
 +        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
      } else {
          ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                        write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                    target_ulong new_value, target_ulong write_mask)
 -{
 -    int ret = rmw_mip(env, 0, ret_value, new_value,
 -                      write_mask & env->mideleg & vsip_writable_mask);
 -    return ret;
 -}
 -
 -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
 -{
 -    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
 -    return 0;
 -}
 -
 -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 -{
 -    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
 -    return write_mie(env, CSR_MIE, newval);
 -}
 -
  static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
  {
      *val = env->vstvec;
 --
-.30.1
+.28.0

-[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
+[PULL v2 08/19] target/riscv: Add sifive_plic vmstate
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Yifei Jiang <jiangyifei@huawei.com>
-When decode_insn16() fails, we fall back to decode_RV32_64C() for
+Add sifive_plic vmstate for supporting sifive_plic migration.
-further compressed instruction decoding. However, prior to this change,
+Current vmstate framework only supports one structure parameter
-we did not raise an illegal instruction exception, if decode_RV32_64C()
+as num field to describe variable length arrays, so introduce
-fails to decode the instruction. This means that we skipped illegal
+num_enables.
 compressed instructions instead of raising an illegal instruction
 exception.
-Instead of patching decode_RV32_64C(), we can just remove it,
+Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
-as it is dead code since f330433b363 anyway.
+Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
 Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201026115530.304-7-jiangyifei@huawei.com
 Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 179 +--------------------------------------
+ include/hw/intc/sifive_plic.h |  1 +
-file changed, 1 insertion(+), 178 deletions(-)
+ hw/intc/sifive_plic.c         | 26 +++++++++++++++++++++++++-
 files changed, 26 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/include/hw/intc/sifive_plic.h
-+++ b/target/riscv/translate.c
++++ b/include/hw/intc/sifive_plic.h
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ struct SiFivePLICState {
-     CPUState *cs;
+     uint32_t num_addrs;
- } DisasContext;
+     uint32_t num_harts;
+     uint32_t bitfield_words;
--#ifdef TARGET_RISCV64
++    uint32_t num_enables;
--/* convert riscv funct3 to qemu memop for load/store */
+     PLICAddr *addr_config;
--static const int tcg_memop_lookup[8] = {
+     uint32_t *source_priority;
--    [0 ... 7] = -1,
+     uint32_t *target_priority;
--    [0] = MO_SB,
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
--    [1] = MO_TESW,
+index XXXXXXX..XXXXXXX 100644
--    [2] = MO_TESL,
+--- a/hw/intc/sifive_plic.c
--    [3] = MO_TEQ,
++++ b/hw/intc/sifive_plic.c
--    [4] = MO_UB,
+@@ -XXX,XX +XXX,XX @@
--    [5] = MO_TEUW,
+ #include "hw/intc/sifive_plic.h"
--    [6] = MO_TEUL,
+ #include "target/riscv/cpu.h"
--};
+ #include "sysemu/sysemu.h"
--#endif
++#include "migration/vmstate.h"
--
- #ifdef TARGET_RISCV64
+ #define RISCV_DEBUG_PLIC 0
- #define CASE_OP_32_64(X) case X: case glue(X, W)
- #else
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+                           TYPE_SIFIVE_PLIC, plic->aperture_size);
-     ctx->base.is_jmp = DISAS_NORETURN;
+     parse_hart_config(plic);
      plic->bitfield_words = (plic->num_sources + 31) >> 5;
 +    plic->num_enables = plic->bitfield_words * plic->num_addrs;
      plic->source_priority = g_new0(uint32_t, plic->num_sources);
      plic->target_priority = g_new(uint32_t, plic->num_addrs);
      plic->pending = g_new0(uint32_t, plic->bitfield_words);
      plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 -    plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 +    plic->enable = g_new0(uint32_t, plic->num_enables);
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
      qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
      msi_nonbroken = true;
  }
--#ifdef TARGET_RISCV64
++static const VMStateDescription vmstate_sifive_plic = {
--static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
++    .name = "riscv_sifive_plic",
--        target_long imm)
++    .version_id = 1,
--{
++    .minimum_version_id = 1,
--    TCGv t0 = tcg_temp_new();
++    .fields = (VMStateField[]) {
--    TCGv t1 = tcg_temp_new();
++            VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
--    gen_get_gpr(t0, rs1);
++                                  num_sources, 0,
--    tcg_gen_addi_tl(t0, t0, imm);
++                                  vmstate_info_uint32, uint32_t),
--    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
++            VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
--
++                                  num_addrs, 0,
--    if (memop < 0) {
++                                  vmstate_info_uint32, uint32_t),
--        gen_exception_illegal(ctx);
++            VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
--        return;
++                                  vmstate_info_uint32, uint32_t),
--    }
++            VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
--
++                                  vmstate_info_uint32, uint32_t),
--    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
++            VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
--    gen_set_gpr(rd, t1);
++                                  vmstate_info_uint32, uint32_t),
--    tcg_temp_free(t0);
++            VMSTATE_END_OF_LIST()
--    tcg_temp_free(t1);
++        }
--}
++};
--
++
--static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+ static void sifive_plic_class_init(ObjectClass *klass, void *data)
 -        target_long imm)
 -{
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -    gen_get_gpr(dat, rs2);
 -    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
 -
 -    if (memop < 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -}
 -#endif
 -
  #ifndef CONFIG_USER_ONLY
  /* The states of mstatus_fs are:
   * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
  static inline void mark_fs_dirty(DisasContext *ctx) { }
  #endif
 -#if !defined(TARGET_RISCV64)
 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
 -        int rs1, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FLW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
 -        /* RISC-V requires NaN-boxing of narrower width floating point values */
 -        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
 -        break;
 -    case OPC_RISC_FLD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -    tcg_temp_free(t0);
 -
 -    mark_fs_dirty(ctx);
 -}
 -
 -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
 -        int rs2, target_long imm)
 -{
 -    TCGv t0;
 -
 -    if (ctx->mstatus_fs == 0) {
 -        gen_exception_illegal(ctx);
 -        return;
 -    }
 -
 -    t0 = tcg_temp_new();
 -    gen_get_gpr(t0, rs1);
 -    tcg_gen_addi_tl(t0, t0, imm);
 -
 -    switch (opc) {
 -    case OPC_RISC_FSW:
 -        if (!has_ext(ctx, RVF)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
 -        break;
 -    case OPC_RISC_FSD:
 -        if (!has_ext(ctx, RVD)) {
 -            goto do_illegal;
 -        }
 -        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
 -        break;
 -    do_illegal:
 -    default:
 -        gen_exception_illegal(ctx);
 -        break;
 -    }
 -
 -    tcg_temp_free(t0);
 -}
 -#endif
 -
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
-     TCGv_i32 t0;
+     DeviceClass *dc = DEVICE_CLASS(klass);
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
-     tcg_temp_free_i32(t0);
+     device_class_set_props(dc, sifive_plic_properties);
      dc->realize = sifive_plic_realize;
 +    dc->vmsd = &vmstate_sifive_plic;
  }
--static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
+ static const TypeInfo sifive_plic_info = {
 -{
 -    uint8_t funct3 = extract16(opcode, 13, 3);
 -    uint8_t rd_rs2 = GET_C_RS2S(opcode);
 -    uint8_t rs1s = GET_C_RS1S(opcode);
 -
 -    switch (funct3) {
 -    case 3:
 -#if defined(TARGET_RISCV64)
 -        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
 -        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
 -                 GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
 -        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
 -                    GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    case 7:
 -#if defined(TARGET_RISCV64)
 -        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
 -        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
 -                  GET_C_LD_IMM(opcode));
 -#else
 -        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
 -        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
 -                     GET_C_LW_IMM(opcode));
 -#endif
 -        break;
 -    }
 -}
 -
 -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
 -{
 -    uint8_t op = extract16(opcode, 0, 2);
 -
 -    switch (op) {
 -    case 0:
 -        decode_RV32_64C0(ctx, opcode);
 -        break;
 -    }
 -}
 -
  static int ex_plus_1(DisasContext *ctx, int nf)
  {
      return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          } else {
              ctx->pc_succ_insn = ctx->base.pc_next + 2;
              if (!decode_insn16(ctx, opcode)) {
 -                /* fall back to old decoder */
 -                decode_RV32_64C(ctx, opcode);
 +                gen_exception_illegal(ctx);
              }
          }
      } else {
 --
-.30.1
+.28.0

-[PULL 04/16] target/riscv: add log of PMP permission checking
+[PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
-From: Jim Shu <cwshu@andestech.com>
+From: Bin Meng <bin.meng@windriver.com>
-Like MMU translation, add qemu log of PMP permission checking for
+It is not easy to find out the memory map for a specific component
-debugging.
+in the PolarFire SoC as the information is scattered in different
 documents. Add some comments so that people can know where to get
 such information from the Microchip website.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
+Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++++++++
+ hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
-file changed, 12 insertions(+)
+file changed, 18 insertions(+)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/hw/riscv/microchip_pfsoc.c
-+++ b/target/riscv/cpu_helper.c
++++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+@@ -XXX,XX +XXX,XX @@
-             if (ret == TRANSLATE_SUCCESS) {
+ /* GEM version */
-                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ #define GEM_REVISION    0x0107010c
-                                                size, access_type, mode);
-+
++/*
-+                qemu_log_mask(CPU_LOG_MMU,
++ * The complete description of the whole PolarFire SoC memory map is scattered
-+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
++ * in different documents. There are several places to look at for memory maps:
-+                              " %d tlb_size " TARGET_FMT_lu "\n",
++ *
-+                              __func__, pa, ret, prot_pmp, tlb_size);
++ * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
-+
++ *   Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
-                 prot &= prot_pmp;
++ *   https://www.microsemi.com/document-portal/doc_download/
-             }
++ *   1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
++ *   describes the whole picture of the PolarFire SoC memory map.
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++ *
-         if (ret == TRANSLATE_SUCCESS) {
++ * 2 A zip file for PolarFire soC memory map, which can be downloaded from
-             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
++ *   https://www.microsemi.com/document-portal/doc_download/
-                                            size, access_type, mode);
++ *   1244581-polarfire-soc-register-map, contains the following 2 major parts:
-+
++ *   - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
-+            qemu_log_mask(CPU_LOG_MMU,
++ *     describes the complete integrated peripherals memory map
-+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
++ *   - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
-+                          " %d tlb_size " TARGET_FMT_lu "\n",
++ *     describes the complete IOSCB modules memory maps
-+                          __func__, pa, ret, prot_pmp, tlb_size);
++ */
-+
+ static const struct MemmapEntry {
-             prot &= prot_pmp;
+     hwaddr base;
-         }
+     hwaddr size;
      }
 --
-.30.1
+.28.0

-New patch
+[PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
+From: Bin Meng <bin.meng@windriver.com>
 The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
 called SGMII PHY module and the CFG module, as documented in the
 chipset datasheet.
 This creates a single file that groups these 2 modules, providing
 the minimum functionalities that make the HSS DDR initialization
 codes happy.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/misc/mchp_pfsoc_dmc.h |  56 ++++++++
  hw/misc/mchp_pfsoc_dmc.c         | 216 +++++++++++++++++++++++++++++++
  MAINTAINERS                      |   2 +
  hw/misc/Kconfig                  |   3 +
  hw/misc/meson.build              |   1 +
 files changed, 278 insertions(+)
  create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
  create mode 100644 hw/misc/mchp_pfsoc_dmc.c
 diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/mchp_pfsoc_dmc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC DDR Memory Controller module emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef MCHP_PFSOC_DMC_H
 +#define MCHP_PFSOC_DMC_H
 +
 +/* DDR SGMII PHY module */
 +
 +#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE   0x1000
 +
 +typedef struct MchpPfSoCDdrSgmiiPhyState {
 +    SysBusDevice parent;
 +    MemoryRegion sgmii_phy;
 +} MchpPfSoCDdrSgmiiPhyState;
 +
 +#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
 +
 +#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
 +    OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
 +                 TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
 +
 +/* DDR CFG module */
 +
 +#define MCHP_PFSOC_DDR_CFG_REG_SIZE         0x40000
 +
 +typedef struct MchpPfSoCDdrCfgState {
 +    SysBusDevice parent;
 +    MemoryRegion cfg;
 +} MchpPfSoCDdrCfgState;
 +
 +#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
 +
 +#define MCHP_PFSOC_DDR_CFG(obj) \
 +    OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
 +                 TYPE_MCHP_PFSOC_DDR_CFG)
 +
 +#endif /* MCHP_PFSOC_DMC_H */
 diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/mchp_pfsoc_dmc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC DDR Memory Controller module emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "hw/hw.h"
 +#include "hw/sysbus.h"
 +#include "hw/misc/mchp_pfsoc_dmc.h"
 +
 +/* DDR SGMII PHY module */
 +
 +#define SGMII_PHY_IOC_REG1              0x208
 +#define SGMII_PHY_TRAINING_STATUS       0x814
 +#define SGMII_PHY_DQ_DQS_ERR_DONE       0x834
 +#define SGMII_PHY_DQDQS_STATUS1         0x84c
 +#define SGMII_PHY_PVT_STAT              0xc20
 +
 +static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
 +                                              unsigned size)
 +{
 +    uint32_t val = 0;
 +    static int training_status_bit;
 +
 +    switch (offset) {
 +    case SGMII_PHY_IOC_REG1:
 +        /* See ddr_pvt_calibration() in HSS */
 +        val = BIT(4) | BIT(2);
 +        break;
 +    case SGMII_PHY_TRAINING_STATUS:
 +        /*
 +         * The codes logic emulates the training status change from
 +         * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
 +         *
 +         * See ddr_setup() in mss_ddr.c in the HSS source codes.
 +         */
 +        val = 1 << training_status_bit;
 +        training_status_bit = (training_status_bit + 1) % 5;
 +        break;
 +    case SGMII_PHY_DQ_DQS_ERR_DONE:
 +        /*
 +         * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
 +         * check that DQ/DQS training passed without error.
 +         */
 +        val = 8;
 +        break;
 +    case SGMII_PHY_DQDQS_STATUS1:
 +        /*
 +         * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
 +         * check that DQ/DQS calculated window is above 5 taps.
 +         */
 +        val = 0xff;
 +        break;
 +    case SGMII_PHY_PVT_STAT:
 +        /* See sgmii_channel_setup() in HSS */
 +        val = BIT(14) | BIT(6);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
 +                                           uint64_t value, unsigned size)
 +{
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                  "(size %d, value 0x%" PRIx64
 +                  ", offset 0x%" HWADDR_PRIx ")\n",
 +                  __func__, size, value, offset);
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
 +    .read = mchp_pfsoc_ddr_sgmii_phy_read,
 +    .write = mchp_pfsoc_ddr_sgmii_phy_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
 +{
 +    MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
 +
 +    memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
 +                          &mchp_pfsoc_ddr_sgmii_phy_ops, s,
 +                          "mchp.pfsoc.ddr_sgmii_phy",
 +                          MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
 +}
 +
 +static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
 +    dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
 +}
 +
 +static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
 +    .name          = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
 +    .class_init    = mchp_pfsoc_ddr_sgmii_phy_class_init,
 +};
 +
 +static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
 +{
 +    type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
 +}
 +
 +type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
 +
 +/* DDR CFG module */
 +
 +#define CFG_MT_DONE_ACK                 0x4428
 +#define CFG_STAT_DFI_INIT_COMPLETE      0x10034
 +#define CFG_STAT_DFI_TRAINING_COMPLETE  0x10038
 +
 +static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
 +                                        unsigned size)
 +{
 +    uint32_t val = 0;
 +
 +    switch (offset) {
 +    case CFG_MT_DONE_ACK:
 +        /* memory test in MTC_test() */
 +        val = BIT(0);
 +        break;
 +    case CFG_STAT_DFI_INIT_COMPLETE:
 +        /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
 +        val = BIT(0);
 +        break;
 +    case CFG_STAT_DFI_TRAINING_COMPLETE:
 +        /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
 +        val = BIT(0);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
 +                                     uint64_t value, unsigned size)
 +{
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                  "(size %d, value 0x%" PRIx64
 +                  ", offset 0x%" HWADDR_PRIx ")\n",
 +                  __func__, size, value, offset);
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
 +    .read = mchp_pfsoc_ddr_cfg_read,
 +    .write = mchp_pfsoc_ddr_cfg_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
 +{
 +    MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
 +
 +    memory_region_init_io(&s->cfg, OBJECT(dev),
 +                          &mchp_pfsoc_ddr_cfg_ops, s,
 +                          "mchp.pfsoc.ddr_cfg",
 +                          MCHP_PFSOC_DDR_CFG_REG_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
 +}
 +
 +static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "Microchip PolarFire SoC DDR CFG module";
 +    dc->realize = mchp_pfsoc_ddr_cfg_realize;
 +}
 +
 +static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
 +    .name          = TYPE_MCHP_PFSOC_DDR_CFG,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MchpPfSoCDdrCfgState),
 +    .class_init    = mchp_pfsoc_ddr_cfg_class_init,
 +};
 +
 +static void mchp_pfsoc_ddr_cfg_register_types(void)
 +{
 +    type_register_static(&mchp_pfsoc_ddr_cfg_info);
 +}
 +
 +type_init(mchp_pfsoc_ddr_cfg_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
  S: Supported
  F: hw/riscv/microchip_pfsoc.c
  F: hw/char/mchp_pfsoc_mmuart.c
 +F: hw/misc/mchp_pfsoc_dmc.c
  F: include/hw/riscv/microchip_pfsoc.h
  F: include/hw/char/mchp_pfsoc_mmuart.h
 +F: include/hw/misc/mchp_pfsoc_dmc.h
  RX Machines
  -----------
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
  config AVR_POWER
      bool
 +config MCHP_PFSOC_DMC
 +    bool
 +
  config SIFIVE_TEST
      bool
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
 +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 --
 .28.0

-[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
+[PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
 From: Bin Meng <bin.meng@windriver.com>
-Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
+Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
 the address bytes. Note only SPI mode is supported by SST flashes.
 [1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
+Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/block/m25p80.c | 3 +++
+ include/hw/riscv/microchip_pfsoc.h |  5 +++++
-file changed, 3 insertions(+)
+ hw/riscv/microchip_pfsoc.c         | 18 ++++++++++++++++++
  hw/riscv/Kconfig                   |  1 +
 files changed, 24 insertions(+)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/hw/block/m25p80.c
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
+@@ -XXX,XX +XXX,XX @@
-     s->needed_bytes = get_addr_length(s);
-     switch (get_man(s)) {
+ #include "hw/char/mchp_pfsoc_mmuart.h"
-     /* Dummy cycles - modeled with bytes writes instead of bits */
+ #include "hw/dma/sifive_pdma.h"
-+    case MAN_SST:
++#include "hw/misc/mchp_pfsoc_dmc.h"
-+        s->needed_bytes += 1;
+ #include "hw/net/cadence_gem.h"
-+        break;
+ #include "hw/sd/cadence_sdhci.h"
-     case MAN_WINBOND:
-         s->needed_bytes += 8;
+@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
-         break;
+     RISCVHartArrayState e_cpus;
      RISCVHartArrayState u_cpus;
      DeviceState *plic;
 +    MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
 +    MchpPfSoCDdrCfgState ddr_cfg;
      MchpPfSoCMMUartState *serial0;
      MchpPfSoCMMUartState *serial1;
      MchpPfSoCMMUartState *serial2;
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_MMUART0,
      MICROCHIP_PFSOC_SYSREG,
      MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_DDR_SGMII_PHY,
      MICROCHIP_PFSOC_EMMC_SD,
 +    MICROCHIP_PFSOC_DDR_CFG,
      MICROCHIP_PFSOC_MMUART1,
      MICROCHIP_PFSOC_MMUART2,
      MICROCHIP_PFSOC_MMUART3,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
   * 4) Cadence eMMC/SDHC controller and an SD card connected to it
   * 5) SiFive Platform DMA (Direct Memory Access Controller)
   * 6) GEM (Gigabit Ethernet MAC Controller)
 + * 7) DMC (DDR Memory Controller)
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
      [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
      [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,     0x1000 },
      [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
 +    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,    0x40000 },
      [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      object_initialize_child(obj, "dma-controller", &s->dma,
                              TYPE_SIFIVE_PDMA);
 +    object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
 +                            TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
 +    object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
 +                            TYPE_MCHP_PFSOC_DDR_CFG);
 +
      object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
      object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
          memmap[MICROCHIP_PFSOC_MPUCFG].base,
          memmap[MICROCHIP_PFSOC_MPUCFG].size);
 +    /* DDR SGMII PHY */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
 +                    memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
 +
 +    /* DDR CFG */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
 +                    memmap[MICROCHIP_PFSOC_DDR_CFG].base);
 +
      /* SDHCI */
      sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config IBEX
  config MICROCHIP_PFSOC
      bool
      select CADENCE_SDHCI
 +    select MCHP_PFSOC_DMC
      select MCHP_PFSOC_MMUART
      select MSI_NONBROKEN
      select SIFIVE_CLINT
 --
-.30.1
+.28.0

-New patch
+[PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support
+From: Bin Meng <bin.meng@windriver.com>
 This creates a model for PolarFire SoC IOSCB [1] module. It actually
 contains lots of sub-modules like various PLLs to control different
 peripherals. Only the mininum capabilities are emulated to make the
 HSS DDR memory initialization codes happy. Lots of sub-modules are
 created as an unimplemented devices.
 [1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
     https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/misc/mchp_pfsoc_ioscb.h |  50 ++++++
  hw/misc/mchp_pfsoc_ioscb.c         | 242 +++++++++++++++++++++++++++++
  MAINTAINERS                        |   2 +
  hw/misc/Kconfig                    |   3 +
  hw/misc/meson.build                |   1 +
 files changed, 298 insertions(+)
  create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
  create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
 diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/mchp_pfsoc_ioscb.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC IOSCB module emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef MCHP_PFSOC_IOSCB_H
 +#define MCHP_PFSOC_IOSCB_H
 +
 +typedef struct MchpPfSoCIoscbState {
 +    SysBusDevice parent;
 +    MemoryRegion container;
 +    MemoryRegion lane01;
 +    MemoryRegion lane23;
 +    MemoryRegion ctrl;
 +    MemoryRegion cfg;
 +    MemoryRegion pll_mss;
 +    MemoryRegion cfm_mss;
 +    MemoryRegion pll_ddr;
 +    MemoryRegion bc_ddr;
 +    MemoryRegion io_calib_ddr;
 +    MemoryRegion pll_sgmii;
 +    MemoryRegion dll_sgmii;
 +    MemoryRegion cfm_sgmii;
 +    MemoryRegion bc_sgmii;
 +    MemoryRegion io_calib_sgmii;
 +} MchpPfSoCIoscbState;
 +
 +#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
 +
 +#define MCHP_PFSOC_IOSCB(obj) \
 +    OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB)
 +
 +#endif /* MCHP_PFSOC_IOSCB_H */
 diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/mchp_pfsoc_ioscb.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC IOSCB module emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "hw/hw.h"
 +#include "hw/sysbus.h"
 +#include "hw/misc/mchp_pfsoc_ioscb.h"
 +
 +/*
 + * The whole IOSCB module registers map into the system address at 0x3000_0000,
 + * named as "System Port 0 (AXI-D0)".
 + */
 +#define IOSCB_WHOLE_REG_SIZE        0x10000000
 +#define IOSCB_SUBMOD_REG_SIZE       0x1000
 +
 +/*
 + * There are many sub-modules in the IOSCB module.
 + * See Microchip PolarFire SoC documentation (Register_Map.zip),
 + * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
 + *
 + * The following are sub-modules offsets that are of concern.
 + */
 +#define IOSCB_LANE01_BASE           0x06500000
 +#define IOSCB_LANE23_BASE           0x06510000
 +#define IOSCB_CTRL_BASE             0x07020000
 +#define IOSCB_CFG_BASE              0x07080000
 +#define IOSCB_PLL_MSS_BASE          0x0E001000
 +#define IOSCB_CFM_MSS_BASE          0x0E002000
 +#define IOSCB_PLL_DDR_BASE          0x0E010000
 +#define IOSCB_BC_DDR_BASE           0x0E020000
 +#define IOSCB_IO_CALIB_DDR_BASE     0x0E040000
 +#define IOSCB_PLL_SGMII_BASE        0x0E080000
 +#define IOSCB_DLL_SGMII_BASE        0x0E100000
 +#define IOSCB_CFM_SGMII_BASE        0x0E200000
 +#define IOSCB_BC_SGMII_BASE         0x0E400000
 +#define IOSCB_IO_CALIB_SGMII_BASE   0x0E800000
 +
 +static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
 +                                      unsigned size)
 +{
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                  __func__, size, offset);
 +
 +    return 0;
 +}
 +
 +static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
 +                                   uint64_t value, unsigned size)
 +{
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                  "(size %d, value 0x%" PRIx64
 +                  ", offset 0x%" HWADDR_PRIx ")\n",
 +                  __func__, size, value, offset);
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
 +    .read = mchp_pfsoc_dummy_read,
 +    .write = mchp_pfsoc_dummy_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +/* All PLL modules in IOSCB have the same register layout */
 +
 +#define PLL_CTRL    0x04
 +
 +static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
 +                                    unsigned size)
 +{
 +    uint32_t val = 0;
 +
 +    switch (offset) {
 +    case PLL_CTRL:
 +        /* PLL is locked */
 +        val = BIT(25);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_pll_ops = {
 +    .read = mchp_pfsoc_pll_read,
 +    .write = mchp_pfsoc_dummy_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +/* IO_CALIB_DDR submodule */
 +
 +#define IO_CALIB_DDR_IOC_REG1   0x08
 +
 +static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
 +                                             unsigned size)
 +{
 +    uint32_t val = 0;
 +
 +    switch (offset) {
 +    case IO_CALIB_DDR_IOC_REG1:
 +        /* calibration completed */
 +        val = BIT(2);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
 +    .read = mchp_pfsoc_io_calib_ddr_read,
 +    .write = mchp_pfsoc_dummy_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
 +{
 +    MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +
 +    memory_region_init(&s->container, OBJECT(s),
 +                       "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
 +    sysbus_init_mmio(sbd, &s->container);
 +
 +    /* add subregions for all sub-modules in IOSCB */
 +
 +    memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
 +
 +    memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
 +
 +    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
 +
 +    memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
 +
 +    memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
 +                          "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
 +
 +    memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
 +
 +    memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
 +                          "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
 +
 +    memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
 +
 +    memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
 +                          &mchp_pfsoc_io_calib_ddr_ops, s,
 +                          "mchp.pfsoc.ioscb.io_calib_ddr",
 +                          IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
 +                                &s->io_calib_ddr);
 +
 +    memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
 +                          "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
 +                                &s->pll_sgmii);
 +
 +    memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
 +                                &s->dll_sgmii);
 +
 +    memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
 +                                &s->cfm_sgmii);
 +
 +    memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
 +                                &s->bc_sgmii);
 +
 +    memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
 +                          s, "mchp.pfsoc.ioscb.io_calib_sgmii",
 +                          IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
 +                                &s->io_calib_sgmii);
 +}
 +
 +static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "Microchip PolarFire SoC IOSCB modules";
 +    dc->realize = mchp_pfsoc_ioscb_realize;
 +}
 +
 +static const TypeInfo mchp_pfsoc_ioscb_info = {
 +    .name          = TYPE_MCHP_PFSOC_IOSCB,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MchpPfSoCIoscbState),
 +    .class_init    = mchp_pfsoc_ioscb_class_init,
 +};
 +
 +static void mchp_pfsoc_ioscb_register_types(void)
 +{
 +    type_register_static(&mchp_pfsoc_ioscb_info);
 +}
 +
 +type_init(mchp_pfsoc_ioscb_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Supported
  F: hw/riscv/microchip_pfsoc.c
  F: hw/char/mchp_pfsoc_mmuart.c
  F: hw/misc/mchp_pfsoc_dmc.c
 +F: hw/misc/mchp_pfsoc_ioscb.c
  F: include/hw/riscv/microchip_pfsoc.h
  F: include/hw/char/mchp_pfsoc_mmuart.h
  F: include/hw/misc/mchp_pfsoc_dmc.h
 +F: include/hw/misc/mchp_pfsoc_ioscb.h
  RX Machines
  -----------
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
  config MCHP_PFSOC_DMC
      bool
 +config MCHP_PFSOC_IOSCB
 +    bool
 +
  config SIFIVE_TEST
      bool
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
 +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 --
 .28.0

-[PULL 09/16] hw/riscv: Add fw_cfg support to virt
+[PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module
-From: Asherah Connor <ashe@kivikakk.ee>
+From: Bin Meng <bin.meng@windriver.com>
-Provides fw_cfg for the virt machine on riscv.  This enables
+Previously IOSCB_CFG was created as an unimplemented device. With
-using e.g.  ramfb later.
+the new IOSCB model, its memory range is already covered by the
 IOSCB hence remove the previous unimplemented device creation in
 the SoC codes.
-Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
+Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
+Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  2 ++
+ include/hw/riscv/microchip_pfsoc.h |  4 +++-
- hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
+ hw/riscv/microchip_pfsoc.c         | 13 ++++++++-----
- hw/riscv/Kconfig        |  1 +
+ hw/riscv/Kconfig                   |  1 +
-files changed, 33 insertions(+)
+files changed, 12 insertions(+), 6 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/include/hw/riscv/virt.h
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+ #include "hw/char/mchp_pfsoc_mmuart.h"
-     DeviceState *plic[VIRT_SOCKETS_MAX];
+ #include "hw/dma/sifive_pdma.h"
-     PFlashCFI01 *flash[2];
+ #include "hw/misc/mchp_pfsoc_dmc.h"
-+    FWCfgState *fw_cfg;
++#include "hw/misc/mchp_pfsoc_ioscb.h"
+ #include "hw/net/cadence_gem.h"
-     int fdt_size;
+ #include "hw/sd/cadence_sdhci.h"
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
      DeviceState *plic;
      MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
      MchpPfSoCDdrCfgState ddr_cfg;
 +    MchpPfSoCIoscbState ioscb;
      MchpPfSoCMMUartState *serial0;
      MchpPfSoCMMUartState *serial1;
      MchpPfSoCMMUartState *serial2;
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_GPIO2,
      MICROCHIP_PFSOC_ENVM_CFG,
      MICROCHIP_PFSOC_ENVM_DATA,
 -    MICROCHIP_PFSOC_IOSCB_CFG,
 +    MICROCHIP_PFSOC_IOSCB,
      MICROCHIP_PFSOC_DRAM,
  };
-@@ -XXX,XX +XXX,XX @@ enum {
-     VIRT_PLIC,
+diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
      VIRT_UART0,
      VIRT_VIRTIO,
 +    VIRT_FW_CFG,
      VIRT_FLASH,
      VIRT_DRAM,
      VIRT_PCIE_MMIO,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/hw/riscv/microchip_pfsoc.c
-+++ b/hw/riscv/virt.c
++++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
+@@ -XXX,XX +XXX,XX @@
-     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+  * 5) SiFive Platform DMA (Direct Memory Access Controller)
-     [VIRT_UART0] =       { 0x10000000,         0x100 },
+  * 6) GEM (Gigabit Ethernet MAC Controller)
-     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+  * 7) DMC (DDR Memory Controller)
-+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
++ * 8) IOSCB modules
-     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
+  *
-     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
+  * This board currently generates devicetree dynamically that indicates at least
-     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
+  * two harts and up to five harts.
-@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
+@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     return dev;
+     [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
 -    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
 +    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
      [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
  };
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      object_initialize_child(obj, "sd-controller", &s->sdhci,
                              TYPE_CADENCE_SDHCI);
 +
 +    object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
  }
-+static FWCfgState *create_fw_cfg(const MachineState *mc)
+ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
-+{
+@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
-+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+                                 memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
-+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+                                 envm_data);
-+    FWCfgState *fw_cfg;
-+    char *nodename;
+-    /* IOSCBCFG */
-+
+-    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
-+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+-        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
-+                                  &address_space_memory);
+-        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
-+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
++    /* IOSCB */
-+
++    sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
-+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
-+    qemu_fdt_add_subnode(mc->fdt, nodename);
++                    memmap[MICROCHIP_PFSOC_IOSCB].base);
-+    qemu_fdt_setprop_string(mc->fdt, nodename,
+ }
-+                            "compatible", "qemu,fw-cfg-mmio");
-+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+ static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
 +                                 2, base, 2, size);
 +    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
 +    g_free(nodename);
 +    return fw_cfg;
 +}
 +
  static void virt_machine_init(MachineState *machine)
  {
      const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          start_addr = virt_memmap[VIRT_FLASH].base;
      }
 +    /*
 +     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
 +     * tree cannot be altered and we get FDT_ERR_NOSPACE.
 +     */
 +    s->fw_cfg = create_fw_cfg(machine);
 +    rom_set_fw(s->fw_cfg);
 +
      /* Compute the fdt load address in dram */
      fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                     machine->ram_size, machine->fdt);
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select SIFIVE_PLIC
      select SIFIVE_TEST
      select VIRTIO_MMIO
 +    select FW_CFG_DMA
  config SIFIVE_E
      bool
+     select CADENCE_SDHCI
+     select MCHP_PFSOC_DMC
++    select MCHP_PFSOC_IOSCB
+     select MCHP_PFSOC_MMUART
+     select MSI_NONBROKEN
+     select SIFIVE_CLINT
 --
-.30.1
+.28.0

-[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
+[PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support
 From: Bin Meng <bin.meng@windriver.com>
-This adds the documentation to describe what is supported for the
+This creates a minimum model for Microchip PolarFire SoC SYSREG
-'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
+module. It only implements the ENVM_CR register to tell guest
 software that eNVM is running at the configured divider rate.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
+Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
+ include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++
- docs/system/target-riscv.rst               |  1 +
+ hw/misc/mchp_pfsoc_sysreg.c         | 99 +++++++++++++++++++++++++++++
-files changed, 90 insertions(+)
+ MAINTAINERS                         |  2 +
- create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
+ hw/misc/Kconfig                     |  3 +
+ hw/misc/meson.build                 |  1 +
-diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
+files changed, 144 insertions(+)
  create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
  create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
 diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/docs/system/riscv/microchip-icicle-kit.rst
++++ b/include/hw/misc/mchp_pfsoc_sysreg.h
 @@ -XXX,XX +XXX,XX @@
-+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
++/*
-+=============================================================
++ * Microchip PolarFire SoC SYSREG module emulation
-+
++ *
-+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
++ * Copyright (c) 2020 Wind River Systems, Inc.
-+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
++ *
-+
++ * Author:
-+For more details about Microchip PolarFire SoC, please see:
++ *   Bin Meng <bin.meng@windriver.com>
-+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
++ *
-+
++ * This program is free software; you can redistribute it and/or
-+The Icicle Kit board information can be found here:
++ * modify it under the terms of the GNU General Public License as
-+https://www.microsemi.com/existing-parts/parts/152514
++ * published by the Free Software Foundation; either version 2 or
-+
++ * (at your option) version 3 of the License.
-+Supported devices
++ *
-+-----------------
++ * This program is distributed in the hope that it will be useful,
-+
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+The ``microchip-icicle-kit`` machine supports the following devices:
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+
++ * GNU General Public License for more details.
-+ * 1 E51 core
++ *
-+ * 4 U54 cores
++ * You should have received a copy of the GNU General Public License along
-+ * Core Level Interruptor (CLINT)
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
-+ * Platform-Level Interrupt Controller (PLIC)
++ */
-+ * L2 Loosely Integrated Memory (L2-LIM)
++
-+ * DDR memory controller
++#ifndef MCHP_PFSOC_SYSREG_H
-+ * 5 MMUARTs
++#define MCHP_PFSOC_SYSREG_H
-+ * 1 DMA controller
++
-+ * 2 GEM Ethernet controllers
++#define MCHP_PFSOC_SYSREG_REG_SIZE  0x2000
-+ * 1 SDHC storage controller
++
-+
++typedef struct MchpPfSoCSysregState {
-+Boot options
++    SysBusDevice parent;
-+------------
++    MemoryRegion sysreg;
-+
++} MchpPfSoCSysregState;
-+The ``microchip-icicle-kit`` machine can start using the standard -bios
++
-+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
++#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
-+HSS loads the second stage bootloader U-Boot from an SD card. It does not
++
-+support direct kernel loading via the -kernel option. One has to load kernel
++#define MCHP_PFSOC_SYSREG(obj) \
-+from U-Boot.
++    OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
-+
++                 TYPE_MCHP_PFSOC_SYSREG)
-+The memory is set to 1537 MiB by default which is the minimum required high
++
-+memory size by HSS. A sanity check on ram size is performed in the machine
++#endif /* MCHP_PFSOC_SYSREG_H */
-+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
-+than 1537 MiB ram is detected.
+new file mode 100644
-+
+index XXXXXXX..XXXXXXX
-+Boot the machine
+--- /dev/null
-+----------------
++++ b/hw/misc/mchp_pfsoc_sysreg.c
-+
+@@ -XXX,XX +XXX,XX @@
-+HSS 2020.12 release is tested at the time of writing. To build an HSS image
++/*
-+that can be booted by the ``microchip-icicle-kit`` machine, type the following
++ * Microchip PolarFire SoC SYSREG module emulation
-+in the HSS source tree:
++ *
-+
++ * Copyright (c) 2020 Wind River Systems, Inc.
-+.. code-block:: bash
++ *
-+
++ * Author:
-+  $ export CROSS_COMPILE=riscv64-linux-
++ *   Bin Meng <bin.meng@windriver.com>
-+  $ cp boards/mpfs-icicle-kit-es/def_config .config
++ *
-+  $ make BOARD=mpfs-icicle-kit-es
++ * This program is free software; you can redistribute it and/or
-+
++ * modify it under the terms of the GNU General Public License as
-+Download the official SD card image released by Microchip and prepare it for
++ * published by the Free Software Foundation; either version 2 or
-+QEMU usage:
++ * (at your option) version 3 of the License.
-+
++ *
-+.. code-block:: bash
++ * This program is distributed in the hope that it will be useful,
-+
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
++ * GNU General Public License for more details.
-+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
++ *
-+
++ * You should have received a copy of the GNU General Public License along
-+Then we can boot the machine by:
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
-+
++ */
-+.. code-block:: bash
++
-+
++#include "qemu/osdep.h"
-+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
++#include "qemu/bitops.h"
-+      -bios path/to/hss.bin -sd path/to/sdcard.img \
++#include "qemu/log.h"
-+      -nic user,model=cadence_gem \
++#include "qapi/error.h"
-+      -nic tap,ifname=tap,model=cadence_gem,script=no \
++#include "hw/hw.h"
-+      -display none -serial stdio \
++#include "hw/sysbus.h"
-+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
++#include "hw/misc/mchp_pfsoc_sysreg.h"
-+      -serial chardev:serial1
++
-+
++#define ENVM_CR         0xb8
-+With above command line, current terminal session will be used for the first
++
-+serial port. Open another terminal window, and use `minicom` to connect the
++static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
-+second serial port.
++                                       unsigned size)
-+
++{
-+.. code-block:: bash
++    uint32_t val = 0;
 +
-+  $ minicom -D unix\#serial1.sock
++    switch (offset) {
-+
++    case ENVM_CR:
-+HSS output is on the first serial port (stdio) and U-Boot outputs on the
++        /* Indicate the eNVM is running at the configured divider rate */
-+second serial port. U-Boot will automatically load the Linux kernel from
++        val = BIT(6);
-+the SD card image.
++        break;
-+
++    default:
-+.. _HSS: https://github.com/polarfire-soc/hart-software-services
++        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
-diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
++                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
 +                                    uint64_t value, unsigned size)
 +{
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                  "(size %d, value 0x%" PRIx64
 +                  ", offset 0x%" HWADDR_PRIx ")\n",
 +                  __func__, size, value, offset);
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
 +    .read = mchp_pfsoc_sysreg_read,
 +    .write = mchp_pfsoc_sysreg_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
 +{
 +    MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
 +
 +    memory_region_init_io(&s->sysreg, OBJECT(dev),
 +                          &mchp_pfsoc_sysreg_ops, s,
 +                          "mchp.pfsoc.sysreg",
 +                          MCHP_PFSOC_SYSREG_REG_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
 +}
 +
 +static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "Microchip PolarFire SoC SYSREG module";
 +    dc->realize = mchp_pfsoc_sysreg_realize;
 +}
 +
 +static const TypeInfo mchp_pfsoc_sysreg_info = {
 +    .name          = TYPE_MCHP_PFSOC_SYSREG,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MchpPfSoCSysregState),
 +    .class_init    = mchp_pfsoc_sysreg_class_init,
 +};
 +
 +static void mchp_pfsoc_sysreg_register_types(void)
 +{
 +    type_register_static(&mchp_pfsoc_sysreg_info);
 +}
 +
 +type_init(mchp_pfsoc_sysreg_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-riscv.rst
+--- a/MAINTAINERS
-+++ b/docs/system/target-riscv.rst
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ F: hw/riscv/microchip_pfsoc.c
- .. toctree::
+ F: hw/char/mchp_pfsoc_mmuart.c
-    :maxdepth: 1
+ F: hw/misc/mchp_pfsoc_dmc.c
+ F: hw/misc/mchp_pfsoc_ioscb.c
-+   riscv/microchip-icicle-kit
++F: hw/misc/mchp_pfsoc_sysreg.c
-    riscv/sifive_u
+ F: include/hw/riscv/microchip_pfsoc.h
+ F: include/hw/char/mchp_pfsoc_mmuart.h
- RISC-V CPU features
+ F: include/hw/misc/mchp_pfsoc_dmc.h
  F: include/hw/misc/mchp_pfsoc_ioscb.h
 +F: include/hw/misc/mchp_pfsoc_sysreg.h
  RX Machines
  -----------
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MCHP_PFSOC_DMC
  config MCHP_PFSOC_IOSCB
      bool
 +config MCHP_PFSOC_SYSREG
 +    bool
 +
  config SIFIVE_TEST
      bool
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
 +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 --
-.30.1
+.28.0

-[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
+[PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module
-From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+From: Bin Meng <bin.meng@windriver.com>
-The current condition for the use of background registers only
+Previously SYSREG was created as an unimplemented device. Now that
-considers the hypervisor load and store instructions,
+we have a simple SYSREG module, connect it.
 but not accesses from M mode via MSTATUS_MPRV+MPV.
-Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
+Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
+Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 2 +-
+ include/hw/riscv/microchip_pfsoc.h | 2 ++
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/riscv/microchip_pfsoc.c         | 9 ++++++---
  hw/riscv/Kconfig                   | 1 +
 files changed, 9 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/target/riscv/cpu_helper.c
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+@@ -XXX,XX +XXX,XX @@
-      * was called. Background registers will be used if the guest has
+ #include "hw/dma/sifive_pdma.h"
-      * forced a two stage translation to be on (in HS or M mode).
+ #include "hw/misc/mchp_pfsoc_dmc.h"
-      */
+ #include "hw/misc/mchp_pfsoc_ioscb.h"
--    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
++#include "hw/misc/mchp_pfsoc_sysreg.h"
-+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
+ #include "hw/net/cadence_gem.h"
-         use_background = true;
+ #include "hw/sd/cadence_sdhci.h"
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
      MchpPfSoCMMUartState *serial2;
      MchpPfSoCMMUartState *serial3;
      MchpPfSoCMMUartState *serial4;
 +    MchpPfSoCSysregState sysreg;
      SiFivePDMAState dma;
      CadenceGEMState gem0;
      CadenceGEMState gem1;
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      object_initialize_child(obj, "dma-controller", &s->dma,
                              TYPE_SIFIVE_PDMA);
 +    object_initialize_child(obj, "sysreg", &s->sysreg,
 +                            TYPE_MCHP_PFSOC_SYSREG);
 +
      object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
                              TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
      object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      }
+     /* SYSREG */
+-    create_unimplemented_device("microchip.pfsoc.sysreg",
+-        memmap[MICROCHIP_PFSOC_SYSREG].base,
+-        memmap[MICROCHIP_PFSOC_SYSREG].size);
++    sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
++                    memmap[MICROCHIP_PFSOC_SYSREG].base);
+     /* MPUCFG */
+     create_unimplemented_device("microchip.pfsoc.mpucfg",
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/Kconfig
++++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
+     select MCHP_PFSOC_DMC
+     select MCHP_PFSOC_IOSCB
+     select MCHP_PFSOC_MMUART
++    select MCHP_PFSOC_SYSREG
+     select MSI_NONBROKEN
+     select SIFIVE_CLINT
+     select SIFIVE_PDMA
 --
-.30.1
+.28.0

-[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
+[PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
-From: Alexander Wagner <alexander.wagner@ulal.de>
+From: Bin Meng <bin.meng@windriver.com>
-Not disabling the UART leads to QEMU overwriting the UART receive buffer with
+Somehow HSS needs to access address 0 [1] for the DDR calibration data
-the newest received byte. The rx_level variable is added to allow the use of
+which is in the chipset's reserved memory. Let's map it.
 the existing OpenTitan driver libraries.
-Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
+[1] See the config_copy() calls in various places in ddr_setup() in
     the HSS source codes.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
+Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/ibex_uart.h |  4 ++++
+ include/hw/riscv/microchip_pfsoc.h |  1 +
- hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
+ hw/riscv/microchip_pfsoc.c         | 11 ++++++++++-
-files changed, 22 insertions(+), 5 deletions(-)
+files changed, 11 insertions(+), 1 deletion(-)
-diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/ibex_uart.h
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/include/hw/char/ibex_uart.h
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
+@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipIcicleKitState {
-     FIELD(FIFO_CTRL, RXILVL, 2, 3)
+                  TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
-     FIELD(FIFO_CTRL, TXILVL, 5, 2)
- REG32(FIFO_STATUS, 0x20)
+ enum {
-+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
++    MICROCHIP_PFSOC_RSVD0,
-+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
+     MICROCHIP_PFSOC_DEBUG,
- REG32(OVRD, 0x24)
+     MICROCHIP_PFSOC_E51_DTIM,
- REG32(VAL, 0x28)
+     MICROCHIP_PFSOC_BUSERR_UNIT0,
- REG32(TIMEOUT_CTRL, 0x2c)
+diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
+index XXXXXXX..XXXXXXX 100644
-     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
+--- a/hw/riscv/microchip_pfsoc.c
-     uint32_t tx_level;
++++ b/hw/riscv/microchip_pfsoc.c
+@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-+    uint32_t rx_level;
+     hwaddr base;
      hwaddr size;
  } microchip_pfsoc_memmap[] = {
 -    [MICROCHIP_PFSOC_DEBUG] =           {        0x0,     0x1000 },
 +    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,      0x100 },
 +    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,      0xf00 },
      [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
      [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
      [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
      const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
      MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
      MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
      MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
      MemoryRegion *envm_data = g_new(MemoryRegion, 1);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
      qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 +    /* Reserved Memory at address 0 */
 +    memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
 +                           memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_RSVD0].base,
 +                                rsvd0_mem);
 +
-     QEMUTimer *fifo_trigger_handle;
+     /* E51 DTIM */
-     uint64_t char_tx_time;
+     memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
+                            memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/ibex_uart.c
 +++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
  {
      IbexUartState *s = opaque;
 -    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
 +           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
          return 1;
      }
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
      s->uart_status &= ~R_STATUS_RXIDLE_MASK;
      s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
 +    /* The RXFULL is set after receiving a single byte
 +     * as the FIFO buffers are not yet implemented.
 +     */
 +    s->uart_status |= R_STATUS_RXFULL_MASK;
 +    s->rx_level += 1;
      if (size > rx_fifo_level) {
          s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
      s->uart_timeout_ctrl = 0x00000000;
      s->tx_level = 0;
 +    s->rx_level = 0;
      s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_RDATA:
          retvalue = s->uart_rdata;
 -        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 +        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
              qemu_chr_fe_accept_input(&s->chr);
 -            s->uart_status |= R_STATUS_RXIDLE_MASK;
 -            s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            s->rx_level -= 1;
 +            s->uart_status &= ~R_STATUS_RXFULL_MASK;
 +            if (s->rx_level == 0) {
 +                s->uart_status |= R_STATUS_RXIDLE_MASK;
 +                s->uart_status |= R_STATUS_RXEMPTY_MASK;
 +            }
          }
          break;
      case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
      case R_FIFO_STATUS:
          retvalue = s->uart_fifo_status;
 -        retvalue |= s->tx_level & 0x1F;
 +        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
 +        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
          qemu_log_mask(LOG_UNIMP,
                        "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
          s->uart_fifo_ctrl = value;
          if (value & R_FIFO_CTRL_RXRST_MASK) {
 +            s->rx_level = 0;
              qemu_log_mask(LOG_UNIMP,
                            "%s: RX fifos are not supported\n", __func__);
          }
 --
-.30.1
+.28.0

-[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
+[PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map
-From: Jim Shu <cwshu@andestech.com>
+From: Bin Meng <bin.meng@windriver.com>
-If PMP permission of any address has been changed by updating PMP entry,
+When system memory is larger than 1 GiB (high memory), PolarFire SoC
-flush all TLB pages to prevent from getting old permission.
+maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
 aliased to the same 1 GiB low memory with different cache attributes.
-Signed-off-by: Jim Shu <cwshu@andestech.com>
+At present QEMU maps the system memory contiguously from 0x8000_0000.
 This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
 the alias to the high memory, and even physical memory is only 1 GiB,
 the HSS codes still tries to probe the high memory alias address.
 It seems there is no issue on the real hardware, so we will have to
 take that into the consideration in our emulation. Due to this, we
 we increase the default system memory size to 1537 MiB (the minimum
 required high memory size by HSS) so that user gets notified an error
 when less than 1537 MiB is specified.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
+Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/pmp.c | 4 ++++
+ include/hw/riscv/microchip_pfsoc.h |  5 ++-
-file changed, 4 insertions(+)
+ hw/riscv/microchip_pfsoc.c         | 50 ++++++++++++++++++++++++++----
 files changed, 48 insertions(+), 7 deletions(-)
-diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/target/riscv/pmp.c
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ enum {
- #include "qapi/error.h"
+     MICROCHIP_PFSOC_ENVM_CFG,
- #include "cpu.h"
+     MICROCHIP_PFSOC_ENVM_DATA,
- #include "trace.h"
+     MICROCHIP_PFSOC_IOSCB,
-+#include "exec/exec-all.h"
+-    MICROCHIP_PFSOC_DRAM,
++    MICROCHIP_PFSOC_DRAM_LO,
- static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
++    MICROCHIP_PFSOC_DRAM_LO_ALIAS,
-     uint8_t val);
++    MICROCHIP_PFSOC_DRAM_HI,
-@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
++    MICROCHIP_PFSOC_DRAM_HI_ALIAS
-         cfg_val = (val >> 8 * i)  & 0xff;
+ };
-         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
-     }
+ enum {
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
 -    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
 +    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
 +    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
 +    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
 +    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,        0x0 },
  };
  static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
      const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
      MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
      MemoryRegion *system_memory = get_system_memory();
 -    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +    MemoryRegion *mem_low = g_new(MemoryRegion, 1);
 +    MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
 +    MemoryRegion *mem_high = g_new(MemoryRegion, 1);
 +    MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
 +    uint64_t mem_high_size;
      DriveInfo *dinfo = drive_get_next(IF_SD);
      /* Sanity check on RAM size */
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
      qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
      /* Register RAM */
 -    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
 -                           machine->ram_size, &error_fatal);
 +    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
 +                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
 +                           &error_fatal);
 +    memory_region_init_alias(mem_low_alias, NULL,
 +                             "microchip.icicle.kit.ram_low.alias",
 +                             mem_low, 0,
 +                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 +                                mem_low);
      memory_region_add_subregion(system_memory,
 -                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
 +                                memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
 +                                mem_low_alias);
 +
-+    /* If PMP permission of any addr has been changed, flush TLB pages. */
++    mem_high_size = machine->ram_size - 1 * GiB;
-+    tlb_flush(env_cpu(env));
++
 +    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
 +                           mem_high_size, &error_fatal);
 +    memory_region_init_alias(mem_high_alias, NULL,
 +                             "microchip.icicle.kit.ram_high.alias",
 +                             mem_high, 0, mem_high_size);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
 +                                mem_high);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
 +                                mem_high_alias);
      /* Load the firmware */
      riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                     MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
      mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
      mc->default_cpus = mc->min_cpus;
 -    mc->default_ram_size = 1 * GiB;
 +
 +    /*
 +     * Map 513 MiB high memory, the mimimum required high memory size, because
 +     * HSS will do memory test against the high memory address range regardless
 +     * of physical memory installed.
 +     *
 +     * See memory_tests() in mss_ddr.c in the HSS source code.
 +     */
 +    mc->default_ram_size = 1537 * MiB;
  }
+ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
 --
-.30.1
+.28.0

-[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
+[PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller
 From: Bin Meng <bin.meng@windriver.com>
-Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
+The latest SD card image [1] released by Microchip ships a Linux
-been updated to use a register mapped at 0x4f000000 instead of a
+kernel with built-in PolarFire SoC I2C driver support. The device
-GPIO to control whether eMMC or SD card is to be used. With this
+tree file includes the description for the I2C1 node hence kernel
-support the same HSS image can be used for both eMMC and SD card
+tries to probe the I2C1 device during boot.
 boot flow, while previously two different board configurations were
 used. This is undocumented but one can take a look at the HSS code
 HSS_MMCInit() in services/mmc/mmc_api.c.
-With this commit, HSS image built from 2020.12 release boots again.
+It is enough to create an unimplemented device for I2C1 to allow
 the kernel to continue booting to the shell.
 [1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
+Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/riscv/microchip_pfsoc.h | 1 +
  hw/riscv/microchip_pfsoc.c         | 6 ++++++
 files changed, 7 insertions(+)
 diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/microchip_pfsoc.h
 +++ b/include/hw/riscv/microchip_pfsoc.h
 @@ -XXX,XX +XXX,XX @@ enum {
-     MICROCHIP_PFSOC_ENVM_DATA,
+     MICROCHIP_PFSOC_MMUART2,
-     MICROCHIP_PFSOC_QSPI_XIP,
+     MICROCHIP_PFSOC_MMUART3,
-     MICROCHIP_PFSOC_IOSCB,
+     MICROCHIP_PFSOC_MMUART4,
-+    MICROCHIP_PFSOC_EMMC_SD_MUX,
++    MICROCHIP_PFSOC_I2C1,
-     MICROCHIP_PFSOC_DRAM_LO,
+     MICROCHIP_PFSOC_GEM0,
-     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+     MICROCHIP_PFSOC_GEM1,
-     MICROCHIP_PFSOC_DRAM_HI,
+     MICROCHIP_PFSOC_GPIO0,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
-     [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
-     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+     [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
-+    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
++    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,     0x1000 },
-     [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
+     [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
-     [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
+     [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
-     [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+     [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
 @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+         qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
-                     memmap[MICROCHIP_PFSOC_IOSCB].base);
+         serial_hd(4));
-+    /* eMMC/SD mux */
++    /* I2C1 */
-+    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
++    create_unimplemented_device("microchip.pfsoc.i2c1",
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
++        memmap[MICROCHIP_PFSOC_I2C1].base,
-+        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
++        memmap[MICROCHIP_PFSOC_I2C1].size);
 +
-     /* QSPI Flash */
+     /* GEMs */
-     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
-                            "microchip.pfsoc.qspi_xip",
+     nd = &nd_table[0];
 --
-.30.1
+.28.0

-[PULL 01/16] target/riscv: fix vs() to return proper error code
+[PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '('
-From: Frank Chang <frank.chang@sifive.com>
+From: Xinhao Zhang <zhangxinhao1@huawei.com>
-vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
+Fix code style. Space required before the open parenthesis '('.
 is not enabled.
-If -1 is returned, exception will be raised and cs->exception_index will
+Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
-be set to the negative return value. The exception will then be treated
+Signed-off-by: Kai Deng <dengkai1@huawei.com>
-as an instruction access fault instead of illegal instruction fault.
+Reported-by: Euler Robot <euler.robot@huawei.com>
+Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210223065935.20208-1-frank.chang@sifive.com
+Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/csr.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
-     if (env->misa & RVV) {
+         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-         return 0;
+             return -RISCV_EXCP_ILLEGAL_INST;
-     }
+         } else {
--    return -1;
+-            if((val ^ env->satp) & SATP_ASID) {
-+    return -RISCV_EXCP_ILLEGAL_INST;
++            if ((val ^ env->satp) & SATP_ASID) {
- }
+                 tlb_flush(env_cpu(env));
+             }
- static int ctr(CPURISCVState *env, int csrno)
+             env->satp = val;
 --
-.30.1
+.28.0

The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:

Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2

for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:

target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR includes:
 - Fix for vector CSR access
 - Improvements to the Ibex UART device
 - PMP improvements and bug fixes
 - Hypervisor extension bug fixes
 - ramfb support for the virt machine
 - Fast read support for SST flash
 - Improvements to the microchip_pfsoc machine

----------------------------------------------------------------
Alexander Wagner (1):
      hw/char: disable ibex uart receive if the buffer is full

Asherah Connor (2):
      hw/riscv: Add fw_cfg support to virt
      hw/riscv: allow ramfb on virt

Bin Meng (3):
      hw/block: m25p80: Support fast read for SST flashes
      hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
      docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine

Frank Chang (1):
      target/riscv: fix vs() to return proper error code

Georg Kotheimer (6):
      target/riscv: Adjust privilege level for HLV(X)/HSV instructions
      target/riscv: Make VSTIP and VSEIP read-only in hip
      target/riscv: Use background registers also for MSTATUS_MPV
      target/riscv: Fix read and write accesses to vsip and vsie
      target/riscv: Add proper two-stage lookup exception detection
      target/riscv: Prevent lost illegal instruction exceptions

Jim Shu (3):
      target/riscv: propagate PMP permission to TLB page
      target/riscv: add log of PMP permission checking
      target/riscv: flush TLB pages if PMP permission has been changed

From: Frank Chang <frank.chang@sifive.com>

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)
-- 
2.30.1

From: Alexander Wagner <alexander.wagner@ulal.de>

Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/ibex_uart.h |  4 ++++
 hw/char/ibex_uart.c         | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
     FIELD(FIFO_CTRL, RXILVL, 2, 3)
     FIELD(FIFO_CTRL, TXILVL, 5, 2)
 REG32(FIFO_STATUS, 0x20)
+    FIELD(FIFO_STATUS, TXLVL, 0, 5)
+    FIELD(FIFO_STATUS, RXLVL, 16, 5)
 REG32(OVRD, 0x24)
 REG32(VAL, 0x28)
 REG32(TIMEOUT_CTRL, 0x2c)
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     uint32_t tx_level;
 
+    uint32_t rx_level;
+
     QEMUTimer *fifo_trigger_handle;
     uint64_t char_tx_time;
 
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
 {
     IbexUartState *s = opaque;
 
-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
         return 1;
     }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
 
     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    /* The RXFULL is set after receiving a single byte
+     * as the FIFO buffers are not yet implemented.
+     */
+    s->uart_status |= R_STATUS_RXFULL_MASK;
+    s->rx_level += 1;
 
     if (size > rx_fifo_level) {
         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
     s->uart_timeout_ctrl = 0x00000000;
 
     s->tx_level = 0;
+    s->rx_level = 0;
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 
     case R_RDATA:
         retvalue = s->uart_rdata;
-        if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+        if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
             qemu_chr_fe_accept_input(&s->chr);
 
-            s->uart_status |= R_STATUS_RXIDLE_MASK;
-            s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            s->rx_level -= 1;
+            s->uart_status &= ~R_STATUS_RXFULL_MASK;
+            if (s->rx_level == 0) {
+                s->uart_status |= R_STATUS_RXIDLE_MASK;
+                s->uart_status |= R_STATUS_RXEMPTY_MASK;
+            }
         }
         break;
     case R_WDATA:
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
     case R_FIFO_STATUS:
         retvalue = s->uart_fifo_status;
 
-        retvalue |= s->tx_level & 0x1F;
+        retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
+        retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
 
         qemu_log_mask(LOG_UNIMP,
                       "%s: RX fifos are not supported\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
         s->uart_fifo_ctrl = value;
 
         if (value & R_FIFO_CTRL_RXRST_MASK) {
+            s->rx_level = 0;
             qemu_log_mask(LOG_UNIMP,
                           "%s: RX fifos are not supported\n", __func__);
         }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.

PMP permission checking also use MMU-style API to change TLB permission
and size.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  4 +-
 target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
 target/riscv/pmp.c        | 80 +++++++++++++++++++++++++++----------
 3 files changed, 125 insertions(+), 43 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t priv, target_ulong mode);
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     env->load_res = -1;
 }
 
+/*
+ * get_physical_address_pmp - check PMP permission for this physical address
+ *
+ * Match the PMP region and check permission for this physical address and it's
+ * TLB page. Returns 0 if the permission checking was successful
+ *
+ * @env: CPURISCVState
+ * @prot: The returned protection attributes
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
+ *            permission checking. NULL if not set TLB page for addr.
+ * @addr: The physical address to be checked permission
+ * @access_type: The type of MMU access
+ * @mode: Indicates current privilege level.
+ */
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                    target_ulong *tlb_size, hwaddr addr,
+                                    int size, MMUAccessType access_type,
+                                    int mode)
+{
+    pmp_priv_t pmp_priv;
+    target_ulong tlb_size_pmp = 0;
+
+    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return TRANSLATE_SUCCESS;
+    }
+
+    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
+                            mode)) {
+        *prot = 0;
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    *prot = pmp_priv_to_page_prot(pmp_priv);
+    if (tlb_size != NULL) {
+        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
+            *tlb_size = tlb_size_pmp;
+        }
+    }
+
+    return TRANSLATE_SUCCESS;
+}
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -XXX,XX +XXX,XX @@ restart:
             pte_addr = base + idx * ptesize;
         }
 
-        if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-            !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
-            1 << MMU_DATA_LOAD, PRV_S)) {
+        int pmp_prot;
+        int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+                                               sizeof(target_ulong),
+                                               MMU_DATA_LOAD, PRV_S);
+        if (pmp_ret != TRANSLATE_SUCCESS) {
             return TRANSLATE_PMP_FAIL;
         }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #ifndef CONFIG_USER_ONLY
     vaddr im_address;
     hwaddr pa = 0;
-    int prot, prot2;
+    int prot, prot2, prot_pmp;
     bool pmp_violation = false;
     bool first_stage_error = true;
     bool two_stage_lookup = false;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
-    target_ulong tlb_size = 0;
+    /* default TLB page size */
+    target_ulong tlb_size = TARGET_PAGE_SIZE;
 
     env->guest_phys_fault_addr = 0;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
             prot &= prot2;
 
-            if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-                (ret == TRANSLATE_SUCCESS) &&
-                !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-                ret = TRANSLATE_PMP_FAIL;
+            if (ret == TRANSLATE_SUCCESS) {
+                ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                               size, access_type, mode);
+                prot &= prot_pmp;
             }
 
             if (ret != TRANSLATE_SUCCESS) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       "%s address=%" VADDR_PRIx " ret %d physical "
                       TARGET_FMT_plx " prot %d\n",
                       __func__, address, ret, pa, prot);
-    }
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        (ret == TRANSLATE_SUCCESS) &&
-        !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-        ret = TRANSLATE_PMP_FAIL;
+        if (ret == TRANSLATE_SUCCESS) {
+            ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+                                           size, access_type, mode);
+            prot &= prot_pmp;
+        }
     }
+
     if (ret == TRANSLATE_PMP_FAIL) {
         pmp_violation = true;
     }
 
     if (ret == TRANSLATE_SUCCESS) {
-        if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
-            tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
-                         prot, mmu_idx, tlb_size);
-        } else {
-            tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                         prot, mmu_idx, TARGET_PAGE_SIZE);
-        }
+        tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
+                     prot, mmu_idx, tlb_size);
         return true;
     } else if (probe) {
         return false;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
     return result;
 }
 
+/*
+ * Check if the address has required RWX privs when no PMP entry is matched.
+ */
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
+{
+    bool ret;
+
+    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+        /*
+         * Privileged spec v1.10 states if HW doesn't implement any PMP entry
+         * or no PMP entry matches an M-Mode access, the access succeeds.
+         */
+        ret = true;
+        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+    } else {
+        /*
+         * Other modes are not allowed to succeed if they don't * match a rule,
+         * but there are rules. We've checked for no rule earlier in this
+         * function.
+         */
+        ret = false;
+        *allowed_privs = 0;
+    }
+
+    return ret;
+}
+
 
 /*
  * Public Interface
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-    target_ulong size, pmp_priv_t privs, target_ulong mode)
+    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
+    target_ulong mode)
 {
     int i = 0;
     int ret = -1;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
-    pmp_priv_t allowed_privs = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return (env->priv == PRV_M) ? true : false;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          * check
          */
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
             }
 
-            if ((privs & allowed_privs) == privs) {
-                ret = 1;
-                break;
-            } else {
-                ret = 0;
-                break;
-            }
+            ret = ((privs & *allowed_privs) == privs);
+            break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        if (mode == PRV_M) {
-            ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
-                      * M-Mode access, the access succeeds */
-        } else {
-            ret = 0; /* Other modes are not allowed to succeed if they don't
-                      * match a rule, but there are rules.  We've checked for
-                      * no rule earlier in this function. */
-        }
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     return ret == 1 ? true : false;
 }
 
-
 /*
  * Handle a write to a pmpcfg CSP
  */
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 
     return false;
 }
+
+/*
+ * Convert PMP privilege to TLB page privilege.
+ */
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
+{
+    int prot = 0;
+
+    if (pmp_priv & PMP_READ) {
+        prot |= PAGE_READ;
+    }
+    if (pmp_priv & PMP_WRITE) {
+        prot |= PAGE_WRITE;
+    }
+    if (pmp_priv & PMP_EXEC) {
+        prot |= PAGE_EXEC;
+    }
+
+    return prot;
+}
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

Like MMU translation, add qemu log of PMP permission checking for
debugging.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             if (ret == TRANSLATE_SUCCESS) {
                 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                                size, access_type, mode);
+
+                qemu_log_mask(CPU_LOG_MMU,
+                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                              " %d tlb_size " TARGET_FMT_lu "\n",
+                              __func__, pa, ret, prot_pmp, tlb_size);
+
                 prot &= prot_pmp;
             }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         if (ret == TRANSLATE_SUCCESS) {
             ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
                                            size, access_type, mode);
+
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+                          " %d tlb_size " TARGET_FMT_lu "\n",
+                          __func__, pa, ret, prot_pmp, tlb_size);
+
             prot &= prot_pmp;
         }
     }
-- 
2.30.1

From: Jim Shu <cwshu@andestech.com>

If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "cpu.h"
 #include "trace.h"
+#include "exec/exec-all.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
     uint8_t val);
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
+
+    /* If PMP permission of any addr has been changed, flush TLB pages. */
+    tlb_flush(env_cpu(env));
 }
 
 
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 
 static const char valid_vm_1_10_32[16] = {
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & hip_writable_mask);
+                      write_mask & hvip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
+    *ret_value &= hvip_writable_mask;
 
     return ret;
 }
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1

From: Asherah Connor <ashe@kivikakk.ee>

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const MemMapEntry virt_memmap[] = {
     [VIRT_DEBUG] =       {        0x0,         0x100 },
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The previous implementation was broken in many ways:
 - Used mideleg instead of hideleg to mask accesses
 - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
 - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* Shift the VS bits to their S bit location in vsie */
+    *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
+    return 0;
+}
+
 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
-        /* Tell the guest the VS bits, shifted to the S bit locations */
-        *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
+        read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
     return 0;
 }
 
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong newval;
+    /* Shift the S bits to their VS bit location in mie */
+    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
+                          ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
+    return write_mie(env, CSR_MIE, newval);
+}
 
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+{
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the guests S bits to VS */
-        newval = (env->mie & ~VS_MODE_INTERRUPTS) |
-                 ((val << 1) & VS_MODE_INTERRUPTS);
+        write_vsie(env, CSR_VSIE, val);
     } else {
-        newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
+        target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
+                              (val & S_MODE_INTERRUPTS);
+        write_mie(env, CSR_MIE, newval);
     }
 
-    return write_mie(env, CSR_MIE, newval);
+    return 0;
 }
 
 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                    target_ulong new_value, target_ulong write_mask)
+{
+    /* Shift the S bits to their VS bit location in mip */
+    int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+                      (write_mask << 1) & vsip_writable_mask & env->hideleg);
+    *ret_value &= VS_MODE_INTERRUPTS;
+    /* Shift the VS bits to their S bit location in vsip */
+    *ret_value >>= 1;
+    return ret;
+}
+
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
     if (riscv_cpu_virt_enabled(env)) {
-        /* Shift the new values to line up with the VS bits */
-        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
-                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
-        ret &= vsip_writable_mask;
-        ret >>= 1;
+        ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
     } else {
         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
-{
-    int ret = rmw_mip(env, 0, ret_value, new_value,
-                      write_mask & env->mideleg & vsip_writable_mask);
-    return ret;
-}
-
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
-    return 0;
-}
-
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
-{
-    target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
-    return write_mie(env, CSR_MIE, newval);
-}
-
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.

What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 ++++
 target/riscv/cpu.c        |  1 +
 target/riscv/cpu_helper.c | 21 ++++++++-------------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong satp_hs;
     uint64_t mstatus_hs;
 
+    /* Signals whether the current exception occurred with two-stage address
+       translation active. */
+    bool two_stage_lookup;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
     env->pc = env->resetvec;
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         g_assert_not_reached();
     }
     env->badaddr = address;
+    env->two_stage_lookup = two_stage;
 }
 
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
+    env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+                            riscv_cpu_two_stage_lookup(mmu_idx);
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #endif /* !CONFIG_USER_ONLY */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         /* handle the trap in S-mode */
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
-            bool two_stage_lookup = false;
 
-            if (env->priv == PRV_M ||
-                (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-                (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                    get_field(env->hstatus, HSTATUS_HU))) {
-                    two_stage_lookup = true;
-            }
-
-            if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
+            if (env->two_stage_lookup && write_tval) {
                 /*
                  * If we are writing a guest virtual address to stval, set
                  * this to 1. If we are trapping to VS we will set this to 0
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                if (!two_stage_lookup) {
-                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
-                                             riscv_cpu_virt_enabled(env));
-                }
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
                 htval = env->guest_phys_fault_addr;
             }
         }
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
      * RISC-V ISA Specification.
      */
 
+    env->two_stage_lookup = false;
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.

[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/block/m25p80.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
     s->needed_bytes = get_addr_length(s);
     switch (get_man(s)) {
     /* Dummy cycles - modeled with bytes writes instead of bits */
+    case MAN_SST:
+        s->needed_bytes += 1;
+        break;
     case MAN_WINBOND:
         s->needed_bytes += 8;
         break;
-- 
2.30.1

From: Bin Meng <bin.meng@windriver.com>

Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

From: Bin Meng <bin.meng@windriver.com>

This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
 docs/system/target-riscv.rst               |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 docs/system/riscv/microchip-icicle-kit.rst

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -XXX,XX +XXX,XX @@
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
+=============================================================
+
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+
+For more details about Microchip PolarFire SoC, please see:
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+
+The Icicle Kit board information can be found here:
+https://www.microsemi.com/existing-parts/parts/152514
+
+Supported devices
+-----------------
+
+The ``microchip-icicle-kit`` machine supports the following devices:
+
+ * 1 E51 core
+ * 4 U54 cores
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * L2 Loosely Integrated Memory (L2-LIM)
+ * DDR memory controller
+ * 5 MMUARTs
+ * 1 DMA controller
+ * 2 GEM Ethernet controllers
+ * 1 SDHC storage controller
+
+Boot options
+------------
+
+The ``microchip-icicle-kit`` machine can start using the standard -bios
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
+support direct kernel loading via the -kernel option. One has to load kernel
+from U-Boot.
+
+The memory is set to 1537 MiB by default which is the minimum required high
+memory size by HSS. A sanity check on ram size is performed in the machine
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
+than 1537 MiB ram is detected.
+
+Boot the machine
+----------------
+
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
+in the HSS source tree:
+
+.. code-block:: bash
+
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ cp boards/mpfs-icicle-kit-es/def_config .config
+  $ make BOARD=mpfs-icicle-kit-es
+
+Download the official SD card image released by Microchip and prepare it for
+QEMU usage:
+
+.. code-block:: bash
+
+  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
+  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
+      -bios path/to/hss.bin -sd path/to/sdcard.img \
+      -nic user,model=cadence_gem \
+      -nic tap,ifname=tap,model=cadence_gem,script=no \
+      -display none -serial stdio \
+      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
+      -serial chardev:serial1
+
+With above command line, current terminal session will be used for the first
+serial port. Open another terminal window, and use `minicom` to connect the
+second serial port.
+
+.. code-block:: bash
+
+  $ minicom -D unix\#serial1.sock
+
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
+second serial port. U-Boot will automatically load the Linux kernel from
+the SD card image.
+
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microchip-icicle-kit
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.30.1

From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 179 +--------------------------------------
 1 file changed, 1 insertion(+), 178 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     CPUState *cs;
 } DisasContext;
 
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
-    [0 ... 7] = -1,
-    [0] = MO_SB,
-    [1] = MO_TESW,
-    [2] = MO_TESL,
-    [3] = MO_TEQ,
-    [4] = MO_UB,
-    [5] = MO_TEUW,
-    [6] = MO_TEUL,
-};
-#endif
-
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
 #else
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-        target_long imm)
-{
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-    gen_get_gpr(dat, rs2);
-    int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
-    if (memop < 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-}
-#endif
-
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 static inline void mark_fs_dirty(DisasContext *ctx) { }
 #endif
 
-#if !defined(TARGET_RISCV64)
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
-        int rs1, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FLW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
-        /* RISC-V requires NaN-boxing of narrower width floating point values */
-        tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
-        break;
-    case OPC_RISC_FLD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-
-    mark_fs_dirty(ctx);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
-        int rs2, target_long imm)
-{
-    TCGv t0;
-
-    if (ctx->mstatus_fs == 0) {
-        gen_exception_illegal(ctx);
-        return;
-    }
-
-    t0 = tcg_temp_new();
-    gen_get_gpr(t0, rs1);
-    tcg_gen_addi_tl(t0, t0, imm);
-
-    switch (opc) {
-    case OPC_RISC_FSW:
-        if (!has_ext(ctx, RVF)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
-        break;
-    case OPC_RISC_FSD:
-        if (!has_ext(ctx, RVD)) {
-            goto do_illegal;
-        }
-        tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
-        break;
-    do_illegal:
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-
-    tcg_temp_free(t0);
-}
-#endif
-
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
     TCGv_i32 t0;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t funct3 = extract16(opcode, 13, 3);
-    uint8_t rd_rs2 = GET_C_RS2S(opcode);
-    uint8_t rs1s = GET_C_RS1S(opcode);
-
-    switch (funct3) {
-    case 3:
-#if defined(TARGET_RISCV64)
-        /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-        gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
-                 GET_C_LD_IMM(opcode));
-#else
-        /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-        gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
-                    GET_C_LW_IMM(opcode));
-#endif
-        break;
-    case 7:
-#if defined(TARGET_RISCV64)
-        /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-        gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
-                  GET_C_LD_IMM(opcode));
-#else
-        /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-        gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
-                     GET_C_LW_IMM(opcode));
-#endif
-        break;
-    }
-}
-
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
-{
-    uint8_t op = extract16(opcode, 0, 2);
-
-    switch (op) {
-    case 0:
-        decode_RV32_64C0(ctx, opcode);
-        break;
-    }
-}
-
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
-                /* fall back to old decoder */
-                decode_RV32_64C(ctx, opcode);
+                gen_exception_illegal(ctx);
             }
         }
     } else {
-- 
2.30.1

The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd:

Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03 12:47:58 +0000)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103

for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870:

target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03 07:17:23 -0800)

----------------------------------------------------------------
This series adds support for migration to RISC-V QEMU and expands the
Microchip PFSoC to allow unmodified HSS and Linux boots.

----------------------------------------------------------------
Anup Patel (2):
      hw/riscv: sifive_u: Allow passing custom DTB
      hw/riscv: virt: Allow passing custom DTB

Bin Meng (10):
      hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
      hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
      hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
      hw/misc: Add Microchip PolarFire SoC IOSCB module support
      hw/riscv: microchip_pfsoc: Connect the IOSCB module
      hw/misc: Add Microchip PolarFire SoC SYSREG module support
      hw/riscv: microchip_pfsoc: Connect the SYSREG module
      hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
      hw/riscv: microchip_pfsoc: Correct DDR memory map
      hw/riscv: microchip_pfsoc: Hook the I2C1 controller

Xinhao Zhang (1):
      target/riscv/csr.c : add space before the open parenthesis '('

Yifei Jiang (6):
      target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
      target/riscv: Add basic vmstate description of CPU
      target/riscv: Add PMP state description
      target/riscv: Add H extension state description
      target/riscv: Add V extension state description
      target/riscv: Add sifive_plic vmstate

include/hw/intc/sifive_plic.h       |   1 +
 include/hw/misc/mchp_pfsoc_dmc.h    |  56 +++++++++
 include/hw/misc/mchp_pfsoc_ioscb.h  |  50 ++++++++
 include/hw/misc/mchp_pfsoc_sysreg.h |  39 ++++++
 include/hw/riscv/microchip_pfsoc.h  |  18 ++-
 target/riscv/cpu.h                  |  24 ++--
 target/riscv/cpu_bits.h             |  19 +--
 target/riscv/internals.h            |   4 +
 target/riscv/pmp.h                  |   2 +
 hw/intc/sifive_plic.c               |  26 +++-
 hw/misc/mchp_pfsoc_dmc.c            | 216 ++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_ioscb.c          | 242 ++++++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_sysreg.c         |  99 +++++++++++++++
 hw/riscv/microchip_pfsoc.c          | 125 ++++++++++++++++---
 hw/riscv/sifive_u.c                 |  28 +++--
 hw/riscv/virt.c                     |  27 ++--
 target/riscv/cpu.c                  |  16 +--
 target/riscv/cpu_helper.c           |  35 ++----
 target/riscv/csr.c                  |  20 +--
 target/riscv/machine.c              | 196 +++++++++++++++++++++++++++++
 target/riscv/op_helper.c            |  11 +-
 target/riscv/pmp.c                  |  29 +++--
 MAINTAINERS                         |   6 +
 hw/misc/Kconfig                     |   9 ++
 hw/misc/meson.build                 |   3 +
 hw/riscv/Kconfig                    |   3 +
 target/riscv/meson.build            |   3 +-
 27 files changed, 1180 insertions(+), 127 deletions(-)
 create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
 create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
 create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
 create mode 100644 hw/misc/mchp_pfsoc_dmc.c
 create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
 create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
 create mode 100644 target/riscv/machine.c

From: Anup Patel <anup.patel@wdc.com>

Extend sifive_u machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
or Linux SiFive DTB to sifive_u machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201022053225.2596110-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     int cpu;
     uint32_t *cells;
     char *nodename;
+    const char *dtb_filename;
     char ethclk_names[] = "pclk\0hclk";
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 
-    fdt = s->fdt = create_device_tree(&s->fdt_size);
-    if (!fdt) {
-        error_report("create_device_tree() failed");
-        exit(1);
+    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
+    if (dtb_filename) {
+        fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
+        if (!fdt) {
+            error_report("load_device_tree() failed");
+            exit(1);
+        }
+        goto update_bootargs;
+    } else {
+        fdt = s->fdt = create_device_tree(&s->fdt_size);
+        if (!fdt) {
+            error_report("create_device_tree() failed");
+            exit(1);
+        }
     }
 
     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
-    if (cmdline) {
-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-    }
-
     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 
     g_free(nodename);
+
+update_bootargs:
+    if (cmdline) {
+        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+    }
 }
 
 static void sifive_u_machine_reset(void *opaque, int n, int level)
-- 
2.28.0

From: Anup Patel <anup.patel@wdc.com>

Extend virt machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
to virt machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201022053225.2596110-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 {
     void *fdt;
     int i, cpu, socket;
+    const char *dtb_filename;
     MachineState *mc = MACHINE(s);
     uint64_t addr, size;
     uint32_t *clint_cells, *plic_cells;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 
-    fdt = s->fdt = create_device_tree(&s->fdt_size);
-    if (!fdt) {
-        error_report("create_device_tree() failed");
-        exit(1);
+    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
+    if (dtb_filename) {
+        fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
+        if (!fdt) {
+            error_report("load_device_tree() failed");
+            exit(1);
+        }
+        goto update_bootargs;
+    } else {
+        fdt = s->fdt = create_device_tree(&s->fdt_size);
+        if (!fdt) {
+            error_report("create_device_tree() failed");
+            exit(1);
+        }
     }
 
     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
-    if (cmdline) {
-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-    }
     g_free(name);
 
     name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
                                  2, flashbase + flashsize, 2, flashsize);
     qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
     g_free(name);
+
+update_bootargs:
+    if (cmdline) {
+        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+    }
 }
 
 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-- 
2.28.0

From: Yifei Jiang <jiangyifei@huawei.com>

mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
This patch expands mstatus and vsstatus to uint64_t instead of
target_ulong so that it can be saved as one unit and reduce some
ifdefs in the code.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-2-jiangyifei@huawei.com
---
 target/riscv/cpu.h        | 24 +++++++++++-------------
 target/riscv/cpu_bits.h   | 19 ++++---------------
 target/riscv/cpu.c        |  8 +++++---
 target/riscv/cpu_helper.c | 35 +++++++----------------------------
 target/riscv/csr.c        | 18 ++++++++++--------
 target/riscv/op_helper.c  | 11 ++++-------
 6 files changed, 41 insertions(+), 74 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong resetvec;
 
     target_ulong mhartid;
-    target_ulong mstatus;
+    /*
+     * For RV32 this is 32-bit mstatus and 32-bit mstatush.
+     * For RV64 this is a 64-bit mstatus.
+     */
+    uint64_t mstatus;
 
     target_ulong mip;
 
-#ifdef TARGET_RISCV32
-    target_ulong mstatush;
-#endif
-
     uint32_t miclaim;
 
     target_ulong mie;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     uint64_t htimedelta;
 
     /* Virtual CSRs */
-    target_ulong vsstatus;
+    /*
+     * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
+     * For RV64 this is a 64-bit vsstatus.
+     */
+    uint64_t vsstatus;
     target_ulong vstvec;
     target_ulong vsscratch;
     target_ulong vsepc;
     target_ulong vscause;
     target_ulong vstval;
     target_ulong vsatp;
-#ifdef TARGET_RISCV32
-    target_ulong vsstatush;
-#endif
 
     target_ulong mtval2;
     target_ulong mtinst;
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong scause_hs;
     target_ulong stval_hs;
     target_ulong satp_hs;
-    target_ulong mstatus_hs;
-#ifdef TARGET_RISCV32
-    target_ulong mstatush_hs;
-#endif
+    uint64_t mstatus_hs;
 
     target_ulong scounteren;
     target_ulong mcounteren;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_RISCV_CPU_BITS_H
 
 #define get_field(reg, mask) (((reg) & \
-                 (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
-#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
-                 (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
-                 (target_ulong)(mask)))
+                 (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
+                 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
+                 (uint64_t)(mask)))
 
 /* Floating point round mode */
 #define FSR_RD_SHIFT        5
@@ -XXX,XX +XXX,XX @@
 #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
 #define MSTATUS_TW          0x20000000 /* since: priv-1.10 */
 #define MSTATUS_TSR         0x40000000 /* since: priv-1.10 */
-#if defined(TARGET_RISCV64)
 #define MSTATUS_GVA         0x4000000000ULL
 #define MSTATUS_MPV         0x8000000000ULL
-#elif defined(TARGET_RISCV32)
-#define MSTATUS_GVA         0x00000040
-#define MSTATUS_MPV         0x00000080
-#endif
-
-#ifdef TARGET_RISCV32
-# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatush, MSTATUS_MPV)
-#else
-# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatus, MSTATUS_MPV)
-#endif
 
 #define MSTATUS64_UXL       0x0000000300000000ULL
 #define MSTATUS64_SXL       0x0000000C00000000ULL
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 #ifndef CONFIG_USER_ONLY
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 #ifdef TARGET_RISCV32
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+                 (target_ulong)(env->mstatus >> 32));
 #endif
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
+                     (target_ulong)env->vsstatus);
     }
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
 
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
-    target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
-                                MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
+    uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+                            MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
+                            MSTATUS64_UXL;
     bool current_virt = riscv_cpu_virt_enabled(env);
 
     g_assert(riscv_has_ext(env, RVH));
 
-#if defined(TARGET_RISCV64)
-    mstatus_mask |= MSTATUS64_UXL;
-#endif
-
     if (current_virt) {
         /* Current V=1 and we are about to change to V=0 */
         env->vsstatus = env->mstatus & mstatus_mask;
         env->mstatus &= ~mstatus_mask;
         env->mstatus |= env->mstatus_hs;
 
-#if defined(TARGET_RISCV32)
-        env->vsstatush = env->mstatush;
-        env->mstatush |= env->mstatush_hs;
-#endif
-
         env->vstvec = env->stvec;
         env->stvec = env->stvec_hs;
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
         env->mstatus &= ~mstatus_mask;
         env->mstatus |= env->vsstatus;
 
-#if defined(TARGET_RISCV32)
-        env->mstatush_hs = env->mstatush;
-        env->mstatush |= env->vsstatush;
-#endif
-
         env->stvec_hs = env->stvec;
         env->stvec = env->vstvec;
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
         access_type != MMU_INST_FETCH &&
         get_field(env->mstatus, MSTATUS_MPRV) &&
-        MSTATUS_MPV_ISSET(env)) {
+        get_field(env->mstatus, MSTATUS_MPV)) {
         riscv_cpu_set_two_stage_lookup(env, true);
     }
 
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
         access_type != MMU_INST_FETCH &&
         get_field(env->mstatus, MSTATUS_MPRV) &&
-        MSTATUS_MPV_ISSET(env)) {
+        get_field(env->mstatus, MSTATUS_MPV)) {
         riscv_cpu_set_two_stage_lookup(env, false);
     }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
-    target_ulong s;
+    uint64_t s;
 
     /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
      * so we mask off the MSB and separate into trap type and cause.
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             if (riscv_cpu_virt_enabled(env)) {
                 riscv_cpu_swap_hypervisor_regs(env);
             }
-#ifdef TARGET_RISCV32
-            env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
-                                       riscv_cpu_virt_enabled(env));
-            if (riscv_cpu_virt_enabled(env) && tval) {
-                env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
-            }
-#else
             env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
-                                      riscv_cpu_virt_enabled(env));
+                                     riscv_cpu_virt_enabled(env));
             if (riscv_cpu_virt_enabled(env) && tval) {
                 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
             }
-#endif
 
             mtval2 = env->guest_phys_fault_addr;
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
 
 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 {
-    target_ulong mstatus = env->mstatus;
-    target_ulong mask = 0;
+    uint64_t mstatus = env->mstatus;
+    uint64_t mask = 0;
     int dirty;
 
     /* flush tlb on mstatus fields that affect VM */
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 #ifdef TARGET_RISCV32
 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    *val = env->mstatush;
+    *val = env->mstatus >> 32;
     return 0;
 }
 
 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 {
-    if ((val ^ env->mstatush) & (MSTATUS_MPV)) {
+    uint64_t valh = (uint64_t)val << 32;
+    uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
+
+    if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
         tlb_flush(env_cpu(env));
     }
 
-    val &= MSTATUS_MPV | MSTATUS_GVA;
-
-    env->mstatush = val;
+    env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
 {
-    env->vsstatus = val;
+    uint64_t mask = (target_ulong)-1;
+    env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
     return 0;
 }
 
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
 
 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
 {
-    target_ulong prev_priv, prev_virt, mstatus;
+    uint64_t mstatus;
+    target_ulong prev_priv, prev_virt;
 
     if (!(env->priv >= PRV_S)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
         riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
     }
 
-    target_ulong mstatus = env->mstatus;
+    uint64_t mstatus = env->mstatus;
     target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
-    target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
+    target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
     mstatus = set_field(mstatus, MSTATUS_MIE,
                         get_field(mstatus, MSTATUS_MPIE));
     mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
     mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
-#ifdef TARGET_RISCV32
-    env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
-#else
     mstatus = set_field(mstatus, MSTATUS_MPV, 0);
-#endif
     env->mstatus = mstatus;
     riscv_cpu_set_mode(env, prev_priv);
 
-- 
2.28.0

From: Yifei Jiang <jiangyifei@huawei.com>

Add basic CPU state description to the newly created machine.c

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/internals.h |  4 +++
 target/riscv/cpu.c       |  8 +----
 target/riscv/machine.c   | 74 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  3 +-
 4 files changed, 81 insertions(+), 8 deletions(-)
 create mode 100644 target/riscv/machine.c

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1);
 #define SEW32 2
 #define SEW64 3
 
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
 static inline uint64_t nanbox_s(float32 f)
 {
     return f | MAKE_64BIT_MASK(32, 32);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/ctype.h"
 #include "qemu/log.h"
 #include "cpu.h"
+#include "internals.h"
 #include "exec/exec-all.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     cpu_set_cpustate_pointers(cpu);
 }
 
-#ifndef CONFIG_USER_ONLY
-static const VMStateDescription vmstate_riscv_cpu = {
-    .name = "cpu",
-    .unmigratable = 1,
-};
-#endif
-
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V VMState Description
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "migration/cpu.h"
+
+const VMStateDescription vmstate_riscv_cpu = {
+    .name = "cpu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+        VMSTATE_UINTTL(env.pc, RISCVCPU),
+        VMSTATE_UINTTL(env.load_res, RISCVCPU),
+        VMSTATE_UINTTL(env.load_val, RISCVCPU),
+        VMSTATE_UINTTL(env.frm, RISCVCPU),
+        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
+        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
+        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
+        VMSTATE_UINTTL(env.misa, RISCVCPU),
+        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+        VMSTATE_UINT32(env.features, RISCVCPU),
+        VMSTATE_UINTTL(env.priv, RISCVCPU),
+        VMSTATE_UINTTL(env.virt, RISCVCPU),
+        VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+        VMSTATE_UINT64(env.mstatus, RISCVCPU),
+        VMSTATE_UINTTL(env.mip, RISCVCPU),
+        VMSTATE_UINT32(env.miclaim, RISCVCPU),
+        VMSTATE_UINTTL(env.mie, RISCVCPU),
+        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
+        VMSTATE_UINTTL(env.satp, RISCVCPU),
+        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
+        VMSTATE_UINTTL(env.stvec, RISCVCPU),
+        VMSTATE_UINTTL(env.sepc, RISCVCPU),
+        VMSTATE_UINTTL(env.scause, RISCVCPU),
+        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
+        VMSTATE_UINTTL(env.mepc, RISCVCPU),
+        VMSTATE_UINTTL(env.mcause, RISCVCPU),
+        VMSTATE_UINTTL(env.mtval, RISCVCPU),
+        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
+        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
+        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
+        VMSTATE_UINT64(env.mtohost, RISCVCPU),
+        VMSTATE_UINT64(env.timecmp, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
   'pmp.c',
-  'monitor.c'
+  'monitor.c',
+  'machine.c'
 ))
 
 target_arch += {'riscv': riscv_ss}
-- 
2.28.0

From: Yifei Jiang <jiangyifei@huawei.com>

In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.

'vmstate_pmp_addr' and 'num_rules' could be regenerated by
pmp_update_rule(). But there exists the problem of updating
num_rules repeatedly in pmp_update_rule(). So here extracts
pmp_update_rule_addr() and pmp_update_rule_nums() to update
'vmstate_pmp_addr' and 'num_rules' respectively.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h     |  2 ++
 target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++
 target/riscv/pmp.c     | 29 ++++++++++++++----------
 3 files changed, 70 insertions(+), 11 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
     target_ulong size, pmp_priv_t priv, target_ulong mode);
 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
                          target_ulong *tlb_size);
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+void pmp_update_rule_nums(CPURISCVState *env);
 
 #endif
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "migration/cpu.h"
 
+static bool pmp_needed(void *opaque)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    return riscv_feature(env, RISCV_FEATURE_PMP);
+}
+
+static int pmp_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+    int i;
+
+    for (i = 0; i < MAX_RISCV_PMPS; i++) {
+        pmp_update_rule_addr(env, i);
+    }
+    pmp_update_rule_nums(env);
+
+    return 0;
+}
+
+static const VMStateDescription vmstate_pmp_entry = {
+    .name = "cpu/pmp/entry",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
+        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_pmp = {
+    .name = "cpu/pmp",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pmp_needed,
+    .post_load = pmp_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
+                             0, vmstate_pmp_entry, pmp_entry_t),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINT64(env.timecmp, RISCVCPU),
 
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_pmp,
+        NULL
     }
 };
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
     }
 }
 
-
-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
- *   end address values.
- *   This function is called relatively infrequently whereas the check that
- *   an address is within a pmp rule is called often, so optimise that one
- */
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
 {
-    int i;
-
-    env->pmp_state.num_rules = 0;
-
     uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
     target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
     target_ulong prev_addr = 0u;
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
 
     env->pmp_state.addr[pmp_index].sa = sa;
     env->pmp_state.addr[pmp_index].ea = ea;
+}
 
+void pmp_update_rule_nums(CPURISCVState *env)
+{
+    int i;
+
+    env->pmp_state.num_rules = 0;
     for (i = 0; i < MAX_RISCV_PMPS; i++) {
         const uint8_t a_field =
             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
@@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
     }
 }
 
+/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
+ *   end address values.
+ *   This function is called relatively infrequently whereas the check that
+ *   an address is within a pmp rule is called often, so optimise that one
+ */
+static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+{
+    pmp_update_rule_addr(env, pmp_index);
+    pmp_update_rule_nums(env);
+}
+
 static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
 {
     int result = 0;
-- 
2.28.0

From: Yifei Jiang <jiangyifei@huawei.com>

In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmp = {
     }
 };
 
+static bool hyper_needed(void *opaque)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    return riscv_has_ext(env, RVH);
+}
+
+static const VMStateDescription vmstate_hyper = {
+    .name = "cpu/hyper",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = hyper_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
+        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
+        VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
+        VMSTATE_UINTTL(env.htval, RISCVCPU),
+        VMSTATE_UINTTL(env.htinst, RISCVCPU),
+        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+        VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
+        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
+        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
+        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
+        VMSTATE_UINTTL(env.vscause, RISCVCPU),
+        VMSTATE_UINTTL(env.vstval, RISCVCPU),
+        VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+
+        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
+        VMSTATE_UINTTL(env.mtinst, RISCVCPU),
+
+        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
+        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
+        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
+        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
+        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
+        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
+        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
     },
     .subsections = (const VMStateDescription * []) {
         &vmstate_pmp,
+        &vmstate_hyper,
         NULL
     }
 };
-- 
2.28.0

From: Yifei Jiang <jiangyifei@huawei.com>

In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

From: Yifei Jiang <jiangyifei@huawei.com>

Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/sifive_plic.h |  1 +
 hw/intc/sifive_plic.c         | 26 +++++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -XXX,XX +XXX,XX @@ struct SiFivePLICState {
     uint32_t num_addrs;
     uint32_t num_harts;
     uint32_t bitfield_words;
+    uint32_t num_enables;
     PLICAddr *addr_config;
     uint32_t *source_priority;
     uint32_t *target_priority;
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/sifive_plic.h"
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
 
 #define RISCV_DEBUG_PLIC 0
 
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
                           TYPE_SIFIVE_PLIC, plic->aperture_size);
     parse_hart_config(plic);
     plic->bitfield_words = (plic->num_sources + 31) >> 5;
+    plic->num_enables = plic->bitfield_words * plic->num_addrs;
     plic->source_priority = g_new0(uint32_t, plic->num_sources);
     plic->target_priority = g_new(uint32_t, plic->num_addrs);
     plic->pending = g_new0(uint32_t, plic->bitfield_words);
     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
-    plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
+    plic->enable = g_new0(uint32_t, plic->num_enables);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
     msi_nonbroken = true;
 }
 
+static const VMStateDescription vmstate_sifive_plic = {
+    .name = "riscv_sifive_plic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+            VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
+                                  num_sources, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
+                                  num_addrs, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
+                                  vmstate_info_uint32, uint32_t),
+            VMSTATE_END_OF_LIST()
+        }
+};
+
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     device_class_set_props(dc, sifive_plic_properties);
     dc->realize = sifive_plic_realize;
+    dc->vmsd = &vmstate_sifive_plic;
 }
 
 static const TypeInfo sifive_plic_info = {
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

It is not easy to find out the memory map for a specific component
in the PolarFire SoC as the information is scattered in different
documents. Add some comments so that people can know where to get
such information from the Microchip website.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 /* GEM version */
 #define GEM_REVISION    0x0107010c
 
+/*
+ * The complete description of the whole PolarFire SoC memory map is scattered
+ * in different documents. There are several places to look at for memory maps:
+ *
+ * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
+ *   Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
+ *   https://www.microsemi.com/document-portal/doc_download/
+ *   1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
+ *   describes the whole picture of the PolarFire SoC memory map.
+ *
+ * 2 A zip file for PolarFire soC memory map, which can be downloaded from
+ *   https://www.microsemi.com/document-portal/doc_download/
+ *   1244581-polarfire-soc-register-map, contains the following 2 major parts:
+ *   - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
+ *     describes the complete integrated peripherals memory map
+ *   - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ *     describes the complete IOSCB modules memory maps
+ */
 static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.

This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/misc/mchp_pfsoc_dmc.h |  56 ++++++++
 hw/misc/mchp_pfsoc_dmc.c         | 216 +++++++++++++++++++++++++++++++
 MAINTAINERS                      |   2 +
 hw/misc/Kconfig                  |   3 +
 hw/misc/meson.build              |   1 +
 5 files changed, 278 insertions(+)
 create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
 create mode 100644 hw/misc/mchp_pfsoc_dmc.c

diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_dmc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC DDR Memory Controller module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_DMC_H
+#define MCHP_PFSOC_DMC_H
+
+/* DDR SGMII PHY module */
+
+#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE   0x1000
+
+typedef struct MchpPfSoCDdrSgmiiPhyState {
+    SysBusDevice parent;
+    MemoryRegion sgmii_phy;
+} MchpPfSoCDdrSgmiiPhyState;
+
+#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
+
+#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
+    OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
+                 TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
+
+/* DDR CFG module */
+
+#define MCHP_PFSOC_DDR_CFG_REG_SIZE         0x40000
+
+typedef struct MchpPfSoCDdrCfgState {
+    SysBusDevice parent;
+    MemoryRegion cfg;
+} MchpPfSoCDdrCfgState;
+
+#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
+
+#define MCHP_PFSOC_DDR_CFG(obj) \
+    OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
+                 TYPE_MCHP_PFSOC_DDR_CFG)
+
+#endif /* MCHP_PFSOC_DMC_H */
diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_dmc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC DDR Memory Controller module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
+
+/* DDR SGMII PHY module */
+
+#define SGMII_PHY_IOC_REG1              0x208
+#define SGMII_PHY_TRAINING_STATUS       0x814
+#define SGMII_PHY_DQ_DQS_ERR_DONE       0x834
+#define SGMII_PHY_DQDQS_STATUS1         0x84c
+#define SGMII_PHY_PVT_STAT              0xc20
+
+static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
+                                              unsigned size)
+{
+    uint32_t val = 0;
+    static int training_status_bit;
+
+    switch (offset) {
+    case SGMII_PHY_IOC_REG1:
+        /* See ddr_pvt_calibration() in HSS */
+        val = BIT(4) | BIT(2);
+        break;
+    case SGMII_PHY_TRAINING_STATUS:
+        /*
+         * The codes logic emulates the training status change from
+         * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
+         *
+         * See ddr_setup() in mss_ddr.c in the HSS source codes.
+         */
+        val = 1 << training_status_bit;
+        training_status_bit = (training_status_bit + 1) % 5;
+        break;
+    case SGMII_PHY_DQ_DQS_ERR_DONE:
+        /*
+         * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+         * check that DQ/DQS training passed without error.
+         */
+        val = 8;
+        break;
+    case SGMII_PHY_DQDQS_STATUS1:
+        /*
+         * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+         * check that DQ/DQS calculated window is above 5 taps.
+         */
+        val = 0xff;
+        break;
+    case SGMII_PHY_PVT_STAT:
+        /* See sgmii_channel_setup() in HSS */
+        val = BIT(14) | BIT(6);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+        break;
+    }
+
+    return val;
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
+                                           uint64_t value, unsigned size)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
+    .read = mchp_pfsoc_ddr_sgmii_phy_read,
+    .write = mchp_pfsoc_ddr_sgmii_phy_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
+
+    memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
+                          &mchp_pfsoc_ddr_sgmii_phy_ops, s,
+                          "mchp.pfsoc.ddr_sgmii_phy",
+                          MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
+    dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
+    .name          = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
+    .class_init    = mchp_pfsoc_ddr_sgmii_phy_class_init,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
+}
+
+type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
+
+/* DDR CFG module */
+
+#define CFG_MT_DONE_ACK                 0x4428
+#define CFG_STAT_DFI_INIT_COMPLETE      0x10034
+#define CFG_STAT_DFI_TRAINING_COMPLETE  0x10038
+
+static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
+                                        unsigned size)
+{
+    uint32_t val = 0;
+
+    switch (offset) {
+    case CFG_MT_DONE_ACK:
+        /* memory test in MTC_test() */
+        val = BIT(0);
+        break;
+    case CFG_STAT_DFI_INIT_COMPLETE:
+        /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
+        val = BIT(0);
+        break;
+    case CFG_STAT_DFI_TRAINING_COMPLETE:
+        /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
+        val = BIT(0);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+        break;
+    }
+
+    return val;
+}
+
+static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
+                                     uint64_t value, unsigned size)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
+    .read = mchp_pfsoc_ddr_cfg_read,
+    .write = mchp_pfsoc_ddr_cfg_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
+
+    memory_region_init_io(&s->cfg, OBJECT(dev),
+                          &mchp_pfsoc_ddr_cfg_ops, s,
+                          "mchp.pfsoc.ddr_cfg",
+                          MCHP_PFSOC_DDR_CFG_REG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
+}
+
+static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "Microchip PolarFire SoC DDR CFG module";
+    dc->realize = mchp_pfsoc_ddr_cfg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
+    .name          = TYPE_MCHP_PFSOC_DDR_CFG,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCDdrCfgState),
+    .class_init    = mchp_pfsoc_ddr_cfg_class_init,
+};
+
+static void mchp_pfsoc_ddr_cfg_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_ddr_cfg_info);
+}
+
+type_init(mchp_pfsoc_ddr_cfg_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/microchip_pfsoc.c
 F: hw/char/mchp_pfsoc_mmuart.c
+F: hw/misc/mchp_pfsoc_dmc.c
 F: include/hw/riscv/microchip_pfsoc.h
 F: include/hw/char/mchp_pfsoc_mmuart.h
+F: include/hw/misc/mchp_pfsoc_dmc.h
 
 RX Machines
 -----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config MCHP_PFSOC_DMC
+    bool
+
 config SIFIVE_TEST
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  5 +++++
 hw/riscv/microchip_pfsoc.c         | 18 ++++++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 24 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
 #include "hw/dma/sifive_pdma.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     RISCVHartArrayState e_cpus;
     RISCVHartArrayState u_cpus;
     DeviceState *plic;
+    MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
+    MchpPfSoCDdrCfgState ddr_cfg;
     MchpPfSoCMMUartState *serial0;
     MchpPfSoCMMUartState *serial1;
     MchpPfSoCMMUartState *serial2;
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART0,
     MICROCHIP_PFSOC_SYSREG,
     MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_DDR_SGMII_PHY,
     MICROCHIP_PFSOC_EMMC_SD,
+    MICROCHIP_PFSOC_DDR_CFG,
     MICROCHIP_PFSOC_MMUART1,
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  * 5) SiFive Platform DMA (Direct Memory Access Controller)
  * 6) GEM (Gigabit Ethernet MAC Controller)
+ * 7) DMC (DDR Memory Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,     0x1000 },
     [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
+    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,    0x40000 },
     [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     object_initialize_child(obj, "dma-controller", &s->dma,
                             TYPE_SIFIVE_PDMA);
 
+    object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
+                            TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
+    object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
+                            TYPE_MCHP_PFSOC_DDR_CFG);
+
     object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
     object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
 
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_MPUCFG].base,
         memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+    /* DDR SGMII PHY */
+    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
+                    memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
+
+    /* DDR CFG */
+    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
+                    memmap[MICROCHIP_PFSOC_DDR_CFG].base);
+
     /* SDHCI */
     sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config IBEX
 config MICROCHIP_PFSOC
     bool
     select CADENCE_SDHCI
+    select MCHP_PFSOC_DMC
     select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This creates a model for PolarFire SoC IOSCB [1] module. It actually
contains lots of sub-modules like various PLLs to control different
peripherals. Only the mininum capabilities are emulated to make the
HSS DDR memory initialization codes happy. Lots of sub-modules are
created as an unimplemented devices.

[1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
    https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/misc/mchp_pfsoc_ioscb.h |  50 ++++++
 hw/misc/mchp_pfsoc_ioscb.c         | 242 +++++++++++++++++++++++++++++
 MAINTAINERS                        |   2 +
 hw/misc/Kconfig                    |   3 +
 hw/misc/meson.build                |   1 +
 5 files changed, 298 insertions(+)
 create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
 create mode 100644 hw/misc/mchp_pfsoc_ioscb.c

diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_ioscb.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC IOSCB module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_IOSCB_H
+#define MCHP_PFSOC_IOSCB_H
+
+typedef struct MchpPfSoCIoscbState {
+    SysBusDevice parent;
+    MemoryRegion container;
+    MemoryRegion lane01;
+    MemoryRegion lane23;
+    MemoryRegion ctrl;
+    MemoryRegion cfg;
+    MemoryRegion pll_mss;
+    MemoryRegion cfm_mss;
+    MemoryRegion pll_ddr;
+    MemoryRegion bc_ddr;
+    MemoryRegion io_calib_ddr;
+    MemoryRegion pll_sgmii;
+    MemoryRegion dll_sgmii;
+    MemoryRegion cfm_sgmii;
+    MemoryRegion bc_sgmii;
+    MemoryRegion io_calib_sgmii;
+} MchpPfSoCIoscbState;
+
+#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
+
+#define MCHP_PFSOC_IOSCB(obj) \
+    OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB)
+
+#endif /* MCHP_PFSOC_IOSCB_H */
diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_ioscb.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC IOSCB module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
+
+/*
+ * The whole IOSCB module registers map into the system address at 0x3000_0000,
+ * named as "System Port 0 (AXI-D0)".
+ */
+#define IOSCB_WHOLE_REG_SIZE        0x10000000
+#define IOSCB_SUBMOD_REG_SIZE       0x1000
+
+/*
+ * There are many sub-modules in the IOSCB module.
+ * See Microchip PolarFire SoC documentation (Register_Map.zip),
+ * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ *
+ * The following are sub-modules offsets that are of concern.
+ */
+#define IOSCB_LANE01_BASE           0x06500000
+#define IOSCB_LANE23_BASE           0x06510000
+#define IOSCB_CTRL_BASE             0x07020000
+#define IOSCB_CFG_BASE              0x07080000
+#define IOSCB_PLL_MSS_BASE          0x0E001000
+#define IOSCB_CFM_MSS_BASE          0x0E002000
+#define IOSCB_PLL_DDR_BASE          0x0E010000
+#define IOSCB_BC_DDR_BASE           0x0E020000
+#define IOSCB_IO_CALIB_DDR_BASE     0x0E040000
+#define IOSCB_PLL_SGMII_BASE        0x0E080000
+#define IOSCB_DLL_SGMII_BASE        0x0E100000
+#define IOSCB_CFM_SGMII_BASE        0x0E200000
+#define IOSCB_BC_SGMII_BASE         0x0E400000
+#define IOSCB_IO_CALIB_SGMII_BASE   0x0E800000
+
+static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                  __func__, size, offset);
+
+    return 0;
+}
+
+static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
+    .read = mchp_pfsoc_dummy_read,
+    .write = mchp_pfsoc_dummy_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* All PLL modules in IOSCB have the same register layout */
+
+#define PLL_CTRL    0x04
+
+static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
+                                    unsigned size)
+{
+    uint32_t val = 0;
+
+    switch (offset) {
+    case PLL_CTRL:
+        /* PLL is locked */
+        val = BIT(25);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+        break;
+    }
+
+    return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_pll_ops = {
+    .read = mchp_pfsoc_pll_read,
+    .write = mchp_pfsoc_dummy_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* IO_CALIB_DDR submodule */
+
+#define IO_CALIB_DDR_IOC_REG1   0x08
+
+static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
+                                             unsigned size)
+{
+    uint32_t val = 0;
+
+    switch (offset) {
+    case IO_CALIB_DDR_IOC_REG1:
+        /* calibration completed */
+        val = BIT(2);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+        break;
+    }
+
+    return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
+    .read = mchp_pfsoc_io_calib_ddr_read,
+    .write = mchp_pfsoc_dummy_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+    memory_region_init(&s->container, OBJECT(s),
+                       "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
+    sysbus_init_mmio(sbd, &s->container);
+
+    /* add subregions for all sub-modules in IOSCB */
+
+    memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
+
+    memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
+
+    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
+
+    memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
+
+    memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+                          "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
+
+    memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
+
+    memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+                          "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
+
+    memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
+
+    memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
+                          &mchp_pfsoc_io_calib_ddr_ops, s,
+                          "mchp.pfsoc.ioscb.io_calib_ddr",
+                          IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
+                                &s->io_calib_ddr);
+
+    memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+                          "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
+                                &s->pll_sgmii);
+
+    memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
+                                &s->dll_sgmii);
+
+    memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
+                                &s->cfm_sgmii);
+
+    memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
+                                &s->bc_sgmii);
+
+    memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
+                          s, "mchp.pfsoc.ioscb.io_calib_sgmii",
+                          IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
+                                &s->io_calib_sgmii);
+}
+
+static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "Microchip PolarFire SoC IOSCB modules";
+    dc->realize = mchp_pfsoc_ioscb_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ioscb_info = {
+    .name          = TYPE_MCHP_PFSOC_IOSCB,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCIoscbState),
+    .class_init    = mchp_pfsoc_ioscb_class_init,
+};
+
+static void mchp_pfsoc_ioscb_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_ioscb_info);
+}
+
+type_init(mchp_pfsoc_ioscb_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Supported
 F: hw/riscv/microchip_pfsoc.c
 F: hw/char/mchp_pfsoc_mmuart.c
 F: hw/misc/mchp_pfsoc_dmc.c
+F: hw/misc/mchp_pfsoc_ioscb.c
 F: include/hw/riscv/microchip_pfsoc.h
 F: include/hw/char/mchp_pfsoc_mmuart.h
 F: include/hw/misc/mchp_pfsoc_dmc.h
+F: include/hw/misc/mchp_pfsoc_ioscb.h
 
 RX Machines
 -----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
 config MCHP_PFSOC_DMC
     bool
 
+config MCHP_PFSOC_IOSCB
+    bool
+
 config SIFIVE_TEST
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  4 +++-
 hw/riscv/microchip_pfsoc.c         | 13 ++++++++-----
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/mchp_pfsoc_mmuart.h"
 #include "hw/dma/sifive_pdma.h"
 #include "hw/misc/mchp_pfsoc_dmc.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     DeviceState *plic;
     MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
     MchpPfSoCDdrCfgState ddr_cfg;
+    MchpPfSoCIoscbState ioscb;
     MchpPfSoCMMUartState *serial0;
     MchpPfSoCMMUartState *serial1;
     MchpPfSoCMMUartState *serial2;
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_GPIO2,
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
-    MICROCHIP_PFSOC_IOSCB_CFG,
+    MICROCHIP_PFSOC_IOSCB,
     MICROCHIP_PFSOC_DRAM,
 };
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 5) SiFive Platform DMA (Direct Memory Access Controller)
  * 6) GEM (Gigabit Ethernet MAC Controller)
  * 7) DMC (DDR Memory Controller)
+ * 8) IOSCB modules
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
-    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
+    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
     [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
 };
 
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
 
     object_initialize_child(obj, "sd-controller", &s->sdhci,
                             TYPE_CADENCE_SDHCI);
+
+    object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
 }
 
 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
                                 memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
                                 envm_data);
 
-    /* IOSCBCFG */
-    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
-        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
-        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+    /* IOSCB */
+    sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+                    memmap[MICROCHIP_PFSOC_IOSCB].base);
 }
 
 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     bool
     select CADENCE_SDHCI
     select MCHP_PFSOC_DMC
+    select MCHP_PFSOC_IOSCB
     select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This creates a minimum model for Microchip PolarFire SoC SYSREG
module. It only implements the ENVM_CR register to tell guest
software that eNVM is running at the configured divider rate.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++
 hw/misc/mchp_pfsoc_sysreg.c         | 99 +++++++++++++++++++++++++++++
 MAINTAINERS                         |  2 +
 hw/misc/Kconfig                     |  3 +
 hw/misc/meson.build                 |  1 +
 5 files changed, 144 insertions(+)
 create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
 create mode 100644 hw/misc/mchp_pfsoc_sysreg.c

diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_sysreg.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC SYSREG module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_SYSREG_H
+#define MCHP_PFSOC_SYSREG_H
+
+#define MCHP_PFSOC_SYSREG_REG_SIZE  0x2000
+
+typedef struct MchpPfSoCSysregState {
+    SysBusDevice parent;
+    MemoryRegion sysreg;
+} MchpPfSoCSysregState;
+
+#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
+
+#define MCHP_PFSOC_SYSREG(obj) \
+    OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
+                 TYPE_MCHP_PFSOC_SYSREG)
+
+#endif /* MCHP_PFSOC_SYSREG_H */
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC SYSREG module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
+
+#define ENVM_CR         0xb8
+
+static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
+                                       unsigned size)
+{
+    uint32_t val = 0;
+
+    switch (offset) {
+    case ENVM_CR:
+        /* Indicate the eNVM is running at the configured divider rate */
+        val = BIT(6);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+        break;
+    }
+
+    return val;
+}
+
+static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
+                                    uint64_t value, unsigned size)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
+    .read = mchp_pfsoc_sysreg_read,
+    .write = mchp_pfsoc_sysreg_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
+
+    memory_region_init_io(&s->sysreg, OBJECT(dev),
+                          &mchp_pfsoc_sysreg_ops, s,
+                          "mchp.pfsoc.sysreg",
+                          MCHP_PFSOC_SYSREG_REG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
+}
+
+static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "Microchip PolarFire SoC SYSREG module";
+    dc->realize = mchp_pfsoc_sysreg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_sysreg_info = {
+    .name          = TYPE_MCHP_PFSOC_SYSREG,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCSysregState),
+    .class_init    = mchp_pfsoc_sysreg_class_init,
+};
+
+static void mchp_pfsoc_sysreg_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_sysreg_info);
+}
+
+type_init(mchp_pfsoc_sysreg_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/riscv/microchip_pfsoc.c
 F: hw/char/mchp_pfsoc_mmuart.c
 F: hw/misc/mchp_pfsoc_dmc.c
 F: hw/misc/mchp_pfsoc_ioscb.c
+F: hw/misc/mchp_pfsoc_sysreg.c
 F: include/hw/riscv/microchip_pfsoc.h
 F: include/hw/char/mchp_pfsoc_mmuart.h
 F: include/hw/misc/mchp_pfsoc_dmc.h
 F: include/hw/misc/mchp_pfsoc_ioscb.h
+F: include/hw/misc/mchp_pfsoc_sysreg.h
 
 RX Machines
 -----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MCHP_PFSOC_DMC
 config MCHP_PFSOC_IOSCB
     bool
 
+config MCHP_PFSOC_SYSREG
+    bool
+
 config SIFIVE_TEST
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 2 ++
 hw/riscv/microchip_pfsoc.c         | 9 ++++++---
 hw/riscv/Kconfig                   | 1 +
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/dma/sifive_pdma.h"
 #include "hw/misc/mchp_pfsoc_dmc.h"
 #include "hw/misc/mchp_pfsoc_ioscb.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial2;
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
+    MchpPfSoCSysregState sysreg;
     SiFivePDMAState dma;
     CadenceGEMState gem0;
     CadenceGEMState gem1;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     object_initialize_child(obj, "dma-controller", &s->dma,
                             TYPE_SIFIVE_PDMA);
 
+    object_initialize_child(obj, "sysreg", &s->sysreg,
+                            TYPE_MCHP_PFSOC_SYSREG);
+
     object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
                             TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
     object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     }
 
     /* SYSREG */
-    create_unimplemented_device("microchip.pfsoc.sysreg",
-        memmap[MICROCHIP_PFSOC_SYSREG].base,
-        memmap[MICROCHIP_PFSOC_SYSREG].size);
+    sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
+                    memmap[MICROCHIP_PFSOC_SYSREG].base);
 
     /* MPUCFG */
     create_unimplemented_device("microchip.pfsoc.mpucfg",
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select MCHP_PFSOC_DMC
     select MCHP_PFSOC_IOSCB
     select MCHP_PFSOC_MMUART
+    select MCHP_PFSOC_SYSREG
     select MSI_NONBROKEN
     select SIFIVE_CLINT
     select SIFIVE_PDMA
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.

[1] See the config_copy() calls in various places in ddr_setup() in
    the HSS source codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  1 +
 hw/riscv/microchip_pfsoc.c         | 11 ++++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

From: Bin Meng <bin.meng@windriver.com>

When system memory is larger than 1 GiB (high memory), PolarFire SoC
maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
aliased to the same 1 GiB low memory with different cache attributes.

At present QEMU maps the system memory contiguously from 0x8000_0000.
This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
the alias to the high memory, and even physical memory is only 1 GiB,
the HSS codes still tries to probe the high memory alias address.
It seems there is no issue on the real hardware, so we will have to
take that into the consideration in our emulation. Due to this, we
we increase the default system memory size to 1537 MiB (the minimum
required high memory size by HSS) so that user gets notified an error
when less than 1537 MiB is specified.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  5 ++-
 hw/riscv/microchip_pfsoc.c         | 50 ++++++++++++++++++++++++++----
 2 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_IOSCB,
-    MICROCHIP_PFSOC_DRAM,
+    MICROCHIP_PFSOC_DRAM_LO,
+    MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+    MICROCHIP_PFSOC_DRAM_HI,
+    MICROCHIP_PFSOC_DRAM_HI_ALIAS
 };
 
 enum {
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
-    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
+    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
+    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
+    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,        0x0 },
 };
 
 static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
     MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *mem_low = g_new(MemoryRegion, 1);
+    MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
+    MemoryRegion *mem_high = g_new(MemoryRegion, 1);
+    MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
+    uint64_t mem_high_size;
     DriveInfo *dinfo = drive_get_next(IF_SD);
 
     /* Sanity check on RAM size */
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* Register RAM */
-    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
-                           machine->ram_size, &error_fatal);
+    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
+                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+                           &error_fatal);
+    memory_region_init_alias(mem_low_alias, NULL,
+                             "microchip.icicle.kit.ram_low.alias",
+                             mem_low, 0,
+                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+                                mem_low);
     memory_region_add_subregion(system_memory,
-                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+                                memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
+                                mem_low_alias);
+
+    mem_high_size = machine->ram_size - 1 * GiB;
+
+    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
+                           mem_high_size, &error_fatal);
+    memory_region_init_alias(mem_high_alias, NULL,
+                             "microchip.icicle.kit.ram_high.alias",
+                             mem_high, 0, mem_high_size);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+                                mem_high);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
+                                mem_high_alias);
 
     /* Load the firmware */
     riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                    MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
     mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpus = mc->min_cpus;
-    mc->default_ram_size = 1 * GiB;
+
+    /*
+     * Map 513 MiB high memory, the mimimum required high memory size, because
+     * HSS will do memory test against the high memory address range regardless
+     * of physical memory installed.
+     *
+     * See memory_tests() in mss_ddr.c in the HSS source code.
+     */
+    mc->default_ram_size = 1537 * MiB;
 }
 
 static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.

It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.

[1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

From: Xinhao Zhang <zhangxinhao1@huawei.com>

Fix code style. Space required before the open parenthesis '('.

Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reported-by: Euler Robot <euler.robot@huawei.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return -RISCV_EXCP_ILLEGAL_INST;
         } else {
-            if((val ^ env->satp) & SATP_ASID) {
+            if ((val ^ env->satp) & SATP_ASID) {
                 tlb_flush(env_cpu(env));
             }
             env->satp = val;
-- 
2.28.0