This is intending to fix the current aarch64 host failure
for s390x guest cdrom-test.  This is caused by the io thread
issuing memory barriers that are supposed to be matched by
the vcpu, but are elided by tcg in rr mode as "unnecessary".

I know Peter would like a smaller patch to sync the io thread
with the vcpu thread.  I've made a couple of attempts at this,
but havn't managed to get something reliable (although now
irritatingly infrequent -- about 1 in 500).

I have further patches to further optimize barriers, and to
generate load-acquire/store-release instructions in tcg.
But it's late in the release cycle, etc etc.

I've done nothing to measure the performance impact of this.
I quit the cdtom-test cycle after 4000 passes.


r~


Richard Henderson (5):
  tcg: Decode the operand to INDEX_op_mb in dumps
  tcg: Do not elide memory barriers for CF_PARALLEL
  tcg: Elide memory barriers implied by the host memory model
  tcg: Create tcg_req_mo
  tcg: Add host memory barriers to cpu_ldst.h interfaces

 include/exec/cpu_ldst.h |  7 ++++
 include/tcg/tcg.h       | 20 +++++++++++
 accel/tcg/cputlb.c      |  2 ++
 accel/tcg/tcg-all.c     |  6 +---
 accel/tcg/user-exec.c   | 17 +++++++++
 tcg/tcg-op.c            | 19 +++++-----
 tcg/tcg.c               | 79 +++++++++++++++++++++++++++++++++++++++++
 7 files changed, 137 insertions(+), 13 deletions(-)

-- 
2.25.1

Patchew URL: https://patchew.org/QEMU/20210316220735.2048137-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210316220735.2048137-1-richard.henderson@linaro.org
Subject: [PATCH 0/5] tcg: Issue memory barriers for guest memory model

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20210311143958.562625-1-richard.henderson@linaro.org -> patchew/20210311143958.562625-1-richard.henderson@linaro.org
 * [new tag]         patchew/20210316220735.2048137-1-richard.henderson@linaro.org -> patchew/20210316220735.2048137-1-richard.henderson@linaro.org
Switched to a new branch 'test'
06ceb5a tcg: Add host memory barriers to cpu_ldst.h interfaces
be4ade5 tcg: Create tcg_req_mo
1336778 tcg: Elide memory barriers implied by the host memory model
d0f90d5 tcg: Do not elide memory barriers for CF_PARALLEL
c9f634b tcg: Decode the operand to INDEX_op_mb in dumps

=== OUTPUT BEGIN ===
1/5 Checking commit c9f634bdbe20 (tcg: Decode the operand to INDEX_op_mb in dumps)
2/5 Checking commit d0f90d584f17 (tcg: Do not elide memory barriers for CF_PARALLEL)
3/5 Checking commit 133677838f14 (tcg: Elide memory barriers implied by the host memory model)
4/5 Checking commit be4ade51a457 (tcg: Create tcg_req_mo)
5/5 Checking commit 06ceb5ad212a (tcg: Add host memory barriers to cpu_ldst.h interfaces)
ERROR: memory barrier without comment
#189: FILE: include/exec/cpu_ldst.h:175:
+            smp_mb();             \

total: 1 errors, 0 warnings, 146 lines checked

Patch 5/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210316220735.2048137-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Ping.  A local rebase seems to apply clean.

r~

On 3/16/21 3:07 PM, Richard Henderson wrote:
> This is intending to fix the current aarch64 host failure
> for s390x guest cdrom-test.  This is caused by the io thread
> issuing memory barriers that are supposed to be matched by
> the vcpu, but are elided by tcg in rr mode as "unnecessary".
> 
> I know Peter would like a smaller patch to sync the io thread
> with the vcpu thread.  I've made a couple of attempts at this,
> but havn't managed to get something reliable (although now
> irritatingly infrequent -- about 1 in 500).
> 
> I have further patches to further optimize barriers, and to
> generate load-acquire/store-release instructions in tcg.
> But it's late in the release cycle, etc etc.
> 
> I've done nothing to measure the performance impact of this.
> I quit the cdtom-test cycle after 4000 passes.
> 
> 
> r~
> 
> 
> Richard Henderson (5):
>    tcg: Decode the operand to INDEX_op_mb in dumps
>    tcg: Do not elide memory barriers for CF_PARALLEL
>    tcg: Elide memory barriers implied by the host memory model
>    tcg: Create tcg_req_mo
>    tcg: Add host memory barriers to cpu_ldst.h interfaces
> 
>   include/exec/cpu_ldst.h |  7 ++++
>   include/tcg/tcg.h       | 20 +++++++++++
>   accel/tcg/cputlb.c      |  2 ++
>   accel/tcg/tcg-all.c     |  6 +---
>   accel/tcg/user-exec.c   | 17 +++++++++
>   tcg/tcg-op.c            | 19 +++++-----
>   tcg/tcg.c               | 79 +++++++++++++++++++++++++++++++++++++++++
>   7 files changed, 137 insertions(+), 13 deletions(-)
>