[PULL 00/39] target-arm queue
[PULL 00/32] target-arm queue
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Last pullreq before 6.0 softfreeze: a few minor feature patches,
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target-arm queue: the big stuff here is the final part of
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some bugfixes, some cleanups.
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rth's patches for Cortex-A76 and Neoverse-N1 support;
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also present are Gavin's NUMA series and a few other things.
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4
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thanks
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-- PMM
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-- PMM
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The following changes since commit 6f34661b6c97a37a5efc27d31c037ddeda4547e2:
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The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2021-03-11 18:55:27 +0000)
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Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210312-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
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for you to fetch changes up to 41f09f2e9f09e4dd386d84174a6dcb5136af17ca:
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for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
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hw/display/pxa2xx: Inline template header (2021-03-12 13:26:08 +0000)
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hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* versal: Support XRAMs and XRAM controller
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* MAINTAINERS/.mailmap: update email for Leif Lindholm
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* smmu: Various minor bug fixes
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* hw/arm: add version information to sbsa-ref machine DT
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* SVE emulation: fix bugs handling odd vector lengths
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* Enable new features for -cpu max:
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* allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
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* tests/acceptance: fix orangepi-pc acceptance tests
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FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
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* hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
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* Emulate Cortex-A76
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* hw/arm/virt: KVM: The IPA lower bound is 32
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* Emulate Neoverse-N1
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* npcm7xx: support MFT module
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* Fix the virt board default NUMA topology
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* pl110, pxa2xx_lcd: tidy up template headers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jones (2):
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Gavin Shan (6):
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accel: kvm: Fix kvm_type invocation
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qapi/machine.json: Add cluster-id
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hw/arm/virt: KVM: The IPA lower bound is 32
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qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
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hw/arm/virt: Consider SMP configuration in CPU topology
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qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
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hw/arm/virt: Fix CPU's default NUMA node ID
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hw/acpi/aml-build: Use existing CPU topology to build PPTT table
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39
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Edgar E. Iglesias (2):
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Leif Lindholm (2):
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hw/misc: versal: Add a model of the XRAM controller
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MAINTAINERS/.mailmap: update email for Leif Lindholm
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hw/arm: versal: Add support for the XRAMs
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hw/arm: add versioning to sbsa-ref machine DT
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Eric Auger (7):
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Richard Henderson (24):
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intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
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target/arm: Handle cpreg registration for missing EL
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dma: Introduce dma_aligned_pow2_mask()
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target/arm: Drop EL3 no EL2 fallbacks
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virtio-iommu: Handle non power of 2 range invalidations
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target/arm: Merge zcr reginfo
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hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
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target/arm: Adjust definition of CONTEXTIDR_EL2
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hw/arm/smmuv3: Enforce invalidation on a power of two range
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target/arm: Move cortex impdef sysregs to cpu_tcg.c
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hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
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target/arm: Update qemu-system-arm -cpu max to cortex-a57
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hw/arm/smmuv3: Uniformize sid traces
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target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
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target/arm: Split out aa32_max_features
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target/arm: Annotate arm_max_initfn with FEAT identifiers
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target/arm: Use field names for manipulating EL2 and EL3 modes
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target/arm: Enable FEAT_Debugv8p2 for -cpu max
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target/arm: Enable FEAT_Debugv8p4 for -cpu max
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target/arm: Add minimal RAS registers
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target/arm: Enable SCR and HCR bits for RAS
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target/arm: Implement virtual SError exceptions
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target/arm: Implement ESB instruction
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target/arm: Enable FEAT_RAS for -cpu max
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target/arm: Enable FEAT_IESB for -cpu max
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target/arm: Enable FEAT_CSV2 for -cpu max
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target/arm: Enable FEAT_CSV2_2 for -cpu max
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target/arm: Enable FEAT_CSV3 for -cpu max
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target/arm: Enable FEAT_DGH for -cpu max
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target/arm: Define cortex-a76
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target/arm: Define neoverse-n1
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69
48
Hao Wu (5):
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docs/system/arm/emulation.rst | 10 +
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hw/misc: Add GPIOs for duty in NPCM7xx PWM
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docs/system/arm/virt.rst | 2 +
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hw/misc: Add NPCM7XX MFT Module
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qapi/machine.json | 6 +-
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hw/arm: Add MFT device to NPCM7xx Soc
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target/arm/cpregs.h | 11 +
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hw/arm: Connect PWM fans in NPCM7XX boards
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target/arm/cpu.h | 23 ++
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tests/qtest: Test PWM fan RPM using MFT in PWM test
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target/arm/helper.h | 1 +
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target/arm/internals.h | 16 ++
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Niek Linnenbank (5):
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target/arm/syndrome.h | 5 +
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hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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target/arm/a32.decode | 16 +-
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tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
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target/arm/t32.decode | 18 +-
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tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
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hw/acpi/aml-build.c | 111 ++++----
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tests/acceptance: update sunxi kernel from armbian to 5.10.16
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hw/arm/sbsa-ref.c | 16 ++
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tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
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hw/arm/virt.c | 21 +-
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hw/core/machine-hmp-cmds.c | 4 +
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Peter Maydell (9):
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hw/core/machine.c | 16 ++
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hw/display/pl110: Remove dead code for non-32-bpp surfaces
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target/arm/cpu.c | 66 ++++-
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hw/display/pl110: Pull included-once parts of template header into pl110.c
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target/arm/cpu64.c | 353 ++++++++++++++-----------
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hw/display/pl110: Remove use of BITS from pl110_template.h
87
target/arm/cpu_tcg.c | 227 +++++++++++-----
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hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
88
target/arm/helper.c | 600 +++++++++++++++++++++++++-----------------
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hw/display/pxa2xx_lcd: Remove dest_width state field
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target/arm/op_helper.c | 43 +++
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hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
90
target/arm/translate-a64.c | 18 ++
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hw/display/pxa2xx: Apply brace-related coding style fixes to template header
91
target/arm/translate.c | 23 ++
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hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
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tests/qtest/numa-test.c | 19 +-
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hw/display/pxa2xx: Inline template header
93
.mailmap | 3 +-
72
94
MAINTAINERS | 2 +-
73
Philippe Mathieu-Daudé (1):
95
25 files changed, 1068 insertions(+), 562 deletions(-)
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hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
75
76
Richard Henderson (8):
77
target/arm: Fix sve_uzp_p vs odd vector lengths
78
target/arm: Fix sve_zip_p vs odd vector lengths
79
target/arm: Fix sve_punpk_p vs odd vector lengths
80
target/arm: Update find_last_active for PREDDESC
81
target/arm: Update BRKA, BRKB, BRKN for PREDDESC
82
target/arm: Update CNTP for PREDDESC
83
target/arm: Update WHILE for PREDDESC
84
target/arm: Update sve reduction vs simd_desc
85
86
docs/system/arm/nuvoton.rst | 2 +-
87
docs/system/arm/xlnx-versal-virt.rst | 1 +
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hw/arm/smmu-internal.h | 5 +
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hw/display/pl110_template.h | 120 +-------
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hw/display/pxa2xx_template.h | 447 ---------------------------
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include/hw/arm/npcm7xx.h | 13 +-
92
include/hw/arm/xlnx-versal.h | 13 +
93
include/hw/boards.h | 1 +
94
include/hw/misc/npcm7xx_mft.h | 70 +++++
95
include/hw/misc/npcm7xx_pwm.h | 4 +-
96
include/hw/misc/xlnx-versal-xramc.h | 97 ++++++
97
include/sysemu/dma.h | 12 +
98
target/arm/kvm_arm.h | 6 +-
99
accel/kvm/kvm-all.c | 2 +
100
hw/arm/npcm7xx.c | 45 ++-
101
hw/arm/npcm7xx_boards.c | 99 ++++++
102
hw/arm/smmu-common.c | 32 +-
103
hw/arm/smmuv3.c | 58 ++--
104
hw/arm/virt.c | 23 +-
105
hw/arm/xlnx-versal.c | 36 +++
106
hw/display/pl110.c | 123 +++++---
107
hw/display/pxa2xx_lcd.c | 520 ++++++++++++++++++++++++++-----
108
hw/i386/intel_iommu.c | 32 +-
109
hw/misc/npcm7xx_mft.c | 540 +++++++++++++++++++++++++++++++++
110
hw/misc/npcm7xx_pwm.c | 4 +
111
hw/misc/xlnx-versal-xramc.c | 253 +++++++++++++++
112
hw/net/allwinner-sun8i-emac.c | 62 ++--
113
hw/timer/sse-timer.c | 1 +
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hw/virtio/virtio-iommu.c | 19 +-
115
softmmu/dma-helpers.c | 26 ++
116
target/arm/kvm.c | 4 +-
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target/arm/sve_helper.c | 107 ++++---
118
target/arm/translate-sve.c | 26 +-
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tests/qtest/npcm7xx_pwm-test.c | 205 ++++++++++++-
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hw/arm/trace-events | 24 +-
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hw/misc/meson.build | 2 +
122
hw/misc/trace-events | 8 +
123
tests/acceptance/boot_linux_console.py | 120 +++-----
124
tests/acceptance/replay_kernel.py | 10 +-
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39 files changed, 2235 insertions(+), 937 deletions(-)
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delete mode 100644 hw/display/pxa2xx_template.h
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create mode 100644 include/hw/misc/npcm7xx_mft.h
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create mode 100644 include/hw/misc/xlnx-versal-xramc.h
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create mode 100644 hw/misc/npcm7xx_mft.c
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create mode 100644 hw/misc/xlnx-versal-xramc.c
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diff view generated by jsdifflib
[PULL 09/39] hw/arm/smmuv3: Uniformize sid traces
[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
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From: Eric Auger <eric.auger@redhat.com>
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From: Leif Lindholm <quic_llindhol@quicinc.com>
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2
3
Convert all sid printouts to sid=0x%x.
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NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
4
separate infrastructure for a transitional period. We've now switched
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over to contributing as Qualcomm Innovation Center (quicinc), so update
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my email address to reflect this.
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7
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
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Message-id: 20210309102742.30442-8-eric.auger@redhat.com
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Cc: Leif Lindholm <leif@nuviainc.com>
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Cc: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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[Fixed commit message typo]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
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hw/arm/trace-events | 24 ++++++++++++------------
16
.mailmap | 3 ++-
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1 file changed, 12 insertions(+), 12 deletions(-)
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MAINTAINERS | 2 +-
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2 files changed, 3 insertions(+), 2 deletions(-)
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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diff --git a/.mailmap b/.mailmap
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/trace-events
22
--- a/.mailmap
16
+++ b/hw/arm/trace-events
23
+++ b/.mailmap
17
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
24
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
18
smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
25
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
19
smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d"
26
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
20
smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
27
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
21
-smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d"
28
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
22
-smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x"
29
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
23
+smmuv3_record_event(const char *type, uint32_t sid) "%s sid=0x%x"
30
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
24
+smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid=0x%x features:0x%x, sid_split:0x%x"
31
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
25
smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"
32
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
26
smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64
33
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
27
-smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"
34
diff --git a/MAINTAINERS b/MAINTAINERS
28
-smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d STE bypass iova:0x%"PRIx64" is_write=%d"
35
index XXXXXXX..XXXXXXX 100644
29
-smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d abort on iova:0x%"PRIx64" is_write=%d"
36
--- a/MAINTAINERS
30
-smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
37
+++ b/MAINTAINERS
31
+smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"
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@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
32
+smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" is_write=%d"
39
SBSA-REF
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+smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x abort on iova:0x%"PRIx64" is_write=%d"
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M: Radoslaw Biernacki <rad@semihalf.com>
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+smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
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M: Peter Maydell <peter.maydell@linaro.org>
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smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
42
-R: Leif Lindholm <leif@nuviainc.com>
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smmuv3_decode_cd(uint32_t oas) "oas=%d"
43
+R: Leif Lindholm <quic_llindhol@quicinc.com>
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smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
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L: qemu-arm@nongnu.org
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-smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
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S: Maintained
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+smmuv3_cmdq_cfgi_ste(int streamid) "streamid= 0x%x"
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F: hw/arm/sbsa-ref.c
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smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
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-smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
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-smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
43
-smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
44
-smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
45
+smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
46
+smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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+smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
48
+smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
49
smmuv3_cmdq_tlbi_nh(void) ""
50
smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
51
-smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
52
+smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
53
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
54
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
55
smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
56
--
47
--
57
2.20.1
48
2.25.1
58
49
59
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diff view generated by jsdifflib
[PULL 04/39] dma: Introduce dma_aligned_pow2_mask()
[PULL 02/32] target/arm: Handle cpreg registration for missing EL
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Currently get_naturally_aligned_size() is used by the intel iommu
3
More gracefully handle cpregs when EL2 and/or EL3 are missing.
4
to compute the maximum invalidation range based on @size which is
4
If the reg is entirely inaccessible, do not register it at all.
5
a power of 2 while being aligned with the @start address and less
5
If the reg is for EL2, and EL3 is present but EL2 is not,
6
than the maximum range defined by @gaw.
6
either discard, squash to res0, const, or keep unchanged.
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7
8
This helper is also useful for other iommu devices (virtio-iommu,
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Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
9
SMMUv3) to make sure IOMMU UNMAP notifiers only are called with
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with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
10
power of 2 range sizes.
10
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
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11
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
12
Let's move this latter into dma-helpers.c and rename it into
12
13
dma_aligned_pow2_mask(). Also rewrite the helper so that it
13
This will simplify cpreg registration for conditional arm features.
14
accomodates UINT64_MAX values for the size mask and max mask.
14
15
It now returns a mask instead of a size. Change the caller.
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
18
Reviewed-by: Peter Xu <peterx@redhat.com>
19
Message-id: 20210309102742.30442-3-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
19
---
22
include/sysemu/dma.h | 12 ++++++++++++
20
target/arm/cpregs.h | 11 +++
23
hw/i386/intel_iommu.c | 30 +++++++-----------------------
21
target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
24
softmmu/dma-helpers.c | 26 ++++++++++++++++++++++++++
22
2 files changed, 133 insertions(+), 56 deletions(-)
25
3 files changed, 45 insertions(+), 23 deletions(-)
23
26
24
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
27
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
28
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
29
--- a/include/sysemu/dma.h
26
--- a/target/arm/cpregs.h
30
+++ b/include/sysemu/dma.h
27
+++ b/target/arm/cpregs.h
31
@@ -XXX,XX +XXX,XX @@ uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
28
@@ -XXX,XX +XXX,XX @@ enum {
32
void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
29
ARM_CP_SVE = 1 << 14,
33
QEMUSGList *sg, enum BlockAcctType type);
30
/* Flag: Do not expose in gdb sysreg xml. */
34
31
ARM_CP_NO_GDB = 1 << 15,
35
+/**
32
+ /*
36
+ * dma_aligned_pow2_mask: Return the address bit mask of the largest
33
+ * Flags: If EL3 but not EL2...
37
+ * power of 2 size less or equal than @end - @start + 1, aligned with @start,
34
+ * - UNDEF: discard the cpreg,
38
+ * and bounded by 1 << @max_addr_bits bits.
35
+ * - KEEP: retain the cpreg as is,
39
+ *
36
+ * - C_NZ: set const on the cpreg, but retain resetvalue,
40
+ * @start: range start address
37
+ * - else: set const on the cpreg, zero resetvalue, aka RES0.
41
+ * @end: range end address (greater than @start)
38
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
42
+ * @max_addr_bits: max address bits (<= 64)
39
+ */
43
+ */
40
+ ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
44
+uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end,
41
+ ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
45
+ int max_addr_bits);
42
+ ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
46
+
43
};
47
#endif
44
48
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
45
/*
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
49
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/i386/intel_iommu.c
48
--- a/target/arm/helper.c
51
+++ b/hw/i386/intel_iommu.c
49
+++ b/target/arm/helper.c
52
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
53
#include "hw/i386/x86-iommu.h"
51
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
54
#include "hw/pci-host/q35.h"
52
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
55
#include "sysemu/kvm.h"
53
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
56
+#include "sysemu/dma.h"
54
- .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
57
#include "sysemu/sysemu.h"
55
+ .access = PL2_RW,
58
#include "hw/i386/apic_internal.h"
56
+ .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
59
#include "kvm/kvm_i386.h"
57
.fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
60
@@ -XXX,XX +XXX,XX @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
58
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
61
return vtd_dev_as;
59
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
62
}
60
- .access = PL2_RW, .resetvalue = 0,
63
61
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
64
-static uint64_t get_naturally_aligned_size(uint64_t start,
62
.writefn = dacr_write, .raw_writefn = raw_write,
65
- uint64_t size, int gaw)
63
.fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
66
-{
64
{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
67
- uint64_t max_mask = 1ULL << gaw;
65
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
68
- uint64_t alignment = start ? start & -start : max_mask;
66
- .access = PL2_RW, .resetvalue = 0,
69
-
67
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
70
- alignment = MIN(alignment, max_mask);
68
.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
71
- size = MIN(size, max_mask);
69
{ .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
72
-
70
.type = ARM_CP_ALIAS,
73
- if (alignment <= size) {
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
74
- /* Increase the alignment of start */
72
.writefn = tlbimva_hyp_is_write },
75
- return alignment;
73
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
76
- } else {
74
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
77
- /* Find the largest page mask from size */
75
- .type = ARM_CP_NO_RAW, .access = PL2_W,
78
- return 1ULL << (63 - clz64(size));
76
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
79
- }
77
.writefn = tlbi_aa64_alle2_write },
80
-}
78
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
81
-
79
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
82
/* Unmap the whole range in the notifier's scope. */
80
- .type = ARM_CP_NO_RAW, .access = PL2_W,
83
static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
81
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
82
.writefn = tlbi_aa64_vae2_write },
83
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
84
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
85
- .access = PL2_W, .type = ARM_CP_NO_RAW,
86
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
87
.writefn = tlbi_aa64_vae2_write },
88
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
90
- .access = PL2_W, .type = ARM_CP_NO_RAW,
91
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
92
.writefn = tlbi_aa64_alle2is_write },
93
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
94
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
95
- .type = ARM_CP_NO_RAW, .access = PL2_W,
96
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
97
.writefn = tlbi_aa64_vae2is_write },
98
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
99
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
100
- .access = PL2_W, .type = ARM_CP_NO_RAW,
101
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
102
.writefn = tlbi_aa64_vae2is_write },
103
#ifndef CONFIG_USER_ONLY
104
/* Unlike the other EL2-related AT operations, these must
105
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
106
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
107
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
108
.access = PL2_W, .accessfn = at_s1e2_access,
109
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
110
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
111
+ .writefn = ats_write64 },
112
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
114
.access = PL2_W, .accessfn = at_s1e2_access,
115
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
116
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
117
+ .writefn = ats_write64 },
118
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
119
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
120
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
122
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
123
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
124
.access = PL2_RW, .accessfn = access_tda,
125
- .type = ARM_CP_NOP },
126
+ .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
127
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
128
* Channel but Linux may try to access this register. The 32-bit
129
* alias is DBGDCCINT.
130
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
131
.access = PL2_W, .type = ARM_CP_NOP },
132
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
136
.writefn = tlbi_aa64_rvae2is_write },
137
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
141
.writefn = tlbi_aa64_rvae2is_write },
142
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
143
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
145
.access = PL2_W, .type = ARM_CP_NOP },
146
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW,
149
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
150
.writefn = tlbi_aa64_rvae2is_write },
151
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
152
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
153
- .access = PL2_W, .type = ARM_CP_NO_RAW,
154
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
.writefn = tlbi_aa64_rvae2is_write },
156
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
157
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
158
- .access = PL2_W, .type = ARM_CP_NO_RAW,
159
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
160
.writefn = tlbi_aa64_rvae2_write },
161
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
162
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
163
- .access = PL2_W, .type = ARM_CP_NO_RAW,
164
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
165
.writefn = tlbi_aa64_rvae2_write },
166
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
167
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
168
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
169
.writefn = tlbi_aa64_vae1is_write },
170
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW,
173
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
174
.writefn = tlbi_aa64_alle2is_write },
175
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
177
- .access = PL2_W, .type = ARM_CP_NO_RAW,
178
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
.writefn = tlbi_aa64_vae2is_write },
180
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
182
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
183
.writefn = tlbi_aa64_alle1is_write },
184
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
185
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
186
- .access = PL2_W, .type = ARM_CP_NO_RAW,
187
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
188
.writefn = tlbi_aa64_vae2is_write },
189
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
190
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
191
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
192
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
193
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
194
.access = PL2_RW, .accessfn = access_el3_aa32ns,
195
- .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
196
+ .resetvalue = cpu->midr,
197
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
198
.fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
199
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
200
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
201
.access = PL2_RW, .resetvalue = cpu->midr,
202
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
203
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
204
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
205
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
206
.access = PL2_RW, .accessfn = access_el3_aa32ns,
207
- .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
208
+ .resetvalue = vmpidr_def,
209
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
210
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
211
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
212
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
213
- .access = PL2_RW,
214
- .resetvalue = vmpidr_def,
215
+ .access = PL2_RW, .resetvalue = vmpidr_def,
216
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
217
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
218
};
219
define_arm_cp_regs(cpu, vpidr_regs);
220
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
221
int crm, int opc1, int opc2,
222
const char *name)
84
{
223
{
85
@@ -XXX,XX +XXX,XX @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
224
+ CPUARMState *env = &cpu->env;
86
225
uint32_t key;
87
while (remain >= VTD_PAGE_SIZE) {
226
ARMCPRegInfo *r2;
88
IOMMUTLBEvent event;
227
bool is64 = r->type & ARM_CP_64BIT;
89
- uint64_t mask = get_naturally_aligned_size(start, remain, s->aw_bits);
228
bool ns = secstate & ARM_CP_SECSTATE_NS;
90
+ uint64_t mask = dma_aligned_pow2_mask(start, end, s->aw_bits);
229
int cp = r->cp;
91
+ uint64_t size = mask + 1;
230
- bool isbanked;
92
231
size_t name_len;
93
- assert(mask);
232
+ bool make_const;
94
+ assert(size);
233
95
234
switch (state) {
96
event.type = IOMMU_NOTIFIER_UNMAP;
235
case ARM_CP_STATE_AA32:
97
event.entry.iova = start;
236
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
98
- event.entry.addr_mask = mask - 1;
237
}
99
+ event.entry.addr_mask = mask;
100
event.entry.target_as = &address_space_memory;
101
event.entry.perm = IOMMU_NONE;
102
/* This field is meaningless for unmap */
103
@@ -XXX,XX +XXX,XX @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
104
105
memory_region_notify_iommu_one(n, &event);
106
107
- start += mask;
108
- remain -= mask;
109
+ start += size;
110
+ remain -= size;
111
}
238
}
112
239
113
assert(!remain);
240
+ /*
114
diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c
241
+ * Eliminate registers that are not present because the EL is missing.
115
index XXXXXXX..XXXXXXX 100644
242
+ * Doing this here makes it easier to put all registers for a given
116
--- a/softmmu/dma-helpers.c
243
+ * feature into the same ARMCPRegInfo array and define them all at once.
117
+++ b/softmmu/dma-helpers.c
244
+ */
118
@@ -XXX,XX +XXX,XX @@ void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
245
+ make_const = false;
119
{
246
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
120
block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
247
+ /*
121
}
248
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
122
+
249
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
123
+uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, int max_addr_bits)
250
+ */
124
+{
251
+ int min_el = ctz32(r->access) / 2;
125
+ uint64_t max_mask = UINT64_MAX, addr_mask = end - start;
252
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
126
+ uint64_t alignment_mask, size_mask;
253
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
127
+
254
+ return;
128
+ if (max_addr_bits != 64) {
255
+ }
129
+ max_mask = (1ULL << max_addr_bits) - 1;
256
+ make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
257
+ }
258
+ } else {
259
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
260
+ ? PL2_RW : PL1_RW);
261
+ if ((r->access & max_el) == 0) {
262
+ return;
263
+ }
130
+ }
264
+ }
131
+
265
+
132
+ alignment_mask = start ? (start & -start) - 1 : max_mask;
266
/* Combine cpreg and name into one allocation. */
133
+ alignment_mask = MIN(alignment_mask, max_mask);
267
name_len = strlen(name) + 1;
134
+ size_mask = MIN(addr_mask, max_mask);
268
r2 = g_malloc(sizeof(*r2) + name_len);
135
+
269
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
136
+ if (alignment_mask <= size_mask) {
270
r2->opaque = opaque;
137
+ /* Increase the alignment of start */
271
}
138
+ return alignment_mask;
272
273
- isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
274
- if (isbanked) {
275
+ if (make_const) {
276
+ /* This should not have been a very special register to begin. */
277
+ int old_special = r2->type & ARM_CP_SPECIAL_MASK;
278
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
279
/*
280
- * Register is banked (using both entries in array).
281
- * Overwriting fieldoffset as the array is only used to define
282
- * banked registers but later only fieldoffset is used.
283
+ * Set the special function to CONST, retaining the other flags.
284
+ * This is important for e.g. ARM_CP_SVE so that we still
285
+ * take the SVE trap if CPTR_EL3.EZ == 0.
286
*/
287
- r2->fieldoffset = r->bank_fieldoffsets[ns];
288
- }
289
+ r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
290
+ /*
291
+ * Usually, these registers become RES0, but there are a few
292
+ * special cases like VPIDR_EL2 which have a constant non-zero
293
+ * value with writes ignored.
294
+ */
295
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
296
+ r2->resetvalue = 0;
297
+ }
298
+ /*
299
+ * ARM_CP_CONST has precedence, so removing the callbacks and
300
+ * offsets are not strictly necessary, but it is potentially
301
+ * less confusing to debug later.
302
+ */
303
+ r2->readfn = NULL;
304
+ r2->writefn = NULL;
305
+ r2->raw_readfn = NULL;
306
+ r2->raw_writefn = NULL;
307
+ r2->resetfn = NULL;
308
+ r2->fieldoffset = 0;
309
+ r2->bank_fieldoffsets[0] = 0;
310
+ r2->bank_fieldoffsets[1] = 0;
139
+ } else {
311
+ } else {
140
+ /* Find the largest page mask from size */
312
+ bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
141
+ if (addr_mask == UINT64_MAX) {
313
142
+ return UINT64_MAX;
314
- if (state == ARM_CP_STATE_AA32) {
315
if (isbanked) {
316
/*
317
- * If the register is banked then we don't need to migrate or
318
- * reset the 32-bit instance in certain cases:
319
- *
320
- * 1) If the register has both 32-bit and 64-bit instances then we
321
- * can count on the 64-bit instance taking care of the
322
- * non-secure bank.
323
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
324
- * taking care of the secure bank. This requires that separate
325
- * 32 and 64-bit definitions are provided.
326
+ * Register is banked (using both entries in array).
327
+ * Overwriting fieldoffset as the array is only used to define
328
+ * banked registers but later only fieldoffset is used.
329
*/
330
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
331
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
332
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
143
+ }
333
+ }
144
+ return (1ULL << (63 - clz64(addr_mask + 1))) - 1;
334
+ if (state == ARM_CP_STATE_AA32) {
145
+ }
335
+ if (isbanked) {
146
+}
336
+ /*
147
+
337
+ * If the register is banked then we don't need to migrate or
338
+ * reset the 32-bit instance in certain cases:
339
+ *
340
+ * 1) If the register has both 32-bit and 64-bit instances
341
+ * then we can count on the 64-bit instance taking care
342
+ * of the non-secure bank.
343
+ * 2) If ARMv8 is enabled then we can count on a 64-bit
344
+ * version taking care of the secure bank. This requires
345
+ * that separate 32 and 64-bit definitions are provided.
346
+ */
347
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
348
+ (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
349
+ r2->type |= ARM_CP_ALIAS;
350
+ }
351
+ } else if ((secstate != r->secure) && !ns) {
352
+ /*
353
+ * The register is not banked so we only want to allow
354
+ * migration of the non-secure instance.
355
+ */
356
r2->type |= ARM_CP_ALIAS;
357
}
358
- } else if ((secstate != r->secure) && !ns) {
359
- /*
360
- * The register is not banked so we only want to allow migration
361
- * of the non-secure instance.
362
- */
363
- r2->type |= ARM_CP_ALIAS;
364
- }
365
366
- if (HOST_BIG_ENDIAN &&
367
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
368
- r2->fieldoffset += sizeof(uint32_t);
369
+ if (HOST_BIG_ENDIAN &&
370
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
371
+ r2->fieldoffset += sizeof(uint32_t);
372
+ }
373
}
374
}
375
376
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
377
* multiple times. Special registers (ie NOP/WFI) are
378
* never migratable and not even raw-accessible.
379
*/
380
- if (r->type & ARM_CP_SPECIAL_MASK) {
381
+ if (r2->type & ARM_CP_SPECIAL_MASK) {
382
r2->type |= ARM_CP_NO_RAW;
383
}
384
if (((r->crm == CP_ANY) && crm != 0) ||
148
--
385
--
149
2.20.1
386
2.25.1
150
151
diff view generated by jsdifflib
[PULL 39/39] hw/display/pxa2xx: Inline template header
[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
1
The template header is now included only once; just inline its contents
1
From: Richard Henderson <richard.henderson@linaro.org>
2
in hw/display/pxa2xx_lcd.c.
2
3
3
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
4
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
5
while registering for v8.
6
7
This is a behavior change for v7 cpus with Security Extensions and
8
without Virtualization Extensions, in that the virtualization cpregs
9
are now correctly not present. This would be a migration compatibility
10
break, except that we have an existing bug in which migration of 32-bit
11
cpus with Security Extensions enabled does not work.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
6
Message-id: 20210211141515.8755-10-peter.maydell@linaro.org
7
---
17
---
8
hw/display/pxa2xx_template.h | 434 -----------------------------------
18
target/arm/helper.c | 158 ++++----------------------------------------
9
hw/display/pxa2xx_lcd.c | 427 +++++++++++++++++++++++++++++++++-
19
1 file changed, 13 insertions(+), 145 deletions(-)
10
2 files changed, 425 insertions(+), 436 deletions(-)
20
11
delete mode 100644 hw/display/pxa2xx_template.h
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
22
index XXXXXXX..XXXXXXX 100644
13
diff --git a/hw/display/pxa2xx_template.h b/hw/display/pxa2xx_template.h
23
--- a/target/arm/helper.c
14
deleted file mode 100644
24
+++ b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
16
--- a/hw/display/pxa2xx_template.h
26
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
17
+++ /dev/null
27
};
18
@@ -XXX,XX +XXX,XX @@
28
19
-/*
29
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
20
- * Intel XScale PXA255/270 LCDC emulation.
30
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
21
- *
31
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
22
- * Copyright (c) 2006 Openedhand Ltd.
32
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
23
- * Written by Andrzej Zaborowski <balrog@zabor.org>
33
- .access = PL2_RW,
24
- *
34
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
25
- * This code is licensed under the GPLv2.
35
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
26
- *
36
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
27
- * Framebuffer format conversion routines.
37
- .access = PL2_RW,
28
- */
38
- .type = ARM_CP_CONST, .resetvalue = 0 },
29
-
39
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
30
-# define SKIP_PIXEL(to) do { to += deststep; } while (0)
40
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
31
-# define COPY_PIXEL(to, from) \
41
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
32
- do { \
42
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
33
- *(uint32_t *) to = from; \
43
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
34
- SKIP_PIXEL(to); \
44
- .access = PL2_RW,
35
- } while (0)
45
- .type = ARM_CP_CONST, .resetvalue = 0 },
36
-
46
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
37
-#ifdef HOST_WORDS_BIGENDIAN
47
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
38
-# define SWAP_WORDS 1
48
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
-#endif
49
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
40
-
50
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
41
-#define FN_2(x) FN(x + 1) FN(x)
51
- .access = PL2_RW, .type = ARM_CP_CONST,
42
-#define FN_4(x) FN_2(x + 2) FN_2(x)
52
- .resetvalue = 0 },
43
-
53
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
44
-static void pxa2xx_draw_line2(void *opaque, uint8_t *dest, const uint8_t *src,
54
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
45
- int width, int deststep)
55
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46
-{
56
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
47
- uint32_t *palette = opaque;
57
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
48
- uint32_t data;
58
- .access = PL2_RW, .type = ARM_CP_CONST,
49
- while (width > 0) {
59
- .resetvalue = 0 },
50
- data = *(uint32_t *) src;
60
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
51
-#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
61
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
52
-#ifdef SWAP_WORDS
62
- .access = PL2_RW, .type = ARM_CP_CONST,
53
- FN_4(12)
63
- .resetvalue = 0 },
54
- FN_4(8)
64
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
55
- FN_4(4)
65
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
56
- FN_4(0)
66
- .access = PL2_RW, .type = ARM_CP_CONST,
57
-#else
67
- .resetvalue = 0 },
58
- FN_4(0)
68
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
59
- FN_4(4)
69
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
60
- FN_4(8)
70
- .access = PL2_RW, .type = ARM_CP_CONST,
61
- FN_4(12)
71
- .resetvalue = 0 },
62
-#endif
72
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
63
-#undef FN
73
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
64
- width -= 16;
74
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
- src += 4;
75
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
66
- }
76
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
67
-}
77
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
68
-
78
- .type = ARM_CP_CONST, .resetvalue = 0 },
69
-static void pxa2xx_draw_line4(void *opaque, uint8_t *dest, const uint8_t *src,
79
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
70
- int width, int deststep)
80
- .cp = 15, .opc1 = 6, .crm = 2,
71
-{
81
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
72
- uint32_t *palette = opaque;
82
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
73
- uint32_t data;
83
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
74
- while (width > 0) {
84
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
75
- data = *(uint32_t *) src;
85
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
-#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
86
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
77
-#ifdef SWAP_WORDS
87
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
78
- FN_2(6)
88
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- FN_2(4)
89
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
80
- FN_2(2)
90
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
81
- FN_2(0)
91
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
82
-#else
92
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
83
- FN_2(0)
93
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
84
- FN_2(2)
94
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- FN_2(4)
95
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
86
- FN_2(6)
96
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
87
-#endif
97
- .resetvalue = 0 },
88
-#undef FN
98
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
89
- width -= 8;
99
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
90
- src += 4;
100
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- }
101
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
92
-}
102
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
93
-
103
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
94
-static void pxa2xx_draw_line8(void *opaque, uint8_t *dest, const uint8_t *src,
104
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
95
- int width, int deststep)
105
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
96
-{
106
- .resetvalue = 0 },
97
- uint32_t *palette = opaque;
107
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
98
- uint32_t data;
108
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
99
- while (width > 0) {
109
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
100
- data = *(uint32_t *) src;
110
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
101
-#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
111
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
102
-#ifdef SWAP_WORDS
112
- .resetvalue = 0 },
103
- FN(24)
113
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
104
- FN(16)
114
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
105
- FN(8)
115
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
106
- FN(0)
116
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
107
-#else
117
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
108
- FN(0)
118
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
109
- FN(8)
119
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
110
- FN(16)
120
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
111
- FN(24)
121
- .access = PL2_RW, .accessfn = access_tda,
112
-#endif
122
- .type = ARM_CP_CONST, .resetvalue = 0 },
113
-#undef FN
123
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
114
- width -= 4;
124
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
115
- src += 4;
125
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
116
- }
126
- .type = ARM_CP_CONST, .resetvalue = 0 },
117
-}
127
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
118
-
128
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
119
-static void pxa2xx_draw_line16(void *opaque, uint8_t *dest, const uint8_t *src,
129
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
120
- int width, int deststep)
130
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
121
-{
131
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
122
- uint32_t data;
132
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
123
- unsigned int r, g, b;
133
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
124
- while (width > 0) {
134
- .type = ARM_CP_CONST,
125
- data = *(uint32_t *) src;
135
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
126
-#ifdef SWAP_WORDS
136
- .access = PL2_RW, .resetvalue = 0 },
127
- data = bswap32(data);
128
-#endif
129
- b = (data & 0x1f) << 3;
130
- data >>= 5;
131
- g = (data & 0x3f) << 2;
132
- data >>= 6;
133
- r = (data & 0x1f) << 3;
134
- data >>= 5;
135
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
136
- b = (data & 0x1f) << 3;
137
- data >>= 5;
138
- g = (data & 0x3f) << 2;
139
- data >>= 6;
140
- r = (data & 0x1f) << 3;
141
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
142
- width -= 2;
143
- src += 4;
144
- }
145
-}
146
-
147
-static void pxa2xx_draw_line16t(void *opaque, uint8_t *dest, const uint8_t *src,
148
- int width, int deststep)
149
-{
150
- uint32_t data;
151
- unsigned int r, g, b;
152
- while (width > 0) {
153
- data = *(uint32_t *) src;
154
-#ifdef SWAP_WORDS
155
- data = bswap32(data);
156
-#endif
157
- b = (data & 0x1f) << 3;
158
- data >>= 5;
159
- g = (data & 0x1f) << 3;
160
- data >>= 5;
161
- r = (data & 0x1f) << 3;
162
- data >>= 5;
163
- if (data & 1) {
164
- SKIP_PIXEL(dest);
165
- } else {
166
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
167
- }
168
- data >>= 1;
169
- b = (data & 0x1f) << 3;
170
- data >>= 5;
171
- g = (data & 0x1f) << 3;
172
- data >>= 5;
173
- r = (data & 0x1f) << 3;
174
- data >>= 5;
175
- if (data & 1) {
176
- SKIP_PIXEL(dest);
177
- } else {
178
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
179
- }
180
- width -= 2;
181
- src += 4;
182
- }
183
-}
184
-
185
-static void pxa2xx_draw_line18(void *opaque, uint8_t *dest, const uint8_t *src,
186
- int width, int deststep)
187
-{
188
- uint32_t data;
189
- unsigned int r, g, b;
190
- while (width > 0) {
191
- data = *(uint32_t *) src;
192
-#ifdef SWAP_WORDS
193
- data = bswap32(data);
194
-#endif
195
- b = (data & 0x3f) << 2;
196
- data >>= 6;
197
- g = (data & 0x3f) << 2;
198
- data >>= 6;
199
- r = (data & 0x3f) << 2;
200
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
201
- width -= 1;
202
- src += 4;
203
- }
204
-}
205
-
206
-/* The wicked packed format */
207
-static void pxa2xx_draw_line18p(void *opaque, uint8_t *dest, const uint8_t *src,
208
- int width, int deststep)
209
-{
210
- uint32_t data[3];
211
- unsigned int r, g, b;
212
- while (width > 0) {
213
- data[0] = *(uint32_t *) src;
214
- src += 4;
215
- data[1] = *(uint32_t *) src;
216
- src += 4;
217
- data[2] = *(uint32_t *) src;
218
- src += 4;
219
-#ifdef SWAP_WORDS
220
- data[0] = bswap32(data[0]);
221
- data[1] = bswap32(data[1]);
222
- data[2] = bswap32(data[2]);
223
-#endif
224
- b = (data[0] & 0x3f) << 2;
225
- data[0] >>= 6;
226
- g = (data[0] & 0x3f) << 2;
227
- data[0] >>= 6;
228
- r = (data[0] & 0x3f) << 2;
229
- data[0] >>= 12;
230
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
231
- b = (data[0] & 0x3f) << 2;
232
- data[0] >>= 6;
233
- g = ((data[1] & 0xf) << 4) | (data[0] << 2);
234
- data[1] >>= 4;
235
- r = (data[1] & 0x3f) << 2;
236
- data[1] >>= 12;
237
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
238
- b = (data[1] & 0x3f) << 2;
239
- data[1] >>= 6;
240
- g = (data[1] & 0x3f) << 2;
241
- data[1] >>= 6;
242
- r = ((data[2] & 0x3) << 6) | (data[1] << 2);
243
- data[2] >>= 8;
244
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
245
- b = (data[2] & 0x3f) << 2;
246
- data[2] >>= 6;
247
- g = (data[2] & 0x3f) << 2;
248
- data[2] >>= 6;
249
- r = data[2] << 2;
250
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
251
- width -= 4;
252
- }
253
-}
254
-
255
-static void pxa2xx_draw_line19(void *opaque, uint8_t *dest, const uint8_t *src,
256
- int width, int deststep)
257
-{
258
- uint32_t data;
259
- unsigned int r, g, b;
260
- while (width > 0) {
261
- data = *(uint32_t *) src;
262
-#ifdef SWAP_WORDS
263
- data = bswap32(data);
264
-#endif
265
- b = (data & 0x3f) << 2;
266
- data >>= 6;
267
- g = (data & 0x3f) << 2;
268
- data >>= 6;
269
- r = (data & 0x3f) << 2;
270
- data >>= 6;
271
- if (data & 1) {
272
- SKIP_PIXEL(dest);
273
- } else {
274
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
275
- }
276
- width -= 1;
277
- src += 4;
278
- }
279
-}
280
-
281
-/* The wicked packed format */
282
-static void pxa2xx_draw_line19p(void *opaque, uint8_t *dest, const uint8_t *src,
283
- int width, int deststep)
284
-{
285
- uint32_t data[3];
286
- unsigned int r, g, b;
287
- while (width > 0) {
288
- data[0] = *(uint32_t *) src;
289
- src += 4;
290
- data[1] = *(uint32_t *) src;
291
- src += 4;
292
- data[2] = *(uint32_t *) src;
293
- src += 4;
294
-# ifdef SWAP_WORDS
295
- data[0] = bswap32(data[0]);
296
- data[1] = bswap32(data[1]);
297
- data[2] = bswap32(data[2]);
298
-# endif
299
- b = (data[0] & 0x3f) << 2;
300
- data[0] >>= 6;
301
- g = (data[0] & 0x3f) << 2;
302
- data[0] >>= 6;
303
- r = (data[0] & 0x3f) << 2;
304
- data[0] >>= 6;
305
- if (data[0] & 1) {
306
- SKIP_PIXEL(dest);
307
- } else {
308
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
309
- }
310
- data[0] >>= 6;
311
- b = (data[0] & 0x3f) << 2;
312
- data[0] >>= 6;
313
- g = ((data[1] & 0xf) << 4) | (data[0] << 2);
314
- data[1] >>= 4;
315
- r = (data[1] & 0x3f) << 2;
316
- data[1] >>= 6;
317
- if (data[1] & 1) {
318
- SKIP_PIXEL(dest);
319
- } else {
320
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
321
- }
322
- data[1] >>= 6;
323
- b = (data[1] & 0x3f) << 2;
324
- data[1] >>= 6;
325
- g = (data[1] & 0x3f) << 2;
326
- data[1] >>= 6;
327
- r = ((data[2] & 0x3) << 6) | (data[1] << 2);
328
- data[2] >>= 2;
329
- if (data[2] & 1) {
330
- SKIP_PIXEL(dest);
331
- } else {
332
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
333
- }
334
- data[2] >>= 6;
335
- b = (data[2] & 0x3f) << 2;
336
- data[2] >>= 6;
337
- g = (data[2] & 0x3f) << 2;
338
- data[2] >>= 6;
339
- r = data[2] << 2;
340
- data[2] >>= 6;
341
- if (data[2] & 1) {
342
- SKIP_PIXEL(dest);
343
- } else {
344
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
345
- }
346
- width -= 4;
347
- }
348
-}
349
-
350
-static void pxa2xx_draw_line24(void *opaque, uint8_t *dest, const uint8_t *src,
351
- int width, int deststep)
352
-{
353
- uint32_t data;
354
- unsigned int r, g, b;
355
- while (width > 0) {
356
- data = *(uint32_t *) src;
357
-#ifdef SWAP_WORDS
358
- data = bswap32(data);
359
-#endif
360
- b = data & 0xff;
361
- data >>= 8;
362
- g = data & 0xff;
363
- data >>= 8;
364
- r = data & 0xff;
365
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
366
- width -= 1;
367
- src += 4;
368
- }
369
-}
370
-
371
-static void pxa2xx_draw_line24t(void *opaque, uint8_t *dest, const uint8_t *src,
372
- int width, int deststep)
373
-{
374
- uint32_t data;
375
- unsigned int r, g, b;
376
- while (width > 0) {
377
- data = *(uint32_t *) src;
378
-#ifdef SWAP_WORDS
379
- data = bswap32(data);
380
-#endif
381
- b = (data & 0x7f) << 1;
382
- data >>= 7;
383
- g = data & 0xff;
384
- data >>= 8;
385
- r = data & 0xff;
386
- data >>= 8;
387
- if (data & 1) {
388
- SKIP_PIXEL(dest);
389
- } else {
390
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
391
- }
392
- width -= 1;
393
- src += 4;
394
- }
395
-}
396
-
397
-static void pxa2xx_draw_line25(void *opaque, uint8_t *dest, const uint8_t *src,
398
- int width, int deststep)
399
-{
400
- uint32_t data;
401
- unsigned int r, g, b;
402
- while (width > 0) {
403
- data = *(uint32_t *) src;
404
-#ifdef SWAP_WORDS
405
- data = bswap32(data);
406
-#endif
407
- b = data & 0xff;
408
- data >>= 8;
409
- g = data & 0xff;
410
- data >>= 8;
411
- r = data & 0xff;
412
- data >>= 8;
413
- if (data & 1) {
414
- SKIP_PIXEL(dest);
415
- } else {
416
- COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
417
- }
418
- width -= 1;
419
- src += 4;
420
- }
421
-}
422
-
423
-/* Overlay planes disabled, no transparency */
424
-static drawfn pxa2xx_draw_fn_32[16] = {
425
- [0 ... 0xf] = NULL,
426
- [pxa_lcdc_2bpp] = pxa2xx_draw_line2,
427
- [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
428
- [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
429
- [pxa_lcdc_16bpp] = pxa2xx_draw_line16,
430
- [pxa_lcdc_18bpp] = pxa2xx_draw_line18,
431
- [pxa_lcdc_18pbpp] = pxa2xx_draw_line18p,
432
- [pxa_lcdc_24bpp] = pxa2xx_draw_line24,
433
-};
137
-};
434
-
138
-
435
-/* Overlay planes enabled, transparency used */
139
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
436
-static drawfn pxa2xx_draw_fn_32t[16] = {
140
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
437
- [0 ... 0xf] = NULL,
141
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
438
- [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
142
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
439
- [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
143
- .access = PL2_RW,
440
- [pxa_lcdc_16bpp] = pxa2xx_draw_line16t,
144
- .type = ARM_CP_CONST, .resetvalue = 0 },
441
- [pxa_lcdc_19bpp] = pxa2xx_draw_line19,
442
- [pxa_lcdc_19pbpp] = pxa2xx_draw_line19p,
443
- [pxa_lcdc_24bpp] = pxa2xx_draw_line24t,
444
- [pxa_lcdc_25bpp] = pxa2xx_draw_line25,
445
-};
145
-};
446
-
146
-
447
-#undef COPY_PIXEL
147
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
448
-#undef SKIP_PIXEL
148
{
449
-
149
ARMCPU *cpu = env_archcpu(env);
450
-#ifdef SWAP_WORDS
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
451
-# undef SWAP_WORDS
151
define_arm_cp_regs(cpu, v8_idregs);
452
-#endif
152
define_arm_cp_regs(cpu, v8_cp_reginfo);
453
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
153
}
454
index XXXXXXX..XXXXXXX 100644
154
- if (arm_feature(env, ARM_FEATURE_EL2)) {
455
--- a/hw/display/pxa2xx_lcd.c
456
+++ b/hw/display/pxa2xx_lcd.c
457
@@ -XXX,XX +XXX,XX @@ typedef struct QEMU_PACKED {
458
/* Size of a pixel in the QEMU UI output surface, in bytes */
459
#define DEST_PIXEL_WIDTH 4
460
461
-#define BITS 32
462
-#include "pxa2xx_template.h"
463
+/* Line drawing code to handle the various possible guest pixel formats */
464
+
155
+
465
+# define SKIP_PIXEL(to) do { to += deststep; } while (0)
156
+ /*
466
+# define COPY_PIXEL(to, from) \
157
+ * Register the base EL2 cpregs.
467
+ do { \
158
+ * Pre v8, these registers are implemented only as part of the
468
+ *(uint32_t *) to = from; \
159
+ * Virtualization Extensions (EL2 present). Beginning with v8,
469
+ SKIP_PIXEL(to); \
160
+ * if EL2 is missing but EL3 is enabled, mostly these become
470
+ } while (0)
161
+ * RES0 from EL3, with some specific exceptions.
162
+ */
163
+ if (arm_feature(env, ARM_FEATURE_EL2)
164
+ || (arm_feature(env, ARM_FEATURE_EL3)
165
+ && arm_feature(env, ARM_FEATURE_V8))) {
166
uint64_t vmpidr_def = mpidr_read_val(env);
167
ARMCPRegInfo vpidr_regs[] = {
168
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
169
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
170
};
171
define_one_arm_cp_reg(cpu, &rvbar);
172
}
173
- } else {
174
- /* If EL2 is missing but higher ELs are enabled, we need to
175
- * register the no_el2 reginfos.
176
- */
177
- if (arm_feature(env, ARM_FEATURE_EL3)) {
178
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
179
- * of MIDR_EL1 and MPIDR_EL1.
180
- */
181
- ARMCPRegInfo vpidr_regs[] = {
182
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
183
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
184
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
185
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
186
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
187
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
188
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
189
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
190
- .type = ARM_CP_NO_RAW,
191
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
192
- };
193
- define_arm_cp_regs(cpu, vpidr_regs);
194
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
195
- if (arm_feature(env, ARM_FEATURE_V8)) {
196
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
197
- }
198
- }
199
}
471
+
200
+
472
+#ifdef HOST_WORDS_BIGENDIAN
201
+ /* Register the base EL3 cpregs. */
473
+# define SWAP_WORDS 1
202
if (arm_feature(env, ARM_FEATURE_EL3)) {
474
+#endif
203
define_arm_cp_regs(cpu, el3_cp_reginfo);
475
+
204
ARMCPRegInfo el3_regs[] = {
476
+#define FN_2(x) FN(x + 1) FN(x)
477
+#define FN_4(x) FN_2(x + 2) FN_2(x)
478
+
479
+static void pxa2xx_draw_line2(void *opaque, uint8_t *dest, const uint8_t *src,
480
+ int width, int deststep)
481
+{
482
+ uint32_t *palette = opaque;
483
+ uint32_t data;
484
+ while (width > 0) {
485
+ data = *(uint32_t *) src;
486
+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
487
+#ifdef SWAP_WORDS
488
+ FN_4(12)
489
+ FN_4(8)
490
+ FN_4(4)
491
+ FN_4(0)
492
+#else
493
+ FN_4(0)
494
+ FN_4(4)
495
+ FN_4(8)
496
+ FN_4(12)
497
+#endif
498
+#undef FN
499
+ width -= 16;
500
+ src += 4;
501
+ }
502
+}
503
+
504
+static void pxa2xx_draw_line4(void *opaque, uint8_t *dest, const uint8_t *src,
505
+ int width, int deststep)
506
+{
507
+ uint32_t *palette = opaque;
508
+ uint32_t data;
509
+ while (width > 0) {
510
+ data = *(uint32_t *) src;
511
+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
512
+#ifdef SWAP_WORDS
513
+ FN_2(6)
514
+ FN_2(4)
515
+ FN_2(2)
516
+ FN_2(0)
517
+#else
518
+ FN_2(0)
519
+ FN_2(2)
520
+ FN_2(4)
521
+ FN_2(6)
522
+#endif
523
+#undef FN
524
+ width -= 8;
525
+ src += 4;
526
+ }
527
+}
528
+
529
+static void pxa2xx_draw_line8(void *opaque, uint8_t *dest, const uint8_t *src,
530
+ int width, int deststep)
531
+{
532
+ uint32_t *palette = opaque;
533
+ uint32_t data;
534
+ while (width > 0) {
535
+ data = *(uint32_t *) src;
536
+#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
537
+#ifdef SWAP_WORDS
538
+ FN(24)
539
+ FN(16)
540
+ FN(8)
541
+ FN(0)
542
+#else
543
+ FN(0)
544
+ FN(8)
545
+ FN(16)
546
+ FN(24)
547
+#endif
548
+#undef FN
549
+ width -= 4;
550
+ src += 4;
551
+ }
552
+}
553
+
554
+static void pxa2xx_draw_line16(void *opaque, uint8_t *dest, const uint8_t *src,
555
+ int width, int deststep)
556
+{
557
+ uint32_t data;
558
+ unsigned int r, g, b;
559
+ while (width > 0) {
560
+ data = *(uint32_t *) src;
561
+#ifdef SWAP_WORDS
562
+ data = bswap32(data);
563
+#endif
564
+ b = (data & 0x1f) << 3;
565
+ data >>= 5;
566
+ g = (data & 0x3f) << 2;
567
+ data >>= 6;
568
+ r = (data & 0x1f) << 3;
569
+ data >>= 5;
570
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
571
+ b = (data & 0x1f) << 3;
572
+ data >>= 5;
573
+ g = (data & 0x3f) << 2;
574
+ data >>= 6;
575
+ r = (data & 0x1f) << 3;
576
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
577
+ width -= 2;
578
+ src += 4;
579
+ }
580
+}
581
+
582
+static void pxa2xx_draw_line16t(void *opaque, uint8_t *dest, const uint8_t *src,
583
+ int width, int deststep)
584
+{
585
+ uint32_t data;
586
+ unsigned int r, g, b;
587
+ while (width > 0) {
588
+ data = *(uint32_t *) src;
589
+#ifdef SWAP_WORDS
590
+ data = bswap32(data);
591
+#endif
592
+ b = (data & 0x1f) << 3;
593
+ data >>= 5;
594
+ g = (data & 0x1f) << 3;
595
+ data >>= 5;
596
+ r = (data & 0x1f) << 3;
597
+ data >>= 5;
598
+ if (data & 1) {
599
+ SKIP_PIXEL(dest);
600
+ } else {
601
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
602
+ }
603
+ data >>= 1;
604
+ b = (data & 0x1f) << 3;
605
+ data >>= 5;
606
+ g = (data & 0x1f) << 3;
607
+ data >>= 5;
608
+ r = (data & 0x1f) << 3;
609
+ data >>= 5;
610
+ if (data & 1) {
611
+ SKIP_PIXEL(dest);
612
+ } else {
613
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
614
+ }
615
+ width -= 2;
616
+ src += 4;
617
+ }
618
+}
619
+
620
+static void pxa2xx_draw_line18(void *opaque, uint8_t *dest, const uint8_t *src,
621
+ int width, int deststep)
622
+{
623
+ uint32_t data;
624
+ unsigned int r, g, b;
625
+ while (width > 0) {
626
+ data = *(uint32_t *) src;
627
+#ifdef SWAP_WORDS
628
+ data = bswap32(data);
629
+#endif
630
+ b = (data & 0x3f) << 2;
631
+ data >>= 6;
632
+ g = (data & 0x3f) << 2;
633
+ data >>= 6;
634
+ r = (data & 0x3f) << 2;
635
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
636
+ width -= 1;
637
+ src += 4;
638
+ }
639
+}
640
+
641
+/* The wicked packed format */
642
+static void pxa2xx_draw_line18p(void *opaque, uint8_t *dest, const uint8_t *src,
643
+ int width, int deststep)
644
+{
645
+ uint32_t data[3];
646
+ unsigned int r, g, b;
647
+ while (width > 0) {
648
+ data[0] = *(uint32_t *) src;
649
+ src += 4;
650
+ data[1] = *(uint32_t *) src;
651
+ src += 4;
652
+ data[2] = *(uint32_t *) src;
653
+ src += 4;
654
+#ifdef SWAP_WORDS
655
+ data[0] = bswap32(data[0]);
656
+ data[1] = bswap32(data[1]);
657
+ data[2] = bswap32(data[2]);
658
+#endif
659
+ b = (data[0] & 0x3f) << 2;
660
+ data[0] >>= 6;
661
+ g = (data[0] & 0x3f) << 2;
662
+ data[0] >>= 6;
663
+ r = (data[0] & 0x3f) << 2;
664
+ data[0] >>= 12;
665
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
666
+ b = (data[0] & 0x3f) << 2;
667
+ data[0] >>= 6;
668
+ g = ((data[1] & 0xf) << 4) | (data[0] << 2);
669
+ data[1] >>= 4;
670
+ r = (data[1] & 0x3f) << 2;
671
+ data[1] >>= 12;
672
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
673
+ b = (data[1] & 0x3f) << 2;
674
+ data[1] >>= 6;
675
+ g = (data[1] & 0x3f) << 2;
676
+ data[1] >>= 6;
677
+ r = ((data[2] & 0x3) << 6) | (data[1] << 2);
678
+ data[2] >>= 8;
679
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
680
+ b = (data[2] & 0x3f) << 2;
681
+ data[2] >>= 6;
682
+ g = (data[2] & 0x3f) << 2;
683
+ data[2] >>= 6;
684
+ r = data[2] << 2;
685
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
686
+ width -= 4;
687
+ }
688
+}
689
+
690
+static void pxa2xx_draw_line19(void *opaque, uint8_t *dest, const uint8_t *src,
691
+ int width, int deststep)
692
+{
693
+ uint32_t data;
694
+ unsigned int r, g, b;
695
+ while (width > 0) {
696
+ data = *(uint32_t *) src;
697
+#ifdef SWAP_WORDS
698
+ data = bswap32(data);
699
+#endif
700
+ b = (data & 0x3f) << 2;
701
+ data >>= 6;
702
+ g = (data & 0x3f) << 2;
703
+ data >>= 6;
704
+ r = (data & 0x3f) << 2;
705
+ data >>= 6;
706
+ if (data & 1) {
707
+ SKIP_PIXEL(dest);
708
+ } else {
709
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
710
+ }
711
+ width -= 1;
712
+ src += 4;
713
+ }
714
+}
715
+
716
+/* The wicked packed format */
717
+static void pxa2xx_draw_line19p(void *opaque, uint8_t *dest, const uint8_t *src,
718
+ int width, int deststep)
719
+{
720
+ uint32_t data[3];
721
+ unsigned int r, g, b;
722
+ while (width > 0) {
723
+ data[0] = *(uint32_t *) src;
724
+ src += 4;
725
+ data[1] = *(uint32_t *) src;
726
+ src += 4;
727
+ data[2] = *(uint32_t *) src;
728
+ src += 4;
729
+# ifdef SWAP_WORDS
730
+ data[0] = bswap32(data[0]);
731
+ data[1] = bswap32(data[1]);
732
+ data[2] = bswap32(data[2]);
733
+# endif
734
+ b = (data[0] & 0x3f) << 2;
735
+ data[0] >>= 6;
736
+ g = (data[0] & 0x3f) << 2;
737
+ data[0] >>= 6;
738
+ r = (data[0] & 0x3f) << 2;
739
+ data[0] >>= 6;
740
+ if (data[0] & 1) {
741
+ SKIP_PIXEL(dest);
742
+ } else {
743
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
744
+ }
745
+ data[0] >>= 6;
746
+ b = (data[0] & 0x3f) << 2;
747
+ data[0] >>= 6;
748
+ g = ((data[1] & 0xf) << 4) | (data[0] << 2);
749
+ data[1] >>= 4;
750
+ r = (data[1] & 0x3f) << 2;
751
+ data[1] >>= 6;
752
+ if (data[1] & 1) {
753
+ SKIP_PIXEL(dest);
754
+ } else {
755
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
756
+ }
757
+ data[1] >>= 6;
758
+ b = (data[1] & 0x3f) << 2;
759
+ data[1] >>= 6;
760
+ g = (data[1] & 0x3f) << 2;
761
+ data[1] >>= 6;
762
+ r = ((data[2] & 0x3) << 6) | (data[1] << 2);
763
+ data[2] >>= 2;
764
+ if (data[2] & 1) {
765
+ SKIP_PIXEL(dest);
766
+ } else {
767
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
768
+ }
769
+ data[2] >>= 6;
770
+ b = (data[2] & 0x3f) << 2;
771
+ data[2] >>= 6;
772
+ g = (data[2] & 0x3f) << 2;
773
+ data[2] >>= 6;
774
+ r = data[2] << 2;
775
+ data[2] >>= 6;
776
+ if (data[2] & 1) {
777
+ SKIP_PIXEL(dest);
778
+ } else {
779
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
780
+ }
781
+ width -= 4;
782
+ }
783
+}
784
+
785
+static void pxa2xx_draw_line24(void *opaque, uint8_t *dest, const uint8_t *src,
786
+ int width, int deststep)
787
+{
788
+ uint32_t data;
789
+ unsigned int r, g, b;
790
+ while (width > 0) {
791
+ data = *(uint32_t *) src;
792
+#ifdef SWAP_WORDS
793
+ data = bswap32(data);
794
+#endif
795
+ b = data & 0xff;
796
+ data >>= 8;
797
+ g = data & 0xff;
798
+ data >>= 8;
799
+ r = data & 0xff;
800
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
801
+ width -= 1;
802
+ src += 4;
803
+ }
804
+}
805
+
806
+static void pxa2xx_draw_line24t(void *opaque, uint8_t *dest, const uint8_t *src,
807
+ int width, int deststep)
808
+{
809
+ uint32_t data;
810
+ unsigned int r, g, b;
811
+ while (width > 0) {
812
+ data = *(uint32_t *) src;
813
+#ifdef SWAP_WORDS
814
+ data = bswap32(data);
815
+#endif
816
+ b = (data & 0x7f) << 1;
817
+ data >>= 7;
818
+ g = data & 0xff;
819
+ data >>= 8;
820
+ r = data & 0xff;
821
+ data >>= 8;
822
+ if (data & 1) {
823
+ SKIP_PIXEL(dest);
824
+ } else {
825
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
826
+ }
827
+ width -= 1;
828
+ src += 4;
829
+ }
830
+}
831
+
832
+static void pxa2xx_draw_line25(void *opaque, uint8_t *dest, const uint8_t *src,
833
+ int width, int deststep)
834
+{
835
+ uint32_t data;
836
+ unsigned int r, g, b;
837
+ while (width > 0) {
838
+ data = *(uint32_t *) src;
839
+#ifdef SWAP_WORDS
840
+ data = bswap32(data);
841
+#endif
842
+ b = data & 0xff;
843
+ data >>= 8;
844
+ g = data & 0xff;
845
+ data >>= 8;
846
+ r = data & 0xff;
847
+ data >>= 8;
848
+ if (data & 1) {
849
+ SKIP_PIXEL(dest);
850
+ } else {
851
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
852
+ }
853
+ width -= 1;
854
+ src += 4;
855
+ }
856
+}
857
+
858
+/* Overlay planes disabled, no transparency */
859
+static drawfn pxa2xx_draw_fn_32[16] = {
860
+ [0 ... 0xf] = NULL,
861
+ [pxa_lcdc_2bpp] = pxa2xx_draw_line2,
862
+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
863
+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
864
+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16,
865
+ [pxa_lcdc_18bpp] = pxa2xx_draw_line18,
866
+ [pxa_lcdc_18pbpp] = pxa2xx_draw_line18p,
867
+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24,
868
+};
869
+
870
+/* Overlay planes enabled, transparency used */
871
+static drawfn pxa2xx_draw_fn_32t[16] = {
872
+ [0 ... 0xf] = NULL,
873
+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
874
+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
875
+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16t,
876
+ [pxa_lcdc_19bpp] = pxa2xx_draw_line19,
877
+ [pxa_lcdc_19pbpp] = pxa2xx_draw_line19p,
878
+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24t,
879
+ [pxa_lcdc_25bpp] = pxa2xx_draw_line25,
880
+};
881
+
882
+#undef COPY_PIXEL
883
+#undef SKIP_PIXEL
884
+
885
+#ifdef SWAP_WORDS
886
+# undef SWAP_WORDS
887
+#endif
888
889
/* Route internal interrupt lines to the global IC */
890
static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
891
--
205
--
892
2.20.1
206
2.25.1
893
894
diff view generated by jsdifflib
[PULL 26/39] hw/misc: Add GPIOs for duty in NPCM7xx PWM
[PULL 04/32] target/arm: Merge zcr reginfo
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds GPIOs in NPCM7xx PWM module for its duty values.
3
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
4
The purpose of this is to connect it to the MFT module to provide
4
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
5
an input for measuring a PWM fan's RPM. Each PWM module has
5
while registering.
6
NPCM7XX_PWM_PER_MODULE of GPIOs, each one corresponds to
7
one PWM instance and can connect to multiple fan instances in MFT.
8
6
9
Reviewed-by: Doug Evans <dje@google.com>
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20210311180855.149764-2-wuhaotsh@google.com
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
11
---
16
include/hw/misc/npcm7xx_pwm.h | 4 +++-
12
target/arm/helper.c | 55 ++++++++++++++-------------------------------
17
hw/misc/npcm7xx_pwm.c | 4 ++++
13
1 file changed, 17 insertions(+), 38 deletions(-)
18
2 files changed, 7 insertions(+), 1 deletion(-)
19
14
20
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/npcm7xx_pwm.h
17
--- a/target/arm/helper.c
23
+++ b/include/hw/misc/npcm7xx_pwm.h
18
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxPWM {
19
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
25
* @iomem: Memory region through which registers are accessed.
26
* @clock: The PWM clock.
27
* @pwm: The PWM channels owned by this module.
28
+ * @duty_gpio_out: The duty cycle of each PWM channels as a output GPIO.
29
* @ppr: The prescaler register.
30
* @csr: The clock selector register.
31
* @pcr: The control register.
32
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState {
33
MemoryRegion iomem;
34
35
Clock *clock;
36
- NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
37
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
38
+ qemu_irq duty_gpio_out[NPCM7XX_PWM_PER_MODULE];
39
40
uint32_t ppr;
41
uint32_t csr;
42
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/misc/npcm7xx_pwm.c
45
+++ b/hw/misc/npcm7xx_pwm.c
46
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
47
trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
48
p->index, p->duty, duty);
49
p->duty = duty;
50
+ qemu_set_irq(p->module->duty_gpio_out[p->index], p->duty);
51
}
20
}
52
}
21
}
53
22
54
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_init(Object *obj)
23
-static const ARMCPRegInfo zcr_el1_reginfo = {
55
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
24
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
56
int i;
25
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
57
26
- .access = PL1_RW, .type = ARM_CP_SVE,
58
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->pwm) != NPCM7XX_PWM_PER_MODULE);
27
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
59
for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
28
- .writefn = zcr_write, .raw_writefn = raw_write
60
NPCM7xxPWM *p = &s->pwm[i];
29
-};
61
p->module = s;
30
-
62
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_init(Object *obj)
31
-static const ARMCPRegInfo zcr_el2_reginfo = {
63
object_property_add_uint32_ptr(obj, "duty[*]",
32
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
64
&s->pwm[i].duty, OBJ_PROP_FLAG_READ);
33
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
34
- .access = PL2_RW, .type = ARM_CP_SVE,
35
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
36
- .writefn = zcr_write, .raw_writefn = raw_write
37
-};
38
-
39
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
40
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
41
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
42
- .access = PL2_RW, .type = ARM_CP_SVE,
43
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
44
-};
45
-
46
-static const ARMCPRegInfo zcr_el3_reginfo = {
47
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
48
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
49
- .access = PL3_RW, .type = ARM_CP_SVE,
50
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
51
- .writefn = zcr_write, .raw_writefn = raw_write
52
+static const ARMCPRegInfo zcr_reginfo[] = {
53
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
54
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
55
+ .access = PL1_RW, .type = ARM_CP_SVE,
56
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
57
+ .writefn = zcr_write, .raw_writefn = raw_write },
58
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
59
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
60
+ .access = PL2_RW, .type = ARM_CP_SVE,
61
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
62
+ .writefn = zcr_write, .raw_writefn = raw_write },
63
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
64
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
65
+ .access = PL3_RW, .type = ARM_CP_SVE,
66
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
67
+ .writefn = zcr_write, .raw_writefn = raw_write },
68
};
69
70
void hw_watchpoint_update(ARMCPU *cpu, int n)
71
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
65
}
72
}
66
+ qdev_init_gpio_out_named(DEVICE(s), s->duty_gpio_out,
73
67
+ "duty-gpio-out", NPCM7XX_PWM_PER_MODULE);
74
if (cpu_isar_feature(aa64_sve, cpu)) {
68
}
75
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
69
76
- if (arm_feature(env, ARM_FEATURE_EL2)) {
70
static const VMStateDescription vmstate_npcm7xx_pwm = {
77
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
78
- } else {
79
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
80
- }
81
- if (arm_feature(env, ARM_FEATURE_EL3)) {
82
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
83
- }
84
+ define_arm_cp_regs(cpu, zcr_reginfo);
85
}
86
87
#ifdef TARGET_AARCH64
71
--
88
--
72
2.20.1
89
2.25.1
73
74
diff view generated by jsdifflib
[PULL 28/39] hw/arm: Add MFT device to NPCM7xx Soc
[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds the recently implemented MFT device to the NPCM7XX
3
This register is present for either VHE or Debugv8p2.
4
SoC file.
5
4
6
Reviewed-by: Doug Evans <dje@google.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20210311180855.149764-4-wuhaotsh@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
docs/system/arm/nuvoton.rst | 2 +-
10
target/arm/helper.c | 15 +++++++++++----
14
include/hw/arm/npcm7xx.h | 2 ++
11
1 file changed, 11 insertions(+), 4 deletions(-)
15
hw/arm/npcm7xx.c | 45 ++++++++++++++++++++++++++++++-------
16
3 files changed, 40 insertions(+), 9 deletions(-)
17
12
18
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/nuvoton.rst
15
--- a/target/arm/helper.c
21
+++ b/docs/system/arm/nuvoton.rst
16
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ Supported devices
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
23
* Pulse Width Modulation (PWM)
18
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
24
* SMBus controller (SMBF)
25
* Ethernet controller (EMC)
26
+ * Tachometer
27
28
Missing devices
29
---------------
30
@@ -XXX,XX +XXX,XX @@ Missing devices
31
* Peripheral SPI controller (PSPI)
32
* SD/MMC host
33
* PECI interface
34
- * Tachometer
35
* PCI and PCIe root complex and bridges
36
* VDM and MCTP support
37
* Serial I/O expansion
38
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/npcm7xx.h
41
+++ b/include/hw/arm/npcm7xx.h
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/mem/npcm7xx_mc.h"
44
#include "hw/misc/npcm7xx_clk.h"
45
#include "hw/misc/npcm7xx_gcr.h"
46
+#include "hw/misc/npcm7xx_mft.h"
47
#include "hw/misc/npcm7xx_pwm.h"
48
#include "hw/misc/npcm7xx_rng.h"
49
#include "hw/net/npcm7xx_emc.h"
50
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
51
NPCM7xxTimerCtrlState tim[3];
52
NPCM7xxADCState adc;
53
NPCM7xxPWMState pwm[2];
54
+ NPCM7xxMFTState mft[8];
55
NPCM7xxOTPState key_storage;
56
NPCM7xxOTPState fuse_array;
57
NPCM7xxMCState mc;
58
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/npcm7xx.c
61
+++ b/hw/arm/npcm7xx.c
62
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
63
NPCM7XX_SMBUS15_IRQ,
64
NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
65
NPCM7XX_PWM1_IRQ, /* PWM module 1 */
66
+ NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
67
+ NPCM7XX_MFT1_IRQ, /* MFT module 1 */
68
+ NPCM7XX_MFT2_IRQ, /* MFT module 2 */
69
+ NPCM7XX_MFT3_IRQ, /* MFT module 3 */
70
+ NPCM7XX_MFT4_IRQ, /* MFT module 4 */
71
+ NPCM7XX_MFT5_IRQ, /* MFT module 5 */
72
+ NPCM7XX_MFT6_IRQ, /* MFT module 6 */
73
+ NPCM7XX_MFT7_IRQ, /* MFT module 7 */
74
NPCM7XX_EMC2RX_IRQ = 114,
75
NPCM7XX_EMC2TX_IRQ,
76
NPCM7XX_GPIO0_IRQ = 116,
77
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_pwm_addr[] = {
78
0xf0104000,
79
};
19
};
80
20
81
+/* Register base address for each MFT Module */
21
+static const ARMCPRegInfo contextidr_el2 = {
82
+static const hwaddr npcm7xx_mft_addr[] = {
22
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
83
+ 0xf0180000,
23
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
84
+ 0xf0181000,
24
+ .access = PL2_RW,
85
+ 0xf0182000,
25
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
86
+ 0xf0183000,
87
+ 0xf0184000,
88
+ 0xf0185000,
89
+ 0xf0186000,
90
+ 0xf0187000,
91
+};
26
+};
92
+
27
+
93
/* Direct memory-mapped access to each SMBus Module. */
28
static const ARMCPRegInfo vhe_reginfo[] = {
94
static const hwaddr npcm7xx_smbus_addr[] = {
29
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
95
0xf0080000,
30
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
96
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
31
- .access = PL2_RW,
97
object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
32
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
33
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
34
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
35
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
37
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
98
}
38
}
99
39
100
+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
40
+ if (cpu_isar_feature(aa64_vh, cpu) ||
101
+ object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
41
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
42
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
102
+ }
43
+ }
103
+
44
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
104
for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
45
define_arm_cp_regs(cpu, vhe_reginfo);
105
object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
106
}
46
}
107
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
108
sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
109
}
110
111
+ /* MFT Modules. Cannot fail. */
112
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));
113
+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
114
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
115
+
116
+ qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
117
+ qdev_get_clock_out(DEVICE(&s->clk),
118
+ "apb4-clock"));
119
+ sysbus_realize(sbd, &error_abort);
120
+ sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);
121
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));
122
+ }
123
+
124
/*
125
* EMC Modules. Cannot fail.
126
* The mapping of the device to its netdev backend works as follows:
127
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
128
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
129
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
130
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
131
- create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
132
- create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
133
- create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
134
- create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
135
- create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
136
- create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
137
- create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
138
- create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
139
create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
140
create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
141
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
142
--
47
--
143
2.20.1
48
2.25.1
144
145
diff view generated by jsdifflib
[PULL 14/39] target/arm: Update BRKA, BRKB, BRKN for PREDDESC
[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since b64ee454a4a0, all predicate operations should be
3
Previously we were defining some of these in user-only mode,
4
using these field macros for predicates.
4
but none of them are accessible from user-only, therefore
5
5
define them only in system mode.
6
7
This will shortly be used from cpu_tcg.c also.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210309155305.11301-6-richard.henderson@linaro.org
11
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/sve_helper.c | 30 ++++++++++++++----------------
14
target/arm/internals.h | 6 ++++
12
target/arm/translate-sve.c | 4 ++--
15
target/arm/cpu64.c | 64 +++---------------------------------------
13
2 files changed, 16 insertions(+), 18 deletions(-)
16
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
14
17
3 files changed, 69 insertions(+), 60 deletions(-)
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
21
--- a/target/arm/internals.h
18
+++ b/target/arm/sve_helper.c
22
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static uint32_t do_zero(ARMPredicateReg *d, intptr_t oprsz)
23
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
20
void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg,
24
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
21
uint32_t pred_desc)
25
#endif
26
27
+#ifdef CONFIG_USER_ONLY
28
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
29
+#else
30
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
31
+#endif
32
+
33
#endif
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu64.c
37
+++ b/target/arm/cpu64.c
38
@@ -XXX,XX +XXX,XX @@
39
#include "hvf_arm.h"
40
#include "qapi/visitor.h"
41
#include "hw/qdev-properties.h"
42
-#include "cpregs.h"
43
+#include "internals.h"
44
45
46
-#ifndef CONFIG_USER_ONLY
47
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
48
-{
49
- ARMCPU *cpu = env_archcpu(env);
50
-
51
- /* Number of cores is in [25:24]; otherwise we RAZ */
52
- return (cpu->core_count - 1) << 24;
53
-}
54
-#endif
55
-
56
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
57
-#ifndef CONFIG_USER_ONLY
58
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
59
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
60
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
61
- .writefn = arm_cp_write_ignore },
62
- { .name = "L2CTLR",
63
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
64
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
65
- .writefn = arm_cp_write_ignore },
66
-#endif
67
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
68
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
69
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
- { .name = "L2ECTLR",
71
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
74
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
75
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
77
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
78
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "CPUACTLR",
80
- .cp = 15, .opc1 = 0, .crm = 15,
81
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
82
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
83
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
84
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- { .name = "CPUECTLR",
86
- .cp = 15, .opc1 = 1, .crm = 15,
87
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
88
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
89
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
90
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- { .name = "CPUMERRSR",
92
- .cp = 15, .opc1 = 2, .crm = 15,
93
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
94
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
95
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
96
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
- { .name = "L2MERRSR",
98
- .cp = 15, .opc1 = 3, .crm = 15,
99
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
100
-};
101
-
102
static void aarch64_a57_initfn(Object *obj)
22
{
103
{
23
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
104
ARMCPU *cpu = ARM_CPU(obj);
24
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
105
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
25
if (last_active_pred(vn, vg, oprsz)) {
106
cpu->gic_num_lrs = 4;
26
compute_brk_z(vd, vm, vg, oprsz, true);
107
cpu->gic_vpribits = 5;
27
} else {
108
cpu->gic_vprebits = 5;
28
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg,
109
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
29
uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg,
110
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
30
uint32_t pred_desc)
31
{
32
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
33
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
34
if (last_active_pred(vn, vg, oprsz)) {
35
return compute_brks_z(vd, vm, vg, oprsz, true);
36
} else {
37
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg,
38
void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg,
39
uint32_t pred_desc)
40
{
41
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
42
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
43
if (last_active_pred(vn, vg, oprsz)) {
44
compute_brk_z(vd, vm, vg, oprsz, false);
45
} else {
46
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg,
47
uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg,
48
uint32_t pred_desc)
49
{
50
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
51
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
52
if (last_active_pred(vn, vg, oprsz)) {
53
return compute_brks_z(vd, vm, vg, oprsz, false);
54
} else {
55
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg,
56
57
void HELPER(sve_brka_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
58
{
59
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
60
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
61
compute_brk_z(vd, vn, vg, oprsz, true);
62
}
111
}
63
112
64
uint32_t HELPER(sve_brkas_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
113
static void aarch64_a53_initfn(Object *obj)
65
{
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
66
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
115
cpu->gic_num_lrs = 4;
67
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
116
cpu->gic_vpribits = 5;
68
return compute_brks_z(vd, vn, vg, oprsz, true);
117
cpu->gic_vprebits = 5;
118
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
119
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
69
}
120
}
70
121
71
void HELPER(sve_brkb_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
122
static void aarch64_a72_initfn(Object *obj)
72
{
123
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
73
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
124
cpu->gic_num_lrs = 4;
74
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
125
cpu->gic_vpribits = 5;
75
compute_brk_z(vd, vn, vg, oprsz, false);
126
cpu->gic_vprebits = 5;
127
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
128
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
76
}
129
}
77
130
78
uint32_t HELPER(sve_brkbs_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
131
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
79
{
132
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
80
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
81
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
82
return compute_brks_z(vd, vn, vg, oprsz, false);
83
}
84
85
void HELPER(sve_brka_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
86
{
87
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
88
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
89
compute_brk_m(vd, vn, vg, oprsz, true);
90
}
91
92
uint32_t HELPER(sve_brkas_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
93
{
94
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
95
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
96
return compute_brks_m(vd, vn, vg, oprsz, true);
97
}
98
99
void HELPER(sve_brkb_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
100
{
101
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
102
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
103
compute_brk_m(vd, vn, vg, oprsz, false);
104
}
105
106
uint32_t HELPER(sve_brkbs_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
107
{
108
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
109
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
110
return compute_brks_m(vd, vn, vg, oprsz, false);
111
}
112
113
void HELPER(sve_brkn)(void *vd, void *vn, void *vg, uint32_t pred_desc)
114
{
115
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
116
-
117
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
118
if (!last_active_pred(vn, vg, oprsz)) {
119
do_zero(vd, oprsz);
120
}
121
@@ -XXX,XX +XXX,XX @@ static uint32_t predtest_ones(ARMPredicateReg *d, intptr_t oprsz,
122
123
uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
124
{
125
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
126
-
127
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
128
if (last_active_pred(vn, vg, oprsz)) {
129
return predtest_ones(vd, oprsz, -1);
130
} else {
131
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
132
index XXXXXXX..XXXXXXX 100644
133
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/translate-sve.c
134
--- a/target/arm/cpu_tcg.c
134
+++ b/target/arm/translate-sve.c
135
+++ b/target/arm/cpu_tcg.c
135
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
136
@@ -XXX,XX +XXX,XX @@
136
TCGv_ptr n = tcg_temp_new_ptr();
137
#endif
137
TCGv_ptr m = tcg_temp_new_ptr();
138
#include "cpregs.h"
138
TCGv_ptr g = tcg_temp_new_ptr();
139
139
- TCGv_i32 t = tcg_const_i32(vsz - 2);
140
+#ifndef CONFIG_USER_ONLY
140
+ TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
141
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
141
142
+{
142
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
143
+ ARMCPU *cpu = env_archcpu(env);
143
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
144
+
144
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
145
+ /* Number of cores is in [25:24]; otherwise we RAZ */
145
TCGv_ptr d = tcg_temp_new_ptr();
146
+ return (cpu->core_count - 1) << 24;
146
TCGv_ptr n = tcg_temp_new_ptr();
147
+}
147
TCGv_ptr g = tcg_temp_new_ptr();
148
+
148
- TCGv_i32 t = tcg_const_i32(vsz - 2);
149
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
149
+ TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
150
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
150
151
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
151
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
152
+ .access = PL1_RW, .readfn = l2ctlr_read,
152
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
153
+ .writefn = arm_cp_write_ignore },
154
+ { .name = "L2CTLR",
155
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
156
+ .access = PL1_RW, .readfn = l2ctlr_read,
157
+ .writefn = arm_cp_write_ignore },
158
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
159
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
160
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
161
+ { .name = "L2ECTLR",
162
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
163
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
164
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
165
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
166
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
167
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
168
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
169
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
170
+ { .name = "CPUACTLR",
171
+ .cp = 15, .opc1 = 0, .crm = 15,
172
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
173
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
174
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
175
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
176
+ { .name = "CPUECTLR",
177
+ .cp = 15, .opc1 = 1, .crm = 15,
178
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
179
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
181
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
182
+ { .name = "CPUMERRSR",
183
+ .cp = 15, .opc1 = 2, .crm = 15,
184
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
185
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
186
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
187
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
188
+ { .name = "L2MERRSR",
189
+ .cp = 15, .opc1 = 3, .crm = 15,
190
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
191
+};
192
+
193
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
194
+{
195
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
196
+}
197
+#endif /* !CONFIG_USER_ONLY */
198
+
199
/* CPU models. These are not needed for the AArch64 linux-user build. */
200
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
201
153
--
202
--
154
2.20.1
203
2.25.1
155
156
diff view generated by jsdifflib
[PULL 03/39] intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With -Werror=maybe-uninitialized configuration we get
3
Instead of starting with cortex-a15 and adding v8 features to
4
../hw/i386/intel_iommu.c: In function ‘vtd_context_device_invalidate’:
4
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
5
../hw/i386/intel_iommu.c:1888:10: error: ‘mask’ may be used
5
This fixes the long-standing to-do where we only enabled v8
6
uninitialized in this function [-Werror=maybe-uninitialized]
6
features for user-only.
7
1888 | mask = ~mask;
8
| ~~~~~^~~~~~~
9
7
10
Add a g_assert_not_reached() to avoid the error.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
13
Reviewed-by: Peter Xu <peterx@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20210309102742.30442-2-eric.auger@redhat.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
12
---
18
hw/i386/intel_iommu.c | 2 ++
13
target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
19
1 file changed, 2 insertions(+)
14
1 file changed, 92 insertions(+), 59 deletions(-)
20
15
21
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
16
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/i386/intel_iommu.c
18
--- a/target/arm/cpu_tcg.c
24
+++ b/hw/i386/intel_iommu.c
19
+++ b/target/arm/cpu_tcg.c
25
@@ -XXX,XX +XXX,XX @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
20
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
26
case 3:
21
static void arm_max_initfn(Object *obj)
27
mask = 7; /* Mask bit 2:0 in the SID field */
22
{
28
break;
23
ARMCPU *cpu = ARM_CPU(obj);
29
+ default:
24
+ uint32_t t;
30
+ g_assert_not_reached();
25
31
}
26
- cortex_a15_initfn(obj);
32
mask = ~mask;
27
+ /* aarch64_a57_initfn, advertising none of the aarch64 features */
28
+ cpu->dtb_compatible = "arm,cortex-a57";
29
+ set_feature(&cpu->env, ARM_FEATURE_V8);
30
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
31
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
32
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
33
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
34
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
35
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
36
+ cpu->midr = 0x411fd070;
37
+ cpu->revidr = 0x00000000;
38
+ cpu->reset_fpsid = 0x41034070;
39
+ cpu->isar.mvfr0 = 0x10110222;
40
+ cpu->isar.mvfr1 = 0x12111111;
41
+ cpu->isar.mvfr2 = 0x00000043;
42
+ cpu->ctr = 0x8444c004;
43
+ cpu->reset_sctlr = 0x00c50838;
44
+ cpu->isar.id_pfr0 = 0x00000131;
45
+ cpu->isar.id_pfr1 = 0x00011011;
46
+ cpu->isar.id_dfr0 = 0x03010066;
47
+ cpu->id_afr0 = 0x00000000;
48
+ cpu->isar.id_mmfr0 = 0x10101105;
49
+ cpu->isar.id_mmfr1 = 0x40000000;
50
+ cpu->isar.id_mmfr2 = 0x01260000;
51
+ cpu->isar.id_mmfr3 = 0x02102211;
52
+ cpu->isar.id_isar0 = 0x02101110;
53
+ cpu->isar.id_isar1 = 0x13112111;
54
+ cpu->isar.id_isar2 = 0x21232042;
55
+ cpu->isar.id_isar3 = 0x01112131;
56
+ cpu->isar.id_isar4 = 0x00011142;
57
+ cpu->isar.id_isar5 = 0x00011121;
58
+ cpu->isar.id_isar6 = 0;
59
+ cpu->isar.dbgdidr = 0x3516d000;
60
+ cpu->clidr = 0x0a200023;
61
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
62
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
63
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
64
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
65
66
- /* old-style VFP short-vector support */
67
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
68
+ /* Add additional features supported by QEMU */
69
+ t = cpu->isar.id_isar5;
70
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
71
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
72
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
73
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
74
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
75
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
76
+ cpu->isar.id_isar5 = t;
77
+
78
+ t = cpu->isar.id_isar6;
79
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
80
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
81
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
82
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
83
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
84
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
85
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
86
+ cpu->isar.id_isar6 = t;
87
+
88
+ t = cpu->isar.mvfr1;
89
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
90
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
91
+ cpu->isar.mvfr1 = t;
92
+
93
+ t = cpu->isar.mvfr2;
94
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
95
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
96
+ cpu->isar.mvfr2 = t;
97
+
98
+ t = cpu->isar.id_mmfr3;
99
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
100
+ cpu->isar.id_mmfr3 = t;
101
+
102
+ t = cpu->isar.id_mmfr4;
103
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
104
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
105
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
106
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
107
+ cpu->isar.id_mmfr4 = t;
108
+
109
+ t = cpu->isar.id_pfr0;
110
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
111
+ cpu->isar.id_pfr0 = t;
112
+
113
+ t = cpu->isar.id_pfr2;
114
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
115
+ cpu->isar.id_pfr2 = t;
116
117
#ifdef CONFIG_USER_ONLY
118
/*
119
- * We don't set these in system emulation mode for the moment,
120
- * since we don't correctly set (all of) the ID registers to
121
- * advertise them.
122
+ * Break with true ARMv8 and add back old-style VFP short-vector support.
123
+ * Only do this for user-mode, where -cpu max is the default, so that
124
+ * older v6 and v7 programs are more likely to work without adjustment.
125
*/
126
- set_feature(&cpu->env, ARM_FEATURE_V8);
127
- {
128
- uint32_t t;
129
-
130
- t = cpu->isar.id_isar5;
131
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
132
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
133
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
134
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
135
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
136
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
137
- cpu->isar.id_isar5 = t;
138
-
139
- t = cpu->isar.id_isar6;
140
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
141
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
142
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
143
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
144
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
145
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
146
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
147
- cpu->isar.id_isar6 = t;
148
-
149
- t = cpu->isar.mvfr1;
150
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
151
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
152
- cpu->isar.mvfr1 = t;
153
-
154
- t = cpu->isar.mvfr2;
155
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
156
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
157
- cpu->isar.mvfr2 = t;
158
-
159
- t = cpu->isar.id_mmfr3;
160
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
161
- cpu->isar.id_mmfr3 = t;
162
-
163
- t = cpu->isar.id_mmfr4;
164
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
165
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
166
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
167
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
168
- cpu->isar.id_mmfr4 = t;
169
-
170
- t = cpu->isar.id_pfr0;
171
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
172
- cpu->isar.id_pfr0 = t;
173
-
174
- t = cpu->isar.id_pfr2;
175
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
176
- cpu->isar.id_pfr2 = t;
177
- }
178
-#endif /* CONFIG_USER_ONLY */
179
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
180
+#endif
181
}
182
#endif /* !TARGET_AARCH64 */
33
183
34
--
184
--
35
2.20.1
185
2.25.1
36
37
diff view generated by jsdifflib
[PULL 19/39] tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The image for Armbian 19.11.3 bionic has been removed from the armbian server.
3
We set this for qemu-system-aarch64, but failed to do so
4
Without the image as input the test arm_orangepi_bionic_19_11 cannot run.
4
for the strictly 32-bit emulation.
5
5
6
This commit removes the test completely and merges the code of the generic function
6
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
7
do_test_arm_orangepi_uboot_armbian back with the 20.08 test.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
10
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
11
Message-id: 20210310195820.21950-3-nieklinnenbank@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
tests/acceptance/boot_linux_console.py | 72 ++++++++------------------
12
target/arm/cpu_tcg.c | 4 ++++
15
1 file changed, 23 insertions(+), 49 deletions(-)
13
1 file changed, 4 insertions(+)
16
14
17
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
15
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/acceptance/boot_linux_console.py
17
--- a/target/arm/cpu_tcg.c
20
+++ b/tests/acceptance/boot_linux_console.py
18
+++ b/target/arm/cpu_tcg.c
21
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
19
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
22
# Wait for VM to shut down gracefully
20
t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
23
self.vm.wait()
21
cpu->isar.id_pfr2 = t;
24
22
25
- def do_test_arm_orangepi_uboot_armbian(self, image_path):
23
+ t = cpu->isar.id_dfr0;
26
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
24
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
27
+ 'Test artifacts fetched from unreliable apt.armbian.com')
25
+ cpu->isar.id_dfr0 = t;
28
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
29
+ def test_arm_orangepi_bionic_20_08(self):
30
+ """
31
+ :avocado: tags=arch:arm
32
+ :avocado: tags=machine:orangepi-pc
33
+ :avocado: tags=device:sd
34
+ """
35
+
26
+
36
+ # This test download a 275 MiB compressed image and expand it
27
#ifdef CONFIG_USER_ONLY
37
+ # to 1036 MiB, but the underlying filesystem is 1552 MiB...
28
/*
38
+ # As we expand it to 2 GiB we are safe.
29
* Break with true ARMv8 and add back old-style VFP short-vector support.
39
+
40
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
41
+ 'Armbian_20.08.1_Orangepipc_bionic_current_5.8.5.img.xz')
42
+ image_hash = ('b4d6775f5673486329e45a0586bf06b6'
43
+ 'dbe792199fd182ac6b9c7bb6c7d3e6dd')
44
+ image_path_xz = self.fetch_asset(image_url, asset_hash=image_hash,
45
+ algorithm='sha256')
46
+ image_path = archive.extract(image_path_xz, self.workdir)
47
+ image_pow2ceil_expand(image_path)
48
+
49
self.vm.set_console()
50
self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
51
'-nic', 'user',
52
@@ -XXX,XX +XXX,XX @@ def do_test_arm_orangepi_uboot_armbian(self, image_path):
53
'to <orangepipc>')
54
self.wait_for_console_pattern('Starting Load Kernel Modules...')
55
56
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
57
- 'Test artifacts fetched from unreliable apt.armbian.com')
58
- @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
59
- @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
60
- def test_arm_orangepi_bionic_19_11(self):
61
- """
62
- :avocado: tags=arch:arm
63
- :avocado: tags=machine:orangepi-pc
64
- :avocado: tags=device:sd
65
- """
66
-
67
- # This test download a 196MB compressed image and expand it to 1GB
68
- image_url = ('https://dl.armbian.com/orangepipc/archive/'
69
- 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
70
- image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
71
- image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
72
- image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
73
- image_path = os.path.join(self.workdir, image_name)
74
- process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
75
- image_pow2ceil_expand(image_path)
76
-
77
- self.do_test_arm_orangepi_uboot_armbian(image_path)
78
-
79
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
80
- 'Test artifacts fetched from unreliable apt.armbian.com')
81
- @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
82
- def test_arm_orangepi_bionic_20_08(self):
83
- """
84
- :avocado: tags=arch:arm
85
- :avocado: tags=machine:orangepi-pc
86
- :avocado: tags=device:sd
87
- """
88
-
89
- # This test download a 275 MiB compressed image and expand it
90
- # to 1036 MiB, but the underlying filesystem is 1552 MiB...
91
- # As we expand it to 2 GiB we are safe.
92
-
93
- image_url = ('https://dl.armbian.com/orangepipc/archive/'
94
- 'Armbian_20.08.1_Orangepipc_bionic_current_5.8.5.img.xz')
95
- image_hash = ('b4d6775f5673486329e45a0586bf06b6'
96
- 'dbe792199fd182ac6b9c7bb6c7d3e6dd')
97
- image_path_xz = self.fetch_asset(image_url, asset_hash=image_hash,
98
- algorithm='sha256')
99
- image_path = archive.extract(image_path_xz, self.workdir)
100
- image_pow2ceil_expand(image_path)
101
-
102
- self.do_test_arm_orangepi_uboot_armbian(image_path)
103
-
104
@skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
105
def test_arm_orangepi_uboot_netbsd9(self):
106
"""
107
--
30
--
108
2.20.1
31
2.25.1
109
110
diff view generated by jsdifflib
[PULL 02/39] hw/arm: versal: Add support for the XRAMs
[PULL 09/32] target/arm: Split out aa32_max_features
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Connect the support for the Versal Accelerator RAMs (XRAMs).
3
Share the code to set AArch32 max features so that we no
4
longer have code drift between qemu{-system,}-{arm,aarch64}.
4
5
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
8
Message-id: 20210308224637.2949533-3-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
docs/system/arm/xlnx-versal-virt.rst | 1 +
11
target/arm/internals.h | 2 +
12
include/hw/arm/xlnx-versal.h | 13 ++++++++++
12
target/arm/cpu64.c | 50 +-----------------
13
hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++
13
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
14
3 files changed, 50 insertions(+)
14
3 files changed, 65 insertions(+), 101 deletions(-)
15
15
16
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/xlnx-versal-virt.rst
18
--- a/target/arm/internals.h
19
+++ b/docs/system/arm/xlnx-versal-virt.rst
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ Implemented devices:
20
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
21
- 8 ADMA (Xilinx zDMA) channels
21
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
22
- 2 SD Controllers
22
#endif
23
- OCM (256KB of On Chip Memory)
23
24
+- XRAM (4MB of on chip Accelerator RAM)
24
+void aa32_max_features(ARMCPU *cpu);
25
- DDR memory
25
+
26
26
#endif
27
QEMU does not yet model any other devices, including the PL and the AI Engine.
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
29
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/xlnx-versal.h
29
--- a/target/arm/cpu64.c
31
+++ b/include/hw/arm/xlnx-versal.h
30
+++ b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
{
33
ARMCPU *cpu = ARM_CPU(obj);
34
uint64_t t;
35
- uint32_t u;
36
37
if (kvm_enabled() || hvf_enabled()) {
38
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
41
cpu->isar.id_aa64zfr0 = t;
42
43
- /* Replicate the same data to the 32-bit id registers. */
44
- u = cpu->isar.id_isar5;
45
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
46
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
47
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
48
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
49
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
50
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
51
- cpu->isar.id_isar5 = u;
52
-
53
- u = cpu->isar.id_isar6;
54
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
55
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
56
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
57
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
58
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
59
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
60
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
61
- cpu->isar.id_isar6 = u;
62
-
63
- u = cpu->isar.id_pfr0;
64
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
65
- cpu->isar.id_pfr0 = u;
66
-
67
- u = cpu->isar.id_pfr2;
68
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
69
- cpu->isar.id_pfr2 = u;
70
-
71
- u = cpu->isar.id_mmfr3;
72
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
73
- cpu->isar.id_mmfr3 = u;
74
-
75
- u = cpu->isar.id_mmfr4;
76
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
77
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
78
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
79
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
80
- cpu->isar.id_mmfr4 = u;
81
-
82
t = cpu->isar.id_aa64dfr0;
83
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
84
cpu->isar.id_aa64dfr0 = t;
85
86
- u = cpu->isar.id_dfr0;
87
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
88
- cpu->isar.id_dfr0 = u;
89
-
90
- u = cpu->isar.mvfr1;
91
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
92
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
93
- cpu->isar.mvfr1 = u;
94
+ /* Replicate the same data to the 32-bit id registers. */
95
+ aa32_max_features(cpu);
96
97
#ifdef CONFIG_USER_ONLY
98
/*
99
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/cpu_tcg.c
102
+++ b/target/arm/cpu_tcg.c
32
@@ -XXX,XX +XXX,XX @@
103
@@ -XXX,XX +XXX,XX @@
33
104
#endif
34
#include "hw/sysbus.h"
105
#include "cpregs.h"
35
#include "hw/arm/boot.h"
106
36
+#include "hw/or-irq.h"
107
+
37
#include "hw/sd/sdhci.h"
108
+/* Share AArch32 -cpu max features with AArch64. */
38
#include "hw/intc/arm_gicv3.h"
109
+void aa32_max_features(ARMCPU *cpu)
39
#include "hw/char/pl011.h"
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/rtc/xlnx-zynqmp-rtc.h"
42
#include "qom/object.h"
43
#include "hw/usb/xlnx-usb-subsystem.h"
44
+#include "hw/misc/xlnx-versal-xramc.h"
45
46
#define TYPE_XLNX_VERSAL "xlnx-versal"
47
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
48
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
49
#define XLNX_VERSAL_NR_GEMS 2
50
#define XLNX_VERSAL_NR_ADMAS 8
51
#define XLNX_VERSAL_NR_SDS 2
52
+#define XLNX_VERSAL_NR_XRAM 4
53
#define XLNX_VERSAL_NR_IRQS 192
54
55
struct Versal {
56
@@ -XXX,XX +XXX,XX @@ struct Versal {
57
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
58
VersalUsb2 usb;
59
} iou;
60
+
61
+ struct {
62
+ qemu_or_irq irq_orgate;
63
+ XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
64
+ } xram;
65
} lpd;
66
67
/* The Platform Management Controller subsystem. */
68
@@ -XXX,XX +XXX,XX @@ struct Versal {
69
#define VERSAL_GEM1_IRQ_0 58
70
#define VERSAL_GEM1_WAKE_IRQ_0 59
71
#define VERSAL_ADMA_IRQ_0 60
72
+#define VERSAL_XRAM_IRQ_0 79
73
#define VERSAL_RTC_APB_ERR_IRQ 121
74
#define VERSAL_SD0_IRQ_0 126
75
#define VERSAL_RTC_ALARM_IRQ 142
76
@@ -XXX,XX +XXX,XX @@ struct Versal {
77
#define MM_OCM 0xfffc0000U
78
#define MM_OCM_SIZE 0x40000
79
80
+#define MM_XRAM 0xfe800000
81
+#define MM_XRAMC 0xff8e0000
82
+#define MM_XRAMC_SIZE 0x10000
83
+
84
#define MM_USB2_CTRL_REGS 0xFF9D0000
85
#define MM_USB2_CTRL_REGS_SIZE 0x10000
86
87
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/arm/xlnx-versal.c
90
+++ b/hw/arm/xlnx-versal.c
91
@@ -XXX,XX +XXX,XX @@
92
*/
93
94
#include "qemu/osdep.h"
95
+#include "qemu/units.h"
96
#include "qapi/error.h"
97
#include "qemu/log.h"
98
#include "qemu/module.h"
99
@@ -XXX,XX +XXX,XX @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
100
sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
101
}
102
103
+static void versal_create_xrams(Versal *s, qemu_irq *pic)
104
+{
110
+{
105
+ int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
111
+ uint32_t t;
106
+ DeviceState *orgate;
112
+
107
+ int i;
113
+ /* Add additional features supported by QEMU */
108
+
114
+ t = cpu->isar.id_isar5;
109
+ /* XRAM IRQs get ORed into a single line. */
115
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
110
+ object_initialize_child(OBJECT(s), "xram-irq-orgate",
116
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
111
+ &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
117
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
112
+ orgate = DEVICE(&s->lpd.xram.irq_orgate);
118
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
113
+ object_property_set_int(OBJECT(orgate),
119
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
114
+ "num-lines", nr_xrams, &error_fatal);
120
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
115
+ qdev_realize(orgate, NULL, &error_fatal);
121
+ cpu->isar.id_isar5 = t;
116
+ qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
122
+
117
+
123
+ t = cpu->isar.id_isar6;
118
+ for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
124
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
119
+ SysBusDevice *sbd;
125
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
120
+ MemoryRegion *mr;
126
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
121
+
127
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
122
+ object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
128
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
123
+ TYPE_XLNX_XRAM_CTRL);
129
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
124
+ sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
130
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
125
+ sysbus_realize(sbd, &error_fatal);
131
+ cpu->isar.id_isar6 = t;
126
+
132
+
127
+ mr = sysbus_mmio_get_region(sbd, 0);
133
+ t = cpu->isar.mvfr1;
128
+ memory_region_add_subregion(&s->mr_ps,
134
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
129
+ MM_XRAMC + i * MM_XRAMC_SIZE, mr);
135
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
130
+ mr = sysbus_mmio_get_region(sbd, 1);
136
+ cpu->isar.mvfr1 = t;
131
+ memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
137
+
132
+
138
+ t = cpu->isar.mvfr2;
133
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
139
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
134
+ }
140
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
141
+ cpu->isar.mvfr2 = t;
142
+
143
+ t = cpu->isar.id_mmfr3;
144
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
145
+ cpu->isar.id_mmfr3 = t;
146
+
147
+ t = cpu->isar.id_mmfr4;
148
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
149
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
150
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
151
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
152
+ cpu->isar.id_mmfr4 = t;
153
+
154
+ t = cpu->isar.id_pfr0;
155
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
156
+ cpu->isar.id_pfr0 = t;
157
+
158
+ t = cpu->isar.id_pfr2;
159
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
160
+ cpu->isar.id_pfr2 = t;
161
+
162
+ t = cpu->isar.id_dfr0;
163
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
164
+ cpu->isar.id_dfr0 = t;
135
+}
165
+}
136
+
166
+
137
/* This takes the board allocated linear DDR memory and creates aliases
167
#ifndef CONFIG_USER_ONLY
138
* for each split DDR range/aperture on the Versal address map.
168
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
139
*/
169
{
140
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
170
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
141
versal_create_admas(s, pic);
171
static void arm_max_initfn(Object *obj)
142
versal_create_sds(s, pic);
172
{
143
versal_create_rtc(s, pic);
173
ARMCPU *cpu = ARM_CPU(obj);
144
+ versal_create_xrams(s, pic);
174
- uint32_t t;
145
versal_map_ddr(s);
175
146
versal_unimp(s);
176
/* aarch64_a57_initfn, advertising none of the aarch64 features */
147
177
cpu->dtb_compatible = "arm,cortex-a57";
178
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
179
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
180
define_cortex_a72_a57_a53_cp_reginfo(cpu);
181
182
- /* Add additional features supported by QEMU */
183
- t = cpu->isar.id_isar5;
184
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
185
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
186
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
187
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
188
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
189
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
190
- cpu->isar.id_isar5 = t;
191
-
192
- t = cpu->isar.id_isar6;
193
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
194
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
195
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
196
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
197
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
198
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
199
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
200
- cpu->isar.id_isar6 = t;
201
-
202
- t = cpu->isar.mvfr1;
203
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
204
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
205
- cpu->isar.mvfr1 = t;
206
-
207
- t = cpu->isar.mvfr2;
208
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
- cpu->isar.mvfr2 = t;
211
-
212
- t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
- cpu->isar.id_mmfr3 = t;
215
-
216
- t = cpu->isar.id_mmfr4;
217
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
218
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
219
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
220
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
221
- cpu->isar.id_mmfr4 = t;
222
-
223
- t = cpu->isar.id_pfr0;
224
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
225
- cpu->isar.id_pfr0 = t;
226
-
227
- t = cpu->isar.id_pfr2;
228
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
229
- cpu->isar.id_pfr2 = t;
230
-
231
- t = cpu->isar.id_dfr0;
232
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
233
- cpu->isar.id_dfr0 = t;
234
+ aa32_max_features(cpu);
235
236
#ifdef CONFIG_USER_ONLY
237
/*
148
--
238
--
149
2.20.1
239
2.25.1
150
151
diff view generated by jsdifflib
[PULL 05/39] virtio-iommu: Handle non power of 2 range invalidations
[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Unmap notifiers work with an address mask assuming an
3
Update the legacy feature names to the current names.
4
invalidation range of a power of 2. Nothing mandates this
4
Provide feature names for id changes that were not marked.
5
in the VIRTIO-IOMMU spec.
5
Sort the field updates into increasing bitfield order.
6
6
7
So in case the range is not a power of 2, split it into
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
several invalidations.
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
9
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Peter Xu <peterx@redhat.com>
12
Message-id: 20210309102742.30442-4-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
hw/virtio/virtio-iommu.c | 19 ++++++++++++++++---
12
target/arm/cpu64.c | 100 +++++++++++++++++++++----------------------
16
1 file changed, 16 insertions(+), 3 deletions(-)
13
target/arm/cpu_tcg.c | 48 ++++++++++-----------
14
2 files changed, 74 insertions(+), 74 deletions(-)
17
15
18
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/virtio/virtio-iommu.c
18
--- a/target/arm/cpu64.c
21
+++ b/hw/virtio/virtio-iommu.c
19
+++ b/target/arm/cpu64.c
22
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_notify_unmap(IOMMUMemoryRegion *mr, hwaddr virt_start,
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
23
hwaddr virt_end)
21
cpu->midr = t;
24
{
22
25
IOMMUTLBEvent event;
23
t = cpu->isar.id_aa64isar0;
26
+ uint64_t delta = virt_end - virt_start;
24
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
27
25
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
28
if (!(mr->iommu_notify_flags & IOMMU_NOTIFIER_UNMAP)) {
26
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
29
return;
27
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
30
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_notify_unmap(IOMMUMemoryRegion *mr, hwaddr virt_start,
28
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
31
29
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
32
event.type = IOMMU_NOTIFIER_UNMAP;
30
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
33
event.entry.target_as = &address_space_memory;
31
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
34
- event.entry.addr_mask = virt_end - virt_start;
32
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
35
- event.entry.iova = virt_start;
33
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
36
event.entry.perm = IOMMU_NONE;
34
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
37
event.entry.translated_addr = 0;
35
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
38
+ event.entry.addr_mask = delta;
36
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
39
+ event.entry.iova = virt_start;
37
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
40
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
41
- memory_region_notify_iommu(mr, 0, event);
39
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
42
+ if (delta == UINT64_MAX) {
40
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
43
+ memory_region_notify_iommu(mr, 0, event);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
44
+ }
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
45
+
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
46
+
44
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
47
+ while (virt_start != virt_end + 1) {
45
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
48
+ uint64_t mask = dma_aligned_pow2_mask(virt_start, virt_end, 64);
46
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
49
+
47
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
50
+ event.entry.addr_mask = mask;
48
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
51
+ event.entry.iova = virt_start;
49
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
52
+ memory_region_notify_iommu(mr, 0, event);
50
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
53
+ virt_start += mask + 1;
51
cpu->isar.id_aa64isar0 = t;
54
+ }
52
53
t = cpu->isar.id_aa64isar1;
54
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
55
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
56
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
57
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
58
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
59
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
61
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
62
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
63
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
64
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
65
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
66
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
67
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
68
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
69
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
70
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
71
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
72
cpu->isar.id_aa64isar1 = t;
73
74
t = cpu->isar.id_aa64pfr0;
75
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
76
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
77
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
78
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
79
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
80
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
81
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
82
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
83
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
84
cpu->isar.id_aa64pfr0 = t;
85
86
t = cpu->isar.id_aa64pfr1;
87
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
88
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
89
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
90
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
91
/*
92
* Begin with full support for MTE. This will be downgraded to MTE=0
93
* during realize if the board provides no tag memory, much like
94
* we do for EL2 with the virtualization=on property.
95
*/
96
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
97
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
98
cpu->isar.id_aa64pfr1 = t;
99
100
t = cpu->isar.id_aa64mmfr0;
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
102
cpu->isar.id_aa64mmfr0 = t;
103
104
t = cpu->isar.id_aa64mmfr1;
105
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
106
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
107
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
108
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
109
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
110
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
111
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
112
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
113
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
114
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
115
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
116
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
117
cpu->isar.id_aa64mmfr1 = t;
118
119
t = cpu->isar.id_aa64mmfr2;
120
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
121
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
122
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
123
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
124
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
125
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
126
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
127
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
128
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
129
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
130
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
131
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
132
cpu->isar.id_aa64mmfr2 = t;
133
134
t = cpu->isar.id_aa64zfr0;
135
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
136
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
137
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
138
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
139
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
140
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
141
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
142
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
143
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
144
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
145
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
146
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
147
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
148
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
149
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
150
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
151
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
152
cpu->isar.id_aa64zfr0 = t;
153
154
t = cpu->isar.id_aa64dfr0;
155
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
156
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
157
cpu->isar.id_aa64dfr0 = t;
158
159
/* Replicate the same data to the 32-bit id registers. */
160
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/cpu_tcg.c
163
+++ b/target/arm/cpu_tcg.c
164
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
165
166
/* Add additional features supported by QEMU */
167
t = cpu->isar.id_isar5;
168
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
169
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
170
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
171
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
172
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
173
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
174
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
175
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
176
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
177
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
178
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
179
cpu->isar.id_isar5 = t;
180
181
t = cpu->isar.id_isar6;
182
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
183
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
184
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
185
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
186
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
187
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
188
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
189
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
190
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
191
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
192
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
193
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
194
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
195
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
196
cpu->isar.id_isar6 = t;
197
198
t = cpu->isar.mvfr1;
199
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
200
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
201
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
202
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
203
cpu->isar.mvfr1 = t;
204
205
t = cpu->isar.mvfr2;
206
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
207
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
208
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
cpu->isar.mvfr2 = t;
211
212
t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
215
cpu->isar.id_mmfr3 = t;
216
217
t = cpu->isar.id_mmfr4;
218
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
219
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
220
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
221
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
222
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
223
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
224
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
225
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
226
cpu->isar.id_mmfr4 = t;
227
228
t = cpu->isar.id_pfr0;
229
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
230
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
231
cpu->isar.id_pfr0 = t;
232
233
t = cpu->isar.id_pfr2;
234
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
235
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
236
cpu->isar.id_pfr2 = t;
237
238
t = cpu->isar.id_dfr0;
239
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
240
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
241
cpu->isar.id_dfr0 = t;
55
}
242
}
56
243
57
static gboolean virtio_iommu_notify_unmap_cb(gpointer key, gpointer value,
58
--
244
--
59
2.20.1
245
2.25.1
60
61
diff view generated by jsdifflib
[PULL 24/39] accel: kvm: Fix kvm_type invocation
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Prior to commit f2ce39b4f067 a MachineClass kvm_type method
3
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
4
only needed to be registered to ensure it would be executed.
4
during arm_cpu_realizefn.
5
With commit f2ce39b4f067 a kvm-type machine property must also
6
be specified. hw/arm/virt relies on the kvm_type method to pass
7
its selected IPA limit to KVM, but this is not exposed as a
8
machine property. Restore the previous functionality of invoking
9
kvm_type when it's present.
10
5
11
Fixes: f2ce39b4f067 ("vl: make qemu_get_machine_opts static")
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
14
Message-id: 20210310135218.255205-2-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
include/hw/boards.h | 1 +
11
target/arm/cpu.c | 22 +++++++++++++---------
18
accel/kvm/kvm-all.c | 2 ++
12
1 file changed, 13 insertions(+), 9 deletions(-)
19
2 files changed, 3 insertions(+)
20
13
21
diff --git a/include/hw/boards.h b/include/hw/boards.h
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/boards.h
16
--- a/target/arm/cpu.c
24
+++ b/include/hw/boards.h
17
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
26
* @kvm_type:
19
*/
27
* Return the type of KVM corresponding to the kvm-type string option or
20
unset_feature(env, ARM_FEATURE_EL3);
28
* computed based on other criteria such as the host kernel capabilities.
21
29
+ * kvm-type may be NULL if it is not needed.
22
- /* Disable the security extension feature bits in the processor feature
30
* @numa_mem_supported:
23
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
31
* true if '--numa node.mem' option is supported and false otherwise
24
+ /*
32
* @smp_parse:
25
+ * Disable the security extension feature bits in the processor
33
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
26
+ * feature registers as well.
34
index XXXXXXX..XXXXXXX 100644
27
*/
35
--- a/accel/kvm/kvm-all.c
28
- cpu->isar.id_pfr1 &= ~0xf0;
36
+++ b/accel/kvm/kvm-all.c
29
- cpu->isar.id_aa64pfr0 &= ~0xf000;
37
@@ -XXX,XX +XXX,XX @@ static int kvm_init(MachineState *ms)
30
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
38
"kvm-type",
31
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
39
&error_abort);
32
+ ID_AA64PFR0, EL3, 0);
40
type = mc->kvm_type(ms, kvm_type);
41
+ } else if (mc->kvm_type) {
42
+ type = mc->kvm_type(ms, NULL);
43
}
33
}
44
34
45
do {
35
if (!cpu->has_el2) {
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
37
}
38
39
if (!arm_feature(env, ARM_FEATURE_EL2)) {
40
- /* Disable the hypervisor feature bits in the processor feature
41
- * registers if we don't have EL2. These are id_pfr1[15:12] and
42
- * id_aa64pfr0_el1[11:8].
43
+ /*
44
+ * Disable the hypervisor feature bits in the processor feature
45
+ * registers if we don't have EL2.
46
*/
47
- cpu->isar.id_aa64pfr0 &= ~0xf00;
48
- cpu->isar.id_pfr1 &= ~0xf000;
49
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
50
+ ID_AA64PFR0, EL2, 0);
51
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
52
+ ID_PFR1, VIRTUALIZATION, 0);
53
}
54
55
#ifndef CONFIG_USER_ONLY
46
--
56
--
47
2.20.1
57
2.25.1
48
49
diff view generated by jsdifflib
[PULL 16/39] target/arm: Update WHILE for PREDDESC
[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since b64ee454a4a0, all predicate operations should be
3
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
4
using these field macros for predicates.
4
is CONTEXTIDR_EL2, which is also conditionally implemented
5
with FEAT_VHE. The rest of the debug extension concerns the
6
External debug interface, which is outside the scope of QEMU.
5
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210309155305.11301-8-richard.henderson@linaro.org
10
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/sve_helper.c | 4 ++--
13
docs/system/arm/emulation.rst | 1 +
12
target/arm/translate-sve.c | 7 ++++---
14
target/arm/cpu.c | 1 +
13
2 files changed, 6 insertions(+), 5 deletions(-)
15
target/arm/cpu64.c | 1 +
16
target/arm/cpu_tcg.c | 2 ++
17
4 files changed, 5 insertions(+)
14
18
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
21
--- a/docs/system/arm/emulation.rst
18
+++ b/target/arm/sve_helper.c
22
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
24
- FEAT_BTI (Branch Target Identification)
21
uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
25
- FEAT_DIT (Data Independent Timing instructions)
22
{
26
- FEAT_DPB (DC CVAP instruction)
23
- uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
27
+- FEAT_Debugv8p2 (Debug changes for v8.2)
24
- intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
28
- FEAT_DotProd (Advanced SIMD dot product instructions)
25
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
29
- FEAT_FCMA (Floating-point complex number instructions)
26
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
30
- FEAT_FHM (Floating-point half-precision multiplication instructions)
27
uint64_t esz_mask = pred_esz_masks[esz];
31
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
28
ARMPredicateReg *d = vd;
29
uint32_t flags;
30
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
31
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/translate-sve.c
33
--- a/target/arm/cpu.c
33
+++ b/target/arm/translate-sve.c
34
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
35
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
35
TCGv_i64 op0, op1, t0, t1, tmax;
36
* feature registers as well.
36
TCGv_i32 t2, t3;
37
*/
37
TCGv_ptr ptr;
38
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
38
- unsigned desc, vsz = vec_full_reg_size(s);
39
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
39
+ unsigned vsz = vec_full_reg_size(s);
40
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
40
+ unsigned desc = 0;
41
ID_AA64PFR0, EL3, 0);
41
TCGCond cond;
42
}
42
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
43
if (!sve_access_check(s)) {
44
index XXXXXXX..XXXXXXX 100644
44
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
45
--- a/target/arm/cpu64.c
45
/* Scale elements to bits. */
46
+++ b/target/arm/cpu64.c
46
tcg_gen_shli_i32(t2, t2, a->esz);
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
47
48
cpu->isar.id_aa64zfr0 = t;
48
- desc = (vsz / 8) - 2;
49
49
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz);
50
t = cpu->isar.id_aa64dfr0;
50
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
51
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
51
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
52
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
52
t3 = tcg_const_i32(desc);
53
cpu->isar.id_aa64dfr0 = t;
53
54
54
ptr = tcg_temp_new_ptr();
55
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/cpu_tcg.c
58
+++ b/target/arm/cpu_tcg.c
59
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
60
cpu->isar.id_pfr2 = t;
61
62
t = cpu->isar.id_dfr0;
63
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
64
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
65
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
66
cpu->isar.id_dfr0 = t;
67
}
55
--
68
--
56
2.20.1
69
2.25.1
57
58
diff view generated by jsdifflib
[PULL 15/39] target/arm: Update CNTP for PREDDESC
[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since b64ee454a4a0, all predicate operations should be
3
This extension concerns changes to the External Debug interface,
4
using these field macros for predicates.
4
with Secure and Non-secure access to the debug registers, and all
5
of it is outside the scope of QEMU. Indicating support for this
6
is mandatory with FEAT_SEL2, which we do implement.
5
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210309155305.11301-7-richard.henderson@linaro.org
10
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/sve_helper.c | 6 +++---
13
docs/system/arm/emulation.rst | 1 +
12
target/arm/translate-sve.c | 6 +++---
14
target/arm/cpu64.c | 2 +-
13
2 files changed, 6 insertions(+), 6 deletions(-)
15
target/arm/cpu_tcg.c | 4 ++--
16
3 files changed, 4 insertions(+), 3 deletions(-)
14
17
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
20
--- a/docs/system/arm/emulation.rst
18
+++ b/target/arm/sve_helper.c
21
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
23
- FEAT_DIT (Data Independent Timing instructions)
21
uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
24
- FEAT_DPB (DC CVAP instruction)
22
{
25
- FEAT_Debugv8p2 (Debug changes for v8.2)
23
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
26
+- FEAT_Debugv8p4 (Debug changes for v8.4)
24
- intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
27
- FEAT_DotProd (Advanced SIMD dot product instructions)
25
+ intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8);
28
- FEAT_FCMA (Floating-point complex number instructions)
26
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
29
- FEAT_FHM (Floating-point half-precision multiplication instructions)
27
uint64_t *n = vn, *g = vg, sum = 0, mask = pred_esz_masks[esz];
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
intptr_t i;
29
30
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
31
+ for (i = 0; i < words; ++i) {
32
uint64_t t = n[i] & g[i] & mask;
33
sum += ctpop64(t);
34
}
35
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
36
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/translate-sve.c
32
--- a/target/arm/cpu64.c
38
+++ b/target/arm/translate-sve.c
33
+++ b/target/arm/cpu64.c
39
@@ -XXX,XX +XXX,XX @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
} else {
35
cpu->isar.id_aa64zfr0 = t;
41
TCGv_ptr t_pn = tcg_temp_new_ptr();
36
42
TCGv_ptr t_pg = tcg_temp_new_ptr();
37
t = cpu->isar.id_aa64dfr0;
43
- unsigned desc;
38
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
44
+ unsigned desc = 0;
39
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
45
TCGv_i32 t_desc;
40
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
46
41
cpu->isar.id_aa64dfr0 = t;
47
- desc = psz - 2;
42
48
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
43
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
49
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
44
index XXXXXXX..XXXXXXX 100644
50
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
45
--- a/target/arm/cpu_tcg.c
51
46
+++ b/target/arm/cpu_tcg.c
52
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
47
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
53
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
48
cpu->isar.id_pfr2 = t;
49
50
t = cpu->isar.id_dfr0;
51
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
52
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
53
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
54
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
55
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
56
cpu->isar.id_dfr0 = t;
57
}
54
--
58
--
55
2.20.1
59
2.25.1
56
57
diff view generated by jsdifflib
[PULL 01/39] hw/misc: versal: Add a model of the XRAM controller
[PULL 14/32] target/arm: Add minimal RAS registers
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
3
Add only the system registers required to implement zero error
4
This is mainly a stub to make firmware happy. The size of
4
records. This means that all values for ERRSELR are out of range,
5
the RAMs can be probed. The interrupt mask logic is
5
which means that it and all of the indexed error record registers
6
modelled but none of the interrups will ever be raised
6
need not be implemented.
7
unless injected.
8
7
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Add the EL2 registers required for injecting virtual SError.
10
Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com
9
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
include/hw/misc/xlnx-versal-xramc.h | 97 +++++++++++
15
target/arm/cpu.h | 5 +++
15
hw/misc/xlnx-versal-xramc.c | 253 ++++++++++++++++++++++++++++
16
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
16
hw/misc/meson.build | 1 +
17
2 files changed, 89 insertions(+)
17
3 files changed, 351 insertions(+)
18
create mode 100644 include/hw/misc/xlnx-versal-xramc.h
19
create mode 100644 hw/misc/xlnx-versal-xramc.c
20
18
21
diff --git a/include/hw/misc/xlnx-versal-xramc.h b/include/hw/misc/xlnx-versal-xramc.h
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
new file mode 100644
20
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX
21
--- a/target/arm/cpu.h
24
--- /dev/null
22
+++ b/target/arm/cpu.h
25
+++ b/include/hw/misc/xlnx-versal-xramc.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
26
@@ -XXX,XX +XXX,XX @@
24
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
25
uint64_t gcr_el1;
26
uint64_t rgsr_el1;
27
+
28
+ /* Minimal RAS registers */
29
+ uint64_t disr_el1;
30
+ uint64_t vdisr_el2;
31
+ uint64_t vsesr_el2;
32
} cp15;
33
34
struct {
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
40
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
41
};
42
27
+/*
43
+/*
28
+ * QEMU model of the Xilinx XRAM Controller.
44
+ * Check for traps to RAS registers, which are controlled
29
+ *
45
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
30
+ * Copyright (c) 2021 Xilinx Inc.
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
32
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
33
+ */
46
+ */
47
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
48
+ bool isread)
49
+{
50
+ int el = arm_current_el(env);
34
+
51
+
35
+#ifndef XLNX_VERSAL_XRAMC_H
52
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
36
+#define XLNX_VERSAL_XRAMC_H
53
+ return CP_ACCESS_TRAP_EL2;
37
+
54
+ }
38
+#include "hw/sysbus.h"
55
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
39
+#include "hw/register.h"
56
+ return CP_ACCESS_TRAP_EL3;
40
+
57
+ }
41
+#define TYPE_XLNX_XRAM_CTRL "xlnx.versal-xramc"
58
+ return CP_ACCESS_OK;
42
+
43
+#define XLNX_XRAM_CTRL(obj) \
44
+ OBJECT_CHECK(XlnxXramCtrl, (obj), TYPE_XLNX_XRAM_CTRL)
45
+
46
+REG32(XRAM_ERR_CTRL, 0x0)
47
+ FIELD(XRAM_ERR_CTRL, UE_RES, 3, 1)
48
+ FIELD(XRAM_ERR_CTRL, PWR_ERR_RES, 2, 1)
49
+ FIELD(XRAM_ERR_CTRL, PZ_ERR_RES, 1, 1)
50
+ FIELD(XRAM_ERR_CTRL, APB_ERR_RES, 0, 1)
51
+REG32(XRAM_ISR, 0x4)
52
+ FIELD(XRAM_ISR, INV_APB, 0, 1)
53
+REG32(XRAM_IMR, 0x8)
54
+ FIELD(XRAM_IMR, INV_APB, 0, 1)
55
+REG32(XRAM_IEN, 0xc)
56
+ FIELD(XRAM_IEN, INV_APB, 0, 1)
57
+REG32(XRAM_IDS, 0x10)
58
+ FIELD(XRAM_IDS, INV_APB, 0, 1)
59
+REG32(XRAM_ECC_CNTL, 0x14)
60
+ FIELD(XRAM_ECC_CNTL, FI_MODE, 2, 1)
61
+ FIELD(XRAM_ECC_CNTL, DET_ONLY, 1, 1)
62
+ FIELD(XRAM_ECC_CNTL, ECC_ON_OFF, 0, 1)
63
+REG32(XRAM_CLR_EXE, 0x18)
64
+ FIELD(XRAM_CLR_EXE, MON_7, 7, 1)
65
+ FIELD(XRAM_CLR_EXE, MON_6, 6, 1)
66
+ FIELD(XRAM_CLR_EXE, MON_5, 5, 1)
67
+ FIELD(XRAM_CLR_EXE, MON_4, 4, 1)
68
+ FIELD(XRAM_CLR_EXE, MON_3, 3, 1)
69
+ FIELD(XRAM_CLR_EXE, MON_2, 2, 1)
70
+ FIELD(XRAM_CLR_EXE, MON_1, 1, 1)
71
+ FIELD(XRAM_CLR_EXE, MON_0, 0, 1)
72
+REG32(XRAM_CE_FFA, 0x1c)
73
+ FIELD(XRAM_CE_FFA, ADDR, 0, 20)
74
+REG32(XRAM_CE_FFD0, 0x20)
75
+REG32(XRAM_CE_FFD1, 0x24)
76
+REG32(XRAM_CE_FFD2, 0x28)
77
+REG32(XRAM_CE_FFD3, 0x2c)
78
+REG32(XRAM_CE_FFE, 0x30)
79
+ FIELD(XRAM_CE_FFE, SYNDROME, 0, 16)
80
+REG32(XRAM_UE_FFA, 0x34)
81
+ FIELD(XRAM_UE_FFA, ADDR, 0, 20)
82
+REG32(XRAM_UE_FFD0, 0x38)
83
+REG32(XRAM_UE_FFD1, 0x3c)
84
+REG32(XRAM_UE_FFD2, 0x40)
85
+REG32(XRAM_UE_FFD3, 0x44)
86
+REG32(XRAM_UE_FFE, 0x48)
87
+ FIELD(XRAM_UE_FFE, SYNDROME, 0, 16)
88
+REG32(XRAM_FI_D0, 0x4c)
89
+REG32(XRAM_FI_D1, 0x50)
90
+REG32(XRAM_FI_D2, 0x54)
91
+REG32(XRAM_FI_D3, 0x58)
92
+REG32(XRAM_FI_SY, 0x5c)
93
+ FIELD(XRAM_FI_SY, DATA, 0, 16)
94
+REG32(XRAM_RMW_UE_FFA, 0x70)
95
+ FIELD(XRAM_RMW_UE_FFA, ADDR, 0, 20)
96
+REG32(XRAM_FI_CNTR, 0x74)
97
+ FIELD(XRAM_FI_CNTR, COUNT, 0, 24)
98
+REG32(XRAM_IMP, 0x80)
99
+ FIELD(XRAM_IMP, SIZE, 0, 4)
100
+REG32(XRAM_PRDY_DBG, 0x84)
101
+ FIELD(XRAM_PRDY_DBG, ISLAND3, 12, 4)
102
+ FIELD(XRAM_PRDY_DBG, ISLAND2, 8, 4)
103
+ FIELD(XRAM_PRDY_DBG, ISLAND1, 4, 4)
104
+ FIELD(XRAM_PRDY_DBG, ISLAND0, 0, 4)
105
+REG32(XRAM_SAFETY_CHK, 0xff8)
106
+
107
+#define XRAM_CTRL_R_MAX (R_XRAM_SAFETY_CHK + 1)
108
+
109
+typedef struct XlnxXramCtrl {
110
+ SysBusDevice parent_obj;
111
+ MemoryRegion ram;
112
+ qemu_irq irq;
113
+
114
+ struct {
115
+ uint64_t size;
116
+ unsigned int encoded_size;
117
+ } cfg;
118
+
119
+ RegisterInfoArray *reg_array;
120
+ uint32_t regs[XRAM_CTRL_R_MAX];
121
+ RegisterInfo regs_info[XRAM_CTRL_R_MAX];
122
+} XlnxXramCtrl;
123
+#endif
124
diff --git a/hw/misc/xlnx-versal-xramc.c b/hw/misc/xlnx-versal-xramc.c
125
new file mode 100644
126
index XXXXXXX..XXXXXXX
127
--- /dev/null
128
+++ b/hw/misc/xlnx-versal-xramc.c
129
@@ -XXX,XX +XXX,XX @@
130
+/*
131
+ * QEMU model of the Xilinx XRAM Controller.
132
+ *
133
+ * Copyright (c) 2021 Xilinx Inc.
134
+ * SPDX-License-Identifier: GPL-2.0-or-later
135
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
136
+ */
137
+
138
+#include "qemu/osdep.h"
139
+#include "qemu/units.h"
140
+#include "qapi/error.h"
141
+#include "migration/vmstate.h"
142
+#include "hw/sysbus.h"
143
+#include "hw/register.h"
144
+#include "hw/qdev-properties.h"
145
+#include "hw/irq.h"
146
+#include "hw/misc/xlnx-versal-xramc.h"
147
+
148
+#ifndef XLNX_XRAM_CTRL_ERR_DEBUG
149
+#define XLNX_XRAM_CTRL_ERR_DEBUG 0
150
+#endif
151
+
152
+static void xram_update_irq(XlnxXramCtrl *s)
153
+{
154
+ bool pending = s->regs[R_XRAM_ISR] & ~s->regs[R_XRAM_IMR];
155
+ qemu_set_irq(s->irq, pending);
156
+}
59
+}
157
+
60
+
158
+static void xram_isr_postw(RegisterInfo *reg, uint64_t val64)
61
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
159
+{
62
+{
160
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
63
+ int el = arm_current_el(env);
161
+ xram_update_irq(s);
64
+
65
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
66
+ return env->cp15.vdisr_el2;
67
+ }
68
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
69
+ return 0; /* RAZ/WI */
70
+ }
71
+ return env->cp15.disr_el1;
162
+}
72
+}
163
+
73
+
164
+static uint64_t xram_ien_prew(RegisterInfo *reg, uint64_t val64)
74
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
165
+{
75
+{
166
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
76
+ int el = arm_current_el(env);
167
+ uint32_t val = val64;
168
+
77
+
169
+ s->regs[R_XRAM_IMR] &= ~val;
78
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
170
+ xram_update_irq(s);
79
+ env->cp15.vdisr_el2 = val;
171
+ return 0;
80
+ return;
81
+ }
82
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
83
+ return; /* RAZ/WI */
84
+ }
85
+ env->cp15.disr_el1 = val;
172
+}
86
+}
173
+
87
+
174
+static uint64_t xram_ids_prew(RegisterInfo *reg, uint64_t val64)
88
+/*
175
+{
89
+ * Minimal RAS implementation with no Error Records.
176
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
90
+ * Which means that all of the Error Record registers:
177
+ uint32_t val = val64;
91
+ * ERXADDR_EL1
178
+
92
+ * ERXCTLR_EL1
179
+ s->regs[R_XRAM_IMR] |= val;
93
+ * ERXFR_EL1
180
+ xram_update_irq(s);
94
+ * ERXMISC0_EL1
181
+ return 0;
95
+ * ERXMISC1_EL1
182
+}
96
+ * ERXMISC2_EL1
183
+
97
+ * ERXMISC3_EL1
184
+static const RegisterAccessInfo xram_ctrl_regs_info[] = {
98
+ * ERXPFGCDN_EL1 (RASv1p1)
185
+ { .name = "XRAM_ERR_CTRL", .addr = A_XRAM_ERR_CTRL,
99
+ * ERXPFGCTL_EL1 (RASv1p1)
186
+ .reset = 0xf,
100
+ * ERXPFGF_EL1 (RASv1p1)
187
+ .rsvd = 0xfffffff0,
101
+ * ERXSTATUS_EL1
188
+ },{ .name = "XRAM_ISR", .addr = A_XRAM_ISR,
102
+ * and
189
+ .rsvd = 0xfffff800,
103
+ * ERRSELR_EL1
190
+ .w1c = 0x7ff,
104
+ * may generate UNDEFINED, which is the effect we get by not
191
+ .post_write = xram_isr_postw,
105
+ * listing them at all.
192
+ },{ .name = "XRAM_IMR", .addr = A_XRAM_IMR,
106
+ */
193
+ .reset = 0x7ff,
107
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
194
+ .rsvd = 0xfffff800,
108
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
195
+ .ro = 0x7ff,
109
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
196
+ },{ .name = "XRAM_IEN", .addr = A_XRAM_IEN,
110
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
197
+ .rsvd = 0xfffff800,
111
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
198
+ .pre_write = xram_ien_prew,
112
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
199
+ },{ .name = "XRAM_IDS", .addr = A_XRAM_IDS,
113
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
200
+ .rsvd = 0xfffff800,
114
+ .access = PL1_R, .accessfn = access_terr,
201
+ .pre_write = xram_ids_prew,
115
+ .type = ARM_CP_CONST, .resetvalue = 0 },
202
+ },{ .name = "XRAM_ECC_CNTL", .addr = A_XRAM_ECC_CNTL,
116
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
203
+ .rsvd = 0xfffffff8,
117
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
204
+ },{ .name = "XRAM_CLR_EXE", .addr = A_XRAM_CLR_EXE,
118
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
205
+ .rsvd = 0xffffff00,
119
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
206
+ },{ .name = "XRAM_CE_FFA", .addr = A_XRAM_CE_FFA,
120
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
207
+ .rsvd = 0xfff00000,
121
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
208
+ .ro = 0xfffff,
209
+ },{ .name = "XRAM_CE_FFD0", .addr = A_XRAM_CE_FFD0,
210
+ .ro = 0xffffffff,
211
+ },{ .name = "XRAM_CE_FFD1", .addr = A_XRAM_CE_FFD1,
212
+ .ro = 0xffffffff,
213
+ },{ .name = "XRAM_CE_FFD2", .addr = A_XRAM_CE_FFD2,
214
+ .ro = 0xffffffff,
215
+ },{ .name = "XRAM_CE_FFD3", .addr = A_XRAM_CE_FFD3,
216
+ .ro = 0xffffffff,
217
+ },{ .name = "XRAM_CE_FFE", .addr = A_XRAM_CE_FFE,
218
+ .rsvd = 0xffff0000,
219
+ .ro = 0xffff,
220
+ },{ .name = "XRAM_UE_FFA", .addr = A_XRAM_UE_FFA,
221
+ .rsvd = 0xfff00000,
222
+ .ro = 0xfffff,
223
+ },{ .name = "XRAM_UE_FFD0", .addr = A_XRAM_UE_FFD0,
224
+ .ro = 0xffffffff,
225
+ },{ .name = "XRAM_UE_FFD1", .addr = A_XRAM_UE_FFD1,
226
+ .ro = 0xffffffff,
227
+ },{ .name = "XRAM_UE_FFD2", .addr = A_XRAM_UE_FFD2,
228
+ .ro = 0xffffffff,
229
+ },{ .name = "XRAM_UE_FFD3", .addr = A_XRAM_UE_FFD3,
230
+ .ro = 0xffffffff,
231
+ },{ .name = "XRAM_UE_FFE", .addr = A_XRAM_UE_FFE,
232
+ .rsvd = 0xffff0000,
233
+ .ro = 0xffff,
234
+ },{ .name = "XRAM_FI_D0", .addr = A_XRAM_FI_D0,
235
+ },{ .name = "XRAM_FI_D1", .addr = A_XRAM_FI_D1,
236
+ },{ .name = "XRAM_FI_D2", .addr = A_XRAM_FI_D2,
237
+ },{ .name = "XRAM_FI_D3", .addr = A_XRAM_FI_D3,
238
+ },{ .name = "XRAM_FI_SY", .addr = A_XRAM_FI_SY,
239
+ .rsvd = 0xffff0000,
240
+ },{ .name = "XRAM_RMW_UE_FFA", .addr = A_XRAM_RMW_UE_FFA,
241
+ .rsvd = 0xfff00000,
242
+ .ro = 0xfffff,
243
+ },{ .name = "XRAM_FI_CNTR", .addr = A_XRAM_FI_CNTR,
244
+ .rsvd = 0xff000000,
245
+ },{ .name = "XRAM_IMP", .addr = A_XRAM_IMP,
246
+ .reset = 0x4,
247
+ .rsvd = 0xfffffff0,
248
+ .ro = 0xf,
249
+ },{ .name = "XRAM_PRDY_DBG", .addr = A_XRAM_PRDY_DBG,
250
+ .reset = 0xffff,
251
+ .rsvd = 0xffff0000,
252
+ .ro = 0xffff,
253
+ },{ .name = "XRAM_SAFETY_CHK", .addr = A_XRAM_SAFETY_CHK,
254
+ }
255
+};
122
+};
256
+
123
+
257
+static void xram_ctrl_reset_enter(Object *obj, ResetType type)
124
/* Return the exception level to which exceptions should be taken
258
+{
125
* via SVEAccessTrap. If an exception should be routed through
259
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
126
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
260
+ unsigned int i;
127
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
261
+
128
if (cpu_isar_feature(aa64_ssbs, cpu)) {
262
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
129
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
263
+ register_reset(&s->regs_info[i]);
130
}
131
+ if (cpu_isar_feature(any_ras, cpu)) {
132
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
264
+ }
133
+ }
265
+
134
266
+ ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size);
135
if (cpu_isar_feature(aa64_vh, cpu) ||
267
+}
136
cpu_isar_feature(aa64_debugv8p2, cpu)) {
268
+
269
+static void xram_ctrl_reset_hold(Object *obj)
270
+{
271
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
272
+
273
+ xram_update_irq(s);
274
+}
275
+
276
+static const MemoryRegionOps xram_ctrl_ops = {
277
+ .read = register_read_memory,
278
+ .write = register_write_memory,
279
+ .endianness = DEVICE_LITTLE_ENDIAN,
280
+ .valid = {
281
+ .min_access_size = 4,
282
+ .max_access_size = 4,
283
+ },
284
+};
285
+
286
+static void xram_ctrl_realize(DeviceState *dev, Error **errp)
287
+{
288
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
289
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(dev);
290
+
291
+ switch (s->cfg.size) {
292
+ case 64 * KiB:
293
+ s->cfg.encoded_size = 0;
294
+ break;
295
+ case 128 * KiB:
296
+ s->cfg.encoded_size = 1;
297
+ break;
298
+ case 256 * KiB:
299
+ s->cfg.encoded_size = 2;
300
+ break;
301
+ case 512 * KiB:
302
+ s->cfg.encoded_size = 3;
303
+ break;
304
+ case 1 * MiB:
305
+ s->cfg.encoded_size = 4;
306
+ break;
307
+ default:
308
+ error_setg(errp, "Unsupported XRAM size %" PRId64, s->cfg.size);
309
+ return;
310
+ }
311
+
312
+ memory_region_init_ram(&s->ram, OBJECT(s),
313
+ object_get_canonical_path_component(OBJECT(s)),
314
+ s->cfg.size, &error_fatal);
315
+ sysbus_init_mmio(sbd, &s->ram);
316
+}
317
+
318
+static void xram_ctrl_init(Object *obj)
319
+{
320
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
321
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
322
+
323
+ s->reg_array =
324
+ register_init_block32(DEVICE(obj), xram_ctrl_regs_info,
325
+ ARRAY_SIZE(xram_ctrl_regs_info),
326
+ s->regs_info, s->regs,
327
+ &xram_ctrl_ops,
328
+ XLNX_XRAM_CTRL_ERR_DEBUG,
329
+ XRAM_CTRL_R_MAX * 4);
330
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
331
+ sysbus_init_irq(sbd, &s->irq);
332
+}
333
+
334
+static void xram_ctrl_finalize(Object *obj)
335
+{
336
+ XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
337
+ register_finalize_block(s->reg_array);
338
+}
339
+
340
+static const VMStateDescription vmstate_xram_ctrl = {
341
+ .name = TYPE_XLNX_XRAM_CTRL,
342
+ .version_id = 1,
343
+ .minimum_version_id = 1,
344
+ .fields = (VMStateField[]) {
345
+ VMSTATE_UINT32_ARRAY(regs, XlnxXramCtrl, XRAM_CTRL_R_MAX),
346
+ VMSTATE_END_OF_LIST(),
347
+ }
348
+};
349
+
350
+static Property xram_ctrl_properties[] = {
351
+ DEFINE_PROP_UINT64("size", XlnxXramCtrl, cfg.size, 1 * MiB),
352
+ DEFINE_PROP_END_OF_LIST(),
353
+};
354
+
355
+static void xram_ctrl_class_init(ObjectClass *klass, void *data)
356
+{
357
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
358
+ DeviceClass *dc = DEVICE_CLASS(klass);
359
+
360
+ dc->realize = xram_ctrl_realize;
361
+ dc->vmsd = &vmstate_xram_ctrl;
362
+ device_class_set_props(dc, xram_ctrl_properties);
363
+
364
+ rc->phases.enter = xram_ctrl_reset_enter;
365
+ rc->phases.hold = xram_ctrl_reset_hold;
366
+}
367
+
368
+static const TypeInfo xram_ctrl_info = {
369
+ .name = TYPE_XLNX_XRAM_CTRL,
370
+ .parent = TYPE_SYS_BUS_DEVICE,
371
+ .instance_size = sizeof(XlnxXramCtrl),
372
+ .class_init = xram_ctrl_class_init,
373
+ .instance_init = xram_ctrl_init,
374
+ .instance_finalize = xram_ctrl_finalize,
375
+};
376
+
377
+static void xram_ctrl_register_types(void)
378
+{
379
+ type_register_static(&xram_ctrl_info);
380
+}
381
+
382
+type_init(xram_ctrl_register_types)
383
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
384
index XXXXXXX..XXXXXXX 100644
385
--- a/hw/misc/meson.build
386
+++ b/hw/misc/meson.build
387
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
388
))
389
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
390
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
391
+softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c'))
392
softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
393
softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
394
softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
395
--
137
--
396
2.20.1
138
2.25.1
397
398
diff view generated by jsdifflib
[PULL 23/39] hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
If the SSECounter link is absent, we set an error message
3
Enable writes to the TERR and TEA bits when RAS is enabled.
4
in sse_timer_realize() but forgot to propagate this error.
4
These bits are otherwise RES0.
5
Add the missing 'return'.
6
5
7
Fixes: CID 1450755 (Null pointer dereferences)
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210312001845.1562670-1-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
hw/timer/sse-timer.c | 1 +
11
target/arm/helper.c | 9 +++++++++
14
1 file changed, 1 insertion(+)
12
1 file changed, 9 insertions(+)
15
13
16
diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/sse-timer.c
16
--- a/target/arm/helper.c
19
+++ b/hw/timer/sse-timer.c
17
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static void sse_timer_realize(DeviceState *dev, Error **errp)
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
21
19
}
22
if (!s->counter) {
20
valid_mask &= ~SCR_NET;
23
error_setg(errp, "counter property was not set");
21
24
+ return;
22
+ if (cpu_isar_feature(aa64_ras, cpu)) {
23
+ valid_mask |= SCR_TERR;
24
+ }
25
if (cpu_isar_feature(aa64_lor, cpu)) {
26
valid_mask |= SCR_TLOR;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
29
}
30
} else {
31
valid_mask &= ~(SCR_RW | SCR_ST);
32
+ if (cpu_isar_feature(aa32_ras, cpu)) {
33
+ valid_mask |= SCR_TERR;
34
+ }
25
}
35
}
26
36
27
s->counter_notifier.notify = sse_timer_counter_callback;
37
if (!arm_feature(env, ARM_FEATURE_EL2)) {
38
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
39
if (cpu_isar_feature(aa64_vh, cpu)) {
40
valid_mask |= HCR_E2H;
41
}
42
+ if (cpu_isar_feature(aa64_ras, cpu)) {
43
+ valid_mask |= HCR_TERR | HCR_TEA;
44
+ }
45
if (cpu_isar_feature(aa64_lor, cpu)) {
46
valid_mask |= HCR_TLOR;
47
}
28
--
48
--
29
2.20.1
49
2.25.1
30
31
diff view generated by jsdifflib
[PULL 29/39] hw/arm: Connect PWM fans in NPCM7XX boards
[PULL 16/32] target/arm: Implement virtual SError exceptions
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds fan_splitters (split IRQs) in NPCM7XX boards. Each fan
3
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
4
splitter corresponds to 1 PWM output and can connect to multiple fan
4
and are routed to EL1 just like other virtual exceptions.
5
inputs (MFT devices).
6
In NPCM7XX boards(NPCM750 EVB and Quanta GSJ boards), we initializes
7
these splitters and connect them to their corresponding modules
8
according their specific device trees.
9
5
10
Reviewed-by: Doug Evans <dje@google.com>
11
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
12
Signed-off-by: Hao Wu <wuhaotsh@google.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210311180855.149764-5-wuhaotsh@google.com
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
include/hw/arm/npcm7xx.h | 11 ++++-
11
target/arm/cpu.h | 2 ++
18
hw/arm/npcm7xx_boards.c | 99 ++++++++++++++++++++++++++++++++++++++++
12
target/arm/internals.h | 8 ++++++++
19
2 files changed, 109 insertions(+), 1 deletion(-)
13
target/arm/syndrome.h | 5 +++++
14
target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
15
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
16
5 files changed, 91 insertions(+), 2 deletions(-)
20
17
21
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/npcm7xx.h
20
--- a/target/arm/cpu.h
24
+++ b/include/hw/arm/npcm7xx.h
21
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@
26
23
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
27
#include "hw/boards.h"
24
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
28
#include "hw/adc/npcm7xx_adc.h"
25
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
29
+#include "hw/core/split-irq.h"
26
+#define EXCP_VSERR 24
30
#include "hw/cpu/a9mpcore.h"
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
31
#include "hw/gpio/npcm7xx_gpio.h"
28
32
#include "hw/i2c/npcm7xx_smbus.h"
29
#define ARMV7M_EXCP_RESET 1
33
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@ enum {
34
#define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
35
#define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
32
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
36
33
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
37
+#define NPCM7XX_NR_PWM_MODULES 2
34
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
38
+
35
39
typedef struct NPCM7xxMachine {
36
/* The usual mapping for an AArch64 system register to its AArch32
40
MachineState parent;
37
* counterpart is for the 32 bit world to have access to the lower
38
diff --git a/target/arm/internals.h b/target/arm/internals.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/internals.h
41
+++ b/target/arm/internals.h
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
43
*/
44
void arm_cpu_update_vfiq(ARMCPU *cpu);
45
46
+/**
47
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
48
+ *
49
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
50
+ * following a change to the HCR_EL2.VSE bit.
51
+ */
52
+void arm_cpu_update_vserr(ARMCPU *cpu);
53
+
54
/**
55
* arm_mmu_idx_el:
56
* @env: The cpu environment
57
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/syndrome.h
60
+++ b/target/arm/syndrome.h
61
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
62
return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
63
}
64
65
+static inline uint32_t syn_serror(uint32_t extra)
66
+{
67
+ return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
68
+}
69
+
70
#endif /* TARGET_ARM_SYNDROME_H */
71
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/cpu.c
74
+++ b/target/arm/cpu.c
75
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
76
return (cpu->power_state != PSCI_OFF)
77
&& cs->interrupt_request &
78
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
79
- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
80
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
81
| CPU_INTERRUPT_EXITTB);
82
}
83
84
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
85
return false;
86
}
87
return !(env->daif & PSTATE_I);
88
+ case EXCP_VSERR:
89
+ if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
90
+ /* VIRQs are only taken when hypervized. */
91
+ return false;
92
+ }
93
+ return !(env->daif & PSTATE_A);
94
default:
95
g_assert_not_reached();
96
}
97
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
98
goto found;
99
}
100
}
101
+ if (interrupt_request & CPU_INTERRUPT_VSERR) {
102
+ excp_idx = EXCP_VSERR;
103
+ target_el = 1;
104
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
105
+ cur_el, secure, hcr_el2)) {
106
+ /* Taking a virtual abort clears HCR_EL2.VSE */
107
+ env->cp15.hcr_el2 &= ~HCR_VSE;
108
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
109
+ goto found;
110
+ }
111
+ }
112
return false;
113
114
found:
115
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
116
}
117
}
118
119
+void arm_cpu_update_vserr(ARMCPU *cpu)
120
+{
41
+ /*
121
+ /*
42
+ * PWM fan splitter. each splitter connects to one PWM output and
122
+ * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
43
+ * multiple MFT inputs.
44
+ */
123
+ */
45
+ SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
124
+ CPUARMState *env = &cpu->env;
46
+ NPCM7XX_PWM_PER_MODULE];
125
+ CPUState *cs = CPU(cpu);
47
} NPCM7xxMachine;
126
+
48
127
+ bool new_state = env->cp15.hcr_el2 & HCR_VSE;
49
#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
128
+
50
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
129
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
51
NPCM7xxCLKState clk;
130
+ if (new_state) {
52
NPCM7xxTimerCtrlState tim[3];
131
+ cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
53
NPCM7xxADCState adc;
132
+ } else {
54
- NPCM7xxPWMState pwm[2];
133
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
55
+ NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];
56
NPCM7xxMFTState mft[8];
57
NPCM7xxOTPState key_storage;
58
NPCM7xxOTPState fuse_array;
59
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/npcm7xx_boards.c
62
+++ b/hw/arm/npcm7xx_boards.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "hw/core/cpu.h"
65
#include "hw/i2c/smbus_eeprom.h"
66
#include "hw/loader.h"
67
+#include "hw/qdev-core.h"
68
#include "hw/qdev-properties.h"
69
#include "qapi/error.h"
70
#include "qemu-common.h"
71
@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
72
i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
73
}
74
75
+static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
76
+ NPCM7xxState *soc, const int *fan_counts)
77
+{
78
+ SplitIRQ *splitters = machine->fan_splitter;
79
+
80
+ /*
81
+ * PWM 0~3 belong to module 0 output 0~3.
82
+ * PWM 4~7 belong to module 1 output 0~3.
83
+ */
84
+ for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
85
+ for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
86
+ int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
87
+ DeviceState *splitter;
88
+
89
+ if (fan_counts[splitter_no] < 1) {
90
+ continue;
91
+ }
92
+ object_initialize_child(OBJECT(machine), "fan-splitter[*]",
93
+ &splitters[splitter_no], TYPE_SPLIT_IRQ);
94
+ splitter = DEVICE(&splitters[splitter_no]);
95
+ qdev_prop_set_uint16(splitter, "num-lines",
96
+ fan_counts[splitter_no]);
97
+ qdev_realize(splitter, NULL, &error_abort);
98
+ qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
99
+ j, qdev_get_gpio_in(splitter, 0));
100
+ }
134
+ }
101
+ }
135
+ }
102
+}
136
+}
103
+
137
+
104
+static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,
138
#ifndef CONFIG_USER_ONLY
105
+ int fan_no, int output_no)
139
static void arm_cpu_set_irq(void *opaque, int irq, int level)
106
+{
140
{
107
+ DeviceState *fan;
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
108
+ int fan_input;
142
index XXXXXXX..XXXXXXX 100644
109
+ qemu_irq fan_duty_gpio;
143
--- a/target/arm/helper.c
110
+
144
+++ b/target/arm/helper.c
111
+ g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
145
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
112
+ /*
146
}
113
+ * Fan 0~1 belong to module 0 input 0~1.
147
}
114
+ * Fan 2~3 belong to module 1 input 0~1.
148
115
+ * ...
149
- /* External aborts are not possible in QEMU so A bit is always clear */
116
+ * Fan 14~15 belong to module 7 input 0~1.
150
+ if (hcr_el2 & HCR_AMO) {
117
+ * Fan 16~17 belong to module 0 input 2~3.
151
+ if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
118
+ * Fan 18~19 belong to module 1 input 2~3.
152
+ ret |= CPSR_A;
119
+ */
153
+ }
120
+ if (fan_no < 16) {
121
+ fan = DEVICE(&soc->mft[fan_no / 2]);
122
+ fan_input = fan_no % 2;
123
+ } else {
124
+ fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
125
+ fan_input = fan_no % 2 + 2;
126
+ }
154
+ }
127
+
155
+
128
+ /* Connect the Fan to PWM module */
156
return ret;
129
+ fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
157
}
130
+ qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
158
131
+}
159
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
132
+
160
g_assert(qemu_mutex_iothread_locked());
133
static void npcm750_evb_i2c_init(NPCM7xxState *soc)
161
arm_cpu_update_virq(cpu);
134
{
162
arm_cpu_update_vfiq(cpu);
135
/* lm75 temperature sensor on SVB, tmp105 is compatible */
163
+ arm_cpu_update_vserr(cpu);
136
@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc)
164
}
137
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
165
138
}
166
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
139
167
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
140
+static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
168
[EXCP_LSERR] = "v8M LSERR UsageFault",
141
+{
169
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
142
+ SplitIRQ *splitter = machine->fan_splitter;
170
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
143
+ static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};
171
+ [EXCP_VSERR] = "Virtual SERR",
144
+
172
};
145
+ npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
173
146
+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
174
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
147
+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
175
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
148
+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
176
mask = CPSR_A | CPSR_I | CPSR_F;
149
+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
177
offset = 4;
150
+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
178
break;
151
+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
179
+ case EXCP_VSERR:
152
+ npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
180
+ {
153
+ npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
181
+ /*
154
+ npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
182
+ * Note that this is reported as a data abort, but the DFAR
155
+ npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
183
+ * has an UNKNOWN value. Construct the SError syndrome from
156
+ npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
184
+ * AET and ExT fields.
157
+ npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
185
+ */
158
+ npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
186
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
159
+ npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
187
+
160
+ npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
188
+ if (extended_addresses_enabled(env)) {
161
+ npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
189
+ env->exception.fsr = arm_fi_to_lfsc(&fi);
162
+}
190
+ } else {
163
+
191
+ env->exception.fsr = arm_fi_to_sfsc(&fi);
164
static void quanta_gsj_i2c_init(NPCM7xxState *soc)
192
+ }
165
{
193
+ env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
166
/* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
194
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
167
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
195
+ qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
168
/* TODO: Add additional i2c devices. */
196
+ env->exception.fsr);
169
}
197
+
170
198
+ new_mode = ARM_CPU_MODE_ABT;
171
+static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
199
+ addr = 0x10;
172
+{
200
+ mask = CPSR_A | CPSR_I;
173
+ SplitIRQ *splitter = machine->fan_splitter;
201
+ offset = 8;
174
+ static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};
202
+ }
175
+
203
+ break;
176
+ npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
204
case EXCP_SMC:
177
+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
205
new_mode = ARM_CPU_MODE_MON;
178
+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
206
addr = 0x08;
179
+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
207
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
180
+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
208
case EXCP_VFIQ:
181
+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
209
addr += 0x100;
182
+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
210
break;
183
+}
211
+ case EXCP_VSERR:
184
+
212
+ addr += 0x180;
185
static void npcm750_evb_init(MachineState *machine)
213
+ /* Construct the SError syndrome from IDS and ISS fields. */
186
{
214
+ env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
187
NPCM7xxState *soc;
215
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
188
@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_init(MachineState *machine)
216
+ break;
189
npcm7xx_load_bootrom(machine, soc);
217
default:
190
npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
218
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
191
npcm750_evb_i2c_init(soc);
219
}
192
+ npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
193
npcm7xx_load_kernel(machine, soc);
194
}
195
196
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_init(MachineState *machine)
197
npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
198
drive_get(IF_MTD, 0, 0));
199
quanta_gsj_i2c_init(soc);
200
+ quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
201
npcm7xx_load_kernel(machine, soc);
202
}
203
204
--
220
--
205
2.20.1
221
2.25.1
206
207
diff view generated by jsdifflib
[PULL 27/39] hw/misc: Add NPCM7XX MFT Module
[PULL 17/32] target/arm: Implement ESB instruction
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch implements Multi Function Timer (MFT) module for NPCM7XX.
3
Check for and defer any pending virtual SError.
4
This module is mainly used to configure PWM fans. It has just enough
5
functionality to make the PWM fan kernel module work.
6
4
7
The module takes two input, the max_rpm of a fan (modifiable via QMP)
8
and duty cycle (a GPIO from the PWM module.) The actual measured RPM
9
is equal to max_rpm * duty_cycle / NPCM7XX_PWM_MAX_DUTY. The RPM is
10
measured as a counter compared to a prescaled input clock. The kernel
11
driver reads this counter and report to user space.
12
13
Refs:
14
https://github.com/torvalds/linux/blob/master/drivers/hwmon/npcm750-pwm-fan.c
15
16
Reviewed-by: Doug Evans <dje@google.com>
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
19
Message-id: 20210311180855.149764-3-wuhaotsh@google.com
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
9
---
23
include/hw/misc/npcm7xx_mft.h | 70 +++++
10
target/arm/helper.h | 1 +
24
hw/misc/npcm7xx_mft.c | 540 ++++++++++++++++++++++++++++++++++
11
target/arm/a32.decode | 16 ++++++++------
25
hw/misc/meson.build | 1 +
12
target/arm/t32.decode | 18 ++++++++--------
26
hw/misc/trace-events | 8 +
13
target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
27
4 files changed, 619 insertions(+)
14
target/arm/translate-a64.c | 17 +++++++++++++++
28
create mode 100644 include/hw/misc/npcm7xx_mft.h
15
target/arm/translate.c | 23 ++++++++++++++++++++
29
create mode 100644 hw/misc/npcm7xx_mft.c
16
6 files changed, 103 insertions(+), 15 deletions(-)
30
17
31
diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
32
new file mode 100644
19
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX
20
--- a/target/arm/helper.h
34
--- /dev/null
21
+++ b/target/arm/helper.h
35
+++ b/include/hw/misc/npcm7xx_mft.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
36
@@ -XXX,XX +XXX,XX @@
23
DEF_HELPER_1(yield, void, env)
24
DEF_HELPER_1(pre_hvc, void, env)
25
DEF_HELPER_2(pre_smc, void, env, i32)
26
+DEF_HELPER_1(vesb, void, env)
27
28
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
29
DEF_HELPER_2(cpsr_write_eret, void, env, i32)
30
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/a32.decode
33
+++ b/target/arm/a32.decode
34
@@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
35
36
{
37
{
38
- YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
39
- WFE ---- 0011 0010 0000 1111 ---- 0000 0010
40
- WFI ---- 0011 0010 0000 1111 ---- 0000 0011
41
+ [
42
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
43
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
44
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
45
46
- # TODO: Implement SEV, SEVL; may help SMP performance.
47
- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
48
- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
49
+ # TODO: Implement SEV, SEVL; may help SMP performance.
50
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
51
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
52
+
53
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
54
+ ]
55
56
# The canonical nop ends in 00000000, but the whole of the
57
# rest of the space executes as nop if otherwise unsupported.
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
63
[
64
# Hints, and CPS
65
{
66
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
67
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
68
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
69
+ [
70
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
71
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
72
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
73
74
- # TODO: Implement SEV, SEVL; may help SMP performance.
75
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
76
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
77
+ # TODO: Implement SEV, SEVL; may help SMP performance.
78
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
79
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
80
81
- # For M-profile minimal-RAS ESB can be a NOP, which is the
82
- # default behaviour since it is in the hint space.
83
- # ESB 1111 0011 1010 1111 1000 0000 0001 0000
84
+ ESB 1111 0011 1010 1111 1000 0000 0001 0000
85
+ ]
86
87
# The canonical nop ends in 0000 0000, but the whole rest
88
# of the space is "reserved hint, behaves as nop".
89
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/op_helper.c
92
+++ b/target/arm/op_helper.c
93
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
94
access_type, mmu_idx, ra);
95
}
96
}
97
+
37
+/*
98
+/*
38
+ * Nuvoton NPCM7xx MFT Module
99
+ * This function corresponds to AArch64.vESBOperation().
39
+ *
100
+ * Note that the AArch32 version is not functionally different.
40
+ * Copyright 2021 Google LLC
41
+ *
42
+ * This program is free software; you can redistribute it and/or modify it
43
+ * under the terms of the GNU General Public License as published by the
44
+ * Free Software Foundation; either version 2 of the License, or
45
+ * (at your option) any later version.
46
+ *
47
+ * This program is distributed in the hope that it will be useful, but WITHOUT
48
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
49
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
50
+ * for more details.
51
+ */
101
+ */
52
+#ifndef NPCM7XX_MFT_H
102
+void HELPER(vesb)(CPUARMState *env)
53
+#define NPCM7XX_MFT_H
54
+
55
+#include "exec/memory.h"
56
+#include "hw/clock.h"
57
+#include "hw/irq.h"
58
+#include "hw/sysbus.h"
59
+#include "qom/object.h"
60
+
61
+/* Max Fan input number. */
62
+#define NPCM7XX_MFT_MAX_FAN_INPUT 19
63
+
64
+/*
65
+ * Number of registers in one MFT module. Don't change this without increasing
66
+ * the version_id in vmstate.
67
+ */
68
+#define NPCM7XX_MFT_NR_REGS (0x20 / sizeof(uint16_t))
69
+
70
+/*
71
+ * The MFT can take up to 4 inputs: A0, B0, A1, B1. It can measure one A and one
72
+ * B simultaneously. NPCM7XX_MFT_INASEL and NPCM7XX_MFT_INBSEL are used to
73
+ * select which A or B input are used.
74
+ */
75
+#define NPCM7XX_MFT_FANIN_COUNT 4
76
+
77
+/**
78
+ * struct NPCM7xxMFTState - Multi Functional Tachometer device state.
79
+ * @parent: System bus device.
80
+ * @iomem: Memory region through which registers are accessed.
81
+ * @clock_in: The input clock for MFT from CLK module.
82
+ * @clock_{1,2}: The counter clocks for NPCM7XX_MFT_CNT{1,2}
83
+ * @irq: The IRQ for this MFT state.
84
+ * @regs: The MMIO registers.
85
+ * @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
86
+ * @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
87
+ */
88
+typedef struct NPCM7xxMFTState {
89
+ SysBusDevice parent;
90
+
91
+ MemoryRegion iomem;
92
+
93
+ Clock *clock_in;
94
+ Clock *clock_1, *clock_2;
95
+ qemu_irq irq;
96
+ uint16_t regs[NPCM7XX_MFT_NR_REGS];
97
+
98
+ uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT];
99
+ uint32_t duty[NPCM7XX_MFT_FANIN_COUNT];
100
+} NPCM7xxMFTState;
101
+
102
+#define TYPE_NPCM7XX_MFT "npcm7xx-mft"
103
+#define NPCM7XX_MFT(obj) \
104
+ OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
105
+
106
+#endif /* NPCM7XX_MFT_H */
107
diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c
108
new file mode 100644
109
index XXXXXXX..XXXXXXX
110
--- /dev/null
111
+++ b/hw/misc/npcm7xx_mft.c
112
@@ -XXX,XX +XXX,XX @@
113
+/*
114
+ * Nuvoton NPCM7xx MFT Module
115
+ *
116
+ * Copyright 2021 Google LLC
117
+ *
118
+ * This program is free software; you can redistribute it and/or modify it
119
+ * under the terms of the GNU General Public License as published by the
120
+ * Free Software Foundation; either version 2 of the License, or
121
+ * (at your option) any later version.
122
+ *
123
+ * This program is distributed in the hope that it will be useful, but WITHOUT
124
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
125
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
126
+ * for more details.
127
+ */
128
+
129
+#include "qemu/osdep.h"
130
+#include "hw/irq.h"
131
+#include "hw/qdev-clock.h"
132
+#include "hw/qdev-properties.h"
133
+#include "hw/misc/npcm7xx_mft.h"
134
+#include "hw/misc/npcm7xx_pwm.h"
135
+#include "hw/registerfields.h"
136
+#include "migration/vmstate.h"
137
+#include "qapi/error.h"
138
+#include "qapi/visitor.h"
139
+#include "qemu/bitops.h"
140
+#include "qemu/error-report.h"
141
+#include "qemu/log.h"
142
+#include "qemu/module.h"
143
+#include "qemu/timer.h"
144
+#include "qemu/units.h"
145
+#include "trace.h"
146
+
147
+/*
148
+ * Some of the registers can only accessed via 16-bit ops and some can only
149
+ * be accessed via 8-bit ops. However we mark all of them using REG16 to
150
+ * simplify implementation. npcm7xx_mft_check_mem_op checks the access length
151
+ * of memory operations.
152
+ */
153
+REG16(NPCM7XX_MFT_CNT1, 0x00);
154
+REG16(NPCM7XX_MFT_CRA, 0x02);
155
+REG16(NPCM7XX_MFT_CRB, 0x04);
156
+REG16(NPCM7XX_MFT_CNT2, 0x06);
157
+REG16(NPCM7XX_MFT_PRSC, 0x08);
158
+REG16(NPCM7XX_MFT_CKC, 0x0a);
159
+REG16(NPCM7XX_MFT_MCTRL, 0x0c);
160
+REG16(NPCM7XX_MFT_ICTRL, 0x0e);
161
+REG16(NPCM7XX_MFT_ICLR, 0x10);
162
+REG16(NPCM7XX_MFT_IEN, 0x12);
163
+REG16(NPCM7XX_MFT_CPA, 0x14);
164
+REG16(NPCM7XX_MFT_CPB, 0x16);
165
+REG16(NPCM7XX_MFT_CPCFG, 0x18);
166
+REG16(NPCM7XX_MFT_INASEL, 0x1a);
167
+REG16(NPCM7XX_MFT_INBSEL, 0x1c);
168
+
169
+/* Register Fields */
170
+#define NPCM7XX_MFT_CKC_C2CSEL BIT(3)
171
+#define NPCM7XX_MFT_CKC_C1CSEL BIT(0)
172
+
173
+#define NPCM7XX_MFT_MCTRL_TBEN BIT(6)
174
+#define NPCM7XX_MFT_MCTRL_TAEN BIT(5)
175
+#define NPCM7XX_MFT_MCTRL_TBEDG BIT(4)
176
+#define NPCM7XX_MFT_MCTRL_TAEDG BIT(3)
177
+#define NPCM7XX_MFT_MCTRL_MODE5 BIT(2)
178
+
179
+#define NPCM7XX_MFT_ICTRL_TFPND BIT(5)
180
+#define NPCM7XX_MFT_ICTRL_TEPND BIT(4)
181
+#define NPCM7XX_MFT_ICTRL_TDPND BIT(3)
182
+#define NPCM7XX_MFT_ICTRL_TCPND BIT(2)
183
+#define NPCM7XX_MFT_ICTRL_TBPND BIT(1)
184
+#define NPCM7XX_MFT_ICTRL_TAPND BIT(0)
185
+
186
+#define NPCM7XX_MFT_ICLR_TFCLR BIT(5)
187
+#define NPCM7XX_MFT_ICLR_TECLR BIT(4)
188
+#define NPCM7XX_MFT_ICLR_TDCLR BIT(3)
189
+#define NPCM7XX_MFT_ICLR_TCCLR BIT(2)
190
+#define NPCM7XX_MFT_ICLR_TBCLR BIT(1)
191
+#define NPCM7XX_MFT_ICLR_TACLR BIT(0)
192
+
193
+#define NPCM7XX_MFT_IEN_TFIEN BIT(5)
194
+#define NPCM7XX_MFT_IEN_TEIEN BIT(4)
195
+#define NPCM7XX_MFT_IEN_TDIEN BIT(3)
196
+#define NPCM7XX_MFT_IEN_TCIEN BIT(2)
197
+#define NPCM7XX_MFT_IEN_TBIEN BIT(1)
198
+#define NPCM7XX_MFT_IEN_TAIEN BIT(0)
199
+
200
+#define NPCM7XX_MFT_CPCFG_GET_B(rv) extract8((rv), 4, 4)
201
+#define NPCM7XX_MFT_CPCFG_GET_A(rv) extract8((rv), 0, 4)
202
+#define NPCM7XX_MFT_CPCFG_HIEN BIT(3)
203
+#define NPCM7XX_MFT_CPCFG_EQEN BIT(2)
204
+#define NPCM7XX_MFT_CPCFG_LOEN BIT(1)
205
+#define NPCM7XX_MFT_CPCFG_CPSEL BIT(0)
206
+
207
+#define NPCM7XX_MFT_INASEL_SELA BIT(0)
208
+#define NPCM7XX_MFT_INBSEL_SELB BIT(0)
209
+
210
+/* Max CNT values of the module. The CNT value is a countdown from it. */
211
+#define NPCM7XX_MFT_MAX_CNT 0xFFFF
212
+
213
+/* Each fan revolution should generated 2 pulses */
214
+#define NPCM7XX_MFT_PULSE_PER_REVOLUTION 2
215
+
216
+typedef enum NPCM7xxMFTCaptureState {
217
+ /* capture succeeded with a valid CNT value. */
218
+ NPCM7XX_CAPTURE_SUCCEED,
219
+ /* capture stopped prematurely due to reaching CPCFG condition. */
220
+ NPCM7XX_CAPTURE_COMPARE_HIT,
221
+ /* capture fails since it reaches underflow condition for CNT. */
222
+ NPCM7XX_CAPTURE_UNDERFLOW,
223
+} NPCM7xxMFTCaptureState;
224
+
225
+static void npcm7xx_mft_reset(NPCM7xxMFTState *s)
226
+{
103
+{
227
+ int i;
104
+ /*
228
+
105
+ * The EL2Enabled() check is done inside arm_hcr_el2_eff,
229
+ /* Only registers PRSC ~ INBSEL need to be reset. */
106
+ * and will return HCR_EL2.VSE == 0, so nothing happens.
230
+ for (i = R_NPCM7XX_MFT_PRSC; i <= R_NPCM7XX_MFT_INBSEL; ++i) {
107
+ */
231
+ s->regs[i] = 0;
108
+ uint64_t hcr = arm_hcr_el2_eff(env);
109
+ bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
110
+ bool pending = enabled && (hcr & HCR_VSE);
111
+ bool masked = (env->daif & PSTATE_A);
112
+
113
+ /* If VSE pending and masked, defer the exception. */
114
+ if (pending && masked) {
115
+ uint32_t syndrome;
116
+
117
+ if (arm_el_is_aa64(env, 1)) {
118
+ /* Copy across IDS and ISS from VSESR. */
119
+ syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
120
+ } else {
121
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
122
+
123
+ if (extended_addresses_enabled(env)) {
124
+ syndrome = arm_fi_to_lfsc(&fi);
125
+ } else {
126
+ syndrome = arm_fi_to_sfsc(&fi);
127
+ }
128
+ /* Copy across AET and ExT from VSESR. */
129
+ syndrome |= env->cp15.vsesr_el2 & 0xd000;
130
+ }
131
+
132
+ /* Set VDISR_EL2.A along with the syndrome. */
133
+ env->cp15.vdisr_el2 = syndrome | (1u << 31);
134
+
135
+ /* Clear pending virtual SError */
136
+ env->cp15.hcr_el2 &= ~HCR_VSE;
137
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
232
+ }
138
+ }
233
+}
139
+}
234
+
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
235
+static void npcm7xx_mft_clear_interrupt(NPCM7xxMFTState *s, uint8_t iclr)
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
145
gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
146
}
147
break;
148
+ case 0b10000: /* ESB */
149
+ /* Without RAS, we must implement this as NOP. */
150
+ if (dc_isar_feature(aa64_ras, s)) {
151
+ /*
152
+ * QEMU does not have a source of physical SErrors,
153
+ * so we are only concerned with virtual SErrors.
154
+ * The pseudocode in the ARM for this case is
155
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
156
+ * AArch64.vESBOperation();
157
+ * Most of the condition can be evaluated at translation time.
158
+ * Test for EL2 present, and defer test for SEL2 to runtime.
159
+ */
160
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
161
+ gen_helper_vesb(cpu_env);
162
+ }
163
+ }
164
+ break;
165
case 0b11000: /* PACIAZ */
166
if (s->pauth_active) {
167
gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
168
diff --git a/target/arm/translate.c b/target/arm/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/translate.c
171
+++ b/target/arm/translate.c
172
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
173
return true;
174
}
175
176
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
236
+{
177
+{
237
+ /*
178
+ /*
238
+ * Clear bits in ICTRL where corresponding bits in iclr is 1.
179
+ * For M-profile, minimal-RAS ESB can be a NOP.
239
+ * Both iclr and ictrl are 8-bit regs. (See npcm7xx_mft_check_mem_op)
180
+ * Without RAS, we must implement this as NOP.
240
+ */
181
+ */
241
+ s->regs[R_NPCM7XX_MFT_ICTRL] &= ~iclr;
182
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
242
+}
243
+
244
+/*
245
+ * If the CPCFG's condition should be triggered during count down from
246
+ * NPCM7XX_MFT_MAX_CNT to src if compared to tgt, return the count when
247
+ * the condition is triggered.
248
+ * Otherwise return -1.
249
+ * Since tgt is uint16_t it must always <= NPCM7XX_MFT_MAX_CNT.
250
+ */
251
+static int npcm7xx_mft_compare(int32_t src, uint16_t tgt, uint8_t cpcfg)
252
+{
253
+ if (cpcfg & NPCM7XX_MFT_CPCFG_HIEN) {
254
+ return NPCM7XX_MFT_MAX_CNT;
255
+ }
256
+ if ((cpcfg & NPCM7XX_MFT_CPCFG_EQEN) && (src <= tgt)) {
257
+ return tgt;
258
+ }
259
+ if ((cpcfg & NPCM7XX_MFT_CPCFG_LOEN) && (tgt > 0) && (src < tgt)) {
260
+ return tgt - 1;
261
+ }
262
+
263
+ return -1;
264
+}
265
+
266
+/* Compute CNT according to corresponding fan's RPM. */
267
+static NPCM7xxMFTCaptureState npcm7xx_mft_compute_cnt(
268
+ Clock *clock, uint32_t max_rpm, uint32_t duty, uint16_t tgt,
269
+ uint8_t cpcfg, uint16_t *cnt)
270
+{
271
+ uint32_t rpm = (uint64_t)max_rpm * (uint64_t)duty / NPCM7XX_PWM_MAX_DUTY;
272
+ int32_t count;
273
+ int stopped;
274
+ NPCM7xxMFTCaptureState state;
275
+
276
+ if (rpm == 0) {
277
+ /*
183
+ /*
278
+ * If RPM = 0, capture won't happen. CNT will continue count down.
184
+ * QEMU does not have a source of physical SErrors,
279
+ * So it's effective equivalent to have a cnt > NPCM7XX_MFT_MAX_CNT
185
+ * so we are only concerned with virtual SErrors.
186
+ * The pseudocode in the ARM for this case is
187
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
188
+ * AArch32.vESBOperation();
189
+ * Most of the condition can be evaluated at translation time.
190
+ * Test for EL2 present, and defer test for SEL2 to runtime.
280
+ */
191
+ */
281
+ count = NPCM7XX_MFT_MAX_CNT + 1;
192
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
282
+ } else {
193
+ gen_helper_vesb(cpu_env);
283
+ /*
284
+ * RPM = revolution/min. The time for one revlution (in ns) is
285
+ * MINUTE_TO_NANOSECOND / RPM.
286
+ */
287
+ count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) /
288
+ (rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION));
289
+ }
290
+
291
+ if (count > NPCM7XX_MFT_MAX_CNT) {
292
+ count = -1;
293
+ } else {
294
+ /* The CNT is a countdown value from NPCM7XX_MFT_MAX_CNT. */
295
+ count = NPCM7XX_MFT_MAX_CNT - count;
296
+ }
297
+ stopped = npcm7xx_mft_compare(count, tgt, cpcfg);
298
+ if (stopped == -1) {
299
+ if (count == -1) {
300
+ /* Underflow */
301
+ state = NPCM7XX_CAPTURE_UNDERFLOW;
302
+ } else {
303
+ state = NPCM7XX_CAPTURE_SUCCEED;
304
+ }
305
+ } else {
306
+ count = stopped;
307
+ state = NPCM7XX_CAPTURE_COMPARE_HIT;
308
+ }
309
+
310
+ if (count != -1) {
311
+ *cnt = count;
312
+ }
313
+ trace_npcm7xx_mft_rpm(clock->canonical_path, clock_get_hz(clock),
314
+ state, count, rpm, duty);
315
+ return state;
316
+}
317
+
318
+/*
319
+ * Capture Fan RPM and update CNT and CR registers accordingly.
320
+ * Raise IRQ if certain contidions are met in IEN.
321
+ */
322
+static void npcm7xx_mft_capture(NPCM7xxMFTState *s)
323
+{
324
+ int irq_level = 0;
325
+ NPCM7xxMFTCaptureState state;
326
+ int sel;
327
+ uint8_t cpcfg;
328
+
329
+ /*
330
+ * If not mode 5, the behavior is undefined. We just do nothing in this
331
+ * case.
332
+ */
333
+ if (!(s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_MODE5)) {
334
+ return;
335
+ }
336
+
337
+ /* Capture input A. */
338
+ if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TAEN &&
339
+ s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) {
340
+ sel = s->regs[R_NPCM7XX_MFT_INASEL] & NPCM7XX_MFT_INASEL_SELA;
341
+ cpcfg = NPCM7XX_MFT_CPCFG_GET_A(s->regs[R_NPCM7XX_MFT_CPCFG]);
342
+ state = npcm7xx_mft_compute_cnt(s->clock_1,
343
+ sel ? s->max_rpm[2] : s->max_rpm[0],
344
+ sel ? s->duty[2] : s->duty[0],
345
+ s->regs[R_NPCM7XX_MFT_CPA],
346
+ cpcfg,
347
+ &s->regs[R_NPCM7XX_MFT_CNT1]);
348
+ switch (state) {
349
+ case NPCM7XX_CAPTURE_SUCCEED:
350
+ /* Interrupt on input capture on TAn transition - TAPND */
351
+ s->regs[R_NPCM7XX_MFT_CRA] = s->regs[R_NPCM7XX_MFT_CNT1];
352
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TAPND;
353
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TAIEN) {
354
+ irq_level = 1;
355
+ }
356
+ break;
357
+
358
+ case NPCM7XX_CAPTURE_COMPARE_HIT:
359
+ /* Compare Hit - TEPND */
360
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TEPND;
361
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TEIEN) {
362
+ irq_level = 1;
363
+ }
364
+ break;
365
+
366
+ case NPCM7XX_CAPTURE_UNDERFLOW:
367
+ /* Underflow - TCPND */
368
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TCPND;
369
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TCIEN) {
370
+ irq_level = 1;
371
+ }
372
+ break;
373
+
374
+ default:
375
+ g_assert_not_reached();
376
+ }
194
+ }
377
+ }
195
+ }
378
+
196
+ return true;
379
+ /* Capture input B. */
380
+ if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TBEN &&
381
+ s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) {
382
+ sel = s->regs[R_NPCM7XX_MFT_INBSEL] & NPCM7XX_MFT_INBSEL_SELB;
383
+ cpcfg = NPCM7XX_MFT_CPCFG_GET_B(s->regs[R_NPCM7XX_MFT_CPCFG]);
384
+ state = npcm7xx_mft_compute_cnt(s->clock_2,
385
+ sel ? s->max_rpm[3] : s->max_rpm[1],
386
+ sel ? s->duty[3] : s->duty[1],
387
+ s->regs[R_NPCM7XX_MFT_CPB],
388
+ cpcfg,
389
+ &s->regs[R_NPCM7XX_MFT_CNT2]);
390
+ switch (state) {
391
+ case NPCM7XX_CAPTURE_SUCCEED:
392
+ /* Interrupt on input capture on TBn transition - TBPND */
393
+ s->regs[R_NPCM7XX_MFT_CRB] = s->regs[R_NPCM7XX_MFT_CNT2];
394
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TBPND;
395
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TBIEN) {
396
+ irq_level = 1;
397
+ }
398
+ break;
399
+
400
+ case NPCM7XX_CAPTURE_COMPARE_HIT:
401
+ /* Compare Hit - TFPND */
402
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TFPND;
403
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TFIEN) {
404
+ irq_level = 1;
405
+ }
406
+ break;
407
+
408
+ case NPCM7XX_CAPTURE_UNDERFLOW:
409
+ /* Underflow - TDPND */
410
+ s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TDPND;
411
+ if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TDIEN) {
412
+ irq_level = 1;
413
+ }
414
+ break;
415
+
416
+ default:
417
+ g_assert_not_reached();
418
+ }
419
+ }
420
+
421
+ trace_npcm7xx_mft_capture(DEVICE(s)->canonical_path, irq_level);
422
+ qemu_set_irq(s->irq, irq_level);
423
+}
197
+}
424
+
198
+
425
+/* Update clock for counters. */
199
static bool trans_NOP(DisasContext *s, arg_NOP *a)
426
+static void npcm7xx_mft_update_clock(void *opaque, ClockEvent event)
200
{
427
+{
201
return true;
428
+ NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
429
+ uint64_t prescaled_clock_period;
430
+
431
+ prescaled_clock_period = clock_get(s->clock_in) *
432
+ (s->regs[R_NPCM7XX_MFT_PRSC] + 1ULL);
433
+ trace_npcm7xx_mft_update_clock(s->clock_in->canonical_path,
434
+ s->regs[R_NPCM7XX_MFT_CKC],
435
+ clock_get(s->clock_in),
436
+ prescaled_clock_period);
437
+ /* Update clock 1 */
438
+ if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) {
439
+ /* Clock is prescaled. */
440
+ clock_update(s->clock_1, prescaled_clock_period);
441
+ } else {
442
+ /* Clock stopped. */
443
+ clock_update(s->clock_1, 0);
444
+ }
445
+ /* Update clock 2 */
446
+ if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) {
447
+ /* Clock is prescaled. */
448
+ clock_update(s->clock_2, prescaled_clock_period);
449
+ } else {
450
+ /* Clock stopped. */
451
+ clock_update(s->clock_2, 0);
452
+ }
453
+
454
+ npcm7xx_mft_capture(s);
455
+}
456
+
457
+static uint64_t npcm7xx_mft_read(void *opaque, hwaddr offset, unsigned size)
458
+{
459
+ NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
460
+ uint16_t value = 0;
461
+
462
+ switch (offset) {
463
+ case A_NPCM7XX_MFT_ICLR:
464
+ qemu_log_mask(LOG_GUEST_ERROR,
465
+ "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
466
+ __func__, offset);
467
+ break;
468
+
469
+ default:
470
+ value = s->regs[offset / 2];
471
+ }
472
+
473
+ trace_npcm7xx_mft_read(DEVICE(s)->canonical_path, offset, value);
474
+ return value;
475
+}
476
+
477
+static void npcm7xx_mft_write(void *opaque, hwaddr offset,
478
+ uint64_t v, unsigned size)
479
+{
480
+ NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
481
+
482
+ trace_npcm7xx_mft_write(DEVICE(s)->canonical_path, offset, v);
483
+ switch (offset) {
484
+ case A_NPCM7XX_MFT_ICLR:
485
+ npcm7xx_mft_clear_interrupt(s, v);
486
+ break;
487
+
488
+ case A_NPCM7XX_MFT_CKC:
489
+ case A_NPCM7XX_MFT_PRSC:
490
+ s->regs[offset / 2] = v;
491
+ npcm7xx_mft_update_clock(s, ClockUpdate);
492
+ break;
493
+
494
+ default:
495
+ s->regs[offset / 2] = v;
496
+ npcm7xx_mft_capture(s);
497
+ break;
498
+ }
499
+}
500
+
501
+static bool npcm7xx_mft_check_mem_op(void *opaque, hwaddr offset,
502
+ unsigned size, bool is_write,
503
+ MemTxAttrs attrs)
504
+{
505
+ switch (offset) {
506
+ /* 16-bit registers. Must be accessed with 16-bit read/write.*/
507
+ case A_NPCM7XX_MFT_CNT1:
508
+ case A_NPCM7XX_MFT_CRA:
509
+ case A_NPCM7XX_MFT_CRB:
510
+ case A_NPCM7XX_MFT_CNT2:
511
+ case A_NPCM7XX_MFT_CPA:
512
+ case A_NPCM7XX_MFT_CPB:
513
+ return size == 2;
514
+
515
+ /* 8-bit registers. Must be accessed with 8-bit read/write.*/
516
+ case A_NPCM7XX_MFT_PRSC:
517
+ case A_NPCM7XX_MFT_CKC:
518
+ case A_NPCM7XX_MFT_MCTRL:
519
+ case A_NPCM7XX_MFT_ICTRL:
520
+ case A_NPCM7XX_MFT_ICLR:
521
+ case A_NPCM7XX_MFT_IEN:
522
+ case A_NPCM7XX_MFT_CPCFG:
523
+ case A_NPCM7XX_MFT_INASEL:
524
+ case A_NPCM7XX_MFT_INBSEL:
525
+ return size == 1;
526
+
527
+ default:
528
+ /* Invalid registers. */
529
+ return false;
530
+ }
531
+}
532
+
533
+static void npcm7xx_mft_get_max_rpm(Object *obj, Visitor *v, const char *name,
534
+ void *opaque, Error **errp)
535
+{
536
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
537
+}
538
+
539
+static void npcm7xx_mft_set_max_rpm(Object *obj, Visitor *v, const char *name,
540
+ void *opaque, Error **errp)
541
+{
542
+ NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
543
+ uint32_t *max_rpm = opaque;
544
+ uint32_t value;
545
+
546
+ if (!visit_type_uint32(v, name, &value, errp)) {
547
+ return;
548
+ }
549
+
550
+ *max_rpm = value;
551
+ npcm7xx_mft_capture(s);
552
+}
553
+
554
+static void npcm7xx_mft_duty_handler(void *opaque, int n, int value)
555
+{
556
+ NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
557
+
558
+ trace_npcm7xx_mft_set_duty(DEVICE(s)->canonical_path, n, value);
559
+ s->duty[n] = value;
560
+ npcm7xx_mft_capture(s);
561
+}
562
+
563
+static const struct MemoryRegionOps npcm7xx_mft_ops = {
564
+ .read = npcm7xx_mft_read,
565
+ .write = npcm7xx_mft_write,
566
+ .endianness = DEVICE_LITTLE_ENDIAN,
567
+ .valid = {
568
+ .min_access_size = 1,
569
+ .max_access_size = 2,
570
+ .unaligned = false,
571
+ .accepts = npcm7xx_mft_check_mem_op,
572
+ },
573
+};
574
+
575
+static void npcm7xx_mft_enter_reset(Object *obj, ResetType type)
576
+{
577
+ NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
578
+
579
+ npcm7xx_mft_reset(s);
580
+}
581
+
582
+static void npcm7xx_mft_hold_reset(Object *obj)
583
+{
584
+ NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
585
+
586
+ qemu_irq_lower(s->irq);
587
+}
588
+
589
+static void npcm7xx_mft_init(Object *obj)
590
+{
591
+ NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
592
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
593
+ DeviceState *dev = DEVICE(obj);
594
+
595
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_mft_ops, s,
596
+ TYPE_NPCM7XX_MFT, 4 * KiB);
597
+ sysbus_init_mmio(sbd, &s->iomem);
598
+ sysbus_init_irq(sbd, &s->irq);
599
+ s->clock_in = qdev_init_clock_in(dev, "clock-in", npcm7xx_mft_update_clock,
600
+ s, ClockUpdate);
601
+ s->clock_1 = qdev_init_clock_out(dev, "clock1");
602
+ s->clock_2 = qdev_init_clock_out(dev, "clock2");
603
+
604
+ for (int i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
605
+ object_property_add(obj, "max_rpm[*]", "uint32",
606
+ npcm7xx_mft_get_max_rpm,
607
+ npcm7xx_mft_set_max_rpm,
608
+ NULL, &s->max_rpm[i]);
609
+ }
610
+ qdev_init_gpio_in_named(dev, npcm7xx_mft_duty_handler, "duty",
611
+ NPCM7XX_MFT_FANIN_COUNT);
612
+}
613
+
614
+static const VMStateDescription vmstate_npcm7xx_mft = {
615
+ .name = "npcm7xx-mft-module",
616
+ .version_id = 0,
617
+ .minimum_version_id = 0,
618
+ .fields = (VMStateField[]) {
619
+ VMSTATE_CLOCK(clock_in, NPCM7xxMFTState),
620
+ VMSTATE_CLOCK(clock_1, NPCM7xxMFTState),
621
+ VMSTATE_CLOCK(clock_2, NPCM7xxMFTState),
622
+ VMSTATE_UINT16_ARRAY(regs, NPCM7xxMFTState, NPCM7XX_MFT_NR_REGS),
623
+ VMSTATE_UINT32_ARRAY(max_rpm, NPCM7xxMFTState, NPCM7XX_MFT_FANIN_COUNT),
624
+ VMSTATE_UINT32_ARRAY(duty, NPCM7xxMFTState, NPCM7XX_MFT_FANIN_COUNT),
625
+ VMSTATE_END_OF_LIST(),
626
+ },
627
+};
628
+
629
+static void npcm7xx_mft_class_init(ObjectClass *klass, void *data)
630
+{
631
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
634
+ dc->desc = "NPCM7xx MFT Controller";
635
+ dc->vmsd = &vmstate_npcm7xx_mft;
636
+ rc->phases.enter = npcm7xx_mft_enter_reset;
637
+ rc->phases.hold = npcm7xx_mft_hold_reset;
638
+}
639
+
640
+static const TypeInfo npcm7xx_mft_info = {
641
+ .name = TYPE_NPCM7XX_MFT,
642
+ .parent = TYPE_SYS_BUS_DEVICE,
643
+ .instance_size = sizeof(NPCM7xxMFTState),
644
+ .class_init = npcm7xx_mft_class_init,
645
+ .instance_init = npcm7xx_mft_init,
646
+};
647
+
648
+static void npcm7xx_mft_register_type(void)
649
+{
650
+ type_register_static(&npcm7xx_mft_info);
651
+}
652
+type_init(npcm7xx_mft_register_type);
653
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
654
index XXXXXXX..XXXXXXX 100644
655
--- a/hw/misc/meson.build
656
+++ b/hw/misc/meson.build
657
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
658
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
659
'npcm7xx_clk.c',
660
'npcm7xx_gcr.c',
661
+ 'npcm7xx_mft.c',
662
'npcm7xx_pwm.c',
663
'npcm7xx_rng.c',
664
))
665
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
666
index XXXXXXX..XXXXXXX 100644
667
--- a/hw/misc/trace-events
668
+++ b/hw/misc/trace-events
669
@@ -XXX,XX +XXX,XX @@ npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
670
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
671
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
672
673
+# npcm7xx_mft.c
674
+npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
675
+npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
676
+npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32
677
+npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d"
678
+npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64
679
+npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d"
680
+
681
# npcm7xx_rng.c
682
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
683
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
684
--
202
--
685
2.20.1
203
2.25.1
686
687
diff view generated by jsdifflib
[PULL 11/39] target/arm: Fix sve_zip_p vs odd vector lengths
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Wrote too much with low-half zip (zip1) with vl % 512 != 0.
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
5
Adjust all of the x + (y << s) to x | (y << s) as a style fix.
6
7
We only ever have exact overlap between D, M, and N. Therefore
8
we only need a single temporary, and we do not need to check for
9
partial overlap.
10
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20210309155305.11301-3-richard.henderson@linaro.org
5
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
7
---
17
target/arm/sve_helper.c | 25 ++++++++++++++-----------
8
docs/system/arm/emulation.rst | 1 +
18
1 file changed, 14 insertions(+), 11 deletions(-)
9
target/arm/cpu64.c | 1 +
10
target/arm/cpu_tcg.c | 1 +
11
3 files changed, 3 insertions(+)
19
12
20
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/sve_helper.c
15
--- a/docs/system/arm/emulation.rst
23
+++ b/target/arm/sve_helper.c
16
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
18
- FEAT_PMULL (PMULL, PMULL2 instructions)
26
int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
19
- FEAT_PMUv3p1 (PMU Extensions v3.1)
27
intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA);
20
- FEAT_PMUv3p4 (PMU Extensions v3.4)
28
+ int esize = 1 << esz;
21
+- FEAT_RAS (Reliability, availability, and serviceability)
29
uint64_t *d = vd;
22
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
30
intptr_t i;
23
- FEAT_RNG (Random number generator)
31
24
- FEAT_SB (Speculation Barrier)
32
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
33
mm = extract64(mm, high * half, half);
26
index XXXXXXX..XXXXXXX 100644
34
nn = expand_bits(nn, esz);
27
--- a/target/arm/cpu64.c
35
mm = expand_bits(mm, esz);
28
+++ b/target/arm/cpu64.c
36
- d[0] = nn + (mm << (1 << esz));
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
37
+ d[0] = nn | (mm << esize);
30
t = cpu->isar.id_aa64pfr0;
38
} else {
31
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
39
- ARMPredicateReg tmp_n, tmp_m;
32
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
40
+ ARMPredicateReg tmp;
33
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
41
34
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
42
/* We produce output faster than we consume input.
35
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
43
Therefore we must be mindful of possible overlap. */
36
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
44
- if ((vn - vd) < (uintptr_t)oprsz) {
37
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
45
- vn = memcpy(&tmp_n, vn, oprsz);
38
index XXXXXXX..XXXXXXX 100644
46
- }
39
--- a/target/arm/cpu_tcg.c
47
- if ((vm - vd) < (uintptr_t)oprsz) {
40
+++ b/target/arm/cpu_tcg.c
48
- vm = memcpy(&tmp_m, vm, oprsz);
41
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
49
+ if (vd == vn) {
42
50
+ vn = memcpy(&tmp, vn, oprsz);
43
t = cpu->isar.id_pfr0;
51
+ if (vd == vm) {
44
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
52
+ vm = vn;
45
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
53
+ }
46
cpu->isar.id_pfr0 = t;
54
+ } else if (vd == vm) {
47
55
+ vm = memcpy(&tmp, vm, oprsz);
48
t = cpu->isar.id_pfr2;
56
}
57
if (high) {
58
high = oprsz >> 1;
59
}
60
61
- if ((high & 3) == 0) {
62
+ if ((oprsz & 7) == 0) {
63
uint32_t *n = vn, *m = vm;
64
high >>= 2;
65
66
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) {
67
+ for (i = 0; i < oprsz / 8; i++) {
68
uint64_t nn = n[H4(high + i)];
69
uint64_t mm = m[H4(high + i)];
70
71
nn = expand_bits(nn, esz);
72
mm = expand_bits(mm, esz);
73
- d[i] = nn + (mm << (1 << esz));
74
+ d[i] = nn | (mm << esize);
75
}
76
} else {
77
uint8_t *n = vn, *m = vm;
78
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
79
80
nn = expand_bits(nn, esz);
81
mm = expand_bits(mm, esz);
82
- d16[H2(i)] = nn + (mm << (1 << esz));
83
+ d16[H2(i)] = nn | (mm << esize);
84
}
85
}
86
}
87
--
49
--
88
2.20.1
50
2.25.1
89
90
diff view generated by jsdifflib
[PULL 13/39] target/arm: Update find_last_active for PREDDESC
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since b64ee454a4a0, all predicate operations should be
3
This feature is AArch64 only, and applies to physical SErrors,
4
using these field macros for predicates.
4
which QEMU does not implement, thus the feature is a nop.
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210309155305.11301-5-richard.henderson@linaro.org
8
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/sve_helper.c | 6 +++---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/translate-sve.c | 7 +++----
12
target/arm/cpu64.c | 1 +
13
2 files changed, 6 insertions(+), 7 deletions(-)
13
2 files changed, 2 insertions(+)
14
14
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
17
--- a/docs/system/arm/emulation.rst
18
+++ b/target/arm/sve_helper.c
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc)
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
*/
20
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
21
int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc)
21
- FEAT_HPDS (Hierarchical permission disables)
22
{
22
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
23
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
23
+- FEAT_IESB (Implicit error synchronization event)
24
- intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
24
- FEAT_JSCVT (JavaScript conversion instructions)
25
+ intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8);
25
- FEAT_LOR (Limited ordering regions)
26
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
26
- FEAT_LPA (Large Physical Address space)
27
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
- return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz);
29
+ return last_active_element(vg, words, esz);
30
}
31
32
void HELPER(sve_splice)(void *vd, void *vn, void *vm, void *vg, uint32_t desc)
33
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
34
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-sve.c
29
--- a/target/arm/cpu64.c
36
+++ b/target/arm/translate-sve.c
30
+++ b/target/arm/cpu64.c
37
@@ -XXX,XX +XXX,XX @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
38
*/
32
t = cpu->isar.id_aa64mmfr2;
39
TCGv_ptr t_p = tcg_temp_new_ptr();
33
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
40
TCGv_i32 t_desc;
34
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
41
- unsigned vsz = pred_full_reg_size(s);
35
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
42
- unsigned desc;
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
43
+ unsigned desc = 0;
37
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
44
38
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
45
- desc = vsz - 2;
46
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
47
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
48
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
49
50
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
51
t_desc = tcg_const_i32(desc);
52
--
39
--
53
2.20.1
40
2.25.1
54
55
diff view generated by jsdifflib
[PULL 12/39] target/arm: Fix sve_punpk_p vs odd vector lengths
[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Wrote too much with punpk1 with vl % 512 != 0.
3
This extension concerns branch speculation, which TCG does
4
not implement. Thus we can trivially enable this feature.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210309155305.11301-4-richard.henderson@linaro.org
8
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/sve_helper.c | 4 ++--
11
docs/system/arm/emulation.rst | 1 +
12
1 file changed, 2 insertions(+), 2 deletions(-)
12
target/arm/cpu64.c | 1 +
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
13
15
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve_helper.c
18
--- a/docs/system/arm/emulation.rst
17
+++ b/target/arm/sve_helper.c
19
+++ b/docs/system/arm/emulation.rst
18
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
high = oprsz >> 1;
21
- FEAT_BBM at level 2 (Translation table break-before-make levels)
20
}
22
- FEAT_BF16 (AArch64 BFloat16 instructions)
21
23
- FEAT_BTI (Branch Target Identification)
22
- if ((high & 3) == 0) {
24
+- FEAT_CSV2 (Cache speculation variant 2)
23
+ if ((oprsz & 7) == 0) {
25
- FEAT_DIT (Data Independent Timing instructions)
24
uint32_t *n = vn;
26
- FEAT_DPB (DC CVAP instruction)
25
high >>= 2;
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
26
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
27
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) {
29
index XXXXXXX..XXXXXXX 100644
28
+ for (i = 0; i < oprsz / 8; i++) {
30
--- a/target/arm/cpu64.c
29
uint64_t nn = n[H4(high + i)];
31
+++ b/target/arm/cpu64.c
30
d[i] = expand_bits(nn, 0);
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
31
}
33
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
34
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
35
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
37
cpu->isar.id_aa64pfr0 = t;
38
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_mmfr4 = t;
46
47
t = cpu->isar.id_pfr0;
48
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
49
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
50
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
51
cpu->isar.id_pfr0 = t;
32
--
52
--
33
2.20.1
53
2.25.1
34
35
diff view generated by jsdifflib
[PULL 30/39] tests/qtest: Test PWM fan RPM using MFT in PWM test
[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds testing of PWM fan RPMs in the existing npcm7xx pwm
3
There is no branch prediction in TCG, therefore there is no
4
test. It tests whether the MFT module can measure correct fan values
4
need to actually include the context number into the predictor.
5
for a PWM fan in NPCM7XX boards.
5
Therefore all we need to do is add the state for SCXTNUM_ELx.
6
6
7
Reviewed-by: Doug Evans <dje@google.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Signed-off-by: Hao Wu <wuhaotsh@google.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20210311180855.149764-6-wuhaotsh@google.com
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
tests/qtest/npcm7xx_pwm-test.c | 205 ++++++++++++++++++++++++++++++++-
12
docs/system/arm/emulation.rst | 3 ++
15
1 file changed, 199 insertions(+), 6 deletions(-)
13
target/arm/cpu.h | 16 +++++++++
14
target/arm/cpu.c | 5 +++
15
target/arm/cpu64.c | 3 +-
16
target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++-
17
5 files changed, 86 insertions(+), 2 deletions(-)
16
18
17
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/qtest/npcm7xx_pwm-test.c
21
--- a/docs/system/arm/emulation.rst
20
+++ b/tests/qtest/npcm7xx_pwm-test.c
22
+++ b/docs/system/arm/emulation.rst
21
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
22
#define PLL_FBDV(rv) extract32((rv), 16, 12)
24
- FEAT_BF16 (AArch64 BFloat16 instructions)
23
#define PLL_OTDV1(rv) extract32((rv), 8, 3)
25
- FEAT_BTI (Branch Target Identification)
24
#define PLL_OTDV2(rv) extract32((rv), 13, 3)
26
- FEAT_CSV2 (Cache speculation variant 2)
25
+#define APB4CKDIV(rv) extract32((rv), 30, 2)
27
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
26
#define APB3CKDIV(rv) extract32((rv), 28, 2)
28
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
27
#define CLK2CKDIV(rv) extract32((rv), 0, 1)
29
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
28
#define CLK4CKDIV(rv) extract32((rv), 26, 2)
30
- FEAT_DIT (Data Independent Timing instructions)
29
@@ -XXX,XX +XXX,XX @@
31
- FEAT_DPB (DC CVAP instruction)
30
32
- FEAT_Debugv8p2 (Debug changes for v8.2)
31
#define MAX_DUTY 1000000
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
34
index XXXXXXX..XXXXXXX 100644
33
+/* MFT (PWM fan) related */
35
--- a/target/arm/cpu.h
34
+#define MFT_BA(n) (0xf0180000 + ((n) * 0x1000))
36
+++ b/target/arm/cpu.h
35
+#define MFT_IRQ(n) (96 + (n))
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
36
+#define MFT_CNT1 0x00
38
ARMPACKey apdb;
37
+#define MFT_CRA 0x02
39
ARMPACKey apga;
38
+#define MFT_CRB 0x04
40
} keys;
39
+#define MFT_CNT2 0x06
41
+
40
+#define MFT_PRSC 0x08
42
+ uint64_t scxtnum_el[4];
41
+#define MFT_CKC 0x0a
43
#endif
42
+#define MFT_MCTRL 0x0c
44
43
+#define MFT_ICTRL 0x0e
45
#if defined(CONFIG_USER_ONLY)
44
+#define MFT_ICLR 0x10
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
45
+#define MFT_IEN 0x12
47
#define SCTLR_WXN (1U << 19)
46
+#define MFT_CPA 0x14
48
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
47
+#define MFT_CPB 0x16
49
#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
48
+#define MFT_CPCFG 0x18
50
+#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
49
+#define MFT_INASEL 0x1a
51
#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
50
+#define MFT_INBSEL 0x1c
52
#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
51
+
53
#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
52
+#define MFT_MCTRL_ALL 0x64
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
53
+#define MFT_ICLR_ALL 0x3f
55
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
54
+#define MFT_IEN_ALL 0x3f
55
+#define MFT_CPCFG_EQ_MODE 0x44
56
+
57
+#define MFT_CKC_C2CSEL BIT(3)
58
+#define MFT_CKC_C1CSEL BIT(0)
59
+
60
+#define MFT_ICTRL_TFPND BIT(5)
61
+#define MFT_ICTRL_TEPND BIT(4)
62
+#define MFT_ICTRL_TDPND BIT(3)
63
+#define MFT_ICTRL_TCPND BIT(2)
64
+#define MFT_ICTRL_TBPND BIT(1)
65
+#define MFT_ICTRL_TAPND BIT(0)
66
+
67
+#define MFT_MAX_CNT 0xffff
68
+#define MFT_TIMEOUT 0x5000
69
+
70
+#define DEFAULT_RPM 19800
71
+#define DEFAULT_PRSC 255
72
+#define MFT_PULSE_PER_REVOLUTION 2
73
+
74
+#define MAX_ERROR 1
75
+
76
typedef struct PWMModule {
77
int irq;
78
uint64_t base_addr;
79
@@ -XXX,XX +XXX,XX @@ static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
80
return pwm_qom_get(qts, path, name);
81
}
56
}
82
57
83
+static void mft_qom_set(QTestState *qts, int index, const char *name,
58
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
84
+ uint32_t value)
85
+{
59
+{
86
+ QDict *response;
60
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
87
+ char *path = g_strdup_printf("/machine/soc/mft[%d]", index);
61
+ if (key >= 2) {
88
+
62
+ return true; /* FEAT_CSV2_2 */
89
+ g_test_message("Setting properties %s of mft[%d] with value %u",
63
+ }
90
+ name, index, value);
64
+ if (key == 1) {
91
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
65
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
92
+ " 'arguments': { 'path': %s, "
66
+ return key >= 2; /* FEAT_CSV2_1p2 */
93
+ " 'property': %s, 'value': %u}}",
67
+ }
94
+ path, name, value);
68
+ return false;
95
+ /* The qom set message returns successfully. */
96
+ g_assert_true(qdict_haskey(response, "return"));
97
+}
69
+}
98
+
70
+
99
static uint32_t get_pll(uint32_t con)
71
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
100
{
72
{
101
return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
73
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
102
* PLL_OTDV2(con));
74
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
103
}
75
index XXXXXXX..XXXXXXX 100644
104
76
--- a/target/arm/cpu.c
105
-static uint64_t read_pclk(QTestState *qts)
77
+++ b/target/arm/cpu.c
106
+static uint64_t read_pclk(QTestState *qts, bool mft)
78
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
107
{
79
*/
108
uint64_t freq = REF_HZ;
80
env->cp15.gcr_el1 = 0x1ffff;
109
uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
81
}
110
uint32_t pllcon;
82
+ /*
111
uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
83
+ * Disable access to SCXTNUM_EL0 from CSV2_1p2.
112
uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
84
+ * This is not yet exposed from the Linux kernel in any way.
113
+ uint32_t apbdiv = mft ? APB4CKDIV(clkdiv2) : APB3CKDIV(clkdiv2);
85
+ */
114
86
+ env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
115
switch (CPUCKSEL(clksel)) {
87
#else
116
case 0:
88
/* Reset into the highest available EL */
117
@@ -XXX,XX +XXX,XX @@ static uint64_t read_pclk(QTestState *qts)
89
if (arm_feature(env, ARM_FEATURE_EL3)) {
118
g_assert_not_reached();
90
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/cpu64.c
93
+++ b/target/arm/cpu64.c
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
95
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
96
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
97
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
98
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
99
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
100
cpu->isar.id_aa64pfr0 = t;
101
102
t = cpu->isar.id_aa64pfr1;
103
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
104
* we do for EL2 with the virtualization=on property.
105
*/
106
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
107
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
108
cpu->isar.id_aa64pfr1 = t;
109
110
t = cpu->isar.id_aa64mmfr0;
111
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/helper.c
114
+++ b/target/arm/helper.c
115
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
116
if (cpu_isar_feature(aa64_mte, cpu)) {
117
valid_mask |= SCR_ATA;
118
}
119
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
120
+ valid_mask |= SCR_ENSCXT;
121
+ }
122
} else {
123
valid_mask &= ~(SCR_RW | SCR_ST);
124
if (cpu_isar_feature(aa32_ras, cpu)) {
125
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
126
if (cpu_isar_feature(aa64_mte, cpu)) {
127
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
128
}
129
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
130
+ valid_mask |= HCR_ENSCXT;
131
+ }
119
}
132
}
120
133
121
- freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
134
/* Clear RES0 bits. */
122
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + apbdiv);
135
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
123
136
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
124
return freq;
137
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
125
}
138
126
@@ -XXX,XX +XXX,XX @@ static uint32_t pwm_selector(uint32_t csr)
139
+ { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
127
static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
140
+ "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
128
uint32_t cnr)
141
+ isar_feature_aa64_scxtnum },
129
{
142
+
130
- return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
143
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
131
+ return read_pclk(qts, false) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
144
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
132
}
145
};
133
146
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
134
static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
147
},
135
@@ -XXX,XX +XXX,XX @@ static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
148
};
136
qtest_writel(qts, td->module->base_addr + offset, value);
149
137
}
150
-#endif
138
151
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
139
+static uint8_t mft_readb(QTestState *qts, int index, unsigned offset)
152
+ bool isread)
140
+{
153
+{
141
+ return qtest_readb(qts, MFT_BA(index) + offset);
154
+ uint64_t hcr = arm_hcr_el2_eff(env);
155
+ int el = arm_current_el(env);
156
+
157
+ if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
158
+ if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
159
+ if (hcr & HCR_TGE) {
160
+ return CP_ACCESS_TRAP_EL2;
161
+ }
162
+ return CP_ACCESS_TRAP;
163
+ }
164
+ } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
165
+ return CP_ACCESS_TRAP_EL2;
166
+ }
167
+ if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
168
+ return CP_ACCESS_TRAP_EL2;
169
+ }
170
+ if (el < 3
171
+ && arm_feature(env, ARM_FEATURE_EL3)
172
+ && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
173
+ return CP_ACCESS_TRAP_EL3;
174
+ }
175
+ return CP_ACCESS_OK;
142
+}
176
+}
143
+
177
+
144
+static uint16_t mft_readw(QTestState *qts, int index, unsigned offset)
178
+static const ARMCPRegInfo scxtnum_reginfo[] = {
145
+{
179
+ { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
146
+ return qtest_readw(qts, MFT_BA(index) + offset);
180
+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
147
+}
181
+ .access = PL0_RW, .accessfn = access_scxtnum,
148
+
182
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
149
+static void mft_writeb(QTestState *qts, int index, unsigned offset,
183
+ { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
150
+ uint8_t value)
184
+ .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
151
+{
185
+ .access = PL1_RW, .accessfn = access_scxtnum,
152
+ qtest_writeb(qts, MFT_BA(index) + offset, value);
186
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
153
+}
187
+ { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
154
+
188
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
155
+static void mft_writew(QTestState *qts, int index, unsigned offset,
189
+ .access = PL2_RW, .accessfn = access_scxtnum,
156
+ uint16_t value)
190
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
157
+{
191
+ { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
158
+ return qtest_writew(qts, MFT_BA(index) + offset, value);
192
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
159
+}
193
+ .access = PL3_RW,
160
+
194
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
161
static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
195
+};
162
{
196
+#endif /* TARGET_AARCH64 */
163
return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
197
164
@@ -XXX,XX +XXX,XX @@ static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
198
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
165
pwm_write(qts, td, td->pwm->cmr_offset, value);
199
bool isread)
166
}
200
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
167
201
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
168
+static int mft_compute_index(const TestData *td)
202
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
169
+{
203
}
170
+ int index = pwm_module_index(td->module) * ARRAY_SIZE(pwm_list) +
204
+
171
+ pwm_index(td->pwm);
205
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
172
+
206
+ define_arm_cp_regs(cpu, scxtnum_reginfo);
173
+ g_assert_cmpint(index, <,
207
+ }
174
+ ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list));
208
#endif
175
+
209
176
+ return index;
210
if (cpu_isar_feature(any_predinv, cpu)) {
177
+}
178
+
179
+static void mft_reset_counters(QTestState *qts, int index)
180
+{
181
+ mft_writew(qts, index, MFT_CNT1, MFT_MAX_CNT);
182
+ mft_writew(qts, index, MFT_CNT2, MFT_MAX_CNT);
183
+ mft_writew(qts, index, MFT_CRA, MFT_MAX_CNT);
184
+ mft_writew(qts, index, MFT_CRB, MFT_MAX_CNT);
185
+ mft_writew(qts, index, MFT_CPA, MFT_MAX_CNT - MFT_TIMEOUT);
186
+ mft_writew(qts, index, MFT_CPB, MFT_MAX_CNT - MFT_TIMEOUT);
187
+}
188
+
189
+static void mft_init(QTestState *qts, const TestData *td)
190
+{
191
+ int index = mft_compute_index(td);
192
+
193
+ /* Enable everything */
194
+ mft_writeb(qts, index, MFT_CKC, 0);
195
+ mft_writeb(qts, index, MFT_ICLR, MFT_ICLR_ALL);
196
+ mft_writeb(qts, index, MFT_MCTRL, MFT_MCTRL_ALL);
197
+ mft_writeb(qts, index, MFT_IEN, MFT_IEN_ALL);
198
+ mft_writeb(qts, index, MFT_INASEL, 0);
199
+ mft_writeb(qts, index, MFT_INBSEL, 0);
200
+
201
+ /* Set cpcfg to use EQ mode, same as kernel driver */
202
+ mft_writeb(qts, index, MFT_CPCFG, MFT_CPCFG_EQ_MODE);
203
+
204
+ /* Write default counters, timeout and prescaler */
205
+ mft_reset_counters(qts, index);
206
+ mft_writeb(qts, index, MFT_PRSC, DEFAULT_PRSC);
207
+
208
+ /* Write default max rpm via QMP */
209
+ mft_qom_set(qts, index, "max_rpm[0]", DEFAULT_RPM);
210
+ mft_qom_set(qts, index, "max_rpm[1]", DEFAULT_RPM);
211
+}
212
+
213
+static int32_t mft_compute_cnt(uint32_t rpm, uint64_t clk)
214
+{
215
+ uint64_t cnt;
216
+
217
+ if (rpm == 0) {
218
+ return -1;
219
+ }
220
+
221
+ cnt = clk * 60 / ((DEFAULT_PRSC + 1) * rpm * MFT_PULSE_PER_REVOLUTION);
222
+ if (cnt >= MFT_TIMEOUT) {
223
+ return -1;
224
+ }
225
+ return MFT_MAX_CNT - cnt;
226
+}
227
+
228
+static void mft_verify_rpm(QTestState *qts, const TestData *td, uint64_t duty)
229
+{
230
+ int index = mft_compute_index(td);
231
+ uint16_t cnt, cr;
232
+ uint32_t rpm = DEFAULT_RPM * duty / MAX_DUTY;
233
+ uint64_t clk = read_pclk(qts, true);
234
+ int32_t expected_cnt = mft_compute_cnt(rpm, clk);
235
+
236
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
237
+ g_test_message(
238
+ "verifying rpm for mft[%d]: clk: %lu, duty: %lu, rpm: %u, cnt: %d",
239
+ index, clk, duty, rpm, expected_cnt);
240
+
241
+ /* Verify rpm for fan A */
242
+ /* Stop capture */
243
+ mft_writeb(qts, index, MFT_CKC, 0);
244
+ mft_writeb(qts, index, MFT_ICLR, MFT_ICLR_ALL);
245
+ mft_reset_counters(qts, index);
246
+ g_assert_cmphex(mft_readw(qts, index, MFT_CNT1), ==, MFT_MAX_CNT);
247
+ g_assert_cmphex(mft_readw(qts, index, MFT_CRA), ==, MFT_MAX_CNT);
248
+ g_assert_cmphex(mft_readw(qts, index, MFT_CPA), ==,
249
+ MFT_MAX_CNT - MFT_TIMEOUT);
250
+ /* Start capture */
251
+ mft_writeb(qts, index, MFT_CKC, MFT_CKC_C1CSEL);
252
+ g_assert_true(qtest_get_irq(qts, MFT_IRQ(index)));
253
+ if (expected_cnt == -1) {
254
+ g_assert_cmphex(mft_readb(qts, index, MFT_ICTRL), ==, MFT_ICTRL_TEPND);
255
+ } else {
256
+ g_assert_cmphex(mft_readb(qts, index, MFT_ICTRL), ==, MFT_ICTRL_TAPND);
257
+ cnt = mft_readw(qts, index, MFT_CNT1);
258
+ /*
259
+ * Due to error in clock measurement and rounding, we might have a small
260
+ * error in measuring RPM.
261
+ */
262
+ g_assert_cmphex(cnt + MAX_ERROR, >=, expected_cnt);
263
+ g_assert_cmphex(cnt, <=, expected_cnt + MAX_ERROR);
264
+ cr = mft_readw(qts, index, MFT_CRA);
265
+ g_assert_cmphex(cnt, ==, cr);
266
+ }
267
+
268
+ /* Verify rpm for fan B */
269
+
270
+ qtest_irq_intercept_out(qts, "/machine/soc/a9mpcore/gic");
271
+}
272
+
273
/* Check pwm registers can be reset to default value */
274
static void test_init(gconstpointer test_data)
275
{
276
const TestData *td = test_data;
277
- QTestState *qts = qtest_init("-machine quanta-gsj");
278
+ QTestState *qts = qtest_init("-machine npcm750-evb");
279
int module = pwm_module_index(td->module);
280
int pwm = pwm_index(td->pwm);
281
282
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
283
static void test_oneshot(gconstpointer test_data)
284
{
285
const TestData *td = test_data;
286
- QTestState *qts = qtest_init("-machine quanta-gsj");
287
+ QTestState *qts = qtest_init("-machine npcm750-evb");
288
int module = pwm_module_index(td->module);
289
int pwm = pwm_index(td->pwm);
290
uint32_t ppr, csr, pcr;
291
@@ -XXX,XX +XXX,XX @@ static void test_oneshot(gconstpointer test_data)
292
static void test_toggle(gconstpointer test_data)
293
{
294
const TestData *td = test_data;
295
- QTestState *qts = qtest_init("-machine quanta-gsj");
296
+ QTestState *qts = qtest_init("-machine npcm750-evb");
297
int module = pwm_module_index(td->module);
298
int pwm = pwm_index(td->pwm);
299
uint32_t ppr, csr, pcr, cnr, cmr;
300
int i, j, k, l;
301
uint64_t expected_freq, expected_duty;
302
303
+ mft_init(qts, td);
304
+
305
pcr = CH_EN | CH_MOD;
306
for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
307
ppr = ppr_list[i];
308
@@ -XXX,XX +XXX,XX @@ static void test_toggle(gconstpointer test_data)
309
==, expected_freq);
310
}
311
312
+ /* Test MFT's RPM is correct. */
313
+ mft_verify_rpm(qts, td, expected_duty);
314
+
315
/* Test inverted mode */
316
expected_duty = pwm_compute_duty(cnr, cmr, true);
317
pwm_write_pcr(qts, td, pcr | CH_INV);
318
--
211
--
319
2.20.1
212
2.25.1
320
321
diff view generated by jsdifflib
[PULL 17/39] target/arm: Update sve reduction vs simd_desc
[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With the reduction operations, we intentionally increase maxsz to
3
This extension concerns cache speculation, which TCG does
4
the next power of 2, so as to fill out the reduction tree correctly.
4
not implement. Thus we can trivially enable this feature.
5
Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small
6
vectors, so this triggers an assertion for vector sizes > 32 that are
7
not themselves a power of 2.
8
5
9
Pass the power-of-two value in the simd_data field instead.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20210309155305.11301-9-richard.henderson@linaro.org
8
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
target/arm/sve_helper.c | 2 +-
11
docs/system/arm/emulation.rst | 1 +
17
target/arm/translate-sve.c | 2 +-
12
target/arm/cpu64.c | 1 +
18
2 files changed, 2 insertions(+), 2 deletions(-)
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
19
15
20
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/sve_helper.c
18
--- a/docs/system/arm/emulation.rst
23
+++ b/target/arm/sve_helper.c
19
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
} \
21
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
26
uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
27
{ \
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
28
- uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \
24
+- FEAT_CSV3 (Cache speculation variant 3)
29
+ uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
25
- FEAT_DIT (Data Independent Timing instructions)
30
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
26
- FEAT_DPB (DC CVAP instruction)
31
for (i = 0; i < oprsz; ) { \
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
32
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
33
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
34
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-sve.c
30
--- a/target/arm/cpu64.c
36
+++ b/target/arm/translate-sve.c
31
+++ b/target/arm/cpu64.c
37
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
38
{
33
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
39
unsigned vsz = vec_full_reg_size(s);
34
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
40
unsigned p2vsz = pow2ceil(vsz);
35
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
41
- TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, p2vsz, 0));
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
42
+ TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
37
cpu->isar.id_aa64pfr0 = t;
43
TCGv_ptr t_zn, t_pg, status;
38
44
TCGv_i64 temp;
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_pfr0 = t;
46
47
t = cpu->isar.id_pfr2;
48
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
49
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
50
cpu->isar.id_pfr2 = t;
45
51
46
--
52
--
47
2.20.1
53
2.25.1
48
49
diff view generated by jsdifflib
[PULL 10/39] target/arm: Fix sve_uzp_p vs odd vector lengths
[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Missed out on compressing the second half of a predicate
3
This extension concerns not merging memory access, which TCG does
4
with length vl % 512 > 256.
4
not implement. Thus we can trivially enable this feature.
5
Add a comment to handle_hint for the DGH instruction, but no code.
5
6
6
Adjust all of the x + (y << s) to x | (y << s) as a
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
general style fix. Drop the extract64 because the input
8
uint64_t are known to be already zero-extended from the
9
current size of the predicate.
10
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20210309155305.11301-2-richard.henderson@linaro.org
9
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
11
---
17
target/arm/sve_helper.c | 30 +++++++++++++++++++++---------
12
docs/system/arm/emulation.rst | 1 +
18
1 file changed, 21 insertions(+), 9 deletions(-)
13
target/arm/cpu64.c | 1 +
14
target/arm/translate-a64.c | 1 +
15
3 files changed, 3 insertions(+)
19
16
20
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/sve_helper.c
19
--- a/docs/system/arm/emulation.rst
23
+++ b/target/arm/sve_helper.c
20
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
if (oprsz <= 8) {
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
26
l = compress_bits(n[0] >> odd, esz);
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
27
h = compress_bits(m[0] >> odd, esz);
24
- FEAT_CSV3 (Cache speculation variant 3)
28
- d[0] = extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz);
25
+- FEAT_DGH (Data gathering hint)
29
+ d[0] = l | (h << (4 * oprsz));
26
- FEAT_DIT (Data Independent Timing instructions)
30
} else {
27
- FEAT_DPB (DC CVAP instruction)
31
ARMPredicateReg tmp_m;
28
- FEAT_Debugv8p2 (Debug changes for v8.2)
32
intptr_t oprsz_16 = oprsz / 16;
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
33
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
30
index XXXXXXX..XXXXXXX 100644
34
h = n[2 * i + 1];
31
--- a/target/arm/cpu64.c
35
l = compress_bits(l >> odd, esz);
32
+++ b/target/arm/cpu64.c
36
h = compress_bits(h >> odd, esz);
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
37
- d[i] = l + (h << 32);
34
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
38
+ d[i] = l | (h << 32);
35
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
39
}
36
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
40
37
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
41
- /* For VL which is not a power of 2, the results from M do not
38
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
42
- align nicely with the uint64_t for D. Put the aligned results
39
cpu->isar.id_aa64isar1 = t;
43
- from M into TMP_M and then copy it into place afterward. */
40
44
+ /*
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
45
+ * For VL which is not a multiple of 512, the results from M do not
42
index XXXXXXX..XXXXXXX 100644
46
+ * align nicely with the uint64_t for D. Put the aligned results
43
--- a/target/arm/translate-a64.c
47
+ * from M into TMP_M and then copy it into place afterward.
44
+++ b/target/arm/translate-a64.c
48
+ */
45
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
49
if (oprsz & 15) {
46
break;
50
- d[i] = compress_bits(n[2 * i] >> odd, esz);
47
case 0b00100: /* SEV */
51
+ int final_shift = (oprsz & 15) * 2;
48
case 0b00101: /* SEVL */
52
+
49
+ case 0b00110: /* DGH */
53
+ l = n[2 * i + 0];
50
/* we treat all as NOP at least for now */
54
+ h = n[2 * i + 1];
51
break;
55
+ l = compress_bits(l >> odd, esz);
52
case 0b00111: /* XPACLRI */
56
+ h = compress_bits(h >> odd, esz);
57
+ d[i] = l | (h << final_shift);
58
59
for (i = 0; i < oprsz_16; i++) {
60
l = m[2 * i + 0];
61
h = m[2 * i + 1];
62
l = compress_bits(l >> odd, esz);
63
h = compress_bits(h >> odd, esz);
64
- tmp_m.p[i] = l + (h << 32);
65
+ tmp_m.p[i] = l | (h << 32);
66
}
67
- tmp_m.p[i] = compress_bits(m[2 * i] >> odd, esz);
68
+ l = m[2 * i + 0];
69
+ h = m[2 * i + 1];
70
+ l = compress_bits(l >> odd, esz);
71
+ h = compress_bits(h >> odd, esz);
72
+ tmp_m.p[i] = l | (h << final_shift);
73
74
swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2);
75
} else {
76
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
77
h = m[2 * i + 1];
78
l = compress_bits(l >> odd, esz);
79
h = compress_bits(h >> odd, esz);
80
- d[oprsz_16 + i] = l + (h << 32);
81
+ d[oprsz_16 + i] = l | (h << 32);
82
}
83
}
84
}
85
--
53
--
86
2.20.1
54
2.25.1
87
88
diff view generated by jsdifflib
[PULL 08/39] hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
[PULL 24/32] target/arm: Define cortex-a76
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL),
3
Enable the a76 for virt and sbsa board use.
4
@end overflows and we fail to handle the command properly.
5
4
6
Once this gets fixed, the current code really is awkward in the
7
sense it loops over the whole range instead of removing the
8
currently cached configs through a hash table lookup.
9
10
Fix both the overflow and the lookup.
11
12
Signed-off-by: Eric Auger <eric.auger@redhat.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210309102742.30442-7-eric.auger@redhat.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
9
---
17
hw/arm/smmu-internal.h | 5 +++++
10
docs/system/arm/virt.rst | 1 +
18
hw/arm/smmuv3.c | 34 ++++++++++++++++++++--------------
11
hw/arm/sbsa-ref.c | 1 +
19
2 files changed, 25 insertions(+), 14 deletions(-)
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
20
15
21
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/smmu-internal.h
18
--- a/docs/system/arm/virt.rst
24
+++ b/hw/arm/smmu-internal.h
19
+++ b/docs/system/arm/virt.rst
25
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo {
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
26
uint64_t mask;
21
- ``cortex-a53`` (64-bit)
27
} SMMUIOTLBPageInvInfo;
22
- ``cortex-a57`` (64-bit)
28
23
- ``cortex-a72`` (64-bit)
29
+typedef struct SMMUSIDRange {
24
+- ``cortex-a76`` (64-bit)
30
+ uint32_t start;
25
- ``a64fx`` (64-bit)
31
+ uint32_t end;
26
- ``host`` (with KVM only)
32
+} SMMUSIDRange;
27
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
33
static const char * const valid_cpus[] = {
34
ARM_CPU_TYPE_NAME("cortex-a57"),
35
ARM_CPU_TYPE_NAME("cortex-a72"),
36
+ ARM_CPU_TYPE_NAME("cortex-a76"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a53"),
46
ARM_CPU_TYPE_NAME("cortex-a57"),
47
ARM_CPU_TYPE_NAME("cortex-a72"),
48
+ ARM_CPU_TYPE_NAME("cortex-a76"),
49
ARM_CPU_TYPE_NAME("a64fx"),
50
ARM_CPU_TYPE_NAME("host"),
51
ARM_CPU_TYPE_NAME("max"),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
57
define_cortex_a72_a57_a53_cp_reginfo(cpu);
58
}
59
60
+static void aarch64_a76_initfn(Object *obj)
61
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
33
+
63
+
34
#endif
64
+ cpu->dtb_compatible = "arm,cortex-a76";
35
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
36
index XXXXXXX..XXXXXXX 100644
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
37
--- a/hw/arm/smmuv3.c
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
+++ b/hw/arm/smmuv3.c
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
@@ -XXX,XX +XXX,XX @@
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
41
#include "hw/arm/smmuv3.h"
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
42
#include "smmuv3-internal.h"
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
43
+#include "smmu-internal.h"
44
45
/**
46
* smmuv3_trigger_irq - pulse @irq if enabled and update
47
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
48
}
49
}
50
51
+static gboolean
52
+smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
53
+{
54
+ SMMUDevice *sdev = (SMMUDevice *)key;
55
+ uint32_t sid = smmu_get_sid(sdev);
56
+ SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
57
+
73
+
58
+ if (sid < sid_range->start || sid > sid_range->end) {
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
59
+ return false;
75
+ cpu->clidr = 0x82000023;
60
+ }
76
+ cpu->ctr = 0x8444C004;
61
+ trace_smmuv3_config_cache_inv(sid);
77
+ cpu->dcz_blocksize = 4;
62
+ return true;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0b1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.18 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
110
+
111
+ /* From B2.93 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
63
+}
123
+}
64
+
124
+
65
static int smmuv3_cmdq_consume(SMMUv3State *s)
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
66
{
126
{
67
SMMUState *bs = ARM_SMMU(s);
127
/*
68
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
69
}
129
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
70
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
130
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
71
{
131
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
72
- uint32_t start = CMD_SID(&cmd), end, i;
132
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
73
+ uint32_t start = CMD_SID(&cmd);
133
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
74
uint8_t range = CMD_STE_RANGE(&cmd);
134
{ .name = "max", .initfn = aarch64_max_initfn },
75
+ uint64_t end = start + (1ULL << (range + 1)) - 1;
135
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
76
+ SMMUSIDRange sid_range = {start, end};
77
78
if (CMD_SSEC(&cmd)) {
79
cmd_error = SMMU_CERROR_ILL;
80
break;
81
}
82
-
83
- end = start + (1 << (range + 1)) - 1;
84
trace_smmuv3_cmdq_cfgi_ste_range(start, end);
85
-
86
- for (i = start; i <= end; i++) {
87
- IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, i);
88
- SMMUDevice *sdev;
89
-
90
- if (!mr) {
91
- continue;
92
- }
93
- sdev = container_of(mr, SMMUDevice, iommu);
94
- smmuv3_flush_config(sdev);
95
- }
96
+ g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
97
+ &sid_range);
98
break;
99
}
100
case SMMU_CMD_CFGI_CD:
101
--
136
--
102
2.20.1
137
2.25.1
103
104
diff view generated by jsdifflib
[PULL 18/39] hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
[PULL 25/32] target/arm: Define neoverse-n1
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Currently the emulated EMAC for sun8i always traverses the transmit queue
3
Enable the n1 for virt and sbsa board use.
4
from the head when transferring packets. It searches for a list of consecutive
5
descriptors whichs are flagged as ready for processing and transmits their payloads
6
accordingly. The controller stops processing once it finds a descriptor that is not
7
marked ready.
8
4
9
While the above behaviour works in most situations, it is not the same as the actual
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
EMAC in hardware. Actual hardware uses the TX_CUR_DESC register value to keep track
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
of the last position in the transmit queue and continues processing from that position
7
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
12
when software triggers the start of DMA processing. The currently emulated behaviour can
13
lead to packet loss on transmit when software fills the transmit queue with ready
14
descriptors that overlap the tail of the circular list.
15
16
This commit modifies the emulated EMAC for sun8i such that it processes
17
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
18
19
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Message-id: 20210310195820.21950-2-nieklinnenbank@gmail.com
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
9
---
24
hw/net/allwinner-sun8i-emac.c | 62 +++++++++++++++++++----------------
10
docs/system/arm/virt.rst | 1 +
25
1 file changed, 34 insertions(+), 28 deletions(-)
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
26
15
27
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
28
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/net/allwinner-sun8i-emac.c
18
--- a/docs/system/arm/virt.rst
30
+++ b/hw/net/allwinner-sun8i-emac.c
19
+++ b/docs/system/arm/virt.rst
31
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
32
qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
21
- ``cortex-a76`` (64-bit)
22
- ``a64fx`` (64-bit)
23
- ``host`` (with KVM only)
24
+- ``neoverse-n1`` (64-bit)
25
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
26
27
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
33
ARM_CPU_TYPE_NAME("cortex-a57"),
34
ARM_CPU_TYPE_NAME("cortex-a72"),
35
ARM_CPU_TYPE_NAME("cortex-a76"),
36
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a72"),
46
ARM_CPU_TYPE_NAME("cortex-a76"),
47
ARM_CPU_TYPE_NAME("a64fx"),
48
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
49
ARM_CPU_TYPE_NAME("host"),
50
ARM_CPU_TYPE_NAME("max"),
51
};
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
57
cpu->isar.mvfr2 = 0x00000043;
33
}
58
}
34
59
35
-static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
60
+static void aarch64_neoverse_n1_initfn(Object *obj)
36
- FrameDescriptor *desc,
37
- size_t min_size)
38
+static bool allwinner_sun8i_emac_desc_owned(FrameDescriptor *desc,
39
+ size_t min_buf_size)
40
{
41
- uint32_t paddr = desc->next;
42
-
43
- dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
44
-
45
- if ((desc->status & DESC_STATUS_CTL) &&
46
- (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
47
- return paddr;
48
- } else {
49
- return 0;
50
- }
51
+ return (desc->status & DESC_STATUS_CTL) && (min_buf_size == 0 ||
52
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_buf_size);
53
}
54
55
-static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
56
- FrameDescriptor *desc,
57
- uint32_t start_addr,
58
- size_t min_size)
59
+static void allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
60
+ FrameDescriptor *desc,
61
+ uint32_t phys_addr)
62
+{
61
+{
63
+ dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc));
62
+ ARMCPU *cpu = ARM_CPU(obj);
63
+
64
+ cpu->dtb_compatible = "arm,neoverse-n1";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444c004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0c1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.23 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
110
+
111
+ /* From B2.98 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
64
+}
123
+}
65
+
124
+
66
+static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
67
+ FrameDescriptor *desc)
68
+{
69
+ const uint32_t nxt = desc->next;
70
+ allwinner_sun8i_emac_get_desc(s, desc, nxt);
71
+ return nxt;
72
+}
73
+
74
+static uint32_t allwinner_sun8i_emac_find_desc(AwSun8iEmacState *s,
75
+ FrameDescriptor *desc,
76
+ uint32_t start_addr,
77
+ size_t min_size)
78
{
126
{
79
uint32_t desc_addr = start_addr;
127
/*
80
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
81
/* Note that the list is a cycle. Last entry points back to the head. */
129
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
82
while (desc_addr != 0) {
130
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
83
- dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
131
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
84
+ allwinner_sun8i_emac_get_desc(s, desc, desc_addr);
132
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
85
133
{ .name = "max", .initfn = aarch64_max_initfn },
86
- if ((desc->status & DESC_STATUS_CTL) &&
134
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
87
- (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
135
{ .name = "host", .initfn = aarch64_host_initfn },
88
+ if (allwinner_sun8i_emac_desc_owned(desc, min_size)) {
89
return desc_addr;
90
} else if (desc->next == start_addr) {
91
break;
92
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
93
FrameDescriptor *desc,
94
size_t min_size)
95
{
96
- return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
97
+ return allwinner_sun8i_emac_find_desc(s, desc, s->rx_desc_curr, min_size);
98
}
99
100
static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
101
- FrameDescriptor *desc,
102
- size_t min_size)
103
+ FrameDescriptor *desc)
104
{
105
- return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
106
+ allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_curr);
107
+ return s->tx_desc_curr;
108
}
109
110
static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
111
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
112
bytes_left -= desc_bytes;
113
114
/* Move to the next descriptor */
115
- s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
116
+ s->rx_desc_curr = allwinner_sun8i_emac_find_desc(s, &desc, desc.next,
117
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
118
if (!s->rx_desc_curr) {
119
/* Not enough buffer space available */
120
s->int_sta |= INT_STA_RX_BUF_UA;
121
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
122
size_t transmitted = 0;
123
static uint8_t packet_buf[2048];
124
125
- s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
126
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc);
127
128
/* Read all transmit descriptors */
129
- while (s->tx_desc_curr != 0) {
130
+ while (allwinner_sun8i_emac_desc_owned(&desc, 0)) {
131
132
/* Read from physical memory into packet buffer */
133
bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
134
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
135
packet_bytes = 0;
136
transmitted++;
137
}
138
- s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
139
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc);
140
}
141
142
/* Raise transmit completed interrupt */
143
--
136
--
144
2.20.1
137
2.25.1
145
146
diff view generated by jsdifflib
[PULL 06/39] hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
If the asid is not set, do not attempt to locate the key directly
3
The sbsa-ref machine is continuously evolving. Some of the changes we
4
as all inserted keys have a valid asid.
4
want to make in the near future, to align with real components (e.g.
5
the GIC-700), will break compatibility for existing firmware.
5
6
6
Use g_hash_table_foreach_remove instead.
7
Introduce two new properties to the DT generated on machine generation:
8
- machine-version-major
9
To be incremented when a platform change makes the machine
10
incompatible with existing firmware.
11
- machine-version-minor
12
To be incremented when functionality is added to the machine
13
without causing incompatibility with existing firmware.
14
to be reset to 0 when machine-version-major is incremented.
7
15
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
16
This versioning scheme is *neither*:
9
Message-id: 20210309102742.30442-5-eric.auger@redhat.com
17
- A QEMU versioned machine type; a given version of QEMU will emulate
18
a given version of the platform.
19
- A reflection of level of SBSA (now SystemReady SR) support provided.
20
21
The version will increment on guest-visible functional changes only,
22
akin to a revision ID register found on a physical platform.
23
24
These properties are both introduced with the value 0.
25
(Hence, a machine where the DT is lacking these nodes is equivalent
26
to version 0.0.)
27
28
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
29
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
30
Cc: Peter Maydell <peter.maydell@linaro.org>
31
Cc: Radoslaw Biernacki <rad@semihalf.com>
32
Cc: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
35
---
13
hw/arm/smmu-common.c | 2 +-
36
hw/arm/sbsa-ref.c | 14 ++++++++++++++
14
1 file changed, 1 insertion(+), 1 deletion(-)
37
1 file changed, 14 insertions(+)
15
38
16
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
39
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
17
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/smmu-common.c
41
--- a/hw/arm/sbsa-ref.c
19
+++ b/hw/arm/smmu-common.c
42
+++ b/hw/arm/sbsa-ref.c
20
@@ -XXX,XX +XXX,XX @@ inline void
43
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
21
smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
44
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
22
uint8_t tg, uint64_t num_pages, uint8_t ttl)
45
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
23
{
46
24
- if (ttl && (num_pages == 1)) {
47
+ /*
25
+ if (ttl && (num_pages == 1) && (asid >= 0)) {
48
+ * This versioning scheme is for informing platform fw only. It is neither:
26
SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
49
+ * - A QEMU versioned machine type; a given version of QEMU will emulate
27
50
+ * a given version of the platform.
28
g_hash_table_remove(s->iotlb, &key);
51
+ * - A reflection of level of SBSA (now SystemReady SR) support provided.
52
+ *
53
+ * machine-version-major: updated when changes breaking fw compatibility
54
+ * are introduced.
55
+ * machine-version-minor: updated when features are added that don't break
56
+ * fw compatibility.
57
+ */
58
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
59
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
60
+
61
if (ms->numa_state->have_numa_distance) {
62
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
63
uint32_t *matrix = g_malloc0(size);
29
--
64
--
30
2.20.1
65
2.25.1
31
66
32
67
diff view generated by jsdifflib
[PULL 07/39] hw/arm/smmuv3: Enforce invalidation on a power of two range
[PULL 27/32] qapi/machine.json: Add cluster-id
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
As of today, the driver can invalidate a number of pages that is
3
This adds cluster-id in CPU instance properties, which will be used
4
not a power of 2. However IOTLB unmap notifications and internal
4
by arm/virt machine. Besides, the cluster-id is also verified or
5
IOTLB invalidations work with masks leading to erroneous
5
dumped in various spots:
6
invalidations.
7
6
8
In case the range is not a power of 2, split invalidations into
7
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
9
power of 2 invalidations.
8
CPU with its NUMA node.
10
9
11
When looking for a single page entry in the vSMMU internal IOTLB,
10
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
12
let's make sure that if the entry is not found using a
11
CPU slots with no NUMA mapping set.
13
g_hash_table_remove() we iterate over all the entries to find a
14
potential range that overlaps it.
15
12
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
13
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
17
Message-id: 20210309102742.30442-6-eric.auger@redhat.com
14
cluster-id.
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
18
Acked-by: Igor Mammedov <imammedo@redhat.com>
19
Message-id: 20220503140304.855514-2-gshan@redhat.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
---
21
hw/arm/smmu-common.c | 30 ++++++++++++++++++------------
22
qapi/machine.json | 6 ++++--
22
hw/arm/smmuv3.c | 24 ++++++++++++++++++++----
23
hw/core/machine-hmp-cmds.c | 4 ++++
23
2 files changed, 38 insertions(+), 16 deletions(-)
24
hw/core/machine.c | 16 ++++++++++++++++
25
3 files changed, 24 insertions(+), 2 deletions(-)
24
26
25
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
27
diff --git a/qapi/machine.json b/qapi/machine.json
26
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/smmu-common.c
29
--- a/qapi/machine.json
28
+++ b/hw/arm/smmu-common.c
30
+++ b/qapi/machine.json
29
@@ -XXX,XX +XXX,XX @@ inline void
31
@@ -XXX,XX +XXX,XX @@
30
smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
32
# @node-id: NUMA node ID the CPU belongs to
31
uint8_t tg, uint64_t num_pages, uint8_t ttl)
33
# @socket-id: socket number within node/board the CPU belongs to
32
{
34
# @die-id: die number within socket the CPU belongs to (since 4.1)
33
+ /* if tg is not set we use 4KB range invalidation */
35
-# @core-id: core number within die the CPU belongs to
34
+ uint8_t granule = tg ? tg * 2 + 10 : 12;
36
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
35
+
37
+# @core-id: core number within cluster the CPU belongs to
36
if (ttl && (num_pages == 1) && (asid >= 0)) {
38
# @thread-id: thread number within core the CPU belongs to
37
SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
39
#
38
40
-# Note: currently there are 5 properties that could be present
39
- g_hash_table_remove(s->iotlb, &key);
41
+# Note: currently there are 6 properties that could be present
40
- } else {
42
# but management should be prepared to pass through other
41
- /* if tg is not set we use 4KB range invalidation */
43
# properties with device_add command to allow for future
42
- uint8_t granule = tg ? tg * 2 + 10 : 12;
44
# interface extension. This also requires the filed names to be kept in
43
-
45
@@ -XXX,XX +XXX,XX @@
44
- SMMUIOTLBPageInvInfo info = {
46
'data': { '*node-id': 'int',
45
- .asid = asid, .iova = iova,
47
'*socket-id': 'int',
46
- .mask = (num_pages * 1 << granule) - 1};
48
'*die-id': 'int',
47
-
49
+ '*cluster-id': 'int',
48
- g_hash_table_foreach_remove(s->iotlb,
50
'*core-id': 'int',
49
- smmu_hash_remove_by_asid_iova,
51
'*thread-id': 'int'
50
- &info);
52
}
51
+ if (g_hash_table_remove(s->iotlb, &key)) {
53
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/machine-hmp-cmds.c
56
+++ b/hw/core/machine-hmp-cmds.c
57
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
58
if (c->has_die_id) {
59
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
60
}
61
+ if (c->has_cluster_id) {
62
+ monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n",
63
+ c->cluster_id);
64
+ }
65
if (c->has_core_id) {
66
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
67
}
68
diff --git a/hw/core/machine.c b/hw/core/machine.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/core/machine.c
71
+++ b/hw/core/machine.c
72
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
73
return;
74
}
75
76
+ if (props->has_cluster_id && !slot->props.has_cluster_id) {
77
+ error_setg(errp, "cluster-id is not supported");
52
+ return;
78
+ return;
53
+ }
79
+ }
54
+ /*
80
+
55
+ * if the entry is not found, let's see if it does not
81
if (props->has_socket_id && !slot->props.has_socket_id) {
56
+ * belong to a larger IOTLB entry
82
error_setg(errp, "socket-id is not supported");
57
+ */
83
return;
84
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
85
continue;
86
}
87
88
+ if (props->has_cluster_id &&
89
+ props->cluster_id != slot->props.cluster_id) {
90
+ continue;
91
+ }
92
+
93
if (props->has_die_id && props->die_id != slot->props.die_id) {
94
continue;
95
}
96
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
97
}
98
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
58
}
99
}
59
+
100
+ if (cpu->props.has_cluster_id) {
60
+ SMMUIOTLBPageInvInfo info = {
101
+ if (s->len) {
61
+ .asid = asid, .iova = iova,
102
+ g_string_append_printf(s, ", ");
62
+ .mask = (num_pages * 1 << granule) - 1};
103
+ }
63
+
104
+ g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
64
+ g_hash_table_foreach_remove(s->iotlb,
65
+ smmu_hash_remove_by_asid_iova,
66
+ &info);
67
}
68
69
inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
70
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/smmuv3.c
73
+++ b/hw/arm/smmuv3.c
74
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
75
uint16_t vmid = CMD_VMID(cmd);
76
bool leaf = CMD_LEAF(cmd);
77
uint8_t tg = CMD_TG(cmd);
78
- hwaddr num_pages = 1;
79
+ uint64_t first_page = 0, last_page;
80
+ uint64_t num_pages = 1;
81
int asid = -1;
82
83
if (tg) {
84
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
85
if (type == SMMU_CMD_TLBI_NH_VA) {
86
asid = CMD_ASID(cmd);
87
}
88
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
89
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
90
- smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
91
+
92
+ /* Split invalidations into ^2 range invalidations */
93
+ last_page = num_pages - 1;
94
+ while (num_pages) {
95
+ uint8_t granule = tg * 2 + 10;
96
+ uint64_t mask, count;
97
+
98
+ mask = dma_aligned_pow2_mask(first_page, last_page, 64 - granule);
99
+ count = mask + 1;
100
+
101
+ trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, count, ttl, leaf);
102
+ smmuv3_inv_notifiers_iova(s, asid, addr, tg, count);
103
+ smmu_iotlb_inv_iova(s, asid, addr, tg, count, ttl);
104
+
105
+ num_pages -= count;
106
+ first_page += count;
107
+ addr += count * BIT_ULL(granule);
108
+ }
105
+ }
109
}
106
if (cpu->props.has_core_id) {
110
107
if (s->len) {
111
static int smmuv3_cmdq_consume(SMMUv3State *s)
108
g_string_append_printf(s, ", ");
112
--
109
--
113
2.20.1
110
2.25.1
114
115
diff view generated by jsdifflib
[PULL 22/39] tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
Previously the ARMBIAN_ARTIFACTS_CACHED pre-condition was added to allow running
3
The CPU topology isn't enabled on arm/virt machine yet, but we're
4
tests that have already existing armbian.com artifacts stored in the local avocado cache,
4
going to do it in next patch. After the CPU topology is enabled by
5
but do not have working URLs to download a fresh copy.
5
next patch, "thread-id=1" becomes invalid because the CPU core is
6
preferred on arm/virt machine. It means these two CPUs have 0/1
7
as their core IDs, but their thread IDs are all 0. It will trigger
8
test failure as the following message indicates:
6
9
7
At this time of writing the URLs for artifacts on the armbian.com server are updated and working.
10
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
8
Any future broken URLs will result in a skipped acceptance test, for example:
11
1.48s killed by signal 6 SIGABRT
12
>>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
13
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \
14
QTEST_QEMU_BINARY=./qemu-system-aarch64 \
15
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \
16
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
17
――――――――――――――――――――――――――――――――――――――――――――――
18
stderr:
19
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
9
20
10
(1/5) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
21
This fixes the issue by providing comprehensive SMP configurations
11
CANCEL: Missing asset https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb (0.53 s)
22
in aarch64_numa_cpu(). The SMP configurations aren't used before
23
the CPU topology is enabled in next patch.
12
24
13
This commits removes the ARMBIAN_ARTIFACTS_CACHED pre-condition such that
25
Signed-off-by: Gavin Shan <gshan@redhat.com>
14
the acceptance tests for the orangepi-pc and cubieboard machines can run.
26
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
15
27
Message-id: 20220503140304.855514-3-gshan@redhat.com
16
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
17
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
18
Message-id: 20210310195820.21950-6-nieklinnenbank@gmail.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
29
---
21
tests/acceptance/boot_linux_console.py | 12 ------------
30
tests/qtest/numa-test.c | 3 ++-
22
tests/acceptance/replay_kernel.py | 2 --
31
1 file changed, 2 insertions(+), 1 deletion(-)
23
2 files changed, 14 deletions(-)
24
32
25
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
33
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
26
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/acceptance/boot_linux_console.py
35
--- a/tests/qtest/numa-test.c
28
+++ b/tests/acceptance/boot_linux_console.py
36
+++ b/tests/qtest/numa-test.c
29
@@ -XXX,XX +XXX,XX @@ def test_arm_exynos4210_initrd(self):
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
30
self.wait_for_console_pattern('Boot successful.')
38
QTestState *qts;
31
# TODO user command, for now the uart is stuck
39
g_autofree char *cli = NULL;
32
40
33
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
41
- cli = make_cli(data, "-machine smp.cpus=2 "
34
- 'Test artifacts fetched from unreliable apt.armbian.com')
42
+ cli = make_cli(data, "-machine "
35
def test_arm_cubieboard_initrd(self):
43
+ "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
36
"""
44
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
37
:avocado: tags=arch:arm
45
"-numa cpu,node-id=1,thread-id=0 "
38
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
46
"-numa cpu,node-id=0,thread-id=1");
39
'system-control@1c00000')
40
# cubieboard's reboot is not functioning; omit reboot test.
41
42
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
43
- 'Test artifacts fetched from unreliable apt.armbian.com')
44
def test_arm_cubieboard_sata(self):
45
"""
46
:avocado: tags=arch:arm
47
@@ -XXX,XX +XXX,XX @@ def test_arm_quanta_gsj_initrd(self):
48
self.wait_for_console_pattern(
49
'Give root password for system maintenance')
50
51
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
52
- 'Test artifacts fetched from unreliable apt.armbian.com')
53
def test_arm_orangepi(self):
54
"""
55
:avocado: tags=arch:arm
56
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
57
console_pattern = 'Kernel command line: %s' % kernel_command_line
58
self.wait_for_console_pattern(console_pattern)
59
60
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
61
- 'Test artifacts fetched from unreliable apt.armbian.com')
62
def test_arm_orangepi_initrd(self):
63
"""
64
:avocado: tags=arch:arm
65
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
66
# Wait for VM to shut down gracefully
67
self.vm.wait()
68
69
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
70
- 'Test artifacts fetched from unreliable apt.armbian.com')
71
def test_arm_orangepi_sd(self):
72
"""
73
:avocado: tags=arch:arm
74
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
75
# Wait for VM to shut down gracefully
76
self.vm.wait()
77
78
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
79
- 'Test artifacts fetched from unreliable apt.armbian.com')
80
@skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
81
def test_arm_orangepi_bionic_20_08(self):
82
"""
83
diff --git a/tests/acceptance/replay_kernel.py b/tests/acceptance/replay_kernel.py
84
index XXXXXXX..XXXXXXX 100644
85
--- a/tests/acceptance/replay_kernel.py
86
+++ b/tests/acceptance/replay_kernel.py
87
@@ -XXX,XX +XXX,XX @@ def test_arm_virt(self):
88
self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=1)
89
90
@skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
91
- @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
92
- 'Test artifacts fetched from unreliable apt.armbian.com')
93
def test_arm_cubieboard_initrd(self):
94
"""
95
:avocado: tags=arch:arm
96
--
47
--
97
2.20.1
48
2.25.1
98
49
99
50
diff view generated by jsdifflib
[PULL 21/39] tests/acceptance: update sunxi kernel from armbian to 5.10.16
[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
The linux kernel 4.20.7 binary for sunxi has been removed from apt.armbian.com:
3
Currently, the SMP configuration isn't considered when the CPU
4
topology is populated. In this case, it's impossible to provide
5
the default CPU-to-NUMA mapping or association based on the socket
6
ID of the given CPU.
4
7
5
$ ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
8
This takes account of SMP configuration when the CPU topology
6
Fetching asset from tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi
9
is populated. The die ID for the given CPU isn't assigned since
7
...
10
it's not supported on arm/virt machine. Besides, the used SMP
8
(1/6) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
11
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
9
CANCEL: Missing asset https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb (0.55 s)
12
to avoid testing failure
10
13
11
This commit updates the sunxi kernel to 5.10.16 for the acceptance
14
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
tests of the orangepi-pc and cubieboard machines.
15
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
13
16
Acked-by: Igor Mammedov <imammedo@redhat.com>
14
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
17
Message-id: 20220503140304.855514-4-gshan@redhat.com
15
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
16
Message-id: 20210310195820.21950-5-nieklinnenbank@gmail.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
---
19
tests/acceptance/boot_linux_console.py | 40 +++++++++++++-------------
20
hw/arm/virt.c | 15 ++++++++++++++-
20
tests/acceptance/replay_kernel.py | 8 +++---
21
1 file changed, 14 insertions(+), 1 deletion(-)
21
2 files changed, 24 insertions(+), 24 deletions(-)
22
22
23
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tests/acceptance/boot_linux_console.py
25
--- a/hw/arm/virt.c
26
+++ b/tests/acceptance/boot_linux_console.py
26
+++ b/hw/arm/virt.c
27
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
27
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
28
:avocado: tags=machine:cubieboard
28
int n;
29
"""
29
unsigned int max_cpus = ms->smp.max_cpus;
30
deb_url = ('https://apt.armbian.com/pool/main/l/'
30
VirtMachineState *vms = VIRT_MACHINE(ms);
31
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
31
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
32
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
32
33
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
33
if (ms->possible_cpus) {
34
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
34
assert(ms->possible_cpus->len == max_cpus);
35
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
36
kernel_path = self.extract_from_deb(deb_path,
36
ms->possible_cpus->cpus[n].type = ms->cpu_type;
37
- '/boot/vmlinuz-4.20.7-sunxi')
37
ms->possible_cpus->cpus[n].arch_id =
38
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
38
virt_cpu_mp_affinity(vms, n);
39
+ '/boot/vmlinuz-5.10.16-sunxi')
39
+
40
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
40
+ assert(!mc->smp_props.dies_supported);
41
dtb_path = self.extract_from_deb(deb_path, dtb_path)
41
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
42
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
42
+ ms->possible_cpus->cpus[n].props.socket_id =
43
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
43
+ n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
44
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
44
+ ms->possible_cpus->cpus[n].props.has_cluster_id = true;
45
:avocado: tags=machine:cubieboard
45
+ ms->possible_cpus->cpus[n].props.cluster_id =
46
"""
46
+ (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
47
deb_url = ('https://apt.armbian.com/pool/main/l/'
47
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
48
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
48
+ ms->possible_cpus->cpus[n].props.core_id =
49
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
49
+ (n / ms->smp.threads) % ms->smp.cores;
50
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
50
ms->possible_cpus->cpus[n].props.has_thread_id = true;
51
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
51
- ms->possible_cpus->cpus[n].props.thread_id = n;
52
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
52
+ ms->possible_cpus->cpus[n].props.thread_id =
53
kernel_path = self.extract_from_deb(deb_path,
53
+ n % ms->smp.threads;
54
- '/boot/vmlinuz-4.20.7-sunxi')
54
}
55
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
55
return ms->possible_cpus;
56
+ '/boot/vmlinuz-5.10.16-sunxi')
56
}
57
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
58
dtb_path = self.extract_from_deb(deb_path, dtb_path)
59
rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
60
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
61
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
62
:avocado: tags=machine:orangepi-pc
63
"""
64
deb_url = ('https://apt.armbian.com/pool/main/l/'
65
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
66
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
67
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
68
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
69
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
70
kernel_path = self.extract_from_deb(deb_path,
71
- '/boot/vmlinuz-4.20.7-sunxi')
72
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
73
+ '/boot/vmlinuz-5.10.16-sunxi')
74
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
75
dtb_path = self.extract_from_deb(deb_path, dtb_path)
76
77
self.vm.set_console()
78
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
79
:avocado: tags=machine:orangepi-pc
80
"""
81
deb_url = ('https://apt.armbian.com/pool/main/l/'
82
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
83
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
84
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
85
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
86
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
87
kernel_path = self.extract_from_deb(deb_path,
88
- '/boot/vmlinuz-4.20.7-sunxi')
89
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
90
+ '/boot/vmlinuz-5.10.16-sunxi')
91
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
92
dtb_path = self.extract_from_deb(deb_path, dtb_path)
93
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
94
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
95
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
96
:avocado: tags=device:sd
97
"""
98
deb_url = ('https://apt.armbian.com/pool/main/l/'
99
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
100
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
101
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
102
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
103
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
104
kernel_path = self.extract_from_deb(deb_path,
105
- '/boot/vmlinuz-4.20.7-sunxi')
106
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
107
+ '/boot/vmlinuz-5.10.16-sunxi')
108
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
109
dtb_path = self.extract_from_deb(deb_path, dtb_path)
110
rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
111
'kci-2019.02/armel/base/rootfs.ext2.xz')
112
diff --git a/tests/acceptance/replay_kernel.py b/tests/acceptance/replay_kernel.py
113
index XXXXXXX..XXXXXXX 100644
114
--- a/tests/acceptance/replay_kernel.py
115
+++ b/tests/acceptance/replay_kernel.py
116
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
117
:avocado: tags=machine:cubieboard
118
"""
119
deb_url = ('https://apt.armbian.com/pool/main/l/'
120
- 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
121
- deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
122
+ 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
123
+ deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
124
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
125
kernel_path = self.extract_from_deb(deb_path,
126
- '/boot/vmlinuz-4.20.7-sunxi')
127
- dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
128
+ '/boot/vmlinuz-5.10.16-sunxi')
129
+ dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
130
dtb_path = self.extract_from_deb(deb_path, dtb_path)
131
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
132
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
133
--
57
--
134
2.20.1
58
2.25.1
135
136
diff view generated by jsdifflib
[PULL 20/39] tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
Update the download URL of the Armbian 20.08 Bionic image for
3
In aarch64_numa_cpu(), the CPU and NUMA association is something
4
test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.
4
like below. Two threads in the same core/cluster/socket are
5
associated with two individual NUMA nodes, which is unreal as
6
Igor Mammedov mentioned. We don't expect the association to break
7
NUMA-to-socket boundary, which matches with the real world.
5
8
6
The archive.armbian.com URL contains more images and should keep stable
9
NUMA-node socket cluster core thread
7
for a longer period of time than dl.armbian.com.
10
------------------------------------------
11
0 0 0 0 0
12
1 0 0 0 1
8
13
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
This corrects the topology for CPUs and their association with
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
NUMA nodes. After this patch is applied, the CPU and NUMA
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
association becomes something like below, which looks real.
12
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
17
Besides, socket/cluster/core/thread IDs are all checked when
13
Message-id: 20210310195820.21950-4-nieklinnenbank@gmail.com
18
the NUMA node IDs are verified. It helps to check if the CPU
19
topology is properly populated or not.
20
21
NUMA-node socket cluster core thread
22
------------------------------------------
23
0 1 0 0 0
24
1 0 0 0 0
25
26
Suggested-by: Igor Mammedov <imammedo@redhat.com>
27
Signed-off-by: Gavin Shan <gshan@redhat.com>
28
Acked-by: Igor Mammedov <imammedo@redhat.com>
29
Message-id: 20220503140304.855514-5-gshan@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
31
---
16
tests/acceptance/boot_linux_console.py | 2 +-
32
tests/qtest/numa-test.c | 18 ++++++++++++------
17
1 file changed, 1 insertion(+), 1 deletion(-)
33
1 file changed, 12 insertions(+), 6 deletions(-)
18
34
19
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
35
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
20
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/acceptance/boot_linux_console.py
37
--- a/tests/qtest/numa-test.c
22
+++ b/tests/acceptance/boot_linux_console.py
38
+++ b/tests/qtest/numa-test.c
23
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_bionic_20_08(self):
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
24
# to 1036 MiB, but the underlying filesystem is 1552 MiB...
40
g_autofree char *cli = NULL;
25
# As we expand it to 2 GiB we are safe.
41
26
42
cli = make_cli(data, "-machine "
27
- image_url = ('https://dl.armbian.com/orangepipc/archive/'
43
- "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
28
+ image_url = ('https://archive.armbian.com/orangepipc/archive/'
44
+ "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
29
'Armbian_20.08.1_Orangepipc_bionic_current_5.8.5.img.xz')
45
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
30
image_hash = ('b4d6775f5673486329e45a0586bf06b6'
46
- "-numa cpu,node-id=1,thread-id=0 "
31
'dbe792199fd182ac6b9c7bb6c7d3e6dd')
47
- "-numa cpu,node-id=0,thread-id=1");
48
+ "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
49
+ "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
50
qts = qtest_init(cli);
51
cpus = get_cpus(qts, &resp);
52
g_assert(cpus);
53
54
while ((e = qlist_pop(cpus))) {
55
QDict *cpu, *props;
56
- int64_t thread, node;
57
+ int64_t socket, cluster, core, thread, node;
58
59
cpu = qobject_to(QDict, e);
60
g_assert(qdict_haskey(cpu, "props"));
61
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
62
63
g_assert(qdict_haskey(props, "node-id"));
64
node = qdict_get_int(props, "node-id");
65
+ g_assert(qdict_haskey(props, "socket-id"));
66
+ socket = qdict_get_int(props, "socket-id");
67
+ g_assert(qdict_haskey(props, "cluster-id"));
68
+ cluster = qdict_get_int(props, "cluster-id");
69
+ g_assert(qdict_haskey(props, "core-id"));
70
+ core = qdict_get_int(props, "core-id");
71
g_assert(qdict_haskey(props, "thread-id"));
72
thread = qdict_get_int(props, "thread-id");
73
74
- if (thread == 0) {
75
+ if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
76
g_assert_cmpint(node, ==, 1);
77
- } else if (thread == 1) {
78
+ } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
79
g_assert_cmpint(node, ==, 0);
80
} else {
81
g_assert(false);
32
--
82
--
33
2.20.1
83
2.25.1
34
35
diff view generated by jsdifflib
[PULL 25/39] hw/arm/virt: KVM: The IPA lower bound is 32
[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
1
From: Andrew Jones <drjones@redhat.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
The virt machine already checks KVM_CAP_ARM_VM_IPA_SIZE to get the
3
When CPU-to-NUMA association isn't explicitly provided by users,
4
upper bound of the IPA size. If that bound is lower than the highest
4
the default one is given by mc->get_default_cpu_node_id(). However,
5
possible GPA for the machine, then QEMU will error out. However, the
5
the CPU topology isn't fully considered in the default association
6
IPA is set to 40 when the highest GPA is less than or equal to 40,
6
and this causes CPU topology broken warnings on booting Linux guest.
7
even when KVM may support an IPA limit as low as 32. This means KVM
8
may fail the VM creation unnecessarily. Additionally, 40 is selected
9
with the value 0, which means use the default, and that gets around
10
a check in some versions of KVM, causing a difficult to debug fail.
11
Always use the IPA size that corresponds to the highest possible GPA,
12
unless it's lower than 32, in which case use 32. Also, we must still
13
use 0 when KVM only supports the legacy fixed 40 bit IPA.
14
7
15
Suggested-by: Marc Zyngier <maz@kernel.org>
8
For example, the following warning messages are observed when the
16
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Linux guest is booted with the following command lines.
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
18
Reviewed-by: Marc Zyngier <maz@kernel.org>
11
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
19
Message-id: 20210310135218.255205-3-drjones@redhat.com
12
-accel kvm -machine virt,gic-version=host \
13
-cpu host \
14
-smp 6,sockets=2,cores=3,threads=1 \
15
-m 1024M,slots=16,maxmem=64G \
16
-object memory-backend-ram,id=mem0,size=128M \
17
-object memory-backend-ram,id=mem1,size=128M \
18
-object memory-backend-ram,id=mem2,size=128M \
19
-object memory-backend-ram,id=mem3,size=128M \
20
-object memory-backend-ram,id=mem4,size=128M \
21
-object memory-backend-ram,id=mem4,size=384M \
22
-numa node,nodeid=0,memdev=mem0 \
23
-numa node,nodeid=1,memdev=mem1 \
24
-numa node,nodeid=2,memdev=mem2 \
25
-numa node,nodeid=3,memdev=mem3 \
26
-numa node,nodeid=4,memdev=mem4 \
27
-numa node,nodeid=5,memdev=mem5
28
:
29
alternatives: patching kernel code
30
BUG: arch topology borken
31
the CLS domain not a subset of the MC domain
32
<the above error log repeats>
33
BUG: arch topology borken
34
the DIE domain not a subset of the NODE domain
35
36
With current implementation of mc->get_default_cpu_node_id(),
37
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
38
That's incorrect because CPU#0/1/2 should be associated with same
39
NUMA node because they're seated in same socket.
40
41
This fixes the issue by considering the socket ID when the default
42
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
43
With this applied, no more CPU topology broken warnings are seen
44
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
45
there are no CPUs associated with NODE#2/3/4/5.
46
47
Signed-off-by: Gavin Shan <gshan@redhat.com>
48
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
49
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
50
Message-id: 20220503140304.855514-6-gshan@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
52
---
22
target/arm/kvm_arm.h | 6 ++++--
53
hw/arm/virt.c | 4 +++-
23
hw/arm/virt.c | 23 ++++++++++++++++-------
54
1 file changed, 3 insertions(+), 1 deletion(-)
24
target/arm/kvm.c | 4 +++-
25
3 files changed, 23 insertions(+), 10 deletions(-)
26
55
27
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/kvm_arm.h
30
+++ b/target/arm/kvm_arm.h
31
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void);
32
/**
33
* kvm_arm_get_max_vm_ipa_size:
34
* @ms: Machine state handle
35
+ * @fixed_ipa: True when the IPA limit is fixed at 40. This is the case
36
+ * for legacy KVM.
37
*
38
* Returns the number of bits in the IPA address space supported by KVM
39
*/
40
-int kvm_arm_get_max_vm_ipa_size(MachineState *ms);
41
+int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa);
42
43
/**
44
* kvm_arm_sync_mpstate_to_kvm:
45
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_add_vcpu_properties(Object *obj)
46
g_assert_not_reached();
47
}
48
49
-static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
50
+static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa)
51
{
52
g_assert_not_reached();
53
}
54
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
56
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
55
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/virt.c
58
--- a/hw/arm/virt.c
57
+++ b/hw/arm/virt.c
59
+++ b/hw/arm/virt.c
58
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
60
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
59
static int virt_kvm_type(MachineState *ms, const char *type_str)
61
62
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
60
{
63
{
61
VirtMachineState *vms = VIRT_MACHINE(ms);
64
- return idx % ms->numa_state->num_nodes;
62
- int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
65
+ int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
63
- int requested_pa_size;
64
+ int max_vm_pa_size, requested_pa_size;
65
+ bool fixed_ipa;
66
+
66
+
67
+ max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
67
+ return socket_id % ms->numa_state->num_nodes;
68
69
/* we freeze the memory map to compute the highest gpa */
70
virt_set_memmap(vms);
71
72
requested_pa_size = 64 - clz64(vms->highest_gpa);
73
74
+ /*
75
+ * KVM requires the IPA size to be at least 32 bits.
76
+ */
77
+ if (requested_pa_size < 32) {
78
+ requested_pa_size = 32;
79
+ }
80
+
81
if (requested_pa_size > max_vm_pa_size) {
82
error_report("-m and ,maxmem option values "
83
"require an IPA range (%d bits) larger than "
84
"the one supported by the host (%d bits)",
85
requested_pa_size, max_vm_pa_size);
86
- exit(1);
87
+ exit(1);
88
}
89
/*
90
- * By default we return 0 which corresponds to an implicit legacy
91
- * 40b IPA setting. Otherwise we return the actual requested PA
92
- * logsize
93
+ * We return the requested PA log size, unless KVM only supports
94
+ * the implicit legacy 40b IPA setting, in which case the kvm_type
95
+ * must be 0.
96
*/
97
- return requested_pa_size > 40 ? requested_pa_size : 0;
98
+ return fixed_ipa ? 0 : requested_pa_size;
99
}
68
}
100
69
101
static void virt_machine_class_init(ObjectClass *oc, void *data)
70
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
102
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/kvm.c
105
+++ b/target/arm/kvm.c
106
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(void)
107
return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3);
108
}
109
110
-int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
111
+int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa)
112
{
113
KVMState *s = KVM_STATE(ms->accelerator);
114
int ret;
115
116
ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE);
117
+ *fixed_ipa = ret <= 0;
118
+
119
return ret > 0 ? ret : 40;
120
}
121
122
--
71
--
123
2.20.1
72
2.25.1
124
125
diff view generated by jsdifflib
[PULL 31/39] hw/display/pl110: Remove dead code for non-32-bpp surfaces
[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
1
For a long time now the UI layer has guaranteed that the console
1
From: Gavin Shan <gshan@redhat.com>
2
surface is always 32 bits per pixel. Remove the legacy dead
3
code from the pl110 display device which was handling the
4
possibility that the console surface was some other format.
5
2
3
When the PPTT table is built, the CPU topology is re-calculated, but
4
it's unecessary because the CPU topology has been populated in
5
virt_possible_cpu_arch_ids() on arm/virt machine.
6
7
This reworks build_pptt() to avoid by reusing the existing IDs in
8
ms->possible_cpus. Currently, the only user of build_pptt() is
9
arm/virt machine.
10
11
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
Tested-by: Yanan Wang <wangyanan55@huawei.com>
13
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
14
Acked-by: Igor Mammedov <imammedo@redhat.com>
15
Acked-by: Michael S. Tsirkin <mst@redhat.com>
16
Message-id: 20220503140304.855514-7-gshan@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
8
Message-id: 20210211141515.8755-2-peter.maydell@linaro.org
9
---
18
---
10
hw/display/pl110.c | 53 +++++++---------------------------------------
19
hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
11
1 file changed, 8 insertions(+), 45 deletions(-)
20
1 file changed, 48 insertions(+), 63 deletions(-)
12
21
13
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
22
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/display/pl110.c
24
--- a/hw/acpi/aml-build.c
16
+++ b/hw/display/pl110.c
25
+++ b/hw/acpi/aml-build.c
17
@@ -XXX,XX +XXX,XX @@ static const unsigned char *idregs[] = {
26
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
18
pl111_id
27
const char *oem_id, const char *oem_table_id)
19
};
28
{
20
29
MachineClass *mc = MACHINE_GET_CLASS(ms);
21
-#define BITS 8
30
- GQueue *list = g_queue_new();
22
-#include "pl110_template.h"
31
- guint pptt_start = table_data->len;
23
-#define BITS 15
32
- guint parent_offset;
24
-#include "pl110_template.h"
33
- guint length, i;
25
-#define BITS 16
34
- int uid = 0;
26
-#include "pl110_template.h"
35
- int socket;
27
-#define BITS 24
36
+ CPUArchIdList *cpus = ms->possible_cpus;
28
-#include "pl110_template.h"
37
+ int64_t socket_id = -1, cluster_id = -1, core_id = -1;
29
#define BITS 32
38
+ uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
30
#include "pl110_template.h"
39
+ uint32_t pptt_start = table_data->len;
31
40
+ int n;
32
@@ -XXX,XX +XXX,XX @@ static void pl110_update_display(void *opaque)
41
AcpiTable table = { .sig = "PPTT", .rev = 2,
33
PL110State *s = (PL110State *)opaque;
42
.oem_id = oem_id, .oem_table_id = oem_table_id };
34
SysBusDevice *sbd;
43
35
DisplaySurface *surface = qemu_console_surface(s->con);
44
acpi_table_begin(&table, table_data);
36
- drawfn* fntable;
45
37
drawfn fn;
46
- for (socket = 0; socket < ms->smp.sockets; socket++) {
38
- int dest_width;
47
- g_queue_push_tail(list,
39
int src_width;
48
- GUINT_TO_POINTER(table_data->len - pptt_start));
40
int bpp_offset;
49
- build_processor_hierarchy_node(
41
int first;
50
- table_data,
42
@@ -XXX,XX +XXX,XX @@ static void pl110_update_display(void *opaque)
51
- /*
43
52
- * Physical package - represents the boundary
44
sbd = SYS_BUS_DEVICE(s);
53
- * of a physical package
45
54
- */
46
- switch (surface_bits_per_pixel(surface)) {
55
- (1 << 0),
47
- case 0:
56
- 0, socket, NULL, 0);
48
- return;
49
- case 8:
50
- fntable = pl110_draw_fn_8;
51
- dest_width = 1;
52
- break;
53
- case 15:
54
- fntable = pl110_draw_fn_15;
55
- dest_width = 2;
56
- break;
57
- case 16:
58
- fntable = pl110_draw_fn_16;
59
- dest_width = 2;
60
- break;
61
- case 24:
62
- fntable = pl110_draw_fn_24;
63
- dest_width = 3;
64
- break;
65
- case 32:
66
- fntable = pl110_draw_fn_32;
67
- dest_width = 4;
68
- break;
69
- default:
70
- fprintf(stderr, "pl110: Bad color depth\n");
71
- exit(1);
72
- }
57
- }
73
if (s->cr & PL110_CR_BGR)
58
-
74
bpp_offset = 0;
59
- if (mc->smp_props.clusters_supported) {
75
else
60
- length = g_queue_get_length(list);
76
@@ -XXX,XX +XXX,XX @@ static void pl110_update_display(void *opaque)
61
- for (i = 0; i < length; i++) {
62
- int cluster;
63
-
64
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
65
- for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
66
- g_queue_push_tail(list,
67
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
- build_processor_hierarchy_node(
69
- table_data,
70
- (0 << 0), /* not a physical package */
71
- parent_offset, cluster, NULL, 0);
72
- }
73
+ /*
74
+ * This works with the assumption that cpus[n].props.*_id has been
75
+ * sorted from top to down levels in mc->possible_cpu_arch_ids().
76
+ * Otherwise, the unexpected and duplicated containers will be
77
+ * created.
78
+ */
79
+ for (n = 0; n < cpus->len; n++) {
80
+ if (cpus->cpus[n].props.socket_id != socket_id) {
81
+ assert(cpus->cpus[n].props.socket_id > socket_id);
82
+ socket_id = cpus->cpus[n].props.socket_id;
83
+ cluster_id = -1;
84
+ core_id = -1;
85
+ socket_offset = table_data->len - pptt_start;
86
+ build_processor_hierarchy_node(table_data,
87
+ (1 << 0), /* Physical package */
88
+ 0, socket_id, NULL, 0);
89
}
90
- }
91
92
- length = g_queue_get_length(list);
93
- for (i = 0; i < length; i++) {
94
- int core;
95
-
96
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
97
- for (core = 0; core < ms->smp.cores; core++) {
98
- if (ms->smp.threads > 1) {
99
- g_queue_push_tail(list,
100
- GUINT_TO_POINTER(table_data->len - pptt_start));
101
- build_processor_hierarchy_node(
102
- table_data,
103
- (0 << 0), /* not a physical package */
104
- parent_offset, core, NULL, 0);
105
- } else {
106
- build_processor_hierarchy_node(
107
- table_data,
108
- (1 << 1) | /* ACPI Processor ID valid */
109
- (1 << 3), /* Node is a Leaf */
110
- parent_offset, uid++, NULL, 0);
111
+ if (mc->smp_props.clusters_supported) {
112
+ if (cpus->cpus[n].props.cluster_id != cluster_id) {
113
+ assert(cpus->cpus[n].props.cluster_id > cluster_id);
114
+ cluster_id = cpus->cpus[n].props.cluster_id;
115
+ core_id = -1;
116
+ cluster_offset = table_data->len - pptt_start;
117
+ build_processor_hierarchy_node(table_data,
118
+ (0 << 0), /* Not a physical package */
119
+ socket_offset, cluster_id, NULL, 0);
120
}
121
+ } else {
122
+ cluster_offset = socket_offset;
123
}
124
- }
125
126
- length = g_queue_get_length(list);
127
- for (i = 0; i < length; i++) {
128
- int thread;
129
+ if (ms->smp.threads == 1) {
130
+ build_processor_hierarchy_node(table_data,
131
+ (1 << 1) | /* ACPI Processor ID valid */
132
+ (1 << 3), /* Node is a Leaf */
133
+ cluster_offset, n, NULL, 0);
134
+ } else {
135
+ if (cpus->cpus[n].props.core_id != core_id) {
136
+ assert(cpus->cpus[n].props.core_id > core_id);
137
+ core_id = cpus->cpus[n].props.core_id;
138
+ core_offset = table_data->len - pptt_start;
139
+ build_processor_hierarchy_node(table_data,
140
+ (0 << 0), /* Not a physical package */
141
+ cluster_offset, core_id, NULL, 0);
142
+ }
143
144
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
145
- for (thread = 0; thread < ms->smp.threads; thread++) {
146
- build_processor_hierarchy_node(
147
- table_data,
148
+ build_processor_hierarchy_node(table_data,
149
(1 << 1) | /* ACPI Processor ID valid */
150
(1 << 2) | /* Processor is a Thread */
151
(1 << 3), /* Node is a Leaf */
152
- parent_offset, uid++, NULL, 0);
153
+ core_offset, n, NULL, 0);
77
}
154
}
78
}
155
}
79
156
80
- if (s->cr & PL110_CR_BEBO)
157
- g_queue_free(list);
81
- fn = fntable[s->bpp + 8 + bpp_offset];
158
acpi_table_end(linker, &table);
82
- else if (s->cr & PL110_CR_BEPO)
159
}
83
- fn = fntable[s->bpp + 16 + bpp_offset];
160
84
- else
85
- fn = fntable[s->bpp + bpp_offset];
86
+ if (s->cr & PL110_CR_BEBO) {
87
+ fn = pl110_draw_fn_32[s->bpp + 8 + bpp_offset];
88
+ } else if (s->cr & PL110_CR_BEPO) {
89
+ fn = pl110_draw_fn_32[s->bpp + 16 + bpp_offset];
90
+ } else {
91
+ fn = pl110_draw_fn_32[s->bpp + bpp_offset];
92
+ }
93
94
src_width = s->cols;
95
switch (s->bpp) {
96
@@ -XXX,XX +XXX,XX @@ static void pl110_update_display(void *opaque)
97
src_width <<= 2;
98
break;
99
}
100
- dest_width *= s->cols;
101
first = 0;
102
if (s->invalidate) {
103
framebuffer_update_memory_section(&s->fbsection,
104
@@ -XXX,XX +XXX,XX @@ static void pl110_update_display(void *opaque)
105
106
framebuffer_update_display(surface, &s->fbsection,
107
s->cols, s->rows,
108
- src_width, dest_width, 0,
109
+ src_width, s->cols * 4, 0,
110
s->invalidate,
111
fn, s->palette,
112
&first, &last);
113
--
161
--
114
2.20.1
162
2.25.1
115
116
diff view generated by jsdifflib
[PULL 32/39] hw/display/pl110: Pull included-once parts of template header into pl110.c
Deleted patch
1
The pl110_template.h header has a doubly-nested multiple-include pattern:
2
* pl110.c includes it once for each host bit depth (now always 32)
3
* every time it is included, it includes itself 6 times, to account
4
for multiple guest device pixel and byte orders
5
1
6
Now we only have to deal with 32-bit host bit depths, we can move the
7
code corresponding to the outer layer of this double-nesting to be
8
directly in pl110.c and reduce the template header to a single layer
9
of nesting.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
13
Message-id: 20210211141515.8755-3-peter.maydell@linaro.org
14
---
15
hw/display/pl110_template.h | 100 +-----------------------------------
16
hw/display/pl110.c | 79 ++++++++++++++++++++++++++++
17
2 files changed, 80 insertions(+), 99 deletions(-)
18
19
diff --git a/hw/display/pl110_template.h b/hw/display/pl110_template.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/display/pl110_template.h
22
+++ b/hw/display/pl110_template.h
23
@@ -XXX,XX +XXX,XX @@
24
*/
25
26
#ifndef ORDER
27
-
28
-#if BITS == 8
29
-#define COPY_PIXEL(to, from) *(to++) = from
30
-#elif BITS == 15 || BITS == 16
31
-#define COPY_PIXEL(to, from) do { *(uint16_t *)to = from; to += 2; } while (0)
32
-#elif BITS == 24
33
-#define COPY_PIXEL(to, from) \
34
- do { \
35
- *(to++) = from; \
36
- *(to++) = (from) >> 8; \
37
- *(to++) = (from) >> 16; \
38
- } while (0)
39
-#elif BITS == 32
40
-#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)
41
-#else
42
-#error unknown bit depth
43
+#error "pl110_template.h is only for inclusion by pl110.c"
44
#endif
45
46
-#undef RGB
47
-#define BORDER bgr
48
-#define ORDER 0
49
-#include "pl110_template.h"
50
-#define ORDER 1
51
-#include "pl110_template.h"
52
-#define ORDER 2
53
-#include "pl110_template.h"
54
-#undef BORDER
55
-#define RGB
56
-#define BORDER rgb
57
-#define ORDER 0
58
-#include "pl110_template.h"
59
-#define ORDER 1
60
-#include "pl110_template.h"
61
-#define ORDER 2
62
-#include "pl110_template.h"
63
-#undef BORDER
64
-
65
-static drawfn glue(pl110_draw_fn_,BITS)[48] =
66
-{
67
- glue(pl110_draw_line1_lblp_bgr,BITS),
68
- glue(pl110_draw_line2_lblp_bgr,BITS),
69
- glue(pl110_draw_line4_lblp_bgr,BITS),
70
- glue(pl110_draw_line8_lblp_bgr,BITS),
71
- glue(pl110_draw_line16_555_lblp_bgr,BITS),
72
- glue(pl110_draw_line32_lblp_bgr,BITS),
73
- glue(pl110_draw_line16_lblp_bgr,BITS),
74
- glue(pl110_draw_line12_lblp_bgr,BITS),
75
-
76
- glue(pl110_draw_line1_bbbp_bgr,BITS),
77
- glue(pl110_draw_line2_bbbp_bgr,BITS),
78
- glue(pl110_draw_line4_bbbp_bgr,BITS),
79
- glue(pl110_draw_line8_bbbp_bgr,BITS),
80
- glue(pl110_draw_line16_555_bbbp_bgr,BITS),
81
- glue(pl110_draw_line32_bbbp_bgr,BITS),
82
- glue(pl110_draw_line16_bbbp_bgr,BITS),
83
- glue(pl110_draw_line12_bbbp_bgr,BITS),
84
-
85
- glue(pl110_draw_line1_lbbp_bgr,BITS),
86
- glue(pl110_draw_line2_lbbp_bgr,BITS),
87
- glue(pl110_draw_line4_lbbp_bgr,BITS),
88
- glue(pl110_draw_line8_lbbp_bgr,BITS),
89
- glue(pl110_draw_line16_555_lbbp_bgr,BITS),
90
- glue(pl110_draw_line32_lbbp_bgr,BITS),
91
- glue(pl110_draw_line16_lbbp_bgr,BITS),
92
- glue(pl110_draw_line12_lbbp_bgr,BITS),
93
-
94
- glue(pl110_draw_line1_lblp_rgb,BITS),
95
- glue(pl110_draw_line2_lblp_rgb,BITS),
96
- glue(pl110_draw_line4_lblp_rgb,BITS),
97
- glue(pl110_draw_line8_lblp_rgb,BITS),
98
- glue(pl110_draw_line16_555_lblp_rgb,BITS),
99
- glue(pl110_draw_line32_lblp_rgb,BITS),
100
- glue(pl110_draw_line16_lblp_rgb,BITS),
101
- glue(pl110_draw_line12_lblp_rgb,BITS),
102
-
103
- glue(pl110_draw_line1_bbbp_rgb,BITS),
104
- glue(pl110_draw_line2_bbbp_rgb,BITS),
105
- glue(pl110_draw_line4_bbbp_rgb,BITS),
106
- glue(pl110_draw_line8_bbbp_rgb,BITS),
107
- glue(pl110_draw_line16_555_bbbp_rgb,BITS),
108
- glue(pl110_draw_line32_bbbp_rgb,BITS),
109
- glue(pl110_draw_line16_bbbp_rgb,BITS),
110
- glue(pl110_draw_line12_bbbp_rgb,BITS),
111
-
112
- glue(pl110_draw_line1_lbbp_rgb,BITS),
113
- glue(pl110_draw_line2_lbbp_rgb,BITS),
114
- glue(pl110_draw_line4_lbbp_rgb,BITS),
115
- glue(pl110_draw_line8_lbbp_rgb,BITS),
116
- glue(pl110_draw_line16_555_lbbp_rgb,BITS),
117
- glue(pl110_draw_line32_lbbp_rgb,BITS),
118
- glue(pl110_draw_line16_lbbp_rgb,BITS),
119
- glue(pl110_draw_line12_lbbp_rgb,BITS),
120
-};
121
-
122
-#undef BITS
123
-#undef COPY_PIXEL
124
-
125
-#else
126
-
127
#if ORDER == 0
128
#define NAME glue(glue(lblp_, BORDER), BITS)
129
#ifdef HOST_WORDS_BIGENDIAN
130
@@ -XXX,XX +XXX,XX @@ static void glue(pl110_draw_line12_,NAME)(void *opaque, uint8_t *d, const uint8_
131
#undef NAME
132
#undef SWAP_WORDS
133
#undef ORDER
134
-
135
-#endif
136
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/display/pl110.c
139
+++ b/hw/display/pl110.c
140
@@ -XXX,XX +XXX,XX @@ static const unsigned char *idregs[] = {
141
};
142
143
#define BITS 32
144
+#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)
145
+
146
+#undef RGB
147
+#define BORDER bgr
148
+#define ORDER 0
149
#include "pl110_template.h"
150
+#define ORDER 1
151
+#include "pl110_template.h"
152
+#define ORDER 2
153
+#include "pl110_template.h"
154
+#undef BORDER
155
+#define RGB
156
+#define BORDER rgb
157
+#define ORDER 0
158
+#include "pl110_template.h"
159
+#define ORDER 1
160
+#include "pl110_template.h"
161
+#define ORDER 2
162
+#include "pl110_template.h"
163
+#undef BORDER
164
+
165
+static drawfn pl110_draw_fn_32[48] = {
166
+ pl110_draw_line1_lblp_bgr32,
167
+ pl110_draw_line2_lblp_bgr32,
168
+ pl110_draw_line4_lblp_bgr32,
169
+ pl110_draw_line8_lblp_bgr32,
170
+ pl110_draw_line16_555_lblp_bgr32,
171
+ pl110_draw_line32_lblp_bgr32,
172
+ pl110_draw_line16_lblp_bgr32,
173
+ pl110_draw_line12_lblp_bgr32,
174
+
175
+ pl110_draw_line1_bbbp_bgr32,
176
+ pl110_draw_line2_bbbp_bgr32,
177
+ pl110_draw_line4_bbbp_bgr32,
178
+ pl110_draw_line8_bbbp_bgr32,
179
+ pl110_draw_line16_555_bbbp_bgr32,
180
+ pl110_draw_line32_bbbp_bgr32,
181
+ pl110_draw_line16_bbbp_bgr32,
182
+ pl110_draw_line12_bbbp_bgr32,
183
+
184
+ pl110_draw_line1_lbbp_bgr32,
185
+ pl110_draw_line2_lbbp_bgr32,
186
+ pl110_draw_line4_lbbp_bgr32,
187
+ pl110_draw_line8_lbbp_bgr32,
188
+ pl110_draw_line16_555_lbbp_bgr32,
189
+ pl110_draw_line32_lbbp_bgr32,
190
+ pl110_draw_line16_lbbp_bgr32,
191
+ pl110_draw_line12_lbbp_bgr32,
192
+
193
+ pl110_draw_line1_lblp_rgb32,
194
+ pl110_draw_line2_lblp_rgb32,
195
+ pl110_draw_line4_lblp_rgb32,
196
+ pl110_draw_line8_lblp_rgb32,
197
+ pl110_draw_line16_555_lblp_rgb32,
198
+ pl110_draw_line32_lblp_rgb32,
199
+ pl110_draw_line16_lblp_rgb32,
200
+ pl110_draw_line12_lblp_rgb32,
201
+
202
+ pl110_draw_line1_bbbp_rgb32,
203
+ pl110_draw_line2_bbbp_rgb32,
204
+ pl110_draw_line4_bbbp_rgb32,
205
+ pl110_draw_line8_bbbp_rgb32,
206
+ pl110_draw_line16_555_bbbp_rgb32,
207
+ pl110_draw_line32_bbbp_rgb32,
208
+ pl110_draw_line16_bbbp_rgb32,
209
+ pl110_draw_line12_bbbp_rgb32,
210
+
211
+ pl110_draw_line1_lbbp_rgb32,
212
+ pl110_draw_line2_lbbp_rgb32,
213
+ pl110_draw_line4_lbbp_rgb32,
214
+ pl110_draw_line8_lbbp_rgb32,
215
+ pl110_draw_line16_555_lbbp_rgb32,
216
+ pl110_draw_line32_lbbp_rgb32,
217
+ pl110_draw_line16_lbbp_rgb32,
218
+ pl110_draw_line12_lbbp_rgb32,
219
+};
220
+
221
+#undef BITS
222
+#undef COPY_PIXEL
223
+
224
225
static int pl110_enabled(PL110State *s)
226
{
227
--
228
2.20.1
229
230
diff view generated by jsdifflib
[PULL 33/39] hw/display/pl110: Remove use of BITS from pl110_template.h
Deleted patch
1
BITS is always 32, so remove all uses of it from the template header,
2
by dropping the trailing '32' from the draw function names and
3
not constructing the name of rgb_to_pixel32() via the glue() macro.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
7
Message-id: 20210211141515.8755-4-peter.maydell@linaro.org
8
---
9
hw/display/pl110_template.h | 20 +++----
10
hw/display/pl110.c | 113 ++++++++++++++++++------------------
11
2 files changed, 65 insertions(+), 68 deletions(-)
12
13
diff --git a/hw/display/pl110_template.h b/hw/display/pl110_template.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/display/pl110_template.h
16
+++ b/hw/display/pl110_template.h
17
@@ -XXX,XX +XXX,XX @@
18
#endif
19
20
#if ORDER == 0
21
-#define NAME glue(glue(lblp_, BORDER), BITS)
22
+#define NAME glue(lblp_, BORDER)
23
#ifdef HOST_WORDS_BIGENDIAN
24
#define SWAP_WORDS 1
25
#endif
26
#elif ORDER == 1
27
-#define NAME glue(glue(bbbp_, BORDER), BITS)
28
+#define NAME glue(bbbp_, BORDER)
29
#ifndef HOST_WORDS_BIGENDIAN
30
#define SWAP_WORDS 1
31
#endif
32
#else
33
#define SWAP_PIXELS 1
34
-#define NAME glue(glue(lbbp_, BORDER), BITS)
35
+#define NAME glue(lbbp_, BORDER)
36
#ifdef HOST_WORDS_BIGENDIAN
37
#define SWAP_WORDS 1
38
#endif
39
@@ -XXX,XX +XXX,XX @@ static void glue(pl110_draw_line16_,NAME)(void *opaque, uint8_t *d, const uint8_
40
MSB = (data & 0x1f) << 3;
41
data >>= 5;
42
#endif
43
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
44
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
45
LSB = (data & 0x1f) << 3;
46
data >>= 5;
47
g = (data & 0x3f) << 2;
48
data >>= 6;
49
MSB = (data & 0x1f) << 3;
50
data >>= 5;
51
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
52
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
53
#undef MSB
54
#undef LSB
55
width -= 2;
56
@@ -XXX,XX +XXX,XX @@ static void glue(pl110_draw_line32_,NAME)(void *opaque, uint8_t *d, const uint8_
57
g = (data >> 16) & 0xff;
58
MSB = (data >> 8) & 0xff;
59
#endif
60
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
61
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
62
#undef MSB
63
#undef LSB
64
width--;
65
@@ -XXX,XX +XXX,XX @@ static void glue(pl110_draw_line16_555_,NAME)(void *opaque, uint8_t *d, const ui
66
data >>= 5;
67
MSB = (data & 0x1f) << 3;
68
data >>= 5;
69
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
70
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
71
LSB = (data & 0x1f) << 3;
72
data >>= 5;
73
g = (data & 0x1f) << 3;
74
data >>= 5;
75
MSB = (data & 0x1f) << 3;
76
data >>= 6;
77
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
78
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
79
#undef MSB
80
#undef LSB
81
width -= 2;
82
@@ -XXX,XX +XXX,XX @@ static void glue(pl110_draw_line12_,NAME)(void *opaque, uint8_t *d, const uint8_
83
data >>= 4;
84
MSB = (data & 0xf) << 4;
85
data >>= 8;
86
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
87
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
88
LSB = (data & 0xf) << 4;
89
data >>= 4;
90
g = (data & 0xf) << 4;
91
data >>= 4;
92
MSB = (data & 0xf) << 4;
93
data >>= 8;
94
- COPY_PIXEL(d, glue(rgb_to_pixel,BITS)(r, g, b));
95
+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));
96
#undef MSB
97
#undef LSB
98
width -= 2;
99
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/display/pl110.c
102
+++ b/hw/display/pl110.c
103
@@ -XXX,XX +XXX,XX @@ static const unsigned char *idregs[] = {
104
pl111_id
105
};
106
107
-#define BITS 32
108
#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)
109
110
#undef RGB
111
@@ -XXX,XX +XXX,XX @@ static const unsigned char *idregs[] = {
112
#include "pl110_template.h"
113
#undef BORDER
114
115
-static drawfn pl110_draw_fn_32[48] = {
116
- pl110_draw_line1_lblp_bgr32,
117
- pl110_draw_line2_lblp_bgr32,
118
- pl110_draw_line4_lblp_bgr32,
119
- pl110_draw_line8_lblp_bgr32,
120
- pl110_draw_line16_555_lblp_bgr32,
121
- pl110_draw_line32_lblp_bgr32,
122
- pl110_draw_line16_lblp_bgr32,
123
- pl110_draw_line12_lblp_bgr32,
124
-
125
- pl110_draw_line1_bbbp_bgr32,
126
- pl110_draw_line2_bbbp_bgr32,
127
- pl110_draw_line4_bbbp_bgr32,
128
- pl110_draw_line8_bbbp_bgr32,
129
- pl110_draw_line16_555_bbbp_bgr32,
130
- pl110_draw_line32_bbbp_bgr32,
131
- pl110_draw_line16_bbbp_bgr32,
132
- pl110_draw_line12_bbbp_bgr32,
133
-
134
- pl110_draw_line1_lbbp_bgr32,
135
- pl110_draw_line2_lbbp_bgr32,
136
- pl110_draw_line4_lbbp_bgr32,
137
- pl110_draw_line8_lbbp_bgr32,
138
- pl110_draw_line16_555_lbbp_bgr32,
139
- pl110_draw_line32_lbbp_bgr32,
140
- pl110_draw_line16_lbbp_bgr32,
141
- pl110_draw_line12_lbbp_bgr32,
142
-
143
- pl110_draw_line1_lblp_rgb32,
144
- pl110_draw_line2_lblp_rgb32,
145
- pl110_draw_line4_lblp_rgb32,
146
- pl110_draw_line8_lblp_rgb32,
147
- pl110_draw_line16_555_lblp_rgb32,
148
- pl110_draw_line32_lblp_rgb32,
149
- pl110_draw_line16_lblp_rgb32,
150
- pl110_draw_line12_lblp_rgb32,
151
-
152
- pl110_draw_line1_bbbp_rgb32,
153
- pl110_draw_line2_bbbp_rgb32,
154
- pl110_draw_line4_bbbp_rgb32,
155
- pl110_draw_line8_bbbp_rgb32,
156
- pl110_draw_line16_555_bbbp_rgb32,
157
- pl110_draw_line32_bbbp_rgb32,
158
- pl110_draw_line16_bbbp_rgb32,
159
- pl110_draw_line12_bbbp_rgb32,
160
-
161
- pl110_draw_line1_lbbp_rgb32,
162
- pl110_draw_line2_lbbp_rgb32,
163
- pl110_draw_line4_lbbp_rgb32,
164
- pl110_draw_line8_lbbp_rgb32,
165
- pl110_draw_line16_555_lbbp_rgb32,
166
- pl110_draw_line32_lbbp_rgb32,
167
- pl110_draw_line16_lbbp_rgb32,
168
- pl110_draw_line12_lbbp_rgb32,
169
-};
170
-
171
-#undef BITS
172
#undef COPY_PIXEL
173
174
+static drawfn pl110_draw_fn_32[48] = {
175
+ pl110_draw_line1_lblp_bgr,
176
+ pl110_draw_line2_lblp_bgr,
177
+ pl110_draw_line4_lblp_bgr,
178
+ pl110_draw_line8_lblp_bgr,
179
+ pl110_draw_line16_555_lblp_bgr,
180
+ pl110_draw_line32_lblp_bgr,
181
+ pl110_draw_line16_lblp_bgr,
182
+ pl110_draw_line12_lblp_bgr,
183
+
184
+ pl110_draw_line1_bbbp_bgr,
185
+ pl110_draw_line2_bbbp_bgr,
186
+ pl110_draw_line4_bbbp_bgr,
187
+ pl110_draw_line8_bbbp_bgr,
188
+ pl110_draw_line16_555_bbbp_bgr,
189
+ pl110_draw_line32_bbbp_bgr,
190
+ pl110_draw_line16_bbbp_bgr,
191
+ pl110_draw_line12_bbbp_bgr,
192
+
193
+ pl110_draw_line1_lbbp_bgr,
194
+ pl110_draw_line2_lbbp_bgr,
195
+ pl110_draw_line4_lbbp_bgr,
196
+ pl110_draw_line8_lbbp_bgr,
197
+ pl110_draw_line16_555_lbbp_bgr,
198
+ pl110_draw_line32_lbbp_bgr,
199
+ pl110_draw_line16_lbbp_bgr,
200
+ pl110_draw_line12_lbbp_bgr,
201
+
202
+ pl110_draw_line1_lblp_rgb,
203
+ pl110_draw_line2_lblp_rgb,
204
+ pl110_draw_line4_lblp_rgb,
205
+ pl110_draw_line8_lblp_rgb,
206
+ pl110_draw_line16_555_lblp_rgb,
207
+ pl110_draw_line32_lblp_rgb,
208
+ pl110_draw_line16_lblp_rgb,
209
+ pl110_draw_line12_lblp_rgb,
210
+
211
+ pl110_draw_line1_bbbp_rgb,
212
+ pl110_draw_line2_bbbp_rgb,
213
+ pl110_draw_line4_bbbp_rgb,
214
+ pl110_draw_line8_bbbp_rgb,
215
+ pl110_draw_line16_555_bbbp_rgb,
216
+ pl110_draw_line32_bbbp_rgb,
217
+ pl110_draw_line16_bbbp_rgb,
218
+ pl110_draw_line12_bbbp_rgb,
219
+
220
+ pl110_draw_line1_lbbp_rgb,
221
+ pl110_draw_line2_lbbp_rgb,
222
+ pl110_draw_line4_lbbp_rgb,
223
+ pl110_draw_line8_lbbp_rgb,
224
+ pl110_draw_line16_555_lbbp_rgb,
225
+ pl110_draw_line32_lbbp_rgb,
226
+ pl110_draw_line16_lbbp_rgb,
227
+ pl110_draw_line12_lbbp_rgb,
228
+};
229
230
static int pl110_enabled(PL110State *s)
231
{
232
--
233
2.20.1
234
235
diff view generated by jsdifflib
[PULL 34/39] hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
Deleted patch
1
For a long time now the UI layer has guaranteed that the console
2
surface is always 32 bits per pixel. Remove the legacy dead code
3
from the pxa2xx_lcd display device which was handling the possibility
4
that the console surface was some other format.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
8
Message-id: 20210211141515.8755-5-peter.maydell@linaro.org
9
---
10
hw/display/pxa2xx_lcd.c | 79 +++++++++--------------------------------
11
1 file changed, 17 insertions(+), 62 deletions(-)
12
13
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/display/pxa2xx_lcd.c
16
+++ b/hw/display/pxa2xx_lcd.c
17
@@ -XXX,XX +XXX,XX @@ struct PXA2xxLCDState {
18
19
int invalidated;
20
QemuConsole *con;
21
- drawfn *line_fn[2];
22
int dest_width;
23
int xres, yres;
24
int pal_for;
25
@@ -XXX,XX +XXX,XX @@ typedef struct QEMU_PACKED {
26
#define LDCMD_SOFINT    (1 << 22)
27
#define LDCMD_PAL    (1 << 26)
28
29
+#define BITS 32
30
+#include "pxa2xx_template.h"
31
+
32
/* Route internal interrupt lines to the global IC */
33
static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
34
{
35
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
36
}
37
}
38
39
+static inline drawfn pxa2xx_drawfn(PXA2xxLCDState *s)
40
+{
41
+ if (s->transp) {
42
+ return pxa2xx_draw_fn_32t[s->bpp];
43
+ } else {
44
+ return pxa2xx_draw_fn_32[s->bpp];
45
+ }
46
+}
47
+
48
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
49
hwaddr addr, int *miny, int *maxy)
50
{
51
DisplaySurface *surface = qemu_console_surface(s->con);
52
int src_width, dest_width;
53
- drawfn fn = NULL;
54
- if (s->dest_width)
55
- fn = s->line_fn[s->transp][s->bpp];
56
+ drawfn fn = pxa2xx_drawfn(s);
57
if (!fn)
58
return;
59
60
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
61
{
62
DisplaySurface *surface = qemu_console_surface(s->con);
63
int src_width, dest_width;
64
- drawfn fn = NULL;
65
- if (s->dest_width)
66
- fn = s->line_fn[s->transp][s->bpp];
67
+ drawfn fn = pxa2xx_drawfn(s);
68
if (!fn)
69
return;
70
71
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
72
{
73
DisplaySurface *surface = qemu_console_surface(s->con);
74
int src_width, dest_width;
75
- drawfn fn = NULL;
76
- if (s->dest_width) {
77
- fn = s->line_fn[s->transp][s->bpp];
78
- }
79
+ drawfn fn = pxa2xx_drawfn(s);
80
if (!fn) {
81
return;
82
}
83
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
84
{
85
DisplaySurface *surface = qemu_console_surface(s->con);
86
int src_width, dest_width;
87
- drawfn fn = NULL;
88
- if (s->dest_width) {
89
- fn = s->line_fn[s->transp][s->bpp];
90
- }
91
+ drawfn fn = pxa2xx_drawfn(s);
92
if (!fn) {
93
return;
94
}
95
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pxa2xx_lcdc = {
96
}
97
};
98
99
-#define BITS 8
100
-#include "pxa2xx_template.h"
101
-#define BITS 15
102
-#include "pxa2xx_template.h"
103
-#define BITS 16
104
-#include "pxa2xx_template.h"
105
-#define BITS 24
106
-#include "pxa2xx_template.h"
107
-#define BITS 32
108
-#include "pxa2xx_template.h"
109
-
110
static const GraphicHwOps pxa2xx_ops = {
111
.invalidate = pxa2xx_invalidate_display,
112
.gfx_update = pxa2xx_update_display,
113
@@ -XXX,XX +XXX,XX @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
114
hwaddr base, qemu_irq irq)
115
{
116
PXA2xxLCDState *s;
117
- DisplaySurface *surface;
118
119
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
120
s->invalidated = 1;
121
@@ -XXX,XX +XXX,XX @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
122
memory_region_add_subregion(sysmem, base, &s->iomem);
123
124
s->con = graphic_console_init(NULL, 0, &pxa2xx_ops, s);
125
- surface = qemu_console_surface(s->con);
126
-
127
- switch (surface_bits_per_pixel(surface)) {
128
- case 0:
129
- s->dest_width = 0;
130
- break;
131
- case 8:
132
- s->line_fn[0] = pxa2xx_draw_fn_8;
133
- s->line_fn[1] = pxa2xx_draw_fn_8t;
134
- s->dest_width = 1;
135
- break;
136
- case 15:
137
- s->line_fn[0] = pxa2xx_draw_fn_15;
138
- s->line_fn[1] = pxa2xx_draw_fn_15t;
139
- s->dest_width = 2;
140
- break;
141
- case 16:
142
- s->line_fn[0] = pxa2xx_draw_fn_16;
143
- s->line_fn[1] = pxa2xx_draw_fn_16t;
144
- s->dest_width = 2;
145
- break;
146
- case 24:
147
- s->line_fn[0] = pxa2xx_draw_fn_24;
148
- s->line_fn[1] = pxa2xx_draw_fn_24t;
149
- s->dest_width = 3;
150
- break;
151
- case 32:
152
- s->line_fn[0] = pxa2xx_draw_fn_32;
153
- s->line_fn[1] = pxa2xx_draw_fn_32t;
154
- s->dest_width = 4;
155
- break;
156
- default:
157
- fprintf(stderr, "%s: Bad color depth\n", __func__);
158
- exit(1);
159
- }
160
+ s->dest_width = 4;
161
162
vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
163
164
--
165
2.20.1
166
167
diff view generated by jsdifflib
[PULL 35/39] hw/display/pxa2xx_lcd: Remove dest_width state field
Deleted patch
1
Since the dest_width is now always 4 because the output surface is
2
32bpp, we can replace the dest_width state field with a constant.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
6
Message-id: 20210211141515.8755-6-peter.maydell@linaro.org
7
---
8
hw/display/pxa2xx_lcd.c | 20 +++++++++++---------
9
1 file changed, 11 insertions(+), 9 deletions(-)
10
11
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/display/pxa2xx_lcd.c
14
+++ b/hw/display/pxa2xx_lcd.c
15
@@ -XXX,XX +XXX,XX @@ typedef struct QEMU_PACKED {
16
#define LDCMD_SOFINT    (1 << 22)
17
#define LDCMD_PAL    (1 << 26)
18
19
+/* Size of a pixel in the QEMU UI output surface, in bytes */
20
+#define DEST_PIXEL_WIDTH 4
21
+
22
#define BITS 32
23
#include "pxa2xx_template.h"
24
25
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
26
else if (s->bpp > pxa_lcdc_8bpp)
27
src_width *= 2;
28
29
- dest_width = s->xres * s->dest_width;
30
+ dest_width = s->xres * DEST_PIXEL_WIDTH;
31
*miny = 0;
32
if (s->invalidated) {
33
framebuffer_update_memory_section(&s->fbsection, s->sysmem,
34
addr, s->yres, src_width);
35
}
36
framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
37
- src_width, dest_width, s->dest_width,
38
+ src_width, dest_width, DEST_PIXEL_WIDTH,
39
s->invalidated,
40
fn, s->dma_ch[0].palette, miny, maxy);
41
}
42
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
43
else if (s->bpp > pxa_lcdc_8bpp)
44
src_width *= 2;
45
46
- dest_width = s->yres * s->dest_width;
47
+ dest_width = s->yres * DEST_PIXEL_WIDTH;
48
*miny = 0;
49
if (s->invalidated) {
50
framebuffer_update_memory_section(&s->fbsection, s->sysmem,
51
addr, s->yres, src_width);
52
}
53
framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
54
- src_width, s->dest_width, -dest_width,
55
+ src_width, DEST_PIXEL_WIDTH, -dest_width,
56
s->invalidated,
57
fn, s->dma_ch[0].palette,
58
miny, maxy);
59
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
60
src_width *= 2;
61
}
62
63
- dest_width = s->xres * s->dest_width;
64
+ dest_width = s->xres * DEST_PIXEL_WIDTH;
65
*miny = 0;
66
if (s->invalidated) {
67
framebuffer_update_memory_section(&s->fbsection, s->sysmem,
68
addr, s->yres, src_width);
69
}
70
framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
71
- src_width, -dest_width, -s->dest_width,
72
+ src_width, -dest_width, -DEST_PIXEL_WIDTH,
73
s->invalidated,
74
fn, s->dma_ch[0].palette, miny, maxy);
75
}
76
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
77
src_width *= 2;
78
}
79
80
- dest_width = s->yres * s->dest_width;
81
+ dest_width = s->yres * DEST_PIXEL_WIDTH;
82
*miny = 0;
83
if (s->invalidated) {
84
framebuffer_update_memory_section(&s->fbsection, s->sysmem,
85
addr, s->yres, src_width);
86
}
87
framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
88
- src_width, -s->dest_width, dest_width,
89
+ src_width, -DEST_PIXEL_WIDTH, dest_width,
90
s->invalidated,
91
fn, s->dma_ch[0].palette,
92
miny, maxy);
93
@@ -XXX,XX +XXX,XX @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
94
memory_region_add_subregion(sysmem, base, &s->iomem);
95
96
s->con = graphic_console_init(NULL, 0, &pxa2xx_ops, s);
97
- s->dest_width = 4;
98
99
vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
100
101
--
102
2.20.1
103
104
diff view generated by jsdifflib
[PULL 36/39] hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
Deleted patch
1
Now that BITS is always 32, expand out all its uses in the template
2
header, including removing now-useless uses of the glue() macro.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
6
Message-id: 20210211141515.8755-7-peter.maydell@linaro.org
7
---
8
hw/display/pxa2xx_template.h | 110 ++++++++++++++---------------------
9
1 file changed, 45 insertions(+), 65 deletions(-)
10
11
diff --git a/hw/display/pxa2xx_template.h b/hw/display/pxa2xx_template.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/display/pxa2xx_template.h
14
+++ b/hw/display/pxa2xx_template.h
15
@@ -XXX,XX +XXX,XX @@
16
*/
17
18
# define SKIP_PIXEL(to)        to += deststep
19
-#if BITS == 8
20
-# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
21
-#elif BITS == 15 || BITS == 16
22
-# define COPY_PIXEL(to, from) \
23
- do { \
24
- *(uint16_t *) to = from; \
25
- SKIP_PIXEL(to); \
26
- } while (0)
27
-#elif BITS == 24
28
-# define COPY_PIXEL(to, from) \
29
- do { \
30
- *(uint16_t *) to = from; \
31
- *(to + 2) = (from) >> 16; \
32
- SKIP_PIXEL(to); \
33
- } while (0)
34
-#elif BITS == 32
35
# define COPY_PIXEL(to, from) \
36
do { \
37
*(uint32_t *) to = from; \
38
SKIP_PIXEL(to); \
39
} while (0)
40
-#else
41
-# error unknown bit depth
42
-#endif
43
44
#ifdef HOST_WORDS_BIGENDIAN
45
# define SWAP_WORDS    1
46
@@ -XXX,XX +XXX,XX @@
47
#define FN_2(x)        FN(x + 1) FN(x)
48
#define FN_4(x)        FN_2(x + 2) FN_2(x)
49
50
-static void glue(pxa2xx_draw_line2_, BITS)(void *opaque,
51
+static void pxa2xx_draw_line2(void *opaque,
52
uint8_t *dest, const uint8_t *src, int width, int deststep)
53
{
54
uint32_t *palette = opaque;
55
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line2_, BITS)(void *opaque,
56
}
57
}
58
59
-static void glue(pxa2xx_draw_line4_, BITS)(void *opaque,
60
+static void pxa2xx_draw_line4(void *opaque,
61
uint8_t *dest, const uint8_t *src, int width, int deststep)
62
{
63
uint32_t *palette = opaque;
64
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line4_, BITS)(void *opaque,
65
}
66
}
67
68
-static void glue(pxa2xx_draw_line8_, BITS)(void *opaque,
69
+static void pxa2xx_draw_line8(void *opaque,
70
uint8_t *dest, const uint8_t *src, int width, int deststep)
71
{
72
uint32_t *palette = opaque;
73
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line8_, BITS)(void *opaque,
74
}
75
}
76
77
-static void glue(pxa2xx_draw_line16_, BITS)(void *opaque,
78
+static void pxa2xx_draw_line16(void *opaque,
79
uint8_t *dest, const uint8_t *src, int width, int deststep)
80
{
81
uint32_t data;
82
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line16_, BITS)(void *opaque,
83
data >>= 6;
84
r = (data & 0x1f) << 3;
85
data >>= 5;
86
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
87
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
88
b = (data & 0x1f) << 3;
89
data >>= 5;
90
g = (data & 0x3f) << 2;
91
data >>= 6;
92
r = (data & 0x1f) << 3;
93
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
94
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
95
width -= 2;
96
src += 4;
97
}
98
}
99
100
-static void glue(pxa2xx_draw_line16t_, BITS)(void *opaque,
101
+static void pxa2xx_draw_line16t(void *opaque,
102
uint8_t *dest, const uint8_t *src, int width, int deststep)
103
{
104
uint32_t data;
105
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line16t_, BITS)(void *opaque,
106
if (data & 1)
107
SKIP_PIXEL(dest);
108
else
109
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
110
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
111
data >>= 1;
112
b = (data & 0x1f) << 3;
113
data >>= 5;
114
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line16t_, BITS)(void *opaque,
115
if (data & 1)
116
SKIP_PIXEL(dest);
117
else
118
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
119
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
120
width -= 2;
121
src += 4;
122
}
123
}
124
125
-static void glue(pxa2xx_draw_line18_, BITS)(void *opaque,
126
+static void pxa2xx_draw_line18(void *opaque,
127
uint8_t *dest, const uint8_t *src, int width, int deststep)
128
{
129
uint32_t data;
130
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line18_, BITS)(void *opaque,
131
g = (data & 0x3f) << 2;
132
data >>= 6;
133
r = (data & 0x3f) << 2;
134
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
135
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
136
width -= 1;
137
src += 4;
138
}
139
}
140
141
/* The wicked packed format */
142
-static void glue(pxa2xx_draw_line18p_, BITS)(void *opaque,
143
+static void pxa2xx_draw_line18p(void *opaque,
144
uint8_t *dest, const uint8_t *src, int width, int deststep)
145
{
146
uint32_t data[3];
147
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line18p_, BITS)(void *opaque,
148
data[0] >>= 6;
149
r = (data[0] & 0x3f) << 2;
150
data[0] >>= 12;
151
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
152
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
153
b = (data[0] & 0x3f) << 2;
154
data[0] >>= 6;
155
g = ((data[1] & 0xf) << 4) | (data[0] << 2);
156
data[1] >>= 4;
157
r = (data[1] & 0x3f) << 2;
158
data[1] >>= 12;
159
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
160
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
161
b = (data[1] & 0x3f) << 2;
162
data[1] >>= 6;
163
g = (data[1] & 0x3f) << 2;
164
data[1] >>= 6;
165
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
166
data[2] >>= 8;
167
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
168
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
169
b = (data[2] & 0x3f) << 2;
170
data[2] >>= 6;
171
g = (data[2] & 0x3f) << 2;
172
data[2] >>= 6;
173
r = data[2] << 2;
174
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
175
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
176
width -= 4;
177
}
178
}
179
180
-static void glue(pxa2xx_draw_line19_, BITS)(void *opaque,
181
+static void pxa2xx_draw_line19(void *opaque,
182
uint8_t *dest, const uint8_t *src, int width, int deststep)
183
{
184
uint32_t data;
185
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line19_, BITS)(void *opaque,
186
if (data & 1)
187
SKIP_PIXEL(dest);
188
else
189
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
190
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
191
width -= 1;
192
src += 4;
193
}
194
}
195
196
/* The wicked packed format */
197
-static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
198
+static void pxa2xx_draw_line19p(void *opaque,
199
uint8_t *dest, const uint8_t *src, int width, int deststep)
200
{
201
uint32_t data[3];
202
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
203
if (data[0] & 1)
204
SKIP_PIXEL(dest);
205
else
206
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
207
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
208
data[0] >>= 6;
209
b = (data[0] & 0x3f) << 2;
210
data[0] >>= 6;
211
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
212
if (data[1] & 1)
213
SKIP_PIXEL(dest);
214
else
215
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
216
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
217
data[1] >>= 6;
218
b = (data[1] & 0x3f) << 2;
219
data[1] >>= 6;
220
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
221
if (data[2] & 1)
222
SKIP_PIXEL(dest);
223
else
224
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
225
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
226
data[2] >>= 6;
227
b = (data[2] & 0x3f) << 2;
228
data[2] >>= 6;
229
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line19p_, BITS)(void *opaque,
230
if (data[2] & 1)
231
SKIP_PIXEL(dest);
232
else
233
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
234
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
235
width -= 4;
236
}
237
}
238
239
-static void glue(pxa2xx_draw_line24_, BITS)(void *opaque,
240
+static void pxa2xx_draw_line24(void *opaque,
241
uint8_t *dest, const uint8_t *src, int width, int deststep)
242
{
243
uint32_t data;
244
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line24_, BITS)(void *opaque,
245
g = data & 0xff;
246
data >>= 8;
247
r = data & 0xff;
248
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
249
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
250
width -= 1;
251
src += 4;
252
}
253
}
254
255
-static void glue(pxa2xx_draw_line24t_, BITS)(void *opaque,
256
+static void pxa2xx_draw_line24t(void *opaque,
257
uint8_t *dest, const uint8_t *src, int width, int deststep)
258
{
259
uint32_t data;
260
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line24t_, BITS)(void *opaque,
261
if (data & 1)
262
SKIP_PIXEL(dest);
263
else
264
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
265
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
266
width -= 1;
267
src += 4;
268
}
269
}
270
271
-static void glue(pxa2xx_draw_line25_, BITS)(void *opaque,
272
+static void pxa2xx_draw_line25(void *opaque,
273
uint8_t *dest, const uint8_t *src, int width, int deststep)
274
{
275
uint32_t data;
276
@@ -XXX,XX +XXX,XX @@ static void glue(pxa2xx_draw_line25_, BITS)(void *opaque,
277
if (data & 1)
278
SKIP_PIXEL(dest);
279
else
280
- COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
281
+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
282
width -= 1;
283
src += 4;
284
}
285
}
286
287
/* Overlay planes disabled, no transparency */
288
-static drawfn glue(pxa2xx_draw_fn_, BITS)[16] =
289
+static drawfn pxa2xx_draw_fn_32[16] =
290
{
291
[0 ... 0xf] = NULL,
292
- [pxa_lcdc_2bpp] = glue(pxa2xx_draw_line2_, BITS),
293
- [pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
294
- [pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
295
- [pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16_, BITS),
296
- [pxa_lcdc_18bpp] = glue(pxa2xx_draw_line18_, BITS),
297
- [pxa_lcdc_18pbpp] = glue(pxa2xx_draw_line18p_, BITS),
298
- [pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24_, BITS),
299
+ [pxa_lcdc_2bpp] = pxa2xx_draw_line2,
300
+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
301
+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
302
+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16,
303
+ [pxa_lcdc_18bpp] = pxa2xx_draw_line18,
304
+ [pxa_lcdc_18pbpp] = pxa2xx_draw_line18p,
305
+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24,
306
};
307
308
/* Overlay planes enabled, transparency used */
309
-static drawfn glue(glue(pxa2xx_draw_fn_, BITS), t)[16] =
310
+static drawfn pxa2xx_draw_fn_32t[16] =
311
{
312
[0 ... 0xf] = NULL,
313
- [pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
314
- [pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
315
- [pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16t_, BITS),
316
- [pxa_lcdc_19bpp] = glue(pxa2xx_draw_line19_, BITS),
317
- [pxa_lcdc_19pbpp] = glue(pxa2xx_draw_line19p_, BITS),
318
- [pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24t_, BITS),
319
- [pxa_lcdc_25bpp] = glue(pxa2xx_draw_line25_, BITS),
320
+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,
321
+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,
322
+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16t,
323
+ [pxa_lcdc_19bpp] = pxa2xx_draw_line19,
324
+ [pxa_lcdc_19pbpp] = pxa2xx_draw_line19p,
325
+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24t,
326
+ [pxa_lcdc_25bpp] = pxa2xx_draw_line25,
327
};
328
329
-#undef BITS
330
#undef COPY_PIXEL
331
#undef SKIP_PIXEL
332
333
--
334
2.20.1
335
336
diff view generated by jsdifflib
[PULL 37/39] hw/display/pxa2xx: Apply brace-related coding style fixes to template header
Deleted patch
1
We're about to move code from the template header into pxa2xx_lcd.c.
2
Before doing that, make coding style fixes so checkpatch doesn't
3
complain about the patch which moves the code. This commit fixes
4
missing braces in the SKIP_PIXEL() macro definition and in if()
5
statements.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
9
Message-id: 20210211141515.8755-8-peter.maydell@linaro.org
10
---
11
hw/display/pxa2xx_template.h | 47 +++++++++++++++++++++---------------
12
1 file changed, 28 insertions(+), 19 deletions(-)
13
14
diff --git a/hw/display/pxa2xx_template.h b/hw/display/pxa2xx_template.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/display/pxa2xx_template.h
17
+++ b/hw/display/pxa2xx_template.h
18
@@ -XXX,XX +XXX,XX @@
19
* Framebuffer format conversion routines.
20
*/
21
22
-# define SKIP_PIXEL(to)        to += deststep
23
+# define SKIP_PIXEL(to) do { to += deststep; } while (0)
24
# define COPY_PIXEL(to, from) \
25
do { \
26
*(uint32_t *) to = from; \
27
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line16t(void *opaque,
28
data >>= 5;
29
r = (data & 0x1f) << 3;
30
data >>= 5;
31
- if (data & 1)
32
+ if (data & 1) {
33
SKIP_PIXEL(dest);
34
- else
35
+ } else {
36
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
37
+ }
38
data >>= 1;
39
b = (data & 0x1f) << 3;
40
data >>= 5;
41
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line16t(void *opaque,
42
data >>= 5;
43
r = (data & 0x1f) << 3;
44
data >>= 5;
45
- if (data & 1)
46
+ if (data & 1) {
47
SKIP_PIXEL(dest);
48
- else
49
+ } else {
50
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
51
+ }
52
width -= 2;
53
src += 4;
54
}
55
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19(void *opaque,
56
data >>= 6;
57
r = (data & 0x3f) << 2;
58
data >>= 6;
59
- if (data & 1)
60
+ if (data & 1) {
61
SKIP_PIXEL(dest);
62
- else
63
+ } else {
64
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
65
+ }
66
width -= 1;
67
src += 4;
68
}
69
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19p(void *opaque,
70
data[0] >>= 6;
71
r = (data[0] & 0x3f) << 2;
72
data[0] >>= 6;
73
- if (data[0] & 1)
74
+ if (data[0] & 1) {
75
SKIP_PIXEL(dest);
76
- else
77
+ } else {
78
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
79
+ }
80
data[0] >>= 6;
81
b = (data[0] & 0x3f) << 2;
82
data[0] >>= 6;
83
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19p(void *opaque,
84
data[1] >>= 4;
85
r = (data[1] & 0x3f) << 2;
86
data[1] >>= 6;
87
- if (data[1] & 1)
88
+ if (data[1] & 1) {
89
SKIP_PIXEL(dest);
90
- else
91
+ } else {
92
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
93
+ }
94
data[1] >>= 6;
95
b = (data[1] & 0x3f) << 2;
96
data[1] >>= 6;
97
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19p(void *opaque,
98
data[1] >>= 6;
99
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
100
data[2] >>= 2;
101
- if (data[2] & 1)
102
+ if (data[2] & 1) {
103
SKIP_PIXEL(dest);
104
- else
105
+ } else {
106
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
107
+ }
108
data[2] >>= 6;
109
b = (data[2] & 0x3f) << 2;
110
data[2] >>= 6;
111
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19p(void *opaque,
112
data[2] >>= 6;
113
r = data[2] << 2;
114
data[2] >>= 6;
115
- if (data[2] & 1)
116
+ if (data[2] & 1) {
117
SKIP_PIXEL(dest);
118
- else
119
+ } else {
120
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
121
+ }
122
width -= 4;
123
}
124
}
125
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line24t(void *opaque,
126
data >>= 8;
127
r = data & 0xff;
128
data >>= 8;
129
- if (data & 1)
130
+ if (data & 1) {
131
SKIP_PIXEL(dest);
132
- else
133
+ } else {
134
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
135
+ }
136
width -= 1;
137
src += 4;
138
}
139
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line25(void *opaque,
140
data >>= 8;
141
r = data & 0xff;
142
data >>= 8;
143
- if (data & 1)
144
+ if (data & 1) {
145
SKIP_PIXEL(dest);
146
- else
147
+ } else {
148
COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));
149
+ }
150
width -= 1;
151
src += 4;
152
}
153
--
154
2.20.1
155
156
diff view generated by jsdifflib
[PULL 38/39] hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
Deleted patch
1
We're about to move code from the template header into pxa2xx_lcd.c.
2
Before doing that, make coding style fixes so checkpatch doesn't
3
complain about the patch which moves the code. This commit is
4
whitespace changes only:
5
* avoid hard-coded tabs
6
* fix ident on function prototypes
7
* no newline before open brace on array definitions
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
11
Message-id: 20210211141515.8755-9-peter.maydell@linaro.org
12
---
13
hw/display/pxa2xx_template.h | 66 +++++++++++++++++-------------------
14
1 file changed, 32 insertions(+), 34 deletions(-)
15
16
diff --git a/hw/display/pxa2xx_template.h b/hw/display/pxa2xx_template.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/display/pxa2xx_template.h
19
+++ b/hw/display/pxa2xx_template.h
20
@@ -XXX,XX +XXX,XX @@
21
} while (0)
22
23
#ifdef HOST_WORDS_BIGENDIAN
24
-# define SWAP_WORDS    1
25
+# define SWAP_WORDS 1
26
#endif
27
28
-#define FN_2(x)        FN(x + 1) FN(x)
29
-#define FN_4(x)        FN_2(x + 2) FN_2(x)
30
+#define FN_2(x) FN(x + 1) FN(x)
31
+#define FN_4(x) FN_2(x + 2) FN_2(x)
32
33
-static void pxa2xx_draw_line2(void *opaque,
34
- uint8_t *dest, const uint8_t *src, int width, int deststep)
35
+static void pxa2xx_draw_line2(void *opaque, uint8_t *dest, const uint8_t *src,
36
+ int width, int deststep)
37
{
38
uint32_t *palette = opaque;
39
uint32_t data;
40
while (width > 0) {
41
data = *(uint32_t *) src;
42
-#define FN(x)        COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
43
+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
44
#ifdef SWAP_WORDS
45
FN_4(12)
46
FN_4(8)
47
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line2(void *opaque,
48
}
49
}
50
51
-static void pxa2xx_draw_line4(void *opaque,
52
- uint8_t *dest, const uint8_t *src, int width, int deststep)
53
+static void pxa2xx_draw_line4(void *opaque, uint8_t *dest, const uint8_t *src,
54
+ int width, int deststep)
55
{
56
uint32_t *palette = opaque;
57
uint32_t data;
58
while (width > 0) {
59
data = *(uint32_t *) src;
60
-#define FN(x)        COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
61
+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
62
#ifdef SWAP_WORDS
63
FN_2(6)
64
FN_2(4)
65
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line4(void *opaque,
66
}
67
}
68
69
-static void pxa2xx_draw_line8(void *opaque,
70
- uint8_t *dest, const uint8_t *src, int width, int deststep)
71
+static void pxa2xx_draw_line8(void *opaque, uint8_t *dest, const uint8_t *src,
72
+ int width, int deststep)
73
{
74
uint32_t *palette = opaque;
75
uint32_t data;
76
while (width > 0) {
77
data = *(uint32_t *) src;
78
-#define FN(x)        COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
79
+#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
80
#ifdef SWAP_WORDS
81
FN(24)
82
FN(16)
83
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line8(void *opaque,
84
}
85
}
86
87
-static void pxa2xx_draw_line16(void *opaque,
88
- uint8_t *dest, const uint8_t *src, int width, int deststep)
89
+static void pxa2xx_draw_line16(void *opaque, uint8_t *dest, const uint8_t *src,
90
+ int width, int deststep)
91
{
92
uint32_t data;
93
unsigned int r, g, b;
94
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line16(void *opaque,
95
}
96
}
97
98
-static void pxa2xx_draw_line16t(void *opaque,
99
- uint8_t *dest, const uint8_t *src, int width, int deststep)
100
+static void pxa2xx_draw_line16t(void *opaque, uint8_t *dest, const uint8_t *src,
101
+ int width, int deststep)
102
{
103
uint32_t data;
104
unsigned int r, g, b;
105
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line16t(void *opaque,
106
}
107
}
108
109
-static void pxa2xx_draw_line18(void *opaque,
110
- uint8_t *dest, const uint8_t *src, int width, int deststep)
111
+static void pxa2xx_draw_line18(void *opaque, uint8_t *dest, const uint8_t *src,
112
+ int width, int deststep)
113
{
114
uint32_t data;
115
unsigned int r, g, b;
116
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line18(void *opaque,
117
}
118
119
/* The wicked packed format */
120
-static void pxa2xx_draw_line18p(void *opaque,
121
- uint8_t *dest, const uint8_t *src, int width, int deststep)
122
+static void pxa2xx_draw_line18p(void *opaque, uint8_t *dest, const uint8_t *src,
123
+ int width, int deststep)
124
{
125
uint32_t data[3];
126
unsigned int r, g, b;
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line18p(void *opaque,
128
}
129
}
130
131
-static void pxa2xx_draw_line19(void *opaque,
132
- uint8_t *dest, const uint8_t *src, int width, int deststep)
133
+static void pxa2xx_draw_line19(void *opaque, uint8_t *dest, const uint8_t *src,
134
+ int width, int deststep)
135
{
136
uint32_t data;
137
unsigned int r, g, b;
138
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19(void *opaque,
139
}
140
141
/* The wicked packed format */
142
-static void pxa2xx_draw_line19p(void *opaque,
143
- uint8_t *dest, const uint8_t *src, int width, int deststep)
144
+static void pxa2xx_draw_line19p(void *opaque, uint8_t *dest, const uint8_t *src,
145
+ int width, int deststep)
146
{
147
uint32_t data[3];
148
unsigned int r, g, b;
149
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line19p(void *opaque,
150
}
151
}
152
153
-static void pxa2xx_draw_line24(void *opaque,
154
- uint8_t *dest, const uint8_t *src, int width, int deststep)
155
+static void pxa2xx_draw_line24(void *opaque, uint8_t *dest, const uint8_t *src,
156
+ int width, int deststep)
157
{
158
uint32_t data;
159
unsigned int r, g, b;
160
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line24(void *opaque,
161
}
162
}
163
164
-static void pxa2xx_draw_line24t(void *opaque,
165
- uint8_t *dest, const uint8_t *src, int width, int deststep)
166
+static void pxa2xx_draw_line24t(void *opaque, uint8_t *dest, const uint8_t *src,
167
+ int width, int deststep)
168
{
169
uint32_t data;
170
unsigned int r, g, b;
171
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line24t(void *opaque,
172
}
173
}
174
175
-static void pxa2xx_draw_line25(void *opaque,
176
- uint8_t *dest, const uint8_t *src, int width, int deststep)
177
+static void pxa2xx_draw_line25(void *opaque, uint8_t *dest, const uint8_t *src,
178
+ int width, int deststep)
179
{
180
uint32_t data;
181
unsigned int r, g, b;
182
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_draw_line25(void *opaque,
183
}
184
185
/* Overlay planes disabled, no transparency */
186
-static drawfn pxa2xx_draw_fn_32[16] =
187
-{
188
+static drawfn pxa2xx_draw_fn_32[16] = {
189
[0 ... 0xf] = NULL,
190
[pxa_lcdc_2bpp] = pxa2xx_draw_line2,
191
[pxa_lcdc_4bpp] = pxa2xx_draw_line4,
192
@@ -XXX,XX +XXX,XX @@ static drawfn pxa2xx_draw_fn_32[16] =
193
};
194
195
/* Overlay planes enabled, transparency used */
196
-static drawfn pxa2xx_draw_fn_32t[16] =
197
-{
198
+static drawfn pxa2xx_draw_fn_32t[16] = {
199
[0 ... 0xf] = NULL,
200
[pxa_lcdc_4bpp] = pxa2xx_draw_line4,
201
[pxa_lcdc_8bpp] = pxa2xx_draw_line8,
202
--
203
2.20.1
204
205
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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