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[PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions

Georg Kotheimer posted 1 patch 4 years, 11 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
[PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Posted by Georg Kotheimer 4 years, 11 months ago 
According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
---
 target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2f43939fb6..d0577b1e08 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -325,7 +325,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         use_background = true;
     }
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
@@ -695,19 +699,18 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+    /* MPRV does not affect the virtual-machine load/store
+       instructions, HLV, HLVX, and HSV. */
+    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+        mode = get_field(env->hstatus, HSTATUS_SPVP);
+    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+               get_field(env->mstatus, MSTATUS_MPRV)) {
+        mode = get_field(env->mstatus, MSTATUS_MPP);
+        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+            two_stage_lookup = true;
         }
     }
 
-    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
-        access_type != MMU_INST_FETCH &&
-        get_field(env->mstatus, MSTATUS_MPRV) &&
-        get_field(env->mstatus, MSTATUS_MPV)) {
-        two_stage_lookup = true;
-    }
-
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
-- 
2.30.1
Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Posted by Alistair Francis 4 years, 10 months ago 
On Thu, Mar 11, 2021 at 5:32 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> According to the specification the "field SPVP of hstatus controls the
> privilege level of the access" for the hypervisor virtual-machine load
> and store instructions HLV, HLVX and HSV.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 2f43939fb6..d0577b1e08 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -325,7 +325,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>          use_background = true;
>      }
>
> -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> +    /* MPRV does not affect the virtual-machine load/store
> +       instructions, HLV, HLVX, and HSV. */
> +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
> +        mode = get_field(env->hstatus, HSTATUS_SPVP);
> +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
>          if (get_field(env->mstatus, MSTATUS_MPRV)) {
>              mode = get_field(env->mstatus, MSTATUS_MPP);
>          }
> @@ -695,19 +699,18 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
>                    __func__, address, access_type, mmu_idx);
>
> -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> -        if (get_field(env->mstatus, MSTATUS_MPRV)) {
> -            mode = get_field(env->mstatus, MSTATUS_MPP);
> +    /* MPRV does not affect the virtual-machine load/store
> +       instructions, HLV, HLVX, and HSV. */
> +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
> +        mode = get_field(env->hstatus, HSTATUS_SPVP);
> +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
> +               get_field(env->mstatus, MSTATUS_MPRV)) {
> +        mode = get_field(env->mstatus, MSTATUS_MPP);
> +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
> +            two_stage_lookup = true;
>          }
>      }
>
> -    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
> -        access_type != MMU_INST_FETCH &&
> -        get_field(env->mstatus, MSTATUS_MPRV) &&
> -        get_field(env->mstatus, MSTATUS_MPV)) {
> -        two_stage_lookup = true;
> -    }
> -
>      if (riscv_cpu_virt_enabled(env) ||
>          ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
>           access_type != MMU_INST_FETCH)) {
> --
> 2.30.1
>
>
Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Posted by Alistair Francis 4 years, 10 months ago 
On Thu, Mar 11, 2021 at 5:32 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> According to the specification the "field SPVP of hstatus controls the
> privilege level of the access" for the hypervisor virtual-machine load
> and store instructions HLV, HLVX and HSV.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 2f43939fb6..d0577b1e08 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -325,7 +325,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>          use_background = true;
>      }
>
> -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> +    /* MPRV does not affect the virtual-machine load/store
> +       instructions, HLV, HLVX, and HSV. */
> +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
> +        mode = get_field(env->hstatus, HSTATUS_SPVP);
> +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
>          if (get_field(env->mstatus, MSTATUS_MPRV)) {
>              mode = get_field(env->mstatus, MSTATUS_MPP);
>          }
> @@ -695,19 +699,18 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
>                    __func__, address, access_type, mmu_idx);
>
> -    if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> -        if (get_field(env->mstatus, MSTATUS_MPRV)) {
> -            mode = get_field(env->mstatus, MSTATUS_MPP);
> +    /* MPRV does not affect the virtual-machine load/store
> +       instructions, HLV, HLVX, and HSV. */
> +    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
> +        mode = get_field(env->hstatus, HSTATUS_SPVP);
> +    } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
> +               get_field(env->mstatus, MSTATUS_MPRV)) {
> +        mode = get_field(env->mstatus, MSTATUS_MPP);
> +        if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
> +            two_stage_lookup = true;
>          }
>      }
>
> -    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
> -        access_type != MMU_INST_FETCH &&
> -        get_field(env->mstatus, MSTATUS_MPRV) &&
> -        get_field(env->mstatus, MSTATUS_MPV)) {
> -        two_stage_lookup = true;
> -    }
> -
>      if (riscv_cpu_virt_enabled(env) ||
>          ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
>           access_type != MMU_INST_FETCH)) {
> --
> 2.30.1
>
>

Patchew 2.1-devel-b67e4c2

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