Introduce the PINTEH opcode (Parallel Interleave Even Halfword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
Use trans_parallel_arith (rth)
---
 target/mips/tx79.decode      |  1 +
 target/mips/tx79_translate.c | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 653910371d2..fbd2be569ad 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -57,6 +57,7 @@ PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
 
 # MMI3
 
+PINTEH          011100 ..... ..... ..... 01010 101001   @rs_rt_rd
 PCPYUD          011100 ..... ..... ..... 01110 101001   @rs_rt_rd
 POR             011100 ..... ..... ..... 10010 101001   @rs_rt_rd
 PNOR            011100 ..... ..... ..... 10011 101001   @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 90c33d26a9f..7c7879face0 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -593,3 +593,25 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
 
     return true;
 }
+
+static void gen_vec_pinteh(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+    TCGv_i64 x, y, mask = tcg_constant_i64(0x0000ffff0000ffffull);
+
+    x = tcg_temp_new_i64();
+    y = tcg_temp_new_i64();
+
+    tcg_gen_shli_i64(x, a, 8);
+    tcg_gen_and_i64(x, x, mask);
+    tcg_gen_and_i64(y, b, mask);
+    tcg_gen_or_i64(d, x, y);
+
+    tcg_temp_free(y);
+    tcg_temp_free(x);
+}
+
+/* Parallel Interleave Even Halfword */
+static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_arith(ctx, a, gen_vec_pinteh);
+}
-- 
2.26.2

On 3/9/21 8:56 AM, Philippe Mathieu-Daudé wrote:
> +    tcg_gen_shli_i64(x, a, 8);
> +    tcg_gen_and_i64(x, x, mask);

I think these two lines need switching?

> +    tcg_gen_and_i64(y, b, mask);
> +    tcg_gen_or_i64(d, x, y);


r~