[RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing)

Philippe Mathieu-Daudé posted 22 patches 4 years, 8 months ago
Failed in applying to current master (apply log)
There is a newer version of this series
target/mips/translate.h      |   6 +
target/mips/tx79.decode      |  79 ++++
target/mips/translate.c      | 790 +---------------------------------
target/mips/tx79_translate.c | 808 +++++++++++++++++++++++++++++++++++
target/mips/txx9_translate.c |  20 +
target/mips/cpu-defs.c.inc   |  59 +++
target/mips/meson.build      |   5 +
7 files changed, 983 insertions(+), 784 deletions(-)
create mode 100644 target/mips/tx79.decode
create mode 100644 target/mips/tx79_translate.c
create mode 100644 target/mips/txx9_translate.c
[RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing)
Posted by Philippe Mathieu-Daudé 4 years, 8 months ago
First part (TCG, testing postponed) of RFC v1:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg782449.html

3 patches can still be improved for performance, but the improvement
is not yet addressed in this series. Other patches are good enough
for review.

https://gitlab.com/philmd/qemu/-/commits/mips-r5900-v2
Based-on: mips-next
Supersedes: <20210214175912.732946-1-f4bug@amsat.org>

Philippe Mathieu-Daudé (22):
  target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
  target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
  target/mips/translate: Make gen_rdhwr() public
  target/mips/translate: Simplify PCPYH using deposit_i64()
  target/mips/tx79: Move PCPYH opcode to decodetree
  target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
  target/mips: Remove 'C790 Multimedia Instructions' dead code
  target/mips/tx79: Salvage instructions description comment
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel
    logic)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword)
  target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()
  target/mips: Reintroduce the R5900 CPU

 target/mips/translate.h      |   6 +
 target/mips/tx79.decode      |  79 ++++
 target/mips/translate.c      | 790 +---------------------------------
 target/mips/tx79_translate.c | 808 +++++++++++++++++++++++++++++++++++
 target/mips/txx9_translate.c |  20 +
 target/mips/cpu-defs.c.inc   |  59 +++
 target/mips/meson.build      |   5 +
 7 files changed, 983 insertions(+), 784 deletions(-)
 create mode 100644 target/mips/tx79.decode
 create mode 100644 target/mips/tx79_translate.c
 create mode 100644 target/mips/txx9_translate.c

-- 
2.26.2

Re: [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing)
Posted by Philippe Mathieu-Daudé 4 years, 8 months ago
On 3/9/21 3:56 PM, Philippe Mathieu-Daudé wrote:
> First part (TCG, testing postponed) of RFC v1:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg782449.html
> 
> 3 patches can still be improved for performance, but the improvement
> is not yet addressed in this series. Other patches are good enough
> for review.
> 
> https://gitlab.com/philmd/qemu/-/commits/mips-r5900-v2
> Based-on: mips-next
> Supersedes: <20210214175912.732946-1-f4bug@amsat.org>
> 
> Philippe Mathieu-Daudé (22):
>   target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
>   target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
>   target/mips/translate: Make gen_rdhwr() public
>   target/mips/translate: Simplify PCPYH using deposit_i64()
>   target/mips/tx79: Move PCPYH opcode to decodetree
>   target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
>   target/mips: Remove 'C790 Multimedia Instructions' dead code
>   target/mips/tx79: Salvage instructions description comment

Patches 1-8 applied to mips-next.

Re: [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing)
Posted by Philippe Mathieu-Daudé 4 years, 4 months ago
On 3/9/21 3:56 PM, Philippe Mathieu-Daudé wrote:
> First part (TCG, testing postponed) of RFC v1:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg782449.html
> 
> 3 patches can still be improved for performance, but the improvement
> is not yet addressed in this series. Other patches are good enough
> for review.
> 
> https://gitlab.com/philmd/qemu/-/commits/mips-r5900-v2
> Based-on: mips-next
> Supersedes: <20210214175912.732946-1-f4bug@amsat.org>
> 
> Philippe Mathieu-Daudé (22):
>   target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
>   target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
>   target/mips/translate: Make gen_rdhwr() public
>   target/mips/translate: Simplify PCPYH using deposit_i64()
>   target/mips/tx79: Move PCPYH opcode to decodetree
>   target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
>   target/mips: Remove 'C790 Multimedia Instructions' dead code
>   target/mips/tx79: Salvage instructions description comment
>   target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel
>     logic)
>   target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
>   target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
>   target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
>   target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
>   target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
>   target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
>   target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword)
>   target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)
>   target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
>   target/mips/tx79: Introduce LQ opcode (Load Quadword)
>   target/mips/tx79: Introduce SQ opcode (Store Quadword)
>   target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()
>   target/mips: Reintroduce the R5900 CPU

Patches 9-15 & 18 applied to mips-next.