The following changes since commit 229a834518b950d56fd1bc94923276504d0ee9d4:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20210306' into staging (2021-03-08 15:45:48 +0000)

https://github.com/legoater/qemu/ tags/pull-aspeed-20210309

for you to fetch changes up to c59f781e3bcca4a80aef5d229488fd45dbfdbd9a:

hw/misc: Model KCS devices in the Aspeed LPC controller (2021-03-09 12:01:28 +0100)

Aspeed patches :

* New model for the Aspeed LPC controller

* Misc cleanups

Andrew Jeffery (4):

hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC

hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet

hw/arm: ast2600: Correct the iBT interrupt ID

hw/misc: Model KCS devices in the Aspeed LPC controller

Cédric Le Goater (2):

hw/arm/aspeed: Fix location of firmware images in documentation

hw/misc: Add a basic Aspeed LPC controller model

Joel Stanley (1):

arm/ast2600: Fix SMP booting with -kernel

From: Andrew Jeffery <andrew@aj.id.au>

The datasheet says we have 197 IRQs allocated, and we need more than 128

to describe IRQs from LPC devices. Raise the value now to allow

modelling of the LPC devices.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-Id: <20210302014317.915120-3-andrew@aj.id.au>

hw/arm/aspeed_ast2600.c | 2 +-

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c

--- a/hw/arm/aspeed_ast2600.c

+++ b/hw/arm/aspeed_ast2600.c

@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {

#define ASPEED_A7MPCORE_ADDR 0x40460000

-#define AST2600_MAX_IRQ 128

+#define AST2600_MAX_IRQ 197

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */

static const int aspeed_soc_ast2600_irqmap[] = {

2.26.2

From: Andrew Jeffery <andrew@aj.id.au>

This appears to be a requirement of the GIC model. The AST2600 allocates

197 GIC IRQs, which we will adjust shortly.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

hw/arm/aspeed_ast2600.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {

#define ASPEED_A7MPCORE_ADDR 0x40460000

-#define ASPEED_SOC_AST2600_MAX_IRQ 128

+#define AST2600_MAX_IRQ 128

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */

static const int aspeed_soc_ast2600_irqmap[] = {

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)

object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,

&error_abort);

object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",

- ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,

+ ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),

&error_abort);

sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);

2.26.2

From: Andrew Jeffery <andrew@aj.id.au>

Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC

IO cycles from the BMC to the host.

Expose support on the BMC side by implementing the usual MMIO

behaviours, and expose the ability to inspect the KCS registers in

"host" style by accessing QOM properties associated with each register.

The model caters to the IRQ style of both the AST2600 and the earlier

SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC

sub-device, while there is a single IRQ shared across all subdevices on

the AST2400 and AST2500.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

include/hw/arm/aspeed_soc.h | 1 +

include/hw/misc/aspeed_lpc.h | 17 +-

hw/arm/aspeed_ast2600.c | 28 ++-

hw/arm/aspeed_soc.c | 24 ++-

hw/misc/aspeed_lpc.c | 359 ++++++++++++++++++++++++++++++++++-

5 files changed, 424 insertions(+), 5 deletions(-)

@@ -XXX,XX +XXX,XX @@ enum {

ASPEED_DEV_SDRAM,

ASPEED_DEV_XDMA,

ASPEED_DEV_EMMC,

+ ASPEED_DEV_KCS,

};

#endif /* ASPEED_SOC_H */

diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/misc/aspeed_lpc.h

+++ b/include/hw/misc/aspeed_lpc.h

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

+#include <stdint.h>

+

#define TYPE_ASPEED_LPC "aspeed.lpc"

#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)

-#define ASPEED_LPC_NR_REGS (0x260 >> 2)

+#define ASPEED_LPC_NR_REGS (0x260 >> 2)

+

+enum aspeed_lpc_subdevice {

+ aspeed_lpc_kcs_1 = 0,

+ aspeed_lpc_kcs_2,

+ aspeed_lpc_kcs_3,

+ aspeed_lpc_kcs_4,

+ aspeed_lpc_ibt,

+#define ASPEED_LPC_NR_SUBDEVS 5

typedef struct AspeedLPCState {

/* <private> */

@@ -XXX,XX +XXX,XX @@ typedef struct AspeedLPCState {

MemoryRegion iomem;

qemu_irq irq;

+ qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS];

+ uint32_t subdevice_irqs_pending;

uint32_t regs[ASPEED_LPC_NR_REGS];

uint32_t hicr7;

} AspeedLPCState;

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast2600.c

+++ b/hw/arm/aspeed_ast2600.c

@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {

[ASPEED_DEV_ETH2] = 3,

[ASPEED_DEV_ETH3] = 32,

[ASPEED_DEV_ETH4] = 33,

-

+ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */

@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {

[ASPEED_DEV_WDT] = 27,

[ASPEED_DEV_PWM] = 28,

[ASPEED_DEV_LPC] = 8,

- [ASPEED_DEV_IBT] = 8, /* LPC */

[ASPEED_DEV_I2C] = 12,

[ASPEED_DEV_ETH1] = 2,

[ASPEED_DEV_ETH2] = 3,

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)

return;

}

sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);

+ /* Connect the LPC IRQ to the VIC */

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,

aspeed_soc_get_irq(s, ASPEED_DEV_LPC));

+

+ /*

+ * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the

+ * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by

+ * contrast, on the AST2600, the subdevice IRQs are connected straight to

+ * the GIC).

+ *

+ * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output

+ * to the VIC is at offset 0.

+ */

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,

+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));

+

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,

+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));

+

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,

+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));

+

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,

+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));

}

static Property aspeed_soc_properties[] = {

DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,

diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_lpc.c

+++ b/hw/misc/aspeed_lpc.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/error-report.h"

#include "hw/misc/aspeed_lpc.h"

#include "qapi/error.h"

+#include "qapi/visitor.h"

+#include "hw/irq.h"

#include "hw/qdev-properties.h"

#include "migration/vmstate.h"

#define TO_REG(offset) ((offset) >> 2)

#define HICR0 TO_REG(0x00)

+#define HICR0_LPC3E BIT(7)

+#define HICR0_LPC2E BIT(6)

+#define HICR0_LPC1E BIT(5)

#define HICR1 TO_REG(0x04)

#define HICR2 TO_REG(0x08)

+#define HICR2_IBFIE3 BIT(3)

+#define HICR2_IBFIE2 BIT(2)

+#define HICR2_IBFIE1 BIT(1)

#define HICR3 TO_REG(0x0C)

#define HICR4 TO_REG(0x10)

+#define HICR4_KCSENBL BIT(2)

+#define IDR1 TO_REG(0x24)

+#define IDR2 TO_REG(0x28)

+#define IDR3 TO_REG(0x2C)

+#define ODR1 TO_REG(0x30)

+#define ODR2 TO_REG(0x34)

+#define ODR3 TO_REG(0x38)

+#define STR1 TO_REG(0x3C)

+#define STR_OBF BIT(0)

+#define STR_IBF BIT(1)

+#define STR_CMD_DATA BIT(3)

+#define STR2 TO_REG(0x40)

+#define STR3 TO_REG(0x44)

#define HICR5 TO_REG(0x80)

#define HICR6 TO_REG(0x84)

#define HICR7 TO_REG(0x88)

#define HICR8 TO_REG(0x8C)

+#define HICRB TO_REG(0x100)

+#define HICRB_IBFIE4 BIT(1)

+#define HICRB_LPC4E BIT(0)

+#define IDR4 TO_REG(0x114)

+#define ODR4 TO_REG(0x118)

+#define STR4 TO_REG(0x11C)

+

+enum aspeed_kcs_channel_id {

+ kcs_channel_1 = 0,

+ kcs_channel_2,

+ kcs_channel_3,

+ kcs_channel_4,

+static const enum aspeed_lpc_subdevice aspeed_kcs_subdevice_map[] = {

+ [kcs_channel_1] = aspeed_lpc_kcs_1,

+ [kcs_channel_2] = aspeed_lpc_kcs_2,

+ [kcs_channel_3] = aspeed_lpc_kcs_3,

+ [kcs_channel_4] = aspeed_lpc_kcs_4,

+};

+struct aspeed_kcs_channel {

+ enum aspeed_kcs_channel_id id;

+ int idr;

+ int odr;

+ int str;

+};

+

+static const struct aspeed_kcs_channel aspeed_kcs_channel_map[] = {

+ [kcs_channel_1] = {

+ .id = kcs_channel_1,

+ .idr = IDR1,

+ .odr = ODR1,