The following changes since commit 91e92cad67caca3bc4b8e920ddb5c8ca64aac9e1:

Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' into staging (2021-03-05 19:04:47 +0000)

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210306

for you to fetch changes up to 6cc9d67c6f682cf04eea2d6e64a252b63a7eccdf:

accel/tcg: Precompute curr_cflags into cpu->tcg_cflags (2021-03-06 11:53:57 -0800)

TCI build fix and cleanup

Streamline tb_lookup

Fixes for tcg/aarch64

Alex Bennée (4):

accel/tcg: rename tb_lookup__cpu_state and hoist state extraction

accel/tcg: move CF_CLUSTER calculation to curr_cflags

accel/tcg: drop the use of CF_HASH_MASK and rename params

include/exec: lightly re-arrange TranslationBlock

Richard Henderson (23):

tcg/aarch64: Fix constant subtraction in tcg_out_addsub2

tcg/aarch64: Fix I3617_CMLE0

tcg/aarch64: Fix generation of "scalar" vector operations

tcg/tci: Use exec/cpu_ldst.h interfaces

tcg: Split out tcg_raise_tb_overflow

tcg: Manage splitwx in tc_ptr_to_region_tree by hand

tcg/tci: Merge identical cases in generation (arithmetic opcodes)

tcg/tci: Merge identical cases in generation (exchange opcodes)

tcg/tci: Merge identical cases in generation (deposit opcode)

tcg/tci: Merge identical cases in generation (conditional opcodes)

tcg/tci: Merge identical cases in generation (load/store opcodes)

tcg/tci: Remove tci_read_r8

tcg/tci: Remove tci_read_r8s

tcg/tci: Remove tci_read_r16

tcg/tci: Remove tci_read_r16s

tcg/tci: Remove tci_read_r32

tcg/tci: Remove tci_read_r32s

tcg/tci: Reduce use of tci_read_r64

tcg/tci: Merge basic arithmetic operations

tcg/tci: Merge extension operations

tcg/tci: Merge bswap operations

tcg/tci: Merge mov, not and neg operations

accel/tcg: Precompute curr_cflags into cpu->tcg_cflags

accel/tcg/tcg-accel-ops.h | 1 +

include/exec/exec-all.h | 22 +-

include/exec/tb-lookup.h | 26 +-

include/hw/core/cpu.h | 2 +

accel/tcg/cpu-exec.c | 34 +--

accel/tcg/tcg-accel-ops-mttcg.c | 3 +-

accel/tcg/tcg-accel-ops-rr.c | 2 +-

accel/tcg/tcg-accel-ops.c | 8 +

accel/tcg/tcg-runtime.c | 6 +-

accel/tcg/translate-all.c | 18 +-

linux-user/main.c | 1 +

linux-user/sh4/signal.c | 8 +-

linux-user/syscall.c | 18 +-

softmmu/physmem.c | 2 +-

tcg/tcg.c | 29 ++-

tcg/tci.c | 526 ++++++++++++----------------------------

tcg/aarch64/tcg-target.c.inc | 229 ++++++++++++++---

tcg/tci/tcg-target.c.inc | 204 ++++++----------

18 files changed, 529 insertions(+), 610 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

Lets make sure all the flags we compare when looking up blocks are

together in the same place.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org>

include/exec/exec-all.h | 11 ++++++++---

1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h

--- a/include/exec/exec-all.h

+++ b/include/exec/exec-all.h

@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {

target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */

target_ulong cs_base; /* CS base for this block */

uint32_t flags; /* flags defining in which context the code was generated */

- uint16_t size; /* size of target code for this block (1 <=

- size <= TARGET_PAGE_SIZE) */

- uint16_t icount;

uint32_t cflags; /* compile flags */

#define CF_COUNT_MASK 0x00007fff

#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */

@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {

/* Per-vCPU dynamic tracing state used to generate this TB */

uint32_t trace_vcpu_dstate;

+ /*

+ * Above fields used for comparing

+ */

+

+ /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */

+ uint16_t size;

+ uint16_t icount;

+

struct tb_tc tc;

/* first and second physical page containing code. The lower bit

2.25.1

From: Alex Bennée <alex.bennee@linaro.org>

We don't really deal in cf_mask most of the time. The one time it's

relevant is when we want to remove an invalidated TB from the QHT

lookup. Everywhere else we should be looking up things without

CF_INVALID set.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org>

include/exec/exec-all.h | 4 +---

include/exec/tb-lookup.h | 9 ++++++---

accel/tcg/cpu-exec.c | 16 ++++++++--------

accel/tcg/tcg-runtime.c | 2 +-

accel/tcg/translate-all.c | 8 +++++---

5 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h

--- a/include/exec/exec-all.h

+++ b/include/exec/exec-all.h

@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {

#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */

#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */

#define CF_CLUSTER_SHIFT 24

-/* cflags' mask for hashing/comparison, basically ignore CF_INVALID */

-#define CF_HASH_MASK (~CF_INVALID)

/* Per-vCPU dynamic tracing state used to generate this TB */

uint32_t trace_vcpu_dstate;

@@ -XXX,XX +XXX,XX @@ void tb_flush(CPUState *cpu);

void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);

TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,

target_ulong cs_base, uint32_t flags,

- uint32_t cf_mask);

+ uint32_t cflags);

void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);

/* GETPC is the true target of the return instruction that we'll execute. */

diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h

index XXXXXXX..XXXXXXX 100644

--- a/include/exec/tb-lookup.h

+++ b/include/exec/tb-lookup.h

@@ -XXX,XX +XXX,XX @@

/* Might cause an exception, so have a longjmp destination ready */

static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,

target_ulong cs_base,

- uint32_t flags, uint32_t cf_mask)

+ uint32_t flags, uint32_t cflags)

{

TranslationBlock *tb;

uint32_t hash;

+ /* we should never be trying to look up an INVALID tb */

+ tcg_debug_assert(!(cflags & CF_INVALID));

+

hash = tb_jmp_cache_hash_func(pc);

tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);

@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,

tb->cs_base == cs_base &&

tb->flags == flags &&

tb->trace_vcpu_dstate == *cpu->trace_dstate &&

- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {

+ tb_cflags(tb) == cflags)) {

return tb;

}

- tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);

+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);

if (tb == NULL) {

return NULL;

}

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ struct tb_desc {

CPUArchState *env;

tb_page_addr_t phys_page1;

uint32_t flags;

- uint32_t cf_mask;

+ uint32_t cflags;

uint32_t trace_vcpu_dstate;

};

@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)

tb->cs_base == desc->cs_base &&

tb->flags == desc->flags &&

tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&

- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {

+ tb_cflags(tb) == desc->cflags) {

/* check next page if needed */

if (tb->page_addr[1] == -1) {

return true;

@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)

TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,

target_ulong cs_base, uint32_t flags,

- uint32_t cf_mask)

+ uint32_t cflags)

{

tb_page_addr_t phys_pc;

struct tb_desc desc;

@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,

desc.env = (CPUArchState *)cpu->env_ptr;

desc.cs_base = cs_base;

desc.flags = flags;

- desc.cf_mask = cf_mask;

+ desc.cflags = cflags;

desc.trace_vcpu_dstate = *cpu->trace_dstate;

desc.pc = pc;

phys_pc = get_page_addr_code(desc.env, pc);

@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,

return NULL;

}

desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;

- h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);

+ h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);

return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);

}

@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,

static inline TranslationBlock *tb_find(CPUState *cpu,

TranslationBlock *last_tb,

- int tb_exit, uint32_t cf_mask)

+ int tb_exit, uint32_t cflags)

{

CPUArchState *env = (CPUArchState *)cpu->env_ptr;

TranslationBlock *tb;

@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,

cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);

- tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);

+ tb = tb_lookup(cpu, pc, cs_base, flags, cflags);

if (tb == NULL) {

mmap_lock();

- tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);

+ tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);

mmap_unlock();

/* We add the TB in the virtual pc hash table for the fast lookup */

qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);

diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/tcg-runtime.c

+++ b/accel/tcg/tcg-runtime.c

@@ -XXX,XX +XXX,XX @@

#include "exec/helper-proto.h"

#include "exec/cpu_ldst.h"

#include "exec/exec-all.h"

-#include "exec/tb-lookup.h"

#include "disas/disas.h"

#include "exec/log.h"

#include "tcg/tcg.h"

+#include "exec/tb-lookup.h"

/* 32-bit helpers */

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/translate-all.c

+++ b/accel/tcg/translate-all.c

@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)

return a->pc == b->pc &&

a->cs_base == b->cs_base &&

a->flags == b->flags &&

- (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) &&

+ (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&

a->trace_vcpu_dstate == b->trace_vcpu_dstate &&

a->page_addr[0] == b->page_addr[0] &&

a->page_addr[1] == b->page_addr[1];

@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)

PageDesc *p;

uint32_t h;

tb_page_addr_t phys_pc;

+ uint32_t orig_cflags = tb_cflags(tb);

assert_memory_lock();

@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)

/* remove the TB from the hash list */

phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);

- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK,

+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,

tb->trace_vcpu_dstate);

if (!qht_remove(&tb_ctx.htable, tb, h)) {

return;

@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,

uint32_t h;

assert_memory_lock();

+ tcg_debug_assert(!(tb->cflags & CF_INVALID));

/*

* Add the TB to the page list, acquiring first the pages's locks.

@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,

}

/* add in the hash table */

- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,

+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,

tb->trace_vcpu_dstate);

qht_insert(&tb_ctx.htable, tb, h, &existing_tb);

2.25.1

An hppa guest executing

0x000000000000e05c: ldil L%10000,r4

0x000000000000e060: ldo 0(r4),r4

0x000000000000e064: sub r3,r4,sp

produces

---- 000000000000e064 000000000000e068

sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0

after folding and constant propagation. Then we hit

tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed.

because aimm is in fact -16, but unsigned.

The ((bl < 0) ^ sub) condition which negates bl is incorrect and will

always lead to this abort. If the constant is positive, sub will make

it negative; if the constant is negative, sub will keep it negative.

tcg/aarch64/tcg-target.c.inc | 16 +++++++++-------

1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc

--- a/tcg/aarch64/tcg-target.c.inc

+++ b/tcg/aarch64/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,

-static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,

- TCGReg rh, TCGReg al, TCGReg ah,

- tcg_target_long bl, tcg_target_long bh,

- bool const_bl, bool const_bh, bool sub)

+static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,

+ TCGReg rh, TCGReg al, TCGReg ah,

+ tcg_target_long bl, tcg_target_long bh,

+ bool const_bl, bool const_bh, bool sub)

TCGReg orig_rl = rl;

AArch64Insn insn;

@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,

if (const_bl) {

- insn = I3401_ADDSI;

- if ((bl < 0) ^ sub) {

- insn = I3401_SUBSI;

+ if (bl < 0) {

bl = -bl;

+ insn = sub ? I3401_ADDSI : I3401_SUBSI;

+ } else {

+ insn = sub ? I3401_SUBSI : I3401_ADDSI;

+

if (unlikely(al == TCG_REG_XZR)) {

/* ??? We want to allow al to be zero for the benefit of

negation via subtraction. However, that leaves open the

2.25.1

The primary motivation is to remove a dozen insns along

the fast-path in tb_lookup. As a byproduct, this allows

us to completely remove parallel_cpus.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

accel/tcg/tcg-accel-ops.h | 1 +

include/exec/exec-all.h | 7 +------

include/hw/core/cpu.h | 2 ++

accel/tcg/cpu-exec.c | 3 ---

accel/tcg/tcg-accel-ops-mttcg.c | 3 +--

accel/tcg/tcg-accel-ops-rr.c | 2 +-

accel/tcg/tcg-accel-ops.c | 8 ++++++++

accel/tcg/translate-all.c | 4 ----

linux-user/main.c | 1 +

linux-user/sh4/signal.c | 8 +++++---

linux-user/syscall.c | 18 ++++++++++--------

11 files changed, 30 insertions(+), 27 deletions(-)

diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h

--- a/accel/tcg/tcg-accel-ops.h

+++ b/accel/tcg/tcg-accel-ops.h

@@ -XXX,XX +XXX,XX @@

void tcg_cpus_destroy(CPUState *cpu);

int tcg_cpus_exec(CPUState *cpu);

void tcg_handle_interrupt(CPUState *cpu, int mask);

+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);

#endif /* TCG_CPUS_H */

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h

index XXXXXXX..XXXXXXX 100644

--- a/include/exec/exec-all.h

+++ b/include/exec/exec-all.h

@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {

uintptr_t jmp_dest[2];

};

-extern bool parallel_cpus;

-

/* Hide the qatomic_read to make code a little easier on the eyes */

static inline uint32_t tb_cflags(const TranslationBlock *tb)

{

@@ -XXX,XX +XXX,XX @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)

/* current cflags for hashing/comparison */

static inline uint32_t curr_cflags(CPUState *cpu)

{

- uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index);

- cflags |= parallel_cpus ? CF_PARALLEL : 0;

- cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;

- return cflags;

+ return cpu->tcg_cflags;

}

/* TranslationBlock invalidate API */

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/core/cpu.h

+++ b/include/hw/core/cpu.h

@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;

* to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will

* be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER

* QOM parent.

+ * @tcg_cflags: Pre-computed cflags for this cpu.

* @nr_cores: Number of cores within this CPU package.

* @nr_threads: Number of threads within this CPU.

* @running: #true if CPU is currently running (lockless).

@@ -XXX,XX +XXX,XX @@ struct CPUState {

/* TODO Move common fields from CPUArchState here. */

int cpu_index;

int cluster_index;

+ uint32_t tcg_cflags;

uint32_t halted;

uint32_t can_do_io;

int32_t exception_index;

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)

mmap_unlock();

}

- /* Since we got here, we know that parallel_cpus must be true. */

- parallel_cpus = false;

cpu_exec_enter(cpu);

/* execute the generated code */

trace_exec_tb(tb, pc);

@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)

* the execution.

*/

g_assert(cpu_in_exclusive_context(cpu));

- parallel_cpus = true;

cpu->running = false;

end_exclusive();

}

diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/tcg-accel-ops-mttcg.c

+++ b/accel/tcg/tcg-accel-ops-mttcg.c

@@ -XXX,XX +XXX,XX @@ void mttcg_start_vcpu_thread(CPUState *cpu)

char thread_name[VCPU_THREAD_NAME_SIZE];

g_assert(tcg_enabled());

-

- parallel_cpus = (current_machine->smp.max_cpus > 1);

+ tcg_cpu_init_cflags(cpu, current_machine->smp.max_cpus > 1);

cpu->thread = g_malloc0(sizeof(QemuThread));

cpu->halt_cond = g_malloc0(sizeof(QemuCond));

diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/tcg-accel-ops-rr.c

+++ b/accel/tcg/tcg-accel-ops-rr.c

@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)

static QemuThread *single_tcg_cpu_thread;

g_assert(tcg_enabled());

- parallel_cpus = false;

+ tcg_cpu_init_cflags(cpu, false);

if (!single_tcg_cpu_thread) {

cpu->thread = g_malloc0(sizeof(QemuThread));

diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/tcg-accel-ops.c

+++ b/accel/tcg/tcg-accel-ops.c

@@ -XXX,XX +XXX,XX @@

/* common functionality among all TCG variants */

+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)

+{

+ uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;

+ cflags |= parallel ? CF_PARALLEL : 0;

+ cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;

+ cpu->tcg_cflags = cflags;

+}

+

void tcg_cpus_destroy(CPUState *cpu)

{

cpu_thread_signal_destroyed(cpu);

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/translate-all.c

+++ b/accel/tcg/translate-all.c

@@ -XXX,XX +XXX,XX @@ static void *l1_map[V_L1_MAX_SIZE];

TCGContext tcg_init_ctx;

__thread TCGContext *tcg_ctx;

TBContext tb_ctx;

-bool parallel_cpus;

static void page_table_config_init(void)

{

@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,

cflags = (cflags & ~CF_COUNT_MASK) | 1;

- cflags &= ~CF_CLUSTER_MASK;

- cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;

-

max_insns = cflags & CF_COUNT_MASK;

if (max_insns == 0) {

max_insns = CF_COUNT_MASK;

diff --git a/linux-user/main.c b/linux-user/main.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/main.c

+++ b/linux-user/main.c

@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env)

/* Reset non arch specific state */

cpu_reset(new_cpu);

+ new_cpu->tcg_cflags = cpu->tcg_cflags;

memcpy(new_env, env, sizeof(CPUArchState));

/* Clone all break/watchpoints.

diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/sh4/signal.c

+++ b/linux-user/sh4/signal.c

@@ -XXX,XX +XXX,XX @@ static abi_ulong get_sigframe(struct target_sigaction *ka,

return (sp - frame_size) & -8ul;

}

-/* Notice when we're in the middle of a gUSA region and reset.

- Note that this will only occur for !parallel_cpus, as we will

- translate such sequences differently in a parallel context. */

+/*

+ * Notice when we're in the middle of a gUSA region and reset.

+ * Note that this will only occur when #CF_PARALLEL is unset, as we

+ * will translate such sequences differently in a parallel context.

+ */

static void unwind_gusa(CPUSH4State *regs)

{

/* If the stack pointer is sufficiently negative, and we haven't

diff --git a/linux-user/syscall.c b/linux-user/syscall.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/syscall.c

+++ b/linux-user/syscall.c

@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,

/* Grab a mutex so that thread setup appears atomic. */

pthread_mutex_lock(&clone_lock);

+ /*

+ * If this is our first additional thread, we need to ensure we

+ * generate code for parallel execution and flush old translations.

+ * Do this now so that the copy gets CF_PARALLEL too.

+ */

+ if (!(cpu->tcg_cflags & CF_PARALLEL)) {

+ cpu->tcg_cflags |= CF_PARALLEL;

+ tb_flush(cpu);

+ }

+

/* we create a new CPU instance. */

new_env = cpu_copy(env);

/* Init regs that differ from the parent. */

@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,

sigprocmask(SIG_BLOCK, &sigmask, &info.sigmask);

cpu->random_seed = qemu_guest_random_seed_thread_part1();

- /* If this is our first additional thread, we need to ensure we

- * generate code for parallel execution and flush old translations.

- */

- if (!parallel_cpus) {

- parallel_cpus = true;

- tb_flush(cpu);

- }

-

ret = pthread_create(&info.thread, &attr, clone_func, &info);

/* TODO: Free new CPU state if thread creation failed. */

2.25.1

From: Alex Bennée <alex.bennee@linaro.org>

There is nothing special about this compile flag that doesn't mean we

can't just compute it with curr_cflags() which we should be using when

building a new set.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org>

include/exec/exec-all.h | 8 +++++---

include/exec/tb-lookup.h | 3 ---

accel/tcg/cpu-exec.c | 9 ++++-----

accel/tcg/tcg-runtime.c | 2 +-

accel/tcg/translate-all.c | 6 +++---

softmmu/physmem.c | 2 +-

6 files changed, 14 insertions(+), 16 deletions(-)

- cpu->cflags_next_tb = (curr_cflags() & ~CF_USE_ICOUNT) | 1;

+ cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | 1;

@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)

have CF_INVALID set, -1 is a convenient invalid value that

does not require tcg headers for cpu_common_reset. */

if (cflags == -1) {

- cflags = curr_cflags();

+ cflags = curr_cflags(cpu);

} else {

cpu->cflags_next_tb = -1;

}

diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c

--- a/accel/tcg/tcg-runtime.c

+++ b/accel/tcg/tcg-runtime.c

@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)

cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);

- tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags());

+ tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu));

if (tb == NULL) {

return tcg_code_gen_epilogue;

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/translate-all.c

+++ b/accel/tcg/translate-all.c

- cpu->cflags_next_tb = 1 | curr_cflags();

+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);

cpu_loop_exit_noexc(cpu);

2.25.1

For some vector operations, "1D" is not a valid type, and there

are separate instructions for the 64-bit scalar operation.

Tested-by: Stefan Weil <sw@weilnetz.de>

Buglink: https://bugs.launchpad.net/qemu/+bug/1916112

Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")

tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++-----

1 file changed, 181 insertions(+), 30 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc

--- a/tcg/aarch64/tcg-target.c.inc

+++ b/tcg/aarch64/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ typedef enum {

I3606_BIC = 0x2f001400,

I3606_ORR = 0x0f001400,

+ /* AdvSIMD scalar shift by immediate */

+ I3609_SSHR = 0x5f000400,

+ I3609_SSRA = 0x5f001400,

+ I3609_SHL = 0x5f005400,

+ I3609_USHR = 0x7f000400,

+ I3609_USRA = 0x7f001400,

+ I3609_SLI = 0x7f005400,

+ /* AdvSIMD scalar three same */

+ I3611_SQADD = 0x5e200c00,

+ I3611_SQSUB = 0x5e202c00,

+ I3611_CMGT = 0x5e203400,

+ I3611_CMGE = 0x5e203c00,

+ I3611_SSHL = 0x5e204400,

+ I3611_ADD = 0x5e208400,

+ I3611_CMTST = 0x5e208c00,

+ I3611_UQADD = 0x7e200c00,

+ I3611_UQSUB = 0x7e202c00,

+ I3611_CMHI = 0x7e203400,

+ I3611_CMHS = 0x7e203c00,

+ I3611_USHL = 0x7e204400,

+ I3611_SUB = 0x7e208400,

+ I3611_CMEQ = 0x7e208c00,

+

+ /* AdvSIMD scalar two-reg misc */

+ I3612_CMGT0 = 0x5e208800,

+ I3612_CMEQ0 = 0x5e209800,

+ I3612_CMLT0 = 0x5e20a800,

+ I3612_ABS = 0x5e20b800,

+ I3612_CMGE0 = 0x7e208800,

+ I3612_CMLE0 = 0x7e209800,

+ I3612_NEG = 0x7e20b800,

+

/* AdvSIMD shift by immediate */

I3614_SSHR = 0x0f000400,

I3614_SSRA = 0x0f001400,

@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,

| (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);

+static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn,

+ TCGReg rd, TCGReg rn, unsigned immhb)

+{

+ tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));

+}

+

+static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn,

+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)

+{

+ tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16

+ | (rn & 0x1f) << 5 | (rd & 0x1f));

+}

+

+static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn,

+ unsigned size, TCGReg rd, TCGReg rn)

+{

+ tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));

+}

+

static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,

TCGReg rd, TCGReg rn, unsigned immhb)

{

@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

unsigned vecl, unsigned vece,

const TCGArg *args, const int *const_args)

{

- static const AArch64Insn cmp_insn[16] = {

+ static const AArch64Insn cmp_vec_insn[16] = {

[TCG_COND_EQ] = I3616_CMEQ,

[TCG_COND_GT] = I3616_CMGT,

[TCG_COND_GE] = I3616_CMGE,

[TCG_COND_GTU] = I3616_CMHI,

[TCG_COND_GEU] = I3616_CMHS,

};

- static const AArch64Insn cmp0_insn[16] = {

+ static const AArch64Insn cmp_scalar_insn[16] = {

+ [TCG_COND_EQ] = I3611_CMEQ,

+ [TCG_COND_GT] = I3611_CMGT,

+ [TCG_COND_GE] = I3611_CMGE,

+ [TCG_COND_GTU] = I3611_CMHI,

+ [TCG_COND_GEU] = I3611_CMHS,

+ };

+ static const AArch64Insn cmp0_vec_insn[16] = {

[TCG_COND_EQ] = I3617_CMEQ0,

[TCG_COND_GT] = I3617_CMGT0,

[TCG_COND_GE] = I3617_CMGE0,

[TCG_COND_LT] = I3617_CMLT0,

[TCG_COND_LE] = I3617_CMLE0,

};

+ static const AArch64Insn cmp0_scalar_insn[16] = {

+ [TCG_COND_EQ] = I3612_CMEQ0,

+ [TCG_COND_GT] = I3612_CMGT0,

+ [TCG_COND_GE] = I3612_CMGE0,

+ [TCG_COND_LT] = I3612_CMLT0,

+ [TCG_COND_LE] = I3612_CMLE0,

+ };

TCGType type = vecl + TCG_TYPE_V64;

unsigned is_q = vecl;

+ bool is_scalar = !is_q && vece == MO_64;

TCGArg a0, a1, a2, a3;

int cmode, imm8;

@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

tcg_out_dupm_vec(s, type, vece, a0, a1, a2);

break;

case INDEX_op_add_vec:

- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_sub_vec:

- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_mul_vec:

tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);

break;

case INDEX_op_neg_vec:

- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);

+ if (is_scalar) {

+ tcg_out_insn(s, 3612, NEG, vece, a0, a1);

+ } else {

+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);

+ }

break;

case INDEX_op_abs_vec:

- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);

+ if (is_scalar) {

+ tcg_out_insn(s, 3612, ABS, vece, a0, a1);

+ } else {

+ tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);

+ }

break;

case INDEX_op_and_vec:

if (const_args[2]) {

@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);

break;

case INDEX_op_ssadd_vec:

- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_sssub_vec:

- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_usadd_vec:

- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_ussub_vec:

- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_smax_vec:

tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);

@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);

break;

case INDEX_op_shli_vec:

- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));

+ if (is_scalar) {

+ tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece));

+ } else {

+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));

+ }

break;

case INDEX_op_shri_vec:

- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2);

+ } else {

+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);

+ }

break;

case INDEX_op_sari_vec:

- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2);

+ } else {

+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);

+ }

break;

case INDEX_op_aa64_sli_vec:

- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));

+ if (is_scalar) {

+ tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece));

+ } else {

+ tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));

+ }

break;

case INDEX_op_shlv_vec:

- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_aa64_sshl_vec:

- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);

+ }

break;

case INDEX_op_cmp_vec:

{

@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

if (cond == TCG_COND_NE) {

if (const_args[2]) {

- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);

+ } else {

+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);

+ }

} else {

- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);

+ if (is_scalar) {

+ tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2);

+ } else {

+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);

+ }

tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);

}

} else {

if (const_args[2]) {

- insn = cmp0_insn[cond];

- if (insn) {

- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);

- break;

+ if (is_scalar) {

+ insn = cmp0_scalar_insn[cond];

+ if (insn) {

+ tcg_out_insn_3612(s, insn, vece, a0, a1);

+ break;

+ }

+ } else {

+ insn = cmp0_vec_insn[cond];

+ if (insn) {

+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);

+ break;

+ }

}

tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);

a2 = TCG_VEC_TMP;

}

- insn = cmp_insn[cond];

- if (insn == 0) {

- TCGArg t;

- t = a1, a1 = a2, a2 = t;

- cond = tcg_swap_cond(cond);

- insn = cmp_insn[cond];

- tcg_debug_assert(insn != 0);

+ if (is_scalar) {

+ insn = cmp_scalar_insn[cond];

+ if (insn == 0) {

+ TCGArg t;

+ t = a1, a1 = a2, a2 = t;

+ cond = tcg_swap_cond(cond);

+ insn = cmp_scalar_insn[cond];

+ tcg_debug_assert(insn != 0);

+ }

+ tcg_out_insn_3611(s, insn, vece, a0, a1, a2);

+ } else {

+ insn = cmp_vec_insn[cond];

+ if (insn == 0) {

+ TCGArg t;

+ t = a1, a1 = a2, a2 = t;

+ cond = tcg_swap_cond(cond);

+ insn = cmp_vec_insn[cond];

+ tcg_debug_assert(insn != 0);

+ }

+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);

}

- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);

}

}

break;

2.25.1